diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v
index 85289990..a58847f3 100644
--- a/rtl/VX_back_end.v
+++ b/rtl/VX_back_end.v
@@ -106,6 +106,8 @@ VX_csr_wrapper VX_csr_wrapper(
 	);
 
 VX_writeback VX_wb(
+	.clk               (clk),
+	.reset             (reset),
 	.VX_mem_wb         (VX_mem_wb),
 	.VX_inst_exec_wb   (VX_inst_exec_wb),
 	.VX_csr_wb         (VX_csr_wb),
diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v
index 9d10ad4d..f67f5be9 100644
--- a/rtl/VX_writeback.v
+++ b/rtl/VX_writeback.v
@@ -3,6 +3,8 @@
 
 
 module VX_writeback (
+		input wire clk,
+		input wire reset,
 		// Mem WB info
 		VX_inst_mem_wb_inter     VX_mem_wb,
 		// EXEC Unit WB info
@@ -16,6 +18,7 @@ module VX_writeback (
 	);
 
 
+		VX_wb_inter              VX_writeback_tempp();
 
 		wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
 		wire mem_wb  = (VX_mem_wb.wb       != 0) && (|VX_mem_wb.wb_valid);
@@ -24,37 +27,50 @@ module VX_writeback (
 
 		assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
 
-		assign VX_writeback_inter.write_data  = exec_wb ? VX_inst_exec_wb.alu_result :
+		assign VX_writeback_tempp.write_data  = exec_wb ? VX_inst_exec_wb.alu_result :
 		                                        csr_wb  ? VX_csr_wb.csr_result       :
 		                                        mem_wb  ? VX_mem_wb.loaded_data      :
 		                                        0;
 
 
-		assign VX_writeback_inter.wb_valid    = exec_wb ? VX_inst_exec_wb.wb_valid :
+		assign VX_writeback_tempp.wb_valid    = exec_wb ? VX_inst_exec_wb.wb_valid :
 		                                        csr_wb  ? VX_csr_wb.valid          :
 		                                        mem_wb  ? VX_mem_wb.wb_valid       :
 		                                        0;    
 
-		assign VX_writeback_inter.rd          = exec_wb ? VX_inst_exec_wb.rd :
+		assign VX_writeback_tempp.rd          = exec_wb ? VX_inst_exec_wb.rd :
 		                                        csr_wb  ? VX_csr_wb.rd       :
 		                                        mem_wb  ? VX_mem_wb.rd       :
 		                                        0;
 
-		assign VX_writeback_inter.wb          = exec_wb ? VX_inst_exec_wb.wb :
+		assign VX_writeback_tempp.wb          = exec_wb ? VX_inst_exec_wb.wb :
 		                                        csr_wb  ? VX_csr_wb.wb       :
 		                                        mem_wb  ? VX_mem_wb.wb       :
 		                                        0;   
 
-		assign VX_writeback_inter.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num :
+		assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num :
 		                                        csr_wb  ? VX_csr_wb.warp_num          :
 		                                        mem_wb  ? VX_mem_wb.wb_warp_num       :
 		                                        0;    		
 
 
 
-		assign VX_writeback_inter.wb_pc       = exec_wb ? VX_inst_exec_wb.exec_wb_pc  :
+		assign VX_writeback_tempp.wb_pc       = exec_wb ? VX_inst_exec_wb.exec_wb_pc  :
 												csr_wb  ? 32'hdeadbeef                :
 												mem_wb  ? VX_mem_wb.mem_wb_pc         :
 												32'hdeadbeef;
 
+
+		wire zero = 0;
+
+		VX_generic_register #(.N(174)) wb_register(
+			.clk  (clk),
+			.reset(reset),
+			.stall(zero),
+			.flush(zero),
+			.in   ({VX_writeback_tempp.write_data, VX_writeback_tempp.wb_valid, VX_writeback_tempp.rd, VX_writeback_tempp.wb, VX_writeback_tempp.wb_warp_num, VX_writeback_tempp.wb_pc}),
+			.out  ({VX_writeback_inter.write_data, VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc})
+			);
+
+
 endmodule // VX_writeback
\ No newline at end of file