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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine
2020-08-26 08:05:34 -04:00
parent 7c5f04ad14 fde3f46798
commit c7cdb09822
9 changed files with 165 additions and 125 deletions
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2
hw/rtl/VX_config.vh
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@@ -55,8 +55,6 @@
`define EXT_F_ENABLE `define EXT_F_ENABLE
`define IBUF_ENABLE
// Device identification // Device identification
`define VENDOR_ID 0 `define VENDOR_ID 0
`define ARCHITECTURE_ID 0 `define ARCHITECTURE_ID 0

85
hw/rtl/VX_gpr_bypass.v
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@@ -2,52 +2,69 @@
module VX_gpr_bypass #( module VX_gpr_bypass #(
parameter DATAW = 1, parameter DATAW = 1,
parameter BUFFERED = 1 parameter PASSTHRU = 0
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire push, input wire push,
input reg pop, input wire pop,
input wire [DATAW-1:0] data_in, input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out output wire [DATAW-1:0] data_out
); );
reg [DATAW-1:0] buffer, buffer2; if (PASSTHRU) begin
reg use_buffer, use_buffer2; reg delayed_push;
reg delayed_push;
always @(posedge clk) begin
if (reset) begin
delayed_push <= 0;
end else begin
delayed_push <= push;
assert(!delayed_push || pop);
end
end
always @(posedge clk) begin assign data_out = data_in;
if (reset) begin
delayed_push <= 0; end else begin
use_buffer <= 0;
use_buffer2 <= 0; reg [DATAW-1:0] buffer, buffer2;
end else begin reg use_buffer, use_buffer2;
delayed_push <= push; reg delayed_push;
assert(!use_buffer2 || use_buffer);
if (pop) begin always @(posedge clk) begin
if (use_buffer) begin if (reset) begin
buffer <= buffer2; delayed_push <= 0;
use_buffer <= use_buffer2; use_buffer <= 0;
use_buffer2 <= 0; use_buffer2 <= 0;
end end else begin
end delayed_push <= push;
if (delayed_push) begin assert(!use_buffer2 || use_buffer);
if (use_buffer) begin if (pop) begin
assert(!use_buffer2); // queue full! if (use_buffer) begin
if (pop) begin buffer <= buffer2;
use_buffer <= use_buffer2;
use_buffer2 <= 0;
end
end
if (delayed_push) begin
if (use_buffer) begin
assert(!use_buffer2); // queue full!
if (pop) begin
buffer <= data_in;
end else begin
buffer2 <= data_in;
use_buffer2 <= 1;
end
use_buffer <= 1;
end else if (!pop) begin
buffer <= data_in; buffer <= data_in;
end else begin use_buffer <= 1;
buffer2 <= data_in; end
use_buffer2 <= 1;
end
use_buffer <= 1;
end else if (!pop) begin
buffer <= data_in;
use_buffer <= 1;
end end
end end
end end
assign data_out = use_buffer ? buffer : data_in;
end end
assign data_out = use_buffer ? buffer : data_in;
endmodule endmodule

89
hw/rtl/VX_ibuffer.v
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@@ -83,12 +83,11 @@ module VX_ibuffer #(
reg [`NW_BITS-1:0] deq_wid, deq_wid_n; reg [`NW_BITS-1:0] deq_wid, deq_wid_n;
reg deq_valid, deq_valid_n; reg deq_valid, deq_valid_n;
reg [DATAW-1:0] deq_instr, deq_instr_n; reg [DATAW-1:0] deq_instr, deq_instr_n;
reg deq_is_size1, deq_is_size1_n;
always @(*) begin always @(*) begin
valid_table_n = valid_table; valid_table_n = valid_table;
if (deq_fire && deq_is_size1) begin if (deq_fire) begin
valid_table_n[ibuf_deq_if.wid] = 0; valid_table_n[ibuf_deq_if.wid] = (q_size[deq_wid] != SIZEW'(1));
end end
if (enq_fire) begin if (enq_fire) begin
valid_table_n[ibuf_enq_if.wid] = 1; valid_table_n[ibuf_enq_if.wid] = 1;
@@ -96,32 +95,35 @@ module VX_ibuffer #(
end end
always @(*) begin always @(*) begin
deq_valid_n = 0; deq_valid_n = 0;
deq_wid_n = 'x; deq_wid_n = 'x;
deq_instr_n = 'x; deq_instr_n = 'x;
deq_is_size1_n = 'x;
schedule_table_n = schedule_table; schedule_table_n = schedule_table;
if (deq_fire && deq_is_size1) begin
schedule_table_n[ibuf_deq_if.wid] = 0; if (0 == num_warps) begin
end deq_valid_n = enq_fire;
deq_wid_n = ibuf_enq_if.wid;
for (integer i = 0; i < `NUM_WARPS; i++) begin deq_instr_n = q_data_in;
if (schedule_table_n[i]) begin end else if ((1 == num_warps) || freeze) begin
deq_valid_n = 1; deq_valid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) || enq_fire;
deq_wid_n = `NW_BITS'(i); deq_wid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) ? deq_wid : ibuf_enq_if.wid;
deq_instr_n = (deq_fire && (ibuf_deq_if.wid == `NW_BITS'(i))) ? q_data_prev[i] : q_data_out[i]; deq_instr_n = deq_fire ? ((q_size[deq_wid] != SIZEW'(1)) ? q_data_prev[deq_wid] : q_data_in) : q_data_out[deq_wid];
deq_is_size1_n = (~(enq_fire && ibuf_enq_if.wid == `NW_BITS'(i)) end else begin
&& (((deq_fire && ibuf_deq_if.wid == `NW_BITS'(i)) && (SIZEW'(2) == q_size[i])) for (integer i = 0; i < `NUM_WARPS; i++) begin
|| (SIZEW'(1) == q_size[i]))); if (schedule_table_n[i]) begin
schedule_table_n[i] = 0; deq_valid_n = 1;
break; deq_wid_n = `NW_BITS'(i);
deq_instr_n = q_data_out[i];
schedule_table_n[i] = 0;
break;
end
end end
end end
end end
wire warp_added = enq_fire && (0 == q_size[ibuf_enq_if.wid]) && (!deq_fire || ibuf_enq_if.wid != ibuf_deq_if.wid); wire warp_added = enq_fire && (0 == q_size[ibuf_enq_if.wid]);
wire warp_removed = deq_fire && (1 == q_size[ibuf_deq_if.wid]) && (!enq_fire || ibuf_enq_if.wid != ibuf_deq_if.wid); wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == ibuf_deq_if.wid) && (1 == q_size[ibuf_deq_if.wid]);
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
@@ -130,20 +132,18 @@ module VX_ibuffer #(
deq_valid <= 0; deq_valid <= 0;
num_warps <= 0; num_warps <= 0;
end else begin end else begin
valid_table <= valid_table_n; valid_table <= valid_table_n;
schedule_table <= (| schedule_table_n) ? schedule_table_n : valid_table_n;
if (enq_fire && (0 == num_warps)) begin if ((| schedule_table_n)) begin
deq_valid <= 1; schedule_table <= schedule_table_n;
deq_wid <= ibuf_enq_if.wid; end else begin
deq_instr <= q_data_in; schedule_table <= valid_table_n;
deq_is_size1 <= 1; schedule_table[deq_wid_n] <= 0;
end else if (!freeze) begin end
deq_valid <= deq_valid_n;
deq_wid <= deq_wid_n; deq_valid <= deq_valid_n;
deq_instr <= deq_instr_n; deq_wid <= deq_wid_n;
deq_is_size1 <= deq_is_size1_n; deq_instr <= deq_instr_n;
end
if (warp_added && !warp_removed) begin if (warp_added && !warp_removed) begin
num_warps <= num_warps + NWARPSW'(1); num_warps <= num_warps + NWARPSW'(1);
@@ -151,14 +151,19 @@ module VX_ibuffer #(
num_warps <= num_warps - NWARPSW'(1); num_warps <= num_warps - NWARPSW'(1);
end end
`ifdef VERILATOR `ifdef VERILATOR
/*if (enq_fire || deq_fire || deq_valid) begin
$display("*** %t: cur=%b(%0d), nxt=%b(%0d), enq=%b(%0d), deq=%b(%0d), nw=%0d(%0d,%0d,%0d,%0d), sched=%b, sched_n=%b",
$time, deq_valid, deq_wid, deq_valid_n, deq_wid_n, enq_fire, ibuf_enq_if.wid, deq_fire, ibuf_deq_if.wid, num_warps, size_r[0], size_r[1], size_r[2], size_r[3], schedule_table, schedule_table_n);
end*/
begin // verify 'num_warps' begin // verify 'num_warps'
integer nw = 0; integer nw = 0;
for (integer i = 0; i < `NUM_WARPS; i++) begin for (integer i = 0; i < `NUM_WARPS; i++) begin
nw += 32'(q_size[i] != 0); nw += 32'(q_size[i] != 0);
end end
assert(nw == 32'(num_warps)); assert(nw == 32'(num_warps)) else $display("%t: error: invalid num_warps: nw=%0d, ref=%0d", $time, num_warps, nw);
assert(~deq_fire || num_warps != 0); assert(~deq_valid || (q_size[deq_wid] != 0)) else $display("%t: error: invalid schedule: wid=%0d", $time, deq_wid);
assert(~deq_fire || (q_size[deq_wid] != 0)) else $display("%t: error: invalid dequeu: wid=%0d", $time, deq_wid);
end end
`endif `endif
end end

5
hw/rtl/VX_instr_demux.v
View File

@@ -48,7 +48,8 @@ module VX_instr_demux (
); );
VX_gpr_bypass #( VX_gpr_bypass #(
.DATAW ((2 * `NUM_THREADS * 32)) .DATAW (2 * `NUM_THREADS * 32),
.PASSTHRU (1) // ALU has no back-pressure, bypass not needed
) alu_bypass ( ) alu_bypass (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -231,6 +232,6 @@ module VX_instr_demux (
`ifdef EXT_F_ENABLE `ifdef EXT_F_ENABLE
|| (fpu_req_ready && (execute_if.ex_type == `EX_FPU)) || (fpu_req_ready && (execute_if.ex_type == `EX_FPU))
`endif `endif
|| (gpu_req_ready && (execute_if.ex_type == `EX_GPU)); || (gpu_req_ready && (execute_if.ex_type == `EX_GPU));
endmodule endmodule

18
hw/rtl/VX_ipdom_stack.v
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@@ -5,15 +5,15 @@ module VX_ipdom_stack #(
parameter WIDTH = 1, parameter WIDTH = 1,
parameter DEPTH = 1 parameter DEPTH = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
input reg [WIDTH - 1:0] q1, input wire [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2, input wire [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d, output wire [WIDTH - 1:0] d,
input wire push, input wire push,
input wire pop, input wire pop,
output wire empty, output wire empty,
output wire full output wire full
); );
localparam STACK_SIZE = 2 ** DEPTH; localparam STACK_SIZE = 2 ** DEPTH;

2
hw/rtl/VX_scoreboard.v
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@@ -55,7 +55,7 @@ module VX_scoreboard #(
if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
$display("%t: core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b, exe=%b, gpr=%b", $display("%t: core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b, exe=%b, gpr=%b",
$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.curr_PC, ibuf_deq_if.rd, ibuf_deq_if.wb, $time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.curr_PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
inuse_reg_mask[ibuf_deq_if.rd], inuse_reg_mask[ibuf_deq_if.rs1], inuse_reg_mask[ibuf_deq_if.rs2], inuse_reg_mask[ibuf_deq_if.rs3], exe_delay, gpr_delay); inuse_regs[ibuf_deq_if.rd], inuse_regs[ibuf_deq_if.rs1], inuse_regs[ibuf_deq_if.rs2], inuse_regs[ibuf_deq_if.rs3], exe_delay, gpr_delay);
end end
end end
`endif `endif

74
hw/rtl/VX_writeback.v
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@@ -23,42 +23,46 @@ module VX_writeback #(
wire mul_valid = mul_commit_if.valid && mul_commit_if.wb; wire mul_valid = mul_commit_if.valid && mul_commit_if.wb;
wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb; wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
VX_writeback_if writeback_tmp_if(); wire wb_valid;
wire [`NW_BITS-1:0] wb_wid;
assign writeback_tmp_if.valid = alu_valid ? alu_commit_if.valid : wire [`NUM_THREADS-1:0] wb_thread_mask;
lsu_valid ? lsu_commit_if.valid : wire [`NR_BITS-1:0] wb_rd;
csr_valid ? csr_commit_if.valid : wire [`NUM_THREADS-1:0][31:0] wb_data;
mul_valid ? mul_commit_if.valid :
fpu_valid ? fpu_commit_if.valid :
0;
assign writeback_tmp_if.wid = alu_valid ? alu_commit_if.wid :
lsu_valid ? lsu_commit_if.wid :
csr_valid ? csr_commit_if.wid :
mul_valid ? mul_commit_if.wid :
fpu_valid ? fpu_commit_if.wid :
0;
assign writeback_tmp_if.thread_mask = alu_valid ? alu_commit_if.thread_mask : assign wb_valid = alu_valid ? alu_commit_if.valid :
lsu_valid ? lsu_commit_if.thread_mask : lsu_valid ? lsu_commit_if.valid :
csr_valid ? csr_commit_if.thread_mask : csr_valid ? csr_commit_if.valid :
mul_valid ? mul_commit_if.thread_mask : mul_valid ? mul_commit_if.valid :
fpu_valid ? fpu_commit_if.thread_mask : fpu_valid ? fpu_commit_if.valid :
0; 0;
assign writeback_tmp_if.rd = alu_valid ? alu_commit_if.rd : assign wb_wid = alu_valid ? alu_commit_if.wid :
lsu_valid ? lsu_commit_if.rd : lsu_valid ? lsu_commit_if.wid :
csr_valid ? csr_commit_if.rd : csr_valid ? csr_commit_if.wid :
mul_valid ? mul_commit_if.rd : mul_valid ? mul_commit_if.wid :
fpu_valid ? fpu_commit_if.rd : fpu_valid ? fpu_commit_if.wid :
0; 0;
assign wb_thread_mask = alu_valid ? alu_commit_if.thread_mask :
lsu_valid ? lsu_commit_if.thread_mask :
csr_valid ? csr_commit_if.thread_mask :
mul_valid ? mul_commit_if.thread_mask :
fpu_valid ? fpu_commit_if.thread_mask :
0;
assign writeback_tmp_if.data = alu_valid ? alu_commit_if.data : assign wb_rd = alu_valid ? alu_commit_if.rd :
lsu_valid ? lsu_commit_if.data : lsu_valid ? lsu_commit_if.rd :
csr_valid ? csr_commit_if.data : csr_valid ? csr_commit_if.rd :
mul_valid ? mul_commit_if.data : mul_valid ? mul_commit_if.rd :
fpu_valid ? fpu_commit_if.data : fpu_valid ? fpu_commit_if.rd :
0; 0;
assign wb_data = alu_valid ? alu_commit_if.data :
lsu_valid ? lsu_commit_if.data :
csr_valid ? csr_commit_if.data :
mul_valid ? mul_commit_if.data :
fpu_valid ? fpu_commit_if.data :
0;
wire stall = ~writeback_if.ready && writeback_if.valid; wire stall = ~writeback_if.ready && writeback_if.valid;
@@ -69,8 +73,8 @@ module VX_writeback #(
.reset (reset), .reset (reset),
.stall (stall), .stall (stall),
.flush (1'b0), .flush (1'b0),
.in ({writeback_tmp_if.valid, writeback_tmp_if.wid, writeback_tmp_if.thread_mask, writeback_tmp_if.rd, writeback_tmp_if.data}), .in ({wb_valid, wb_wid, wb_thread_mask, wb_rd, wb_data}),
.out ({writeback_if.valid, writeback_if.wid, writeback_if.thread_mask, writeback_if.rd, writeback_if.data}) .out ({writeback_if.valid, writeback_if.wid, writeback_if.thread_mask, writeback_if.rd, writeback_if.data})
); );
assign alu_commit_if.ready = !stall; assign alu_commit_if.ready = !stall;

1
hw/simulate/simulator.cpp
View File

@@ -12,6 +12,7 @@ double sc_time_stamp() {
Simulator::Simulator() { Simulator::Simulator() {
// force random values for unitialized signals // force random values for unitialized signals
Verilated::randReset(2); Verilated::randReset(2);
Verilated::randSeed(50);
// Turn off assertion before reset // Turn off assertion before reset
Verilated::assertOn(false); Verilated::assertOn(false);

14
hw/syn/quartus/project.tcl
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@@ -38,6 +38,20 @@ set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name POWER_USE_TA_VALUE 65
set_global_assignment -name SEED 1
set idx 0 set idx 0
foreach arg $q_args_orig { foreach arg $q_args_orig {