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redesigned driver demo, fixed startup code, removed --cpu from simx,

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This commit is contained in:
Blaise Tine
2020-03-29 00:38:17 -04:00
parent 2d5cf89e00
commit c8a6470595
63 changed files with 40963 additions and 364160 deletions
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14
simX/include/archdef.h
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@@ -16,17 +16,16 @@ namespace Harp {
public:
struct Undefined {};
ArchDef(const std::string &s, bool cpu_mode = false, int num_warps =32, int num_threads = 32)
: cpu_mode_(cpu_mode) {
ArchDef(const std::string &s, int num_warps = 32, int num_threads = 32) {
std::istringstream iss(s.c_str());
wordSize = 4;
encChar = 'w';
nRegs = 32;
nPRegs = 0;
nThds = num_warps;
nWarps = num_threads;
nWarps = num_warps;
nThds = num_threads;
extent = EXT_WARPS;
// if (!iss) { extent = EXT_NULL; return; }
@@ -99,10 +98,6 @@ namespace Harp {
ThdNum getNWarps() const {
if (extent < EXT_WARPS) throw Undefined(); else return nWarps;
}
bool is_cpu_mode() const {
return cpu_mode_;
}
private:
enum Extent {
@@ -115,7 +110,6 @@ namespace Harp {
ThdNum nThds, nWarps;
RegNum nRegs, nPRegs;
char encChar;
bool cpu_mode_;
};
}

4254
simX/instruction.cpp
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File diff suppressed because it is too large Load Diff

10
simX/simX.cpp
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@@ -21,6 +21,8 @@
#include "include/args.h"
#include "include/help.h"
#include "../runtime/config.h"
#include <sys/stat.h>
//////////////
@@ -58,9 +60,8 @@ int emu_main(int argc, char **argv) {
string archString("rv32i");
string imgFileName("a.dsfsdout.bin");
bool showHelp(false), showStats(false), basicMachine(true);
bool cpu_mode(false);
int max_warps(32);
int max_threads(32);
int max_warps(NW);
int max_threads(NT);
/* Read the command line arguments. */
CommandLineArgFlag fh("-h", "--help", "", showHelp);
@@ -68,7 +69,6 @@ int emu_main(int argc, char **argv) {
CommandLineArgSetter<string>fa("-a", "--arch", "", archString);
CommandLineArgFlag fs("-s", "--stats", "", showStats);
CommandLineArgFlag fb("-b", "--basic", "", basicMachine);
CommandLineArgFlag fx("-x", "--cpu", "", cpu_mode);
CommandLineArgSetter<int> fw("-w", "--warps", "", max_warps);
CommandLineArgSetter<int> ft("-t", "--threads", "", max_threads);
@@ -80,7 +80,7 @@ int emu_main(int argc, char **argv) {
}
/* Instantiate a Core, RAM, and console output. */
ArchDef arch(archString, cpu_mode, max_warps, max_threads);
ArchDef arch(archString, max_warps, max_threads);
Decoder *dec;

92
simX/test_riscv.sh
View File

@@ -3,139 +3,139 @@ cd obj_dir
echo start > results.txt
echo ./riscv_tests/rv32ui-p-add.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-and.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-or.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-div.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-divu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mul.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-rem.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-remu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt