Added cache critical path optimizations
This commit is contained in:
10
hw/rtl/cache/VX_bank.v
vendored
10
hw/rtl/cache/VX_bank.v
vendored
@@ -536,7 +536,7 @@ module VX_bank #(
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|| dwbq_push_stall
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|| dwbq_push_stall
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|| dram_fill_req_stall);
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|| dram_fill_req_stall);
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assign recover_mrvq_state_st2 = miss_add && is_mrvq_st2;
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assign recover_mrvq_state_st2 = miss_add_unqual && is_mrvq_st2; // Doesn't need to include the stalls
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wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
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wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
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wire [`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel = wsel_st2;
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wire [`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel = wsel_st2;
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@@ -547,12 +547,12 @@ module VX_bank #(
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wire miss_add_is_mrvq = valid_st2 && is_mrvq_st2 && !stall_bank_pipe;
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wire miss_add_is_mrvq = valid_st2 && is_mrvq_st2 && !stall_bank_pipe;
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assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == qual_addr_st0);
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assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == dfpq_addr_st0); // Doesn't need to be muxed to qual, only care about fills
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assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1e);
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assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1e);
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assign mrvq_init_ready_state_st2 = mrvq_init_ready_state_unqual_st2
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assign mrvq_init_ready_state_st2 = mrvq_init_ready_state_unqual_st2 // When req was in st1e, either matched with an mrvq entery OR mrvq recovering state
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|| mrvq_init_ready_state_hazard_st0_st1
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|| mrvq_init_ready_state_hazard_st0_st1 // If there's a fill in st0 that has the same address as miss_add_addr
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|| mrvq_init_ready_state_hazard_st1e_st1;
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|| mrvq_init_ready_state_hazard_st1e_st1; // If there's a fill in st1 that has the same address as miss_add_addr
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VX_cache_miss_resrv #(
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VX_cache_miss_resrv #(
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.BANK_ID (BANK_ID),
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.BANK_ID (BANK_ID),
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