diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 705518fa..5af4660c 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -30,6 +30,7 @@ SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(MULTICORE) +VL_FLAGS += -Wno-DECLFILENAME # Use 64 bytes DRAM blocks CFLAGS += -DGLOBAL_BLOCK_SIZE=64 @@ -37,6 +38,9 @@ VL_FLAGS += -DGLOBAL_BLOCK_SIZE=64 VL_FLAGS += --x-initial unique +VL_FLAGS += -DDPRFQ_SIZE=0 -DIPRFQ_SIZE=0 -DSPRFQ_SIZE=0 -DL2PRFQ_SIZE=0 -DL3PRFQ_SIZE=0 +VL_FLAGS += -DDFILL_INVALIDAOR_SIZE=0 -DIFILL_INVALIDAOR_SIZE=0 -DSFILL_INVALIDAOR_SIZE=0 -DL2FILL_INVALIDAOR_SIZE=0 -DL3FILL_INVALIDAOR_SIZE=0 + # Enable Verilator multithreaded simulation #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #VL_FLAGS += --threads $(THREADS) diff --git a/hw/Makefile b/hw/Makefile index 5352a4b8..cc8cc4a9 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -3,6 +3,7 @@ all: build-s CF += -std=c++11 -fms-extensions VF += --language 1800-2009 --assert -Wall -Wpedantic +VF += -Wno-DECLFILENAME VF += -exe $(SRCS) $(INCLUDE) diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 59f1c574..812c30f1 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -22,6 +22,10 @@ /* verilator lint_on PINCONNECTEMPTY */ \ /* verilator lint_on DECLFILENAME */ +`define UNUSED_VAR(x) /* verilator lint_off UNUSED */ \ + wire [$bits(x)-1:0] __``x``__ = x; \ + /* verilator lint_on UNUSED */ + `define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ . x () \ /* verilator lint_on PINCONNECTEMPTY */ diff --git a/hw/rtl/VX_dmem_ctrl.v b/hw/rtl/VX_dmem_ctrl.v index 22275fe3..5fea01aa 100644 --- a/hw/rtl/VX_dmem_ctrl.v +++ b/hw/rtl/VX_dmem_ctrl.v @@ -96,40 +96,40 @@ module VX_dmem_ctrl # ( .core_rsp_ready (smem_core_rsp_if.core_rsp_ready), // DRAM request - `UNUSED_PIN(dram_req_read), - `UNUSED_PIN(dram_req_write), - `UNUSED_PIN(dram_req_addr), - `UNUSED_PIN(dram_req_data), - `UNUSED_PIN(dram_req_tag), + `UNUSED_PIN (dram_req_read), + `UNUSED_PIN (dram_req_write), + `UNUSED_PIN (dram_req_addr), + `UNUSED_PIN (dram_req_data), + `UNUSED_PIN (dram_req_tag), .dram_req_ready (1'b0), // DRAM response .dram_rsp_valid (1'b0), .dram_rsp_data (0), .dram_rsp_tag (`SDRAM_TAG_WIDTH'(0)), - `UNUSED_PIN(dram_rsp_ready), + `UNUSED_PIN (dram_rsp_ready), // Snoop request .snp_req_valid (1'b0), .snp_req_addr (0), .snp_req_tag (0), - `UNUSED_PIN(snp_req_ready), + `UNUSED_PIN (snp_req_ready), // Snoop response - `UNUSED_PIN(snp_rsp_valid), - `UNUSED_PIN(snp_rsp_tag), + `UNUSED_PIN (snp_rsp_valid), + `UNUSED_PIN (snp_rsp_tag), .snp_rsp_ready (1'b0), // Snoop forward out - `UNUSED_PIN(snp_fwdout_valid), - `UNUSED_PIN(snp_fwdout_addr), - `UNUSED_PIN(snp_fwdout_tag), + `UNUSED_PIN (snp_fwdout_valid), + `UNUSED_PIN (snp_fwdout_addr), + `UNUSED_PIN (snp_fwdout_tag), .snp_fwdout_ready (0), // Snoop forward in .snp_fwdin_valid (0), .snp_fwdin_tag (0), - `UNUSED_PIN(snp_fwdin_ready) + `UNUSED_PIN (snp_fwdin_ready) ); VX_cache #( @@ -203,15 +203,15 @@ module VX_dmem_ctrl # ( .snp_rsp_ready (dcache_snp_rsp_if.snp_rsp_ready), // Snoop forward out - `UNUSED_PIN(snp_fwdout_valid), - `UNUSED_PIN(snp_fwdout_addr), - `UNUSED_PIN(snp_fwdout_tag), + `UNUSED_PIN (snp_fwdout_valid), + `UNUSED_PIN (snp_fwdout_addr), + `UNUSED_PIN (snp_fwdout_tag), .snp_fwdout_ready (0), // Snoop forward in .snp_fwdin_valid (0), .snp_fwdin_tag (0), - `UNUSED_PIN(snp_fwdin_ready) + `UNUSED_PIN (snp_fwdin_ready) ); VX_cache #( @@ -276,23 +276,23 @@ module VX_dmem_ctrl # ( .snp_req_valid (1'b0), .snp_req_addr (0), .snp_req_tag (0), - `UNUSED_PIN(snp_req_ready), + `UNUSED_PIN (snp_req_ready), // Snoop response - `UNUSED_PIN(snp_rsp_valid), - `UNUSED_PIN(snp_rsp_tag), + `UNUSED_PIN (snp_rsp_valid), + `UNUSED_PIN (snp_rsp_tag), .snp_rsp_ready (1'b0), // Snoop forward out - `UNUSED_PIN(snp_fwdout_valid), - `UNUSED_PIN(snp_fwdout_addr), - `UNUSED_PIN(snp_fwdout_tag), + `UNUSED_PIN (snp_fwdout_valid), + `UNUSED_PIN (snp_fwdout_addr), + `UNUSED_PIN (snp_fwdout_tag), .snp_fwdout_ready (0), // Snoop forward in .snp_fwdin_valid (0), .snp_fwdin_tag (0), - `UNUSED_PIN(snp_fwdin_ready) + `UNUSED_PIN (snp_fwdin_ready) ); endmodule diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 5cb39408..36ba9941 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -101,7 +101,7 @@ module VX_gpr_stage ( .flush (stall_rest), .in (stall_lsu), .out (delayed_lsu_last_cycle), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); wire[`NUM_THREADS-1:0][31:0] temp_store_data; diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index bae2910e..53a02937 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -114,12 +114,10 @@ module Vortex_Cluster #( .D_dram_rsp_valid (per_core_D_dram_rsp_valid [i]), .D_dram_rsp_data (per_core_D_dram_rsp_data [i]), .D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]), - .D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]), - .I_dram_req_read (per_core_I_dram_req_read [i]), + .D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]), - `IGNORE_WARNINGS_BEGIN - .I_dram_req_write (), - `IGNORE_WARNINGS_END + .I_dram_req_read (per_core_I_dram_req_read [i]), + `UNUSED_PIN (I_dram_req_write), .I_dram_req_addr (per_core_I_dram_req_addr [i]), .I_dram_req_data (per_core_I_dram_req_data [i]), .I_dram_req_tag (per_core_I_dram_req_tag [i]), @@ -400,11 +398,9 @@ module Vortex_Cluster #( .snp_req_tag (snp_req_tag), .snp_req_ready (snp_req_ready), - .snp_rsp_valid (snp_rsp_valid), + .snp_rsp_valid (snp_rsp_valid), + `UNUSED_PIN (snp_rsp_addr), .snp_rsp_tag (snp_rsp_tag), - `IGNORE_WARNINGS_BEGIN - .snp_rsp_addr (), - `IGNORE_WARNINGS_END .snp_rsp_ready (snp_rsp_ready), .snp_fwdout_valid (arb_snp_fwdout_valid), diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 25b041f5..ace27ae2 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -113,7 +113,6 @@ module VX_bank #( wire[2:0] debug_mem_write_st0; wire[`REQS_BITS-1:0] debug_tid_st0; - wire[31:0] debug_use_pc_st1e; wire[1:0] debug_wb_st1e; wire[4:0] debug_rd_st1e; @@ -122,7 +121,6 @@ module VX_bank #( wire[2:0] debug_mem_write_st1e; wire[`REQS_BITS-1:0] debug_tid_st1e; - wire[31:0] debug_use_pc_st2; wire[1:0] debug_wb_st2; wire[4:0] debug_rd_st2; @@ -151,7 +149,7 @@ module VX_bank #( .data_out({snrq_addr_st0, snrq_tag_st0}), .empty (snrq_empty), .full (snrq_full), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); assign snp_req_ready = ~snrq_full; @@ -174,7 +172,7 @@ module VX_bank #( .data_out({dfpq_addr_st0, dfpq_filldata_st0}), .empty (dfpq_empty), .full (dfpq_full), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); assign dram_fill_rsp_ready = !dfpq_full; @@ -585,7 +583,7 @@ module VX_bank #( .data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}), .empty (cwbq_empty), .full (cwbq_full), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); assign core_rsp_valid = !cwbq_empty; @@ -655,7 +653,7 @@ module VX_bank #( .data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}), .empty (dwbq_empty), .full (dwbq_full), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); wire dram_wb_req_fire = dram_wb_req_valid && dram_wb_req_ready; diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index aaa8a3f7..06f27375 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -439,13 +439,13 @@ module VX_cache #( .NUM_BANKS (NUM_BANKS), .BANK_LINE_SIZE (BANK_LINE_SIZE), .SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH) - ) snp_rsp_arb ( + ) snp_rsp_arb ( .per_bank_snp_rsp_valid (per_bank_snp_rsp_valid), .per_bank_snp_rsp_tag (per_bank_snp_rsp_tag), .per_bank_snp_rsp_ready (per_bank_snp_rsp_ready), - .snp_rsp_valid (snp_rsp_valid), - .snp_rsp_tag (snp_rsp_tag), - .snp_rsp_ready (snp_rsp_ready) + .snp_rsp_valid (snp_rsp_valid), + .snp_rsp_tag (snp_rsp_tag), + .snp_rsp_ready (snp_rsp_ready) ); endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache_dfq_queue.v b/hw/rtl/cache/VX_cache_dfq_queue.v index dcdea1e5..c1368d32 100644 --- a/hw/rtl/cache/VX_cache_dfq_queue.v +++ b/hw/rtl/cache/VX_cache_dfq_queue.v @@ -51,7 +51,7 @@ module VX_cache_dfq_queue #( .data_out({out_per_bank_dram_fill_req_valid, out_per_bank_dram_fill_req_addr}), .empty (o_empty), .full (dfqq_full), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}}); diff --git a/hw/rtl/cache/VX_cache_req_queue.v b/hw/rtl/cache/VX_cache_req_queue.v index 4d4609ce..0bb8f1d6 100644 --- a/hw/rtl/cache/VX_cache_req_queue.v +++ b/hw/rtl/cache/VX_cache_req_queue.v @@ -84,7 +84,7 @@ module VX_cache_req_queue #( .data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}), .empty (o_empty), .full (reqq_full), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}}; diff --git a/hw/rtl/cache/VX_fill_invalidator.v b/hw/rtl/cache/VX_fill_invalidator.v index 45fab1ca..0e258bc1 100644 --- a/hw/rtl/cache/VX_fill_invalidator.v +++ b/hw/rtl/cache/VX_fill_invalidator.v @@ -10,12 +10,9 @@ module VX_fill_invalidator #( ) ( input wire clk, input wire reset, - input wire possible_fill, input wire success_fill, - input wire[`LINE_ADDR_WIDTH-1:0] fill_addr, - output reg invalidate_fill ); @@ -23,6 +20,12 @@ module VX_fill_invalidator #( assign invalidate_fill = 0; + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (possible_fill) + `UNUSED_VAR (success_fill) + `UNUSED_VAR (fill_addr) + end else begin reg [FILL_INVALIDAOR_SIZE-1:0] fills_active; diff --git a/hw/rtl/cache/VX_prefetcher.v b/hw/rtl/cache/VX_prefetcher.v index 4478123e..f1fafe8e 100644 --- a/hw/rtl/cache/VX_prefetcher.v +++ b/hw/rtl/cache/VX_prefetcher.v @@ -47,7 +47,7 @@ module VX_prefetcher #( .empty (current_empty), .full (current_full), - `UNUSED_PIN(size) + `UNUSED_PIN (size) ); assign pref_valid = 0; // TODO use_valid != 0; diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index 5f338589..2ce1e4c4 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -27,9 +27,7 @@ module VX_divide #( generate if (NREP != DREP) begin - `IGNORE_WARNINGS_BEGIN different_nrep_drep_not_yet_supported non_existing_module(); - `IGNORE_WARNINGS_END end if (IMPL == "quartus") begin @@ -58,6 +56,7 @@ module VX_divide #( wire [WIDTHN-1:0] numer_pipe_end; wire [WIDTHD-1:0] denom_pipe_end; + if (PIPELINE == 0) begin assign numer_pipe_end = numer; assign denom_pipe_end = denom; @@ -100,16 +99,6 @@ module VX_divide #( if (NREP == "SIGNED") begin - /*VX_divide_ifnal_signed #( - .WIDTHN, - .WIDTHD - )div( - .numer(numer_pipe_end), - .denom(denom_pipe_end), - .quotient, - .remainder - );*/ - always @(*) begin if (denom_pipe_end == 0) begin quotient = 32'hffffffff; @@ -118,12 +107,12 @@ module VX_divide #( else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin // this edge case kills verilator in some cases by causing a division // overflow exception. INT_MIN / -1 (on x86) - quotient = 0; + quotient = 0; remainder = 0; end else begin - quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end)); - remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end)); + quotient = $signed($signed(numer_pipe_end) / $signed(denom_pipe_end)); + remainder = $signed($signed(numer_pipe_end) % $signed(denom_pipe_end)); end end diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 0a307a16..40f130bb 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -4,26 +4,30 @@ module VX_generic_queue #( parameter DATAW, parameter SIZE = 16, parameter BUFFERED_OUTPUT = 1 -) ( -`IGNORE_WARNINGS_BEGIN +) ( input wire clk, input wire reset, input wire push, - input wire pop, - output wire empty, - output wire full, -`IGNORE_WARNINGS_END + input wire pop, input wire [DATAW-1:0] data_in, output wire [DATAW-1:0] data_out, + output wire empty, + output wire full, output wire [`LOG2UP(SIZE+1)-1:0] size ); if (SIZE == 0) begin assign empty = 1; - assign data_out = data_in; + assign data_out = 0; assign full = 0; assign size = 0; + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (push) + `UNUSED_VAR (pop) + `UNUSED_VAR (data_in) + end else begin // (SIZE > 0) `ifdef QUEUE_FORCE_MLAB diff --git a/hw/rtl/libs/VX_generic_register.v b/hw/rtl/libs/VX_generic_register.v index a570b676..8f1036de 100644 --- a/hw/rtl/libs/VX_generic_register.v +++ b/hw/rtl/libs/VX_generic_register.v @@ -4,33 +4,25 @@ module VX_generic_register #( parameter N, parameter PassThru = 0 ) ( -`IGNORE_WARNINGS_BEGIN input wire clk, input wire reset, input wire stall, input wire flush, -`IGNORE_WARNINGS_END input wire[N-1:0] in, output wire[N-1:0] out ); + reg [(N-1):0] value; - if (PassThru) begin - assign out = in; - end else begin - - reg [(N-1):0] value; - - always @(posedge clk) begin - if (reset) begin - value <= 0; - end else if (flush) begin - value <= 0; - end else if (~stall) begin - value <= in; - end + always @(posedge clk) begin + if (reset) begin + value <= 0; + end else if (flush) begin + value <= 0; + end else if (~stall) begin + value <= in; end - - assign out = value; end + assign out = PassThru ? in : value; + endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_mult.v b/hw/rtl/libs/VX_mult.v index 287d7116..088cad0d 100644 --- a/hw/rtl/libs/VX_mult.v +++ b/hw/rtl/libs/VX_mult.v @@ -34,7 +34,6 @@ module VX_mult #( localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5; if (FORCE_LE == "YES") begin - `IGNORE_WARNINGS_BEGIN lpm_mult #( .LPM_WIDTHA(WIDTHA), .LPM_WIDTHB(WIDTHB), @@ -51,7 +50,6 @@ module VX_mult #( .datab(datab), .result(result) ); - `IGNORE_WARNINGS_END end else begin lpm_mult#( @@ -76,6 +74,7 @@ module VX_mult #( wire [WIDTHA-1:0] dataa_pipe_end; wire [WIDTHB-1:0] datab_pipe_end; + if (PIPELINE == 0) begin assign dataa_pipe_end = dataa; assign datab_pipe_end = datab;