From d33916f1e0d8bf468c56b9df3d9b7a983a135377 Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@iam-ssh1.research.intel-research.net>
Date: Mon, 29 Jun 2020 00:38:59 -0700
Subject: [PATCH] minor update

---
 driver/rtlsim/Makefile    | 5 ++---
 hw/rtl/VX_lsu_unit.v      | 2 +-
 hw/simulate/Makefile      | 4 ++--
 hw/simulate/simulator.cpp | 6 +-----
 4 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile
index bafa89bc..b106d147 100644
--- a/driver/rtlsim/Makefile
+++ b/driver/rtlsim/Makefile
@@ -13,7 +13,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
 DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE  
 DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
 
-DBG_FLAGS += $(DBG_PRINT_FLAGS)
+#DBG_FLAGS += $(DBG_PRINT_FLAGS)
 DBG_FLAGS += -DDBG_CORE_REQ_INFO
 
 #CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4
@@ -38,8 +38,7 @@ RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../
 
 VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
 VL_FLAGS += -Wno-DECLFILENAME
-VL_FLAGS += --x-initial unique
-VL_FLAGS += --x-assign unique
+VL_FLAGS += --x-initial unique --x-assign unique
 
 # Enable Verilator multithreaded simulation
 #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v
index 60a6e7b2..640640b3 100644
--- a/hw/rtl/VX_lsu_unit.v
+++ b/hw/rtl/VX_lsu_unit.v
@@ -116,7 +116,7 @@ module VX_lsu_unit #(
         end    
         if (mrq_pop_part) begin
             mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd;
-            assert(mrq_read_addr == dbg_mrq_write_addr);            
+            assert(($time < 2) || mrq_read_addr == dbg_mrq_write_addr);            
         end
     end
 
diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile
index eba2d281..73697f0b 100644
--- a/hw/simulate/Makefile
+++ b/hw/simulate/Makefile
@@ -12,7 +12,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
 DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE  
 DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
 
-DBG_FLAGS += $(DBG_PRINT_FLAGS)
+#DBG_FLAGS += $(DBG_PRINT_FLAGS)
 DBG_FLAGS += -DDBG_CORE_REQ_INFO
 
 INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate
@@ -25,7 +25,7 @@ CF += -std=c++11 -fms-extensions -I../..
 
 VF += --language 1800-2009 --assert -Wall -Wpedantic
 VF += -Wno-DECLFILENAME
-VF += --x-initial unique
+VF += --x-initial unique --x-assign unique
 VF += -exe $(SRCS) $(INCLUDE)
 
 DBG += -DVCD_OUTPUT $(DBG_FLAGS)
diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp
index 09a9b72c..2976a43c 100644
--- a/hw/simulate/simulator.cpp
+++ b/hw/simulate/simulator.cpp
@@ -9,13 +9,9 @@ double sc_time_stamp() {
   return timestamp;
 }
 
-Simulator::Simulator() {    
-
-#ifdef NDEBUG
+Simulator::Simulator() {  
   // force random values for unitialized signals  
   Verilated::randReset(2);
-  Verilated::assertOn(false);
-#endif
 
   ram_ = nullptr;
   vortex_ = new VVortex();