From 18c1dc2f0e8c941903f549ce997df99f9477a8d7 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 28 Sep 2021 02:42:04 -0700 Subject: [PATCH 1/6] fixed interface modports --- ci/regression.sh | 3 -- hw/rtl/VX_issue.v | 79 ++++++++++++++++++----------- hw/rtl/VX_pipeline.v | 6 +-- hw/rtl/VX_scoreboard.v | 16 +++--- hw/rtl/cache/VX_shared_mem.v | 5 +- hw/rtl/interfaces/VX_ibuffer_if.v | 14 +++++ hw/rtl/interfaces/VX_writeback_if.v | 9 ++++ 7 files changed, 86 insertions(+), 46 deletions(-) diff --git a/ci/regression.sh b/ci/regression.sh index 4b825960..8a5bff96 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -3,9 +3,6 @@ # exit when any command fails set -e -# build sources -make -s - coverage() { echo "begin coverage tests..." diff --git a/hw/rtl/VX_issue.v b/hw/rtl/VX_issue.v index 31483b9a..e6312fd4 100644 --- a/hw/rtl/VX_issue.v +++ b/hw/rtl/VX_issue.v @@ -24,11 +24,51 @@ module VX_issue #( VX_gpu_req_if.master gpu_req_if ); VX_ibuffer_if ibuffer_if(); - VX_ibuffer_if execute_if(); - VX_gpr_req_if gpr_req_if(); VX_gpr_rsp_if gpr_rsp_if(); - wire scoreboard_delay; + VX_gpr_req_if gpr_req_if(); + assign gpr_req_if.wid = ibuffer_if.wid; + assign gpr_req_if.rs1 = ibuffer_if.rs1; + assign gpr_req_if.rs2 = ibuffer_if.rs2; + assign gpr_req_if.rs3 = ibuffer_if.rs3; + + VX_writeback_if sboard_wb_if(); + assign sboard_wb_if.valid = writeback_if.valid; + assign sboard_wb_if.wid = writeback_if.wid; + assign sboard_wb_if.PC = writeback_if.PC; + assign sboard_wb_if.rd = writeback_if.rd; + assign sboard_wb_if.eop = writeback_if.eop; + assign sboard_wb_if.ready = writeback_if.ready; + + VX_ibuffer_if sboard_ib_if(); + assign sboard_ib_if.valid = ibuffer_if.valid && idmux_ib_if.ready; + assign sboard_ib_if.wid = ibuffer_if.wid; + assign sboard_ib_if.PC = ibuffer_if.PC; + assign sboard_ib_if.wb = ibuffer_if.wb; + assign sboard_ib_if.rd = ibuffer_if.rd; + assign sboard_ib_if.rd_n = ibuffer_if.rd_n; + assign sboard_ib_if.rs1_n = ibuffer_if.rs1_n; + assign sboard_ib_if.rs2_n = ibuffer_if.rs2_n; + assign sboard_ib_if.rs3_n = ibuffer_if.rs3_n; + assign sboard_ib_if.wid_n = ibuffer_if.wid_n; + + VX_ibuffer_if idmux_ib_if(); + assign idmux_ib_if.valid = ibuffer_if.valid && sboard_ib_if.ready; + assign idmux_ib_if.wid = ibuffer_if.wid; + assign idmux_ib_if.tmask = ibuffer_if.tmask; + assign idmux_ib_if.PC = ibuffer_if.PC; + assign idmux_ib_if.ex_type = ibuffer_if.ex_type; + assign idmux_ib_if.op_type = ibuffer_if.op_type; + assign idmux_ib_if.op_mod = ibuffer_if.op_mod; + assign idmux_ib_if.wb = ibuffer_if.wb; + assign idmux_ib_if.rd = ibuffer_if.rd; + assign idmux_ib_if.rs1 = ibuffer_if.rs1; + assign idmux_ib_if.imm = ibuffer_if.imm; + assign idmux_ib_if.use_PC = ibuffer_if.use_PC; + assign idmux_ib_if.use_imm = ibuffer_if.use_imm; + + // issue the instruction + assign ibuffer_if.ready = sboard_ib_if.ready && idmux_ib_if.ready; `RESET_RELAY (ibuf_reset); `RESET_RELAY (gpr_reset); @@ -48,15 +88,9 @@ module VX_issue #( ) scoreboard ( .clk (clk), .reset (reset), - .ibuffer_if (ibuffer_if), - .writeback_if(writeback_if), - .delay (scoreboard_delay) + .ibuffer_if (sboard_ib_if), + .writeback_if(sboard_wb_if) ); - - assign gpr_req_if.wid = ibuffer_if.wid; - assign gpr_req_if.rs1 = ibuffer_if.rs1; - assign gpr_req_if.rs2 = ibuffer_if.rs2; - assign gpr_req_if.rs3 = ibuffer_if.rs3; VX_gpr_stage #( .CORE_ID(CORE_ID) @@ -68,24 +102,10 @@ module VX_issue #( .gpr_rsp_if (gpr_rsp_if) ); - assign execute_if.valid = ibuffer_if.valid && ~scoreboard_delay; - assign execute_if.wid = ibuffer_if.wid; - assign execute_if.tmask = ibuffer_if.tmask; - assign execute_if.PC = ibuffer_if.PC; - assign execute_if.ex_type = ibuffer_if.ex_type; - assign execute_if.op_type = ibuffer_if.op_type; - assign execute_if.op_mod = ibuffer_if.op_mod; - assign execute_if.wb = ibuffer_if.wb; - assign execute_if.rd = ibuffer_if.rd; - assign execute_if.rs1 = ibuffer_if.rs1; - assign execute_if.imm = ibuffer_if.imm; - assign execute_if.use_PC = ibuffer_if.use_PC; - assign execute_if.use_imm = ibuffer_if.use_imm; - VX_instr_demux instr_demux ( .clk (clk), .reset (demux_reset), - .ibuffer_if (execute_if), + .ibuffer_if (idmux_ib_if), .gpr_rsp_if (gpr_rsp_if), .alu_req_if (alu_req_if), .lsu_req_if (lsu_req_if), @@ -94,10 +114,7 @@ module VX_issue #( .fpu_req_if (fpu_req_if), `endif .gpu_req_if (gpu_req_if) - ); - - // issue the instruction - assign ibuffer_if.ready = !scoreboard_delay && execute_if.ready; + ); `SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready); `SCOPE_ASSIGN (issue_wid, ibuffer_if.wid); @@ -115,7 +132,7 @@ module VX_issue #( `SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC); `SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm); `SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay); - `SCOPE_ASSIGN (execute_delay, ~execute_if.ready); + `SCOPE_ASSIGN (execute_delay, ~idmux_ib_if.ready); `SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data); `SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data); `SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data); diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index ea763315..8bbc7ead 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -22,19 +22,19 @@ module VX_pipeline #( input wire dcache_rsp_valid, input wire [`NUM_THREADS-1:0] dcache_rsp_tmask, input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data, - input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag, + input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag, output wire dcache_rsp_ready, // Icache core request output wire icache_req_valid, output wire [29:0] icache_req_addr, - output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag, + output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag, input wire icache_req_ready, // Icache core response input wire icache_rsp_valid, input wire [31:0] icache_rsp_data, - input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag, + input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag, output wire icache_rsp_ready, `ifdef PERF_ENABLE diff --git a/hw/rtl/VX_scoreboard.v b/hw/rtl/VX_scoreboard.v index f6592c4f..9503ecdf 100644 --- a/hw/rtl/VX_scoreboard.v +++ b/hw/rtl/VX_scoreboard.v @@ -3,12 +3,11 @@ module VX_scoreboard #( parameter CORE_ID = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, - VX_ibuffer_if.slave ibuffer_if, - VX_writeback_if.slave writeback_if, - output wire delay + VX_ibuffer_if.scoreboard ibuffer_if, + VX_writeback_if.scoreboard writeback_if ); reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; @@ -43,7 +42,12 @@ module VX_scoreboard #( deq_inuse_rs3 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs3_n]; end - assign delay = deq_inuse_rd | deq_inuse_rs1 | deq_inuse_rs2 | deq_inuse_rs3; + assign writeback_if.ready = 1'b1; + + assign ibuffer_if.ready = ~(deq_inuse_rd + | deq_inuse_rs1 + | deq_inuse_rs2 + | deq_inuse_rs3); `UNUSED_VAR (writeback_if.PC) diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 2a8f7c47..51c60a38 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -157,7 +157,8 @@ module VX_shared_mem #( .valid_out (creq_out_valid) ); - wire crsq_last_read; + wire crsq_in_valid, crsq_in_ready; + wire crsq_last_read; assign creq_out_ready = core_req_writeonly || (crsq_in_ready && crsq_last_read); @@ -195,8 +196,6 @@ module VX_shared_mem #( wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; reg [NUM_BANKS-1:0] bank_rsp_sel_r, bank_rsp_sel_n; - wire crsq_in_valid, crsq_in_ready; - wire crsq_in_fire = crsq_in_valid && crsq_in_ready; assign crsq_last_read = (bank_rsp_sel_n == core_req_read_mask); diff --git a/hw/rtl/interfaces/VX_ibuffer_if.v b/hw/rtl/interfaces/VX_ibuffer_if.v index bb791737..45569371 100644 --- a/hw/rtl/interfaces/VX_ibuffer_if.v +++ b/hw/rtl/interfaces/VX_ibuffer_if.v @@ -76,6 +76,20 @@ interface VX_ibuffer_if (); input wid_n, output ready ); + + modport scoreboard ( + input valid, + input wid, + input PC, + input wb, + input rd, + input rd_n, + input rs1_n, + input rs2_n, + input rs3_n, + input wid_n, + output ready + ); endinterface diff --git a/hw/rtl/interfaces/VX_writeback_if.v b/hw/rtl/interfaces/VX_writeback_if.v index 8f05fc7a..b3e2060d 100644 --- a/hw/rtl/interfaces/VX_writeback_if.v +++ b/hw/rtl/interfaces/VX_writeback_if.v @@ -36,6 +36,15 @@ interface VX_writeback_if (); output ready ); + modport scoreboard ( + input valid, + input wid, + input PC, + input rd, + input eop, + output ready + ); + endinterface `endif From a45261b530559a08d76f6930d22d52d6b511ae61 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 29 Sep 2021 03:24:17 -0400 Subject: [PATCH 2/6] code refactoring for Vivado compatibility --- hw/rtl/VX_cluster.v | 22 ++++++++-------- hw/rtl/VX_core.v | 16 ++++++------ hw/rtl/VX_csr_data.v | 2 ++ hw/rtl/VX_decode.v | 2 ++ hw/rtl/VX_define.vh | 13 ++++++---- hw/rtl/VX_fpu_unit.v | 3 ++- hw/rtl/{VX_types.vh => VX_gpu_types.vh} | 34 +++++++------------------ hw/rtl/VX_gpu_unit.v | 1 + hw/rtl/VX_lsu_unit.v | 2 +- hw/rtl/VX_platform.vh | 28 +++++++++++--------- hw/rtl/Vortex.v | 10 ++++---- hw/rtl/fp_cores/VX_fp_class.v | 2 +- hw/rtl/fp_cores/VX_fp_cvt.v | 2 +- hw/rtl/fp_cores/VX_fp_div.v | 6 +---- hw/rtl/fp_cores/VX_fp_fma.v | 6 +---- hw/rtl/fp_cores/VX_fp_ncomp.v | 2 +- hw/rtl/fp_cores/VX_fp_rounding.v | 3 +-- hw/rtl/fp_cores/VX_fp_sqrt.v | 6 +---- hw/rtl/fp_cores/VX_fpu_define.vh | 14 ++++++++++ hw/rtl/fp_cores/VX_fpu_dpi.v | 9 ++----- hw/rtl/fp_cores/VX_fpu_fpga.v | 2 +- hw/rtl/fp_cores/VX_fpu_fpnew.v | 2 +- hw/rtl/fp_cores/VX_fpu_types.vh | 32 +++++++++++++++++++++++ hw/rtl/interfaces/VX_fpu_to_csr_if.v | 2 +- hw/rtl/interfaces/VX_warp_ctl_if.v | 12 ++++----- hw/rtl/libs/VX_bypass_buffer.v | 2 +- hw/rtl/libs/VX_dp_ram.v | 2 +- hw/rtl/libs/VX_sp_ram.v | 2 +- hw/rtl/libs/VX_stream_arbiter.v | 2 +- hw/syn/opae/vortex_afu.qsf | 1 - hw/syn/quartus/project.tcl | 1 - 31 files changed, 133 insertions(+), 110 deletions(-) rename hw/rtl/{VX_types.vh => VX_gpu_types.vh} (51%) create mode 100644 hw/rtl/fp_cores/VX_fpu_define.vh create mode 100644 hw/rtl/fp_cores/VX_fpu_types.vh diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index 030b7e65..be933ae6 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -12,16 +12,16 @@ module VX_cluster #( // Memory request output wire mem_req_valid, output wire mem_req_rw, - output wire [`L2_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, - output wire [`L2_MEM_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`L2_MEM_DATA_WIDTH-1:0] mem_req_data, - output wire [`L2_MEM_TAG_WIDTH-1:0] mem_req_tag, + output wire [`L2_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, + output wire [`L2_MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`L2_MEM_DATA_WIDTH-1:0] mem_req_data, + output wire [`L2_MEM_TAG_WIDTH-1:0] mem_req_tag, input wire mem_req_ready, // Memory response input wire mem_rsp_valid, - input wire [`L2_MEM_DATA_WIDTH-1:0] mem_rsp_data, - input wire [`L2_MEM_TAG_WIDTH-1:0] mem_rsp_tag, + input wire [`L2_MEM_DATA_WIDTH-1:0] mem_rsp_data, + input wire [`L2_MEM_TAG_WIDTH-1:0] mem_rsp_tag, output wire mem_rsp_ready, // Status @@ -34,12 +34,12 @@ module VX_cluster #( wire [`NUM_CORES-1:0][`DCACHE_MEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen; wire [`NUM_CORES-1:0][`DCACHE_MEM_ADDR_WIDTH-1:0] per_core_mem_req_addr; wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_req_data; - wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_req_tag; + wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_req_tag; wire [`NUM_CORES-1:0] per_core_mem_req_ready; wire [`NUM_CORES-1:0] per_core_mem_rsp_valid; wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_rsp_data; - wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag; + wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag; wire [`NUM_CORES-1:0] per_core_mem_rsp_ready; wire [`NUM_CORES-1:0] per_core_busy; @@ -69,7 +69,7 @@ module VX_cluster #( .mem_rsp_tag (per_core_mem_rsp_tag [i]), .mem_rsp_ready (per_core_mem_rsp_ready[i]), - .busy (per_core_busy [i]) + .busy (per_core_busy [i]) ); end @@ -96,7 +96,7 @@ module VX_cluster #( .MRSQ_SIZE (`L2_MRSQ_SIZE), .MREQ_SIZE (`L2_MREQ_SIZE), .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`XMEM_TAG_WIDTH), + .CORE_TAG_WIDTH (`L1_MEM_TAG_WIDTH), .CORE_TAG_ID_BITS (0), .MEM_TAG_WIDTH (`L2_MEM_TAG_WIDTH), .NC_ENABLE (1) @@ -150,7 +150,7 @@ module VX_cluster #( .NUM_REQS (`NUM_CORES), .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`XMEM_TAG_WIDTH), + .TAG_IN_WIDTH (`L1_MEM_TAG_WIDTH), .TYPE ("R"), .TAG_SEL_IDX (1), // Skip 0 for NC flag .BUFFERED_REQ (1), diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index a4a27eb0..d1cbbb6f 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -12,16 +12,16 @@ module VX_core #( // Memory request output wire mem_req_valid, output wire mem_req_rw, - output wire [`DCACHE_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, - output wire [`DCACHE_MEM_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_req_data, - output wire [`XMEM_TAG_WIDTH-1:0] mem_req_tag, + output wire [`DCACHE_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, + output wire [`DCACHE_MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_req_data, + output wire [`L1_MEM_TAG_WIDTH-1:0] mem_req_tag, input wire mem_req_ready, // Memory reponse input wire mem_rsp_valid, - input wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_rsp_data, - input wire [`XMEM_TAG_WIDTH-1:0] mem_rsp_tag, + input wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_rsp_data, + input wire [`L1_MEM_TAG_WIDTH-1:0] mem_rsp_tag, output wire mem_rsp_ready, // Status @@ -34,12 +34,12 @@ module VX_core #( VX_mem_req_if #( .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), - .TAG_WIDTH (`XMEM_TAG_WIDTH) + .TAG_WIDTH (`L1_MEM_TAG_WIDTH) ) mem_req_if(); VX_mem_rsp_if #( .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), - .TAG_WIDTH (`XMEM_TAG_WIDTH) + .TAG_WIDTH (`L1_MEM_TAG_WIDTH) ) mem_rsp_if(); assign mem_req_valid = mem_req_if.valid; diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index 733de498..3baf73f7 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -30,6 +30,8 @@ module VX_csr_data #( input wire busy ); + import fpu_types::*; + reg [`CSR_WIDTH-1:0] csr_satp; reg [`CSR_WIDTH-1:0] csr_mstatus; reg [`CSR_WIDTH-1:0] csr_medeleg; diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index fbcbba11..bd01b273 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -1,5 +1,7 @@ `include "VX_define.vh" +`ifdef DBG_PRINT_PIPELINE `include "VX_print_instr.vh" +`endif `ifdef EXT_F_ENABLE `define USED_IREG(r) \ diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index d557373c..406f4f02 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -301,6 +301,9 @@ `define _DNC_MEM_TAG_WIDTH ($clog2(`DCACHE_NUM_REQS) + `_DMEM_ADDR_RATIO_W + `DCACHE_CORE_TAG_WIDTH) `define DCACHE_MEM_TAG_WIDTH `MAX((`CLOG2(`DCACHE_NUM_BANKS) + `CLOG2(`DCACHE_MSHR_SIZE) + `NC_FLAG_BITS), `_DNC_MEM_TAG_WIDTH) +// Merged D-cache/I-cache memory tag +`define L1_MEM_TAG_WIDTH (`MAX(`ICACHE_MEM_TAG_WIDTH, `DCACHE_MEM_TAG_WIDTH) + `CLOG2(2)) + ////////////////////////// SM Configurable Knobs ////////////////////////////// // Cache ID @@ -343,9 +346,9 @@ // Memory request tag bits `define _L2_MEM_ADDR_RATIO_W $clog2(`L2_CACHE_LINE_SIZE / `L2_WORD_SIZE) -`define _L2_NC_MEM_TAG_WIDTH ($clog2(`L2_NUM_REQS) + `_L2_MEM_ADDR_RATIO_W + `XMEM_TAG_WIDTH) +`define _L2_NC_MEM_TAG_WIDTH ($clog2(`L2_NUM_REQS) + `_L2_MEM_ADDR_RATIO_W + `L1_MEM_TAG_WIDTH) `define _L2_MEM_TAG_WIDTH `MAX((`CLOG2(`L2_NUM_BANKS) + `CLOG2(`L2_MSHR_SIZE) + `NC_FLAG_BITS), `_L2_NC_MEM_TAG_WIDTH) -`define L2_MEM_TAG_WIDTH ((`L2_ENABLE) ? `_L2_MEM_TAG_WIDTH : (`XMEM_TAG_WIDTH + `CLOG2(`L2_NUM_REQS))) +`define L2_MEM_TAG_WIDTH ((`L2_ENABLE) ? `_L2_MEM_TAG_WIDTH : (`L1_MEM_TAG_WIDTH + `CLOG2(`L2_NUM_REQS))) ////////////////////////// L3cache Configurable Knobs ///////////////////////// @@ -390,9 +393,9 @@ `define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)} -// Merged D-cache/I-cache memory tag -`define XMEM_TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH + `CLOG2(2)) +/////////////////////////////////////////////////////////////////////////////// -`include "VX_types.vh" +`include "VX_fpu_types.vh" +`include "VX_gpu_types.vh" `endif diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v index d2b6f118..7b0f07cc 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.v @@ -13,7 +13,8 @@ module VX_fpu_unit #( input wire[`NUM_WARPS-1:0] csr_pending, output wire[`NUM_WARPS-1:0] pending ); - + import fpu_types::*; + `UNUSED_PARAM (CORE_ID) localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE); diff --git a/hw/rtl/VX_types.vh b/hw/rtl/VX_gpu_types.vh similarity index 51% rename from hw/rtl/VX_types.vh rename to hw/rtl/VX_gpu_types.vh index 4654daae..70537487 100644 --- a/hw/rtl/VX_types.vh +++ b/hw/rtl/VX_gpu_types.vh @@ -1,34 +1,16 @@ -`ifndef VX_TYPES -`define VX_TYPES +`ifndef VX_GPU_TYPES +`define VX_GPU_TYPES `include "VX_define.vh" -typedef struct packed { - logic is_normal; - logic is_zero; - logic is_subnormal; - logic is_inf; - logic is_nan; - logic is_quiet; - logic is_signaling; -} fp_class_t; - -typedef struct packed { - logic NV; // 4-Invalid - logic DZ; // 3-Divide by zero - logic OF; // 2-Overflow - logic UF; // 1-Underflow - logic NX; // 0-Inexact -} fflags_t; - -`define FFLAGS_BITS $bits(fflags_t) +package gpu_types; typedef struct packed { logic valid; logic [`NUM_THREADS-1:0] tmask; } gpu_tmc_t; -`define GPU_TMC_BITS (1+`NUM_THREADS) +`define GPU_TMC_BITS $bits(gpu_tmc_t) typedef struct packed { logic valid; @@ -36,7 +18,7 @@ typedef struct packed { logic [31:0] pc; } gpu_wspawn_t; -`define GPU_WSPAWN_BITS (1+`NUM_WARPS+32) +`define GPU_WSPAWN_BITS $bits(gpu_wspawn_t) typedef struct packed { logic valid; @@ -46,7 +28,7 @@ typedef struct packed { logic [31:0] pc; } gpu_split_t; -`define GPU_SPLIT_BITS (1+1+`NUM_THREADS+`NUM_THREADS+32) +`define GPU_SPLIT_BITS $bits(gpu_split_t) typedef struct packed { logic valid; @@ -54,6 +36,8 @@ typedef struct packed { logic [`NW_BITS-1:0] size_m1; } gpu_barrier_t; -`define GPU_BARRIER_BITS (1+`NB_BITS+`NW_BITS) +`define GPU_BARRIER_BITS $bits(gpu_barrier_t) + +endpackage `endif \ No newline at end of file diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v index 18e9f573..b8cd1b78 100644 --- a/hw/rtl/VX_gpu_unit.v +++ b/hw/rtl/VX_gpu_unit.v @@ -15,6 +15,7 @@ module VX_gpu_unit #( VX_warp_ctl_if.master warp_ctl_if, VX_commit_if.master gpu_commit_if ); + import gpu_types::*; `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (clk) diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index de05a60c..69c013b0 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -303,7 +303,7 @@ module VX_lsu_unit #( `SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data); `SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr); -`ifndef SYNTHESIS +`ifndef __SYNTHESIS__ reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs; wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index e9ec6deb..9331873c 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -1,7 +1,7 @@ `ifndef VX_PLATFORM `define VX_PLATFORM -`ifndef SYNTHESIS +`ifndef __SYNTHESIS__ `include "util_dpi.vh" `endif @@ -9,7 +9,7 @@ /////////////////////////////////////////////////////////////////////////////// -`ifndef SYNTHESIS +`ifndef __SYNTHESIS__ `ifndef NDEBUG `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \ @@ -29,7 +29,8 @@ /* verilator lint_off UNOPTFLAT */ \ /* verilator lint_off UNDRIVEN */ \ /* verilator lint_off DECLFILENAME */ \ - /* verilator lint_off IMPLICIT */ + /* verilator lint_off IMPLICIT */ \ + /* verilator lint_off IMPORTSTAR */ `define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ /* verilator lint_on PINCONNECTEMPTY */ \ @@ -37,7 +38,8 @@ /* verilator lint_on UNOPTFLAT */ \ /* verilator lint_on UNDRIVEN */ \ /* verilator lint_on DECLFILENAME */ \ - /* verilator lint_on IMPLICIT */ + /* verilator lint_on IMPLICIT */ \ + /* verilator lint_on IMPORTSTAR */ `define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \ localparam __``x = x; \ @@ -49,6 +51,9 @@ . x () \ /* verilator lint_on PINCONNECTEMPTY */ +`define ERROR(msg) \ + $error msg + `define ASSERT(cond, msg) \ assert(cond) else $error msg @@ -65,7 +70,7 @@ `define TRACING_ON /* verilator tracing_on */ `define TRACING_OFF /* verilator tracing_off */ -`else // SYNTHESIS +`else // __SYNTHESIS__ `define DEBUG_BLOCK(x) `define IGNORE_UNUSED_BEGIN @@ -75,13 +80,14 @@ `define UNUSED_PARAM(x) `define UNUSED_VAR(x) `define UNUSED_PIN(x) . x () +`define ERROR(msg) `define ASSERT(cond, msg) if (cond); `define STATIC_ASSERT(cond, msg) `define RUNTIME_ASSERT(cond, msg) `define TRACING_ON `define TRACING_OFF -`endif // SYNTHESIS +`endif // __SYNTHESIS__ /////////////////////////////////////////////////////////////////////////////// @@ -106,14 +112,12 @@ `define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) `define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1)))) -`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : x); +`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : (x)); -`define MIN(x, y) ((x < y) ? (x) : (y)) -`define MAX(x, y) ((x > y) ? (x) : (y)) +`define MIN(x, y) (((x) < (y)) ? (x) : (y)) +`define MAX(x, y) (((x) > (y)) ? (x) : (y)) -`define UP(x) (((x) > 0) ? x : 1) - -`define SAFE_RNG(h,l) `MAX(h,l) : l +`define UP(x) (((x) > 0) ? (x) : 1) `define RTRIM(x,s) x[$bits(x)-1:($bits(x)-s)] diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index a2ea0a68..03469568 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -30,14 +30,14 @@ module Vortex ( wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw; wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data; + wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag; wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_busy; diff --git a/hw/rtl/fp_cores/VX_fp_class.v b/hw/rtl/fp_cores/VX_fp_class.v index d30247e5..a98d51d5 100644 --- a/hw/rtl/fp_cores/VX_fp_class.v +++ b/hw/rtl/fp_cores/VX_fp_class.v @@ -1,5 +1,5 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" module VX_fp_class # ( parameter MAN_BITS = 23, diff --git a/hw/rtl/fp_cores/VX_fp_cvt.v b/hw/rtl/fp_cores/VX_fp_cvt.v index 2f435f39..733713c1 100644 --- a/hw/rtl/fp_cores/VX_fp_cvt.v +++ b/hw/rtl/fp_cores/VX_fp_cvt.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" /// Modified port of cast module from fpnew Libray /// reference: https://github.com/pulp-platform/fpnew diff --git a/hw/rtl/fp_cores/VX_fp_div.v b/hw/rtl/fp_cores/VX_fp_div.v index 163b4c0e..7bf5f75c 100644 --- a/hw/rtl/fp_cores/VX_fp_div.v +++ b/hw/rtl/fp_cores/VX_fp_div.v @@ -1,8 +1,4 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif +`include "VX_fpu_define.vh" module VX_fp_div #( parameter TAGW = 1, diff --git a/hw/rtl/fp_cores/VX_fp_fma.v b/hw/rtl/fp_cores/VX_fp_fma.v index 13ee473b..84b9653a 100644 --- a/hw/rtl/fp_cores/VX_fp_fma.v +++ b/hw/rtl/fp_cores/VX_fp_fma.v @@ -1,8 +1,4 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif +`include "VX_fpu_define.vh" module VX_fp_fma #( parameter TAGW = 1, diff --git a/hw/rtl/fp_cores/VX_fp_ncomp.v b/hw/rtl/fp_cores/VX_fp_ncomp.v index df6c6b38..17d42102 100644 --- a/hw/rtl/fp_cores/VX_fp_ncomp.v +++ b/hw/rtl/fp_cores/VX_fp_ncomp.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" /// Modified port of noncomp module from fpnew Libray /// reference: https://github.com/pulp-platform/fpnew diff --git a/hw/rtl/fp_cores/VX_fp_rounding.v b/hw/rtl/fp_cores/VX_fp_rounding.v index 654f6e8d..415dd29d 100644 --- a/hw/rtl/fp_cores/VX_fp_rounding.v +++ b/hw/rtl/fp_cores/VX_fp_rounding.v @@ -1,5 +1,4 @@ - -`include "VX_define.vh" +`include "VX_fpu_define.vh" /// Modified port of rouding module from fpnew Libray /// reference: https://github.com/pulp-platform/fpnew diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.v b/hw/rtl/fp_cores/VX_fp_sqrt.v index dc1b2bcb..97a3b35a 100644 --- a/hw/rtl/fp_cores/VX_fp_sqrt.v +++ b/hw/rtl/fp_cores/VX_fp_sqrt.v @@ -1,8 +1,4 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif +`include "VX_fpu_define.vh" module VX_fp_sqrt #( parameter TAGW = 1, diff --git a/hw/rtl/fp_cores/VX_fpu_define.vh b/hw/rtl/fp_cores/VX_fpu_define.vh new file mode 100644 index 00000000..d764e8e4 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fpu_define.vh @@ -0,0 +1,14 @@ +`ifndef VX_FPU_DEFINE +`define VX_FPU_DEFINE + +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +`IGNORE_WARNINGS_BEGIN +import fpu_types::*; +`IGNORE_WARNINGS_END + +`endif \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_dpi.v b/hw/rtl/fp_cores/VX_fpu_dpi.v index bd87485b..ec0b3573 100644 --- a/hw/rtl/fp_cores/VX_fpu_dpi.v +++ b/hw/rtl/fp_cores/VX_fpu_dpi.v @@ -1,7 +1,4 @@ -`ifndef SYNTHESIS - -`include "VX_define.vh" -`include "float_dpi.vh" +`include "VX_fpu_define.vh" module VX_fpu_dpi #( parameter TAGW = 1 @@ -410,6 +407,4 @@ module VX_fpu_dpi #( assign ready_in = per_core_ready_in[core_select]; -endmodule - -`endif \ No newline at end of file +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_fpga.v b/hw/rtl/fp_cores/VX_fpu_fpga.v index 029f8976..671f1656 100644 --- a/hw/rtl/fp_cores/VX_fpu_fpga.v +++ b/hw/rtl/fp_cores/VX_fpu_fpga.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" module VX_fpu_fpga #( parameter TAGW = 4 diff --git a/hw/rtl/fp_cores/VX_fpu_fpnew.v b/hw/rtl/fp_cores/VX_fpu_fpnew.v index 57a73bff..3711dc3b 100644 --- a/hw/rtl/fp_cores/VX_fpu_fpnew.v +++ b/hw/rtl/fp_cores/VX_fpu_fpnew.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_fpu_define.vh" `include "fpnew_pkg.sv" `include "defs_div_sqrt_mvp.sv" diff --git a/hw/rtl/fp_cores/VX_fpu_types.vh b/hw/rtl/fp_cores/VX_fpu_types.vh new file mode 100644 index 00000000..3b8999de --- /dev/null +++ b/hw/rtl/fp_cores/VX_fpu_types.vh @@ -0,0 +1,32 @@ +`ifndef VX_FPU_TYPES +`define VX_FPU_TYPES + +`include "VX_define.vh" + +package fpu_types; + +typedef struct packed { + logic is_normal; + logic is_zero; + logic is_subnormal; + logic is_inf; + logic is_nan; + logic is_quiet; + logic is_signaling; +} fp_class_t; + +`define FP_CLASS_BITS $bits(fp_class_t) + +typedef struct packed { + logic NV; // 4-Invalid + logic DZ; // 3-Divide by zero + logic OF; // 2-Overflow + logic UF; // 1-Underflow + logic NX; // 0-Inexact +} fflags_t; + +`define FFLAGS_BITS $bits(fflags_t) + +endpackage + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.v b/hw/rtl/interfaces/VX_fpu_to_csr_if.v index 865c8cfa..62fe9628 100644 --- a/hw/rtl/interfaces/VX_fpu_to_csr_if.v +++ b/hw/rtl/interfaces/VX_fpu_to_csr_if.v @@ -7,7 +7,7 @@ interface VX_fpu_to_csr_if (); wire write_enable; wire [`NW_BITS-1:0] write_wid; - fflags_t write_fflags; + fpu_types::fflags_t write_fflags; wire [`NW_BITS-1:0] read_wid; wire [`INST_FRM_BITS-1:0] read_frm; diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.v b/hw/rtl/interfaces/VX_warp_ctl_if.v index d2117941..d38d29b1 100644 --- a/hw/rtl/interfaces/VX_warp_ctl_if.v +++ b/hw/rtl/interfaces/VX_warp_ctl_if.v @@ -5,12 +5,12 @@ interface VX_warp_ctl_if (); - wire valid; - wire [`NW_BITS-1:0] wid; - gpu_tmc_t tmc; - gpu_wspawn_t wspawn; - gpu_barrier_t barrier; - gpu_split_t split; + wire valid; + wire [`NW_BITS-1:0] wid; + gpu_types::gpu_tmc_t tmc; + gpu_types::gpu_wspawn_t wspawn; + gpu_types::gpu_barrier_t barrier; + gpu_types::gpu_split_t split; modport master ( output valid, diff --git a/hw/rtl/libs/VX_bypass_buffer.v b/hw/rtl/libs/VX_bypass_buffer.v index 170c2a88..efb5517f 100644 --- a/hw/rtl/libs/VX_bypass_buffer.v +++ b/hw/rtl/libs/VX_bypass_buffer.v @@ -31,7 +31,7 @@ module VX_bypass_buffer #( buffer_valid <= 0; end if (valid_in && ~ready_out) begin - `ASSERT(!buffer_valid, "runtime error"); + `ASSERT(!buffer_valid, ("runtime error")); buffer_valid <= 1; end end diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index 7b39246f..1fa48a69 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -34,7 +34,7 @@ module VX_dp_ram #( end \ end -`ifdef SYNTHESIS +`ifdef __SYNTHESIS__ if (LUTRAM) begin if (OUT_REG) begin reg [DATAW-1:0] rdata_r; diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v index 2ed01d0d..d27ae153 100644 --- a/hw/rtl/libs/VX_sp_ram.v +++ b/hw/rtl/libs/VX_sp_ram.v @@ -33,7 +33,7 @@ module VX_sp_ram #( end \ end -`ifdef SYNTHESIS +`ifdef __SYNTHESIS__ if (LUTRAM) begin if (OUT_REG) begin reg [DATAW-1:0] rdata_r; diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.v index faca5d66..c4466f39 100644 --- a/hw/rtl/libs/VX_stream_arbiter.v +++ b/hw/rtl/libs/VX_stream_arbiter.v @@ -95,7 +95,7 @@ module VX_stream_arbiter #( .grant_onehot (sel_onehot) ); end else begin - $error ("invalid parameter"); + `ERROR(("invalid parameter")); end wire [LANES-1:0] valid_in_sel; diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/opae/vortex_afu.qsf index 1628f9d8..07e9a846 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/opae/vortex_afu.qsf @@ -5,7 +5,6 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON set_global_assignment -name VERILOG_MACRO QUARTUS -set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index 87fb09b7..8f6208dd 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -36,7 +36,6 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON set_global_assignment -name VERILOG_MACRO QUARTUS -set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON From 04249c3ee9809d8bdfdb4ece675194177c4eaf54 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 29 Sep 2021 04:48:53 -0400 Subject: [PATCH 3/6] code refactoring for Vivado compatibility --- hw/rtl/{VX_alu_unit.v => VX_alu_unit.sv} | 0 hw/rtl/{VX_cluster.v => VX_cluster.sv} | 0 hw/rtl/{VX_commit.v => VX_commit.sv} | 0 hw/rtl/{VX_core.v => VX_core.sv} | 0 hw/rtl/{VX_csr_data.v => VX_csr_data.sv} | 0 hw/rtl/{VX_csr_unit.v => VX_csr_unit.sv} | 0 hw/rtl/{VX_decode.v => VX_decode.sv} | 0 hw/rtl/{VX_execute.v => VX_execute.sv} | 0 hw/rtl/{VX_fetch.v => VX_fetch.sv} | 0 hw/rtl/{VX_fpu_unit.v => VX_fpu_unit.sv} | 0 hw/rtl/{VX_gpr_stage.v => VX_gpr_stage.sv} | 0 hw/rtl/{VX_gpu_unit.v => VX_gpu_unit.sv} | 0 hw/rtl/{VX_ibuffer.v => VX_ibuffer.sv} | 0 hw/rtl/{VX_icache_stage.v => VX_icache_stage.sv} | 0 hw/rtl/{VX_instr_demux.v => VX_instr_demux.sv} | 0 hw/rtl/{VX_ipdom_stack.v => VX_ipdom_stack.sv} | 0 hw/rtl/{VX_issue.v => VX_issue.sv} | 0 hw/rtl/{VX_lsu_unit.v => VX_lsu_unit.sv} | 0 hw/rtl/{VX_mem_arb.v => VX_mem_arb.sv} | 0 hw/rtl/{VX_mem_unit.v => VX_mem_unit.sv} | 0 hw/rtl/{VX_muldiv.v => VX_muldiv.sv} | 0 hw/rtl/{VX_pipeline.v => VX_pipeline.sv} | 0 hw/rtl/{VX_scoreboard.v => VX_scoreboard.sv} | 0 hw/rtl/{VX_smem_arb.v => VX_smem_arb.sv} | 0 hw/rtl/{VX_warp_sched.v => VX_warp_sched.sv} | 0 hw/rtl/{VX_writeback.v => VX_writeback.sv} | 0 hw/rtl/{Vortex.v => Vortex.sv} | 0 hw/rtl/{Vortex_axi.v => Vortex_axi.sv} | 0 hw/rtl/afu/{VX_avs_wrapper.v => VX_avs_wrapper.sv} | 0 hw/rtl/afu/{VX_to_mem.v => VX_to_mem.sv} | 0 hw/rtl/cache/{VX_bank.v => VX_bank.sv} | 0 hw/rtl/cache/{VX_cache.v => VX_cache.sv} | 0 hw/rtl/cache/{VX_core_req_bank_sel.v => VX_core_req_bank_sel.sv} | 0 hw/rtl/cache/{VX_core_rsp_merge.v => VX_core_rsp_merge.sv} | 0 hw/rtl/cache/{VX_data_access.v => VX_data_access.sv} | 0 hw/rtl/cache/{VX_flush_ctrl.v => VX_flush_ctrl.sv} | 0 hw/rtl/cache/{VX_miss_resrv.v => VX_miss_resrv.sv} | 0 hw/rtl/cache/{VX_nc_bypass.v => VX_nc_bypass.sv} | 0 hw/rtl/cache/{VX_shared_mem.v => VX_shared_mem.sv} | 0 hw/rtl/cache/{VX_tag_access.v => VX_tag_access.sv} | 0 hw/rtl/fp_cores/{VX_fp_class.v => VX_fp_class.sv} | 0 hw/rtl/fp_cores/{VX_fp_cvt.v => VX_fp_cvt.sv} | 0 hw/rtl/fp_cores/{VX_fp_div.v => VX_fp_div.sv} | 0 hw/rtl/fp_cores/{VX_fp_fma.v => VX_fp_fma.sv} | 0 hw/rtl/fp_cores/{VX_fp_ncomp.v => VX_fp_ncomp.sv} | 0 hw/rtl/fp_cores/{VX_fp_rounding.v => VX_fp_rounding.sv} | 0 hw/rtl/fp_cores/{VX_fp_sqrt.v => VX_fp_sqrt.sv} | 0 hw/rtl/fp_cores/{VX_fpu_dpi.v => VX_fpu_dpi.sv} | 0 hw/rtl/fp_cores/{VX_fpu_fpga.v => VX_fpu_fpga.sv} | 0 hw/rtl/fp_cores/{VX_fpu_fpnew.v => VX_fpu_fpnew.sv} | 0 hw/rtl/interfaces/{VX_alu_req_if.v => VX_alu_req_if.sv} | 0 hw/rtl/interfaces/{VX_branch_ctl_if.v => VX_branch_ctl_if.sv} | 0 hw/rtl/interfaces/{VX_cmt_to_csr_if.v => VX_cmt_to_csr_if.sv} | 0 hw/rtl/interfaces/{VX_commit_if.v => VX_commit_if.sv} | 0 hw/rtl/interfaces/{VX_csr_req_if.v => VX_csr_req_if.sv} | 0 hw/rtl/interfaces/{VX_dcache_req_if.v => VX_dcache_req_if.sv} | 0 hw/rtl/interfaces/{VX_dcache_rsp_if.v => VX_dcache_rsp_if.sv} | 0 hw/rtl/interfaces/{VX_decode_if.v => VX_decode_if.sv} | 0 hw/rtl/interfaces/{VX_fetch_to_csr_if.v => VX_fetch_to_csr_if.sv} | 0 hw/rtl/interfaces/{VX_fpu_req_if.v => VX_fpu_req_if.sv} | 0 hw/rtl/interfaces/{VX_fpu_to_csr_if.v => VX_fpu_to_csr_if.sv} | 0 hw/rtl/interfaces/{VX_gpr_req_if.v => VX_gpr_req_if.sv} | 0 hw/rtl/interfaces/{VX_gpr_rsp_if.v => VX_gpr_rsp_if.sv} | 0 hw/rtl/interfaces/{VX_gpu_req_if.v => VX_gpu_req_if.sv} | 0 hw/rtl/interfaces/{VX_ibuffer_if.v => VX_ibuffer_if.sv} | 0 hw/rtl/interfaces/{VX_icache_req_if.v => VX_icache_req_if.sv} | 0 hw/rtl/interfaces/{VX_icache_rsp_if.v => VX_icache_rsp_if.sv} | 0 hw/rtl/interfaces/{VX_ifetch_req_if.v => VX_ifetch_req_if.sv} | 0 hw/rtl/interfaces/{VX_ifetch_rsp_if.v => VX_ifetch_rsp_if.sv} | 0 hw/rtl/interfaces/{VX_join_if.v => VX_join_if.sv} | 0 hw/rtl/interfaces/{VX_lsu_req_if.v => VX_lsu_req_if.sv} | 0 hw/rtl/interfaces/{VX_mem_req_if.v => VX_mem_req_if.sv} | 0 hw/rtl/interfaces/{VX_mem_rsp_if.v => VX_mem_rsp_if.sv} | 0 hw/rtl/interfaces/{VX_perf_cache_if.v => VX_perf_cache_if.sv} | 0 hw/rtl/interfaces/{VX_perf_memsys_if.v => VX_perf_memsys_if.sv} | 0 .../interfaces/{VX_perf_pipeline_if.v => VX_perf_pipeline_if.sv} | 0 hw/rtl/interfaces/{VX_warp_ctl_if.v => VX_warp_ctl_if.sv} | 0 hw/rtl/interfaces/{VX_writeback_if.v => VX_writeback_if.sv} | 0 hw/rtl/interfaces/{VX_wstall_if.v => VX_wstall_if.sv} | 0 hw/rtl/libs/{VX_axi_adapter.v => VX_axi_adapter.sv} | 0 hw/rtl/libs/{VX_bits_insert.v => VX_bits_insert.sv} | 0 hw/rtl/libs/{VX_bits_remove.v => VX_bits_remove.sv} | 0 hw/rtl/libs/{VX_bypass_buffer.v => VX_bypass_buffer.sv} | 0 hw/rtl/libs/{VX_divider.v => VX_divider.sv} | 0 hw/rtl/libs/{VX_dp_ram.v => VX_dp_ram.sv} | 0 hw/rtl/libs/{VX_elastic_buffer.v => VX_elastic_buffer.sv} | 0 hw/rtl/libs/{VX_fair_arbiter.v => VX_fair_arbiter.sv} | 0 hw/rtl/libs/{VX_fifo_queue.v => VX_fifo_queue.sv} | 0 hw/rtl/libs/{VX_find_first.v => VX_find_first.sv} | 0 hw/rtl/libs/{VX_fixed_arbiter.v => VX_fixed_arbiter.sv} | 0 hw/rtl/libs/{VX_index_buffer.v => VX_index_buffer.sv} | 0 hw/rtl/libs/{VX_index_queue.v => VX_index_queue.sv} | 0 hw/rtl/libs/{VX_lzc.v => VX_lzc.sv} | 0 hw/rtl/libs/{VX_matrix_arbiter.v => VX_matrix_arbiter.sv} | 0 hw/rtl/libs/{VX_multiplier.v => VX_multiplier.sv} | 0 hw/rtl/libs/{VX_mux.v => VX_mux.sv} | 0 hw/rtl/libs/{VX_onehot_encoder.v => VX_onehot_encoder.sv} | 0 hw/rtl/libs/{VX_onehot_mux.v => VX_onehot_mux.sv} | 0 hw/rtl/libs/{VX_pending_size.v => VX_pending_size.sv} | 0 hw/rtl/libs/{VX_pipe_register.v => VX_pipe_register.sv} | 0 hw/rtl/libs/{VX_popcount.v => VX_popcount.sv} | 0 hw/rtl/libs/{VX_priority_encoder.v => VX_priority_encoder.sv} | 0 hw/rtl/libs/{VX_reset_relay.v => VX_reset_relay.sv} | 0 hw/rtl/libs/{VX_rr_arbiter.v => VX_rr_arbiter.sv} | 0 hw/rtl/libs/{VX_scan.v => VX_scan.sv} | 0 hw/rtl/libs/{VX_scope.v => VX_scope.sv} | 0 hw/rtl/libs/{VX_serial_div.v => VX_serial_div.sv} | 0 hw/rtl/libs/{VX_shift_register.v => VX_shift_register.sv} | 0 hw/rtl/libs/{VX_skid_buffer.v => VX_skid_buffer.sv} | 0 hw/rtl/libs/{VX_sp_ram.v => VX_sp_ram.sv} | 0 hw/rtl/libs/{VX_stream_arbiter.v => VX_stream_arbiter.sv} | 0 hw/rtl/libs/{VX_stream_demux.v => VX_stream_demux.sv} | 0 112 files changed, 0 insertions(+), 0 deletions(-) rename hw/rtl/{VX_alu_unit.v => VX_alu_unit.sv} (100%) rename hw/rtl/{VX_cluster.v => VX_cluster.sv} (100%) rename hw/rtl/{VX_commit.v => VX_commit.sv} (100%) rename hw/rtl/{VX_core.v => VX_core.sv} (100%) rename hw/rtl/{VX_csr_data.v => VX_csr_data.sv} (100%) rename hw/rtl/{VX_csr_unit.v => VX_csr_unit.sv} (100%) rename hw/rtl/{VX_decode.v => VX_decode.sv} (100%) rename hw/rtl/{VX_execute.v => VX_execute.sv} (100%) rename hw/rtl/{VX_fetch.v => VX_fetch.sv} (100%) rename hw/rtl/{VX_fpu_unit.v => VX_fpu_unit.sv} (100%) rename hw/rtl/{VX_gpr_stage.v => VX_gpr_stage.sv} (100%) rename hw/rtl/{VX_gpu_unit.v => VX_gpu_unit.sv} (100%) rename hw/rtl/{VX_ibuffer.v => VX_ibuffer.sv} (100%) rename hw/rtl/{VX_icache_stage.v => VX_icache_stage.sv} (100%) rename hw/rtl/{VX_instr_demux.v => VX_instr_demux.sv} (100%) rename hw/rtl/{VX_ipdom_stack.v => VX_ipdom_stack.sv} (100%) rename hw/rtl/{VX_issue.v => VX_issue.sv} (100%) rename hw/rtl/{VX_lsu_unit.v => VX_lsu_unit.sv} (100%) rename hw/rtl/{VX_mem_arb.v => VX_mem_arb.sv} (100%) rename hw/rtl/{VX_mem_unit.v => VX_mem_unit.sv} (100%) rename hw/rtl/{VX_muldiv.v => VX_muldiv.sv} (100%) rename hw/rtl/{VX_pipeline.v => VX_pipeline.sv} (100%) rename hw/rtl/{VX_scoreboard.v => VX_scoreboard.sv} (100%) rename hw/rtl/{VX_smem_arb.v => VX_smem_arb.sv} (100%) rename hw/rtl/{VX_warp_sched.v => VX_warp_sched.sv} (100%) rename hw/rtl/{VX_writeback.v => VX_writeback.sv} (100%) rename hw/rtl/{Vortex.v => Vortex.sv} (100%) rename hw/rtl/{Vortex_axi.v => Vortex_axi.sv} (100%) rename hw/rtl/afu/{VX_avs_wrapper.v => VX_avs_wrapper.sv} (100%) rename hw/rtl/afu/{VX_to_mem.v => VX_to_mem.sv} (100%) rename hw/rtl/cache/{VX_bank.v => VX_bank.sv} (100%) rename hw/rtl/cache/{VX_cache.v => VX_cache.sv} (100%) rename hw/rtl/cache/{VX_core_req_bank_sel.v => VX_core_req_bank_sel.sv} (100%) rename hw/rtl/cache/{VX_core_rsp_merge.v => VX_core_rsp_merge.sv} (100%) rename hw/rtl/cache/{VX_data_access.v => VX_data_access.sv} (100%) rename hw/rtl/cache/{VX_flush_ctrl.v => VX_flush_ctrl.sv} (100%) rename hw/rtl/cache/{VX_miss_resrv.v => VX_miss_resrv.sv} (100%) rename hw/rtl/cache/{VX_nc_bypass.v => VX_nc_bypass.sv} (100%) rename hw/rtl/cache/{VX_shared_mem.v => VX_shared_mem.sv} (100%) rename hw/rtl/cache/{VX_tag_access.v => VX_tag_access.sv} (100%) rename hw/rtl/fp_cores/{VX_fp_class.v => VX_fp_class.sv} (100%) rename hw/rtl/fp_cores/{VX_fp_cvt.v => VX_fp_cvt.sv} (100%) rename hw/rtl/fp_cores/{VX_fp_div.v => VX_fp_div.sv} (100%) rename hw/rtl/fp_cores/{VX_fp_fma.v => VX_fp_fma.sv} (100%) rename hw/rtl/fp_cores/{VX_fp_ncomp.v => VX_fp_ncomp.sv} (100%) rename hw/rtl/fp_cores/{VX_fp_rounding.v => VX_fp_rounding.sv} (100%) rename hw/rtl/fp_cores/{VX_fp_sqrt.v => VX_fp_sqrt.sv} (100%) rename hw/rtl/fp_cores/{VX_fpu_dpi.v => VX_fpu_dpi.sv} (100%) rename hw/rtl/fp_cores/{VX_fpu_fpga.v => VX_fpu_fpga.sv} (100%) rename hw/rtl/fp_cores/{VX_fpu_fpnew.v => VX_fpu_fpnew.sv} (100%) rename hw/rtl/interfaces/{VX_alu_req_if.v => VX_alu_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_branch_ctl_if.v => VX_branch_ctl_if.sv} (100%) rename hw/rtl/interfaces/{VX_cmt_to_csr_if.v => VX_cmt_to_csr_if.sv} (100%) rename hw/rtl/interfaces/{VX_commit_if.v => VX_commit_if.sv} (100%) rename hw/rtl/interfaces/{VX_csr_req_if.v => VX_csr_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_dcache_req_if.v => VX_dcache_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_dcache_rsp_if.v => VX_dcache_rsp_if.sv} (100%) rename hw/rtl/interfaces/{VX_decode_if.v => VX_decode_if.sv} (100%) rename hw/rtl/interfaces/{VX_fetch_to_csr_if.v => VX_fetch_to_csr_if.sv} (100%) rename hw/rtl/interfaces/{VX_fpu_req_if.v => VX_fpu_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_fpu_to_csr_if.v => VX_fpu_to_csr_if.sv} (100%) rename hw/rtl/interfaces/{VX_gpr_req_if.v => VX_gpr_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_gpr_rsp_if.v => VX_gpr_rsp_if.sv} (100%) rename hw/rtl/interfaces/{VX_gpu_req_if.v => VX_gpu_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_ibuffer_if.v => VX_ibuffer_if.sv} (100%) rename hw/rtl/interfaces/{VX_icache_req_if.v => VX_icache_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_icache_rsp_if.v => VX_icache_rsp_if.sv} (100%) rename hw/rtl/interfaces/{VX_ifetch_req_if.v => VX_ifetch_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_ifetch_rsp_if.v => VX_ifetch_rsp_if.sv} (100%) rename hw/rtl/interfaces/{VX_join_if.v => VX_join_if.sv} (100%) rename hw/rtl/interfaces/{VX_lsu_req_if.v => VX_lsu_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_mem_req_if.v => VX_mem_req_if.sv} (100%) rename hw/rtl/interfaces/{VX_mem_rsp_if.v => VX_mem_rsp_if.sv} (100%) rename hw/rtl/interfaces/{VX_perf_cache_if.v => VX_perf_cache_if.sv} (100%) rename hw/rtl/interfaces/{VX_perf_memsys_if.v => VX_perf_memsys_if.sv} (100%) rename hw/rtl/interfaces/{VX_perf_pipeline_if.v => VX_perf_pipeline_if.sv} (100%) rename hw/rtl/interfaces/{VX_warp_ctl_if.v => VX_warp_ctl_if.sv} (100%) rename hw/rtl/interfaces/{VX_writeback_if.v => VX_writeback_if.sv} (100%) rename hw/rtl/interfaces/{VX_wstall_if.v => VX_wstall_if.sv} (100%) rename hw/rtl/libs/{VX_axi_adapter.v => VX_axi_adapter.sv} (100%) rename hw/rtl/libs/{VX_bits_insert.v => VX_bits_insert.sv} (100%) rename hw/rtl/libs/{VX_bits_remove.v => VX_bits_remove.sv} (100%) rename hw/rtl/libs/{VX_bypass_buffer.v => VX_bypass_buffer.sv} (100%) rename hw/rtl/libs/{VX_divider.v => VX_divider.sv} (100%) rename hw/rtl/libs/{VX_dp_ram.v => VX_dp_ram.sv} (100%) rename hw/rtl/libs/{VX_elastic_buffer.v => VX_elastic_buffer.sv} (100%) rename hw/rtl/libs/{VX_fair_arbiter.v => VX_fair_arbiter.sv} (100%) rename hw/rtl/libs/{VX_fifo_queue.v => VX_fifo_queue.sv} (100%) rename hw/rtl/libs/{VX_find_first.v => VX_find_first.sv} (100%) rename hw/rtl/libs/{VX_fixed_arbiter.v => VX_fixed_arbiter.sv} (100%) rename hw/rtl/libs/{VX_index_buffer.v => VX_index_buffer.sv} (100%) rename hw/rtl/libs/{VX_index_queue.v => VX_index_queue.sv} (100%) rename hw/rtl/libs/{VX_lzc.v => VX_lzc.sv} (100%) rename hw/rtl/libs/{VX_matrix_arbiter.v => VX_matrix_arbiter.sv} (100%) rename hw/rtl/libs/{VX_multiplier.v => VX_multiplier.sv} (100%) rename hw/rtl/libs/{VX_mux.v => VX_mux.sv} (100%) rename hw/rtl/libs/{VX_onehot_encoder.v => VX_onehot_encoder.sv} (100%) rename hw/rtl/libs/{VX_onehot_mux.v => VX_onehot_mux.sv} (100%) rename hw/rtl/libs/{VX_pending_size.v => VX_pending_size.sv} (100%) rename hw/rtl/libs/{VX_pipe_register.v => VX_pipe_register.sv} (100%) rename hw/rtl/libs/{VX_popcount.v => VX_popcount.sv} (100%) rename hw/rtl/libs/{VX_priority_encoder.v => VX_priority_encoder.sv} (100%) rename hw/rtl/libs/{VX_reset_relay.v => VX_reset_relay.sv} (100%) rename hw/rtl/libs/{VX_rr_arbiter.v => VX_rr_arbiter.sv} (100%) rename hw/rtl/libs/{VX_scan.v => VX_scan.sv} (100%) rename hw/rtl/libs/{VX_scope.v => VX_scope.sv} (100%) rename hw/rtl/libs/{VX_serial_div.v => VX_serial_div.sv} (100%) rename hw/rtl/libs/{VX_shift_register.v => VX_shift_register.sv} (100%) rename hw/rtl/libs/{VX_skid_buffer.v => VX_skid_buffer.sv} (100%) rename hw/rtl/libs/{VX_sp_ram.v => VX_sp_ram.sv} (100%) rename hw/rtl/libs/{VX_stream_arbiter.v => VX_stream_arbiter.sv} (100%) rename hw/rtl/libs/{VX_stream_demux.v => VX_stream_demux.sv} (100%) diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.sv similarity index 100% rename from hw/rtl/VX_alu_unit.v rename to hw/rtl/VX_alu_unit.sv diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.sv similarity index 100% rename from hw/rtl/VX_cluster.v rename to hw/rtl/VX_cluster.sv diff --git a/hw/rtl/VX_commit.v b/hw/rtl/VX_commit.sv similarity index 100% rename from hw/rtl/VX_commit.v rename to hw/rtl/VX_commit.sv diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.sv similarity index 100% rename from hw/rtl/VX_core.v rename to hw/rtl/VX_core.sv diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.sv similarity index 100% rename from hw/rtl/VX_csr_data.v rename to hw/rtl/VX_csr_data.sv diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.sv similarity index 100% rename from hw/rtl/VX_csr_unit.v rename to hw/rtl/VX_csr_unit.sv diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.sv similarity index 100% rename from hw/rtl/VX_decode.v rename to hw/rtl/VX_decode.sv diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.sv similarity index 100% rename from hw/rtl/VX_execute.v rename to hw/rtl/VX_execute.sv diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.sv similarity index 100% rename from hw/rtl/VX_fetch.v rename to hw/rtl/VX_fetch.sv diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.sv similarity index 100% rename from hw/rtl/VX_fpu_unit.v rename to hw/rtl/VX_fpu_unit.sv diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.sv similarity index 100% rename from hw/rtl/VX_gpr_stage.v rename to hw/rtl/VX_gpr_stage.sv diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.sv similarity index 100% rename from hw/rtl/VX_gpu_unit.v rename to hw/rtl/VX_gpu_unit.sv diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.sv similarity index 100% rename from hw/rtl/VX_ibuffer.v rename to hw/rtl/VX_ibuffer.sv diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.sv similarity index 100% rename from hw/rtl/VX_icache_stage.v rename to hw/rtl/VX_icache_stage.sv diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.sv similarity index 100% rename from hw/rtl/VX_instr_demux.v rename to hw/rtl/VX_instr_demux.sv diff --git a/hw/rtl/VX_ipdom_stack.v b/hw/rtl/VX_ipdom_stack.sv similarity index 100% rename from hw/rtl/VX_ipdom_stack.v rename to hw/rtl/VX_ipdom_stack.sv diff --git a/hw/rtl/VX_issue.v b/hw/rtl/VX_issue.sv similarity index 100% rename from hw/rtl/VX_issue.v rename to hw/rtl/VX_issue.sv diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.sv similarity index 100% rename from hw/rtl/VX_lsu_unit.v rename to hw/rtl/VX_lsu_unit.sv diff --git a/hw/rtl/VX_mem_arb.v b/hw/rtl/VX_mem_arb.sv similarity index 100% rename from hw/rtl/VX_mem_arb.v rename to hw/rtl/VX_mem_arb.sv diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.sv similarity index 100% rename from hw/rtl/VX_mem_unit.v rename to hw/rtl/VX_mem_unit.sv diff --git a/hw/rtl/VX_muldiv.v b/hw/rtl/VX_muldiv.sv similarity index 100% rename from hw/rtl/VX_muldiv.v rename to hw/rtl/VX_muldiv.sv diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.sv similarity index 100% rename from hw/rtl/VX_pipeline.v rename to hw/rtl/VX_pipeline.sv diff --git a/hw/rtl/VX_scoreboard.v b/hw/rtl/VX_scoreboard.sv similarity index 100% rename from hw/rtl/VX_scoreboard.v rename to hw/rtl/VX_scoreboard.sv diff --git a/hw/rtl/VX_smem_arb.v b/hw/rtl/VX_smem_arb.sv similarity index 100% rename from hw/rtl/VX_smem_arb.v rename to hw/rtl/VX_smem_arb.sv diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.sv similarity index 100% rename from hw/rtl/VX_warp_sched.v rename to hw/rtl/VX_warp_sched.sv diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.sv similarity index 100% rename from hw/rtl/VX_writeback.v rename to hw/rtl/VX_writeback.sv diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.sv similarity index 100% rename from hw/rtl/Vortex.v rename to hw/rtl/Vortex.sv diff --git a/hw/rtl/Vortex_axi.v b/hw/rtl/Vortex_axi.sv similarity index 100% rename from hw/rtl/Vortex_axi.v rename to hw/rtl/Vortex_axi.sv diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.sv similarity index 100% rename from hw/rtl/afu/VX_avs_wrapper.v rename to hw/rtl/afu/VX_avs_wrapper.sv diff --git a/hw/rtl/afu/VX_to_mem.v b/hw/rtl/afu/VX_to_mem.sv similarity index 100% rename from hw/rtl/afu/VX_to_mem.v rename to hw/rtl/afu/VX_to_mem.sv diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.sv similarity index 100% rename from hw/rtl/cache/VX_bank.v rename to hw/rtl/cache/VX_bank.sv diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.sv similarity index 100% rename from hw/rtl/cache/VX_cache.v rename to hw/rtl/cache/VX_cache.sv diff --git a/hw/rtl/cache/VX_core_req_bank_sel.v b/hw/rtl/cache/VX_core_req_bank_sel.sv similarity index 100% rename from hw/rtl/cache/VX_core_req_bank_sel.v rename to hw/rtl/cache/VX_core_req_bank_sel.sv diff --git a/hw/rtl/cache/VX_core_rsp_merge.v b/hw/rtl/cache/VX_core_rsp_merge.sv similarity index 100% rename from hw/rtl/cache/VX_core_rsp_merge.v rename to hw/rtl/cache/VX_core_rsp_merge.sv diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.sv similarity index 100% rename from hw/rtl/cache/VX_data_access.v rename to hw/rtl/cache/VX_data_access.sv diff --git a/hw/rtl/cache/VX_flush_ctrl.v b/hw/rtl/cache/VX_flush_ctrl.sv similarity index 100% rename from hw/rtl/cache/VX_flush_ctrl.v rename to hw/rtl/cache/VX_flush_ctrl.sv diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.sv similarity index 100% rename from hw/rtl/cache/VX_miss_resrv.v rename to hw/rtl/cache/VX_miss_resrv.sv diff --git a/hw/rtl/cache/VX_nc_bypass.v b/hw/rtl/cache/VX_nc_bypass.sv similarity index 100% rename from hw/rtl/cache/VX_nc_bypass.v rename to hw/rtl/cache/VX_nc_bypass.sv diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.sv similarity index 100% rename from hw/rtl/cache/VX_shared_mem.v rename to hw/rtl/cache/VX_shared_mem.sv diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.sv similarity index 100% rename from hw/rtl/cache/VX_tag_access.v rename to hw/rtl/cache/VX_tag_access.sv diff --git a/hw/rtl/fp_cores/VX_fp_class.v b/hw/rtl/fp_cores/VX_fp_class.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fp_class.v rename to hw/rtl/fp_cores/VX_fp_class.sv diff --git a/hw/rtl/fp_cores/VX_fp_cvt.v b/hw/rtl/fp_cores/VX_fp_cvt.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fp_cvt.v rename to hw/rtl/fp_cores/VX_fp_cvt.sv diff --git a/hw/rtl/fp_cores/VX_fp_div.v b/hw/rtl/fp_cores/VX_fp_div.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fp_div.v rename to hw/rtl/fp_cores/VX_fp_div.sv diff --git a/hw/rtl/fp_cores/VX_fp_fma.v b/hw/rtl/fp_cores/VX_fp_fma.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fp_fma.v rename to hw/rtl/fp_cores/VX_fp_fma.sv diff --git a/hw/rtl/fp_cores/VX_fp_ncomp.v b/hw/rtl/fp_cores/VX_fp_ncomp.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fp_ncomp.v rename to hw/rtl/fp_cores/VX_fp_ncomp.sv diff --git a/hw/rtl/fp_cores/VX_fp_rounding.v b/hw/rtl/fp_cores/VX_fp_rounding.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fp_rounding.v rename to hw/rtl/fp_cores/VX_fp_rounding.sv diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.v b/hw/rtl/fp_cores/VX_fp_sqrt.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fp_sqrt.v rename to hw/rtl/fp_cores/VX_fp_sqrt.sv diff --git a/hw/rtl/fp_cores/VX_fpu_dpi.v b/hw/rtl/fp_cores/VX_fpu_dpi.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fpu_dpi.v rename to hw/rtl/fp_cores/VX_fpu_dpi.sv diff --git a/hw/rtl/fp_cores/VX_fpu_fpga.v b/hw/rtl/fp_cores/VX_fpu_fpga.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fpu_fpga.v rename to hw/rtl/fp_cores/VX_fpu_fpga.sv diff --git a/hw/rtl/fp_cores/VX_fpu_fpnew.v b/hw/rtl/fp_cores/VX_fpu_fpnew.sv similarity index 100% rename from hw/rtl/fp_cores/VX_fpu_fpnew.v rename to hw/rtl/fp_cores/VX_fpu_fpnew.sv diff --git a/hw/rtl/interfaces/VX_alu_req_if.v b/hw/rtl/interfaces/VX_alu_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_alu_req_if.v rename to hw/rtl/interfaces/VX_alu_req_if.sv diff --git a/hw/rtl/interfaces/VX_branch_ctl_if.v b/hw/rtl/interfaces/VX_branch_ctl_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_branch_ctl_if.v rename to hw/rtl/interfaces/VX_branch_ctl_if.sv diff --git a/hw/rtl/interfaces/VX_cmt_to_csr_if.v b/hw/rtl/interfaces/VX_cmt_to_csr_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_cmt_to_csr_if.v rename to hw/rtl/interfaces/VX_cmt_to_csr_if.sv diff --git a/hw/rtl/interfaces/VX_commit_if.v b/hw/rtl/interfaces/VX_commit_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_commit_if.v rename to hw/rtl/interfaces/VX_commit_if.sv diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_csr_req_if.v rename to hw/rtl/interfaces/VX_csr_req_if.sv diff --git a/hw/rtl/interfaces/VX_dcache_req_if.v b/hw/rtl/interfaces/VX_dcache_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_dcache_req_if.v rename to hw/rtl/interfaces/VX_dcache_req_if.sv diff --git a/hw/rtl/interfaces/VX_dcache_rsp_if.v b/hw/rtl/interfaces/VX_dcache_rsp_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_dcache_rsp_if.v rename to hw/rtl/interfaces/VX_dcache_rsp_if.sv diff --git a/hw/rtl/interfaces/VX_decode_if.v b/hw/rtl/interfaces/VX_decode_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_decode_if.v rename to hw/rtl/interfaces/VX_decode_if.sv diff --git a/hw/rtl/interfaces/VX_fetch_to_csr_if.v b/hw/rtl/interfaces/VX_fetch_to_csr_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_fetch_to_csr_if.v rename to hw/rtl/interfaces/VX_fetch_to_csr_if.sv diff --git a/hw/rtl/interfaces/VX_fpu_req_if.v b/hw/rtl/interfaces/VX_fpu_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_fpu_req_if.v rename to hw/rtl/interfaces/VX_fpu_req_if.sv diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.v b/hw/rtl/interfaces/VX_fpu_to_csr_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_fpu_to_csr_if.v rename to hw/rtl/interfaces/VX_fpu_to_csr_if.sv diff --git a/hw/rtl/interfaces/VX_gpr_req_if.v b/hw/rtl/interfaces/VX_gpr_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_gpr_req_if.v rename to hw/rtl/interfaces/VX_gpr_req_if.sv diff --git a/hw/rtl/interfaces/VX_gpr_rsp_if.v b/hw/rtl/interfaces/VX_gpr_rsp_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_gpr_rsp_if.v rename to hw/rtl/interfaces/VX_gpr_rsp_if.sv diff --git a/hw/rtl/interfaces/VX_gpu_req_if.v b/hw/rtl/interfaces/VX_gpu_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_gpu_req_if.v rename to hw/rtl/interfaces/VX_gpu_req_if.sv diff --git a/hw/rtl/interfaces/VX_ibuffer_if.v b/hw/rtl/interfaces/VX_ibuffer_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_ibuffer_if.v rename to hw/rtl/interfaces/VX_ibuffer_if.sv diff --git a/hw/rtl/interfaces/VX_icache_req_if.v b/hw/rtl/interfaces/VX_icache_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_icache_req_if.v rename to hw/rtl/interfaces/VX_icache_req_if.sv diff --git a/hw/rtl/interfaces/VX_icache_rsp_if.v b/hw/rtl/interfaces/VX_icache_rsp_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_icache_rsp_if.v rename to hw/rtl/interfaces/VX_icache_rsp_if.sv diff --git a/hw/rtl/interfaces/VX_ifetch_req_if.v b/hw/rtl/interfaces/VX_ifetch_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_ifetch_req_if.v rename to hw/rtl/interfaces/VX_ifetch_req_if.sv diff --git a/hw/rtl/interfaces/VX_ifetch_rsp_if.v b/hw/rtl/interfaces/VX_ifetch_rsp_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_ifetch_rsp_if.v rename to hw/rtl/interfaces/VX_ifetch_rsp_if.sv diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_join_if.v rename to hw/rtl/interfaces/VX_join_if.sv diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_lsu_req_if.v rename to hw/rtl/interfaces/VX_lsu_req_if.sv diff --git a/hw/rtl/interfaces/VX_mem_req_if.v b/hw/rtl/interfaces/VX_mem_req_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_mem_req_if.v rename to hw/rtl/interfaces/VX_mem_req_if.sv diff --git a/hw/rtl/interfaces/VX_mem_rsp_if.v b/hw/rtl/interfaces/VX_mem_rsp_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_mem_rsp_if.v rename to hw/rtl/interfaces/VX_mem_rsp_if.sv diff --git a/hw/rtl/interfaces/VX_perf_cache_if.v b/hw/rtl/interfaces/VX_perf_cache_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_perf_cache_if.v rename to hw/rtl/interfaces/VX_perf_cache_if.sv diff --git a/hw/rtl/interfaces/VX_perf_memsys_if.v b/hw/rtl/interfaces/VX_perf_memsys_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_perf_memsys_if.v rename to hw/rtl/interfaces/VX_perf_memsys_if.sv diff --git a/hw/rtl/interfaces/VX_perf_pipeline_if.v b/hw/rtl/interfaces/VX_perf_pipeline_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_perf_pipeline_if.v rename to hw/rtl/interfaces/VX_perf_pipeline_if.sv diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.v b/hw/rtl/interfaces/VX_warp_ctl_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_warp_ctl_if.v rename to hw/rtl/interfaces/VX_warp_ctl_if.sv diff --git a/hw/rtl/interfaces/VX_writeback_if.v b/hw/rtl/interfaces/VX_writeback_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_writeback_if.v rename to hw/rtl/interfaces/VX_writeback_if.sv diff --git a/hw/rtl/interfaces/VX_wstall_if.v b/hw/rtl/interfaces/VX_wstall_if.sv similarity index 100% rename from hw/rtl/interfaces/VX_wstall_if.v rename to hw/rtl/interfaces/VX_wstall_if.sv diff --git a/hw/rtl/libs/VX_axi_adapter.v b/hw/rtl/libs/VX_axi_adapter.sv similarity index 100% rename from hw/rtl/libs/VX_axi_adapter.v rename to hw/rtl/libs/VX_axi_adapter.sv diff --git a/hw/rtl/libs/VX_bits_insert.v b/hw/rtl/libs/VX_bits_insert.sv similarity index 100% rename from hw/rtl/libs/VX_bits_insert.v rename to hw/rtl/libs/VX_bits_insert.sv diff --git a/hw/rtl/libs/VX_bits_remove.v b/hw/rtl/libs/VX_bits_remove.sv similarity index 100% rename from hw/rtl/libs/VX_bits_remove.v rename to hw/rtl/libs/VX_bits_remove.sv diff --git a/hw/rtl/libs/VX_bypass_buffer.v b/hw/rtl/libs/VX_bypass_buffer.sv similarity index 100% rename from hw/rtl/libs/VX_bypass_buffer.v rename to hw/rtl/libs/VX_bypass_buffer.sv diff --git a/hw/rtl/libs/VX_divider.v b/hw/rtl/libs/VX_divider.sv similarity index 100% rename from hw/rtl/libs/VX_divider.v rename to hw/rtl/libs/VX_divider.sv diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.sv similarity index 100% rename from hw/rtl/libs/VX_dp_ram.v rename to hw/rtl/libs/VX_dp_ram.sv diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.sv similarity index 100% rename from hw/rtl/libs/VX_elastic_buffer.v rename to hw/rtl/libs/VX_elastic_buffer.sv diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.sv similarity index 100% rename from hw/rtl/libs/VX_fair_arbiter.v rename to hw/rtl/libs/VX_fair_arbiter.sv diff --git a/hw/rtl/libs/VX_fifo_queue.v b/hw/rtl/libs/VX_fifo_queue.sv similarity index 100% rename from hw/rtl/libs/VX_fifo_queue.v rename to hw/rtl/libs/VX_fifo_queue.sv diff --git a/hw/rtl/libs/VX_find_first.v b/hw/rtl/libs/VX_find_first.sv similarity index 100% rename from hw/rtl/libs/VX_find_first.v rename to hw/rtl/libs/VX_find_first.sv diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.sv similarity index 100% rename from hw/rtl/libs/VX_fixed_arbiter.v rename to hw/rtl/libs/VX_fixed_arbiter.sv diff --git a/hw/rtl/libs/VX_index_buffer.v b/hw/rtl/libs/VX_index_buffer.sv similarity index 100% rename from hw/rtl/libs/VX_index_buffer.v rename to hw/rtl/libs/VX_index_buffer.sv diff --git a/hw/rtl/libs/VX_index_queue.v b/hw/rtl/libs/VX_index_queue.sv similarity index 100% rename from hw/rtl/libs/VX_index_queue.v rename to hw/rtl/libs/VX_index_queue.sv diff --git a/hw/rtl/libs/VX_lzc.v b/hw/rtl/libs/VX_lzc.sv similarity index 100% rename from hw/rtl/libs/VX_lzc.v rename to hw/rtl/libs/VX_lzc.sv diff --git a/hw/rtl/libs/VX_matrix_arbiter.v b/hw/rtl/libs/VX_matrix_arbiter.sv similarity index 100% rename from hw/rtl/libs/VX_matrix_arbiter.v rename to hw/rtl/libs/VX_matrix_arbiter.sv diff --git a/hw/rtl/libs/VX_multiplier.v b/hw/rtl/libs/VX_multiplier.sv similarity index 100% rename from hw/rtl/libs/VX_multiplier.v rename to hw/rtl/libs/VX_multiplier.sv diff --git a/hw/rtl/libs/VX_mux.v b/hw/rtl/libs/VX_mux.sv similarity index 100% rename from hw/rtl/libs/VX_mux.v rename to hw/rtl/libs/VX_mux.sv diff --git a/hw/rtl/libs/VX_onehot_encoder.v b/hw/rtl/libs/VX_onehot_encoder.sv similarity index 100% rename from hw/rtl/libs/VX_onehot_encoder.v rename to hw/rtl/libs/VX_onehot_encoder.sv diff --git a/hw/rtl/libs/VX_onehot_mux.v b/hw/rtl/libs/VX_onehot_mux.sv similarity index 100% rename from hw/rtl/libs/VX_onehot_mux.v rename to hw/rtl/libs/VX_onehot_mux.sv diff --git a/hw/rtl/libs/VX_pending_size.v b/hw/rtl/libs/VX_pending_size.sv similarity index 100% rename from hw/rtl/libs/VX_pending_size.v rename to hw/rtl/libs/VX_pending_size.sv diff --git a/hw/rtl/libs/VX_pipe_register.v b/hw/rtl/libs/VX_pipe_register.sv similarity index 100% rename from hw/rtl/libs/VX_pipe_register.v rename to hw/rtl/libs/VX_pipe_register.sv diff --git a/hw/rtl/libs/VX_popcount.v b/hw/rtl/libs/VX_popcount.sv similarity index 100% rename from hw/rtl/libs/VX_popcount.v rename to hw/rtl/libs/VX_popcount.sv diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.sv similarity index 100% rename from hw/rtl/libs/VX_priority_encoder.v rename to hw/rtl/libs/VX_priority_encoder.sv diff --git a/hw/rtl/libs/VX_reset_relay.v b/hw/rtl/libs/VX_reset_relay.sv similarity index 100% rename from hw/rtl/libs/VX_reset_relay.v rename to hw/rtl/libs/VX_reset_relay.sv diff --git a/hw/rtl/libs/VX_rr_arbiter.v b/hw/rtl/libs/VX_rr_arbiter.sv similarity index 100% rename from hw/rtl/libs/VX_rr_arbiter.v rename to hw/rtl/libs/VX_rr_arbiter.sv diff --git a/hw/rtl/libs/VX_scan.v b/hw/rtl/libs/VX_scan.sv similarity index 100% rename from hw/rtl/libs/VX_scan.v rename to hw/rtl/libs/VX_scan.sv diff --git a/hw/rtl/libs/VX_scope.v b/hw/rtl/libs/VX_scope.sv similarity index 100% rename from hw/rtl/libs/VX_scope.v rename to hw/rtl/libs/VX_scope.sv diff --git a/hw/rtl/libs/VX_serial_div.v b/hw/rtl/libs/VX_serial_div.sv similarity index 100% rename from hw/rtl/libs/VX_serial_div.v rename to hw/rtl/libs/VX_serial_div.sv diff --git a/hw/rtl/libs/VX_shift_register.v b/hw/rtl/libs/VX_shift_register.sv similarity index 100% rename from hw/rtl/libs/VX_shift_register.v rename to hw/rtl/libs/VX_shift_register.sv diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.sv similarity index 100% rename from hw/rtl/libs/VX_skid_buffer.v rename to hw/rtl/libs/VX_skid_buffer.sv diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.sv similarity index 100% rename from hw/rtl/libs/VX_sp_ram.v rename to hw/rtl/libs/VX_sp_ram.sv diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.sv similarity index 100% rename from hw/rtl/libs/VX_stream_arbiter.v rename to hw/rtl/libs/VX_stream_arbiter.sv diff --git a/hw/rtl/libs/VX_stream_demux.v b/hw/rtl/libs/VX_stream_demux.sv similarity index 100% rename from hw/rtl/libs/VX_stream_demux.v rename to hw/rtl/libs/VX_stream_demux.sv From bbcb50ba81acaaf4ad2447f7fb88295c2913568a Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 29 Sep 2021 04:49:36 -0400 Subject: [PATCH 4/6] minor update --- hw/simulate/Makefile | 2 +- hw/syn/quartus/vortex/Makefile | 2 +- hw/syn/yosys/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 7fb0de8a..b43b0d4c 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -47,7 +47,7 @@ VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += verilator.vlt VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE) -VL_FLAGS += --cc Vortex.v --top-module $(TOP) +VL_FLAGS += --cc $(TOP) --top-module $(TOP) # FPU backend FPU_CORE ?= FPU_FPNEW diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index ff735e86..48e40608 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -1,6 +1,6 @@ PROJECT = Vortex TOP_LEVEL_ENTITY = Vortex -SRC_FILE = Vortex.v +SRC_FILE = Vortex.sv RTL_DIR = ../../../../rtl FAMILY = "Arria 10" diff --git a/hw/syn/yosys/Makefile b/hw/syn/yosys/Makefile index 0aabcef4..6ac5f6a0 100644 --- a/hw/syn/yosys/Makefile +++ b/hw/syn/yosys/Makefile @@ -1,6 +1,6 @@ PROJECT = Vortex TOP_LEVEL_ENTITY = Vortex -SRC_FILE = Vortex.v +SRC_FILE = Vortex.sv RTL_DIR = ../../rtl DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64 From 8e82ee00a02784fbe785326e174a99e52951d0d3 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 29 Sep 2021 09:32:21 -0700 Subject: [PATCH 5/6] minor update --- hw/rtl/VX_lsu_unit.sv | 2 +- hw/rtl/VX_platform.vh | 8 ++++---- hw/rtl/libs/VX_dp_ram.sv | 2 +- hw/rtl/libs/VX_sp_ram.sv | 2 +- hw/syn/opae/vortex_afu.qsf | 1 + hw/syn/quartus/Makefile | 7 ++++++- hw/syn/quartus/project.tcl | 1 + 7 files changed, 15 insertions(+), 8 deletions(-) diff --git a/hw/rtl/VX_lsu_unit.sv b/hw/rtl/VX_lsu_unit.sv index 69c013b0..de05a60c 100644 --- a/hw/rtl/VX_lsu_unit.sv +++ b/hw/rtl/VX_lsu_unit.sv @@ -303,7 +303,7 @@ module VX_lsu_unit #( `SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data); `SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr); -`ifndef __SYNTHESIS__ +`ifndef SYNTHESIS reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs; wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 9331873c..202da95c 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -1,7 +1,7 @@ `ifndef VX_PLATFORM `define VX_PLATFORM -`ifndef __SYNTHESIS__ +`ifndef SYNTHESIS `include "util_dpi.vh" `endif @@ -9,7 +9,7 @@ /////////////////////////////////////////////////////////////////////////////// -`ifndef __SYNTHESIS__ +`ifndef SYNTHESIS `ifndef NDEBUG `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \ @@ -70,7 +70,7 @@ `define TRACING_ON /* verilator tracing_on */ `define TRACING_OFF /* verilator tracing_off */ -`else // __SYNTHESIS__ +`else // SYNTHESIS `define DEBUG_BLOCK(x) `define IGNORE_UNUSED_BEGIN @@ -87,7 +87,7 @@ `define TRACING_ON `define TRACING_OFF -`endif // __SYNTHESIS__ +`endif // SYNTHESIS /////////////////////////////////////////////////////////////////////////////// diff --git a/hw/rtl/libs/VX_dp_ram.sv b/hw/rtl/libs/VX_dp_ram.sv index 1fa48a69..7b39246f 100644 --- a/hw/rtl/libs/VX_dp_ram.sv +++ b/hw/rtl/libs/VX_dp_ram.sv @@ -34,7 +34,7 @@ module VX_dp_ram #( end \ end -`ifdef __SYNTHESIS__ +`ifdef SYNTHESIS if (LUTRAM) begin if (OUT_REG) begin reg [DATAW-1:0] rdata_r; diff --git a/hw/rtl/libs/VX_sp_ram.sv b/hw/rtl/libs/VX_sp_ram.sv index d27ae153..2ed01d0d 100644 --- a/hw/rtl/libs/VX_sp_ram.sv +++ b/hw/rtl/libs/VX_sp_ram.sv @@ -33,7 +33,7 @@ module VX_sp_ram #( end \ end -`ifdef __SYNTHESIS__ +`ifdef SYNTHESIS if (LUTRAM) begin if (OUT_REG) begin reg [DATAW-1:0] rdata_r; diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/opae/vortex_afu.qsf index 07e9a846..1628f9d8 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/opae/vortex_afu.qsf @@ -5,6 +5,7 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON set_global_assignment -name VERILOG_MACRO QUARTUS +set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON diff --git a/hw/syn/quartus/Makefile b/hw/syn/quartus/Makefile index 6263ac17..662848e1 100644 --- a/hw/syn/quartus/Makefile +++ b/hw/syn/quartus/Makefile @@ -1,6 +1,11 @@ BUILD_DIR ?= build -.PHONY: unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64 +.PHONY: dogfood unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64 + +dogfood: + mkdir -p dogfood/$(BUILD_DIR) + cp dogfood/Makefile dogfood/$(BUILD_DIR) + $(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 & unittest: mkdir -p unittest/$(BUILD_DIR) diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index 8f6208dd..87fb09b7 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -36,6 +36,7 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON set_global_assignment -name VERILOG_MACRO QUARTUS +set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON From fe14a9933d4c8cdf22f9ad83ae8845950ea1d618 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 29 Sep 2021 09:32:47 -0700 Subject: [PATCH 6/6] device caps fix --- hw/rtl/afu/vortex_afu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 4801bee9..696725e2 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -94,7 +94,7 @@ localparam STATE_WIDTH = $clog2(STATE_MAX_VALUE); wire [127:0] afu_id = `AFU_ACCEL_UUID; -wire [63:0] dev_caps = {16'(`NUM_THREADS), 16'(`NUM_WARPS), 16'(`NUM_CORES), 16'(`IMPLEMENTATION_ID)}; +wire [63:0] dev_caps = {16'(`NUM_THREADS), 16'(`NUM_WARPS), 16'(`NUM_CORES * `NUM_CLUSTERS), 16'(`IMPLEMENTATION_ID)}; reg [STATE_WIDTH-1:0] state;