diff --git a/.gitmodules b/.gitmodules index 0db51e41..af1d1a47 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,9 +4,6 @@ [submodule "third_party/softfloat"] path = third_party/softfloat url = https://github.com/ucb-bar/berkeley-softfloat-3.git -[submodule "third_party/cocogfx"] - path = third_party/cocogfx - url = https://github.com/gtcasl/cocogfx.git [submodule "third_party/ramulator"] path = third_party/ramulator url = https://github.com/CMU-SAFARI/ramulator.git diff --git a/.travis.yml b/.travis.yml index 95672102..f28c770f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,21 +9,31 @@ addons: packages: - build-essential - valgrind - - verilator - - yosys - libpng-dev - libboost-serialization-dev - libstdc++6 + - hwloc -install: - # Set environments - - export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain - - export VERILATOR_ROOT=/opt/verilator - - export PATH=$VERILATOR_ROOT/bin:$PATH +install: # Install toolchain - - ci/toolchain_install.sh -all + - export TOOLDIR=$HOME/tools + - mkdir -p $TOOLDIR + - DESTDIR=$TOOLDIR ./ci/toolchain_install.sh --all + # Set environments + - export RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv-gnu-toolchain + - export LLVM_POCL=$TOOLDIR/llvm-pocl + - export LLVM_VORTEX=$TOOLDIR/llvm-vortex + - export VERILATOR_ROOT=$TOOLDIR/verilator + - export PATH=$VERILATOR_ROOT/bin:$PATH + - export SV2V_PATH=$TOOLDIR/sv2v + - export PATH=$SV2V_PATH/bin:$PATH + - export YOSYS_PATH=$TOOLDIR/yosys + - export PATH=$YOSYS_PATH/bin:$PATH + - export POCL_CC_PATH=$TOOLDIR/pocl/compiler + - export POCL_RT_PATH=$TOOLDIR/pocl/runtime # build project - - make -s + - cp -r $PWD ../build32 && cd ../build32 && make clean-all && make + - cp -r $PWD ../build64 && cd ../build64 && make clean-all && XLEN=64 RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv64-gnu-toolchain make # stages ordering stages: @@ -32,45 +42,54 @@ stages: jobs: include: - stage: test - name: coverage - script: cp -r $PWD ../build_coverage && cd ../build_coverage && ./ci/travis_run.py ./ci/regression.sh -coverage + name: unittest + script: cp -r ../build32 ../build32_unittest && cd ../build32_unittest && ./ci/travis_run.py ./ci/regression.sh --unittest - stage: test - name: coverage64 - script: cp -r $PWD ../build_coverage64 && cd ../build_coverage64 && ./ci/travis_run.py ./ci/regression64.sh -coverage + name: isa + script: cp -r ../build32 ../build32_isa && cd ../build32_isa && ./ci/travis_run.py ./ci/regression.sh --isa - stage: test - name: tex - script: cp -r $PWD ../build_tex && cd ../build_tex && ./ci/travis_run.py ./ci/regression.sh -tex + name: isa64 + script: cp -r ../build64 ../build64_isa && cd ../build64_isa && XLEN=64 RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv64-gnu-toolchain ./ci/travis_run.py ./ci/regression.sh --isa + - stage: test + name: regression + script: cp -r ../build32 ../build32_regression && cd ../build32_regression && ./ci/travis_run.py ./ci/regression.sh --regression + - stage: test + name: regression64 + script: cp -r ../build64 ../build64_regression && cd ../build64_regression && XLEN=64 RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv64-gnu-toolchain ./ci/travis_run.py ./ci/regression.sh --regression + - stage: test + name: opencl + script: cp -r ../build32 ../build32_opencl && cd ../build32_opencl && ./ci/travis_run.py ./ci/regression.sh --opencl - stage: test name: cluster - script: cp -r $PWD ../build_cluster && cd ../build_cluster && ./ci/travis_run.py ./ci/regression.sh -cluster + script: cp -r ../build32 ../build32_cluster && cd ../build32_cluster && ./ci/travis_run.py ./ci/regression.sh --cluster - stage: test name: config - script: cp -r $PWD ../build_config && cd ../build_config && ./ci/travis_run.py ./ci/regression.sh -config + script: cp -r ../build32 ../build32_config && cd ../build32_config && ./ci/travis_run.py ./ci/regression.sh --config - stage: test name: debug - script: cp -r $PWD ../build_debug && cd ../build_debug && ./ci/travis_run.py ./ci/regression.sh -debug + script: cp -r ../build32 ../build32_debug && cd ../build32_debug && ./ci/travis_run.py ./ci/regression.sh --debug - stage: test name: stress0 - script: cp -r $PWD ../build_stress0 && cd ../build_stress0 && ./ci/travis_run.py ./ci/regression.sh -stress0 + script: cp -r ../build32 ../build32_stress0 && cd ../build32_stress0 && ./ci/travis_run.py ./ci/regression.sh --stress0 - stage: test name: stress1 - script: cp -r $PWD ../build_stress1 && cd ../build_stress1 && ./ci/travis_run.py ./ci/regression.sh -stress1 + script: cp -r ../build32 ../build32_stress1 && cd ../build32_stress1 && ./ci/travis_run.py ./ci/regression.sh --stress1 + - stage: test + name: synthesis + script: cp -r ../build32 ../build32_isa && cd ../build32_isa && ./ci/travis_run.py ./ci/regression.sh --synthesis + - stage: test + name: synthesis64 + script: cp -r ../build64 ../build64_isa && cd ../build64_isa && XLEN=64 ./ci/travis_run.py ./ci/regression.sh --synthesis - stage: test name: compiler - script: cp -r $PWD ../build_compiler && cd ../build_compiler && ./ci/travis_run.py ./ci/test_compiler.sh - - stage: test - name: tex - script: cp -r $PWD ../build_tex && cd ../build_tex && ./ci/travis_run.py ./ci/regression.sh -tex - - stage: test - name: unittest - script: cp -r $PWD ../build_unittest && cd ../build_unittest && ./ci/travis_run.py ./ci/regression.sh -unittest - + script: cp -r ../build32 ../build32_compiler && cd ../build32_compiler && ./ci/travis_run.py ./ci/test_compiler.sh + after_success: # Gather code coverage - - lcov --directory driver --capture --output-file driver.cov # capture trace - - lcov --directory simx --capture --output-file simx.cov # capture trace - - lcov --list driver.cov # output coverage data for debugging - - lcov --list simx.cov # output coverage data for debugging + - lcov --directory runtime --capture --output-file runtime.cov # capture trace + - lcov --directory sim --capture --output-file sim.cov # capture trace + - lcov --list runtime.cov # output coverage data for debugging + - lcov --list sim.cov # output coverage data for debugging # Upload coverage report - - bash <(curl -s https://codecov.io/bash) -f driver.cov - - bash <(curl -s https://codecov.io/bash) -f simx.cov + - bash <(curl -s https://codecov.io/bash) -f runtime.cov + - bash <(curl -s https://codecov.io/bash) -f sim.cov diff --git a/LICENSE b/LICENSE index 63fcff77..261eeb9e 100644 --- a/LICENSE +++ b/LICENSE @@ -1,24 +1,201 @@ -Copyright (c) <2020>, -All rights reserved. + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Makefile b/Makefile index 8142a1be..39d2b1b0 100644 --- a/Makefile +++ b/Makefile @@ -2,13 +2,27 @@ all: $(MAKE) -C third_party $(MAKE) -C hw $(MAKE) -C sim - $(MAKE) -C driver + $(MAKE) -C kernel $(MAKE) -C runtime $(MAKE) -C tests clean: $(MAKE) -C hw clean $(MAKE) -C sim clean - $(MAKE) -C driver clean + $(MAKE) -C kernel clean $(MAKE) -C runtime clean - $(MAKE) -C tests clean \ No newline at end of file + $(MAKE) -C tests clean + +clean-all: + $(MAKE) -C third_party clean + $(MAKE) -C hw clean + $(MAKE) -C sim clean + $(MAKE) -C kernel clean + $(MAKE) -C runtime clean + $(MAKE) -C tests clean-all + +crtlsim: + $(MAKE) -C sim clean + +brtlsim: + $(MAKE) -C sim diff --git a/README.md b/README.md index 4d43ec9c..5a122f91 100644 --- a/README.md +++ b/README.md @@ -1,22 +1,25 @@ [![Build Status](https://travis-ci.com/vortexgpgpu/vortex.svg?branch=master)](https://travis-ci.com/vortexgpgpu/vortex) [![codecov](https://codecov.io/gh/vortexgpgpu/vortex/branch/master/graph/badge.svg)](https://codecov.io/gh/vortexgpgpu/vortex) -# Vortex OpenGPU +# Vortex GPGPU -Vortex is a full-system RISCV-based GPGPU processor. +Vortex is a full-stack open-source RISC-V GPGPU. ## Specifications -- Support RISC-V RV32IMF ISA -- Performance: - - 1024 total threads running at 250 MHz - - 128 Gflops of compute bandwidth - - 16 GB/s of memory bandwidth -- Scalability: up to 64 cores with optional L2 and L3 caches -- Software: OpenCL 1.2 Support +- Support RISC-V RV32IMAF and RV64IMAFD +- Microarchitecture: + - configurable number of cores, warps, and threads. + - configurable number of ALU, FPU, LSU, and SFU units per core. + - configurable pipeline issue width. + - optional shared memory, L1, L2, and L3 caches. +- Software: + - OpenCL 1.2 Support. - Supported FPGAs: - - Intel Arria 10 - - Intel Stratix 10 + - Altera Arria 10 + - Altera Stratix 10 + - Xilinx Alveo U50, U250, U280 + - Xilinx Versal VCK5000 ## Directory structure @@ -38,6 +41,11 @@ Vortex is a full-system RISCV-based GPGPU processor. - [LLVM](https://llvm.org/) - [RISCV-GNU-TOOLCHAIN](https://github.com/riscv-collab/riscv-gnu-toolchain) - [Verilator](https://www.veripool.org/verilator) +- [FpNew](https://github.com/pulp-platform/fpnew.git) +- [SoftFloat](https://github.com/ucb-bar/berkeley-softfloat-3.git) +- [Ramulator](https://github.com/CMU-SAFARI/ramulator.git) +- [Yosys](https://github.com/YosysHQ/yosys) +- [Sv2v](https://github.com/zachjs/sv2v) ### Install development tools $ sudo apt-get install build-essential $ sudo apt-get install git @@ -45,8 +53,19 @@ Vortex is a full-system RISCV-based GPGPU processor. $ git clone --recursive https://github.com/vortexgpgpu/vortex.git $ cd Vortex ### Install prebuilt toolchain - $ ./ci/toolchain_install.sh -all + $ ./ci/toolchain_install.sh --all + + By default, the toolchain will install to /opt folder. + You can install the toolchain to a different directory by overiding DESTDIR. + + $ DESTDIR=$TOOLDIR ./ci/toolchain_install.sh --all + $ export VORTEX_HOME=$TOOLDIR/vortex + $ export LLVM_VORTEX=$TOOLDIR/llvm-vortex + $ export LLVM_POCL=$TOOLDIR/llvm-pocl + $ export RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv-gnu-toolchain + $ export VERILATOR_ROOT=$TOOLDIR/verilator + $ export PATH=$VERILATOR_ROOT/bin:$PATH ### Build Vortex sources $ make -s ### Quick demo running vecadd OpenCL kernel on 2 cores - $ ./ci/blackbox.sh --driver=rtlsim --cores=2 --app=vecadd + $ ./ci/blackbox.sh --cores=2 --app=vecadd diff --git a/ci/blackbox.sh b/ci/blackbox.sh index 15257944..5e06ae65 100755 --- a/ci/blackbox.sh +++ b/ci/blackbox.sh @@ -1,26 +1,42 @@ #!/bin/sh +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + show_usage() { echo "Vortex BlackBox Test Driver v1.0" - echo "Usage: [[--clusters=#n] [--cores=#n] [--warps=#n] [--threads=#n] [--l2cache] [--l3cache] [[--driver=rtlsim|vlsim|simx] [--debug] [--scope] [--perf] [--app=vecadd|sgemm|basic|demo|dogfood] [--args=] [--help]]" + echo "Usage: $0 [[--clusters=#n] [--cores=#n] [--warps=#n] [--threads=#n] [--l2cache] [--l3cache] [[--driver=#name] [--app=#app] [--args=#args] [--debug=#level] [--scope] [--perf=#class] [--rebuild=0|1] [--log=logfile] [--help]]" } SCRIPT_DIR=$(dirname "$0") VORTEX_HOME=$SCRIPT_DIR/.. -DRIVER=vlsim +DRIVER=simx APP=sgemm CLUSTERS=1 CORES=1 WARPS=4 THREADS=4 -L2=0 -L3=0 +L2= +L3= DEBUG=0 +DEBUG_LEVEL=0 SCOPE=0 HAS_ARGS=0 -DEBUG_LEVEL=1 +PERF_CLASS=0 +REBUILD=2 +LOGFILE=run.log for i in "$@" do @@ -50,14 +66,15 @@ case $i in shift ;; --l2cache) - L2=1 + L2=-DL2_ENABLE shift ;; --l3cache) - L3=1 + L3=-DL3_ENABLE shift ;; - --debug) + --debug=*) + DEBUG_LEVEL=${i#*=} DEBUG=1 shift ;; @@ -66,8 +83,9 @@ case $i in CORES=1 shift ;; - --perf) + --perf=*) PERF_FLAG=-DPERF_ENABLE + PERF_CLASS=${i#*=} shift ;; --args=*) @@ -75,33 +93,37 @@ case $i in HAS_ARGS=1 shift ;; + --rebuild=*) + REBUILD=${i#*=} + shift + ;; + --log=*) + LOGFILE=${i#*=} + shift + ;; --help) show_usage exit 0 ;; *) - show_usage - exit -1 - ;; + show_usage + exit -1 + ;; esac done case $DRIVER in - rtlsim) - DRIVER_PATH=$VORTEX_HOME/driver/rtlsim - ;; - vlsim) - DRIVER_PATH=$VORTEX_HOME/driver/vlsim - ;; - asesim) - DRIVER_PATH=$VORTEX_HOME/driver/asesim - ;; - fpga) - DRIVER_PATH=$VORTEX_HOME/driver/fpga - ;; simx) - DRIVER_PATH=$VORTEX_HOME/driver/simx - DEBUG_LEVEL=3 + DRIVER_PATH=$VORTEX_HOME/runtime/simx + ;; + rtlsim) + DRIVER_PATH=$VORTEX_HOME/runtime/rtlsim + ;; + opae) + DRIVER_PATH=$VORTEX_HOME/runtime/opae + ;; + xrt) + DRIVER_PATH=$VORTEX_HOME/runtime/xrt ;; *) echo "invalid driver: $DRIVER" @@ -116,49 +138,61 @@ elif [ -d "$VORTEX_HOME/tests/regression/$APP" ]; then APP_PATH=$VORTEX_HOME/tests/regression/$APP else - echo "Application folder found: $APP" + echo "Application folder not found: $APP" exit -1 fi -CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_THREADS=$THREADS -DL2_ENABLE=$L2 -DL3_ENABLE=$L3 $PERF_FLAG $CONFIGS" +CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_THREADS=$THREADS $L2 $L3 $PERF_FLAG $CONFIGS" echo "CONFIGS=$CONFIGS" -BLACKBOX_CACHE=blackbox.$DRIVER.cache - -if [ -f "$BLACKBOX_CACHE" ] -then - LAST_CONFIGS=`cat $BLACKBOX_CACHE` -fi - -if [ "$CONFIGS+$DEBUG+$SCOPE" != "$LAST_CONFIGS" ]; +if [ $REBUILD -ne 0 ] then - make -C $DRIVER_PATH clean + BLACKBOX_CACHE=blackbox.$DRIVER.cache + if [ -f "$BLACKBOX_CACHE" ] + then + LAST_CONFIGS=`cat $BLACKBOX_CACHE` + fi + + if [ $REBUILD -eq 1 ] || [ "$CONFIGS+$DEBUG+$SCOPE" != "$LAST_CONFIGS" ]; + then + make -C $DRIVER_PATH clean > /dev/null + echo "$CONFIGS+$DEBUG+$SCOPE" > $BLACKBOX_CACHE + fi fi -echo "$CONFIGS+$DEBUG+$SCOPE" > $BLACKBOX_CACHE +# export performance monitor class identifier +export PERF_CLASS=$PERF_CLASS status=0 -if [ $DEBUG -eq 1 ] +# ensure config update +make -C $VORTEX_HOME/hw config > /dev/null + +# ensure the stub driver is present +make -C $VORTEX_HOME/runtime/stub > /dev/null + +if [ $DEBUG -ne 0 ] then + # driver initialization if [ $SCOPE -eq 1 ] then echo "running: DEBUG=$DEBUG_LEVEL SCOPE=1 CONFIGS="$CONFIGS" make -C $DRIVER_PATH" - DEBUG=$DEBUG_LEVEL SCOPE=1 CONFIGS="$CONFIGS" make -C $DRIVER_PATH + DEBUG=$DEBUG_LEVEL SCOPE=1 CONFIGS="$CONFIGS" make -C $DRIVER_PATH > /dev/null else echo "running: DEBUG=$DEBUG_LEVEL CONFIGS="$CONFIGS" make -C $DRIVER_PATH" - DEBUG=$DEBUG_LEVEL CONFIGS="$CONFIGS" make -C $DRIVER_PATH - fi + DEBUG=$DEBUG_LEVEL CONFIGS="$CONFIGS" make -C $DRIVER_PATH > /dev/null + fi + # running application if [ $HAS_ARGS -eq 1 ] then - echo "running: OPTS=$ARGS make -C $APP_PATH run-$DRIVER > run.log 2>&1" - OPTS=$ARGS make -C $APP_PATH run-$DRIVER > run.log 2>&1 + echo "running: OPTS=$ARGS make -C $APP_PATH run-$DRIVER > $LOGFILE 2>&1" + OPTS=$ARGS make -C $APP_PATH run-$DRIVER > $LOGFILE 2>&1 status=$? else - echo "running: make -C $APP_PATH run-$DRIVER > run.log 2>&1" - make -C $APP_PATH run-$DRIVER > run.log 2>&1 + echo "running: make -C $APP_PATH run-$DRIVER > $LOGFILE 2>&1" + make -C $APP_PATH run-$DRIVER > $LOGFILE 2>&1 status=$? fi @@ -167,17 +201,17 @@ then mv -f $APP_PATH/trace.vcd . fi else - echo "driver initialization..." + # driver initialization if [ $SCOPE -eq 1 ] then echo "running: SCOPE=1 CONFIGS="$CONFIGS" make -C $DRIVER_PATH" - SCOPE=1 CONFIGS="$CONFIGS" make -C $DRIVER_PATH + SCOPE=1 CONFIGS="$CONFIGS" make -C $DRIVER_PATH > /dev/null else echo "running: CONFIGS="$CONFIGS" make -C $DRIVER_PATH" - CONFIGS="$CONFIGS" make -C $DRIVER_PATH + CONFIGS="$CONFIGS" make -C $DRIVER_PATH > /dev/null fi - echo "running application..." + # running application if [ $HAS_ARGS -eq 1 ] then echo "running: OPTS=$ARGS make -C $APP_PATH run-$DRIVER" @@ -190,4 +224,4 @@ else fi fi -exit $status \ No newline at end of file +exit $status diff --git a/ci/prebuilt.sh b/ci/prebuilt.sh deleted file mode 100755 index 6b0f81e7..00000000 --- a/ci/prebuilt.sh +++ /dev/null @@ -1,73 +0,0 @@ -#!/bin/bash - -# exit when any command fails -set -e - -OS_DIR=${OS_DIR:-'ubuntu/bionic'} -SRCDIR=${SRCDIR:-'/opt'} -DESTDIR=${DESTDIR:-'.'} - -echo "OS_DIR=${OS_DIR}" -echo "SRCDIR=${SRCDIR}" -echo "DESTDIR=${DESTDIR}" - -riscv() -{ - echo "prebuilt riscv-gnu-toolchain..." - tar -C $SRCDIR -cvjf riscv-gnu-toolchain.tar.bz2 riscv-gnu-toolchain - split -b 50M riscv-gnu-toolchain.tar.bz2 "riscv-gnu-toolchain.tar.bz2.part" - mv riscv-gnu-toolchain.tar.bz2.part* $DESTDIR/riscv-gnu-toolchain/$OS_DIR - rm riscv-gnu-toolchain.tar.bz2 -} - -llvm() -{ - echo "prebuilt llvm-riscv..." - tar -C $SRCDIR -cvjf llvm-vortex1.tar.bz2 llvm-riscv - split -b 50M llvm-vortex1.tar.bz2 "llvm-vortex1.tar.bz2.part" - mv llvm-vortex1.tar.bz2.part* $DESTDIR/llvm-vortex/$OS_DIR - rm llvm-vortex1.tar.bz2 -} - -pocl() -{ - echo "prebuilt pocl..." - tar -C $SRCDIR -cvjf pocl1.tar.bz2 pocl - mv pocl1.tar.bz2 $DESTDIR/pocl/$OS_DIR -} - -verilator() -{ - echo "prebuilt verilator..." - tar -C $SRCDIR -cvjf verilator.tar.bz2 verilator - mv verilator.tar.bz2 $DESTDIR/verilator/$OS_DIR -} - -usage() -{ - echo "usage: prebuilt [[-riscv] [-llvm] [-pocl] [-verilator] [-all] [-h|--help]]" -} - -while [ "$1" != "" ]; do - case $1 in - -pocl ) pocl - ;; - -verilator ) verilator - ;; - -riscv ) riscv - ;; - -llvm ) llvm - ;; - -all ) riscv - llvm - pocl - verilator - ;; - -h | --help ) usage - exit - ;; - * ) usage - exit 1 - esac - shift -done diff --git a/ci/regression.sh b/ci/regression.sh index 37eb33b6..d1f9e30b 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -1,44 +1,102 @@ #!/bin/bash +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + # exit when any command fails set -e -# ensure build -make -s +# clear blackbox cache +rm -f blackbox.*.cache unittest() { make -C tests/unittest run } -coverage() +isa() { -echo "begin coverage tests..." +echo "begin isa tests..." -make -C tests/runtime run-rtlsim -make -C tests/riscv/isa run-rtlsim -make -C tests/regression run-vlsim -make -C tests/opencl run-vlsim -make -C tests/runtime run-simx make -C tests/riscv/isa run-simx -make -C tests/regression run-simx -make -C tests/opencl run-simx +make -C tests/riscv/isa run-rtlsim +CONFIGS="-DDPI_DISABLE" make -C tests/riscv/isa run-rtlsim -echo "coverage tests done!" +make -C sim/rtlsim clean && CONFIGS="-DFPU_FPNEW" make -C sim/rtlsim +make -C tests/riscv/isa run-rtlsim-32f + +make -C sim/rtlsim clean && CONFIGS="-DFPU_DPI" make -C sim/rtlsim +make -C tests/riscv/isa run-rtlsim-32f + +make -C sim/rtlsim clean && CONFIGS="-DFPU_DSP" make -C sim/rtlsim +make -C tests/riscv/isa run-rtlsim-32f + +if [ "$XLEN" == "64" ] +then + make -C sim/rtlsim clean && CONFIGS="-DFPU_FPNEW" make -C sim/rtlsim + make -C tests/riscv/isa run-rtlsim-64f + + make -C sim/rtlsim clean && CONFIGS="-DEXT_D_ENABLE -DFPU_FPNEW" make -C sim/rtlsim + make -C tests/riscv/isa run-rtlsim-64d || true + + make -C sim/rtlsim clean && CONFIGS="-DFPU_DPI" make -C sim/rtlsim + make -C tests/riscv/isa run-rtlsim-64f + + make -C sim/rtlsim clean && CONFIGS="-DFPU_DSP" make -C sim/rtlsim + make -C tests/riscv/isa run-rtlsim-64fx +fi + +make -C sim/rtlsim clean && make -C sim/rtlsim + +echo "isa tests done!" } -tex() +regression() { -echo "begin texture tests..." +echo "begin regression tests..." -CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=vlsim --app=tex --args="-isoccer.png -osoccer_result.png -g0" -CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=simx --app=tex --args="-isoccer.png -osoccer_result.png -g0" -CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=rtlsim --app=tex --args="-itoad.png -otoad_result.png -g1" -CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=simx --app=tex --args="-irainbow.png -orainbow_result.png -g2" -CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=rtlsim --app=tex --args="-itoad.png -otoad_result.png -g1" --perf -CONFIGS="-DEXT_TEX_ENABLE=1" ./ci/blackbox.sh --driver=simx --app=tex --args="-itoad.png -otoad_result.png -g1" --perf +make -C tests/kernel run-simx +make -C tests/kernel run-rtlsim -echo "coverage texture done!" +make -C tests/regression run-simx +make -C tests/regression run-rtlsim + +# test FPU hardware implementations +CONFIGS="-DFPU_DPI" ./ci/blackbox.sh --driver=rtlsim --app=dogfood +CONFIGS="-DFPU_DSP" ./ci/blackbox.sh --driver=rtlsim --app=dogfood +CONFIGS="-DFPU_FPNEW" ./ci/blackbox.sh --driver=rtlsim --app=dogfood + +# test local barrier +./ci/blackbox.sh --driver=simx --app=dogfood --args="-n1 -t19" +./ci/blackbox.sh --driver=rtlsim --app=dogfood --args="-n1 -t19" + +# test global barrier +CONFIGS="-DGBAR_ENABLE" ./ci/blackbox.sh --driver=simx --app=dogfood --args="-n1 -t20" --cores=2 +CONFIGS="-DGBAR_ENABLE" ./ci/blackbox.sh --driver=rtlsim --app=dogfood --args="-n1 -t20" --cores=2 + +# test FPU core + +echo "regression tests done!" +} + +opencl() +{ +echo "begin opencl tests..." + +make -C tests/opencl run-simx +make -C tests/opencl run-rtlsim + +echo "opencl tests done!" } cluster() @@ -46,23 +104,26 @@ cluster() echo "begin clustering tests..." # warp/threads configurations -./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo -./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo -./ci/blackbox.sh --driver=simx --cores=1 --warps=8 --threads=16 --app=demo +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=1 --threads=1 --app=diverge +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=2 --app=diverge +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=diverge +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=diverge +./ci/blackbox.sh --driver=simx --cores=1 --warps=1 --threads=1 --app=diverge +./ci/blackbox.sh --driver=simx --cores=1 --warps=8 --threads=16 --app=diverge # cores clustering -./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1" -./ci/blackbox.sh --driver=rtlsim --cores=4 --clusters=1 --app=demo --args="-n1" -./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1" -./ci/blackbox.sh --driver=simx --cores=4 --clusters=1 --app=demo --args="-n1" -./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=diverge --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=4 --clusters=1 --app=diverge --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=diverge --args="-n1" +./ci/blackbox.sh --driver=simx --cores=4 --clusters=1 --app=diverge --args="-n1" +./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --app=diverge --args="-n1" # L2/L3 -./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1" -./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=diverge --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=diverge --args="-n1" ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1" -./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --l2cache --app=demo --args="-n1" -./ci/blackbox.sh --driver=simx --cores=4 --clusters=4 --l2cache --l3cache --app=demo --args="-n1" +./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --l2cache --app=diverge --args="-n1" +./ci/blackbox.sh --driver=simx --cores=4 --clusters=4 --l2cache --l3cache --app=diverge --args="-n1" echo "clustering tests done!" } @@ -71,11 +132,22 @@ debug() { echo "begin debugging tests..." -./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --perf --app=demo --args="-n1" -./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --perf --app=demo --args="-n1" -./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --debug --app=demo --args="-n1" -./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --debug --app=demo --args="-n1" -./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1" +# test CSV trace generation +make -C sim/simx clean && DEBUG=3 make -C sim/simx +make -C sim/rtlsim clean && DEBUG=3 CONFIGS="-DGPR_RESET" make -C sim/rtlsim +make -C tests/riscv/isa run-simx-32im > run_simx.log +make -C tests/riscv/isa run-rtlsim-32im > run_rtlsim.log +./ci/trace_csv.py -trtlsim run_rtlsim.log -otrace_rtlsim.csv +./ci/trace_csv.py -tsimx run_simx.log -otrace_simx.csv +diff trace_rtlsim.csv trace_simx.csv +make -C sim/simx clean && make -C sim/simx +make -C sim/rtlsim clean && make -C sim/rtlsim + +./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --perf=1 --app=demo --args="-n1" +./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --perf=1 --app=demo --args="-n1" +./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --debug=1 --app=demo --args="-n1" +./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --debug=1 --app=demo --args="-n1" +./ci/blackbox.sh --driver=opae --cores=1 --scope --app=basic --args="-t0 -n1" echo "debugging tests done!" } @@ -84,51 +156,77 @@ config() { echo "begin configuration tests..." +# disable DPI +CONFIGS="-DDPI_DISABLE -DFPU_FPNEW" ./ci/blackbox.sh --driver=rtlsim --app=dogfood +CONFIGS="-DDPI_DISABLE -DFPU_FPNEW" ./ci/blackbox.sh --driver=opae --app=dogfood + +# issue width +CONFIGS="-DISSUE_WIDTH=1" ./ci/blackbox.sh --driver=rtlsim --app=diverge +CONFIGS="-DISSUE_WIDTH=2" ./ci/blackbox.sh --driver=rtlsim --app=diverge +CONFIGS="-DISSUE_WIDTH=1" ./ci/blackbox.sh --driver=simx --app=diverge +CONFIGS="-DISSUE_WIDTH=2" ./ci/blackbox.sh --driver=simx --app=diverge + +# dispatch size +CONFIGS="-DNUM_ALU_BLOCK=1 -DNUM_ALU_LANES=1" ./ci/blackbox.sh --driver=rtlsim --app=diverge +CONFIGS="-DNUM_ALU_BLOCK=2 -DNUM_ALU_LANES=2" ./ci/blackbox.sh --driver=rtlsim --app=diverge +CONFIGS="-DNUM_ALU_BLOCK=1 -DNUM_ALU_LANES=1" ./ci/blackbox.sh --driver=simx --app=diverge +CONFIGS="-DNUM_ALU_BLOCK=2 -DNUM_ALU_LANES=2" ./ci/blackbox.sh --driver=simx --app=diverge + +# FPU scaling +CONFIGS="-DNUM_ALU_BLOCK=4 -DNUM_FPU_LANES=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemm +CONFIGS="-DNUM_ALU_BLOCK=2 -DNUM_FPU_LANES=4" ./ci/blackbox.sh --driver=rtlsim --app=sgemm +CONFIGS="-DNUM_ALU_BLOCK=4 -DNUM_FPU_LANES=4" ./ci/blackbox.sh --driver=rtlsim --app=sgemm + +# custom program startup address +make -C tests/regression/dogfood clean-all +STARTUP_ADDR=0x40000000 make -C tests/regression/dogfood +CONFIGS="-DSTARTUP_ADDR=0x40000000" ./ci/blackbox.sh --driver=simx --app=dogfood +CONFIGS="-DSTARTUP_ADDR=0x40000000" ./ci/blackbox.sh --driver=rtlsim --app=dogfood +make -C tests/regression/dogfood clean-all +make -C tests/regression/dogfood + # disabling M extension -CONFIGS=-DEXT_M_DISABLE ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext +CONFIGS="-DEXT_M_DISABLE" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext # disabling F extension -CONFIGS=-DEXT_F_DISABLE ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext -CONFIGS=-DEXT_F_DISABLE ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext --perf -CONFIGS=-DEXT_F_DISABLE ./ci/blackbox.sh --driver=simx --cores=1 --app=no_mf_ext --perf +CONFIGS="-DEXT_F_DISABLE" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext +CONFIGS="-DEXT_F_DISABLE" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_mf_ext --perf=1 +CONFIGS="-DEXT_F_DISABLE" ./ci/blackbox.sh --driver=simx --cores=1 --app=no_mf_ext --perf=1 # disable shared memory -CONFIGS=-DSM_ENABLE=0 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_smem -CONFIGS=-DSM_ENABLE=0 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_smem --perf -CONFIGS=-DSM_ENABLE=0 ./ci/blackbox.sh --driver=simx --cores=1 --app=no_smem --perf +CONFIGS="-DSM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_smem +CONFIGS="-DSM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=no_smem --perf=1 +CONFIGS="-DSM_DISABLE" ./ci/blackbox.sh --driver=simx --cores=1 --app=no_smem --perf=1 -# using Default FPU core -FPU_CORE=FPU_DEFAULT ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=dogfood +# disable L1 cache +CONFIGS="-DL1_DISABLE -DSM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemm +CONFIGS="-DDCACHE_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemm -# using FPNEW FPU core -FPU_CORE=FPU_FPNEW ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=dogfood +# multiple L1 caches per cluster +CONFIGS="-DNUM_DCACHES=2 -DNUM_ICACHES=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemm --cores=8 --warps=1 --threads=2 -# using AXI bus +# test AXI bus AXI_BUS=1 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo # adjust l1 block size to match l2 -CONFIGS="-DL1_BLOCK_SIZE=64" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr --args="-n1" +CONFIGS="-DL1_LINE_SIZE=64" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr --args="-n1" # test cache banking -CONFIGS="-DDNUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr -CONFIGS="-DDNUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr -CONFIGS="-DDNUM_BANKS=2" ./ci/blackbox.sh --driver=simx --cores=1 --app=io_addr - -# test cache multi-porting -CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr -CONFIGS="-DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo --debug --args="-n1" -CONFIGS="-DL2_NUM_PORTS=2 -DDNUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr -CONFIGS="-DL2_NUM_PORTS=4 -DDNUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=4 --l2cache --app=io_addr -CONFIGS="-DL2_NUM_PORTS=4 -DDNUM_PORTS=4" ./ci/blackbox.sh --driver=simx --cores=4 --l2cache --app=io_addr +CONFIGS="-DSMEM_NUM_BANKS=4 -DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --app=sgemm +CONFIGS="-DSMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemm +CONFIGS="-DSMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=sgemm +CONFIGS="-DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm +CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm +CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --cores=1 --app=sgemm # test 128-bit MEM block -CONFIGS=-DMEM_BLOCK_SIZE=16 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo +CONFIGS="-DMEM_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=opae --cores=1 --app=demo # test single-bank DRAM -CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo +CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=opae --cores=1 --app=demo # test 27-bit DRAM address -CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo +CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=opae --cores=1 --app=demo echo "configuration tests done!" } @@ -138,14 +236,9 @@ stress0() echo "begin stress0 tests..." # test verilator reset values -CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm -CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=sgemm -FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood -FPU_CORE=FPU_DEFAULT CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood -CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr -CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr -CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --app=printf -CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --app=printf +CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood +CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr +CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=opae --app=printf echo "stress0 tests done!" } @@ -154,51 +247,75 @@ stress1() { echo "begin stress1 tests..." -./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256" +./ci/blackbox.sh --driver=rtlsim --app=sgemm --args="-n128" --l2cache echo "stress1 tests done!" } -usage() +synthesis() { - echo "usage: regression [-unittest] [-coverage] [-tex] [-cluster] [-debug] [-config] [-stress[#n]] [-all] [-h|--help]" +echo "begin synthesis tests..." + +PREFIX=build_base make -C hw/syn/yosys clean +PREFIX=build_base CONFIGS="-DDPI_DISABLE -DEXT_F_DISABLE" make -C hw/syn/yosys elaborate + +echo "synthesis tests done!" } +show_usage() +{ + echo "Vortex Regression Test" + echo "Usage: $0 [--unittest] [--isa] [--regression] [--opencl] [--cluster] [--debug] [--config] [--stress[#n]] [--synthesis] [--all] [--h|--help]" +} + +start=$SECONDS + while [ "$1" != "" ]; do case $1 in - -unittest ) unittest + --unittest ) unittest ;; - -coverage ) coverage + --isa ) isa ;; - -tex ) tex + --regression ) regression ;; - -cluster ) cluster + --opencl ) opencl ;; - -debug ) debug + --cluster ) cluster ;; - -config ) config + --debug ) debug ;; - -stress0 ) stress0 + --config ) config ;; - -stress1 ) stress1 + --stress0 ) stress0 ;; - -stress ) stress0 + --stress1 ) stress1 + ;; + --stress ) stress0 stress1 ;; - -all ) unittest - coverage - tex + --synthesis ) synthesis + ;; + --all ) unittest + isa + regression + opencl cluster debug config stress0 stress1 + synthesis ;; - -h | --help ) usage + -h | --help ) show_usage exit ;; - * ) usage + * ) show_usage exit 1 esac shift -done \ No newline at end of file +done + +echo "Regression completed!" + +duration=$(( SECONDS - start )) +awk -v t=$duration 'BEGIN{t=int(t*1000); printf "Elapsed Time: %d:%02d:%02d\n", t/3600000, t/60000%60, t/1000%60}' diff --git a/ci/regression64.sh b/ci/regression64.sh deleted file mode 100755 index 3c22d5cb..00000000 --- a/ci/regression64.sh +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/bash - -# exit when any command fails -set -e - -# ensure build -make -s - -coverage() -{ -echo "begin coverage tests..." - -make -C sim/simx clean -XLEN=64 make -C sim/simx -XLEN=64 make -C tests/riscv/isa run-simx - -echo "coverage tests done!" -} - -usage() -{ - echo "usage: regression [-coverage] [-all] [-h|--help]" -} - -while [ "$1" != "" ]; do - case $1 in - -coverage ) coverage - ;; - -all ) coverage - ;; - -h | --help ) usage - exit - ;; - * ) usage - exit 1 - esac - shift -done \ No newline at end of file diff --git a/ci/test_compiler.sh b/ci/test_compiler.sh index 07445af4..a270a060 100755 --- a/ci/test_compiler.sh +++ b/ci/test_compiler.sh @@ -1,30 +1,31 @@ #!/bin/bash +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + # exit when any command fails set -e -# ensure build -make -s - # clear POCL cache rm -rf ~/.cache/pocl -# rebuild runtime -make -C runtime clean -make -C runtime +# force rebuild test kernels +make -C tests clean-all -# rebuild drivers -make -C driver clean -make -C driver +# ensure build +make -s -# rebuild runtime tests -make -C tests/runtime clean -make -C tests/runtime - -# rebuild regression tests -make -C tests/regression clean-all -make -C tests/regression - -# rebuild opencl tests -make -C tests/opencl clean-all -make -C tests/opencl \ No newline at end of file +# run tests +make -C tests/kernel run-simx +make -C tests/regression run-simx +make -C tests/opencl run-simx \ No newline at end of file diff --git a/ci/toolchain_install.sh b/ci/toolchain_install.sh index b83f15ca..69c20327 100755 --- a/ci/toolchain_install.sh +++ b/ci/toolchain_install.sh @@ -1,5 +1,18 @@ #!/bin/bash +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + # exit when any command fails set -e @@ -7,91 +20,166 @@ REPOSITORY=https://github.com/vortexgpgpu/vortex-toolchain-prebuilt/raw/master DESTDIR="${DESTDIR:=/opt}" +OS="${OS:=ubuntu/bionic}" + riscv() { - for x in {a..j} + case $OS in + "centos/7") parts=$(eval echo {a..h}) ;; + *) parts=$(eval echo {a..j}) ;; + esac + rm -f riscv-gnu-toolchain.tar.bz2.parta* + for x in $parts do - wget $REPOSITORY/riscv-gnu-toolchain/ubuntu/bionic/riscv-gnu-toolchain.tar.bz2.parta$x + wget $REPOSITORY/riscv-gnu-toolchain/$OS/riscv-gnu-toolchain.tar.bz2.parta$x done cat riscv-gnu-toolchain.tar.bz2.parta* > riscv-gnu-toolchain.tar.bz2 tar -xvf riscv-gnu-toolchain.tar.bz2 - rm -f riscv-gnu-toolchain.tar.bz2* cp -r riscv-gnu-toolchain $DESTDIR + rm -f riscv-gnu-toolchain.tar.bz2* rm -rf riscv-gnu-toolchain } riscv64() { - for x in {a..j} + case $OS in + "centos/7") parts=$(eval echo {a..h}) ;; + *) parts=$(eval echo {a..j}) ;; + esac + rm -f riscv64-gnu-toolchain.tar.bz2.parta* + for x in $parts do - wget $REPOSITORY/riscv64-gnu-toolchain/ubuntu/bionic/riscv64-gnu-toolchain.tar.bz2.parta$x + wget $REPOSITORY/riscv64-gnu-toolchain/$OS/riscv64-gnu-toolchain.tar.bz2.parta$x done cat riscv64-gnu-toolchain.tar.bz2.parta* > riscv64-gnu-toolchain.tar.bz2 tar -xvf riscv64-gnu-toolchain.tar.bz2 - rm -f riscv64-gnu-toolchain.tar.bz2* cp -r riscv64-gnu-toolchain $DESTDIR + rm -f riscv64-gnu-toolchain.tar.bz2* rm -rf riscv64-gnu-toolchain } -llvm() +llvm-vortex() { - for x in {a..b} + case $OS in + "centos/7") parts=$(eval echo {a..b}) ;; + *) parts=$(eval echo {a..b}) ;; + esac + echo $parts + rm -f llvm-vortex.tar.bz2.parta* + for x in $parts do - wget $REPOSITORY/llvm-vortex/ubuntu/bionic/llvm-vortex1.tar.bz2.parta$x + wget $REPOSITORY/llvm-vortex/$OS/llvm-vortex.tar.bz2.parta$x done - cat llvm-vortex1.tar.bz2.parta* > llvm-vortex1.tar.bz2 - tar -xvf llvm-vortex1.tar.bz2 - rm -f llvm-vortex1.tar.bz2* - cp -r llvm-riscv $DESTDIR - rm -rf llvm-riscv + cat llvm-vortex.tar.bz2.parta* > llvm-vortex.tar.bz2 + tar -xvf llvm-vortex.tar.bz2 + cp -r llvm-vortex $DESTDIR + rm -f llvm-vortex.tar.bz2* + rm -rf llvm-vortex +} + +llvm-pocl() +{ + case $OS in + "centos/7") parts=$(eval echo {a..b}) ;; + *) parts=$(eval echo {a..b}) ;; + esac + echo $parts + rm -f llvm-pocl.tar.bz2.parta* + for x in $parts + do + wget $REPOSITORY/llvm-pocl/$OS/llvm-pocl.tar.bz2.parta$x + done + cat llvm-pocl.tar.bz2.parta* > llvm-pocl.tar.bz2 + tar -xvf llvm-pocl.tar.bz2 + cp -r llvm-pocl $DESTDIR + rm -f llvm-pocl.tar.bz2* + rm -rf llvm-pocl } pocl() { - wget $REPOSITORY/pocl/ubuntu/bionic/pocl1.tar.bz2 - tar -xvf pocl1.tar.bz2 - rm -f pocl1.tar.bz2 + wget $REPOSITORY/pocl/$OS/pocl.tar.bz2 + tar -xvf pocl.tar.bz2 + rm -f pocl.tar.bz2 cp -r pocl $DESTDIR rm -rf pocl } verilator() { - wget $REPOSITORY/verilator/ubuntu/bionic/verilator.tar.bz2 + wget $REPOSITORY/verilator/$OS/verilator.tar.bz2 tar -xvf verilator.tar.bz2 - rm -f verilator.tar.bz2 cp -r verilator $DESTDIR + rm -f verilator.tar.bz2 rm -rf verilator } -usage() +sv2v() { - echo "usage: toolchain_install [[-riscv] [-riscv64] [-llvm] [-pocl] [-verilator] [-all] [-h|--help]]" + wget $REPOSITORY/sv2v/$OS/sv2v.tar.bz2 + tar -xvf sv2v.tar.bz2 + rm -f sv2v.tar.bz2 + cp -r sv2v $DESTDIR + rm -rf sv2v +} + +yosys() +{ + case $OS in + "centos/7") parts=$(eval echo {a..c}) ;; + *) parts=$(eval echo {a..c}) ;; + esac + echo $parts + rm -f yosys.tar.bz2.parta* + for x in $parts + do + wget $REPOSITORY/yosys/$OS/yosys.tar.bz2.parta$x + done + cat yosys.tar.bz2.parta* > yosys.tar.bz2 + tar -xvf yosys.tar.bz2 + cp -r yosys $DESTDIR + rm -f yosys.tar.bz2* + rm -rf yosys +} + +show_usage() +{ + echo "Install Pre-built Vortex Toolchain" + echo "Usage: $0 [[--riscv] [--riscv64] [--llvm-vortex] [--llvm-pocl] [--pocl] [--verilator] [--sv2v] [--yosys] [--all] [-h|--help]]" } while [ "$1" != "" ]; do case $1 in - -pocl ) pocl + --pocl ) pocl ;; - -verilator ) verilator - ;; - -riscv ) riscv - ;; - -riscv64 ) riscv64 - ;; - -llvm ) llvm + --verilator ) verilator ;; - -all ) riscv - riscv64 - llvm - pocl - verilator - ;; - -h | --help ) usage - exit - ;; - * ) usage - exit 1 + --riscv ) riscv + ;; + --riscv64 ) riscv64 + ;; + --llvm-vortex ) llvm-vortex + ;; + --llvm-pocl ) llvm-pocl + ;; + --sv2v ) sv2v + ;; + --yosys ) yosys + ;; + --all ) riscv + riscv64 + llvm-vortex + llvm-pocl + pocl + verilator + sv2v + yosys + ;; + -h | --help ) show_usage + exit + ;; + * ) show_usage + exit 1 esac shift done \ No newline at end of file diff --git a/ci/toolchain_prebuilt.sh b/ci/toolchain_prebuilt.sh new file mode 100755 index 00000000..acd5fb3f --- /dev/null +++ b/ci/toolchain_prebuilt.sh @@ -0,0 +1,133 @@ +#!/bin/bash + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# exit when any command fails +set -e + +OS_DIR=${OS_DIR:-'ubuntu/bionic'} +SRCDIR=${SRCDIR:-'/opt'} +DESTDIR=${DESTDIR:-'.'} + +echo "OS_DIR=${OS_DIR}" +echo "SRCDIR=${SRCDIR}" +echo "DESTDIR=${DESTDIR}" + +riscv() +{ + echo "prebuilt riscv-gnu-toolchain..." + tar -C $SRCDIR -cvjf riscv-gnu-toolchain.tar.bz2 riscv-gnu-toolchain + split -b 50M riscv-gnu-toolchain.tar.bz2 "riscv-gnu-toolchain.tar.bz2.part" + mv riscv-gnu-toolchain.tar.bz2.part* $DESTDIR/riscv-gnu-toolchain/$OS_DIR + rm riscv-gnu-toolchain.tar.bz2 +} + +riscv64() +{ + echo "prebuilt riscv64-gnu-toolchain..." + tar -C $SRCDIR -cvjf riscv64-gnu-toolchain.tar.bz2 riscv64-gnu-toolchain + split -b 50M riscv64-gnu-toolchain.tar.bz2 "riscv64-gnu-toolchain.tar.bz2.part" + mv riscv64-gnu-toolchain.tar.bz2.part* $DESTDIR/riscv64-gnu-toolchain/$OS_DIR + rm riscv64-gnu-toolchain.tar.bz2 +} + +llvm-vortex() +{ + echo "prebuilt llvm-vortex..." + tar -C $SRCDIR -cvjf llvm-vortex.tar.bz2 llvm-vortex + split -b 50M llvm-vortex.tar.bz2 "llvm-vortex.tar.bz2.part" + mv llvm-vortex.tar.bz2.part* $DESTDIR/llvm-vortex/$OS_DIR + rm llvm-vortex.tar.bz2 +} + +llvm-pocl() +{ + echo "prebuilt llvm-pocl..." + tar -C $SRCDIR -cvjf llvm-pocl.tar.bz2 llvm-pocl + split -b 50M llvm-pocl.tar.bz2 "llvm-pocl.tar.bz2.part" + mv llvm-pocl.tar.bz2.part* $DESTDIR/llvm-pocl/$OS_DIR + rm llvm-pocl.tar.bz2 +} + +pocl() +{ + echo "prebuilt pocl..." + tar -C $SRCDIR -cvjf pocl.tar.bz2 pocl + mv pocl.tar.bz2 $DESTDIR/pocl/$OS_DIR +} + +verilator() +{ + echo "prebuilt verilator..." + tar -C $SRCDIR -cvjf verilator.tar.bz2 verilator + mv verilator.tar.bz2 $DESTDIR/verilator/$OS_DIR +} + +sv2v() +{ + echo "prebuilt sv2v..." + tar -C $SRCDIR -cvjf sv2v.tar.bz2 sv2v + mv sv2v.tar.bz2 $DESTDIR/sv2v/$OS_DIR +} + +yosys() +{ + echo "prebuilt yosys..." + tar -C $SRCDIR -cvjf yosys.tar.bz2 yosys + split -b 50M yosys.tar.bz2 "yosys.tar.bz2.part" + mv yosys.tar.bz2.part* $DESTDIR/yosys/$OS_DIR + rm yosys.tar.bz2 +} + +show_usage() +{ + echo "Setup Pre-built Vortex Toolchain" + echo "Usage: $0 [[--riscv] [--llvm-vortex] [--llvm-pocl] [--pocl] [--verilator] [--sv2v] [-yosys] [--all] [-h|--help]]" +} + +while [ "$1" != "" ]; do + case $1 in + --pocl ) pocl + ;; + --verilator ) verilator + ;; + --riscv ) riscv + ;; + --riscv64 ) riscv64 + ;; + --llvm-vortex ) llvm-vortex + ;; + --llvm-pocl ) llvm-pocl + ;; + --sv2v ) sv2v + ;; + --yosys ) yosys + ;; + --all ) riscv + riscv64 + llvm-vortex + llvm-pocl + pocl + verilator + sv2v + yosys + ;; + -h | --help ) show_usage + exit + ;; + * ) show_usage + exit 1 + esac + shift +done diff --git a/ci/trace_csv.py b/ci/trace_csv.py new file mode 100755 index 00000000..2fe7e712 --- /dev/null +++ b/ci/trace_csv.py @@ -0,0 +1,245 @@ +#!/usr/bin/env python3 + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import sys +import argparse +import csv +import re + +def parse_args(): + parser = argparse.ArgumentParser(description='CPU trace log to CSV format converter.') + parser.add_argument('-t', '--type', default='simx', help='log type (rtlsim or simx)') + parser.add_argument('-o', '--csv', default='trace.csv', help='Output CSV file') + parser.add_argument('log', help='Input log file') + return parser.parse_args() + +def parse_simx(log_filename): + pc_pattern = r"PC=(0x[0-9a-fA-F]+)" + instr_pattern = r"Instr (0x[0-9a-fA-F]+):" + opcode_pattern = r"Instr 0x[0-9a-fA-F]+: ([0-9a-zA-Z_\.]+)" + core_id_pattern = r"cid=(\d+)" + warp_id_pattern = r"wid=(\d+)" + tmask_pattern = r"tmask=(\d+)" + operands_pattern = r"Src\d+ Reg: (.+)" + destination_pattern = r"Dest Reg: (.+)" + uuid_pattern = r"#(\d+)" + entries = [] + with open(log_filename, 'r') as log_file: + instr_data = None + for lineno, line in enumerate(log_file, start=1): + if line.startswith("DEBUG Fetch:"): + if instr_data: + entries.append(instr_data) + instr_data = {} + instr_data["lineno"] = lineno + instr_data["PC"] = re.search(pc_pattern, line).group(1) + instr_data["core_id"] = re.search(core_id_pattern, line).group(1) + instr_data["warp_id"] = re.search(warp_id_pattern, line).group(1) + instr_data["tmask"] = re.search(tmask_pattern, line).group(1) + instr_data["uuid"] = re.search(uuid_pattern, line).group(1) + elif line.startswith("DEBUG Instr"): + instr_data["instr"] = re.search(instr_pattern, line).group(1) + instr_data["opcode"] = re.search(opcode_pattern, line).group(1) + elif line.startswith("DEBUG Src"): + src_reg = re.search(operands_pattern, line).group(1) + instr_data["operands"] = (instr_data["operands"] + ', ' + src_reg) if 'operands' in instr_data else src_reg + elif line.startswith("DEBUG Dest"): + instr_data["destination"] = re.search(destination_pattern, line).group(1) + if instr_data: + entries.append(instr_data) + return entries + +def reverse_binary(bin_str): + return bin_str[::-1] + +def bin_to_array(bin_str): + return [int(bit) for bit in bin_str] + +def append_reg(text, value, sep): + if sep: + text += ", " + ivalue = int(value) + if (ivalue >= 32): + text += "f" + str(ivalue % 32) + else: + text += "x" + value + sep = True + return text, sep + +def append_imm(text, value, sep): + if sep: + text += ", " + text += value + sep = True + return text, sep + +def append_value(text, reg, value, tmask_arr, sep): + text, sep = append_reg(text, reg, sep) + text += "={" + for i in range(len(tmask_arr)): + if i != 0: + text += ", " + if tmask_arr[i]: + text += value[i] + else: + text +="-" + text += "}" + return text, sep + +def parse_rtlsim(log_filename): + line_pattern = r"\d+: core(\d+)-(decode|issue|commit)" + pc_pattern = r"PC=(0x[0-9a-fA-F]+)" + instr_pattern = r"instr=(0x[0-9a-fA-F]+)" + ex_pattern = r"ex=([a-zA-Z]+)" + op_pattern = r"op=([\?0-9a-zA-Z_\.]+)" + warp_id_pattern = r"wid=(\d+)" + tmask_pattern = r"tmask=(\d+)" + wb_pattern = r"wb=(\d)" + opds_pattern = r"opds=(\d+)" + use_imm_pattern = r"use_imm=(\d)" + imm_pattern = r"imm=(0x[0-9a-fA-F]+)" + rd_pattern = r"rd=(\d+)" + rs1_pattern = r"rs1=(\d+)" + rs2_pattern = r"rs2=(\d+)" + rs3_pattern = r"rs3=(\d+)" + rs1_data_pattern = r"rs1_data=\{(.+?)\}" + rs2_data_pattern = r"rs2_data=\{(.+?)\}" + rs3_data_pattern = r"rs3_data=\{(.+?)\}" + rd_data_pattern = r"data=\{(.+?)\}" + eop_pattern = r"eop=(\d)" + uuid_pattern = r"#(\d+)" + entries = [] + with open(log_filename, 'r') as log_file: + instr_data = {} + for lineno, line in enumerate(log_file, start=1): + line_match = re.search(line_pattern, line) + if line_match: + PC = re.search(pc_pattern, line).group(1) + warp_id = re.search(warp_id_pattern, line).group(1) + tmask = re.search(tmask_pattern, line).group(1) + uuid = re.search(uuid_pattern, line).group(1) + core_id = line_match.group(1) + stage = line_match.group(2) + if stage == "decode": + trace = {} + trace["uuid"] = uuid + trace["PC"] = PC + trace["core_id"] = core_id + trace["warp_id"] = warp_id + trace["tmask"] = reverse_binary(tmask) + trace["instr"] = re.search(instr_pattern, line).group(1) + trace["opcode"] = re.search(op_pattern, line).group(1) + trace["opds"] = bin_to_array(re.search(opds_pattern, line).group(1)) + trace["rd"] = re.search(rd_pattern, line).group(1) + trace["rs1"] = re.search(rs1_pattern, line).group(1) + trace["rs2"] = re.search(rs2_pattern, line).group(1) + trace["rs3"] = re.search(rs3_pattern, line).group(1) + trace["use_imm"] = re.search(use_imm_pattern, line).group(1) == "1" + trace["imm"] = re.search(imm_pattern, line).group(1) + instr_data[uuid] = trace + elif stage == "issue": + if uuid in instr_data: + trace = instr_data[uuid] + trace["lineno"] = lineno + opds = trace["opds"] + if opds[1]: + trace["rs1_data"] = re.search(rs1_data_pattern, line).group(1).split(', ')[::-1] + if opds[2]: + trace["rs2_data"] = re.search(rs2_data_pattern, line).group(1).split(', ')[::-1] + if opds[3]: + trace["rs3_data"] = re.search(rs3_data_pattern, line).group(1).split(', ')[::-1] + trace["issued"] = True + instr_data[uuid] = trace + elif stage == "commit": + if uuid in instr_data: + trace = instr_data[uuid] + if "issued" in trace: + opds = trace["opds"] + dst_tmask_arr = bin_to_array(tmask)[::-1] + wb = re.search(wb_pattern, line).group(1) == "1" + if wb: + rd_data = re.search(rd_data_pattern, line).group(1).split(', ')[::-1] + if 'rd_data' in trace: + merged_rd_data = trace['rd_data'] + for i in range(len(dst_tmask_arr)): + if dst_tmask_arr[i] == 1: + merged_rd_data[i] = rd_data[i] + trace['rd_data'] = merged_rd_data + else: + trace['rd_data'] = rd_data + instr_data[uuid] = trace + eop = re.search(eop_pattern, line).group(1) == "1" + if eop: + tmask_arr = bin_to_array(trace["tmask"]) + destination = '' + if wb: + destination, sep = append_value(destination, trace["rd"], trace['rd_data'], tmask_arr, False) + del trace['rd_data'] + trace["destination"] = destination + operands = '' + sep = False + if opds[1]: + operands, sep = append_value(operands, trace["rs1"], trace["rs1_data"], tmask_arr, sep) + del trace["rs1_data"] + if opds[2]: + operands, sep = append_value(operands, trace["rs2"], trace["rs2_data"], tmask_arr, sep) + del trace["rs2_data"] + if opds[3]: + operands, sep = append_value(operands, trace["rs3"], trace["rs3_data"], tmask_arr, sep) + del trace["rs3_data"] + trace["operands"] = operands + del trace["opds"] + del trace["rd"] + del trace["rs1"] + del trace["rs2"] + del trace["rs3"] + del trace["use_imm"] + del trace["imm"] + del trace["issued"] + del instr_data[uuid] + entries.append(trace) + return entries + +def write_csv(log_filename, csv_filename, log_type): + entries = None + + # parse log file + if log_type == "rtlsim": + entries = parse_rtlsim(log_filename) + elif log_type == "simx": + entries = parse_simx(log_filename) + else: + print('Error: invalid log type') + sys.exit() + + # sort entries by uuid + entries.sort(key=lambda x: (int(x['core_id']), int(x['warp_id']), int(x['lineno']))) + for entry in entries: + del entry['lineno'] + + # write to CSV + with open(csv_filename, 'w', newline='') as csv_file: + fieldnames = ["uuid", "PC", "opcode", "instr", "core_id", "warp_id", "tmask", "operands", "destination"] + writer = csv.DictWriter(csv_file, fieldnames=fieldnames) + writer.writeheader() + for entry in entries: + writer.writerow(entry) + +def main(): + args = parse_args() + write_csv(args.log, args.csv, args.type) + +if __name__ == "__main__": + main() diff --git a/ci/travis_run.py b/ci/travis_run.py index 8b524314..eaa85275 100755 --- a/ci/travis_run.py +++ b/ci/travis_run.py @@ -1,4 +1,18 @@ #!/usr/bin/env python + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + import sys import time import threading diff --git a/docs/cache_subsystem.md b/docs/cache_subsystem.md index 1c03a326..4bfc0ded 100644 --- a/docs/cache_subsystem.md +++ b/docs/cache_subsystem.md @@ -40,9 +40,9 @@ VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/c - Core Response Merge - Cache accesses one line at a time. As a result, each request may not come back in the same response. This module tries to recombine the responses by thread ID. -### VX_bank.v +### VX_cache_bank.v -VX_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory. +VX_cache_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory. ![Image of Vortex Cache Bank](./assets/img/vortex_bank.png) diff --git a/docs/codebase.md b/docs/codebase.md index 5a33920f..b1d939c4 100644 --- a/docs/codebase.md +++ b/docs/codebase.md @@ -3,38 +3,39 @@ The directory/file layout of the Vortex codebase is as followed: - `hw`: - - `rtl`: hardware rtl sources - - `cache`: cache subsystem code - - `fp_cores`: floating point unit code + - `rtl`: hardware rtl sources + - `core`: core pipeline + - `cache`: cache subsystem + - `mem`: memory subsystem + - `fpu`: floating point unit - `interfaces`: interfaces for inter-module communication - - `libs`: general-purpose RTL modules + - `libs`: general-purpose RTL modules - `syn`: synthesis directory - - `opae`: OPAE synthesis scripts - - `quartus`: Quartus synthesis scripts + - `altera`: Altera synthesis scripts + - `xilinx`: Xilinx synthesis scripts - `synopsys`: Synopsys synthesis scripts - `modelsim`: Modelsim synthesis scripts - `yosys`: Yosys synthesis scripts - `unit_tests`: unit tests for some hardware components -- `driver`: host drivers repository +- `runtime`: host runtime software APIs - `include`: Vortex driver public headers - `stub`: Vortex stub driver library - - `fpga`: software driver that uses Intel OPAE FPGA - - `asesim`: software driver that uses Intel ASE simulator - - `vlsim`: software driver that uses vlsim simulator + - `opae`: software driver that uses Intel OPAE API with device targets=fpga|asesim|opaesim + - `xrt`: software driver that uses Xilinx XRT API with device targets=hw|hw_emu|sw_emu - `rtlsim`: software driver that uses rtlsim simulator - `simx`: software driver that uses simX simulator -- `runtime`: kernel runtime software +- `kernel`: GPU kernel software APIs - `include`: Vortex runtime public headers - `linker`: linker file for compiling kernels - `src`: runtime implementation - `sim`: - - `vlsim`: AFU RTL simulator + - `opaesim`: Intel OPAE AFU RTL simulator - `rtlsim`: processor RTL simulator - `simX`: cycle approximate simulator for vortex - `tests`: tests repository. - - `runtime`: runtime tests - - `regression`: regression tests - - `riscv`: RISC-V standard tests + - `riscv`: RISC-V conformance tests + - `kernel`: kernel tests + - `regression`: regression tests - `opencl`: opencl benchmarks and tests - `ci`: continuous integration scripts - `miscs`: miscellaneous resources. diff --git a/docs/debugging.md b/docs/debugging.md index befae5dc..7dbe0896 100644 --- a/docs/debugging.md +++ b/docs/debugging.md @@ -1,29 +1,37 @@ -# Debugging Vortex Hardware +# Debugging Vortex GPU + +## Testing changes to the RTL or simulator GPU driver. + +The Blackbox utility script will not pick up your changes if the h/w configuration is the same as during teh last run. +To force the utility to build the driver, you need pass the --rebuild=1 option when running tests. +Using --rebuild=0 will prevent the rebuild even if the h/w configuration is different from last run. + + $ ./ci/blackbox.sh --driver=simx --app=demo --rebuild=1 ## SimX Debugging SimX cycle-approximate simulator allows faster debugging of Vortex kernels' execution. -The recommended method to enable debugging is to pass the `--debug` flag to `blackbox` tool when running a program. +The recommended method to enable debugging is to pass the `--debug=` flag to `blackbox` tool when running a program. // Running demo program on SimX in debug mode - $ ./ci/blackbox.sh --driver=simx --app=demo --debug + $ ./ci/blackbox.sh --driver=simx --app=demo --debug=1 -A debug trace `run.log` is generated in the current directory during the program execution. The trace includes important states of the simulated processor (decoded instruction, register states, pipeline states, etc..). You can increase the verbosity level of the trace by changing the `DEBUG_LEVEL` variable to a value [1-5] (default is 3). +A debug trace `run.log` is generated in the current directory during the program execution. The trace includes important states of the simulated processor (decoded instruction, register states, pipeline states, etc..). You can increase the verbosity of the trace by changing the debug level. - // Using SimX in debug mode with verbose level 4 - $ CONFIGS=-DDEBUG_LEVEL=4 ./ci/blackbox.sh --driver=simx --app=demo --debug + // Using SimX in debug mode with verbose level 3 + $ ./ci/blackbox.sh --driver=simx --app=demo --debug=3 ## RTL Debugging -To debug the processor RTL, you need to use VLSIM or RTLSIM driver. VLSIM simulates the full processor including the AFU command processor (using `/rtl/afu/vortex_afu.sv` as top module). RTLSIM simulates the Vortex processor only (using `/rtl/Vortex.v` as top module). +To debug the processor RTL, you need to use VLSIM or RTLSIM driver. VLSIM simulates the full processor including the AFU command processor (using `/rtl/afu/opae/vortex_afu.sv` as top module). RTLSIM simulates the Vortex processor only (using `/rtl/Vortex.v` as top module). The recommended method to enable debugging is to pass the `--debug` flag to `blackbox` tool when running a program. - // Running demo program on vlsim in debug mode - $ ./ci/blackbox.sh --driver=vlsim --app=demo --debug + // Running demo program on the opae simulator in debug mode + $ TARGET=opaesim ./ci/blackbox.sh --driver=opae --app=demo --debug=1 // Running demo program on rtlsim in debug mode - $ ./ci/blackbox.sh --driver=rtlsim --app=demo --debug + $ ./ci/blackbox.sh --driver=rtlsim --app=demo --debug=1 A debug trace `run.log` is generated in the current directory during the program execution. The trace includes important states of the simulated processor (memory, caches, pipeline, stalls, etc..). A waveform trace `trace.vcd` is also generated in the current directory during the program execution. You can visualize the waveform trace using any tool that can open VCD files (Modelsim, Quartus, Vivado, etc..). [GTKwave] (http://gtkwave.sourceforge.net) is a great open-source scope analyzer that also works with VCD files. @@ -32,7 +40,7 @@ A debug trace `run.log` is generated in the current directory during the program Debugging the FPGA directly may be necessary to investigate runtime bugs that the RTL simulation cannot catch. We have implemented an in-house scope analyzer for Vortex that works when the FPGA is running. To enable the FPGA scope analyzer, the FPGA bitstream should be built using `SCOPE=1` flag & cd /hw/syn/opae - $ CONFIGS=-DSCOPE=1 make fpga-4c + $ CONFIGS="-DSCOPE=1" TARGET=fpga make When running the program on the FPGA, you need to pass the `--scope` flag to the `blackbox` tool. @@ -40,4 +48,18 @@ When running the program on the FPGA, you need to pass the `--scope` flag to the $ ./ci/blackbox.sh --driver=fpga --app=demo --scope -A waveform trace `trace.vcd` will be generated in the current directory during the program execution. This trace includes a limited set of signals that are defined in `/hw/scripts/scope.json`. You can expand your signals' selection by updating the json file. \ No newline at end of file +A waveform trace `trace.vcd` will be generated in the current directory during the program execution. This trace includes a limited set of signals that are defined in `/hw/scripts/scope.json`. You can expand your signals' selection by updating the json file. + +## Analyzing Vortex trace log + +When debugging Vortex RTL or SimX Simulator, reading the trace run.log file can be overwhelming when the trace gets really large. +We provide a trace sanitizer tool under ./hw/scripts/trace_csv.py that you can use to convert the large trace into a CSV file containing all the instructions that executed with their source and destination operands. + + $ ./ci/blackbox.sh --driver=rtlsim --app=demo --debug=3 --log=run_rtlsim.log + $ ./ci/trace_csv.py -trtlsim run_rtlsim.log -otrace_rtlsim.csv + + $ ./ci/blackbox.sh --driver=simx --app=demo --debug=3 --log=run_simx.log + $ ./ci/trace_csv.py -tsimx run_simx.log -otrace_simx.csv + +The first column in the CSV trace is UUID (universal unique identifier) of the instruction and the content is sorted by the UUID. You can use the UUID to trace the same instruction running on either the RTL hw or SimX simulator. +This can be very effective if you want to use SimX to debugging your RTL hardware by comparing CSV traces. \ No newline at end of file diff --git a/docs/execute_opencl_on_vortex.md b/docs/execute_opencl_on_vortex.md deleted file mode 100644 index 96f9e4b4..00000000 --- a/docs/execute_opencl_on_vortex.md +++ /dev/null @@ -1,128 +0,0 @@ -# Execute OpenCL on Vortex backend - -## Requirements -- [Vortex](https://github.com/vortexgpgpu/vortex) -- [POCL for Vortex](https://github.com/vortexgpgpu/pocl) -- [riscv-toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain) -- [llvm-riscv](https://github.com/llvm-mirror/llvm) - -For installation, please see [Build Instructions](../README.md) for more details. - -**For Ubuntu18.04 users, you can directly download pre-build toolchains with [toolchain_install.sh](https://github.com/vortexgpgpu/vortex/blob/master/ci/toolchain_install.sh) script.** -```bash -# please modify the DESTDIR variable in the script before execution -bash toolchain_install.sh -all -``` -Assuming we have installed all dependencies in `/opt` path, we can get the following environment: -```bash -tree -L 2 /opt -''' -/opt/ -├── llvm-riscv -│ ├── bin -│ ├── include -│ ├── lib -│ ├── libexec -│ └── share -├── pocl -│ ├── compiler -│ └── runtime -├── riscv-gnu-toolchain -│ ├── bin -│ ├── drops -│ ├── include -│ ├── lib -│ ├── libexec -│ ├── riscv32-unknown-elf -│ ├── share -│ └── var -└── verilator - ├── bin - ├── examples - ├── include - ├── verilator-config.cmake - └── verilator-config-version.cmake -''' -``` -## Execute OpenCL on Vortex -In this tutorial, we show the example of executing a vecadd programs on SIMX backend. -To execute a OpenCL program on Vortex, we have the following steps: -- Compile the [OpenCL kernels](https://github.com/vortexgpgpu/vortex/blob/master/tests/opencl/vecadd/kernel.cl) into risc-v binary by POCL compiler. -- Compile the [OpenCL host](https://github.com/vortexgpgpu/vortex/blob/master/tests/opencl/vecadd/main.cc) and link with Vortex driver(```-lvortex```). -- Execute the compiled host programs on a backend. - -Thus, we can write a Makefile as following: -```Makefile -LLVM_PREFIX ?= /opt/llvm-riscv -RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain -SYSROOT ?= $(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf -POCL_CC_PATH ?= /opt/pocl/compiler -POCL_RT_PATH ?= /opt/pocl/runtime - -OPTS ?= -n64 - -# please edit these two variable to your environment -VORTEX_DRV_PATH ?= $(realpath ../../../driver) -VORTEX_RT_PATH ?= $(realpath ../../../runtime) - -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" -K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" - -CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors - -CXXFLAGS += -Wno-deprecated-declarations -Wno-unused-parameter - -CXXFLAGS += -I$(POCL_RT_PATH)/include - -LDFLAGS += -L$(POCL_RT_PATH)/lib -L$(VORTEX_DRV_PATH)/stub -lOpenCL -lvortex - -PROJECT = vecadd - -SRCS = main.cc - -all: $(PROJECT) kernel.pocl - -kernel.pocl: kernel.cl - LLVM_PREFIX=$(LLVM_PREFIX) POCL_DEBUG=all LD_LIBRARY_PATH=$(LLVM_PREFIX)/lib:$(POCL_CC_PATH)/lib $(POCL_CC_PATH)/bin/poclcc -LLCFLAGS $(K_LLCFLAGS) -CFLAGS $(K_CFLAGS) -LDFLAGS $(K_LDFLAGS) -o kernel.pocl kernel.cl - -$(PROJECT): $(SRCS) - $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ - -run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) - -run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) - -run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) - -run-simx: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) - -run-rtlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) - -.depend: $(SRCS) - $(CXX) $(CXXFLAGS) -MM $^ > .depend; - -clean: - rm -rf $(PROJECT) *.o .depend - -clean-all: clean - rm -rf *.pocl *.dump - -ifneq ($(MAKECMDGOALS),clean) - -include .depend -endif -``` - -First, build the host program. -```bash -make all -``` -If we want to execute on SIMX, we can execute the command below. -```bash -make run-simx -``` diff --git a/docs/fpga_setup.md b/docs/fpga_setup.md index 741ac03a..61ff481f 100644 --- a/docs/fpga_setup.md +++ b/docs/fpga_setup.md @@ -17,22 +17,16 @@ OPAE Build ------------------ The FPGA has to following configuration options: -- 1 core fpga (fpga-1c) -- 2 cores fpga (fpga-2c) -- 4 cores fpga (fpga-4c) -- 8 cores fpga (fpga-8c) -- 16 cores fpga (fpga-16c) -- 32 cores fpga (fpga-32c) -- 64 cores fpga (fpga-64c) +- DEVICE_FAMILY=arria10 | stratix10 +- NUM_CORES=#n Command line: - $ cd hw/syn/opae - $ make fpga-c + $ cd hw/syn/altera/opae + $ PREFIX=test1 TARGET=fpga NUM_CORES=4 make -Example: `make fpga-4c` - -A new folder (ex: `build_fpga_4c`) will be created and the build will start and take ~30-480 min to complete. +A new folder (ex: `test1_xxx_4c`) will be created and the build will start and take ~30-480 min to complete. +Setting TARGET=ase will build the project for simulation using Intel ASE. OPAE Build Configuration @@ -45,35 +39,32 @@ The hardware configuration file `/hw/rtl/VX_config.vh` defines all the hardware You configure the syntesis build from the command line: - $ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make fpga-4c + $ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make OPAE Build Progress ------------------- You could check the last 10 lines in the build log for possible errors until build completion. - $ tail -n 10 ./build_fpga_c/build.log + $ tail -n 10 /build.log Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs. $ ps -u - If the build fails and you need to restart it, clean up the build folder using the following command: - $ make clean-fpga-c - -Example: `make clean-fpga-4c` + $ make clean The file `vortex_afu.gbs` should exist when the build is done: - $ ls -lsa ./build_fpga_c/vortex_afu.gbs + $ ls -lsa /vortex_afu.gbs Signing the bitstream and Programming the FPGA ---------------------------------------------- - $ cd ./build_fpga_c + $ cd $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs $ fpgasupdate vortex_afu_unsigned_ssl.gbs diff --git a/docs/index.md b/docs/index.md index f7544b03..19bbfa4d 100644 --- a/docs/index.md +++ b/docs/index.md @@ -11,7 +11,6 @@ - [Debugging](debugging.md) - [Useful Links](references.md) - ## Installation - Refer to the build instructions in [README](../README.md). @@ -22,9 +21,11 @@ Running Vortex simulators with different configurations: - Run basic driver test with rtlsim driver and Vortex config of 2 clusters, 2 cores, 2 warps, 4 threads $ ./ci/blackbox.sh --driver=rtlsim --clusters=2 --cores=2 --warps=2 --threads=4 --app=basic -- Run demo driver test with vlsim driver and Vortex config of 1 clusters, 4 cores, 4 warps, 2 threads - $ ./ci/blackbox.sh --driver=vlsim --clusters=1 --cores=4 --warps=4 --threads=2 --app=demo +- Run demo driver test with opae driver and Vortex config of 1 clusters, 4 cores, 4 warps, 2 threads + + $ ./ci/blackbox.sh --driver=opae --clusters=1 --cores=4 --warps=4 --threads=2 --app=demo + - Run dogfood driver test with simx driver and Vortex config of 4 cluster, 4 cores, 8 warps, 6 threads $ ./ci/blackbox.sh --driver=simx --clusters=4 --cores=4 --warps=8 --threads=6 --app=dogfood \ No newline at end of file diff --git a/docs/simulation.md b/docs/simulation.md index e6ac9e0c..3861b3a7 100644 --- a/docs/simulation.md +++ b/docs/simulation.md @@ -10,7 +10,7 @@ SimX is a C++ cycle-level in-house simulator developed for Vortex. The relevant ### FGPA Simulation -The current target FPGA for simulation is the Arria10 Intel Accelerator Card v1.0. The guide to build the fpga with specific configurations is located [here.](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/FPGA_Startup_Guide.md) +The current target FPGA for simulation is the Arria10 Intel Accelerator Card v1.0. The guide to build the fpga with specific configurations is located [here.](fpga_setup.md) ### How to Test @@ -22,15 +22,15 @@ Running tests under specific drivers (rtlsim,simx,fpga) is done using the script - *Threads* - used to specify the number of threads (smallest unit of computation) within a configuration. - *L2cache* - used to enable the shard l2cache among the Vortex cores. - *L3cache* - used to enable the shared l3cache among the Vortex clusters. -- *Driver* - used to specify which driver to run the Vortex simulation (either rtlsim, vlsim, fpga, or simx). +- *Driver* - used to specify which driver to run the Vortex simulation (either rtlsim, opae, xrt, simx). - *Debug* - used to enable debug mode for the Vortex simulation. - *Perf* - used to enable the detailed performance counters within the Vortex simulation. - *App* - used to specify which test/benchmark to run in the Vortex simulation. The main choices are vecadd, sgemm, basic, demo, and dogfood. Other tests/benchmarks are located in the `/benchmarks/opencl` folder though not all of them work wit the current version of Vortex. - *Args* - used to pass additional arguments to the application. -Example use of command line arguments: Run the sgemm benchmark using the vlsim driver with a Vortex configuration of 1 cluster, 4 cores, 4 warps, and 4 threads. +Example use of command line arguments: Run the sgemm benchmark using the opae driver with a Vortex configuration of 1 cluster, 4 cores, 4 warps, and 4 threads. - $ ./ci/blackbox.sh --clusters=1 --cores=4 --warps=4 --threads=4 --driver=vlsim --app=sgemm + $ ./ci/blackbox.sh --clusters=1 --cores=4 --warps=4 --threads=4 --driver=opae --app=sgemm Output from terminal: ``` diff --git a/docs/testing.md b/docs/testing.md new file mode 100644 index 00000000..552008f3 --- /dev/null +++ b/docs/testing.md @@ -0,0 +1,33 @@ +# Testing + +## Running a Vortex application + +The framework provides a utility script: blakcbox.sh under the /ci/ folder for executing applications in the tests tree. +You can query the commandline options of the tool using: + + $ ./ci/blakcbox.sh --help + +To execute sgemm test program on the simx driver and passing "-n10" as argument to sgemm: + + $ ./ci/blakcbox.sh --driver=simx --app=sgemm --args="-n10" + +You can execute the same application of a GPU architecture with 2 cores: + + $ ./ci/blakcbox.sh --core=2 --driver=simx --app=sgemm --args="-n10" + +When excuting, Blackbox needs to recompile the driver if the desired architecture changes. +It tracks the latest configuration in a file under the current directory blackbox..cache. +To avoid having to rebuild the driver all the time, Blackbox checks if the latest cached configuration matches the current. + +## Running Benchmarks + +The Vortex test suite is located under the /test/ folder +You can execute the default regression suite by running the following commands at the root folder. + + $ make -C tests/regression run-simx + $ make -C tests/regression run-rtlsim + +You can execute the default opncl suite by running the following commands at the root folder. + + $ make -C tests/opencl run-simx + $ make -C tests/opencl run-rtlsim \ No newline at end of file diff --git a/driver/Makefile b/driver/Makefile deleted file mode 100644 index 8899c0cc..00000000 --- a/driver/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -all: stub rtlsim simx vlsim - -stub: - $(MAKE) -C stub - -fpga: - $(MAKE) -C fpga - -asesim: - $(MAKE) -C asesim - -vlsim: - $(MAKE) -C vlsim - -rtlsim: - $(MAKE) -C rtlsim - -simx: - $(MAKE) -C simx - -clean: - $(MAKE) clean -C stub - $(MAKE) clean -C fpga - $(MAKE) clean -C asesim - $(MAKE) clean -C vlsim - $(MAKE) clean -C rtlsim - $(MAKE) clean -C simx - -.PHONY: all stub fpga asesim vlsim rtlsim simx clean \ No newline at end of file diff --git a/driver/asesim/Makefile b/driver/asesim/Makefile deleted file mode 100644 index a85b4908..00000000 --- a/driver/asesim/Makefile +++ /dev/null @@ -1,73 +0,0 @@ -OPAE_HOME ?= /tools/opae/1.4.0 - -RTL_DIR=../../hw/rtl - -SCRIPT_DIR=../../hw/scripts - -OPAE_SYN_DIR=../../hw/syn/opae - -CXXFLAGS += -std=c++11 -Wall -Wextra -pedantic -Wfatal-errors - -CXXFLAGS += -I. -I../include -I../../hw -I$(OPAE_HOME)/include -I$(OPAE_SYN_DIR) - -LDFLAGS += -L$(OPAE_HOME)/lib -luuid -lopae-c-ase - -# stack execution protection -LDFLAGS +=-z noexecstack - -# data relocation and projection -LDFLAGS +=-z relro -z now - -# stack buffer overrun detection -CXXFLAGS +=-fstack-protector - -# Position independent code -CXXFLAGS += -fPIC - -# Add external configuration -CXXFLAGS += $(CONFIGS) - -# Dump perf stats -CXXFLAGS += -DDUMP_PERF_STATS - -LDFLAGS += -shared - -PROJECT = libvortex.so - -SRCS = ../common/opae.cpp ../common/vx_utils.cpp - -# Debugigng -ifdef DEBUG - CXXFLAGS += -g -O0 -else - CXXFLAGS += -O2 -DNDEBUG -endif - -# Enable scope analyzer -ifdef SCOPE - CXXFLAGS += -DSCOPE - SRCS += ../common/vx_scope.cpp - SCOPE_H = scope-defs.h -endif - -# Enable perf counters -ifdef PERF - CXXFLAGS += -DPERF_ENABLE -endif - -all: $(PROJECT) - -$(OPAE_SYN_DIR)/vortex_afu.h: - $(MAKE) -C $(OPAE_SYN_DIR) vortex_afu.h - -scope-defs.h: $(SCRIPT_DIR)/scope.json - $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json - -# generate scope data -scope: scope-defs.h - -$(PROJECT): $(SRCS) $(OPAE_SYN_DIR)/vortex_afu.h $(SCOPE_H) - $(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) -o $(PROJECT) - -clean: - rm -rf $(PROJECT) *.o scope-defs.h \ No newline at end of file diff --git a/driver/common/opae.cpp b/driver/common/opae.cpp deleted file mode 100755 index 4246f4fb..00000000 --- a/driver/common/opae.cpp +++ /dev/null @@ -1,535 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(USE_FPGA) || defined(USE_ASE) -#include -#include -#elif defined(USE_VLSIM) -#include -#endif - -#include "vx_utils.h" -#include "vx_malloc.h" -#include -#include -#include "vortex_afu.h" - -#ifdef SCOPE -#include "vx_scope.h" -#endif - -#define CHECK_RES(_expr) \ - do { \ - fpga_result res = _expr; \ - if (res == FPGA_OK) \ - break; \ - printf("[VXDRV] Error: '%s' returned %d, %s!\n", \ - #_expr, (int)res, fpgaErrStr(res)); \ - return -1; \ - } while (false) - -/////////////////////////////////////////////////////////////////////////////// - -#define CMD_MEM_READ AFU_IMAGE_CMD_MEM_READ -#define CMD_MEM_WRITE AFU_IMAGE_CMD_MEM_WRITE -#define CMD_RUN AFU_IMAGE_CMD_RUN - -#define MMIO_CMD_TYPE (AFU_IMAGE_MMIO_CMD_TYPE * 4) -#define MMIO_IO_ADDR (AFU_IMAGE_MMIO_IO_ADDR * 4) -#define MMIO_MEM_ADDR (AFU_IMAGE_MMIO_MEM_ADDR * 4) -#define MMIO_DATA_SIZE (AFU_IMAGE_MMIO_DATA_SIZE * 4) -#define MMIO_DEV_CAPS (AFU_IMAGE_MMIO_DEV_CAPS * 4) -#define MMIO_STATUS (AFU_IMAGE_MMIO_STATUS * 4) - -#define STATUS_STATE_BITS 8 - -/////////////////////////////////////////////////////////////////////////////// - -class vx_device { -public: - vx_device() - : mem_allocator( - ALLOC_BASE_ADDR, - ALLOC_BASE_ADDR + LOCAL_MEM_SIZE, - 4096, - CACHE_BLOCK_SIZE) - {} - - ~vx_device() {} - - fpga_handle fpga; - vortex::MemoryAllocator mem_allocator; - unsigned version; - unsigned num_cores; - unsigned num_warps; - unsigned num_threads; -}; - -typedef struct vx_buffer_ { - uint64_t wsid; - void* host_ptr; - uint64_t io_addr; - vx_device_h hdevice; - uint64_t size; -} vx_buffer_t; - -/////////////////////////////////////////////////////////////////////////////// - -#ifdef DUMP_PERF_STATS -class AutoPerfDump { -private: - std::list devices_; - -public: - AutoPerfDump() {} - - ~AutoPerfDump() { - for (auto device : devices_) { - vx_dump_perf(device, stdout); - } - } - - void add_device(vx_device_h device) { - devices_.push_back(device); - } - - void remove_device(vx_device_h device) { - devices_.remove(device); - } -}; - -AutoPerfDump gAutoPerfDump; -#endif - -/////////////////////////////////////////////////////////////////////////////// - -extern int vx_dev_caps(vx_device_h hdevice, uint32_t caps_id, uint64_t *value) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - switch (caps_id) { - case VX_CAPS_VERSION: - *value = device->version; - break; - case VX_CAPS_MAX_CORES: - *value = device->num_cores; - break; - case VX_CAPS_MAX_WARPS: - *value = device->num_warps; - break; - case VX_CAPS_MAX_THREADS: - *value = device->num_threads; - break; - case VX_CAPS_CACHE_LINE_SIZE: - *value = CACHE_BLOCK_SIZE; - break; - case VX_CAPS_LOCAL_MEM_SIZE: - *value = LOCAL_MEM_SIZE; - break; - case VX_CAPS_ALLOC_BASE_ADDR: - *value = ALLOC_BASE_ADDR; - break; - case VX_CAPS_KERNEL_BASE_ADDR: - *value = STARTUP_ADDR; - break; - default: - fprintf(stderr, "[VXDRV] Error: invalid caps id: %d\n", caps_id); - std::abort(); - return -1; - } - - return 0; -} - -extern int vx_dev_open(vx_device_h* hdevice) { - if (nullptr == hdevice) - return -1; - - fpga_handle accel_handle; - vx_device* device; - -#ifndef USE_VLSIM - fpga_result res; - fpga_token accel_token; - fpga_properties filter = nullptr; - fpga_guid guid; - uint32_t num_matches; - - // Set up a filter that will search for an accelerator - CHECK_RES(fpgaGetProperties(nullptr, &filter)); - res = fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); - if (res != FPGA_OK) { - fprintf(stderr, "[VXDRV] Error: fpgaGetProperties() returned %d, %s!\n", (int)res, fpgaErrStr(res)); - fpgaDestroyProperties(&filter); - return -1; - } - - // Add the desired UUID to the filter - uuid_parse(AFU_ACCEL_UUID, guid); - res = fpgaPropertiesSetGUID(filter, guid); - if (res != FPGA_OK) { - fprintf(stderr, "[VXDRV] Error: fpgaPropertiesSetGUID() returned %d, %s!\n", (int)res, fpgaErrStr(res)); - fpgaDestroyProperties(&filter); - return -1; - } - - // Do the search across the available FPGA contexts - num_matches = 1; - res = fpgaEnumerate(&filter, 1, &accel_token, 1, &num_matches); - if (res != FPGA_OK) { - fprintf(stderr, "[VXDRV] Error: fpgaEnumerate() returned %d, %s!\n", (int)res, fpgaErrStr(res)); - fpgaDestroyProperties(&filter); - return -1; - } - - // Not needed anymore - fpgaDestroyProperties(&filter); - - if (num_matches < 1) { - fprintf(stderr, "[VXDRV] Error: accelerator %s not found!\n", AFU_ACCEL_UUID); - fpgaDestroyToken(&accel_token); - return -1; - } - - // Open accelerator - res = fpgaOpen(accel_token, &accel_handle, 0); - if (res != FPGA_OK) { - fprintf(stderr, "[VXDRV] Error: fpgaOpen() returned %d, %s!\n", (int)res, fpgaErrStr(res)); - fpgaDestroyToken(&accel_token); - return -1; - } - - // Done with token - fpgaDestroyToken(&accel_token); -#else - // Open accelerator - CHECK_RES(fpgaOpen(NULL, &accel_handle, 0)); -#endif - - // allocate device object - device = new vx_device(); - if (nullptr == device) { - fpgaClose(accel_handle); - return -1; - } - - device->fpga = accel_handle; - - { - // Load device CAPS - uint64_t dev_caps; - int ret = fpgaReadMMIO64(device->fpga, 0, MMIO_DEV_CAPS, &dev_caps); - if (ret != FPGA_OK) { - fpgaClose(accel_handle); - return ret; - } - device->version = (dev_caps >> 0) & 0xffff; - device->num_cores = (dev_caps >> 16) & 0xffff; - device->num_warps = (dev_caps >> 32) & 0xffff; - device->num_threads = (dev_caps >> 48) & 0xffff; - #ifndef NDEBUG - fprintf(stdout, "[VXDRV] DEVCAPS: version=%d, num_cores=%d, num_warps=%d, num_threads=%d\n", - device->version, device->num_cores, device->num_warps, device->num_threads); - #endif - } - -#ifdef SCOPE - { - int ret = vx_scope_start(accel_handle, 0, -1); - if (ret != 0) { - fpgaClose(accel_handle); - return ret; - } - } -#endif - - *hdevice = device; - -#ifdef DUMP_PERF_STATS - gAutoPerfDump.add_device(*hdevice); -#endif - - return 0; -} - -extern int vx_dev_close(vx_device_h hdevice) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - -#ifdef SCOPE - vx_scope_stop(device->fpga); -#endif - -#ifdef DUMP_PERF_STATS - gAutoPerfDump.remove_device(hdevice); - vx_dump_perf(hdevice, stdout); -#endif - - fpgaClose(device->fpga); - - delete device; - - return 0; -} - -extern int vx_mem_alloc(vx_device_h hdevice, uint64_t size, uint64_t* dev_maddr) { - if (nullptr == hdevice - || nullptr == dev_maddr - || 0 >= size) - return -1; - - vx_device *device = ((vx_device*)hdevice); - return device->mem_allocator.allocate(size, dev_maddr); -} - -extern int vx_mem_free(vx_device_h hdevice, uint64_t dev_maddr) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - return device->mem_allocator.release(dev_maddr); -} - -extern int vx_buf_alloc(vx_device_h hdevice, uint64_t size, vx_buffer_h* hbuffer) { - fpga_result res; - void* host_ptr; - uint64_t wsid; - uint64_t io_addr; - vx_buffer_t* buffer; - - if (nullptr == hdevice - || 0 >= size - || nullptr == hbuffer) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - size_t asize = aligned_size(size, CACHE_BLOCK_SIZE); - - res = fpgaPrepareBuffer(device->fpga, asize, &host_ptr, &wsid, 0); - if (FPGA_OK != res) { - return -1; - } - - // Get the physical address of the buffer in the accelerator - res = fpgaGetIOAddress(device->fpga, wsid, &io_addr); - if (FPGA_OK != res) { - fpgaReleaseBuffer(device->fpga, wsid); - return -1; - } - - // allocate buffer object - buffer = (vx_buffer_t*)malloc(sizeof(vx_buffer_t)); - if (nullptr == buffer) { - fpgaReleaseBuffer(device->fpga, wsid); - return -1; - } - - buffer->wsid = wsid; - buffer->host_ptr = host_ptr; - buffer->io_addr = io_addr; - buffer->hdevice = hdevice; - buffer->size = asize; - - *hbuffer = buffer; - - return 0; -} - -extern void* vx_host_ptr(vx_buffer_h hbuffer) { - if (nullptr == hbuffer) - return nullptr; - - vx_buffer_t* buffer = ((vx_buffer_t*)hbuffer); - return buffer->host_ptr; -} - -extern int vx_buf_free(vx_buffer_h hbuffer) { - if (nullptr == hbuffer) - return -1; - - vx_buffer_t* buffer = ((vx_buffer_t*)hbuffer); - vx_device *device = ((vx_device*)buffer->hdevice); - - fpgaReleaseBuffer(device->fpga, buffer->wsid); - - free(buffer); - - return 0; -} - -extern int vx_ready_wait(vx_device_h hdevice, uint64_t timeout) { - if (nullptr == hdevice) - return -1; - - std::unordered_map print_bufs; - - vx_device *device = ((vx_device*)hdevice); - - struct timespec sleep_time; - -#if defined(USE_ASE) - sleep_time.tv_sec = 1; - sleep_time.tv_nsec = 0; -#else - sleep_time.tv_sec = 0; - sleep_time.tv_nsec = 1000000; -#endif - - // to milliseconds - uint64_t sleep_time_ms = (sleep_time.tv_sec * 1000) + (sleep_time.tv_nsec / 1000000); - - for (;;) { - uint64_t status; - CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_STATUS, &status)); - - // check for console data - uint32_t cout_data = status >> STATUS_STATE_BITS; - if (cout_data & 0x1) { - // retrieve console data - do { - char cout_char = (cout_data >> 1) & 0xff; - uint32_t cout_tid = (cout_data >> 9) & 0xff; - auto& ss_buf = print_bufs[cout_tid]; - ss_buf << cout_char; - if (cout_char == '\n') { - std::cout << std::dec << "#" << cout_tid << ": " << ss_buf.str() << std::flush; - ss_buf.str(""); - } - CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_STATUS, &status)); - cout_data = status >> STATUS_STATE_BITS; - } while (cout_data & 0x1); - } - - uint32_t state = status & ((1 << STATUS_STATE_BITS)-1); - - if (0 == state || 0 == timeout) { - for (auto& buf : print_bufs) { - auto str = buf.second.str(); - if (!str.empty()) { - std::cout << "#" << buf.first << ": " << str << std::endl; - } - } - if (state != 0) { - fprintf(stdout, "[VXDRV] ready-wait timed out: state=%d\n", state); - } - break; - } - - nanosleep(&sleep_time, nullptr); - timeout -= sleep_time_ms; - }; - - return 0; -} - -extern int vx_copy_to_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t src_offset) { - if (nullptr == hbuffer - || 0 >= size) - return -1; - - vx_buffer_t *buffer = ((vx_buffer_t*)hbuffer); - vx_device *device = ((vx_device*)buffer->hdevice); - - uint64_t dev_mem_size = LOCAL_MEM_SIZE; - uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE); - - // check alignment - if (!is_aligned(dev_maddr, CACHE_BLOCK_SIZE)) - return -1; - if (!is_aligned(buffer->io_addr + src_offset, CACHE_BLOCK_SIZE)) - return -1; - - // bound checking - if (src_offset + asize > buffer->size) - return -1; - if (dev_maddr + asize > dev_mem_size) - return -1; - - // Ensure ready for new command - if (vx_ready_wait(buffer->hdevice, MAX_TIMEOUT) != 0) - return -1; - - auto ls_shift = (int)std::log2(CACHE_BLOCK_SIZE); - - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_IO_ADDR, (buffer->io_addr + src_offset) >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_MEM_WRITE)); - - // Wait for the write operation to finish - if (vx_ready_wait(buffer->hdevice, MAX_TIMEOUT) != 0) - return -1; - - return 0; -} - -extern int vx_copy_from_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t dest_offset) { - if (nullptr == hbuffer - || 0 >= size) - return -1; - - vx_buffer_t *buffer = ((vx_buffer_t*)hbuffer); - vx_device *device = ((vx_device*)buffer->hdevice); - - uint64_t dev_mem_size = LOCAL_MEM_SIZE; - uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE); - - // check alignment - if (!is_aligned(dev_maddr, CACHE_BLOCK_SIZE)) - return -1; - if (!is_aligned(buffer->io_addr + dest_offset, CACHE_BLOCK_SIZE)) - return -1; - - // bound checking - if (dest_offset + asize > buffer->size) - return -1; - if (dev_maddr + asize > dev_mem_size) - return -1; - - // Ensure ready for new command - if (vx_ready_wait(buffer->hdevice, MAX_TIMEOUT) != 0) - return -1; - - auto ls_shift = (int)std::log2(CACHE_BLOCK_SIZE); - - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_IO_ADDR, (buffer->io_addr + dest_offset) >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_MEM_READ)); - - // Wait for the write operation to finish - if (vx_ready_wait(buffer->hdevice, MAX_TIMEOUT) != 0) - return -1; - - return 0; -} - -extern int vx_start(vx_device_h hdevice) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - // Ensure ready for new command - if (vx_ready_wait(hdevice, MAX_TIMEOUT) != 0) - return -1; - - // start execution - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_RUN)); - - return 0; -} \ No newline at end of file diff --git a/driver/common/vx_scope.cpp b/driver/common/vx_scope.cpp deleted file mode 100644 index 9e855d5b..00000000 --- a/driver/common/vx_scope.cpp +++ /dev/null @@ -1,250 +0,0 @@ -#include "vx_scope.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define FRAME_FLUSH_SIZE 100 - -#define CHECK_RES(_expr) \ - do { \ - fpga_result res = _expr; \ - if (res == FPGA_OK) \ - break; \ - printf("OPAE Error: '%s' returned %d, %s!\n", \ - #_expr, (int)res, fpgaErrStr(res)); \ - return -1; \ - } while (false) - -#define MMIO_SCOPE_READ (AFU_IMAGE_MMIO_SCOPE_READ * 4) -#define MMIO_SCOPE_WRITE (AFU_IMAGE_MMIO_SCOPE_WRITE * 4) - -#define CMD_GET_VALID 0 -#define CMD_GET_DATA 1 -#define CMD_GET_WIDTH 2 -#define CMD_GET_COUNT 3 -#define CMD_SET_START 4 -#define CMD_SET_STOP 5 -#define CMD_GET_OFFSET 6 - -static constexpr int num_modules = sizeof(scope_modules) / sizeof(scope_module_t); - -static constexpr int num_taps = sizeof(scope_taps) / sizeof(scope_tap_t); - -constexpr int calcFrameWidth(int index = 0) { - return (index < num_taps) ? (scope_taps[index].width + calcFrameWidth(index + 1)) : 0; -} - -static constexpr int fwidth = calcFrameWidth(); - -#ifdef HANG_TIMEOUT -static std::thread g_timeout_thread; -static std::mutex g_timeout_mutex; - -static void timeout_callback(fpga_handle fpga) { - std::this_thread::sleep_for(std::chrono::seconds{HANG_TIMEOUT}); - vx_scope_stop(fpga); - fpgaClose(fpga); - exit(0); -} -#endif - -uint64_t print_clock(std::ofstream& ofs, uint64_t delta, uint64_t timestamp) { - while (delta != 0) { - ofs << '#' << timestamp++ << std::endl; - ofs << "b0 0" << std::endl; - ofs << '#' << timestamp++ << std::endl; - ofs << "b1 0" << std::endl; - --delta; - } - return timestamp; -} - -void dump_taps(std::ofstream& ofs, int module) { - for (int i = 0; i < num_taps; ++i) { - auto& tap = scope_taps[i]; - if (tap.module != module) - continue; - ofs << "$var reg " << tap.width << " " << (i + 1) << " " << tap.name << " $end" << std::endl; - } -} - -void dump_module(std::ofstream& ofs, int parent) { - for (auto& module : scope_modules) { - if (module.parent != parent) - continue; - if (module.name[0] == '*') { - ofs << "$var reg 1 0 clk $end" << std::endl; - } else { - ofs << "$scope module " << module.name << " $end" << std::endl; - } - dump_module(ofs, module.index); - dump_taps(ofs, module.index); - if (module.name[0] != '*') { - ofs << "$upscope $end" << std::endl; - } - } -} - -int vx_scope_start(fpga_handle hfpga, uint64_t start_time, uint64_t stop_time) { - if (nullptr == hfpga) - return -1; - - if (stop_time != uint64_t(-1)) { - // set stop time - uint64_t cmd_stop = ((stop_time << 3) | CMD_SET_STOP); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_stop)); - std::cout << "scope stop time: " << std::dec << stop_time << "s" << std::endl; - } - - // start recording - uint64_t cmd_delay = ((start_time << 3) | CMD_SET_START); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_delay)); - std::cout << "scope start time: " << std::dec << start_time << "s" << std::endl; - -#ifdef HANG_TIMEOUT - g_timeout_thread = std::thread(timeout_callback, hfpga); - g_timeout_thread.detach(); -#endif - - return 0; -} - -int vx_scope_stop(fpga_handle hfpga) { -#ifdef HANG_TIMEOUT - if (!g_timeout_mutex.try_lock()) - return 0; -#endif - - if (nullptr == hfpga) - return -1; - - // forced stop - uint64_t cmd_stop = ((0 << 3) | CMD_SET_STOP); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_stop)); - - std::cout << "scope trace dump begin..." << std::endl; - - std::ofstream ofs("trace.vcd"); - - ofs << "$version Generated by Vortex Scope $end" << std::endl; - ofs << "$timescale 1 ns $end" << std::endl; - ofs << "$scope module TOP $end" << std::endl; - - dump_module(ofs, -1); - dump_taps(ofs, -1); - ofs << "$upscope $end" << std::endl; - ofs << "enddefinitions $end" << std::endl; - - uint64_t frame_width, max_frames, data_valid, offset, delta; - uint64_t timestamp = 0; - uint64_t frame_offset = 0; - uint64_t frame_no = 0; - int signal_id = 0; - int signal_offset = 0; - - // wait for recording to terminate - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_VALID)); - do { - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); - if (data_valid) - break; - std::this_thread::sleep_for(std::chrono::seconds(1)); - } while (true); - - // get frame width - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_WIDTH)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &frame_width)); - std::cout << "scope::frame_width=" << std::dec << frame_width << std::endl; - - if (fwidth != (int)frame_width) { - std::cerr << "invalid frame_width: expecting " << std::dec << fwidth << "!" << std::endl; - std::abort(); - } - - // get max frames - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_COUNT)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &max_frames)); - std::cout << "scope::max_frames=" << std::dec << max_frames << std::endl; - - // get offset - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_OFFSET)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &offset)); - - // get data - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_DATA)); - - // print clock header - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta)); - timestamp = print_clock(ofs, offset + delta + 2, timestamp); - signal_id = num_taps; - - std::vector signal_data(frame_width+1); - - do { - if (frame_no == (max_frames-1)) { - // verify last frame is valid - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_VALID)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); - assert(data_valid == 1); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_DATA)); - } - - // read next data words - uint64_t word; - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &word)); - - do { - int signal_width = scope_taps[signal_id-1].width; - int word_offset = frame_offset % 64; - - signal_data[signal_width - signal_offset - 1] = ((word >> word_offset) & 0x1) ? '1' : '0'; - - ++signal_offset; - ++frame_offset; - - if (signal_offset == signal_width) { - signal_data[signal_width] = 0; // string null termination - ofs << 'b' << signal_data.data() << ' ' << signal_id << std::endl; - signal_offset = 0; - --signal_id; - } - - if (frame_offset == frame_width) { - assert(0 == signal_offset); - frame_offset = 0; - ++frame_no; - - if (frame_no != max_frames) { - // print clock header - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta)); - timestamp = print_clock(ofs, delta + 1, timestamp); - signal_id = num_taps; - if (0 == (frame_no % FRAME_FLUSH_SIZE)) { - ofs << std::flush; - std::cout << "*** " << frame_no << "/" << max_frames << " frames" << std::endl; - } - } - } - - } while ((frame_offset % 64) != 0); - - } while (frame_no != max_frames); - - std::cout << "scope trace dump done! - " << (timestamp/2) << " cycles" << std::endl; - - // verify data not valid - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_VALID)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); - assert(data_valid == 0); - - return 0; -} \ No newline at end of file diff --git a/driver/common/vx_scope.h b/driver/common/vx_scope.h deleted file mode 100644 index 0e2ae081..00000000 --- a/driver/common/vx_scope.h +++ /dev/null @@ -1,19 +0,0 @@ -#pragma once - -#include - -#ifdef USE_VLSIM -#include -#else -#include -#endif - -#if defined(USE_FPGA) -#define HANG_TIMEOUT 60 -#else -#define HANG_TIMEOUT (30*60) -#endif - -int vx_scope_start(fpga_handle hfpga, uint64_t start_time = 0, uint64_t stop_time = -1); - -int vx_scope_stop(fpga_handle hfpga); \ No newline at end of file diff --git a/driver/common/vx_utils.cpp b/driver/common/vx_utils.cpp deleted file mode 100644 index 4ca5377d..00000000 --- a/driver/common/vx_utils.cpp +++ /dev/null @@ -1,356 +0,0 @@ -#include "vx_utils.h" -#include -#include -#include -#include -#include -#include - -uint64_t aligned_size(uint64_t size, uint64_t alignment) { - assert(0 == (alignment & (alignment - 1))); - return (size + alignment - 1) & ~(alignment - 1); -} - -bool is_aligned(uint64_t addr, uint64_t alignment) { - assert(0 == (alignment & (alignment - 1))); - return 0 == (addr & (alignment - 1)); -} - -extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, uint64_t size) { - int err = 0; - - if (NULL == content || 0 == size) - return -1; - - uint32_t buffer_transfer_size = 65536; // 64 KB - uint64_t kernel_base_addr; - err = vx_dev_caps(device, VX_CAPS_KERNEL_BASE_ADDR, &kernel_base_addr); - if (err != 0) - return -1; - - // allocate device buffer - vx_buffer_h buffer; - err = vx_buf_alloc(device, buffer_transfer_size, &buffer); - if (err != 0) - return -1; - - // get buffer address - auto buf_ptr = (uint8_t*)vx_host_ptr(buffer); - - // - // upload content - // - - uint64_t offset = 0; - while (offset < size) { - auto chunk_size = std::min(buffer_transfer_size, size - offset); - std::memcpy(buf_ptr, (uint8_t*)content + offset, chunk_size); - - /*printf("*** Upload Kernel to 0x%0x: data=", kernel_base_addr + offset); - for (int i = 0, n = ((chunk_size+7)/8); i < n; ++i) { - printf("%08x", ((uint64_t*)((uint8_t*)content + offset))[n-1-i]); - } - printf("\n");*/ - - err = vx_copy_to_dev(buffer, kernel_base_addr + offset, chunk_size, 0); - if (err != 0) { - vx_buf_free(buffer); - return err; - } - offset += chunk_size; - } - - vx_buf_free(buffer); - - return 0; -} - -extern int vx_upload_kernel_file(vx_device_h device, const char* filename) { - std::ifstream ifs(filename); - if (!ifs) { - std::cout << "error: " << filename << " not found" << std::endl; - return -1; - } - - // read file content - ifs.seekg(0, ifs.end); - auto size = ifs.tellg(); - auto content = new char [size]; - ifs.seekg(0, ifs.beg); - ifs.read(content, size); - - // upload - int err = vx_upload_kernel_bytes(device, content, size); - - // release buffer - delete[] content; - - return err; -} - -/*static uint32_t get_csr_32(const uint32_t* buffer, int addr) { - uint32_t value_lo = buffer[addr - CSR_MPM_BASE]; - return value_lo; -}*/ - -static uint64_t get_csr_64(const uint32_t* buffer, int addr) { - uint32_t value_lo = buffer[addr - CSR_MPM_BASE]; - uint32_t value_hi = buffer[addr - CSR_MPM_BASE + 32]; - return (uint64_t(value_hi) << 32) | value_lo; -} - -extern int vx_dump_perf(vx_device_h device, FILE* stream) { - int ret = 0; - - uint64_t instrs = 0; - uint64_t cycles = 0; - -#ifdef PERF_ENABLE - // PERF: pipeline stalls - uint64_t ibuffer_stalls = 0; - uint64_t scoreboard_stalls = 0; - uint64_t lsu_stalls = 0; - uint64_t fpu_stalls = 0; - uint64_t csr_stalls = 0; - uint64_t alu_stalls = 0; - uint64_t gpu_stalls = 0; - // PERF: decode - uint64_t loads = 0; - uint64_t stores = 0; - uint64_t branches = 0; - // PERF: Icache - uint64_t icache_reads = 0; - uint64_t icache_read_misses = 0; - // PERF: Dcache - uint64_t dcache_reads = 0; - uint64_t dcache_writes = 0; - uint64_t dcache_read_misses = 0; - uint64_t dcache_write_misses = 0; - uint64_t dcache_bank_stalls = 0; - uint64_t dcache_mshr_stalls = 0; - // PERF: shared memory - uint64_t smem_reads = 0; - uint64_t smem_writes = 0; - uint64_t smem_bank_stalls = 0; - // PERF: memory - uint64_t mem_reads = 0; - uint64_t mem_writes = 0; - uint64_t mem_lat = 0; -#ifdef EXT_TEX_ENABLE - // PERF: texunit - uint64_t tex_mem_reads = 0; - uint64_t tex_mem_lat = 0; -#endif -#endif - - uint64_t num_cores; - ret = vx_dev_caps(device, VX_CAPS_MAX_CORES, &num_cores); - if (ret != 0) - return ret; - - vx_buffer_h staging_buf; - ret = vx_buf_alloc(device, 64 * sizeof(uint32_t), &staging_buf); - if (ret != 0) - return ret; - - auto staging_ptr = (uint32_t*)vx_host_ptr(staging_buf); - - for (unsigned core_id = 0; core_id < num_cores; ++core_id) { - ret = vx_copy_from_dev(staging_buf, IO_CSR_ADDR + 64 * sizeof(uint32_t) * core_id, 64 * sizeof(uint32_t), 0); - if (ret != 0) { - vx_buf_free(staging_buf); - return ret; - } - - uint64_t instrs_per_core = get_csr_64(staging_ptr, CSR_MINSTRET); - uint64_t cycles_per_core = get_csr_64(staging_ptr, CSR_MCYCLE); - float IPC = (float)(double(instrs_per_core) / double(cycles_per_core)); - if (num_cores > 1) fprintf(stream, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs_per_core, cycles_per_core, IPC); - instrs += instrs_per_core; - cycles = std::max(cycles_per_core, cycles); - - #ifdef PERF_ENABLE - // PERF: pipeline - // ibuffer_stall - uint64_t ibuffer_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_IBUF_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: ibuffer stalls=%ld\n", core_id, ibuffer_stalls_per_core); - ibuffer_stalls += ibuffer_stalls_per_core; - // scoreboard_stall - uint64_t scoreboard_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_SCRB_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: scoreboard stalls=%ld\n", core_id, scoreboard_stalls_per_core); - scoreboard_stalls += scoreboard_stalls_per_core; - // alu_stall - uint64_t alu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_ALU_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: alu unit stalls=%ld\n", core_id, alu_stalls_per_core); - alu_stalls += alu_stalls_per_core; - // lsu_stall - uint64_t lsu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_LSU_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: lsu unit stalls=%ld\n", core_id, lsu_stalls_per_core); - lsu_stalls += lsu_stalls_per_core; - // csr_stall - uint64_t csr_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_CSR_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: csr unit stalls=%ld\n", core_id, csr_stalls_per_core); - csr_stalls += csr_stalls_per_core; - // fpu_stall - uint64_t fpu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_FPU_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: fpu unit stalls=%ld\n", core_id, fpu_stalls_per_core); - fpu_stalls += fpu_stalls_per_core; - // gpu_stall - uint64_t gpu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_GPU_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: gpu unit stalls=%ld\n", core_id, gpu_stalls_per_core); - gpu_stalls += gpu_stalls_per_core; - - // PERF: decode - // loads - uint64_t loads_per_core = get_csr_64(staging_ptr, CSR_MPM_LOADS); - if (num_cores > 1) fprintf(stream, "PERF: core%d: loads=%ld\n", core_id, loads_per_core); - loads += loads_per_core; - // stores - uint64_t stores_per_core = get_csr_64(staging_ptr, CSR_MPM_STORES); - if (num_cores > 1) fprintf(stream, "PERF: core%d: stores=%ld\n", core_id, stores_per_core); - stores += stores_per_core; - // branches - uint64_t branches_per_core = get_csr_64(staging_ptr, CSR_MPM_BRANCHES); - if (num_cores > 1) fprintf(stream, "PERF: core%d: branches=%ld\n", core_id, branches_per_core); - branches += branches_per_core; - - // PERF: Icache - // total reads - uint64_t icache_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_ICACHE_READS); - if (num_cores > 1) fprintf(stream, "PERF: core%d: icache reads=%ld\n", core_id, icache_reads_per_core); - icache_reads += icache_reads_per_core; - // read misses - uint64_t icache_miss_r_per_core = get_csr_64(staging_ptr, CSR_MPM_ICACHE_MISS_R); - int icache_read_hit_ratio = (int)((1.0 - (double(icache_miss_r_per_core) / double(icache_reads_per_core))) * 100); - if (num_cores > 1) fprintf(stream, "PERF: core%d: icache misses=%ld (hit ratio=%d%%)\n", core_id, icache_miss_r_per_core, icache_read_hit_ratio); - icache_read_misses += icache_miss_r_per_core; - - // PERF: Dcache - // total reads - uint64_t dcache_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_READS); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache reads=%ld\n", core_id, dcache_reads_per_core); - dcache_reads += dcache_reads_per_core; - // total write - uint64_t dcache_writes_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_WRITES); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache writes=%ld\n", core_id, dcache_writes_per_core); - dcache_writes += dcache_writes_per_core; - // read misses - uint64_t dcache_miss_r_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_MISS_R); - int dcache_read_hit_ratio = (int)((1.0 - (double(dcache_miss_r_per_core) / double(dcache_reads_per_core))) * 100); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache read misses=%ld (hit ratio=%d%%)\n", core_id, dcache_miss_r_per_core, dcache_read_hit_ratio); - dcache_read_misses += dcache_miss_r_per_core; - // read misses - uint64_t dcache_miss_w_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_MISS_W); - int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_miss_w_per_core) / double(dcache_writes_per_core))) * 100); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache write misses=%ld (hit ratio=%d%%)\n", core_id, dcache_miss_w_per_core, dcache_write_hit_ratio); - dcache_write_misses += dcache_miss_w_per_core; - // bank_stalls - uint64_t dcache_bank_st_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_BANK_ST); - int dcache_bank_utilization = (int)((double(dcache_reads_per_core + dcache_writes_per_core) / double(dcache_reads_per_core + dcache_writes_per_core + dcache_bank_st_per_core)) * 100); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache bank stalls=%ld (utilization=%d%%)\n", core_id, dcache_bank_st_per_core, dcache_bank_utilization); - dcache_bank_stalls += dcache_bank_st_per_core; - // mshr_stalls - uint64_t dcache_mshr_st_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_MSHR_ST); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache mshr stalls=%ld\n", core_id, dcache_mshr_st_per_core); - dcache_mshr_stalls += dcache_mshr_st_per_core; - - // PERF: SMEM - // total reads - uint64_t smem_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_SMEM_READS); - if (num_cores > 1) fprintf(stream, "PERF: core%d: smem reads=%ld\n", core_id, smem_reads_per_core); - smem_reads += smem_reads_per_core; - // total write - uint64_t smem_writes_per_core = get_csr_64(staging_ptr, CSR_MPM_SMEM_WRITES); - if (num_cores > 1) fprintf(stream, "PERF: core%d: smem writes=%ld\n", core_id, smem_writes_per_core); - smem_writes += smem_writes_per_core; - // bank_stalls - uint64_t smem_bank_st_per_core = get_csr_64(staging_ptr, CSR_MPM_SMEM_BANK_ST); - int smem_bank_utilization = (int)((double(smem_reads_per_core + smem_writes_per_core) / double(smem_reads_per_core + smem_writes_per_core + smem_bank_st_per_core)) * 100); - if (num_cores > 1) fprintf(stream, "PERF: core%d: smem bank stalls=%ld (utilization=%d%%)\n", core_id, smem_bank_st_per_core, smem_bank_utilization); - smem_bank_stalls += smem_bank_st_per_core; - - // PERF: memory - uint64_t mem_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_MEM_READS); - uint64_t mem_writes_per_core = get_csr_64(staging_ptr, CSR_MPM_MEM_WRITES); - uint64_t mem_lat_per_core = get_csr_64(staging_ptr, CSR_MPM_MEM_LAT); - int mem_avg_lat = (int)(double(mem_lat_per_core) / double(mem_reads_per_core)); - if (num_cores > 1) fprintf(stream, "PERF: core%d: memory requests=%ld (reads=%ld, writes=%ld)\n", core_id, (mem_reads_per_core + mem_writes_per_core), mem_reads_per_core, mem_writes_per_core); - if (num_cores > 1) fprintf(stream, "PERF: core%d: memory latency=%d cycles\n", core_id, mem_avg_lat); - mem_reads += mem_reads_per_core; - mem_writes += mem_writes_per_core; - mem_lat += mem_lat_per_core; - - #ifdef EXT_TEX_ENABLE - // total reads - uint64_t tex_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_TEX_READS); - if (num_cores > 1) fprintf(stream, "PERF: core%d: tex memory reads=%ld\n", core_id, tex_reads_per_core); - tex_mem_reads += tex_reads_per_core; - - // read latency - uint64_t tex_lat_per_core = get_csr_64(staging_ptr, CSR_MPM_TEX_LAT); - int tex_avg_lat = (int)(double(tex_lat_per_core) / double(tex_reads_per_core)); - if (num_cores > 1) fprintf(stream, "PERF: core%d: tex memory latency=%d cycles\n", core_id, tex_avg_lat); - tex_mem_lat += tex_lat_per_core; - #endif - #endif - } - - float IPC = (float)(double(instrs) / double(cycles)); - fprintf(stream, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC); - -#ifdef PERF_ENABLE - int icache_read_hit_ratio = (int)((1.0 - (double(icache_read_misses) / double(icache_reads))) * 100); - int dcache_read_hit_ratio = (int)((1.0 - (double(dcache_read_misses) / double(dcache_reads))) * 100); - int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_write_misses) / double(dcache_writes))) * 100); - int dcache_bank_utilization = (int)((double(dcache_reads + dcache_writes) / double(dcache_reads + dcache_writes + dcache_bank_stalls)) * 100); - int smem_bank_utilization = (int)((double(smem_reads + smem_writes) / double(smem_reads + smem_writes + smem_bank_stalls)) * 100); - int mem_avg_lat = (int)(double(mem_lat) / double(mem_reads)); - fprintf(stream, "PERF: ibuffer stalls=%ld\n", ibuffer_stalls); - fprintf(stream, "PERF: scoreboard stalls=%ld\n", scoreboard_stalls); - fprintf(stream, "PERF: alu unit stalls=%ld\n", alu_stalls); - fprintf(stream, "PERF: lsu unit stalls=%ld\n", lsu_stalls); - fprintf(stream, "PERF: csr unit stalls=%ld\n", csr_stalls); - fprintf(stream, "PERF: fpu unit stalls=%ld\n", fpu_stalls); - fprintf(stream, "PERF: gpu unit stalls=%ld\n", gpu_stalls); - fprintf(stream, "PERF: loads=%ld\n", loads); - fprintf(stream, "PERF: stores=%ld\n", stores); - fprintf(stream, "PERF: branches=%ld\n", branches); - fprintf(stream, "PERF: icache reads=%ld\n", icache_reads); - fprintf(stream, "PERF: icache read misses=%ld (hit ratio=%d%%)\n", icache_read_misses, icache_read_hit_ratio); - fprintf(stream, "PERF: dcache reads=%ld\n", dcache_reads); - fprintf(stream, "PERF: dcache writes=%ld\n", dcache_writes); - fprintf(stream, "PERF: dcache read misses=%ld (hit ratio=%d%%)\n", dcache_read_misses, dcache_read_hit_ratio); - fprintf(stream, "PERF: dcache write misses=%ld (hit ratio=%d%%)\n", dcache_write_misses, dcache_write_hit_ratio); - fprintf(stream, "PERF: dcache bank stalls=%ld (utilization=%d%%)\n", dcache_bank_stalls, dcache_bank_utilization); - fprintf(stream, "PERF: dcache mshr stalls=%ld\n", dcache_mshr_stalls); - fprintf(stream, "PERF: smem reads=%ld\n", smem_reads); - fprintf(stream, "PERF: smem writes=%ld\n", smem_writes); - fprintf(stream, "PERF: smem bank stalls=%ld (utilization=%d%%)\n", smem_bank_stalls, smem_bank_utilization); - fprintf(stream, "PERF: memory requests=%ld (reads=%ld, writes=%ld)\n", (mem_reads + mem_writes), mem_reads, mem_writes); - fprintf(stream, "PERF: memory average latency=%d cycles\n", mem_avg_lat); -#ifdef EXT_TEX_ENABLE - int tex_avg_lat = (int)(double(tex_mem_lat) / double(tex_mem_reads)); - fprintf(stream, "PERF: tex memory reads=%ld\n", tex_mem_reads); - fprintf(stream, "PERF: tex memory latency=%d cycles\n", tex_avg_lat); -#endif -#endif - - // release allocated resources - vx_buf_free(staging_buf); - - return ret; -} - -// Deprecated API functions - -extern int vx_alloc_shared_mem(vx_device_h hdevice, uint64_t size, vx_buffer_h* hbuffer) { - return vx_buf_alloc(hdevice, size, hbuffer); -} - -extern int vx_buf_release(vx_buffer_h hbuffer) { - return vx_buf_free(hbuffer); -} - -extern int vx_alloc_dev_mem(vx_device_h hdevice, uint64_t size, uint64_t* dev_maddr) { - return vx_mem_alloc(hdevice, size, dev_maddr); -} \ No newline at end of file diff --git a/driver/common/vx_utils.h b/driver/common/vx_utils.h deleted file mode 100644 index b86c75af..00000000 --- a/driver/common/vx_utils.h +++ /dev/null @@ -1,11 +0,0 @@ -#pragma once - -#include - -uint64_t aligned_size(uint64_t size, uint64_t alignment); - -bool is_aligned(uint64_t addr, uint64_t alignment); - -#define CACHE_BLOCK_SIZE 64 -#define ALLOC_BASE_ADDR 0x00000000 -#define LOCAL_MEM_SIZE 4294967296 // 4 GB \ No newline at end of file diff --git a/driver/fpga/Makefile b/driver/fpga/Makefile deleted file mode 100644 index e5a5417f..00000000 --- a/driver/fpga/Makefile +++ /dev/null @@ -1,75 +0,0 @@ -OPAE_HOME ?= /tools/opae/1.4.0 - -RTL_DIR=../../hw/rtl - -SCRIPT_DIR=../../hw/scripts - -OPAE_SYN_DIR=../../hw/syn/opae - -CXXFLAGS += -std=c++11 -Wall -Wextra -pedantic -Wfatal-errors - -CXXFLAGS += -I. -I../include -I../../hw -I$(OPAE_HOME)/include -I$(OPAE_SYN_DIR) - -LDFLAGS += -L$(OPAE_HOME)/lib -luuid -lopae-c - -#SCOPE=1 - -# stack execution protection -LDFLAGS +=-z noexecstack - -# data relocation and projection -LDFLAGS +=-z relro -z now - -# stack buffer overrun detection -CXXFLAGS +=-fstack-protector - -# Position independent code -CXXFLAGS += -fPIC - -# Add external configuration -CXXFLAGS += $(CONFIGS) - -# Dump perf stats -CXXFLAGS += -DDUMP_PERF_STATS - -LDFLAGS += -shared - -PROJECT = libvortex.so - -SRCS = ../common/opae.cpp ../common/vx_utils.cpp - -# Debugigng -ifdef DEBUG - CXXFLAGS += -g -O0 -else - CXXFLAGS += -O2 -DNDEBUG -endif - -# Enable scope analyzer -ifdef SCOPE - CXXFLAGS += -DSCOPE - SRCS += ../common/vx_scope.cpp - SCOPE_H = scope-defs.h -endif - -# Enable perf counters -ifdef PERF - CXXFLAGS += -DPERF_ENABLE -endif - -all: $(PROJECT) - -$(OPAE_SYN_DIR)/vortex_afu.h: - $(MAKE) -C $(OPAE_SYN_DIR) vortex_afu.h - -scope-defs.h: $(SCRIPT_DIR)/scope.json - $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json - -# generate scope data -scope: scope-defs.h - -$(PROJECT): $(SRCS) $(OPAE_SYN_DIR)/vortex_afu.h $(SCOPE_H) - $(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) -o $(PROJECT) - -clean: - rm -rf $(PROJECT) *.o scope-defs.h \ No newline at end of file diff --git a/driver/include/vortex.h b/driver/include/vortex.h deleted file mode 100644 index 693e4fac..00000000 --- a/driver/include/vortex.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef __VX_DRIVER_H__ -#define __VX_DRIVER_H__ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef void* vx_device_h; - -typedef void* vx_buffer_h; - -// device caps ids -#define VX_CAPS_VERSION 0x0 -#define VX_CAPS_MAX_CORES 0x1 -#define VX_CAPS_MAX_WARPS 0x2 -#define VX_CAPS_MAX_THREADS 0x3 -#define VX_CAPS_CACHE_LINE_SIZE 0x4 -#define VX_CAPS_LOCAL_MEM_SIZE 0x5 -#define VX_CAPS_ALLOC_BASE_ADDR 0x6 -#define VX_CAPS_KERNEL_BASE_ADDR 0x7 - -#define MAX_TIMEOUT (60*60*1000) // 1hr - -// open the device and connect to it -int vx_dev_open(vx_device_h* hdevice); - -// Close the device when all the operations are done -int vx_dev_close(vx_device_h hdevice); - -// return device configurations -int vx_dev_caps(vx_device_h hdevice, uint32_t caps_id, uint64_t *value); - -// Allocate shared buffer with device -int vx_buf_alloc(vx_device_h hdevice, uint64_t size, vx_buffer_h* hbuffer); - -// release buffer -int vx_buf_free(vx_buffer_h hbuffer); - -// Get host pointer address -void* vx_host_ptr(vx_buffer_h hbuffer); - -// allocate device memory and return address -int vx_mem_alloc(vx_device_h hdevice, uint64_t size, uint64_t* dev_maddr); - -// release device memory -int vx_mem_free(vx_device_h hdevice, uint64_t dev_maddr); - -// Copy bytes from buffer to device local memory -int vx_copy_to_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t src_offset); - -// Copy bytes from device local memory to buffer -int vx_copy_from_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t dst_offset); - -// Start device execution -int vx_start(vx_device_h hdevice); - -// Wait for device ready with milliseconds timeout -int vx_ready_wait(vx_device_h hdevice, uint64_t timeout); - -////////////////////////////// UTILITY FUNCIONS /////////////////////////////// - -// upload kernel bytes to device -int vx_upload_kernel_bytes(vx_device_h device, const void* content, uint64_t size); - -// upload kernel file to device -int vx_upload_kernel_file(vx_device_h device, const char* filename); - -// dump performance counters -int vx_dump_perf(vx_device_h device, FILE* stream); - -//////////////////////////// DEPRECATED FUNCTIONS ///////////////////////////// -int vx_alloc_dev_mem(vx_device_h hdevice, uint64_t size, uint64_t* dev_maddr); -int vx_alloc_shared_mem(vx_device_h hdevice, uint64_t size, vx_buffer_h* hbuffer); -int vx_buf_release(vx_buffer_h hbuffer); - -#ifdef __cplusplus -} -#endif - -#endif // __VX_DRIVER_H__ diff --git a/driver/rtlsim/vortex.cpp b/driver/rtlsim/vortex.cpp deleted file mode 100644 index 8e180339..00000000 --- a/driver/rtlsim/vortex.cpp +++ /dev/null @@ -1,355 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define RAM_PAGE_SIZE 4096 - -using namespace vortex; - -/////////////////////////////////////////////////////////////////////////////// - -class vx_device; -class vx_buffer { -public: - vx_buffer(uint64_t size, vx_device* device) - : size_(size) - , device_(device) { - auto aligned_asize = aligned_size(size, CACHE_BLOCK_SIZE); - data_ = malloc(aligned_asize); - } - - ~vx_buffer() { - if (data_) { - free(data_); - } - } - - void* data() const { - return data_; - } - - uint64_t size() const { - return size_; - } - - vx_device* device() const { - return device_; - } - -private: - uint64_t size_; - vx_device* device_; - void* data_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class vx_device { -public: - vx_device() - : ram_(RAM_PAGE_SIZE) - , mem_allocator_( - ALLOC_BASE_ADDR, - ALLOC_BASE_ADDR + LOCAL_MEM_SIZE, - RAM_PAGE_SIZE, - CACHE_BLOCK_SIZE) - { - processor_.attach_ram(&ram_); - } - - ~vx_device() { - if (future_.valid()) { - future_.wait(); - } - } - - int alloc_local_mem(uint64_t size, uint64_t* dev_maddr) { - return mem_allocator_.allocate(size, dev_maddr); - } - - int free_local_mem(uint64_t dev_maddr) { - return mem_allocator_.release(dev_maddr); - } - - int upload(const void* src, uint64_t dest_addr, uint64_t size, uint64_t src_offset) { - uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE); - if (dest_addr + asize > LOCAL_MEM_SIZE) - return -1; - - /*printf("VXDRV: upload %ld bytes from 0x%lx:", size, uintptr_t((uint8_t*)src + src_offset)); - for (int i = 0; i < (asize / CACHE_BLOCK_SIZE); ++i) { - printf("\n0x%08lx=", dest_addr + i * CACHE_BLOCK_SIZE); - for (int j = 0; j < CACHE_BLOCK_SIZE; ++j) { - printf("%02x", *((uint8_t*)src + src_offset + i * CACHE_BLOCK_SIZE + CACHE_BLOCK_SIZE - 1 - j)); - } - } - printf("\n");*/ - - ram_.write((const uint8_t*)src + src_offset, dest_addr, asize); - return 0; - } - - int download(void* dest, uint64_t src_addr, uint64_t size, uint64_t dest_offset) { - uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE); - if (src_addr + asize > LOCAL_MEM_SIZE) - return -1; - - ram_.read((uint8_t*)dest + dest_offset, src_addr, asize); - - /*printf("VXDRV: download %ld bytes to 0x%lx:", size, uintptr_t((uint8_t*)dest + dest_offset)); - for (int i = 0; i < (asize / CACHE_BLOCK_SIZE); ++i) { - printf("\n0x%08lx=", src_addr + i * CACHE_BLOCK_SIZE); - for (int j = 0; j < CACHE_BLOCK_SIZE; ++j) { - printf("%02x", *((uint8_t*)dest + dest_offset + i * CACHE_BLOCK_SIZE + CACHE_BLOCK_SIZE - 1 - j)); - } - } - printf("\n");*/ - - return 0; - } - - int start() { - // ensure prior run completed - if (future_.valid()) { - future_.wait(); - } - // start new run - future_ = std::async(std::launch::async, [&]{ - processor_.run(); - }); - return 0; - } - - int wait(uint64_t timeout) { - if (!future_.valid()) - return 0; - uint64_t timeout_sec = timeout / 1000; - std::chrono::seconds wait_time(1); - for (;;) { - // wait for 1 sec and check status - auto status = future_.wait_for(wait_time); - if (status == std::future_status::ready - || 0 == timeout_sec--) - break; - } - return 0; - } - -private: - - RAM ram_; - Processor processor_; - MemoryAllocator mem_allocator_; - std::future future_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -#ifdef DUMP_PERF_STATS -class AutoPerfDump { -private: - std::list devices_; - -public: - AutoPerfDump() {} - - ~AutoPerfDump() { - for (auto device : devices_) { - vx_dump_perf(device, stdout); - } - } - - void add_device(vx_device_h device) { - devices_.push_back(device); - } - - void remove_device(vx_device_h device) { - devices_.remove(device); - } -}; - -AutoPerfDump gAutoPerfDump; -#endif - -/////////////////////////////////////////////////////////////////////////////// - -extern int vx_dev_caps(vx_device_h hdevice, uint32_t caps_id, uint64_t *value) { - if (nullptr == hdevice) - return -1; - - switch (caps_id) { - case VX_CAPS_VERSION: - *value = IMPLEMENTATION_ID; - break; - case VX_CAPS_MAX_CORES: - *value = NUM_CORES * NUM_CLUSTERS; - break; - case VX_CAPS_MAX_WARPS: - *value = NUM_WARPS; - break; - case VX_CAPS_MAX_THREADS: - *value = NUM_THREADS; - break; - case VX_CAPS_CACHE_LINE_SIZE: - *value = CACHE_BLOCK_SIZE; - break; - case VX_CAPS_LOCAL_MEM_SIZE: - *value = LOCAL_MEM_SIZE; - break; - case VX_CAPS_ALLOC_BASE_ADDR: - *value = ALLOC_BASE_ADDR; - break; - case VX_CAPS_KERNEL_BASE_ADDR: - *value = STARTUP_ADDR; - break; - default: - std::cout << "invalid caps id: " << caps_id << std::endl; - std::abort(); - return -1; - } - - return 0; -} - -extern int vx_dev_open(vx_device_h* hdevice) { - if (nullptr == hdevice) - return -1; - - *hdevice = new vx_device(); - -#ifdef DUMP_PERF_STATS - gAutoPerfDump.add_device(*hdevice); -#endif - - return 0; -} - -extern int vx_dev_close(vx_device_h hdevice) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - -#ifdef DUMP_PERF_STATS - gAutoPerfDump.remove_device(hdevice); - vx_dump_perf(hdevice, stdout); -#endif - - delete device; - - return 0; -} - -extern int vx_mem_alloc(vx_device_h hdevice, uint64_t size, uint64_t* dev_maddr) { - if (nullptr == hdevice - || nullptr == dev_maddr - || 0 >= size) - return -1; - - vx_device *device = ((vx_device*)hdevice); - return device->alloc_local_mem(size, dev_maddr); -} - -extern int vx_mem_free(vx_device_h hdevice, uint64_t dev_maddr) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - return device->free_local_mem(dev_maddr); -} - -extern int vx_buf_alloc(vx_device_h hdevice, uint64_t size, vx_buffer_h* hbuffer) { - if (nullptr == hdevice - || 0 >= size - || nullptr == hbuffer) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - auto buffer = new vx_buffer(size, device); - if (nullptr == buffer->data()) { - delete buffer; - return -1; - } - - *hbuffer = buffer; - - return 0; -} - -extern void* vx_host_ptr(vx_buffer_h hbuffer) { - if (nullptr == hbuffer) - return nullptr; - - vx_buffer* buffer = ((vx_buffer*)hbuffer); - - return buffer->data(); -} - -extern int vx_buf_free(vx_buffer_h hbuffer) { - if (nullptr == hbuffer) - return -1; - - vx_buffer* buffer = ((vx_buffer*)hbuffer); - - delete buffer; - - return 0; -} - -extern int vx_copy_to_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t src_offset) { - if (nullptr == hbuffer - || 0 >= size) - return -1; - - auto buffer = (vx_buffer*)hbuffer; - - if (size + src_offset > buffer->size()) - return -1; - - return buffer->device()->upload(buffer->data(), dev_maddr, size, src_offset); -} - -extern int vx_copy_from_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t dest_offset) { - if (nullptr == hbuffer - || 0 >= size) - return -1; - - auto buffer = (vx_buffer*)hbuffer; - - if (size + dest_offset > buffer->size()) - return -1; - - return buffer->device()->download(buffer->data(), dev_maddr, size, dest_offset); -} - -extern int vx_start(vx_device_h hdevice) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - return device->start(); -} - -extern int vx_ready_wait(vx_device_h hdevice, uint64_t timeout) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - return device->wait(timeout); -} \ No newline at end of file diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp deleted file mode 100644 index 95957cc2..00000000 --- a/driver/simx/vortex.cpp +++ /dev/null @@ -1,357 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include - -#include -#include -#include -#include - - -using namespace vortex; - -/////////////////////////////////////////////////////////////////////////////// - -class vx_device; - -class vx_buffer { -public: - vx_buffer(uint64_t size, vx_device* device) - : size_(size) - , device_(device) { - uint64_t aligned_asize = aligned_size(size, CACHE_BLOCK_SIZE); - data_ = malloc(aligned_asize); - } - - ~vx_buffer() { - if (data_) { - free(data_); - } - } - - void* data() const { - return data_; - } - - uint64_t size() const { - return size_; - } - - vx_device* device() const { - return device_; - } - -private: - uint64_t size_; - vx_device* device_; - void* data_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class vx_device { -public: - vx_device() - : arch_(NUM_CORES * NUM_CLUSTERS, NUM_WARPS, NUM_THREADS) - , ram_(RAM_PAGE_SIZE) - , processor_(arch_) - , mem_allocator_( - ALLOC_BASE_ADDR, - ALLOC_BASE_ADDR + LOCAL_MEM_SIZE, - RAM_PAGE_SIZE, - CACHE_BLOCK_SIZE) - { - // attach memory module - processor_.attach_ram(&ram_); - } - - ~vx_device() { - if (future_.valid()) { - future_.wait(); - } - } - - int alloc_local_mem(uint64_t size, uint64_t* dev_maddr) { - return mem_allocator_.allocate(size, dev_maddr); - } - - int free_local_mem(uint64_t dev_maddr) { - return mem_allocator_.release(dev_maddr); - } - - int upload(const void* src, uint64_t dest_addr, uint64_t size, uint64_t src_offset) { - uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE); - if (dest_addr + asize > LOCAL_MEM_SIZE) - return -1; - - ram_.write((const uint8_t*)src + src_offset, dest_addr, asize); - - /*printf("VXDRV: upload %d bytes to 0x%x\n", size, dest_addr); - for (int i = 0; i < size; i += 4) { - printf("mem-write: 0x%x <- 0x%x\n", dest_addr + i, *(uint32_t*)((uint8_t*)src + src_offset + i)); - }*/ - - return 0; - } - - int download(void* dest, uint64_t src_addr, uint64_t size, uint64_t dest_offset) { - uint64_t asize = aligned_size(size, CACHE_BLOCK_SIZE); - if (src_addr + asize > LOCAL_MEM_SIZE) - return -1; - - ram_.read((uint8_t*)dest + dest_offset, src_addr, asize); - - /*printf("VXDRV: download %d bytes from 0x%x\n", size, src_addr); - for (int i = 0; i < size; i += 4) { - printf("mem-read: 0x%x -> 0x%x\n", src_addr + i, *(uint32_t*)((uint8_t*)dest + dest_offset + i)); - }*/ - - return 0; - } - - int start() { - // ensure prior run completed - if (future_.valid()) { - future_.wait(); - } - - // start new run - future_ = std::async(std::launch::async, [&]{ - processor_.run(); - }); - - return 0; - } - - int wait(uint64_t timeout) { - if (!future_.valid()) - return 0; - uint64_t timeout_sec = timeout / 1000; - std::chrono::seconds wait_time(1); - for (;;) { - // wait for 1 sec and check status - auto status = future_.wait_for(wait_time); - if (status == std::future_status::ready - || 0 == timeout_sec--) - break; - } - return 0; - } - -private: - ArchDef arch_; - RAM ram_; - Processor processor_; - MemoryAllocator mem_allocator_; - std::future future_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -#ifdef DUMP_PERF_STATS -class AutoPerfDump { -private: - std::list devices_; - -public: - AutoPerfDump() {} - - ~AutoPerfDump() { - for (auto device : devices_) { - vx_dump_perf(device, stdout); - } - } - - void add_device(vx_device_h device) { - devices_.push_back(device); - } - - void remove_device(vx_device_h device) { - devices_.remove(device); - } -}; - -AutoPerfDump gAutoPerfDump; -#endif - -/////////////////////////////////////////////////////////////////////////////// - -extern int vx_dev_open(vx_device_h* hdevice) { - if (nullptr == hdevice) - return -1; - - *hdevice = new vx_device(); - -#ifdef DUMP_PERF_STATS - gAutoPerfDump.add_device(*hdevice); -#endif - - return 0; -} - -extern int vx_dev_close(vx_device_h hdevice) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - -#ifdef DUMP_PERF_STATS - gAutoPerfDump.remove_device(hdevice); - vx_dump_perf(hdevice, stdout); -#endif - - delete device; - - return 0; -} - -extern int vx_dev_caps(vx_device_h hdevice, uint32_t caps_id, uint64_t *value) { - if (nullptr == hdevice) - return -1; - - switch (caps_id) { - case VX_CAPS_VERSION: - *value = IMPLEMENTATION_ID; - break; - case VX_CAPS_MAX_CORES: - *value = NUM_CORES * NUM_CLUSTERS; - break; - case VX_CAPS_MAX_WARPS: - *value = NUM_WARPS; - break; - case VX_CAPS_MAX_THREADS: - *value = NUM_THREADS; - break; - case VX_CAPS_CACHE_LINE_SIZE: - *value = CACHE_BLOCK_SIZE; - break; - case VX_CAPS_LOCAL_MEM_SIZE: - *value = LOCAL_MEM_SIZE; - break; - case VX_CAPS_ALLOC_BASE_ADDR: - *value = ALLOC_BASE_ADDR; - break; - case VX_CAPS_KERNEL_BASE_ADDR: - *value = STARTUP_ADDR; - break; - default: - std::cout << "invalid caps id: " << caps_id << std::endl; - std::abort(); - return -1; - } - - return 0; -} - -extern int vx_mem_alloc(vx_device_h hdevice, uint64_t size, uint64_t* dev_maddr) { - if (nullptr == hdevice - || nullptr == dev_maddr - || 0 >= size) - return -1; - - vx_device *device = ((vx_device*)hdevice); - return device->alloc_local_mem(size, dev_maddr); -} - -extern int vx_mem_free(vx_device_h hdevice, uint64_t dev_maddr) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - return device->free_local_mem(dev_maddr); -} - -extern int vx_buf_alloc(vx_device_h hdevice, uint64_t size, vx_buffer_h* hbuffer) { - if (nullptr == hdevice - || 0 >= size - || nullptr == hbuffer) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - auto buffer = new vx_buffer(size, device); - if (nullptr == buffer->data()) { - delete buffer; - return -1; - } - - *hbuffer = buffer; - - return 0; -} - -extern void* vx_host_ptr(vx_buffer_h hbuffer) { - if (nullptr == hbuffer) - return nullptr; - - vx_buffer* buffer = ((vx_buffer*)hbuffer); - - return buffer->data(); -} - -extern int vx_buf_free(vx_buffer_h hbuffer) { - if (nullptr == hbuffer) - return -1; - - vx_buffer* buffer = ((vx_buffer*)hbuffer); - - delete buffer; - - return 0; -} - -extern int vx_copy_to_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t src_offset) { - if (nullptr == hbuffer - || 0 >= size) - return -1; - - auto buffer = (vx_buffer*)hbuffer; - - if (size + src_offset > buffer->size()) - return -1; - - return buffer->device()->upload(buffer->data(), dev_maddr, size, src_offset); -} - -extern int vx_copy_from_dev(vx_buffer_h hbuffer, uint64_t dev_maddr, uint64_t size, uint64_t dest_offset) { - if (nullptr == hbuffer - || 0 >= size) - return -1; - - auto buffer = (vx_buffer*)hbuffer; - - if (size + dest_offset > buffer->size()) - return -1; - - return buffer->device()->download(buffer->data(), dev_maddr, size, dest_offset); -} - -extern int vx_start(vx_device_h hdevice) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - return device->start(); -} - -extern int vx_ready_wait(vx_device_h hdevice, uint64_t timeout) { - if (nullptr == hdevice) - return -1; - - vx_device *device = ((vx_device*)hdevice); - - return device->wait(timeout); -} \ No newline at end of file diff --git a/driver/stub/vortex.cpp b/driver/stub/vortex.cpp deleted file mode 100644 index 1fa86796..00000000 --- a/driver/stub/vortex.cpp +++ /dev/null @@ -1,49 +0,0 @@ -#include - -extern int vx_dev_open(vx_device_h* /*hdevice*/) { - return -1; -} - -extern int vx_dev_close(vx_device_h /*hdevice*/) { - return -1; -} - -extern int vx_dev_caps(vx_device_h /*hdevice*/, uint32_t /*caps_id*/, uint64_t* /*value*/) { - return -1; -} - -extern int vx_mem_alloc(vx_device_h /*hdevice*/, uint64_t /*size*/, uint64_t* /*dev_maddr*/) { - return -1; -} - -int vx_mem_free(vx_device_h /*hdevice*/, uint64_t /*dev_maddr*/) { - return -1; -} - -extern int vx_buf_alloc(vx_device_h /*hdevice*/, uint64_t /*size*/, vx_buffer_h* /*hbuffer*/) { - return -1; -} - -extern void* vx_host_ptr(vx_buffer_h /*hbuffer*/) { - return nullptr; -} - -extern int vx_buf_free(vx_buffer_h /*hbuffer*/) { - return -1; -} - -extern int vx_copy_to_dev(vx_buffer_h /*hbuffer*/, uint64_t /*dev_maddr*/, uint64_t /*size*/, uint64_t /*src_offset*/) { - return -1; -} - -extern int vx_copy_from_dev(vx_buffer_h /*hbuffer*/, uint64_t /*dev_maddr*/, uint64_t /*size*/, uint64_t /*dest_offset*/) { - return -1; -} - -extern int vx_start(vx_device_h /*hdevice*/) { - return -1; -} - -extern int vx_ready_wait(vx_device_h /*hdevice*/, uint64_t /*timeout*/) { - return -1; -} \ No newline at end of file diff --git a/driver/vlsim/Makefile b/driver/vlsim/Makefile deleted file mode 100644 index a560c3a8..00000000 --- a/driver/vlsim/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -VLSIM_DIR = ../../sim/vlsim - -RTL_DIR=../../hw/rtl - -SCRIPT_DIR=../../hw/scripts - -CXXFLAGS += -std=c++11 -Wall -Wextra -pedantic -Wfatal-errors - -CXXFLAGS += -I. -I../include -I../../hw -I$(VLSIM_DIR) - -# Position independent code -CXXFLAGS += -fPIC - -# Add external configuration -CXXFLAGS += $(CONFIGS) - -# Dump perf stats -CXXFLAGS += -DDUMP_PERF_STATS - -LDFLAGS += -shared -pthread -LDFLAGS += -L. -lopae-c-vlsim - -SRCS = ../common/opae.cpp ../common/vx_utils.cpp - -# Debugigng -ifdef DEBUG - CXXFLAGS += -g -O0 -else - CXXFLAGS += -O2 -DNDEBUG -endif - -# Enable scope analyzer -ifdef SCOPE - CXXFLAGS += -DSCOPE - SRCS += ../common/vx_scope.cpp - SCOPE_H = scope-defs.h -endif - -# Enable perf counters -ifdef PERF - CXXFLAGS += -DPERF_ENABLE -endif - -PROJECT = libvortex.so - -all: $(PROJECT) - -scope-defs.h: $(SCRIPT_DIR)/scope.json - $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json - -# generate scope data -scope: scope-defs.h - -$(PROJECT): $(SRCS) $(SCOPE_H) - DESTDIR=../../driver/vlsim $(MAKE) -C $(VLSIM_DIR) ../../driver/vlsim/libopae-c-vlsim.so - $(CXX) $(CXXFLAGS) -DUSE_VLSIM $(SRCS) $(LDFLAGS) -o $(PROJECT) - -clean: - DESTDIR=../../driver/vlsim $(MAKE) -C $(VLSIM_DIR) clean - rm -rf libopae-c-vlsim.so $(PROJECT) *.o scope-defs.h \ No newline at end of file diff --git a/hw/.gitignore b/hw/.gitignore index c9aa863d..e4187f99 100644 --- a/hw/.gitignore +++ b/hw/.gitignore @@ -1 +1,2 @@ -obj_dir/* \ No newline at end of file +VX_config.h +VX_types.h \ No newline at end of file diff --git a/hw/Makefile b/hw/Makefile index bb834e32..5f8d2bb3 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -1,12 +1,17 @@ RTL_DIR=./rtl SCRIPT_DIR=./scripts -all: VX_config.h +all: config + +config: VX_config.h VX_types.h VX_config.h: $(RTL_DIR)/VX_config.vh $(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/VX_config.vh -o VX_config.h -clean: - rm -f VX_config.h +VX_types.h: $(RTL_DIR)/VX_types.vh + $(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/VX_types.vh -o VX_types.h -.PHONY: VX_config.h \ No newline at end of file +clean: + rm -f VX_config.h VX_types.h + +.PHONY: VX_config.h VX_types.h \ No newline at end of file diff --git a/hw/dpi/float_dpi.cpp b/hw/dpi/float_dpi.cpp index 9a6b4a12..340b258d 100644 --- a/hw/dpi/float_dpi.cpp +++ b/hw/dpi/float_dpi.cpp @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include #include #include @@ -5,167 +18,323 @@ #include #include #include +#include #include "svdpi.h" #include "verilated_vpi.h" #include "VX_config.h" extern "C" { - void dpi_fadd(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fsub(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fmul(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fnmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fnmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fadd(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_fsub(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_fmul(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_fmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_fmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_fnmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_fnmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); - void dpi_fdiv(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_fsqrt(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fdiv(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_fsqrt(bool enable, int dst_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + + void dpi_ftoi(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_ftou(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_itof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_utof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags); + void dpi_f2f(bool enable, int dst_fmt, int64_t a, int64_t* result); - void dpi_ftoi(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_ftou(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_itof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); - void dpi_utof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags); + void dpi_fclss(bool enable, int dst_fmt, int64_t a, int64_t* result); + void dpi_fsgnj(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result); + void dpi_fsgnjn(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result); + void dpi_fsgnjx(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result); - void dpi_fclss(bool enable, int a, int* result); - void dpi_fsgnj(bool enable, int a, int b, int* result); - void dpi_fsgnjn(bool enable, int a, int b, int* result); - void dpi_fsgnjx(bool enable, int a, int b, int* result); - - void dpi_flt(bool enable, int a, int b, int* result, svBitVecVal* fflags); - void dpi_fle(bool enable, int a, int b, int* result, svBitVecVal* fflags); - void dpi_feq(bool enable, int a, int b, int* result, svBitVecVal* fflags); - void dpi_fmin(bool enable, int a, int b, int* result, svBitVecVal* fflags); - void dpi_fmax(bool enable, int a, int b, int* result, svBitVecVal* fflags); + void dpi_flt(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags); + void dpi_fle(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags); + void dpi_feq(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags); + void dpi_fmin(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags); + void dpi_fmax(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags); } -void dpi_fadd(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { - if (!enable) - return; - *result = rv_fadd_s(a, b, (*frm & 0x7), fflags); +inline uint64_t nan_box(uint32_t value) { +#ifdef FPU_RV64F + return value | 0xffffffff00000000; +#else + return value; +#endif } -void dpi_fsub(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { - if (!enable) - return; - *result = rv_fsub_s(a, b, (*frm & 0x7), fflags); +inline bool is_nan_boxed(uint64_t value) { +#ifdef FPU_RV64F + return (uint32_t(value >> 32) == 0xffffffff); +#else + __unused (value); + return true; +#endif } -void dpi_fmul(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { - if (!enable) - return; - *result = rv_fmul_s(a, b, (*frm & 0x7), fflags); +inline int64_t check_boxing(int64_t a) { + if (!is_nan_boxed(a)) { + return nan_box(0x7fc00000); // NaN + } + return a; } -void dpi_fmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fadd(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fmadd_s(a, b, c, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fadd_d(a, b, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fadd_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags)); + } } -void dpi_fmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fsub(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fmsub_s(a, b, c, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fsub_d(a, b, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fsub_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags)); + } } -void dpi_fnmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fmul(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fnmadd_s(a, b, c, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fmul_d(a, b, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fmul_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags)); + } } -void dpi_fnmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fnmsub_s(a, b, c, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fmadd_d(a, b, c, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fmadd_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags)); + } } -void dpi_fdiv(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fdiv_s(a, b, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fmsub_d(a, b, c, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fmsub_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags)); + } } -void dpi_fsqrt(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fnmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fsqrt_s(a, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fnmadd_d(a, b, c, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fnmadd_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags)); + } } -void dpi_ftoi(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fnmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_ftoi_s(a, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fnmsub_d(a, b, c, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fnmsub_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags)); + } } -void dpi_ftou(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fdiv(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_ftou_s(a, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fdiv_d(a, b, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fdiv_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags)); + } } -void dpi_itof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_fsqrt(bool enable, int dst_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_itof_s(a, (*frm & 0x7), fflags); + if (dst_fmt) { + *result = rv_fsqrt_d(a, (*frm & 0x7), fflags); + } else { + *result = nan_box(rv_fsqrt_s(check_boxing(a), (*frm & 0x7), fflags)); + } } -void dpi_utof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) { +void dpi_ftoi(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_utof_s(a, (*frm & 0x7), fflags); + if (dst_fmt) { + if (src_fmt) { + *result = rv_ftol_d(a, (*frm & 0x7), fflags); + } else { + *result = rv_ftol_s(check_boxing(a), (*frm & 0x7), fflags); + } + } else { + if (src_fmt) { + *result = sext(rv_ftoi_d(a, (*frm & 0x7), fflags), 32); + } else { + *result = sext(rv_ftoi_s(check_boxing(a), (*frm & 0x7), fflags), 32); + } + } } -void dpi_flt(bool enable, int a, int b, int* result, svBitVecVal* fflags) { +void dpi_ftou(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_flt_s(a, b, fflags); + if (dst_fmt) { + if (src_fmt) { + *result = rv_ftolu_d(a, (*frm & 0x7), fflags); + } else { + *result = rv_ftolu_s(check_boxing(a), (*frm & 0x7), fflags); + } + } else { + if (src_fmt) { + *result = sext(rv_ftou_d(a, (*frm & 0x7), fflags), 32); + } else { + *result = sext(rv_ftou_s(check_boxing(a), (*frm & 0x7), fflags), 32); + } + } } -void dpi_fle(bool enable, int a, int b, int* result, svBitVecVal* fflags) { +void dpi_itof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fle_s(a, b, fflags); + if (dst_fmt) { + if (src_fmt) { + *result = rv_ltof_d(a, (*frm & 0x7), fflags); + } else { + *result = rv_itof_d(a, (*frm & 0x7), fflags); + } + } else { + if (src_fmt) { + *result = nan_box(rv_ltof_s(a, (*frm & 0x7), fflags)); + } else { + *result = nan_box(rv_itof_s(a, (*frm & 0x7), fflags)); + } + } } -void dpi_feq(bool enable, int a, int b, int* result, svBitVecVal* fflags) { +void dpi_utof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_feq_s(a, b, fflags); + if (dst_fmt) { + if (src_fmt) { + *result = rv_lutof_d(a, (*frm & 0x7), fflags); + } else { + *result = rv_utof_d(a, (*frm & 0x7), fflags); + } + } else { + if (src_fmt) { + *result = nan_box(rv_lutof_s(a, (*frm & 0x7), fflags)); + } else { + *result = nan_box(rv_utof_s(a, (*frm & 0x7), fflags)); + } + } } -void dpi_fmin(bool enable, int a, int b, int* result, svBitVecVal* fflags) { +void dpi_f2f(bool enable, int dst_fmt, int64_t a, int64_t* result) { if (!enable) return; - *result = rv_fmin_s(a, b, fflags); + if (dst_fmt) { + *result = rv_ftod((int32_t)check_boxing(a)); + } else { + *result = nan_box(rv_dtof(a)); + } } -void dpi_fmax(bool enable, int a, int b, int* result, svBitVecVal* fflags) { +void dpi_fclss(bool enable, int dst_fmt, int64_t a, int64_t* result) { if (!enable) return; - *result = rv_fmax_s(a, b, fflags); + if (dst_fmt) { + *result = rv_fclss_d(a); + } else { + *result = rv_fclss_s(check_boxing(a)); + } } -void dpi_fclss(bool enable, int a, int* result) { +void dpi_fsgnj(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result) { if (!enable) return; - *result = rv_fclss_s(a); + if (dst_fmt) { + *result = rv_fsgnj_d(a, b); + } else { + *result = nan_box(rv_fsgnj_s(check_boxing(a), check_boxing(b))); + } } -void dpi_fsgnj(bool enable, int a, int b, int* result) { +void dpi_fsgnjn(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result) { if (!enable) return; - *result = rv_fsgnj_s(a, b); + if (dst_fmt) { + *result = rv_fsgnjn_d(a, b); + } else { + *result = nan_box(rv_fsgnjn_s(check_boxing(a), check_boxing(b))); + } } -void dpi_fsgnjn(bool enable, int a, int b, int* result) { +void dpi_fsgnjx(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result) { if (!enable) return; - *result = rv_fsgnjn_s(a, b); + if (dst_fmt) { + *result = rv_fsgnjx_d(a, b); + } else { + *result = nan_box(rv_fsgnjx_s(check_boxing(a), check_boxing(b))); + } } -void dpi_fsgnjx(bool enable, int a, int b, int* result) { +void dpi_flt(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) { if (!enable) return; - *result = rv_fsgnjx_s(a, b); + if (dst_fmt) { + *result = rv_flt_d(a, b, fflags); + } else { + *result = rv_flt_s(check_boxing(a), check_boxing(b), fflags); + } +} + +void dpi_fle(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) { + if (!enable) + return; + if (dst_fmt) { + *result = rv_fle_d(a, b, fflags); + } else { + *result = rv_fle_s(check_boxing(a), check_boxing(b), fflags); + } +} + +void dpi_feq(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) { + if (!enable) + return; + if (dst_fmt) { + *result = rv_feq_d(a, b, fflags); + } else { + *result = rv_feq_s(check_boxing(a), check_boxing(b), fflags); + } +} + +void dpi_fmin(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) { + if (!enable) + return; + if (dst_fmt) { + *result = rv_fmin_d(a, b, fflags); + } else { + *result = nan_box(rv_fmin_s(check_boxing(a), check_boxing(b), fflags)); + } +} + +void dpi_fmax(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) { + if (!enable) + return; + if (dst_fmt) { + *result = rv_fmax_d(a, b, fflags); + } else { + *result = nan_box(rv_fmax_s(check_boxing(a), check_boxing(b), fflags)); + } } \ No newline at end of file diff --git a/hw/dpi/float_dpi.vh b/hw/dpi/float_dpi.vh index 968f8028..13580765 100644 --- a/hw/dpi/float_dpi.vh +++ b/hw/dpi/float_dpi.vh @@ -1,31 +1,47 @@ -`ifndef FLOAT_DPI -`define FLOAT_DPI +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. -import "DPI-C" function void dpi_fadd(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fsub(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fmul(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fmadd(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fmsub(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fnmadd(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fnmsub(input logic enable, input int a, input int b, input int c, input bit[2:0] frm, output int result, output bit[4:0] fflags); +`ifndef FLOAT_DPI_VH +`define FLOAT_DPI_VH -import "DPI-C" function void dpi_fdiv(input logic enable, input int a, input int b, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fsqrt(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); +`include "VX_config.vh" -import "DPI-C" function void dpi_ftoi(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_ftou(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_itof(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_utof(input logic enable, input int a, input bit[2:0] frm, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fadd(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fsub(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmul(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmadd(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmsub(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fnmadd(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fnmsub(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fclss(input logic enable, input int a, output int result); -import "DPI-C" function void dpi_fsgnj(input logic enable, input int a, input int b, output int result); -import "DPI-C" function void dpi_fsgnjn(input logic enable, input int a, input int b, output int result); -import "DPI-C" function void dpi_fsgnjx(input logic enable, input int a, input int b, output int result); +import "DPI-C" function void dpi_fdiv(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fsqrt(input logic enable, input int dst_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); -import "DPI-C" function void dpi_flt(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fle(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_feq(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fmin(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); -import "DPI-C" function void dpi_fmax(input logic enable, input int a, input int b, output int result, output bit[4:0] fflags); +import "DPI-C" function void dpi_ftoi(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_ftou(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_itof(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_utof(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_f2f(input logic enable, input int dst_fmt, input longint a, output longint result); -`endif \ No newline at end of file +import "DPI-C" function void dpi_fclss(input logic enable, input int dst_fmt, input longint a, output longint result); +import "DPI-C" function void dpi_fsgnj(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result); +import "DPI-C" function void dpi_fsgnjn(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result); +import "DPI-C" function void dpi_fsgnjx(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result); + +import "DPI-C" function void dpi_flt(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fle(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_feq(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmin(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmax(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); + +`endif diff --git a/hw/dpi/util_dpi.cpp b/hw/dpi/util_dpi.cpp index a8db1a53..faf121cf 100644 --- a/hw/dpi/util_dpi.cpp +++ b/hw/dpi/util_dpi.cpp @@ -1,23 +1,57 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include #include #include #include #include #include + #include "svdpi.h" #include "verilated_vpi.h" #include "VX_config.h" +#include "uuid_gen.h" + +#ifdef XLEN_64 +#define iword_t int64_t +#define uword_t uint64_t +#define idword_t __int128_t +#define udword_t __uint128_t +#else +#define iword_t int32_t +#define uword_t uint32_t +#define idword_t int64_t +#define udword_t uint64_t +#endif + +#ifndef DEBUG_LEVEL +#define DEBUG_LEVEL 3 +#endif + extern "C" { - void dpi_imul(bool enable, int a, int b, bool is_signed_a, bool is_signed_b, int* resultl, int* resulth); - void dpi_idiv(bool enable, int a, int b, bool is_signed, int* quotient, int* remainder); + void dpi_imul(bool enable, bool is_signed_a, bool is_signed_b, iword_t a, iword_t b, iword_t* resultl, iword_t* resulth); + void dpi_idiv(bool enable, bool is_signed, iword_t a, iword_t b, iword_t* quotient, iword_t* remainder); int dpi_register(); void dpi_assert(int inst, bool cond, int delay); - void dpi_trace(const char* format, ...); + void dpi_trace(int level, const char* format, ...); void dpi_trace_start(); void dpi_trace_stop(); + + uint64_t dpi_uuid_gen(bool reset, int wid, uint64_t PC); } bool sim_trace_enabled(); @@ -93,49 +127,54 @@ void dpi_assert(int inst, bool cond, int delay) { } } -void dpi_imul(bool enable, int a, int b, bool is_signed_a, bool is_signed_b, int* resultl, int* resulth) { +/////////////////////////////////////////////////////////////////////////////// + +void dpi_imul(bool enable, bool is_signed_a, bool is_signed_b, iword_t a, iword_t b, iword_t* resultl, iword_t* resulth) { if (!enable) return; + udword_t first = *(uword_t*)&a; + udword_t second = *(uword_t*)&b; + + udword_t mask = udword_t(-1) << (8 * sizeof(iword_t)); - uint64_t first = *(uint32_t*)&a; - uint64_t second = *(uint32_t*)&b; - - if (is_signed_a && (first & 0x80000000)) { - first |= 0xFFFFFFFF00000000; + if (is_signed_a && a < 0) { + first |= mask; } - if (is_signed_b && (second & 0x80000000)) { - second |= 0xFFFFFFFF00000000; + if (is_signed_b && b < 0) { + second |= mask; } - uint64_t result; + udword_t result; if (is_signed_a || is_signed_b) { - result = (int64_t)first * (int64_t)second; + result = idword_t(first) * idword_t(second); } else { result = first * second; - } - - *resultl = result & 0xFFFFFFFF; - *resulth = (result >> 32) & 0xFFFFFFFF; + } + + *resultl = iword_t(result); + *resulth = iword_t(result >> (8 * sizeof(iword_t))); } -void dpi_idiv(bool enable, int a, int b, bool is_signed, int* quotient, int* remainder) { +void dpi_idiv(bool enable, bool is_signed, iword_t a, iword_t b, iword_t* quotient, iword_t* remainder) { if (!enable) return; - uint32_t dividen = *(uint32_t*)&a; - uint32_t divisor = *(uint32_t*)&b; + uword_t dividen = a; + uword_t divisor = b; + + auto inf_neg = uword_t(1) << (XLEN-1); if (is_signed) { if (b == 0) { *quotient = -1; *remainder = dividen; - } else if (dividen == 0x80000000 && divisor == 0xffffffff) { + } else if (dividen == inf_neg && divisor == -1) { *remainder = 0; *quotient = dividen; } else { - *quotient = (int32_t)dividen / (int32_t)divisor; - *remainder = (int32_t)dividen % (int32_t)divisor; + *quotient = (iword_t)dividen / (iword_t)divisor; + *remainder = (iword_t)dividen % (iword_t)divisor; } } else { if (b == 0) { @@ -148,7 +187,11 @@ void dpi_idiv(bool enable, int a, int b, bool is_signed, int* quotient, int* rem } } -void dpi_trace(const char* format, ...) { +/////////////////////////////////////////////////////////////////////////////// + +void dpi_trace(int level, const char* format, ...) { + if (level > DEBUG_LEVEL) + return; if (!sim_trace_enabled()) return; va_list va; @@ -163,4 +206,28 @@ void dpi_trace_start() { void dpi_trace_stop() { sim_trace_enable(false); +} + +/////////////////////////////////////////////////////////////////////////////// + +std::unordered_map> g_uuid_gens; + +uint64_t dpi_uuid_gen(bool reset, int wid, uint64_t PC) { + if (reset) { + g_uuid_gens.clear(); + return 0; + } + std::shared_ptr uuid_gen; + auto it = g_uuid_gens.find(wid); + if (it == g_uuid_gens.end()) { + uuid_gen = std::make_shared(); + g_uuid_gens.emplace(wid, uuid_gen); + } else { + uuid_gen = it->second; + } + uint32_t instr_uuid = uuid_gen->get_uuid(PC); + uint32_t instr_id = instr_uuid & 0xffff; + uint32_t instr_ref = instr_uuid >> 16; + uint64_t uuid = (uint64_t(instr_ref) << 32) | (wid << 16) | instr_id; + return uuid; } \ No newline at end of file diff --git a/hw/dpi/util_dpi.vh b/hw/dpi/util_dpi.vh index c1306ff4..42a736ed 100644 --- a/hw/dpi/util_dpi.vh +++ b/hw/dpi/util_dpi.vh @@ -1,14 +1,37 @@ -`ifndef UTIL_DPI -`define UTIL_DPI +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. -import "DPI-C" function void dpi_imul(input logic enable, input int a, input int b, input logic is_signed_a, input logic is_signed_b, output int resultl, output int resulth); -import "DPI-C" function void dpi_idiv(input logic enable, input int a, input int b, input logic is_signed, output int quotient, output int remainder); +`ifndef UTIL_DPI_VH +`define UTIL_DPI_VH + +`include "VX_config.vh" + +`ifdef XLEN_64 +`define INT_TYPE longint +`else +`define INT_TYPE int +`endif + +import "DPI-C" function void dpi_imul(input logic enable, input logic is_signed_a, input logic is_signed_b, input `INT_TYPE a, input `INT_TYPE b, output `INT_TYPE resultl, output `INT_TYPE resulth); +import "DPI-C" function void dpi_idiv(input logic enable, input logic is_signed, input `INT_TYPE a, input `INT_TYPE b, output `INT_TYPE quotient, output `INT_TYPE remainder); import "DPI-C" function int dpi_register(); import "DPI-C" function void dpi_assert(int inst, input logic cond, input int delay); -import "DPI-C" function void dpi_trace(input string format /*verilator sformat*/); +import "DPI-C" function void dpi_trace(input int level, input string format /*verilator sformat*/); import "DPI-C" function void dpi_trace_start(); import "DPI-C" function void dpi_trace_stop(); -`endif \ No newline at end of file +import "DPI-C" function longint dpi_uuid_gen(input logic reset, input int wid, input longint PC); + +`endif diff --git a/hw/rtl/.gitignore b/hw/rtl/.gitignore deleted file mode 100644 index a98a6b43..00000000 --- a/hw/rtl/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/VX_user_config.vh \ No newline at end of file diff --git a/hw/rtl/VX_alu_unit.sv b/hw/rtl/VX_alu_unit.sv deleted file mode 100644 index d4a79d46..00000000 --- a/hw/rtl/VX_alu_unit.sv +++ /dev/null @@ -1,235 +0,0 @@ -`include "VX_define.vh" - -module VX_alu_unit #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // Inputs - VX_alu_req_if.slave alu_req_if, - - // Outputs - VX_branch_ctl_if.master branch_ctl_if, - VX_commit_if.master alu_commit_if -); - - `UNUSED_PARAM (CORE_ID) - - reg [`NUM_THREADS-1:0][31:0] alu_result; - wire [`NUM_THREADS-1:0][31:0] add_result; - wire [`NUM_THREADS-1:0][32:0] sub_result; - wire [`NUM_THREADS-1:0][31:0] shr_result; - reg [`NUM_THREADS-1:0][31:0] msc_result; - - wire ready_in; - - `UNUSED_VAR (alu_req_if.op_mod) - wire is_br_op = `INST_ALU_IS_BR(alu_req_if.op_mod); - wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_BITS'(alu_req_if.op_type); - wire [`INST_BR_BITS-1:0] br_op = `INST_BR_BITS'(alu_req_if.op_type); - wire alu_signed = `INST_ALU_SIGNED(alu_op); - wire [1:0] alu_op_class = `INST_ALU_OP_CLASS(alu_op); - wire is_sub = (alu_op == `INST_ALU_SUB); - - wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data; - wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data; - - wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.use_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1; - wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.use_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2; - wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.use_imm && ~is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i]; - end - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [32:0] sub_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]}; - wire [32:0] sub_in2 = {alu_signed & alu_in2_less[i][31], alu_in2_less[i]}; - assign sub_result[i] = sub_in1 - sub_in2; - end - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [32:0] shr_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]}; - assign shr_result[i] = 32'($signed(shr_in1) >>> alu_in2_imm[i][4:0]); - end - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - always @(*) begin - case (alu_op) - `INST_ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; - `INST_ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; - `INST_ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; - //`INST_ALU_SLL, - default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0]; - endcase - end - end - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - always @(*) begin - case (alu_op_class) - 2'b00: alu_result[i] = add_result[i]; // ADD, LUI, AUIPC - 2'b01: alu_result[i] = {31'b0, sub_result[i][32]}; // SLTU, SLT - 2'b10: alu_result[i] = is_sub ? sub_result[i][31:0] // SUB - : shr_result[i]; // SRL, SRA - // 2'b11, - default: alu_result[i] = msc_result[i]; // AND, OR, XOR, SLL - endcase - end - end - - // branch - - wire is_jal = is_br_op && (br_op == `INST_BR_JAL || br_op == `INST_BR_JALR); - wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result; - - wire [31:0] br_dest = add_result[alu_req_if.tid]; - wire [32:0] cmp_result = sub_result[alu_req_if.tid]; - - wire is_less = cmp_result[32]; - wire is_equal = ~(| cmp_result[31:0]); - - // output - - wire alu_valid_in; - wire alu_ready_in; - wire alu_valid_out; - wire alu_ready_out; - wire [`UUID_BITS-1:0] alu_uuid; - wire [`NW_BITS-1:0] alu_wid; - wire [`NUM_THREADS-1:0] alu_tmask; - wire [31:0] alu_PC; - wire [`NR_BITS-1:0] alu_rd; - wire alu_wb; - wire [`NUM_THREADS-1:0][31:0] alu_data; - - wire [`INST_BR_BITS-1:0] br_op_r; - wire [31:0] br_dest_r; - wire is_less_r; - wire is_equal_r; - wire is_br_op_r; - - assign alu_ready_in = alu_ready_out || ~alu_valid_out; - - VX_pipe_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `INST_BR_BITS + 1 + 1 + 32), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (alu_ready_in), - .data_in ({alu_valid_in, alu_req_if.uuid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, is_less, is_equal, br_dest}), - .data_out ({alu_valid_out, alu_uuid, alu_wid, alu_tmask, alu_PC, alu_rd, alu_wb, alu_data, is_br_op_r, br_op_r, is_less_r, is_equal_r, br_dest_r}) - ); - - `UNUSED_VAR (br_op_r) - wire br_neg = `INST_BR_NEG(br_op_r); - wire br_less = `INST_BR_LESS(br_op_r); - wire br_static = `INST_BR_STATIC(br_op_r); - - assign branch_ctl_if.valid = alu_valid_out && alu_ready_out && is_br_op_r; - assign branch_ctl_if.taken = ((br_less ? is_less_r : is_equal_r) ^ br_neg) | br_static; - assign branch_ctl_if.wid = alu_wid; - assign branch_ctl_if.dest = br_dest_r; - -`ifdef EXT_M_ENABLE - - wire mul_valid_in; - wire mul_ready_in; - wire mul_valid_out; - wire mul_ready_out; - wire [`UUID_BITS-1:0] mul_uuid; - wire [`NW_BITS-1:0] mul_wid; - wire [`NUM_THREADS-1:0] mul_tmask; - wire [31:0] mul_PC; - wire [`NR_BITS-1:0] mul_rd; - wire mul_wb; - wire [`NUM_THREADS-1:0][31:0] mul_data; - - wire [`INST_MUL_BITS-1:0] mul_op = `INST_MUL_BITS'(alu_req_if.op_type); - - VX_muldiv muldiv ( - .clk (clk), - .reset (reset), - - // Inputs - .alu_op (mul_op), - .uuid_in (alu_req_if.uuid), - .wid_in (alu_req_if.wid), - .tmask_in (alu_req_if.tmask), - .PC_in (alu_req_if.PC), - .rd_in (alu_req_if.rd), - .wb_in (alu_req_if.wb), - .alu_in1 (alu_req_if.rs1_data), - .alu_in2 (alu_req_if.rs2_data), - - // Outputs - .wid_out (mul_wid), - .uuid_out (mul_uuid), - .tmask_out (mul_tmask), - .PC_out (mul_PC), - .rd_out (mul_rd), - .wb_out (mul_wb), - .data_out (mul_data), - - // handshake - .valid_in (mul_valid_in), - .ready_in (mul_ready_in), - .valid_out (mul_valid_out), - .ready_out (mul_ready_out) - ); - - wire is_mul_op = `INST_ALU_IS_MUL(alu_req_if.op_mod); - - assign ready_in = is_mul_op ? mul_ready_in : alu_ready_in; - - assign alu_valid_in = alu_req_if.valid && ~is_mul_op; - assign mul_valid_in = alu_req_if.valid && is_mul_op; - - assign alu_commit_if.valid = alu_valid_out || mul_valid_out; - assign alu_commit_if.uuid = alu_valid_out ? alu_uuid : mul_uuid; - assign alu_commit_if.wid = alu_valid_out ? alu_wid : mul_wid; - assign alu_commit_if.tmask = alu_valid_out ? alu_tmask : mul_tmask; - assign alu_commit_if.PC = alu_valid_out ? alu_PC : mul_PC; - assign alu_commit_if.rd = alu_valid_out ? alu_rd : mul_rd; - assign alu_commit_if.wb = alu_valid_out ? alu_wb : mul_wb; - assign alu_commit_if.data = alu_valid_out ? alu_data : mul_data; - - assign alu_ready_out = alu_commit_if.ready; - assign mul_ready_out = alu_commit_if.ready & ~alu_valid_out; // ALU takes priority - -`else - - assign ready_in = alu_ready_in; - - assign alu_valid_in = alu_req_if.valid; - - assign alu_commit_if.valid = alu_valid_out; - assign alu_commit_if.uuid = alu_uuid; - assign alu_commit_if.wid = alu_wid; - assign alu_commit_if.tmask = alu_tmask; - assign alu_commit_if.PC = alu_PC; - assign alu_commit_if.rd = alu_rd; - assign alu_commit_if.wb = alu_wb; - assign alu_commit_if.data = alu_data; - - assign alu_ready_out = alu_commit_if.ready; - -`endif - - assign alu_commit_if.eop = 1'b1; - - // can accept new request? - assign alu_req_if.ready = ready_in; - -`ifdef DBG_TRACE_CORE_PIPELINE - always @(posedge clk) begin - if (branch_ctl_if.valid) begin - dpi_trace("%d: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h (#%0d)\n", - $time, CORE_ID, branch_ctl_if.wid, alu_commit_if.PC, branch_ctl_if.taken, branch_ctl_if.dest, alu_uuid); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_cache_arb.sv b/hw/rtl/VX_cache_arb.sv deleted file mode 100644 index 85800edf..00000000 --- a/hw/rtl/VX_cache_arb.sv +++ /dev/null @@ -1,159 +0,0 @@ -`include "VX_define.vh" - -module VX_cache_arb #( - parameter NUM_REQS = 1, - parameter LANES = 1, - parameter DATA_SIZE = 1, - parameter TAG_IN_WIDTH = 1, - parameter TAG_SEL_IDX = 0, - parameter BUFFERED_REQ = 0, - parameter BUFFERED_RSP = 0, - parameter TYPE = "R", - - localparam ADDR_WIDTH = (32-`CLOG2(DATA_SIZE)), - localparam DATA_WIDTH = (8 * DATA_SIZE), - localparam LOG_NUM_REQS = `CLOG2(NUM_REQS), - localparam TAG_OUT_WIDTH = TAG_IN_WIDTH + LOG_NUM_REQS -) ( - input wire clk, - input wire reset, - - // input requests - input wire [NUM_REQS-1:0][LANES-1:0] req_valid_in, - input wire [NUM_REQS-1:0][LANES-1:0] req_rw_in, - input wire [NUM_REQS-1:0][LANES-1:0][DATA_SIZE-1:0] req_byteen_in, - input wire [NUM_REQS-1:0][LANES-1:0][ADDR_WIDTH-1:0] req_addr_in, - input wire [NUM_REQS-1:0][LANES-1:0][DATA_WIDTH-1:0] req_data_in, - input wire [NUM_REQS-1:0][LANES-1:0][TAG_IN_WIDTH-1:0] req_tag_in, - output wire [NUM_REQS-1:0][LANES-1:0] req_ready_in, - - // output request - output wire [LANES-1:0] req_valid_out, - output wire [LANES-1:0] req_rw_out, - output wire [LANES-1:0][DATA_SIZE-1:0] req_byteen_out, - output wire [LANES-1:0][ADDR_WIDTH-1:0] req_addr_out, - output wire [LANES-1:0][DATA_WIDTH-1:0] req_data_out, - output wire [LANES-1:0][TAG_OUT_WIDTH-1:0] req_tag_out, - input wire [LANES-1:0] req_ready_out, - - // input response - input wire rsp_valid_in, - input wire [LANES-1:0] rsp_tmask_in, - input wire [LANES-1:0][DATA_WIDTH-1:0] rsp_data_in, - input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in, - output wire rsp_ready_in, - - // output responses - output wire [NUM_REQS-1:0] rsp_valid_out, - output wire [NUM_REQS-1:0][LANES-1:0] rsp_tmask_out, - output wire [NUM_REQS-1:0][LANES-1:0][DATA_WIDTH-1:0] rsp_data_out, - output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out, - input wire [NUM_REQS-1:0] rsp_ready_out -); - localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH; - localparam RSP_DATAW = LANES * (1 + DATA_WIDTH) + TAG_IN_WIDTH; - - if (NUM_REQS > 1) begin - - wire [NUM_REQS-1:0][LANES-1:0][REQ_DATAW-1:0] req_data_in_merged; - wire [LANES-1:0][REQ_DATAW-1:0] req_data_out_merged; - - for (genvar i = 0; i < NUM_REQS; i++) begin - for (genvar j = 0; j < LANES; ++j) begin - wire [TAG_OUT_WIDTH-1:0] req_tag_in_w; - - VX_bits_insert #( - .N (TAG_IN_WIDTH), - .S (LOG_NUM_REQS), - .POS (TAG_SEL_IDX) - ) bits_insert ( - .data_in (req_tag_in[i][j]), - .sel_in (LOG_NUM_REQS'(i)), - .data_out (req_tag_in_w) - ); - - assign req_data_in_merged[i][j] = {req_tag_in_w, req_addr_in[i][j], req_rw_in[i][j], req_byteen_in[i][j], req_data_in[i][j]}; - end - end - - VX_stream_arbiter #( - .NUM_REQS (NUM_REQS), - .LANES (LANES), - .DATAW (REQ_DATAW), - .BUFFERED (BUFFERED_REQ), - .TYPE (TYPE) - ) req_arb ( - .clk (clk), - .reset (reset), - .valid_in (req_valid_in), - .data_in (req_data_in_merged), - .ready_in (req_ready_in), - .valid_out (req_valid_out), - .data_out (req_data_out_merged), - .ready_out (req_ready_out) - ); - - for (genvar i = 0; i < LANES; ++i) begin - assign {req_tag_out[i], req_addr_out[i], req_rw_out[i], req_byteen_out[i], req_data_out[i]} = req_data_out_merged[i]; - end - - /////////////////////////////////////////////////////////////////////// - - wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out_merged; - - wire [LOG_NUM_REQS-1:0] rsp_sel = rsp_tag_in[TAG_SEL_IDX +: LOG_NUM_REQS]; - - wire [TAG_IN_WIDTH-1:0] rsp_tag_in_w; - - VX_bits_remove #( - .N (TAG_OUT_WIDTH), - .S (LOG_NUM_REQS), - .POS (TAG_SEL_IDX) - ) bits_remove ( - .data_in (rsp_tag_in), - .data_out (rsp_tag_in_w) - ); - - VX_stream_demux #( - .NUM_REQS (NUM_REQS), - .LANES (1), - .DATAW (RSP_DATAW), - .BUFFERED (BUFFERED_RSP) - ) rsp_demux ( - .clk (clk), - .reset (reset), - .sel_in (rsp_sel), - .valid_in (rsp_valid_in), - .data_in ({rsp_tmask_in, rsp_tag_in_w, rsp_data_in}), - .ready_in (rsp_ready_in), - .valid_out (rsp_valid_out), - .data_out (rsp_data_out_merged), - .ready_out (rsp_ready_out) - ); - - for (genvar i = 0; i < NUM_REQS; i++) begin - assign {rsp_tmask_out[i], rsp_tag_out[i], rsp_data_out[i]} = rsp_data_out_merged[i]; - end - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - assign req_valid_out = req_valid_in; - assign req_tag_out = req_tag_in; - assign req_addr_out = req_addr_in; - assign req_rw_out = req_rw_in; - assign req_byteen_out = req_byteen_in; - assign req_data_out = req_data_in; - assign req_ready_in = req_ready_out; - - assign rsp_valid_out = rsp_valid_in; - assign rsp_tmask_out = rsp_tmask_in; - assign rsp_tag_out = rsp_tag_in; - assign rsp_data_out = rsp_data_in; - assign rsp_ready_in = rsp_ready_out; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_cluster.sv b/hw/rtl/VX_cluster.sv index be933ae6..782bde9a 100644 --- a/hw/rtl/VX_cluster.sv +++ b/hw/rtl/VX_cluster.sv @@ -1,195 +1,155 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_define.vh" -module VX_cluster #( +module VX_cluster import VX_gpu_pkg::*; #( parameter CLUSTER_ID = 0 ) ( - `SCOPE_IO_VX_cluster + `SCOPE_IO_DECL // Clock - input wire clk, - input wire reset, + input wire clk, + input wire reset, - // Memory request - output wire mem_req_valid, - output wire mem_req_rw, - output wire [`L2_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, - output wire [`L2_MEM_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`L2_MEM_DATA_WIDTH-1:0] mem_req_data, - output wire [`L2_MEM_TAG_WIDTH-1:0] mem_req_tag, - input wire mem_req_ready, +`ifdef PERF_ENABLE + VX_mem_perf_if.master mem_perf_if, + VX_mem_perf_if.slave perf_memsys_total_if, +`endif - // Memory response - input wire mem_rsp_valid, - input wire [`L2_MEM_DATA_WIDTH-1:0] mem_rsp_data, - input wire [`L2_MEM_TAG_WIDTH-1:0] mem_rsp_tag, - output wire mem_rsp_ready, + VX_dcr_bus_if.slave dcr_bus_if, + + // Memory + VX_mem_bus_if.master mem_bus_if, + + // simulation helper signals + output wire sim_ebreak, + output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value, // Status - output wire busy -); - `STATIC_ASSERT((`L2_ENABLE == 0 || `NUM_CORES > 1), ("invalid parameter")) + output wire busy +); - wire [`NUM_CORES-1:0] per_core_mem_req_valid; - wire [`NUM_CORES-1:0] per_core_mem_req_rw; - wire [`NUM_CORES-1:0][`DCACHE_MEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen; - wire [`NUM_CORES-1:0][`DCACHE_MEM_ADDR_WIDTH-1:0] per_core_mem_req_addr; - wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_req_data; - wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_req_tag; - wire [`NUM_CORES-1:0] per_core_mem_req_ready; +`ifdef SCOPE + localparam scope_socket = 0; + `SCOPE_IO_SWITCH (scope_socket + `NUM_SOCKETS); +`endif - wire [`NUM_CORES-1:0] per_core_mem_rsp_valid; - wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_rsp_data; - wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag; - wire [`NUM_CORES-1:0] per_core_mem_rsp_ready; +`ifdef GBAR_ENABLE - wire [`NUM_CORES-1:0] per_core_busy; + VX_gbar_bus_if per_socket_gbar_bus_if[`NUM_SOCKETS](); + VX_gbar_bus_if gbar_bus_if(); - for (genvar i = 0; i < `NUM_CORES; i++) begin + `RESET_RELAY (gbar_reset, reset); - `RESET_RELAY (core_reset); + VX_gbar_arb #( + .NUM_REQS (`NUM_SOCKETS), + .OUT_REG ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure + ) gbar_arb ( + .clk (clk), + .reset (gbar_reset), + .bus_in_if (per_socket_gbar_bus_if), + .bus_out_if (gbar_bus_if) + ); - VX_core #( - .CORE_ID(i + (CLUSTER_ID * `NUM_CORES)) - ) core ( - `SCOPE_BIND_VX_cluster_core(i) + VX_gbar_unit #( + .INSTANCE_ID ($sformatf("gbar%0d", CLUSTER_ID)) + ) gbar_unit ( + .clk (clk), + .reset (gbar_reset), + .gbar_bus_if (gbar_bus_if) + ); +`endif - .clk (clk), - .reset (core_reset), - - .mem_req_valid (per_core_mem_req_valid[i]), - .mem_req_rw (per_core_mem_req_rw [i]), - .mem_req_byteen (per_core_mem_req_byteen[i]), - .mem_req_addr (per_core_mem_req_addr [i]), - .mem_req_data (per_core_mem_req_data [i]), - .mem_req_tag (per_core_mem_req_tag [i]), - .mem_req_ready (per_core_mem_req_ready[i]), - - .mem_rsp_valid (per_core_mem_rsp_valid[i]), - .mem_rsp_data (per_core_mem_rsp_data [i]), - .mem_rsp_tag (per_core_mem_rsp_tag [i]), - .mem_rsp_ready (per_core_mem_rsp_ready[i]), - - .busy (per_core_busy [i]) - ); - end + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_ARB_TAG_WIDTH) + ) per_socket_dcache_bus_if[`NUM_SOCKETS * DCACHE_NUM_REQS](); - assign busy = (| per_core_busy); + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_WORD_SIZE), + .TAG_WIDTH (ICACHE_ARB_TAG_WIDTH) + ) per_socket_icache_bus_if[`NUM_SOCKETS](); + + `RESET_RELAY (mem_unit_reset, reset); + + VX_mem_unit #( + .CLUSTER_ID (CLUSTER_ID) + ) mem_unit ( + .clk (clk), + .reset (mem_unit_reset), - if (`L2_ENABLE) begin `ifdef PERF_ENABLE - VX_perf_cache_if perf_l2cache_if(); + .mem_perf_if (mem_perf_if), `endif - `RESET_RELAY (l2_reset); + .dcache_bus_if (per_socket_dcache_bus_if), + + .icache_bus_if (per_socket_icache_bus_if), - VX_cache #( - .CACHE_ID (`L2_CACHE_ID), - .CACHE_SIZE (`L2_CACHE_SIZE), - .CACHE_LINE_SIZE (`L2_CACHE_LINE_SIZE), - .NUM_BANKS (`L2_NUM_BANKS), - .NUM_PORTS (`L2_NUM_PORTS), - .WORD_SIZE (`L2_WORD_SIZE), - .NUM_REQS (`L2_NUM_REQS), - .CREQ_SIZE (`L2_CREQ_SIZE), - .CRSQ_SIZE (`L2_CRSQ_SIZE), - .MSHR_SIZE (`L2_MSHR_SIZE), - .MRSQ_SIZE (`L2_MRSQ_SIZE), - .MREQ_SIZE (`L2_MREQ_SIZE), - .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`L1_MEM_TAG_WIDTH), - .CORE_TAG_ID_BITS (0), - .MEM_TAG_WIDTH (`L2_MEM_TAG_WIDTH), - .NC_ENABLE (1) - ) l2cache ( - `SCOPE_BIND_VX_cluster_l2cache - - .clk (clk), - .reset (l2_reset), + .mem_bus_if (mem_bus_if) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire [`NUM_SOCKETS-1:0] per_socket_sim_ebreak; + wire [`NUM_SOCKETS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_socket_sim_wb_value; + assign sim_ebreak = per_socket_sim_ebreak[0]; + assign sim_wb_value = per_socket_sim_wb_value[0]; + `UNUSED_VAR (per_socket_sim_ebreak) + `UNUSED_VAR (per_socket_sim_wb_value) + + VX_dcr_bus_if socket_dcr_bus_tmp_if(); + assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END); + assign socket_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr; + assign socket_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data; + + wire [`NUM_SOCKETS-1:0] per_socket_busy; + + `BUFFER_DCR_BUS_IF (socket_dcr_bus_if, socket_dcr_bus_tmp_if, (`NUM_SOCKETS > 1)); + + // Generate all sockets + for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin + + `RESET_RELAY (socket_reset, reset); + + VX_socket #( + .SOCKET_ID ((CLUSTER_ID * `NUM_SOCKETS) + i) + ) socket ( + `SCOPE_IO_BIND (scope_socket+i) + .clk (clk), + .reset (socket_reset), `ifdef PERF_ENABLE - .perf_cache_if (perf_l2cache_if), + .mem_perf_if (perf_memsys_total_if), + `endif + + .dcr_bus_if (socket_dcr_bus_if), + + .dcache_bus_if (per_socket_dcache_bus_if[i * DCACHE_NUM_REQS +: DCACHE_NUM_REQS]), + + .icache_bus_if (per_socket_icache_bus_if[i]), + + `ifdef GBAR_ENABLE + .gbar_bus_if (per_socket_gbar_bus_if[i]), `endif - // Core request - .core_req_valid (per_core_mem_req_valid), - .core_req_rw (per_core_mem_req_rw), - .core_req_byteen (per_core_mem_req_byteen), - .core_req_addr (per_core_mem_req_addr), - .core_req_data (per_core_mem_req_data), - .core_req_tag (per_core_mem_req_tag), - .core_req_ready (per_core_mem_req_ready), - - // Core response - .core_rsp_valid (per_core_mem_rsp_valid), - .core_rsp_data (per_core_mem_rsp_data), - .core_rsp_tag (per_core_mem_rsp_tag), - .core_rsp_ready (per_core_mem_rsp_ready), - `UNUSED_PIN (core_rsp_tmask), - - // Memory request - .mem_req_valid (mem_req_valid), - .mem_req_rw (mem_req_rw), - .mem_req_byteen (mem_req_byteen), - .mem_req_addr (mem_req_addr), - .mem_req_data (mem_req_data), - .mem_req_tag (mem_req_tag), - .mem_req_ready (mem_req_ready), - - // Memory response - .mem_rsp_valid (mem_rsp_valid), - .mem_rsp_tag (mem_rsp_tag), - .mem_rsp_data (mem_rsp_data), - .mem_rsp_ready (mem_rsp_ready) + .sim_ebreak (per_socket_sim_ebreak[i]), + .sim_wb_value (per_socket_sim_wb_value[i]), + .busy (per_socket_busy[i]) ); - - end else begin - - `RESET_RELAY (mem_arb_reset); - - VX_mem_arb #( - .NUM_REQS (`NUM_CORES), - .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), - .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`L1_MEM_TAG_WIDTH), - .TYPE ("R"), - .TAG_SEL_IDX (1), // Skip 0 for NC flag - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) - ) mem_arb ( - .clk (clk), - .reset (mem_arb_reset), - - // Core request - .req_valid_in (per_core_mem_req_valid), - .req_rw_in (per_core_mem_req_rw), - .req_byteen_in (per_core_mem_req_byteen), - .req_addr_in (per_core_mem_req_addr), - .req_data_in (per_core_mem_req_data), - .req_tag_in (per_core_mem_req_tag), - .req_ready_in (per_core_mem_req_ready), - - // Memory request - .req_valid_out (mem_req_valid), - .req_rw_out (mem_req_rw), - .req_byteen_out (mem_req_byteen), - .req_addr_out (mem_req_addr), - .req_data_out (mem_req_data), - .req_tag_out (mem_req_tag), - .req_ready_out (mem_req_ready), - - // Core response - .rsp_valid_out (per_core_mem_rsp_valid), - .rsp_data_out (per_core_mem_rsp_data), - .rsp_tag_out (per_core_mem_rsp_tag), - .rsp_ready_out (per_core_mem_rsp_ready), - - // Memory response - .rsp_valid_in (mem_rsp_valid), - .rsp_tag_in (mem_rsp_tag), - .rsp_data_in (mem_rsp_data), - .rsp_ready_in (mem_rsp_ready) - ); - end + `BUFFER_BUSY (busy, (| per_socket_busy), (`NUM_SOCKETS > 1)); + endmodule diff --git a/hw/rtl/VX_commit.sv b/hw/rtl/VX_commit.sv deleted file mode 100644 index ef8ecc98..00000000 --- a/hw/rtl/VX_commit.sv +++ /dev/null @@ -1,138 +0,0 @@ -`include "VX_define.vh" - -module VX_commit #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // inputs - VX_commit_if.slave alu_commit_if, - VX_commit_if.slave ld_commit_if, - VX_commit_if.slave st_commit_if, - VX_commit_if.slave csr_commit_if, -`ifdef EXT_F_ENABLE - VX_commit_if.slave fpu_commit_if, -`endif - VX_commit_if.slave gpu_commit_if, - - // outputs - VX_writeback_if.master writeback_if, - VX_cmt_to_csr_if.master cmt_to_csr_if -); - // CSRs update - - wire alu_commit_fire = alu_commit_if.valid && alu_commit_if.ready; - wire ld_commit_fire = ld_commit_if.valid && ld_commit_if.ready; - wire st_commit_fire = st_commit_if.valid && st_commit_if.ready; - wire csr_commit_fire = csr_commit_if.valid && csr_commit_if.ready; -`ifdef EXT_F_ENABLE - wire fpu_commit_fire = fpu_commit_if.valid && fpu_commit_if.ready; -`endif - wire gpu_commit_fire = gpu_commit_if.valid && gpu_commit_if.ready; - - wire commit_fire = alu_commit_fire - || ld_commit_fire - || st_commit_fire - || csr_commit_fire - `ifdef EXT_F_ENABLE - || fpu_commit_fire - `endif - || gpu_commit_fire; - -`ifdef EXT_F_ENABLE - wire [(6*`NUM_THREADS)-1:0] commit_tmask; -`else - wire [(5*`NUM_THREADS)-1:0] commit_tmask; -`endif - - wire [$clog2($bits(commit_tmask)+1)-1:0] commit_size; - - assign commit_tmask = { - {`NUM_THREADS{alu_commit_fire}} & alu_commit_if.tmask, - {`NUM_THREADS{ld_commit_fire}} & ld_commit_if.tmask, - {`NUM_THREADS{st_commit_fire}} & st_commit_if.tmask, - {`NUM_THREADS{csr_commit_fire}} & csr_commit_if.tmask, - `ifdef EXT_F_ENABLE - {`NUM_THREADS{fpu_commit_fire}} & fpu_commit_if.tmask, - `endif - {`NUM_THREADS{gpu_commit_fire}} & gpu_commit_if.tmask - }; - - `POP_COUNT(commit_size, commit_tmask); - - VX_pipe_register #( - .DATAW (1 + $bits(commit_size)), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (1'b1), - .data_in ({commit_fire, commit_size}), - .data_out ({cmt_to_csr_if.valid, cmt_to_csr_if.commit_size}) - ); - - // Writeback - - VX_writeback #( - .CORE_ID(CORE_ID) - ) writeback ( - .clk (clk), - .reset (reset), - - .alu_commit_if (alu_commit_if), - .ld_commit_if (ld_commit_if), - .csr_commit_if (csr_commit_if), - `ifdef EXT_F_ENABLE - .fpu_commit_if (fpu_commit_if), - `endif - .gpu_commit_if (gpu_commit_if), - .writeback_if (writeback_if) - ); - - // store and gpu commits don't writeback - assign st_commit_if.ready = 1'b1; - -`ifdef DBG_TRACE_CORE_PIPELINE - always @(posedge clk) begin - if (alu_commit_if.valid && alu_commit_if.ready) begin - dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd); - `TRACE_ARRAY1D(alu_commit_if.data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", alu_commit_if.uuid); - end - if (ld_commit_if.valid && ld_commit_if.ready) begin - dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.wb, ld_commit_if.rd); - `TRACE_ARRAY1D(ld_commit_if.data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", ld_commit_if.uuid); - end - if (st_commit_if.valid && st_commit_if.ready) begin - dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d (#%0d)\n", $time, CORE_ID, st_commit_if.wid, st_commit_if.PC, st_commit_if.tmask, st_commit_if.wb, st_commit_if.rd, st_commit_if.uuid); - end - if (csr_commit_if.valid && csr_commit_if.ready) begin - dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=CSR, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.wb, csr_commit_if.rd); - `TRACE_ARRAY1D(csr_commit_if.data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", csr_commit_if.uuid); - end - `ifdef EXT_F_ENABLE - if (fpu_commit_if.valid && fpu_commit_if.ready) begin - dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.wb, fpu_commit_if.rd); - `TRACE_ARRAY1D(fpu_commit_if.data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", fpu_commit_if.uuid); - end - `endif - if (gpu_commit_if.valid && gpu_commit_if.ready) begin - dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=GPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.wb, gpu_commit_if.rd); - `TRACE_ARRAY1D(gpu_commit_if.data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", gpu_commit_if.uuid); - end - end -`endif - -endmodule - - - - - - - diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 8a8e8dcf..f5bdb2d2 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -1,7 +1,49 @@ -`ifndef VX_CONFIG -`define VX_CONFIG +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. -`ifndef XLEN +`ifndef VX_CONFIG_VH +`define VX_CONFIG_VH + +`ifndef MIN +`define MIN(x, y) (((x) < (y)) ? (x) : (y)) +`endif + +`ifndef MAX +`define MAX(x, y) (((x) > (y)) ? (x) : (y)) +`endif + +`ifndef CLAMP +`define CLAMP(x, lo, hi) (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x))) +`endif + +`ifndef UP +`define UP(x) (((x) != 0) ? (x) : 1) +`endif + +/////////////////////////////////////////////////////////////////////////////// + +// 32 bit XLEN as default. +`ifndef XLEN_32 +`ifndef XLEN_64 +`define XLEN_32 +`endif +`endif + +`ifdef XLEN_64 +`define XLEN 64 +`endif + +`ifdef XLEN_32 `define XLEN 32 `endif @@ -25,54 +67,127 @@ `define NUM_BARRIERS 4 `endif -`ifndef L2_ENABLE -`define L2_ENABLE 0 +`ifndef SOCKET_SIZE +`define SOCKET_SIZE `MIN(4, `NUM_CORES) `endif -`ifndef L3_ENABLE -`define L3_ENABLE 0 +`ifdef L2_ENABLE + `define L2_ENABLED 1 +`else + `define L2_ENABLED 0 `endif -`ifndef SM_ENABLE -`define SM_ENABLE 1 +`ifdef L3_ENABLE + `define L3_ENABLED 1 +`else + `define L3_ENABLED 0 +`endif + +`ifdef L1_DISABLE + `define ICACHE_DISABLE + `define DCACHE_DISABLE `endif `ifndef MEM_BLOCK_SIZE `define MEM_BLOCK_SIZE 64 `endif -`ifndef L1_BLOCK_SIZE -`define L1_BLOCK_SIZE ((`L2_ENABLE || `L3_ENABLE) ? 16 : `MEM_BLOCK_SIZE) +`ifndef MEM_ADDR_WIDTH +`ifdef XLEN_64 +`define MEM_ADDR_WIDTH 48 +`else +`define MEM_ADDR_WIDTH 32 `endif +`endif + +`ifndef L1_LINE_SIZE +`ifdef L1_DISABLE +`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 4 : `MEM_BLOCK_SIZE) +`else +`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 16 : `MEM_BLOCK_SIZE) +`endif +`endif + +`ifdef XLEN_64 + +`ifndef STARTUP_ADDR +`define STARTUP_ADDR 64'h180000000 +`endif + +`ifndef STACK_BASE_ADDR +`define STACK_BASE_ADDR 64'h1FF000000 +`endif + +`else `ifndef STARTUP_ADDR `define STARTUP_ADDR 32'h80000000 `endif -`ifndef IO_BASE_ADDR -`define IO_BASE_ADDR 32'hFF000000 +`ifndef STACK_BASE_ADDR +`define STACK_BASE_ADDR 32'hFF000000 `endif -`ifndef IO_ADDR_SIZE -`define IO_ADDR_SIZE (32'hFFFFFFFF - `IO_BASE_ADDR + 1) -`endif - -`ifndef IO_COUT_ADDR -`define IO_COUT_ADDR (32'hFFFFFFFF - `MEM_BLOCK_SIZE + 1) -`endif - -`ifndef IO_COUT_SIZE -`define IO_COUT_SIZE `MEM_BLOCK_SIZE -`endif - -`ifndef IO_CSR_ADDR -`define IO_CSR_ADDR `IO_BASE_ADDR `endif `ifndef SMEM_BASE_ADDR -`define SMEM_BASE_ADDR `IO_BASE_ADDR +`define SMEM_BASE_ADDR `STACK_BASE_ADDR `endif +`ifndef SMEM_LOG_SIZE +`define SMEM_LOG_SIZE 14 +`endif + +`ifndef IO_BASE_ADDR +`define IO_BASE_ADDR (`SMEM_BASE_ADDR + (1 << `SMEM_LOG_SIZE)) +`endif + +`ifndef IO_COUT_ADDR +`define IO_COUT_ADDR `IO_BASE_ADDR +`endif +`define IO_COUT_SIZE `MEM_BLOCK_SIZE + +`ifndef IO_CSR_ADDR +`define IO_CSR_ADDR (`IO_COUT_ADDR + `IO_COUT_SIZE) +`endif +`define IO_CSR_SIZE (4 * 64 * `NUM_CORES * `NUM_CLUSTERS) + +`ifndef STACK_LOG2_SIZE +`define STACK_LOG2_SIZE 13 +`endif +`define STACK_SIZE (1 << `STACK_LOG2_SIZE) + +`define RESET_DELAY 8 + +`ifndef STALL_TIMEOUT +`define STALL_TIMEOUT (100000 * (1 ** (`L2_ENABLED + `L3_ENABLED))) +`endif + +`ifndef FPU_FPNEW +`ifndef FPU_DSP +`ifndef FPU_DPI +`ifdef SYNTHESIS +`define FPU_DSP +`else +`define FPU_DPI +`endif +`endif +`endif +`endif + +`ifndef SYNTHESIS +`ifndef DPI_DISABLE +`define IMUL_DPI +`define IDIV_DPI +`endif +`endif + +`ifndef DEBUG_LEVEL +`define DEBUG_LEVEL 3 +`endif + +// ISA Extensions ///////////////////////////////////////////////////////////// + `ifndef EXT_M_DISABLE `define EXT_M_ENABLE `endif @@ -81,230 +196,278 @@ `define EXT_F_ENABLE `endif -// Device identification +`ifdef EXT_D_ENABLE +`define FLEN_64 +`else +`define FLEN_32 +`endif + +`ifdef FLEN_64 +`define FLEN 64 +`endif + +`ifdef FLEN_32 +`define FLEN 32 +`endif + +`ifdef XLEN_64 +`ifdef FLEN_32 + `define FPU_RV64F +`endif +`endif + +`define ISA_STD_A 0 +`define ISA_STD_C 2 +`define ISA_STD_D 3 +`define ISA_STD_E 4 +`define ISA_STD_F 5 +`define ISA_STD_H 7 +`define ISA_STD_I 8 +`define ISA_STD_N 13 +`define ISA_STD_Q 16 +`define ISA_STD_S 18 +`define ISA_STD_U 20 + +`define ISA_EXT_TEX 0 +`define ISA_EXT_RASTER 1 +`define ISA_EXT_ROP 2 + +`ifdef EXT_A_ENABLE + `define EXT_A_ENABLED 1 +`else + `define EXT_A_ENABLED 0 +`endif + +`ifdef EXT_C_ENABLE + `define EXT_C_ENABLED 1 +`else + `define EXT_C_ENABLED 0 +`endif + +`ifdef EXT_D_ENABLE + `define EXT_D_ENABLED 1 +`else + `define EXT_D_ENABLED 0 +`endif + +`ifdef EXT_F_ENABLE + `define EXT_F_ENABLED 1 +`else + `define EXT_F_ENABLED 0 +`endif + +`ifdef EXT_M_ENABLE + `define EXT_M_ENABLED 1 +`else + `define EXT_M_ENABLED 0 +`endif + +`define ISA_X_ENABLED 0 + +`define MISA_EXT 0 + +`define MISA_STD (`EXT_A_ENABLED << 0) /* A - Atomic Instructions extension */ \ + | (0 << 1) /* B - Tentatively reserved for Bit operations extension */ \ + | (`EXT_C_ENABLED << 2) /* C - Compressed extension */ \ + | (`EXT_D_ENABLED << 3) /* D - Double precsision floating-point extension */ \ + | (0 << 4) /* E - RV32E base ISA */ \ + | (`EXT_F_ENABLED << 5) /* F - Single precsision floating-point extension */ \ + | (0 << 6) /* G - Additional standard extensions present */ \ + | (0 << 7) /* H - Hypervisor mode implemented */ \ + | (1 << 8) /* I - RV32I/64I/128I base ISA */ \ + | (0 << 9) /* J - Reserved */ \ + | (0 << 10) /* K - Reserved */ \ + | (0 << 11) /* L - Tentatively reserved for Bit operations extension */ \ + | (`EXT_M_ENABLED << 12) /* M - Integer Multiply/Divide extension */ \ + | (0 << 13) /* N - User level interrupts supported */ \ + | (0 << 14) /* O - Reserved */ \ + | (0 << 15) /* P - Tentatively reserved for Packed-SIMD extension */ \ + | (0 << 16) /* Q - Quad-precision floating-point extension */ \ + | (0 << 17) /* R - Reserved */ \ + | (0 << 18) /* S - Supervisor mode implemented */ \ + | (0 << 19) /* T - Tentatively reserved for Transactional Memory extension */ \ + | (1 << 20) /* U - User mode implemented */ \ + | (0 << 21) /* V - Tentatively reserved for Vector extension */ \ + | (0 << 22) /* W - Reserved */ \ + | (`ISA_X_ENABLED << 23) /* X - Non-standard extensions present */ \ + | (0 << 24) /* Y - Reserved */ \ + | (0 << 25) /* Z - Reserved */ + +// Device identification ////////////////////////////////////////////////////// + `define VENDOR_ID 0 `define ARCHITECTURE_ID 0 `define IMPLEMENTATION_ID 0 -/////////////////////////////////////////////////////////////////////////////// +// Pipeline Configuration ///////////////////////////////////////////////////// -`ifndef LATENCY_IMUL -`define LATENCY_IMUL 3 +// Issue width +`ifndef ISSUE_WIDTH +`define ISSUE_WIDTH `MIN(`NUM_WARPS, 4) `endif -`ifndef LATENCY_FNCP -`define LATENCY_FNCP 2 +// Number of ALU units +`ifndef NUM_ALU_LANES +`define NUM_ALU_LANES `UP(`NUM_THREADS / 2) +`endif +`ifndef NUM_ALU_BLOCKS +`define NUM_ALU_BLOCKS `UP(`ISSUE_WIDTH / 1) `endif -`ifndef LATENCY_FMA -`define LATENCY_FMA 4 +// Number of FPU units +`ifndef NUM_FPU_LANES +`define NUM_FPU_LANES `UP(`NUM_THREADS / 2) +`endif +`ifndef NUM_FPU_BLOCKS +`define NUM_FPU_BLOCKS `UP(`ISSUE_WIDTH / 1) `endif -`ifndef LATENCY_FDIV -`ifdef ALTERA_S10 -`define LATENCY_FDIV 34 -`else -`define LATENCY_FDIV 15 -`endif +// Number of LSU units +`ifndef NUM_LSU_LANES +`define NUM_LSU_LANES `MIN(`NUM_THREADS, 4) `endif -`ifndef LATENCY_FSQRT -`ifdef ALTERA_S10 -`define LATENCY_FSQRT 25 -`else -`define LATENCY_FSQRT 10 +// Number of SFU units +`ifndef NUM_SFU_LANES +`define NUM_SFU_LANES `MIN(`NUM_THREADS, 4) `endif -`endif - -`ifndef LATENCY_FDIVSQRT -`define LATENCY_FDIVSQRT 32 -`endif - -`ifndef LATENCY_FCVT -`define LATENCY_FCVT 5 -`endif - -`define RESET_DELAY 6 - -// CSR Addresses ////////////////////////////////////////////////////////////// - -// User Floating-Point CSRs -`define CSR_FFLAGS 12'h001 -`define CSR_FRM 12'h002 -`define CSR_FCSR 12'h003 - -`define CSR_SATP 12'h180 - -`define CSR_PMPCFG0 12'h3A0 -`define CSR_PMPADDR0 12'h3B0 - -`define CSR_MSTATUS 12'h300 -`define CSR_MISA 12'h301 -`define CSR_MEDELEG 12'h302 -`define CSR_MIDELEG 12'h303 -`define CSR_MIE 12'h304 -`define CSR_MTVEC 12'h305 - -`define CSR_MEPC 12'h341 - -// Machine Performance-monitoring counters -`define CSR_MPM_BASE 12'hB00 -`define CSR_MPM_BASE_H 12'hB80 -// PERF: pipeline -`define CSR_MCYCLE 12'hB00 -`define CSR_MCYCLE_H 12'hB80 -`define CSR_MPM_RESERVED 12'hB01 -`define CSR_MPM_RESERVED_H 12'hB81 -`define CSR_MINSTRET 12'hB02 -`define CSR_MINSTRET_H 12'hB82 -`define CSR_MPM_IBUF_ST 12'hB03 -`define CSR_MPM_IBUF_ST_H 12'hB83 -`define CSR_MPM_SCRB_ST 12'hB04 -`define CSR_MPM_SCRB_ST_H 12'hB84 -`define CSR_MPM_ALU_ST 12'hB05 -`define CSR_MPM_ALU_ST_H 12'hB85 -`define CSR_MPM_LSU_ST 12'hB06 -`define CSR_MPM_LSU_ST_H 12'hB86 -`define CSR_MPM_CSR_ST 12'hB07 -`define CSR_MPM_CSR_ST_H 12'hB87 -`define CSR_MPM_FPU_ST 12'hB08 -`define CSR_MPM_FPU_ST_H 12'hB88 -`define CSR_MPM_GPU_ST 12'hB09 -`define CSR_MPM_GPU_ST_H 12'hB89 -// PERF: decode -`define CSR_MPM_LOADS 12'hB0A -`define CSR_MPM_LOADS_H 12'hB8A -`define CSR_MPM_STORES 12'hB0B -`define CSR_MPM_STORES_H 12'hB8B -`define CSR_MPM_BRANCHES 12'hB0C -`define CSR_MPM_BRANCHES_H 12'hB8C -// PERF: icache -`define CSR_MPM_ICACHE_READS 12'hB0D // total reads -`define CSR_MPM_ICACHE_READS_H 12'hB8D -`define CSR_MPM_ICACHE_MISS_R 12'hB0E // read misses -`define CSR_MPM_ICACHE_MISS_R_H 12'hB8E -// PERF: dcache -`define CSR_MPM_DCACHE_READS 12'hB0F // total reads -`define CSR_MPM_DCACHE_READS_H 12'hB8F -`define CSR_MPM_DCACHE_WRITES 12'hB10 // total writes -`define CSR_MPM_DCACHE_WRITES_H 12'hB90 -`define CSR_MPM_DCACHE_MISS_R 12'hB11 // read misses -`define CSR_MPM_DCACHE_MISS_R_H 12'hB91 -`define CSR_MPM_DCACHE_MISS_W 12'hB12 // write misses -`define CSR_MPM_DCACHE_MISS_W_H 12'hB92 -`define CSR_MPM_DCACHE_BANK_ST 12'hB13 // bank conflicts -`define CSR_MPM_DCACHE_BANK_ST_H 12'hB93 -`define CSR_MPM_DCACHE_MSHR_ST 12'hB14 // MSHR stalls -`define CSR_MPM_DCACHE_MSHR_ST_H 12'hB94 -// PERF: smem -`define CSR_MPM_SMEM_READS 12'hB15 // total reads -`define CSR_MPM_SMEM_READS_H 12'hB95 -`define CSR_MPM_SMEM_WRITES 12'hB16 // total writes -`define CSR_MPM_SMEM_WRITES_H 12'hB96 -`define CSR_MPM_SMEM_BANK_ST 12'hB17 // bank conflicts -`define CSR_MPM_SMEM_BANK_ST_H 12'hB97 -// PERF: memory -`define CSR_MPM_MEM_READS 12'hB18 // memory reads -`define CSR_MPM_MEM_READS_H 12'hB98 -`define CSR_MPM_MEM_WRITES 12'hB19 // memory writes -`define CSR_MPM_MEM_WRITES_H 12'hB99 -`define CSR_MPM_MEM_LAT 12'hB1A // memory latency -`define CSR_MPM_MEM_LAT_H 12'hB9A -// PERF: texunit -`define CSR_MPM_TEX_READS 12'hB1B // texture accesses -`define CSR_MPM_TEX_READS_H 12'hB9B -`define CSR_MPM_TEX_LAT 12'hB1C // texture latency -`define CSR_MPM_TEX_LAT_H 12'hB9C - -// Machine Information Registers -`define CSR_MVENDORID 12'hF11 -`define CSR_MARCHID 12'hF12 -`define CSR_MIMPID 12'hF13 -`define CSR_MHARTID 12'hF14 - -// User SIMT CSRs -`define CSR_WTID 12'hCC0 -`define CSR_LTID 12'hCC1 -`define CSR_GTID 12'hCC2 -`define CSR_LWID 12'hCC3 -`define CSR_GWID `CSR_MHARTID -`define CSR_GCID 12'hCC5 -`define CSR_TMASK 12'hCC4 - -// Machine SIMT CSRs -`define CSR_NT 12'hFC0 -`define CSR_NW 12'hFC1 -`define CSR_NC 12'hFC2 - -////////// Texture Units ////////////////////////////////////////////////////// - -`define NUM_TEX_UNITS 2 -`define TEX_SUBPIXEL_BITS 8 - -`define TEX_DIM_BITS 15 -`define TEX_LOD_MAX `TEX_DIM_BITS -`define TEX_LOD_BITS 4 - -`define TEX_FXD_BITS 32 -`define TEX_FXD_FRAC (`TEX_DIM_BITS+`TEX_SUBPIXEL_BITS) - -`define TEX_STATE_ADDR 0 -`define TEX_STATE_WIDTH 1 -`define TEX_STATE_HEIGHT 2 -`define TEX_STATE_FORMAT 3 -`define TEX_STATE_FILTER 4 -`define TEX_STATE_WRAPU 5 -`define TEX_STATE_WRAPV 6 -`define TEX_STATE_MIPOFF(lod) (7+(lod)) -`define NUM_TEX_STATES (`TEX_STATE_MIPOFF(`TEX_LOD_MAX)+1) - -`define CSR_TEX_UNIT 12'hFD0 - -`define CSR_TEX_STATE_BEGIN 12'hFD1 -`define CSR_TEX_ADDR (`CSR_TEX_STATE_BEGIN+`TEX_STATE_ADDR) -`define CSR_TEX_WIDTH (`CSR_TEX_STATE_BEGIN+`TEX_STATE_WIDTH) -`define CSR_TEX_HEIGHT (`CSR_TEX_STATE_BEGIN+`TEX_STATE_HEIGHT) -`define CSR_TEX_FORMAT (`CSR_TEX_STATE_BEGIN+`TEX_STATE_FORMAT) -`define CSR_TEX_FILTER (`CSR_TEX_STATE_BEGIN+`TEX_STATE_FILTER) -`define CSR_TEX_WRAPU (`CSR_TEX_STATE_BEGIN+`TEX_STATE_WRAPU) -`define CSR_TEX_WRAPV (`CSR_TEX_STATE_BEGIN+`TEX_STATE_WRAPV) -`define CSR_TEX_MIPOFF(lod) (`CSR_TEX_STATE_BEGIN+`TEX_STATE_MIPOFF(lod)) -`define CSR_TEX_STATE_END (`CSR_TEX_STATE_BEGIN+`NUM_TEX_STATES) - -`define CSR_TEX_STATE(addr) ((addr) - `CSR_TEX_STATE_BEGIN) - -// Pipeline Queues //////////////////////////////////////////////////////////// // Size of Instruction Buffer `ifndef IBUF_SIZE -`define IBUF_SIZE 2 +`define IBUF_SIZE (2 * (`NUM_WARPS / `ISSUE_WIDTH)) `endif // Size of LSU Request Queue `ifndef LSUQ_SIZE -`define LSUQ_SIZE (`NUM_WARPS * 2) +`define LSUQ_SIZE (2 * (`NUM_THREADS / `NUM_LSU_LANES)) `endif +// LSU Duplicate Address Check +`ifdef LSU_DUP +`define LSU_DUP_ENABLED 1 +`else +`define LSU_DUP_ENABLED 0 +`endif + +`ifdef GBAR_ENABLE +`define GBAR_ENABLED 1 +`else +`define GBAR_ENABLED 0 +`endif + +`ifndef LATENCY_IMUL +`ifdef VIVADO +`define LATENCY_IMUL 4 +`endif +`ifdef QUARTUS +`define LATENCY_IMUL 3 +`endif +`ifndef LATENCY_IMUL +`define LATENCY_IMUL 4 +`endif +`endif + +// Floating-Point Units /////////////////////////////////////////////////////// + // Size of FPU Request Queue -`ifndef FPUQ_SIZE -`define FPUQ_SIZE 8 +`ifndef FPU_REQ_QUEUE_SIZE +`define FPU_REQ_QUEUE_SIZE (2 * (`NUM_THREADS / `NUM_FPU_LANES)) `endif -// Texture Unit Request Queue -`ifndef TEXQ_SIZE -`define TEXQ_SIZE (`NUM_WARPS * 2) +// FNCP Latency +`ifndef LATENCY_FNCP +`define LATENCY_FNCP 2 +`endif + +// FMA Latency +`ifndef LATENCY_FMA +`ifdef FPU_DPI +`define LATENCY_FMA 4 +`endif +`ifdef FPU_FPNEW +`define LATENCY_FMA 4 +`endif +`ifdef FPU_DSP +`ifdef QUARTUS +`define LATENCY_FMA 4 +`endif +`ifdef VIVADO +`define LATENCY_FMA 16 +`endif +`ifndef LATENCY_FMA +`define LATENCY_FMA 4 +`endif +`endif +`endif + +// FDIV Latency +`ifndef LATENCY_FDIV +`ifdef FPU_DPI +`define LATENCY_FDIV 15 +`endif +`ifdef FPU_FPNEW +`define LATENCY_FDIV 16 +`endif +`ifdef FPU_DSP +`ifdef QUARTUS +`define LATENCY_FDIV 15 +`endif +`ifdef VIVADO +`define LATENCY_FDIV 28 +`endif +`ifndef LATENCY_FDIV +`define LATENCY_FDIV 16 +`endif +`endif +`endif + +// FSQRT Latency +`ifndef LATENCY_FSQRT +`ifdef FPU_DPI +`define LATENCY_FSQRT 10 +`endif +`ifdef FPU_FPNEW +`define LATENCY_FSQRT 16 +`endif +`ifdef FPU_DSP +`ifdef QUARTUS +`define LATENCY_FSQRT 10 +`endif +`ifdef VIVADO +`define LATENCY_FSQRT 28 +`endif +`ifndef LATENCY_FSQRT +`define LATENCY_FSQRT 16 +`endif +`endif +`endif + +// FCVT Latency +`ifndef LATENCY_FCVT +`define LATENCY_FCVT 5 `endif // Icache Configurable Knobs ////////////////////////////////////////////////// -// Size of cache in bytes -`ifndef ICACHE_SIZE -`define ICACHE_SIZE 16384 +// Cache Enable +`ifndef ICACHE_DISABLE +`define ICACHE_ENABLE +`endif +`ifdef ICACHE_ENABLE + `define ICACHE_ENABLED 1 +`else + `define ICACHE_ENABLED 0 + `define NUM_ICACHES 0 `endif -// Core Request Queue Size -`ifndef ICACHE_CREQ_SIZE -`define ICACHE_CREQ_SIZE 0 +// Number of Cache Units +`ifndef NUM_ICACHES +`define NUM_ICACHES `UP(`NUM_CORES / 4) +`endif + +// Cache Size +`ifndef ICACHE_SIZE +`define ICACHE_SIZE 16384 `endif // Core Response Queue Size @@ -314,7 +477,7 @@ // Miss Handling Register Size `ifndef ICACHE_MSHR_SIZE -`define ICACHE_MSHR_SIZE `NUM_WARPS +`define ICACHE_MSHR_SIZE 16 `endif // Memory Request Queue Size @@ -327,26 +490,38 @@ `define ICACHE_MRSQ_SIZE 0 `endif +// Number of Associative Ways +`ifndef ICACHE_NUM_WAYS +`define ICACHE_NUM_WAYS 2 +`endif + // Dcache Configurable Knobs ////////////////////////////////////////////////// -// Size of cache in bytes +// Cache Enable +`ifndef DCACHE_DISABLE +`define DCACHE_ENABLE +`endif +`ifdef DCACHE_ENABLE + `define DCACHE_ENABLED 1 +`else + `define DCACHE_ENABLED 0 + `define NUM_DCACHES 0 + `define DCACHE_NUM_BANKS 1 +`endif + +// Number of Cache Units +`ifndef NUM_DCACHES +`define NUM_DCACHES `UP(`NUM_CORES / 4) +`endif + +// Cache Size `ifndef DCACHE_SIZE `define DCACHE_SIZE 16384 `endif -// Number of banks +// Number of Banks `ifndef DCACHE_NUM_BANKS -`define DCACHE_NUM_BANKS `NUM_THREADS -`endif - -// Number of ports per bank -`ifndef DCACHE_NUM_PORTS -`define DCACHE_NUM_PORTS 1 -`endif - -// Core Request Queue Size -`ifndef DCACHE_CREQ_SIZE -`define DCACHE_CREQ_SIZE 0 +`define DCACHE_NUM_BANKS (`NUM_LSU_LANES) `endif // Core Response Queue Size @@ -356,7 +531,7 @@ // Miss Handling Register Size `ifndef DCACHE_MSHR_SIZE -`define DCACHE_MSHR_SIZE `LSUQ_SIZE +`define DCACHE_MSHR_SIZE 16 `endif // Memory Request Queue Size @@ -369,54 +544,42 @@ `define DCACHE_MRSQ_SIZE 0 `endif +// Number of Associative Ways +`ifndef DCACHE_NUM_WAYS +`define DCACHE_NUM_WAYS 2 +`endif + // SM Configurable Knobs ////////////////////////////////////////////////////// -// per thread stack size -`ifndef STACK_LOG2_SIZE -`define STACK_LOG2_SIZE 10 +`ifndef SM_DISABLE +`define SM_ENABLE `endif -`define STACK_SIZE (1 << `STACK_LOG2_SIZE) - -// Size of cache in bytes -`ifndef SMEM_SIZE -`define SMEM_SIZE (`STACK_SIZE * `NUM_WARPS * `NUM_THREADS) +`ifdef SM_ENABLE + `define SM_ENABLED 1 +`else + `define SM_ENABLED 0 + `define SMEM_NUM_BANKS 1 `endif -// Number of banks +// Number of Banks `ifndef SMEM_NUM_BANKS -`define SMEM_NUM_BANKS `NUM_THREADS -`endif - -// Core Request Queue Size -`ifndef SMEM_CREQ_SIZE -`define SMEM_CREQ_SIZE 2 -`endif - -// Core Response Queue Size -`ifndef SMEM_CRSQ_SIZE -`define SMEM_CRSQ_SIZE 2 +`define SMEM_NUM_BANKS (`NUM_LSU_LANES) `endif // L2cache Configurable Knobs ///////////////////////////////////////////////// -// Size of cache in bytes +// Cache Size `ifndef L2_CACHE_SIZE -`define L2_CACHE_SIZE 131072 +`ifdef ALTERA_S10 +`define L2_CACHE_SIZE 2097152 +`else +`define L2_CACHE_SIZE 1048576 +`endif `endif -// Number of banks +// Number of Banks `ifndef L2_NUM_BANKS -`define L2_NUM_BANKS ((`NUM_CORES < 4) ? `NUM_CORES : 4) -`endif - -// Number of ports per bank -`ifndef L2_NUM_PORTS -`define L2_NUM_PORTS 1 -`endif - -// Core Request Queue Size -`ifndef L2_CREQ_SIZE -`define L2_CREQ_SIZE 0 +`define L2_NUM_BANKS 2 `endif // Core Response Queue Size @@ -439,26 +602,25 @@ `define L2_MRSQ_SIZE 0 `endif +// Number of Associative Ways +`ifndef L2_NUM_WAYS +`define L2_NUM_WAYS 4 +`endif + // L3cache Configurable Knobs ///////////////////////////////////////////////// -// Size of cache in bytes +// Cache Size `ifndef L3_CACHE_SIZE +`ifdef ALTERA_S10 +`define L3_CACHE_SIZE 2097152 +`else `define L3_CACHE_SIZE 1048576 `endif +`endif -// Number of banks +// Number of Banks `ifndef L3_NUM_BANKS -`define L3_NUM_BANKS ((`NUM_CLUSTERS < 4) ? `NUM_CORES : 4) -`endif - -// Number of ports per bank -`ifndef L3_NUM_PORTS -`define L3_NUM_PORTS 1 -`endif - -// Core Request Queue Size -`ifndef L3_CREQ_SIZE -`define L3_CREQ_SIZE 0 +`define L3_NUM_BANKS `MIN(4, `NUM_CLUSTERS) `endif // Core Response Queue Size @@ -481,4 +643,9 @@ `define L3_MRSQ_SIZE 0 `endif -`endif \ No newline at end of file +// Number of Associative Ways +`ifndef L3_NUM_WAYS +`define L3_NUM_WAYS 4 +`endif + +`endif // VX_CONFIG_VH diff --git a/hw/rtl/VX_core.sv b/hw/rtl/VX_core.sv deleted file mode 100644 index d1cbbb6f..00000000 --- a/hw/rtl/VX_core.sv +++ /dev/null @@ -1,156 +0,0 @@ -`include "VX_define.vh" - -module VX_core #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_core - - // Clock - input wire clk, - input wire reset, - - // Memory request - output wire mem_req_valid, - output wire mem_req_rw, - output wire [`DCACHE_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, - output wire [`DCACHE_MEM_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_req_data, - output wire [`L1_MEM_TAG_WIDTH-1:0] mem_req_tag, - input wire mem_req_ready, - - // Memory reponse - input wire mem_rsp_valid, - input wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_rsp_data, - input wire [`L1_MEM_TAG_WIDTH-1:0] mem_rsp_tag, - output wire mem_rsp_ready, - - // Status - output wire busy -); -`ifdef PERF_ENABLE - VX_perf_memsys_if perf_memsys_if(); -`endif - - VX_mem_req_if #( - .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), - .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), - .TAG_WIDTH (`L1_MEM_TAG_WIDTH) - ) mem_req_if(); - - VX_mem_rsp_if #( - .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), - .TAG_WIDTH (`L1_MEM_TAG_WIDTH) - ) mem_rsp_if(); - - assign mem_req_valid = mem_req_if.valid; - assign mem_req_rw = mem_req_if.rw; - assign mem_req_byteen= mem_req_if.byteen; - assign mem_req_addr = mem_req_if.addr; - assign mem_req_data = mem_req_if.data; - assign mem_req_tag = mem_req_if.tag; - assign mem_req_if.ready = mem_req_ready; - - assign mem_rsp_if.valid = mem_rsp_valid; - assign mem_rsp_if.data = mem_rsp_data; - assign mem_rsp_if.tag = mem_rsp_tag; - assign mem_rsp_ready = mem_rsp_if.ready; - - //-- - - VX_dcache_req_if #( - .NUM_REQS (`DCACHE_NUM_REQS), - .WORD_SIZE (`DCACHE_WORD_SIZE), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) - ) dcache_req_if(); - - VX_dcache_rsp_if #( - .NUM_REQS (`DCACHE_NUM_REQS), - .WORD_SIZE (`DCACHE_WORD_SIZE), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) - ) dcache_rsp_if(); - - VX_icache_req_if #( - .WORD_SIZE (`ICACHE_WORD_SIZE), - .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) - ) icache_req_if(); - - VX_icache_rsp_if #( - .WORD_SIZE (`ICACHE_WORD_SIZE), - .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) - ) icache_rsp_if(); - - VX_pipeline #( - .CORE_ID(CORE_ID) - ) pipeline ( - `SCOPE_BIND_VX_core_pipeline - `ifdef PERF_ENABLE - .perf_memsys_if (perf_memsys_if), - `endif - - .clk(clk), - .reset(reset), - - // Dcache core request - .dcache_req_valid (dcache_req_if.valid), - .dcache_req_rw (dcache_req_if.rw), - .dcache_req_byteen (dcache_req_if.byteen), - .dcache_req_addr (dcache_req_if.addr), - .dcache_req_data (dcache_req_if.data), - .dcache_req_tag (dcache_req_if.tag), - .dcache_req_ready (dcache_req_if.ready), - - // Dcache core reponse - .dcache_rsp_valid (dcache_rsp_if.valid), - .dcache_rsp_tmask (dcache_rsp_if.tmask), - .dcache_rsp_data (dcache_rsp_if.data), - .dcache_rsp_tag (dcache_rsp_if.tag), - .dcache_rsp_ready (dcache_rsp_if.ready), - - // Icache core request - .icache_req_valid (icache_req_if.valid), - .icache_req_addr (icache_req_if.addr), - .icache_req_tag (icache_req_if.tag), - .icache_req_ready (icache_req_if.ready), - - // Icache core reponse - .icache_rsp_valid (icache_rsp_if.valid), - .icache_rsp_data (icache_rsp_if.data), - .icache_rsp_tag (icache_rsp_if.tag), - .icache_rsp_ready (icache_rsp_if.ready), - - // Status - .busy(busy) - ); - - //-- - - VX_mem_unit #( - .CORE_ID(CORE_ID) - ) mem_unit ( - `SCOPE_BIND_VX_core_mem_unit - `ifdef PERF_ENABLE - .perf_memsys_if (perf_memsys_if), - `endif - - .clk (clk), - .reset (reset), - - // Core <-> Dcache - .dcache_req_if (dcache_req_if), - .dcache_rsp_if (dcache_rsp_if), - - // Core <-> Icache - .icache_req_if (icache_req_if), - .icache_rsp_if (icache_rsp_if), - - // Memory - .mem_req_if (mem_req_if), - .mem_rsp_if (mem_rsp_if) - ); - -endmodule - - - - - diff --git a/hw/rtl/VX_csr_data.sv b/hw/rtl/VX_csr_data.sv deleted file mode 100644 index 6d4a82c9..00000000 --- a/hw/rtl/VX_csr_data.sv +++ /dev/null @@ -1,265 +0,0 @@ -`include "VX_define.vh" - -module VX_csr_data #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE -`ifdef EXT_TEX_ENABLE - VX_perf_tex_if.slave perf_tex_if, -`endif - VX_perf_memsys_if.slave perf_memsys_if, - VX_perf_pipeline_if.slave perf_pipeline_if, -`endif - - VX_cmt_to_csr_if.slave cmt_to_csr_if, - VX_fetch_to_csr_if.slave fetch_to_csr_if, - -`ifdef EXT_F_ENABLE - VX_fpu_to_csr_if.slave fpu_to_csr_if, -`endif -`ifdef EXT_TEX_ENABLE - VX_tex_csr_if.master tex_csr_if, -`endif - - input wire read_enable, - input wire [`UUID_BITS-1:0] read_uuid, - input wire[`CSR_ADDR_BITS-1:0] read_addr, - input wire[`NW_BITS-1:0] read_wid, - output wire[31:0] read_data, - - input wire write_enable, - input wire [`UUID_BITS-1:0] write_uuid, - input wire[`CSR_ADDR_BITS-1:0] write_addr, - input wire[`NW_BITS-1:0] write_wid, - input wire[31:0] write_data, - - input wire busy -); - import fpu_types::*; - - reg [`CSR_WIDTH-1:0] csr_satp; - reg [`CSR_WIDTH-1:0] csr_mstatus; - reg [`CSR_WIDTH-1:0] csr_medeleg; - reg [`CSR_WIDTH-1:0] csr_mideleg; - reg [`CSR_WIDTH-1:0] csr_mie; - reg [`CSR_WIDTH-1:0] csr_mtvec; - reg [`CSR_WIDTH-1:0] csr_mepc; - reg [`CSR_WIDTH-1:0] csr_pmpcfg [0:0]; - reg [`CSR_WIDTH-1:0] csr_pmpaddr [0:0]; - reg [63:0] csr_cycle; - reg [63:0] csr_instret; - - reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FFLAGS_BITS-1:0] fcsr; - - always @(posedge clk) begin - if (reset) begin - fcsr <= '0; - end else begin - `ifdef EXT_F_ENABLE - if (fpu_to_csr_if.write_enable) begin - fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] - | fpu_to_csr_if.write_fflags; - end - `endif - if (write_enable) begin - case (write_addr) - `CSR_FFLAGS: fcsr[write_wid][`FFLAGS_BITS-1:0] <= write_data[`FFLAGS_BITS-1:0]; - `CSR_FRM: fcsr[write_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS] <= write_data[`INST_FRM_BITS-1:0]; - `CSR_FCSR: fcsr[write_wid] <= write_data[`FFLAGS_BITS+`INST_FRM_BITS-1:0]; - `CSR_SATP: csr_satp <= write_data[`CSR_WIDTH-1:0]; - `CSR_MSTATUS: csr_mstatus <= write_data[`CSR_WIDTH-1:0]; - `CSR_MEDELEG: csr_medeleg <= write_data[`CSR_WIDTH-1:0]; - `CSR_MIDELEG: csr_mideleg <= write_data[`CSR_WIDTH-1:0]; - `CSR_MIE: csr_mie <= write_data[`CSR_WIDTH-1:0]; - `CSR_MTVEC: csr_mtvec <= write_data[`CSR_WIDTH-1:0]; - `CSR_MEPC: csr_mepc <= write_data[`CSR_WIDTH-1:0]; - `CSR_PMPCFG0: csr_pmpcfg[0] <= write_data[`CSR_WIDTH-1:0]; - `CSR_PMPADDR0: csr_pmpaddr[0] <= write_data[`CSR_WIDTH-1:0]; - default: begin - `ifdef EXT_TEX_ENABLE - `ASSERT((write_addr == `CSR_TEX_UNIT) - || (write_addr >= `CSR_TEX_STATE_BEGIN - && write_addr < `CSR_TEX_STATE_END), - ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid)); - `else - `ASSERT(~write_enable, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid)); - `endif - end - endcase - end - end - end - - `UNUSED_VAR (write_data) - - // TEX CSRs -`ifdef EXT_TEX_ENABLE - assign tex_csr_if.write_enable = write_enable; - assign tex_csr_if.write_addr = write_addr; - assign tex_csr_if.write_data = write_data; - assign tex_csr_if.write_uuid = write_uuid; -`endif - - always @(posedge clk) begin - if (reset) begin - csr_cycle <= 0; - csr_instret <= 0; - end else begin - if (busy) begin - csr_cycle <= csr_cycle + 1; - end - if (cmt_to_csr_if.valid) begin - csr_instret <= csr_instret + 64'(cmt_to_csr_if.commit_size); - end - end - end - - reg [31:0] read_data_r; - reg read_addr_valid_r; - - always @(*) begin - read_data_r = 'x; - read_addr_valid_r = 1; - case (read_addr) - `CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFLAGS_BITS-1:0]); - `CSR_FRM : read_data_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]); - `CSR_FCSR : read_data_r = 32'(fcsr[read_wid]); - - `CSR_WTID , - `CSR_LTID , - `CSR_LWID : read_data_r = 32'(read_wid); - `CSR_GTID , - /*`CSR_MHARTID ,*/ - `CSR_GWID : read_data_r = CORE_ID * `NUM_WARPS + 32'(read_wid); - `CSR_GCID : read_data_r = CORE_ID; - - `CSR_TMASK : read_data_r = 32'(fetch_to_csr_if.thread_masks[read_wid]); - - `CSR_NT : read_data_r = `NUM_THREADS; - `CSR_NW : read_data_r = `NUM_WARPS; - `CSR_NC : read_data_r = `NUM_CORES * `NUM_CLUSTERS; - - `CSR_MCYCLE : read_data_r = csr_cycle[31:0]; - `CSR_MCYCLE_H : read_data_r = 32'(csr_cycle[`PERF_CTR_BITS-1:32]); - `CSR_MINSTRET : read_data_r = csr_instret[31:0]; - `CSR_MINSTRET_H : read_data_r = 32'(csr_instret[`PERF_CTR_BITS-1:32]); - - `ifdef PERF_ENABLE - // PERF: pipeline - `CSR_MPM_IBUF_ST : read_data_r = perf_pipeline_if.ibf_stalls[31:0]; - `CSR_MPM_IBUF_ST_H : read_data_r = 32'(perf_pipeline_if.ibf_stalls[`PERF_CTR_BITS-1:32]); - `CSR_MPM_SCRB_ST : read_data_r = perf_pipeline_if.scb_stalls[31:0]; - `CSR_MPM_SCRB_ST_H : read_data_r = 32'(perf_pipeline_if.scb_stalls[`PERF_CTR_BITS-1:32]); - `CSR_MPM_ALU_ST : read_data_r = perf_pipeline_if.alu_stalls[31:0]; - `CSR_MPM_ALU_ST_H : read_data_r = 32'(perf_pipeline_if.alu_stalls[`PERF_CTR_BITS-1:32]); - `CSR_MPM_LSU_ST : read_data_r = perf_pipeline_if.lsu_stalls[31:0]; - `CSR_MPM_LSU_ST_H : read_data_r = 32'(perf_pipeline_if.lsu_stalls[`PERF_CTR_BITS-1:32]); - `CSR_MPM_CSR_ST : read_data_r = perf_pipeline_if.csr_stalls[31:0]; - `CSR_MPM_CSR_ST_H : read_data_r = 32'(perf_pipeline_if.csr_stalls[`PERF_CTR_BITS-1:32]); - `ifdef EXT_F_ENABLE - `CSR_MPM_FPU_ST : read_data_r = perf_pipeline_if.fpu_stalls[31:0]; - `CSR_MPM_FPU_ST_H : read_data_r = 32'(perf_pipeline_if.fpu_stalls[`PERF_CTR_BITS-1:32]); - `else - `CSR_MPM_FPU_ST : read_data_r = '0; - `CSR_MPM_FPU_ST_H : read_data_r = '0; - `endif - `CSR_MPM_GPU_ST : read_data_r = perf_pipeline_if.gpu_stalls[31:0]; - `CSR_MPM_GPU_ST_H : read_data_r = 32'(perf_pipeline_if.gpu_stalls[`PERF_CTR_BITS-1:32]); - // PERF: decode - `CSR_MPM_LOADS : read_data_r = perf_pipeline_if.loads[31:0]; - `CSR_MPM_LOADS_H : read_data_r = 32'(perf_pipeline_if.loads[`PERF_CTR_BITS-1:32]); - `CSR_MPM_STORES : read_data_r = perf_pipeline_if.stores[31:0]; - `CSR_MPM_STORES_H : read_data_r = 32'(perf_pipeline_if.stores[`PERF_CTR_BITS-1:32]); - `CSR_MPM_BRANCHES : read_data_r = perf_pipeline_if.branches[31:0]; - `CSR_MPM_BRANCHES_H : read_data_r = 32'(perf_pipeline_if.branches[`PERF_CTR_BITS-1:32]); - // PERF: icache - `CSR_MPM_ICACHE_READS : read_data_r = perf_memsys_if.icache_reads[31:0]; - `CSR_MPM_ICACHE_READS_H : read_data_r = 32'(perf_memsys_if.icache_reads[`PERF_CTR_BITS-1:32]); - `CSR_MPM_ICACHE_MISS_R : read_data_r = perf_memsys_if.icache_read_misses[31:0]; - `CSR_MPM_ICACHE_MISS_R_H : read_data_r = 32'(perf_memsys_if.icache_read_misses[`PERF_CTR_BITS-1:32]); - // PERF: dcache - `CSR_MPM_DCACHE_READS : read_data_r = perf_memsys_if.dcache_reads[31:0]; - `CSR_MPM_DCACHE_READS_H : read_data_r = 32'(perf_memsys_if.dcache_reads[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DCACHE_WRITES : read_data_r = perf_memsys_if.dcache_writes[31:0]; - `CSR_MPM_DCACHE_WRITES_H : read_data_r = 32'(perf_memsys_if.dcache_writes[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DCACHE_MISS_R : read_data_r = perf_memsys_if.dcache_read_misses[31:0]; - `CSR_MPM_DCACHE_MISS_R_H : read_data_r = 32'(perf_memsys_if.dcache_read_misses[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DCACHE_MISS_W : read_data_r = perf_memsys_if.dcache_write_misses[31:0]; - `CSR_MPM_DCACHE_MISS_W_H : read_data_r = 32'(perf_memsys_if.dcache_write_misses[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DCACHE_BANK_ST : read_data_r = perf_memsys_if.dcache_bank_stalls[31:0]; - `CSR_MPM_DCACHE_BANK_ST_H : read_data_r = 32'(perf_memsys_if.dcache_bank_stalls[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DCACHE_MSHR_ST : read_data_r = perf_memsys_if.dcache_mshr_stalls[31:0]; - `CSR_MPM_DCACHE_MSHR_ST_H : read_data_r = 32'(perf_memsys_if.dcache_mshr_stalls[`PERF_CTR_BITS-1:32]); - // PERF: smem - `CSR_MPM_SMEM_READS : read_data_r = perf_memsys_if.smem_reads[31:0]; - `CSR_MPM_SMEM_READS_H : read_data_r = 32'(perf_memsys_if.smem_reads[`PERF_CTR_BITS-1:32]); - `CSR_MPM_SMEM_WRITES : read_data_r = perf_memsys_if.smem_writes[31:0]; - `CSR_MPM_SMEM_WRITES_H : read_data_r = 32'(perf_memsys_if.smem_writes[`PERF_CTR_BITS-1:32]); - `CSR_MPM_SMEM_BANK_ST : read_data_r = perf_memsys_if.smem_bank_stalls[31:0]; - `CSR_MPM_SMEM_BANK_ST_H : read_data_r = 32'(perf_memsys_if.smem_bank_stalls[`PERF_CTR_BITS-1:32]); - // PERF: memory - `CSR_MPM_MEM_READS : read_data_r = perf_memsys_if.mem_reads[31:0]; - `CSR_MPM_MEM_READS_H : read_data_r = 32'(perf_memsys_if.mem_reads[`PERF_CTR_BITS-1:32]); - `CSR_MPM_MEM_WRITES : read_data_r = perf_memsys_if.mem_writes[31:0]; - `CSR_MPM_MEM_WRITES_H : read_data_r = 32'(perf_memsys_if.mem_writes[`PERF_CTR_BITS-1:32]); - `CSR_MPM_MEM_LAT : read_data_r = perf_memsys_if.mem_latency[31:0]; - `CSR_MPM_MEM_LAT_H : read_data_r = 32'(perf_memsys_if.mem_latency[`PERF_CTR_BITS-1:32]); - `ifdef EXT_TEX_ENABLE - // PERF: texunit - `CSR_MPM_TEX_READS : read_data_r = perf_tex_if.mem_reads[31:0]; - `CSR_MPM_TEX_READS_H : read_data_r = 32'(perf_tex_if.mem_reads[`PERF_CTR_BITS-1:32]); - `CSR_MPM_TEX_LAT : read_data_r = perf_tex_if.mem_latency[31:0]; - `CSR_MPM_TEX_LAT_H : read_data_r = 32'(perf_tex_if.mem_latency[`PERF_CTR_BITS-1:32]); - `endif - // PERF: reserved - `CSR_MPM_RESERVED : read_data_r = '0; - `CSR_MPM_RESERVED_H : read_data_r = '0; - `endif - - `CSR_SATP : read_data_r = 32'(csr_satp); - - `CSR_MSTATUS : read_data_r = 32'(csr_mstatus); - `CSR_MISA : read_data_r = `ISA_CODE; - `CSR_MEDELEG : read_data_r = 32'(csr_medeleg); - `CSR_MIDELEG : read_data_r = 32'(csr_mideleg); - `CSR_MIE : read_data_r = 32'(csr_mie); - `CSR_MTVEC : read_data_r = 32'(csr_mtvec); - - `CSR_MEPC : read_data_r = 32'(csr_mepc); - - `CSR_PMPCFG0 : read_data_r = 32'(csr_pmpcfg[0]); - `CSR_PMPADDR0 : read_data_r = 32'(csr_pmpaddr[0]); - - `CSR_MVENDORID : read_data_r = `VENDOR_ID; - `CSR_MARCHID : read_data_r = `ARCHITECTURE_ID; - `CSR_MIMPID : read_data_r = `IMPLEMENTATION_ID; - - default: begin - if ((read_addr >= `CSR_MPM_BASE && read_addr < (`CSR_MPM_BASE + 32)) - || (read_addr >= `CSR_MPM_BASE_H && read_addr < (`CSR_MPM_BASE_H + 32))) begin - read_addr_valid_r = 1; - end else - `ifdef EXT_TEX_ENABLE - if ((read_addr == `CSR_TEX_UNIT) - || (read_addr >= `CSR_TEX_STATE_BEGIN - && read_addr < `CSR_TEX_STATE_END)) begin - read_addr_valid_r = 1; - end else - `endif - read_addr_valid_r = 0; - end - endcase - end - - `RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("%t: *** invalid CSR read address: %0h (#%0d)", $time, read_addr, read_uuid)) - - assign read_data = read_data_r; - -`ifdef EXT_F_ENABLE - assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]; -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_csr_unit.sv b/hw/rtl/VX_csr_unit.sv deleted file mode 100644 index 9186586a..00000000 --- a/hw/rtl/VX_csr_unit.sv +++ /dev/null @@ -1,151 +0,0 @@ -`include "VX_define.vh" - -module VX_csr_unit #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE -`ifdef EXT_TEX_ENABLE - VX_perf_tex_if.slave perf_tex_if, -`endif - VX_perf_memsys_if.slave perf_memsys_if, - VX_perf_pipeline_if.slave perf_pipeline_if, -`endif - - VX_cmt_to_csr_if.slave cmt_to_csr_if, - VX_fetch_to_csr_if.slave fetch_to_csr_if, - VX_csr_req_if.slave csr_req_if, - VX_commit_if.master csr_commit_if, - -`ifdef EXT_F_ENABLE - VX_fpu_to_csr_if.slave fpu_to_csr_if, - input wire[`NUM_WARPS-1:0] fpu_pending, -`endif -`ifdef EXT_TEX_ENABLE - VX_tex_csr_if.master tex_csr_if, -`endif - - output wire[`NUM_WARPS-1:0] pending, - input wire busy -); - wire csr_we_s1; - wire [`CSR_ADDR_BITS-1:0] csr_addr_s1; - wire [31:0] csr_read_data; - wire [31:0] csr_read_data_s1; - wire [31:0] csr_updated_data_s1; - - wire write_enable = csr_commit_if.valid && csr_we_s1; - - wire [31:0] csr_req_data = csr_req_if.use_imm ? 32'(csr_req_if.imm) : csr_req_if.rs1_data; - - VX_csr_data #( - .CORE_ID(CORE_ID) - ) csr_data ( - .clk (clk), - .reset (reset), - `ifdef PERF_ENABLE - `ifdef EXT_TEX_ENABLE - .perf_tex_if (perf_tex_if), - `endif - .perf_memsys_if (perf_memsys_if), - .perf_pipeline_if(perf_pipeline_if), - `endif - .cmt_to_csr_if (cmt_to_csr_if), - .fetch_to_csr_if(fetch_to_csr_if), - `ifdef EXT_F_ENABLE - .fpu_to_csr_if (fpu_to_csr_if), - `endif - `ifdef EXT_TEX_ENABLE - .tex_csr_if (tex_csr_if), - `endif - .read_enable (csr_req_if.valid), - .read_uuid (csr_req_if.uuid), - .read_addr (csr_req_if.addr), - .read_wid (csr_req_if.wid), - .read_data (csr_read_data), - .write_enable (write_enable), - .write_uuid (csr_commit_if.uuid), - .write_addr (csr_addr_s1), - .write_wid (csr_commit_if.wid), - .write_data (csr_updated_data_s1), - .busy (busy) - ); - - wire write_hazard = (csr_addr_s1 == csr_req_if.addr) - && (csr_commit_if.wid == csr_req_if.wid) - && csr_commit_if.valid; - - wire [31:0] csr_read_data_qual = write_hazard ? csr_updated_data_s1 : csr_read_data; - - reg [31:0] csr_updated_data; - reg csr_we_s0_unqual; - - always @(*) begin - csr_we_s0_unqual = (csr_req_data != 0); - case (csr_req_if.op_type) - `INST_CSR_RW: begin - csr_updated_data = csr_req_data; - csr_we_s0_unqual = 1; - end - `INST_CSR_RS: begin - csr_updated_data = csr_read_data_qual | csr_req_data; - end - //`INST_CSR_RC - default: begin - csr_updated_data = csr_read_data_qual & ~csr_req_data; - end - endcase - end - -`ifdef EXT_F_ENABLE - wire stall_in = fpu_pending[csr_req_if.wid]; -`else - wire stall_in = 0; -`endif - - wire csr_req_valid = csr_req_if.valid && !stall_in; - - wire stall_out = ~csr_commit_if.ready && csr_commit_if.valid; - - VX_pipe_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1 + `CSR_ADDR_BITS + 32 + 32), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_out), - .data_in ({csr_req_valid, csr_req_if.uuid, csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.rd, csr_req_if.wb, csr_we_s0_unqual, csr_req_if.addr, csr_read_data_qual, csr_updated_data}), - .data_out ({csr_commit_if.valid, csr_commit_if.uuid, csr_commit_if.wid, csr_commit_if.tmask, csr_commit_if.PC, csr_commit_if.rd, csr_commit_if.wb, csr_we_s1, csr_addr_s1, csr_read_data_s1, csr_updated_data_s1}) - ); - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - assign csr_commit_if.data[i] = (csr_addr_s1 == `CSR_WTID) ? i : - (csr_addr_s1 == `CSR_LTID - || csr_addr_s1 == `CSR_GTID) ? (csr_read_data_s1 * `NUM_THREADS + i) : - csr_read_data_s1; - end - - assign csr_commit_if.eop = 1'b1; - - // can accept new request? - assign csr_req_if.ready = ~(stall_out || stall_in); - - // pending request - reg [`NUM_WARPS-1:0] pending_r; - always @(posedge clk) begin - if (reset) begin - pending_r <= 0; - end else begin - if (csr_commit_if.valid && csr_commit_if.ready) begin - pending_r[csr_commit_if.wid] <= 0; - end - if (csr_req_if.valid && csr_req_if.ready) begin - pending_r[csr_req_if.wid] <= 1; - end - end - end - assign pending = pending_r; - -endmodule diff --git a/hw/rtl/VX_decode.sv b/hw/rtl/VX_decode.sv deleted file mode 100644 index e6646a32..00000000 --- a/hw/rtl/VX_decode.sv +++ /dev/null @@ -1,495 +0,0 @@ -`include "VX_define.vh" -`ifdef DBG_TRACE_CORE_PIPELINE -`include "VX_trace_instr.vh" -`endif - -`ifdef EXT_F_ENABLE - `define USED_IREG(r) \ - r``_r = {1'b0, ``r} - - `define USED_FREG(r) \ - r``_r = {1'b1, ``r} -`else - `define USED_IREG(r) \ - r``_r = ``r -`endif - -module VX_decode #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE - VX_perf_pipeline_if.decode perf_decode_if, -`endif - - // inputs - VX_ifetch_rsp_if.slave ifetch_rsp_if, - - // outputs - VX_decode_if.master decode_if, - VX_wstall_if.master wstall_if, - VX_join_if.master join_if -); - `UNUSED_PARAM (CORE_ID) - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - reg [`EX_BITS-1:0] ex_type; - reg [`INST_OP_BITS-1:0] op_type; - reg [`INST_MOD_BITS-1:0] op_mod; - reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r; - reg [31:0] imm; - reg use_rd, use_PC, use_imm; - reg is_join, is_wstall; - - wire [31:0] instr = ifetch_rsp_if.data; - wire [6:0] opcode = instr[6:0]; - wire [1:0] func2 = instr[26:25]; - wire [2:0] func3 = instr[14:12]; - wire [6:0] func7 = instr[31:25]; - wire [11:0] u_12 = instr[31:20]; - - wire [4:0] rd = instr[11:7]; - wire [4:0] rs1 = instr[19:15]; - wire [4:0] rs2 = instr[24:20]; - wire [4:0] rs3 = instr[31:27]; - - wire [19:0] upper_imm = {func7, rs2, rs1, func3}; - wire [11:0] alu_imm = (func3[0] && ~func3[1]) ? {{7{1'b0}}, rs2} : u_12; - wire [11:0] s_imm = {func7, rd}; - wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; - wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; - - `UNUSED_VAR (rs3) - - always @(*) begin - - ex_type = 0; - op_type = 'x; - op_mod = 0; - rd_r = 0; - rs1_r = 0; - rs2_r = 0; - rs3_r = 0; - imm = 'x; - use_imm = 0; - use_PC = 0; - use_rd = 0; - is_join = 0; - is_wstall = 0; - - case (opcode) - `INST_I: begin - ex_type = `EX_ALU; - case (func3) - 3'h0: op_type = `INST_OP_BITS'(`INST_ALU_ADD); - 3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL); - 3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT); - 3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU); - 3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR); - 3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL); - 3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR); - 3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND); - default:; - endcase - use_rd = 1; - use_imm = 1; - imm = {{20{alu_imm[11]}}, alu_imm}; - `USED_IREG (rd); - `USED_IREG (rs1); - end - `INST_R: begin - ex_type = `EX_ALU; - `ifdef EXT_F_ENABLE - if (func7[0]) begin - case (func3) - 3'h0: op_type = `INST_OP_BITS'(`INST_MUL_MUL); - 3'h1: op_type = `INST_OP_BITS'(`INST_MUL_MULH); - 3'h2: op_type = `INST_OP_BITS'(`INST_MUL_MULHSU); - 3'h3: op_type = `INST_OP_BITS'(`INST_MUL_MULHU); - 3'h4: op_type = `INST_OP_BITS'(`INST_MUL_DIV); - 3'h5: op_type = `INST_OP_BITS'(`INST_MUL_DIVU); - 3'h6: op_type = `INST_OP_BITS'(`INST_MUL_REM); - 3'h7: op_type = `INST_OP_BITS'(`INST_MUL_REMU); - default:; - endcase - op_mod = 2; - end else - `endif - begin - case (func3) - 3'h0: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SUB) : `INST_OP_BITS'(`INST_ALU_ADD); - 3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL); - 3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT); - 3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU); - 3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR); - 3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL); - 3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR); - 3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND); - default:; - endcase - end - use_rd = 1; - `USED_IREG (rd); - `USED_IREG (rs1); - `USED_IREG (rs2); - end - `INST_LUI: begin - ex_type = `EX_ALU; - op_type = `INST_OP_BITS'(`INST_ALU_LUI); - use_rd = 1; - use_imm = 1; - imm = {upper_imm, 12'(0)}; - `USED_IREG (rd); - rs1_r = 0; - end - `INST_AUIPC: begin - ex_type = `EX_ALU; - op_type = `INST_OP_BITS'(`INST_ALU_AUIPC); - use_rd = 1; - use_imm = 1; - use_PC = 1; - imm = {upper_imm, 12'(0)}; - `USED_IREG (rd); - end - `INST_JAL: begin - ex_type = `EX_ALU; - op_type = `INST_OP_BITS'(`INST_BR_JAL); - op_mod = 1; - use_rd = 1; - use_imm = 1; - use_PC = 1; - is_wstall = 1; - imm = {{11{jal_imm[20]}}, jal_imm}; - `USED_IREG (rd); - end - `INST_JALR: begin - ex_type = `EX_ALU; - op_type = `INST_OP_BITS'(`INST_BR_JALR); - op_mod = 1; - use_rd = 1; - use_imm = 1; - is_wstall = 1; - imm = {{20{u_12[11]}}, u_12}; - `USED_IREG (rd); - `USED_IREG (rs1); - end - `INST_B: begin - ex_type = `EX_ALU; - case (func3) - 3'h0: op_type = `INST_OP_BITS'(`INST_BR_EQ); - 3'h1: op_type = `INST_OP_BITS'(`INST_BR_NE); - 3'h4: op_type = `INST_OP_BITS'(`INST_BR_LT); - 3'h5: op_type = `INST_OP_BITS'(`INST_BR_GE); - 3'h6: op_type = `INST_OP_BITS'(`INST_BR_LTU); - 3'h7: op_type = `INST_OP_BITS'(`INST_BR_GEU); - default:; - endcase - op_mod = 1; - use_imm = 1; - use_PC = 1; - is_wstall = 1; - imm = {{19{b_imm[12]}}, b_imm}; - `USED_IREG (rs1); - `USED_IREG (rs2); - end - `INST_FENCE: begin - ex_type = `EX_LSU; - op_mod = `INST_MOD_BITS'(1); - end - `INST_SYS : begin - if (func3[1:0] != 0) begin - ex_type = `EX_CSR; - op_type = `INST_OP_BITS'(func3[1:0]); - use_rd = 1; - use_imm = func3[2]; - imm[`CSR_ADDR_BITS-1:0] = u_12; // addr - `USED_IREG (rd); - if (func3[2]) begin - imm[`CSR_ADDR_BITS +: `NRI_BITS] = rs1; // imm - end else begin - `USED_IREG (rs1); - end - end else begin - ex_type = `EX_ALU; - case (u_12) - 12'h000: op_type = `INST_OP_BITS'(`INST_BR_ECALL); - 12'h001: op_type = `INST_OP_BITS'(`INST_BR_EBREAK); - 12'h002: op_type = `INST_OP_BITS'(`INST_BR_URET); - 12'h102: op_type = `INST_OP_BITS'(`INST_BR_SRET); - 12'h302: op_type = `INST_OP_BITS'(`INST_BR_MRET); - default:; - endcase - op_mod = 1; - use_rd = 1; - use_imm = 1; - use_PC = 1; - is_wstall = 1; - imm = 32'd4; - `USED_IREG (rd); - end - end - `ifdef EXT_F_ENABLE - `INST_FL, - `endif - `INST_L: begin - ex_type = `EX_LSU; - op_type = `INST_OP_BITS'({1'b0, func3}); - use_rd = 1; - imm = {{20{u_12[11]}}, u_12}; - `ifdef EXT_F_ENABLE - if (opcode[2]) begin - `USED_FREG (rd); - end else - `endif - `USED_IREG (rd); - `USED_IREG (rs1); - end - `ifdef EXT_F_ENABLE - `INST_FS, - `endif - `INST_S: begin - ex_type = `EX_LSU; - op_type = `INST_OP_BITS'({1'b1, func3}); - imm = {{20{s_imm[11]}}, s_imm}; - `USED_IREG (rs1); - `ifdef EXT_F_ENABLE - if (opcode[2]) begin - `USED_FREG (rs2); - end else - `endif - `USED_IREG (rs2); - end - `ifdef EXT_F_ENABLE - `INST_FMADD, - `INST_FMSUB, - `INST_FNMSUB, - `INST_FNMADD: begin - ex_type = `EX_FPU; - op_type = `INST_OP_BITS'(opcode[3:0]); - op_mod = func3; - use_rd = 1; - `USED_FREG (rd); - `USED_FREG (rs1); - `USED_FREG (rs2); - `USED_FREG (rs3); - end - `INST_FCI: begin - ex_type = `EX_FPU; - op_mod = func3; - use_rd = 1; - case (func7) - 7'h00, // FADD - 7'h04, // FSUB - 7'h08, // FMUL - 7'h0C: begin // FDIV - op_type = `INST_OP_BITS'(func7[3:0]); - `USED_FREG (rd); - `USED_FREG (rs1); - `USED_FREG (rs2); - end - 7'h2C: begin - op_type = `INST_OP_BITS'(`INST_FPU_SQRT); - `USED_FREG (rd); - `USED_FREG (rs1); - end - 7'h50: begin - op_type = `INST_OP_BITS'(`INST_FPU_CMP); - `USED_IREG (rd); - `USED_FREG (rs1); - `USED_FREG (rs2); - end - 7'h60: begin - op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTWUS) : `INST_OP_BITS'(`INST_FPU_CVTWS); - `USED_IREG (rd); - `USED_FREG (rs1); - end - 7'h68: begin - op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTSWU) : `INST_OP_BITS'(`INST_FPU_CVTSW); - `USED_FREG (rd); - `USED_IREG (rs1); - end - 7'h10: begin - // FSGNJ=0, FSGNJN=1, FSGNJX=2 - op_type = `INST_OP_BITS'(`INST_FPU_MISC); - op_mod = {1'b0, func3[1:0]}; - `USED_FREG (rd); - `USED_FREG (rs1); - `USED_FREG (rs2); - end - 7'h14: begin - // FMIN=3, FMAX=4 - op_type = `INST_OP_BITS'(`INST_FPU_MISC); - op_mod = func3[0] ? 4 : 3; - `USED_FREG (rd); - `USED_FREG (rs1); - `USED_FREG (rs2); - end - 7'h70: begin - if (func3[0]) begin - // FCLASS - op_type = `INST_OP_BITS'(`INST_FPU_CLASS); - end else begin - // FMV.X.W=5 - op_type = `INST_OP_BITS'(`INST_FPU_MISC); - op_mod = 5; - end - `USED_IREG (rd); - `USED_FREG (rs1); - end - 7'h78: begin - // FMV.W.X=6 - op_type = `INST_OP_BITS'(`INST_FPU_MISC); - op_mod = 6; - `USED_FREG (rd); - `USED_IREG (rs1); - end - default:; - endcase - end - `endif - `INST_GPGPU: begin - ex_type = `EX_GPU; - case (func3) - 3'h0: begin - op_type = rs2[0] ? `INST_OP_BITS'(`INST_GPU_PRED) : `INST_OP_BITS'(`INST_GPU_TMC); - is_wstall = 1; - `USED_IREG (rs1); - end - 3'h1: begin - op_type = `INST_OP_BITS'(`INST_GPU_WSPAWN); - `USED_IREG (rs1); - `USED_IREG (rs2); - end - 3'h2: begin - op_type = `INST_OP_BITS'(`INST_GPU_SPLIT); - is_wstall = 1; - `USED_IREG (rs1); - end - 3'h3: begin - op_type = `INST_OP_BITS'(`INST_GPU_JOIN); - is_join = 1; - end - 3'h4: begin - op_type = `INST_OP_BITS'(`INST_GPU_BAR); - is_wstall = 1; - `USED_IREG (rs1); - `USED_IREG (rs2); - end - 3'h5: begin - ex_type = `EX_LSU; - op_type = `INST_OP_BITS'(`INST_LSU_LW); - op_mod = `INST_MOD_BITS'(2); - `USED_IREG (rs1); - end - default:; - endcase - end - `INST_GPU: begin - case (func3) - `ifdef EXT_TEX_ENABLE - 3'h0: begin - ex_type = `EX_GPU; - op_type = `INST_OP_BITS'(`INST_GPU_TEX); - op_mod = `INST_MOD_BITS'(func2); - use_rd = 1; - `USED_IREG (rd); - `USED_IREG (rs1); - `USED_IREG (rs2); - `USED_IREG (rs3); - end - `endif - default:; - endcase - end - default:; - endcase - end - - `UNUSED_VAR (func2) - - // disable write to integer register r0 - wire wb = use_rd && (| rd_r); - - assign decode_if.valid = ifetch_rsp_if.valid; - assign decode_if.uuid = ifetch_rsp_if.uuid; - assign decode_if.wid = ifetch_rsp_if.wid; - assign decode_if.tmask = ifetch_rsp_if.tmask; - assign decode_if.PC = ifetch_rsp_if.PC; - assign decode_if.ex_type = ex_type; - assign decode_if.op_type = op_type; - assign decode_if.op_mod = op_mod; - assign decode_if.wb = wb; - assign decode_if.rd = rd_r; - assign decode_if.rs1 = rs1_r; - assign decode_if.rs2 = rs2_r; - assign decode_if.rs3 = rs3_r; - assign decode_if.imm = imm; - assign decode_if.use_PC = use_PC; - assign decode_if.use_imm = use_imm; - - /////////////////////////////////////////////////////////////////////////// - - wire ifetch_rsp_fire = ifetch_rsp_if.valid && ifetch_rsp_if.ready; - - assign join_if.valid = ifetch_rsp_fire && is_join; - assign join_if.wid = ifetch_rsp_if.wid; - - assign wstall_if.valid = ifetch_rsp_fire; - assign wstall_if.wid = ifetch_rsp_if.wid; - assign wstall_if.stalled = is_wstall; - - assign ifetch_rsp_if.ready = decode_if.ready; - -`ifdef PERF_ENABLE - wire [$clog2(`NUM_THREADS+1)-1:0] perf_loads_per_cycle; - wire [$clog2(`NUM_THREADS+1)-1:0] perf_stores_per_cycle; - wire [$clog2(`NUM_THREADS+1)-1:0] perf_branches_per_cycle; - - wire [`NUM_THREADS-1:0] perf_loads_per_mask = decode_if.tmask & {`NUM_THREADS{decode_if.ex_type == `EX_LSU && `INST_LSU_IS_MEM(decode_if.op_mod) && decode_if.wb}}; - wire [`NUM_THREADS-1:0] perf_stores_per_mask = decode_if.tmask & {`NUM_THREADS{decode_if.ex_type == `EX_LSU && `INST_LSU_IS_MEM(decode_if.op_mod) && ~decode_if.wb}}; - wire [`NUM_THREADS-1:0] perf_branches_per_mask = decode_if.tmask & {`NUM_THREADS{decode_if.ex_type == `EX_ALU && `INST_ALU_IS_BR(decode_if.op_mod)}}; - - `POP_COUNT(perf_loads_per_cycle, perf_loads_per_mask); - `POP_COUNT(perf_stores_per_cycle, perf_stores_per_mask); - `POP_COUNT(perf_branches_per_cycle, perf_branches_per_mask); - - reg [`PERF_CTR_BITS-1:0] perf_loads; - reg [`PERF_CTR_BITS-1:0] perf_stores; - reg [`PERF_CTR_BITS-1:0] perf_branches; - - always @(posedge clk) begin - if (reset) begin - perf_loads <= 0; - perf_stores <= 0; - perf_branches <= 0; - end else begin - if (decode_if.valid && decode_if.ready) begin - perf_loads <= perf_loads + `PERF_CTR_BITS'(perf_loads_per_cycle); - perf_stores <= perf_stores + `PERF_CTR_BITS'(perf_stores_per_cycle); - perf_branches <= perf_branches + `PERF_CTR_BITS'(perf_branches_per_cycle); - end - end - end - - assign perf_decode_if.loads = perf_loads; - assign perf_decode_if.stores = perf_stores; - assign perf_decode_if.branches = perf_branches; -`endif - -`ifdef DBG_TRACE_CORE_PIPELINE - always @(posedge clk) begin - if (decode_if.valid && decode_if.ready) begin - dpi_trace("%d: core%0d-decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC); - trace_ex_type(decode_if.ex_type); - dpi_trace(", op="); - trace_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod); - dpi_trace(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b (#%0d)\n", - decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.use_PC, decode_if.use_imm, decode_if.uuid); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 2badf7f8..31714580 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -1,416 +1,425 @@ -`ifndef VX_DEFINE -`define VX_DEFINE - -`include "VX_platform.vh" -`include "VX_config.vh" - -/////////////////////////////////////////////////////////////////////////////// - -`define NW_BITS `LOG2UP(`NUM_WARPS) - -`define NT_BITS `LOG2UP(`NUM_THREADS) - -`define NC_BITS `LOG2UP(`NUM_CORES) - -`define NB_BITS `LOG2UP(`NUM_BARRIERS) - -`define NUM_IREGS 32 - -`define NRI_BITS `LOG2UP(`NUM_IREGS) - -`define NTEX_BITS `LOG2UP(`NUM_TEX_UNITS) - -`ifdef EXT_F_ENABLE -`define NUM_REGS (2 * `NUM_IREGS) -`else -`define NUM_REGS `NUM_IREGS -`endif - -`define NR_BITS `LOG2UP(`NUM_REGS) - -`define CSR_ADDR_BITS 12 - -`define CSR_WIDTH 12 - -`define PERF_CTR_BITS 44 - -`define UUID_BITS 44 - -/////////////////////////////////////////////////////////////////////////////// - -`define EX_NOP 3'h0 -`define EX_ALU 3'h1 -`define EX_LSU 3'h2 -`define EX_CSR 3'h3 -`define EX_FPU 3'h4 -`define EX_GPU 3'h5 -`define EX_BITS 3 - -/////////////////////////////////////////////////////////////////////////////// - -`define INST_LUI 7'b0110111 -`define INST_AUIPC 7'b0010111 -`define INST_JAL 7'b1101111 -`define INST_JALR 7'b1100111 -`define INST_B 7'b1100011 // branch instructions -`define INST_L 7'b0000011 // load instructions -`define INST_S 7'b0100011 // store instructions -`define INST_I 7'b0010011 // immediate instructions -`define INST_R 7'b0110011 // register instructions -`define INST_FENCE 7'b0001111 // Fence instructions -`define INST_SYS 7'b1110011 // system instructions - -`define INST_FL 7'b0000111 // float load instruction -`define INST_FS 7'b0100111 // float store instruction -`define INST_FMADD 7'b1000011 -`define INST_FMSUB 7'b1000111 -`define INST_FNMSUB 7'b1001011 -`define INST_FNMADD 7'b1001111 -`define INST_FCI 7'b1010011 // float common instructions - -`define INST_GPGPU 7'b1101011 -`define INST_GPU 7'b1011011 - -`define INST_TEX 7'b0101011 - -/////////////////////////////////////////////////////////////////////////////// - -`define INST_FRM_RNE 3'b000 // round to nearest even -`define INST_FRM_RTZ 3'b001 // round to zero -`define INST_FRM_RDN 3'b010 // round to -inf -`define INST_FRM_RUP 3'b011 // round to +inf -`define INST_FRM_RMM 3'b100 // round to nearest max magnitude -`define INST_FRM_DYN 3'b111 // dynamic mode -`define INST_FRM_BITS 3 - -/////////////////////////////////////////////////////////////////////////////// - -`define INST_OP_BITS 4 -`define INST_MOD_BITS 3 - -/////////////////////////////////////////////////////////////////////////////// - -`define INST_ALU_ADD 4'b0000 -`define INST_ALU_LUI 4'b0010 -`define INST_ALU_AUIPC 4'b0011 -`define INST_ALU_SLTU 4'b0100 -`define INST_ALU_SLT 4'b0101 -`define INST_ALU_SRL 4'b1000 -`define INST_ALU_SRA 4'b1001 -`define INST_ALU_SUB 4'b1011 -`define INST_ALU_AND 4'b1100 -`define INST_ALU_OR 4'b1101 -`define INST_ALU_XOR 4'b1110 -`define INST_ALU_SLL 4'b1111 -`define INST_ALU_OTHER 4'b0111 -`define INST_ALU_BITS 4 -`define INST_ALU_OP(x) x[`INST_ALU_BITS-1:0] -`define INST_ALU_OP_CLASS(x) x[3:2] -`define INST_ALU_SIGNED(x) x[0] -`define INST_ALU_IS_BR(x) x[0] -`define INST_ALU_IS_MUL(x) x[1] - -`define INST_BR_EQ 4'b0000 -`define INST_BR_NE 4'b0010 -`define INST_BR_LTU 4'b0100 -`define INST_BR_GEU 4'b0110 -`define INST_BR_LT 4'b0101 -`define INST_BR_GE 4'b0111 -`define INST_BR_JAL 4'b1000 -`define INST_BR_JALR 4'b1001 -`define INST_BR_ECALL 4'b1010 -`define INST_BR_EBREAK 4'b1011 -`define INST_BR_URET 4'b1100 -`define INST_BR_SRET 4'b1101 -`define INST_BR_MRET 4'b1110 -`define INST_BR_OTHER 4'b1111 -`define INST_BR_BITS 4 -`define INST_BR_NEG(x) x[1] -`define INST_BR_LESS(x) x[2] -`define INST_BR_STATIC(x) x[3] - -`define INST_MUL_MUL 3'h0 -`define INST_MUL_MULH 3'h1 -`define INST_MUL_MULHSU 3'h2 -`define INST_MUL_MULHU 3'h3 -`define INST_MUL_DIV 3'h4 -`define INST_MUL_DIVU 3'h5 -`define INST_MUL_REM 3'h6 -`define INST_MUL_REMU 3'h7 -`define INST_MUL_BITS 3 -`define INST_MUL_IS_DIV(x) x[2] - -`define INST_FMT_B 3'b000 -`define INST_FMT_H 3'b001 -`define INST_FMT_W 3'b010 -`define INST_FMT_BU 3'b100 -`define INST_FMT_HU 3'b101 - -`define INST_LSU_LB 4'b0000 -`define INST_LSU_LH 4'b0001 -`define INST_LSU_LW 4'b0010 -`define INST_LSU_LBU 4'b0100 -`define INST_LSU_LHU 4'b0101 -`define INST_LSU_SB 4'b1000 -`define INST_LSU_SH 4'b1001 -`define INST_LSU_SW 4'b1010 -`define INST_LSU_BITS 4 -`define INST_LSU_FMT(x) x[2:0] -`define INST_LSU_WSIZE(x) x[1:0] -`define INST_LSU_IS_MEM(x) (3'h0 == x) -`define INST_LSU_IS_FENCE(x) (3'h1 == x) -`define INST_LSU_IS_PREFETCH(x) (3'h2 == x) - -`define INST_FENCE_BITS 1 -`define INST_FENCE_D 1'h0 -`define INST_FENCE_I 1'h1 - -`define INST_CSR_RW 2'h1 -`define INST_CSR_RS 2'h2 -`define INST_CSR_RC 2'h3 -`define INST_CSR_OTHER 2'h0 -`define INST_CSR_BITS 2 - -`define INST_FPU_ADD 4'h0 -`define INST_FPU_SUB 4'h4 -`define INST_FPU_MUL 4'h8 -`define INST_FPU_DIV 4'hC -`define INST_FPU_CVTWS 4'h1 // FCVT.W.S -`define INST_FPU_CVTWUS 4'h5 // FCVT.WU.S -`define INST_FPU_CVTSW 4'h9 // FCVT.S.W -`define INST_FPU_CVTSWU 4'hD // FCVT.S.WU -`define INST_FPU_SQRT 4'h2 -`define INST_FPU_CLASS 4'h6 -`define INST_FPU_CMP 4'hA -`define INST_FPU_MISC 4'hE // SGNJ, SGNJN, SGNJX, FMIN, FMAX, MVXW, MVWX -`define INST_FPU_MADD 4'h3 -`define INST_FPU_MSUB 4'h7 -`define INST_FPU_NMSUB 4'hB -`define INST_FPU_NMADD 4'hF -`define INST_FPU_BITS 4 - -`define INST_GPU_TMC 4'h0 -`define INST_GPU_WSPAWN 4'h1 -`define INST_GPU_SPLIT 4'h2 -`define INST_GPU_JOIN 4'h3 -`define INST_GPU_BAR 4'h4 -`define INST_GPU_PRED 4'h5 -`define INST_GPU_TEX 4'h6 -`define INST_GPU_BITS 4 - -/////////////////////////////////////////////////////////////////////////////// - -`ifdef EXT_M_ENABLE - `define ISA_EXT_M (1 << 12) -`else - `define ISA_EXT_M 0 -`endif - -`ifdef EXT_F_ENABLE - `define ISA_EXT_F (1 << 5) -`else - `define ISA_EXT_F 0 -`endif - -`define ISA_CODE (0 << 0) // A - Atomic Instructions extension \ - | (0 << 1) // B - Tentatively reserved for Bit operations extension \ - | (0 << 2) // C - Compressed extension \ - | (0 << 3) // D - Double precsision floating-point extension \ - | (0 << 4) // E - RV32E base ISA \ - |`ISA_EXT_F // F - Single precsision floating-point extension \ - | (0 << 6) // G - Additional standard extensions present \ - | (0 << 7) // H - Hypervisor mode implemented \ - | (1 << 8) // I - RV32I/64I/128I base ISA \ - | (0 << 9) // J - Reserved \ - | (0 << 10) // K - Reserved \ - | (0 << 11) // L - Tentatively reserved for Bit operations extension \ - |`ISA_EXT_M // M - Integer Multiply/Divide extension \ - | (0 << 13) // N - User level interrupts supported \ - | (0 << 14) // O - Reserved \ - | (0 << 15) // P - Tentatively reserved for Packed-SIMD extension \ - | (0 << 16) // Q - Quad-precision floating-point extension \ - | (0 << 17) // R - Reserved \ - | (0 << 18) // S - Supervisor mode implemented \ - | (0 << 19) // T - Tentatively reserved for Transactional Memory extension \ - | (1 << 20) // U - User mode implemented \ - | (0 << 21) // V - Tentatively reserved for Vector extension \ - | (0 << 22) // W - Reserved \ - | (1 << 23) // X - Non-standard extensions present \ - | (0 << 24) // Y - Reserved \ - | (0 << 25) // Z - Reserved - -/////////////////////////////////////////////////////////////////////////////// - -// non-cacheable tag bits -`define NC_TAG_BIT 1 - -// texture tag bits -`define TEX_TAG_BIT 1 - -// cache address type bits -`define CACHE_ADDR_TYPE_BITS (`NC_TAG_BIT + `SM_ENABLE) - -////////////////////////// Icache Configurable Knobs ////////////////////////// - -// Cache ID -`define ICACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0) - -// Word size in bytes -`define ICACHE_WORD_SIZE 4 - -// Block size in bytes -`define ICACHE_LINE_SIZE `L1_BLOCK_SIZE - -// TAG sharing enable -`define ICACHE_CORE_TAG_ID_BITS `NW_BITS - -// Core request tag bits -`define ICACHE_CORE_TAG_WIDTH (`UUID_BITS + `ICACHE_CORE_TAG_ID_BITS) - -// Memory request data bits -`define ICACHE_MEM_DATA_WIDTH (`ICACHE_LINE_SIZE * 8) - -// Memory request address bits -`define ICACHE_MEM_ADDR_WIDTH (32 - `CLOG2(`ICACHE_LINE_SIZE)) - -// Memory request tag bits -`define ICACHE_MEM_TAG_WIDTH `CLOG2(`ICACHE_MSHR_SIZE) - -////////////////////////// Dcache Configurable Knobs ////////////////////////// - -// Cache ID -`define DCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1) - -// Word size in bytes -`define DCACHE_WORD_SIZE 4 - -// Block size in bytes -`define DCACHE_LINE_SIZE `L1_BLOCK_SIZE - -// Core request tag bits -`define LSUQ_ADDR_BITS `LOG2UP(`LSUQ_SIZE) -`ifdef EXT_TEX_ENABLE -`define LSU_TAG_ID_BITS `MAX(`LSUQ_ADDR_BITS, 2) -`define LSU_TEX_DCACHE_TAG_BITS (`UUID_BITS + `LSU_TAG_ID_BITS + `CACHE_ADDR_TYPE_BITS) -`define DCACHE_CORE_TAG_ID_BITS (`LSU_TAG_ID_BITS + `CACHE_ADDR_TYPE_BITS + `TEX_TAG_BIT) -`else -`define LSU_TAG_ID_BITS `LSUQ_ADDR_BITS -`define DCACHE_CORE_TAG_ID_BITS (`LSU_TAG_ID_BITS + `CACHE_ADDR_TYPE_BITS) -`endif -`define DCACHE_CORE_TAG_WIDTH (`UUID_BITS + `DCACHE_CORE_TAG_ID_BITS) - -// Memory request data bits -`define DCACHE_MEM_DATA_WIDTH (`DCACHE_LINE_SIZE * 8) - -// Memory request address bits -`define DCACHE_MEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE)) - -// Memory byte enable bits -`define DCACHE_MEM_BYTEEN_WIDTH `DCACHE_LINE_SIZE - -// Input request size -`define DCACHE_NUM_REQS `NUM_THREADS - -// Memory request tag bits -`define _DMEM_ADDR_RATIO_W $clog2(`DCACHE_LINE_SIZE / `DCACHE_WORD_SIZE) -`define _DNC_MEM_TAG_WIDTH ($clog2(`DCACHE_NUM_REQS) + `_DMEM_ADDR_RATIO_W + `DCACHE_CORE_TAG_WIDTH) -`define DCACHE_MEM_TAG_WIDTH `MAX((`CLOG2(`DCACHE_NUM_BANKS) + `CLOG2(`DCACHE_MSHR_SIZE) + `NC_TAG_BIT), `_DNC_MEM_TAG_WIDTH) - -// Merged D-cache/I-cache memory tag -`define L1_MEM_TAG_WIDTH (`MAX(`ICACHE_MEM_TAG_WIDTH, `DCACHE_MEM_TAG_WIDTH) + `CLOG2(2)) - -////////////////////////// SM Configurable Knobs ////////////////////////////// - -// Cache ID -`define SMEM_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 2) - -// Word size in bytes -`define SMEM_WORD_SIZE 4 - -// bank address offset -`define SMEM_BANK_ADDR_OFFSET `CLOG2(`STACK_SIZE / `SMEM_WORD_SIZE) - -// Input request size -`define SMEM_NUM_REQS `NUM_THREADS - -////////////////////////// L2cache Configurable Knobs ///////////////////////// - -// Cache ID -`define L2_CACHE_ID (32'(`L3_ENABLE) + CLUSTER_ID) - -// Word size in bytes -`define L2_WORD_SIZE `DCACHE_LINE_SIZE - -// Block size in bytes -`define L2_CACHE_LINE_SIZE ((`L2_ENABLE) ? `MEM_BLOCK_SIZE : `L2_WORD_SIZE) - -// Input request tag bits -`define L2_CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH + `CLOG2(`NUM_CORES)) - -// Memory request data bits -`define L2_MEM_DATA_WIDTH (`L2_CACHE_LINE_SIZE * 8) - -// Memory request address bits -`define L2_MEM_ADDR_WIDTH (32 - `CLOG2(`L2_CACHE_LINE_SIZE)) - -// Memory byte enable bits -`define L2_MEM_BYTEEN_WIDTH `L2_CACHE_LINE_SIZE - -// Input request size -`define L2_NUM_REQS `NUM_CORES - -// Memory request tag bits -`define _L2_MEM_ADDR_RATIO_W $clog2(`L2_CACHE_LINE_SIZE / `L2_WORD_SIZE) -`define _L2_NC_MEM_TAG_WIDTH ($clog2(`L2_NUM_REQS) + `_L2_MEM_ADDR_RATIO_W + `L1_MEM_TAG_WIDTH) -`define _L2_MEM_TAG_WIDTH `MAX((`CLOG2(`L2_NUM_BANKS) + `CLOG2(`L2_MSHR_SIZE) + `NC_TAG_BIT), `_L2_NC_MEM_TAG_WIDTH) -`define L2_MEM_TAG_WIDTH ((`L2_ENABLE) ? `_L2_MEM_TAG_WIDTH : (`L1_MEM_TAG_WIDTH + `CLOG2(`L2_NUM_REQS))) - -////////////////////////// L3cache Configurable Knobs ///////////////////////// - -// Cache ID -`define L3_CACHE_ID 0 - -// Word size in bytes -`define L3_WORD_SIZE `L2_CACHE_LINE_SIZE - -// Block size in bytes -`define L3_CACHE_LINE_SIZE ((`L3_ENABLE) ? `MEM_BLOCK_SIZE : `L3_WORD_SIZE) - -// Input request tag bits -`define L3_CORE_TAG_WIDTH (`L2_CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS)) - -// Memory request data bits -`define L3_MEM_DATA_WIDTH (`L3_CACHE_LINE_SIZE * 8) - -// Memory request address bits -`define L3_MEM_ADDR_WIDTH (32 - `CLOG2(`L3_CACHE_LINE_SIZE)) - -// Memory byte enable bits -`define L3_MEM_BYTEEN_WIDTH `L3_CACHE_LINE_SIZE - -// Input request size -`define L3_NUM_REQS `NUM_CLUSTERS - -// Memory request tag bits -`define _L3_MEM_ADDR_RATIO_W $clog2(`L3_CACHE_LINE_SIZE / `L3_WORD_SIZE) -`define _L3_NC_MEM_TAG_WIDTH ($clog2(`L3_NUM_REQS) + `_L3_MEM_ADDR_RATIO_W + `L2_MEM_TAG_WIDTH) -`define _L3_MEM_TAG_WIDTH `MAX((`CLOG2(`L3_NUM_BANKS) + `CLOG2(`L3_MSHR_SIZE) + `NC_TAG_BIT), `_L3_NC_MEM_TAG_WIDTH) -`define L3_MEM_TAG_WIDTH ((`L3_ENABLE) ? `_L3_MEM_TAG_WIDTH : (`L2_MEM_TAG_WIDTH + `CLOG2(`L3_NUM_REQS))) - -/////////////////////////////////////////////////////////////////////////////// - -`define VX_MEM_BYTEEN_WIDTH `L3_MEM_BYTEEN_WIDTH -`define VX_MEM_ADDR_WIDTH `L3_MEM_ADDR_WIDTH -`define VX_MEM_DATA_WIDTH `L3_MEM_DATA_WIDTH -`define VX_MEM_TAG_WIDTH `L3_MEM_TAG_WIDTH -`define VX_CORE_TAG_WIDTH `L3_CORE_TAG_WIDTH -`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES) - -`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)} - -/////////////////////////////////////////////////////////////////////////////// - -`include "VX_fpu_types.vh" -`include "VX_gpu_types.vh" - -`endif +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_DEFINE_VH +`define VX_DEFINE_VH + +`include "VX_platform.vh" +`include "VX_config.vh" +`include "VX_types.vh" + +/////////////////////////////////////////////////////////////////////////////// + +`define NW_BITS `CLOG2(`NUM_WARPS) +`define NC_WIDTH `UP(`NC_BITS) + +`define NT_BITS `CLOG2(`NUM_THREADS) +`define NW_WIDTH `UP(`NW_BITS) + +`define NC_BITS `CLOG2(`NUM_CORES) +`define NT_WIDTH `UP(`NT_BITS) + +`define NB_BITS `CLOG2(`NUM_BARRIERS) +`define NB_WIDTH `UP(`NB_BITS) + +`define NUM_IREGS 32 + +`define NRI_BITS `CLOG2(`NUM_IREGS) + +`ifdef EXT_F_ENABLE +`define NUM_REGS (2 * `NUM_IREGS) +`else +`define NUM_REGS `NUM_IREGS +`endif + +`define NR_BITS `CLOG2(`NUM_REGS) + +`define PERF_CTR_BITS 44 + +`ifndef NDEBUG +`define UUID_WIDTH 44 +`else +`define UUID_WIDTH 1 +`endif + +/////////////////////////////////////////////////////////////////////////////// + +`define EX_ALU 0 +`define EX_LSU 1 +`define EX_SFU 2 +`define EX_FPU 3 + +`define NUM_EX_UNITS (3 + `EXT_F_ENABLED) +`define EX_BITS `CLOG2(`NUM_EX_UNITS) + +/////////////////////////////////////////////////////////////////////////////// + +`define INST_LUI 7'b0110111 +`define INST_AUIPC 7'b0010111 +`define INST_JAL 7'b1101111 +`define INST_JALR 7'b1100111 +`define INST_B 7'b1100011 // branch instructions +`define INST_L 7'b0000011 // load instructions +`define INST_S 7'b0100011 // store instructions +`define INST_I 7'b0010011 // immediate instructions +`define INST_R 7'b0110011 // register instructions +`define INST_FENCE 7'b0001111 // Fence instructions +`define INST_SYS 7'b1110011 // system instructions + +// RV64I instruction specific opcodes (for any W instruction) +`define INST_I_W 7'b0011011 // W type immediate instructions +`define INST_R_W 7'b0111011 // W type register instructions + +`define INST_FL 7'b0000111 // float load instruction +`define INST_FS 7'b0100111 // float store instruction +`define INST_FMADD 7'b1000011 +`define INST_FMSUB 7'b1000111 +`define INST_FNMSUB 7'b1001011 +`define INST_FNMADD 7'b1001111 +`define INST_FCI 7'b1010011 // float common instructions + +// Custom extension opcodes +`define INST_EXT1 7'b0001011 // 0x0B +`define INST_EXT2 7'b0101011 // 0x2B +`define INST_EXT3 7'b1011011 // 0x5B +`define INST_EXT4 7'b1111011 // 0x7B + +/////////////////////////////////////////////////////////////////////////////// + +`define INST_FRM_RNE 3'b000 // round to nearest even +`define INST_FRM_RTZ 3'b001 // round to zero +`define INST_FRM_RDN 3'b010 // round to -inf +`define INST_FRM_RUP 3'b011 // round to +inf +`define INST_FRM_RMM 3'b100 // round to nearest max magnitude +`define INST_FRM_DYN 3'b111 // dynamic mode +`define INST_FRM_BITS 3 + +/////////////////////////////////////////////////////////////////////////////// + +`define INST_OP_BITS 4 +`define INST_MOD_BITS 3 +`define INST_FMT_BITS 2 + +/////////////////////////////////////////////////////////////////////////////// + +`define INST_ALU_ADD 4'b0000 +`define INST_ALU_LUI 4'b0010 +`define INST_ALU_AUIPC 4'b0011 +`define INST_ALU_SLTU 4'b0100 +`define INST_ALU_SLT 4'b0101 +`define INST_ALU_SUB 4'b0111 +`define INST_ALU_SRL 4'b1000 +`define INST_ALU_SRA 4'b1001 +`define INST_ALU_AND 4'b1100 +`define INST_ALU_OR 4'b1101 +`define INST_ALU_XOR 4'b1110 +`define INST_ALU_SLL 4'b1111 +`define INST_ALU_OTHER 4'b0111 +`define INST_ALU_BITS 4 +`define INST_ALU_CLASS(op) op[3:2] +`define INST_ALU_SIGNED(op) op[0] +`define INST_ALU_IS_SUB(op) op[1] +`define INST_ALU_IS_BR(mod) mod[0] +`define INST_ALU_IS_M(mod) mod[1] +`define INST_ALU_IS_W(mod) mod[2] + +`define INST_BR_EQ 4'b0000 +`define INST_BR_NE 4'b0010 +`define INST_BR_LTU 4'b0100 +`define INST_BR_GEU 4'b0110 +`define INST_BR_LT 4'b0101 +`define INST_BR_GE 4'b0111 +`define INST_BR_JAL 4'b1000 +`define INST_BR_JALR 4'b1001 +`define INST_BR_ECALL 4'b1010 +`define INST_BR_EBREAK 4'b1011 +`define INST_BR_URET 4'b1100 +`define INST_BR_SRET 4'b1101 +`define INST_BR_MRET 4'b1110 +`define INST_BR_OTHER 4'b1111 +`define INST_BR_BITS 4 +`define INST_BR_CLASS(op) {1'b0, ~op[3]} +`define INST_BR_IS_NEG(op) op[1] +`define INST_BR_IS_LESS(op) op[2] +`define INST_BR_IS_STATIC(op) op[3] + +`define INST_M_MUL 3'b000 +`define INST_M_MULHU 3'b001 +`define INST_M_MULH 3'b010 +`define INST_M_MULHSU 3'b011 +`define INST_M_DIV 3'b100 +`define INST_M_DIVU 3'b101 +`define INST_M_REM 3'b110 +`define INST_M_REMU 3'b111 +`define INST_M_BITS 3 +`define INST_M_SIGNED(op) (~op[0]) +`define INST_M_IS_MULX(op) (~op[2]) +`define INST_M_IS_MULH(op) (op[1:0] != 0) +`define INST_M_SIGNED_A(op) (op[1:0] != 1) +`define INST_M_IS_REM(op) op[1] + +`define INST_FMT_B 3'b000 +`define INST_FMT_H 3'b001 +`define INST_FMT_W 3'b010 +`define INST_FMT_D 3'b011 +`define INST_FMT_BU 3'b100 +`define INST_FMT_HU 3'b101 +`define INST_FMT_WU 3'b110 + +`define INST_LSU_LB 4'b0000 +`define INST_LSU_LH 4'b0001 +`define INST_LSU_LW 4'b0010 +`define INST_LSU_LD 4'b0011 // new for RV64I LD +`define INST_LSU_LBU 4'b0100 +`define INST_LSU_LHU 4'b0101 +`define INST_LSU_LWU 4'b0110 // new for RV64I LWU +`define INST_LSU_SB 4'b1000 +`define INST_LSU_SH 4'b1001 +`define INST_LSU_SW 4'b1010 +`define INST_LSU_SD 4'b1011 // new for RV64I SD +`define INST_LSU_FENCE 4'b1111 +`define INST_LSU_BITS 4 +`define INST_LSU_FMT(op) op[2:0] +`define INST_LSU_WSIZE(op) op[1:0] +`define INST_LSU_IS_FENCE(op) (op[3:2] == 3) + +`define INST_FENCE_BITS 1 +`define INST_FENCE_D 1'h0 +`define INST_FENCE_I 1'h1 + +`define INST_FPU_ADD 4'b0000 +`define INST_FPU_SUB 4'b0001 +`define INST_FPU_MUL 4'b0010 +`define INST_FPU_DIV 4'b0011 +`define INST_FPU_SQRT 4'b0100 +`define INST_FPU_CMP 4'b0101 // mod: LE=0, LT=1, EQ=2 +`define INST_FPU_F2F 4'b0110 +`define INST_FPU_MISC 4'b0111 // mod: SGNJ=0, SGNJN=1, SGNJX=2, CLASS=3, MVXW=4, MVWX=5, FMIN=6, FMAX=7 +`define INST_FPU_F2I 4'b1000 +`define INST_FPU_F2U 4'b1001 +`define INST_FPU_I2F 4'b1010 +`define INST_FPU_U2F 4'b1011 +`define INST_FPU_MADD 4'b1100 +`define INST_FPU_MSUB 4'b1101 +`define INST_FPU_NMSUB 4'b1110 +`define INST_FPU_NMADD 4'b1111 +`define INST_FPU_BITS 4 +`define INST_FPU_IS_W(mod) (mod[4]) +`define INST_FPU_IS_CLASS(op, mod) (op == `INST_FPU_MISC && mod == 3) +`define INST_FPU_IS_MVXW(op, mod) (op == `INST_FPU_MISC && mod == 4) + +`define INST_SFU_TMC 4'h0 +`define INST_SFU_WSPAWN 4'h1 +`define INST_SFU_SPLIT 4'h2 +`define INST_SFU_JOIN 4'h3 +`define INST_SFU_BAR 4'h4 +`define INST_SFU_PRED 4'h5 +`define INST_SFU_CSRRW 4'h6 +`define INST_SFU_CSRRS 4'h7 +`define INST_SFU_CSRRC 4'h8 +`define INST_SFU_TEX 4'h9 +`define INST_SFU_RASTER 4'hA +`define INST_SFU_ROP 4'hB +`define INST_SFU_CMOV 4'hC +`define INST_SFU_BITS 4 +`define INST_SFU_CSR(f3) (4'h6 + 4'(f3) - 4'h1) +`define INST_SFU_IS_WCTL(op) (op <= 5) +`define INST_SFU_IS_CSR(op) (op >= 6 && op <= 8) + +/////////////////////////////////////////////////////////////////////////////// + +`define NUM_SOCKETS `UP(`NUM_CORES / `SOCKET_SIZE) + +/////////////////////////////////////////////////////////////////////////////// + +// non-cacheable tag bits +`define NC_TAG_BITS 1 + +// cache address type bits +`ifdef SM_ENABLE +`define CACHE_ADDR_TYPE_BITS (`NC_TAG_BITS + 1) +`else +`define CACHE_ADDR_TYPE_BITS `NC_TAG_BITS +`endif + +`define ARB_SEL_BITS(I, O) ((I > O) ? `CLOG2((I + O - 1) / O) : 0) + +/////////////////////////////////////////////////////////////////////////////// + +`define CACHE_MEM_TAG_WIDTH(mshr_size, num_banks) \ + (`CLOG2(mshr_size) + `CLOG2(num_banks) + `NC_TAG_BITS) + +`define CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width) \ + (`CLOG2(num_reqs) + `CLOG2(line_size / word_size) + tag_width) + +`define CACHE_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width) \ + (`CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width) + `NC_TAG_BITS) + +`define CACHE_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, line_size, word_size, tag_width) \ + `MAX(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks), `CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width)) + +/////////////////////////////////////////////////////////////////////////////// + +`define CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches) \ + (tag_width + `ARB_SEL_BITS(num_inputs, `UP(num_caches))) + +`define CACHE_CLUSTER_MEM_ARB_TAG(tag_width, num_caches) \ + (tag_width + `ARB_SEL_BITS(`UP(num_caches), 1)) + +`define CACHE_CLUSTER_MEM_TAG_WIDTH(mshr_size, num_banks, num_caches) \ + `CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks), num_caches) + +`define CACHE_CLUSTER_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \ + `CACHE_CLUSTER_MEM_ARB_TAG((`CLOG2(num_reqs) + `CLOG2(line_size / word_size) + `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches)), num_caches) + +`define CACHE_CLUSTER_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \ + `CACHE_CLUSTER_MEM_ARB_TAG((`CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches)) + `NC_TAG_BITS), num_caches) + +`define CACHE_CLUSTER_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \ + `CACHE_CLUSTER_MEM_ARB_TAG(`MAX(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks), `CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches))), num_caches) + +/////////////////////////////////////////////////////////////////////////////// + +`ifdef L2_ENABLE +`define L2_LINE_SIZE `MEM_BLOCK_SIZE +`else +`define L2_LINE_SIZE `L1_LINE_SIZE +`endif + +`ifdef L3_ENABLE +`define L3_LINE_SIZE `MEM_BLOCK_SIZE +`else +`define L3_LINE_SIZE `L2_LINE_SIZE +`endif + +`define VX_MEM_BYTEEN_WIDTH `L3_LINE_SIZE +`define VX_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH - `CLOG2(`L3_LINE_SIZE)) +`define VX_MEM_DATA_WIDTH (`L3_LINE_SIZE * 8) +`define VX_MEM_TAG_WIDTH L3_MEM_TAG_WIDTH + +`define VX_DCR_ADDR_WIDTH `VX_DCR_ADDR_BITS +`define VX_DCR_DATA_WIDTH 32 + +`define TO_FULL_ADDR(x) {x, (`MEM_ADDR_WIDTH-$bits(x))'(0)} + +/////////////////////////////////////////////////////////////////////////////// + +`define BUFFER_BUSY(dst, src, enable) \ + logic __busy; \ + if (enable) begin \ + always @(posedge clk) begin \ + if (reset) begin \ + __busy <= 1'b0; \ + end else begin \ + __busy <= src; \ + end \ + end \ + end else begin \ + assign __busy = src; \ + end \ + assign dst = __busy + +`define POP_COUNT_EX(out, in, model) \ + VX_popcount #( \ + .N ($bits(in)), \ + .MODEL (model) \ + ) __``out ( \ + .data_in (in), \ + .data_out (out) \ + ) + +`define POP_COUNT(out, in) `POP_COUNT_EX(out, in, 1) + +`define ASSIGN_VX_MEM_BUS_IF(dst, src) \ + assign dst.req_valid = src.req_valid; \ + assign dst.req_data = src.req_data; \ + assign src.req_ready = dst.req_ready; \ + assign src.rsp_valid = dst.rsp_valid; \ + assign src.rsp_data = dst.rsp_data; \ + assign dst.rsp_ready = src.rsp_ready + +`define ASSIGN_VX_MEM_BUS_IF_X(dst, src, TD, TS) \ + assign dst.req_valid = src.req_valid; \ + assign dst.req_data.rw = src.req_data.rw; \ + assign dst.req_data.byteen = src.req_data.byteen; \ + assign dst.req_data.addr = src.req_data.addr; \ + assign dst.req_data.data = src.req_data.data; \ + if (TD != TS) \ + assign dst.req_data.tag = {src.req_data.tag, {(TD-TS){1'b0}}}; \ + else \ + assign dst.req_data.tag = src.req_data.tag; \ + assign src.req_ready = dst.req_ready; \ + assign src.rsp_valid = dst.rsp_valid; \ + assign src.rsp_data.data = dst.rsp_data.data; \ + assign src.rsp_data.tag = dst.rsp_data.tag[TD-1 -: TS]; \ + assign dst.rsp_ready = src.rsp_ready + +`define BUFFER_DCR_BUS_IF(dst, src, enable) \ + logic [(1 + `VX_DCR_ADDR_WIDTH + `VX_DCR_DATA_WIDTH)-1:0] __``dst; \ + if (enable) begin \ + always @(posedge clk) begin \ + __``dst <= {src.write_valid, src.write_addr, src.write_data}; \ + end \ + end else begin \ + assign __``dst = {src.write_valid, src.write_addr, src.write_data}; \ + end \ + VX_dcr_bus_if dst(); \ + assign {dst.write_valid, dst.write_addr, dst.write_data} = __``dst + +`define PERF_REDUCE(dst, src, field, width, count) \ + wire [count-1:0][width-1:0] __reduce_add_i_``src``field; \ + wire [width-1:0] __reduce_add_o_``dst``field; \ + reg [width-1:0] __reduce_add_r_``dst``field; \ + for (genvar __i = 0; __i < count; ++__i) begin \ + assign __reduce_add_i_``src``field[__i] = ``src[__i].``field; \ + end \ + VX_reduce #(.DATAW_IN(width), .N(count), .OP("+")) __reduce_add_``dst``field ( \ + __reduce_add_i_``src``field, \ + __reduce_add_o_``dst``field \ + ); \ + always @(posedge clk) begin \ + if (reset) begin \ + __reduce_add_r_``dst``field <= '0; \ + end else begin \ + __reduce_add_r_``dst``field <= __reduce_add_o_``dst``field; \ + end \ + end \ + assign ``dst.``field = __reduce_add_r_``dst``field + +`define PERF_CACHE_ADD(dst, src, count) \ + `PERF_REDUCE (dst, src, reads, `PERF_CTR_BITS, count); \ + `PERF_REDUCE (dst, src, writes, `PERF_CTR_BITS, count); \ + `PERF_REDUCE (dst, src, read_misses, `PERF_CTR_BITS, count); \ + `PERF_REDUCE (dst, src, write_misses, `PERF_CTR_BITS, count); \ + `PERF_REDUCE (dst, src, bank_stalls, `PERF_CTR_BITS, count); \ + `PERF_REDUCE (dst, src, mshr_stalls, `PERF_CTR_BITS, count); \ + `PERF_REDUCE (dst, src, mem_stalls, `PERF_CTR_BITS, count); \ + `PERF_REDUCE (dst, src, crsp_stalls, `PERF_CTR_BITS, count) + +`define ASSIGN_BLOCKED_WID(dst, src, block_idx, block_size) \ + if (block_size != 1) begin \ + if (block_size != `NUM_WARPS) begin \ + assign dst = {src[`NW_WIDTH-1:`CLOG2(block_size)], `CLOG2(block_size)'(block_idx)}; \ + end else begin \ + assign dst = `NW_WIDTH'(block_idx); \ + end \ + end else begin \ + assign dst = src; \ + end + +`define TO_DISPATCH_DATA(data, tid) \ + {data.uuid, data.wis, data.tmask, data.op_type, data.op_mod, data.wb, data.use_PC, data.use_imm, data.PC, data.imm, data.rd, tid, data.rs1_data, data.rs2_data, data.rs3_data} + +/////////////////////////////////////////////////////////////////////////////// + +`endif // VX_DEFINE_VH diff --git a/hw/rtl/VX_dispatch.sv b/hw/rtl/VX_dispatch.sv deleted file mode 100644 index 9b8b88c8..00000000 --- a/hw/rtl/VX_dispatch.sv +++ /dev/null @@ -1,159 +0,0 @@ -`include "VX_define.vh" - -module VX_dispatch ( - input wire clk, - input wire reset, - - // inputs - VX_ibuffer_if.slave ibuffer_if, - VX_gpr_rsp_if.slave gpr_rsp_if, - - // outputs - VX_alu_req_if.master alu_req_if, - VX_lsu_req_if.master lsu_req_if, - VX_csr_req_if.master csr_req_if, -`ifdef EXT_F_ENABLE - VX_fpu_req_if.master fpu_req_if, -`endif - VX_gpu_req_if.master gpu_req_if -); - wire [`NT_BITS-1:0] tid; - wire alu_req_ready; - wire lsu_req_ready; - wire csr_req_ready; -`ifdef EXT_F_ENABLE - wire fpu_req_ready; -`endif - wire gpu_req_ready; - - VX_lzc #( - .N (`NUM_THREADS) - ) tid_select ( - .in_i (ibuffer_if.tmask), - .cnt_o (tid), - `UNUSED_PIN (valid_o) - ); - - wire [31:0] next_PC = ibuffer_if.PC + 4; - - // ALU unit - - wire alu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_ALU); - wire [`INST_ALU_BITS-1:0] alu_op_type = `INST_ALU_BITS'(ibuffer_if.op_type); - - VX_skid_buffer #( - .DATAW (`UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + 32 + `INST_ALU_BITS + `INST_MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), - .OUT_REG (1) - ) alu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (alu_req_valid), - .ready_in (alu_req_ready), - .data_in ({ibuffer_if.uuid, ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, alu_op_type, ibuffer_if.op_mod, ibuffer_if.imm, ibuffer_if.use_PC, ibuffer_if.use_imm, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({alu_req_if.uuid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), - .valid_out (alu_req_if.valid), - .ready_out (alu_req_if.ready) - ); - - // lsu unit - - wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU); - wire [`INST_LSU_BITS-1:0] lsu_op_type = `INST_LSU_BITS'(ibuffer_if.op_type); - wire lsu_is_fence = `INST_LSU_IS_FENCE(ibuffer_if.op_mod); - wire lsu_is_prefetch = `INST_LSU_IS_PREFETCH(ibuffer_if.op_mod); - - VX_skid_buffer #( - .DATAW (`UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `INST_LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32) + 1), - .OUT_REG (1) - ) lsu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (lsu_req_valid), - .ready_in (lsu_req_ready), - .data_in ({ibuffer_if.uuid, ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, lsu_op_type, lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, lsu_is_prefetch}), - .data_out ({lsu_req_if.uuid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data, lsu_req_if.is_prefetch}), - .valid_out (lsu_req_if.valid), - .ready_out (lsu_req_if.ready) - ); - - // csr unit - - wire csr_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_CSR); - wire [`INST_CSR_BITS-1:0] csr_op_type = `INST_CSR_BITS'(ibuffer_if.op_type); - wire [`CSR_ADDR_BITS-1:0] csr_addr = ibuffer_if.imm[`CSR_ADDR_BITS-1:0]; - wire [`NRI_BITS-1:0] csr_imm = ibuffer_if.imm[`CSR_ADDR_BITS +: `NRI_BITS]; - wire [31:0] csr_rs1_data = gpr_rsp_if.rs1_data[tid]; - - VX_skid_buffer #( - .DATAW (`UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `INST_CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NRI_BITS + 32), - .OUT_REG (1) - ) csr_buffer ( - .clk (clk), - .reset (reset), - .valid_in (csr_req_valid), - .ready_in (csr_req_ready), - .data_in ({ibuffer_if.uuid, ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, csr_op_type, csr_addr, ibuffer_if.rd, ibuffer_if.wb, ibuffer_if.use_imm, csr_imm, csr_rs1_data}), - .data_out ({csr_req_if.uuid, csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.imm, csr_req_if.rs1_data}), - .valid_out (csr_req_if.valid), - .ready_out (csr_req_if.ready) - ); - - // fpu unit - -`ifdef EXT_F_ENABLE - wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU); - wire [`INST_FPU_BITS-1:0] fpu_op_type = `INST_FPU_BITS'(ibuffer_if.op_type); - - VX_skid_buffer #( - .DATAW (`UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `INST_FPU_BITS + `INST_MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), - .OUT_REG (1) - ) fpu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (fpu_req_valid), - .ready_in (fpu_req_ready), - .data_in ({ibuffer_if.uuid, ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, fpu_op_type, ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), - .data_out ({fpu_req_if.uuid, fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), - .valid_out (fpu_req_if.valid), - .ready_out (fpu_req_if.ready) - ); -`else - `UNUSED_VAR (gpr_rsp_if.rs3_data) -`endif - - // gpu unit - - wire gpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_GPU); - wire [`INST_GPU_BITS-1:0] gpu_op_type = `INST_GPU_BITS'(ibuffer_if.op_type); - - VX_skid_buffer #( - .DATAW (`UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + 32 + `INST_GPU_BITS + `INST_MOD_BITS + `NR_BITS + 1 + `NT_BITS + (3 * `NUM_THREADS * 32)), - .OUT_REG (1) - ) gpu_buffer ( - .clk (clk), - .reset (reset), - .valid_in (gpu_req_valid), - .ready_in (gpu_req_ready), - .data_in ({ibuffer_if.uuid, ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, gpu_op_type, ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), - .data_out ({gpu_req_if.uuid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.op_mod, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.tid, gpu_req_if.rs1_data, gpu_req_if.rs2_data, gpu_req_if.rs3_data}), - .valid_out (gpu_req_if.valid), - .ready_out (gpu_req_if.ready) - ); - - // can take next request? - reg ready_r; - always @(*) begin - case (ibuffer_if.ex_type) - `EX_ALU: ready_r = alu_req_ready; - `EX_LSU: ready_r = lsu_req_ready; - `EX_CSR: ready_r = csr_req_ready; - `ifdef EXT_F_ENABLE - `EX_FPU: ready_r = fpu_req_ready; - `endif - `EX_GPU: ready_r = gpu_req_ready; - default: ready_r = 1'b1; // ignore NOPs - endcase - end - assign ibuffer_if.ready = ready_r; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_execute.sv b/hw/rtl/VX_execute.sv deleted file mode 100644 index 3549465a..00000000 --- a/hw/rtl/VX_execute.sv +++ /dev/null @@ -1,237 +0,0 @@ -`include "VX_define.vh" - -module VX_execute #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_execute - - input wire clk, - input wire reset, - - // Dcache interface - VX_dcache_req_if.master dcache_req_if, - VX_dcache_rsp_if.slave dcache_rsp_if, - - // commit interface - VX_cmt_to_csr_if.slave cmt_to_csr_if, - - // fetch interface - VX_fetch_to_csr_if.slave fetch_to_csr_if, - -`ifdef PERF_ENABLE - VX_perf_memsys_if.slave perf_memsys_if, - VX_perf_pipeline_if.slave perf_pipeline_if, - `endif - - // inputs - VX_alu_req_if.slave alu_req_if, - VX_lsu_req_if.slave lsu_req_if, - VX_csr_req_if.slave csr_req_if, -`ifdef EXT_F_ENABLE - VX_fpu_req_if.slave fpu_req_if, -`endif - VX_gpu_req_if.slave gpu_req_if, - - // outputs - VX_branch_ctl_if.master branch_ctl_if, - VX_warp_ctl_if.master warp_ctl_if, - VX_commit_if.master alu_commit_if, - VX_commit_if.master ld_commit_if, - VX_commit_if.master st_commit_if, - VX_commit_if.master csr_commit_if, -`ifdef EXT_F_ENABLE - VX_commit_if.master fpu_commit_if, -`endif - VX_commit_if.master gpu_commit_if, - - input wire busy -); - -`ifdef EXT_TEX_ENABLE - - VX_dcache_req_if #( - .NUM_REQS (`NUM_THREADS), - .WORD_SIZE (4), - .TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS) - ) lsu_dcache_req_if(); - - VX_dcache_rsp_if #( - .NUM_REQS (`NUM_THREADS), - .WORD_SIZE (4), - .TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS) - ) lsu_dcache_rsp_if(); - - VX_dcache_req_if #( - .NUM_REQS (`NUM_THREADS), - .WORD_SIZE (4), - .TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS) - ) tex_dcache_req_if(); - - VX_dcache_rsp_if #( - .NUM_REQS (`NUM_THREADS), - .WORD_SIZE (4), - .TAG_WIDTH (`LSU_TEX_DCACHE_TAG_BITS) - ) tex_dcache_rsp_if(); - - VX_tex_csr_if tex_csr_if(); - -`ifdef PERF_ENABLE - VX_perf_tex_if perf_tex_if(); -`endif - - VX_cache_arb #( - .NUM_REQS (2), - .LANES (`NUM_THREADS), - .DATA_SIZE (4), - .TAG_IN_WIDTH (`LSU_TEX_DCACHE_TAG_BITS), - .TAG_SEL_IDX (`NC_TAG_BIT + `SM_ENABLE) - ) tex_lsu_arb ( - .clk (clk), - .reset (reset), - - // Tex/LSU request - .req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}), - .req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}), - .req_byteen_in ({tex_dcache_req_if.byteen, lsu_dcache_req_if.byteen}), - .req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}), - .req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}), - .req_tag_in ({tex_dcache_req_if.tag, lsu_dcache_req_if.tag}), - .req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}), - - // Dcache request - .req_valid_out (dcache_req_if.valid), - .req_rw_out (dcache_req_if.rw), - .req_byteen_out (dcache_req_if.byteen), - .req_addr_out (dcache_req_if.addr), - .req_data_out (dcache_req_if.data), - .req_tag_out (dcache_req_if.tag), - .req_ready_out (dcache_req_if.ready), - - // Dcache response - .rsp_valid_in (dcache_rsp_if.valid), - .rsp_tmask_in (dcache_rsp_if.tmask), - .rsp_tag_in (dcache_rsp_if.tag), - .rsp_data_in (dcache_rsp_if.data), - .rsp_ready_in (dcache_rsp_if.ready), - - // Tex/LSU response - .rsp_valid_out ({tex_dcache_rsp_if.valid, lsu_dcache_rsp_if.valid}), - .rsp_tmask_out ({tex_dcache_rsp_if.tmask, lsu_dcache_rsp_if.tmask}), - .rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}), - .rsp_tag_out ({tex_dcache_rsp_if.tag, lsu_dcache_rsp_if.tag}), - .rsp_ready_out ({tex_dcache_rsp_if.ready, lsu_dcache_rsp_if.ready}) - ); - -`endif - -`ifdef EXT_F_ENABLE - wire [`NUM_WARPS-1:0] csr_pending; - wire [`NUM_WARPS-1:0] fpu_pending; - VX_fpu_to_csr_if fpu_to_csr_if(); -`endif - - `RESET_RELAY (alu_reset); - `RESET_RELAY (lsu_reset); - `RESET_RELAY (csr_reset); - `RESET_RELAY (gpu_reset); - - VX_alu_unit #( - .CORE_ID(CORE_ID) - ) alu_unit ( - .clk (clk), - .reset (alu_reset), - .alu_req_if (alu_req_if), - .branch_ctl_if (branch_ctl_if), - .alu_commit_if (alu_commit_if) - ); - - VX_lsu_unit #( - .CORE_ID(CORE_ID) - ) lsu_unit ( - `SCOPE_BIND_VX_execute_lsu_unit - .clk (clk), - .reset (lsu_reset), - `ifdef EXT_TEX_ENABLE - .dcache_req_if (lsu_dcache_req_if), - .dcache_rsp_if (lsu_dcache_rsp_if), - `else - .dcache_req_if (dcache_req_if), - .dcache_rsp_if (dcache_rsp_if), - `endif - .lsu_req_if (lsu_req_if), - .ld_commit_if (ld_commit_if), - .st_commit_if (st_commit_if) - ); - - VX_csr_unit #( - .CORE_ID(CORE_ID) - ) csr_unit ( - .clk (clk), - .reset (csr_reset), - `ifdef PERF_ENABLE - `ifdef EXT_TEX_ENABLE - .perf_tex_if (perf_tex_if), - `endif - .perf_memsys_if (perf_memsys_if), - .perf_pipeline_if(perf_pipeline_if), - `endif - .cmt_to_csr_if (cmt_to_csr_if), - .fetch_to_csr_if(fetch_to_csr_if), - .csr_req_if (csr_req_if), - .csr_commit_if (csr_commit_if), - `ifdef EXT_F_ENABLE - .fpu_to_csr_if (fpu_to_csr_if), - .fpu_pending (fpu_pending), - .pending (csr_pending), - `else - `UNUSED_PIN (pending), - `endif - `ifdef EXT_TEX_ENABLE - .tex_csr_if (tex_csr_if), - `endif - .busy (busy) - ); - -`ifdef EXT_F_ENABLE - `RESET_RELAY (fpu_reset); - - VX_fpu_unit #( - .CORE_ID(CORE_ID) - ) fpu_unit ( - .clk (clk), - .reset (fpu_reset), - .fpu_req_if (fpu_req_if), - .fpu_to_csr_if (fpu_to_csr_if), - .fpu_commit_if (fpu_commit_if), - .csr_pending (csr_pending), - .pending (fpu_pending) - ); -`endif - - VX_gpu_unit #( - .CORE_ID(CORE_ID) - ) gpu_unit ( - `SCOPE_BIND_VX_execute_gpu_unit - .clk (clk), - .reset (gpu_reset), - .gpu_req_if (gpu_req_if), - `ifdef EXT_TEX_ENABLE - `ifdef PERF_ENABLE - .perf_tex_if (perf_tex_if), - `endif - .tex_csr_if (tex_csr_if), - .dcache_req_if (tex_dcache_req_if), - .dcache_rsp_if (tex_dcache_rsp_if), - `endif - .warp_ctl_if (warp_ctl_if), - .gpu_commit_if (gpu_commit_if) - ); - - // special workaround to get RISC-V tests Pass/Fail status - wire ebreak /* verilator public */; - assign ebreak = alu_req_if.valid && alu_req_if.ready - && `INST_ALU_IS_BR(alu_req_if.op_mod) - && (`INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_EBREAK - || `INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_ECALL); - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_fetch.sv b/hw/rtl/VX_fetch.sv deleted file mode 100644 index 7db7faab..00000000 --- a/hw/rtl/VX_fetch.sv +++ /dev/null @@ -1,68 +0,0 @@ -`include "VX_define.vh" - -module VX_fetch #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_fetch - - input wire clk, - input wire reset, - - // Icache interface - VX_icache_req_if.master icache_req_if, - VX_icache_rsp_if.slave icache_rsp_if, - - // inputs - VX_wstall_if.slave wstall_if, - VX_join_if.slave join_if, - VX_branch_ctl_if.slave branch_ctl_if, - VX_warp_ctl_if.slave warp_ctl_if, - - // outputs - VX_ifetch_rsp_if.master ifetch_rsp_if, - - // csr interface - VX_fetch_to_csr_if.master fetch_to_csr_if, - - // busy status - output wire busy -); - - VX_ifetch_req_if ifetch_req_if(); - - VX_warp_sched #( - .CORE_ID(CORE_ID) - ) warp_sched ( - `SCOPE_BIND_VX_fetch_warp_sched - - .clk (clk), - .reset (reset), - - .warp_ctl_if (warp_ctl_if), - .wstall_if (wstall_if), - .join_if (join_if), - .branch_ctl_if (branch_ctl_if), - - .ifetch_req_if (ifetch_req_if), - - .fetch_to_csr_if (fetch_to_csr_if), - - .busy (busy) - ); - - VX_icache_stage #( - .CORE_ID(CORE_ID) - ) icache_stage ( - `SCOPE_BIND_VX_fetch_icache_stage - - .clk (clk), - .reset (reset), - - .icache_rsp_if (icache_rsp_if), - .icache_req_if (icache_req_if), - - .ifetch_req_if (ifetch_req_if), - .ifetch_rsp_if (ifetch_rsp_if) - ); - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_fpu_unit.sv b/hw/rtl/VX_fpu_unit.sv deleted file mode 100644 index 342bf36d..00000000 --- a/hw/rtl/VX_fpu_unit.sv +++ /dev/null @@ -1,219 +0,0 @@ -`include "VX_define.vh" - -module VX_fpu_unit #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - VX_fpu_req_if.slave fpu_req_if, - VX_fpu_to_csr_if.master fpu_to_csr_if, - VX_commit_if.master fpu_commit_if, - - input wire[`NUM_WARPS-1:0] csr_pending, - output wire[`NUM_WARPS-1:0] pending -); - import fpu_types::*; - - `UNUSED_PARAM (CORE_ID) - localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE); - - wire ready_in; - wire valid_out; - wire ready_out; - - wire [`UUID_BITS-1:0] rsp_uuid; - wire [`NW_BITS-1:0] rsp_wid; - wire [`NUM_THREADS-1:0] rsp_tmask; - wire [31:0] rsp_PC; - wire [`NR_BITS-1:0] rsp_rd; - wire rsp_wb; - - wire has_fflags; - fflags_t [`NUM_THREADS-1:0] fflags; - wire [`NUM_THREADS-1:0][31:0] result; - - wire [FPUQ_BITS-1:0] tag_in, tag_out; - wire fpuq_full; - - wire fpuq_push = fpu_req_if.valid && fpu_req_if.ready; - wire fpuq_pop = valid_out && ready_out; - - VX_index_buffer #( - .DATAW (`UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1), - .SIZE (`FPUQ_SIZE) - ) req_metadata ( - .clk (clk), - .reset (reset), - .acquire_slot (fpuq_push), - .write_addr (tag_in), - .read_addr (tag_out), - .release_addr (tag_out), - .write_data ({fpu_req_if.uuid, fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.rd, fpu_req_if.wb}), - .read_data ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}), - .release_slot (fpuq_pop), - .full (fpuq_full), - `UNUSED_PIN (empty) - ); - - // can accept new request? - assign fpu_req_if.ready = ready_in && ~fpuq_full && !csr_pending[fpu_req_if.wid]; - - wire valid_in = fpu_req_if.valid && ~fpuq_full && !csr_pending[fpu_req_if.wid]; - - // resolve dynamic FRM from CSR - assign fpu_to_csr_if.read_wid = fpu_req_if.wid; - wire [`INST_FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `INST_FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod; - -`ifdef FPU_DPI - - VX_fpu_dpi #( - .TAGW (FPUQ_BITS) - ) fpu_dpi ( - .clk (clk), - .reset (reset), - - .valid_in (valid_in), - .ready_in (ready_in), - - .tag_in (tag_in), - - .op_type (fpu_req_if.op_type), - .frm (fpu_frm), - - .dataa (fpu_req_if.rs1_data), - .datab (fpu_req_if.rs2_data), - .datac (fpu_req_if.rs3_data), - .result (result), - - .has_fflags (has_fflags), - .fflags (fflags), - - .tag_out (tag_out), - - .ready_out (ready_out), - .valid_out (valid_out) - ); - -`elsif FPU_FPNEW - - VX_fpu_fpnew #( - .FMULADD (1), - .FDIVSQRT (1), - .FNONCOMP (1), - .FCONV (1), - .TAGW (FPUQ_BITS) - ) fpu_fpnew ( - .clk (clk), - .reset (reset), - - .valid_in (valid_in), - .ready_in (ready_in), - - .tag_in (tag_in), - - .op_type (fpu_req_if.op_type), - .frm (fpu_frm), - - .dataa (fpu_req_if.rs1_data), - .datab (fpu_req_if.rs2_data), - .datac (fpu_req_if.rs3_data), - .result (result), - - .has_fflags (has_fflags), - .fflags (fflags), - - .tag_out (tag_out), - - .ready_out (ready_out), - .valid_out (valid_out) - ); - -`else - - VX_fpu_fpga #( - .TAGW (FPUQ_BITS) - ) fpu_fpga ( - .clk (clk), - .reset (reset), - - .valid_in (valid_in), - .ready_in (ready_in), - - .tag_in (tag_in), - - .op_type (fpu_req_if.op_type), - .frm (fpu_frm), - - .dataa (fpu_req_if.rs1_data), - .datab (fpu_req_if.rs2_data), - .datac (fpu_req_if.rs3_data), - .result (result), - - .has_fflags (has_fflags), - .fflags (fflags), - - .tag_out (tag_out), - - .ready_out (ready_out), - .valid_out (valid_out) - ); - -`endif - - reg has_fflags_r; - fflags_t fflags_r; - - fflags_t rsp_fflags; - always @(*) begin - rsp_fflags = '0; - for (integer i = 0; i < `NUM_THREADS; i++) begin - if (rsp_tmask[i]) begin - rsp_fflags.NX |= fflags[i].NX; - rsp_fflags.UF |= fflags[i].UF; - rsp_fflags.OF |= fflags[i].OF; - rsp_fflags.DZ |= fflags[i].DZ; - rsp_fflags.NV |= fflags[i].NV; - end - end - end - - wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid; - - VX_pipe_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFLAGS_BITS), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_out), - .data_in ({valid_out, rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, rsp_fflags}), - .data_out ({fpu_commit_if.valid, fpu_commit_if.uuid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, has_fflags_r, fflags_r}) - ); - - assign fpu_commit_if.eop = 1'b1; - - assign ready_out = ~stall_out; - - // CSR fflags Update - assign fpu_to_csr_if.write_enable = fpu_commit_if.valid && fpu_commit_if.ready && has_fflags_r; - assign fpu_to_csr_if.write_wid = fpu_commit_if.wid; - assign fpu_to_csr_if.write_fflags = fflags_r; - - // pending request - reg [`NUM_WARPS-1:0] pending_r; - always @(posedge clk) begin - if (reset) begin - pending_r <= 0; - end else begin - if (fpu_commit_if.valid && fpu_commit_if.ready) begin - pending_r[fpu_commit_if.wid] <= 0; - end - if (fpu_req_if.valid && fpu_req_if.ready) begin - pending_r[fpu_req_if.wid] <= 1; - end - end - end - assign pending = pending_r; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpr_stage.sv b/hw/rtl/VX_gpr_stage.sv deleted file mode 100644 index 05fc6248..00000000 --- a/hw/rtl/VX_gpr_stage.sv +++ /dev/null @@ -1,91 +0,0 @@ -`include "VX_define.vh" - -module VX_gpr_stage #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // inputs - VX_writeback_if.slave writeback_if, - VX_gpr_req_if.slave gpr_req_if, - - // outputs - VX_gpr_rsp_if.master gpr_rsp_if -); - - `UNUSED_PARAM (CORE_ID) - `UNUSED_VAR (reset) - - localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS; - - // ensure r0 never gets written, which can happen before the reset - wire write_enable = writeback_if.valid && (writeback_if.rd != 0); - - wire [`NUM_THREADS-1:0] wren; - for (genvar i = 0; i < `NUM_THREADS; ++i) begin - assign wren[i] = write_enable && writeback_if.tmask[i]; - end - - wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2; - assign waddr = {writeback_if.wid, writeback_if.rd}; - assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1}; - assign raddr2 = {gpr_req_if.wid, gpr_req_if.rs2}; - - for (genvar i = 0; i < `NUM_THREADS; ++i) begin - VX_dp_ram #( - .DATAW (32), - .SIZE (RAM_SIZE), - .INIT_ENABLE (1), - .INIT_VALUE (0) - ) dp_ram1 ( - .clk (clk), - .wren (wren[i]), - .waddr (waddr), - .wdata (writeback_if.data[i]), - .raddr (raddr1), - .rdata (gpr_rsp_if.rs1_data[i]) - ); - - VX_dp_ram #( - .DATAW (32), - .SIZE (RAM_SIZE), - .INIT_ENABLE (1), - .INIT_VALUE (0) - ) dp_ram2 ( - .clk (clk), - .wren (wren[i]), - .waddr (waddr), - .wdata (writeback_if.data[i]), - .raddr (raddr2), - .rdata (gpr_rsp_if.rs2_data[i]) - ); - end - -`ifdef EXT_F_ENABLE - wire [$clog2(RAM_SIZE)-1:0] raddr3; - assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3}; - - for (genvar i = 0; i < `NUM_THREADS; ++i) begin - VX_dp_ram #( - .DATAW (32), - .SIZE (RAM_SIZE), - .INIT_ENABLE (1), - .INIT_VALUE (0) - ) dp_ram3 ( - .clk (clk), - .wren (wren[i]), - .waddr (waddr), - .wdata (writeback_if.data[i]), - .raddr (raddr3), - .rdata (gpr_rsp_if.rs3_data[i]) - ); - end -`else - `UNUSED_VAR (gpr_req_if.rs3) - assign gpr_rsp_if.rs3_data = 'x; -`endif - - assign writeback_if.ready = 1'b1; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpu_pkg.sv b/hw/rtl/VX_gpu_pkg.sv new file mode 100644 index 00000000..a1b61fc7 --- /dev/null +++ b/hw/rtl/VX_gpu_pkg.sv @@ -0,0 +1,218 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_GPU_PKG_VH +`define VX_GPU_PKG_VH + +`include "VX_define.vh" + +package VX_gpu_pkg; + + typedef struct packed { + logic valid; + logic [`NUM_THREADS-1:0] tmask; + } tmc_t; + + typedef struct packed { + logic valid; + logic [`NUM_WARPS-1:0] wmask; + logic [`XLEN-1:0] pc; + } wspawn_t; + + typedef struct packed { + logic valid; + logic is_dvg; + logic [`NUM_THREADS-1:0] then_tmask; + logic [`NUM_THREADS-1:0] else_tmask; + logic [`XLEN-1:0] next_pc; + } split_t; + + typedef struct packed { + logic valid; + logic is_dvg; + } join_t; + + typedef struct packed { + logic valid; + logic [`NB_WIDTH-1:0] id; + logic is_global; + `ifdef GBAR_ENABLE + logic [`MAX(`NW_WIDTH, `NC_WIDTH)-1:0] size_m1; + `else + logic [`NW_WIDTH-1:0] size_m1; + `endif + } barrier_t; + + typedef struct packed { + logic [`XLEN-1:0] startup_addr; + logic [7:0] mpm_class; + } base_dcrs_t; + + /* verilator lint_off UNUSED */ + + ////////////////////////// Icache Parameters ////////////////////////////// + + // Word size in bytes + localparam ICACHE_WORD_SIZE = 4; + localparam ICACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(ICACHE_WORD_SIZE)); + + // Block size in bytes + localparam ICACHE_LINE_SIZE = `L1_LINE_SIZE; + + // Core request tag Id bits + localparam ICACHE_TAG_ID_BITS = `NW_WIDTH; + + // Core request tag bits + localparam ICACHE_TAG_WIDTH = (`UUID_WIDTH + ICACHE_TAG_ID_BITS); + localparam ICACHE_ARB_TAG_WIDTH = (ICACHE_TAG_WIDTH + `CLOG2(`SOCKET_SIZE)); + + // Memory request data bits + localparam ICACHE_MEM_DATA_WIDTH = (ICACHE_LINE_SIZE * 8); + + // Memory request tag bits + `ifdef ICACHE_ENABLE + localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_MEM_TAG_WIDTH(`ICACHE_MSHR_SIZE, 1, `NUM_ICACHES); + `else + localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(1, ICACHE_LINE_SIZE, ICACHE_WORD_SIZE, ICACHE_ARB_TAG_WIDTH, `NUM_SOCKETS, `NUM_ICACHES); + `endif + + ////////////////////////// Dcache Parameters ////////////////////////////// + + // Word size in bytes + localparam DCACHE_WORD_SIZE = (`XLEN / 8); + localparam DCACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(DCACHE_WORD_SIZE)); + + // Block size in bytes + localparam DCACHE_LINE_SIZE = `L1_LINE_SIZE; + + // Input request size + localparam DCACHE_NUM_REQS = `MAX(`DCACHE_NUM_BANKS, `SMEM_NUM_BANKS); + + // Memory request size + localparam LSU_MEM_REQS = `NUM_LSU_LANES; + + // Batch select bits + localparam DCACHE_NUM_BATCHES = ((LSU_MEM_REQS + DCACHE_NUM_REQS - 1) / DCACHE_NUM_REQS); + localparam DCACHE_BATCH_SEL_BITS = `CLOG2(DCACHE_NUM_BATCHES); + + // Core request tag Id bits + localparam LSUQ_TAG_BITS = (`CLOG2(`LSUQ_SIZE) + DCACHE_BATCH_SEL_BITS); + localparam DCACHE_TAG_ID_BITS = (LSUQ_TAG_BITS + `CACHE_ADDR_TYPE_BITS); + + // Core request tag bits + localparam DCACHE_TAG_WIDTH = (`UUID_WIDTH + DCACHE_TAG_ID_BITS); + localparam DCACHE_NOSM_TAG_WIDTH = (DCACHE_TAG_WIDTH - `SM_ENABLED); + localparam DCACHE_ARB_TAG_WIDTH = (DCACHE_NOSM_TAG_WIDTH + `CLOG2(`SOCKET_SIZE)); + + // Memory request data bits + localparam DCACHE_MEM_DATA_WIDTH = (DCACHE_LINE_SIZE * 8); + + // Memory request tag bits + `ifdef DCACHE_ENABLE + localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_MEM_TAG_WIDTH(`DCACHE_MSHR_SIZE, `DCACHE_NUM_BANKS, DCACHE_NUM_REQS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_ARB_TAG_WIDTH, `NUM_SOCKETS, `NUM_DCACHES); + `else + localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_BYPASS_TAG_WIDTH(DCACHE_NUM_REQS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_ARB_TAG_WIDTH, `NUM_SOCKETS, `NUM_DCACHES); + `endif + + /////////////////////////////// L1 Parameters ///////////////////////////// + + localparam L1_MEM_TAG_WIDTH = `MAX(ICACHE_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH); + + localparam NUM_L1_OUTPUTS = 2; + + /////////////////////////////// L2 Parameters ///////////////////////////// + + // Word size in bytes + localparam L2_WORD_SIZE = `L1_LINE_SIZE; + + // Input request size + localparam L2_NUM_REQS = NUM_L1_OUTPUTS; + + // Core request tag bits + localparam L2_TAG_WIDTH = L1_MEM_TAG_WIDTH; + + // Memory request data bits + localparam L2_MEM_DATA_WIDTH = (`L2_LINE_SIZE * 8); + + // Memory request tag bits + `ifdef L2_ENABLE + localparam L2_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L2_MSHR_SIZE, `L2_NUM_BANKS, L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH); + `else + localparam L2_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH); + `endif + + /////////////////////////////// L3 Parameters ///////////////////////////// + + // Word size in bytes + localparam L3_WORD_SIZE = `L2_LINE_SIZE; + + // Input request size + localparam L3_NUM_REQS = `NUM_CLUSTERS; + + // Core request tag bits + localparam L3_TAG_WIDTH = L2_MEM_TAG_WIDTH; + + // Memory request data bits + localparam L3_MEM_DATA_WIDTH = (`L3_LINE_SIZE * 8); + + // Memory request tag bits + `ifdef L3_ENABLE + localparam L3_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L3_MSHR_SIZE, `L3_NUM_BANKS, L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH); + `else + localparam L3_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH); + `endif + + /* verilator lint_on UNUSED */ + + /////////////////////////////// Issue parameters ////////////////////////// + + localparam ISSUE_IDX_W = `LOG2UP(`ISSUE_WIDTH); + localparam ISSUE_RATIO = `NUM_WARPS / `ISSUE_WIDTH; + localparam ISSUE_WIS_W = `LOG2UP(ISSUE_RATIO); + localparam ISSUE_ADDRW = `LOG2UP(`NUM_REGS * (ISSUE_RATIO)); + +`IGNORE_UNUSED_BEGIN + function logic [ISSUE_IDX_W-1:0] wid_to_isw( + input logic [`NW_WIDTH-1:0] wid + ); + if (`ISSUE_WIDTH > 1) begin + wid_to_isw = ISSUE_IDX_W'(wid); + end else begin + wid_to_isw = 0; + end + endfunction + `IGNORE_UNUSED_END + + function logic [`NW_WIDTH-1:0] wis_to_wid( + input logic [ISSUE_WIS_W-1:0] wis, + input logic [ISSUE_IDX_W-1:0] isw + ); + wis_to_wid = `NW_WIDTH'({wis, isw} >> (ISSUE_IDX_W-`CLOG2(`ISSUE_WIDTH))); + endfunction + + function logic [ISSUE_WIS_W-1:0] wid_to_wis( + input logic [`NW_WIDTH-1:0] wid + ); + wid_to_wis = ISSUE_WIS_W'(wid >> `CLOG2(`ISSUE_WIDTH)); + endfunction + + function logic [ISSUE_ADDRW-1:0] wis_to_addr( + input logic [`NR_BITS-1:0] rid, + input logic [ISSUE_WIS_W-1:0] wis + ); + wis_to_addr = ISSUE_ADDRW'({rid, wis} >> (ISSUE_WIS_W-`CLOG2(ISSUE_RATIO))); + endfunction + +endpackage + +`endif // VX_GPU_PKG_VH diff --git a/hw/rtl/VX_gpu_types.vh b/hw/rtl/VX_gpu_types.vh deleted file mode 100644 index 857f2efc..00000000 --- a/hw/rtl/VX_gpu_types.vh +++ /dev/null @@ -1,43 +0,0 @@ -`ifndef VX_GPU_TYPES -`define VX_GPU_TYPES - -`include "VX_define.vh" - -package gpu_types; - -typedef struct packed { - logic valid; - logic [`NUM_THREADS-1:0] tmask; -} gpu_tmc_t; - -`define GPU_TMC_BITS $bits(gpu_types::gpu_tmc_t) - -typedef struct packed { - logic valid; - logic [`NUM_WARPS-1:0] wmask; - logic [31:0] pc; -} gpu_wspawn_t; - -`define GPU_WSPAWN_BITS $bits(gpu_types::gpu_wspawn_t) - -typedef struct packed { - logic valid; - logic diverged; - logic [`NUM_THREADS-1:0] then_tmask; - logic [`NUM_THREADS-1:0] else_tmask; - logic [31:0] pc; -} gpu_split_t; - -`define GPU_SPLIT_BITS $bits(gpu_types::gpu_split_t) - -typedef struct packed { - logic valid; - logic [`NB_BITS-1:0] id; - logic [`NW_BITS-1:0] size_m1; -} gpu_barrier_t; - -`define GPU_BARRIER_BITS $bits(gpu_types::gpu_barrier_t) - -endpackage - -`endif \ No newline at end of file diff --git a/hw/rtl/VX_gpu_unit.sv b/hw/rtl/VX_gpu_unit.sv deleted file mode 100644 index b4047830..00000000 --- a/hw/rtl/VX_gpu_unit.sv +++ /dev/null @@ -1,220 +0,0 @@ -`include "VX_define.vh" - -module VX_gpu_unit #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_gpu_unit - - input wire clk, - input wire reset, - - // Inputs - VX_gpu_req_if.slave gpu_req_if, - -`ifdef EXT_TEX_ENABLE - // PERF -`ifdef PERF_ENABLE - VX_perf_tex_if.master perf_tex_if, -`endif - VX_dcache_req_if.master dcache_req_if, - VX_dcache_rsp_if.slave dcache_rsp_if, - VX_tex_csr_if.slave tex_csr_if, -`endif - - // Outputs - VX_warp_ctl_if.master warp_ctl_if, - VX_commit_if.master gpu_commit_if -); - import gpu_types::*; - - `UNUSED_PARAM (CORE_ID) - - localparam WCTL_DATAW = `GPU_TMC_BITS + `GPU_WSPAWN_BITS + `GPU_SPLIT_BITS + `GPU_BARRIER_BITS; - localparam RSP_DATAW = `MAX(`NUM_THREADS * 32, WCTL_DATAW); - - wire rsp_valid; - wire [`UUID_BITS-1:0] rsp_uuid; - wire [`NW_BITS-1:0] rsp_wid; - wire [`NUM_THREADS-1:0] rsp_tmask; - wire [31:0] rsp_PC; - wire [`NR_BITS-1:0] rsp_rd; - wire rsp_wb; - - wire [RSP_DATAW-1:0] rsp_data, rsp_data_r; - - gpu_tmc_t tmc; - gpu_wspawn_t wspawn; - gpu_barrier_t barrier; - gpu_split_t split; - - wire [WCTL_DATAW-1:0] warp_ctl_data; - wire is_warp_ctl; - - wire stall_in, stall_out; - - wire is_wspawn = (gpu_req_if.op_type == `INST_GPU_WSPAWN); - wire is_tmc = (gpu_req_if.op_type == `INST_GPU_TMC); - wire is_split = (gpu_req_if.op_type == `INST_GPU_SPLIT); - wire is_bar = (gpu_req_if.op_type == `INST_GPU_BAR); - wire is_pred = (gpu_req_if.op_type == `INST_GPU_PRED); - - wire [31:0] rs1_data = gpu_req_if.rs1_data[gpu_req_if.tid]; - wire [31:0] rs2_data = gpu_req_if.rs2_data[gpu_req_if.tid]; - - wire [`NUM_THREADS-1:0] taken_tmask; - wire [`NUM_THREADS-1:0] not_taken_tmask; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire taken = (gpu_req_if.rs1_data[i] != 0); - assign taken_tmask[i] = gpu_req_if.tmask[i] & taken; - assign not_taken_tmask[i] = gpu_req_if.tmask[i] & ~taken; - end - - // tmc - - wire [`NUM_THREADS-1:0] pred_mask = (taken_tmask != 0) ? taken_tmask : gpu_req_if.tmask; - - assign tmc.valid = is_tmc || is_pred; - assign tmc.tmask = is_pred ? pred_mask : rs1_data[`NUM_THREADS-1:0]; - - // wspawn - - wire [31:0] wspawn_pc = rs2_data; - wire [`NUM_WARPS-1:0] wspawn_wmask; - for (genvar i = 0; i < `NUM_WARPS; i++) begin - assign wspawn_wmask[i] = (i < rs1_data); - end - assign wspawn.valid = is_wspawn; - assign wspawn.wmask = wspawn_wmask; - assign wspawn.pc = wspawn_pc; - - // split - - assign split.valid = is_split; - assign split.diverged = (| taken_tmask) && (| not_taken_tmask); - assign split.then_tmask = taken_tmask; - assign split.else_tmask = not_taken_tmask; - assign split.pc = gpu_req_if.next_PC; - - // barrier - - assign barrier.valid = is_bar; - assign barrier.id = rs1_data[`NB_BITS-1:0]; - assign barrier.size_m1 = (`NW_BITS)'(rs2_data - 1); - - // pack warp ctl result - assign warp_ctl_data = {tmc, wspawn, split, barrier}; - - // texture - -`ifdef EXT_TEX_ENABLE - - `UNUSED_VAR (gpu_req_if.op_mod) - - VX_tex_req_if tex_req_if(); - VX_tex_rsp_if tex_rsp_if(); - - wire is_tex = (gpu_req_if.op_type == `INST_GPU_TEX); - - assign tex_req_if.valid = gpu_req_if.valid && is_tex; - assign tex_req_if.uuid = gpu_req_if.uuid; - assign tex_req_if.wid = gpu_req_if.wid; - assign tex_req_if.tmask = gpu_req_if.tmask; - assign tex_req_if.PC = gpu_req_if.PC; - assign tex_req_if.rd = gpu_req_if.rd; - assign tex_req_if.wb = gpu_req_if.wb; - - assign tex_req_if.unit = gpu_req_if.op_mod[`NTEX_BITS-1:0]; - assign tex_req_if.coords[0] = gpu_req_if.rs1_data; - assign tex_req_if.coords[1] = gpu_req_if.rs2_data; - assign tex_req_if.lod = gpu_req_if.rs3_data; - - VX_tex_unit #( - .CORE_ID(CORE_ID) - ) tex_unit ( - .clk (clk), - .reset (reset), - `ifdef PERF_ENABLE - .perf_tex_if (perf_tex_if), - `endif - .tex_req_if (tex_req_if), - .tex_csr_if (tex_csr_if), - .tex_rsp_if (tex_rsp_if), - .dcache_req_if (dcache_req_if), - .dcache_rsp_if (dcache_rsp_if) - ); - - assign tex_rsp_if.ready = !stall_out; - - assign stall_in = (is_tex && ~tex_req_if.ready) - || (~is_tex && (tex_rsp_if.valid || stall_out)); - - assign is_warp_ctl = !(is_tex || tex_rsp_if.valid); - - assign rsp_valid = tex_rsp_if.valid || (gpu_req_if.valid && ~is_tex); - assign rsp_uuid = tex_rsp_if.valid ? tex_rsp_if.uuid : gpu_req_if.uuid; - assign rsp_wid = tex_rsp_if.valid ? tex_rsp_if.wid : gpu_req_if.wid; - assign rsp_tmask = tex_rsp_if.valid ? tex_rsp_if.tmask : gpu_req_if.tmask; - assign rsp_PC = tex_rsp_if.valid ? tex_rsp_if.PC : gpu_req_if.PC; - assign rsp_rd = tex_rsp_if.rd; - assign rsp_wb = tex_rsp_if.valid && tex_rsp_if.wb; - assign rsp_data = tex_rsp_if.valid ? RSP_DATAW'(tex_rsp_if.data) : RSP_DATAW'(warp_ctl_data); - -`else - - `UNUSED_VAR (gpu_req_if.op_mod) - `UNUSED_VAR (gpu_req_if.rs3_data) - `UNUSED_VAR (gpu_req_if.wb) - `UNUSED_VAR (gpu_req_if.rd) - - assign stall_in = stall_out; - assign is_warp_ctl = 1; - - assign rsp_valid = gpu_req_if.valid; - assign rsp_uuid = gpu_req_if.uuid; - assign rsp_wid = gpu_req_if.wid; - assign rsp_tmask = gpu_req_if.tmask; - assign rsp_PC = gpu_req_if.PC; - assign rsp_rd = 0; - assign rsp_wb = 0; - assign rsp_data = RSP_DATAW'(warp_ctl_data); - -`endif - - wire is_warp_ctl_r; - - // output - assign stall_out = ~gpu_commit_if.ready && gpu_commit_if.valid; - - VX_pipe_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + RSP_DATAW + 1), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_out), - .data_in ({rsp_valid, rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data, is_warp_ctl}), - .data_out ({gpu_commit_if.valid, gpu_commit_if.uuid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.rd, gpu_commit_if.wb, rsp_data_r, is_warp_ctl_r}) - ); - - assign gpu_commit_if.data = rsp_data_r[(`NUM_THREADS * 32)-1:0]; - assign gpu_commit_if.eop = 1'b1; - - // warp control reponse - - assign {warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.barrier} = rsp_data_r[WCTL_DATAW-1:0]; - - assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready && is_warp_ctl_r; - assign warp_ctl_if.wid = gpu_commit_if.wid; - - // can accept new request? - assign gpu_req_if.ready = ~stall_in; - - `SCOPE_ASSIGN (gpu_rsp_valid, warp_ctl_if.valid); - `SCOPE_ASSIGN (gpu_rsp_uuid, gpu_commit_if.uuid); - `SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc.valid); - `SCOPE_ASSIGN (gpu_rsp_wspawn, warp_ctl_if.wspawn.valid); - `SCOPE_ASSIGN (gpu_rsp_split, warp_ctl_if.split.valid); - `SCOPE_ASSIGN (gpu_rsp_barrier, warp_ctl_if.barrier.valid); - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_ibuffer.sv b/hw/rtl/VX_ibuffer.sv deleted file mode 100644 index 6231ac5f..00000000 --- a/hw/rtl/VX_ibuffer.sv +++ /dev/null @@ -1,210 +0,0 @@ -`include "VX_define.vh" - -module VX_ibuffer #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // inputs - VX_decode_if.slave decode_if, - - // outputs - VX_ibuffer_if.master ibuffer_if -); - - `UNUSED_PARAM (CORE_ID) - - localparam DATAW = `UUID_BITS + `NUM_THREADS + 32 + `EX_BITS + `INST_OP_BITS + `INST_FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1; - localparam ADDRW = $clog2(`IBUF_SIZE+1); - localparam NWARPSW = $clog2(`NUM_WARPS+1); - - reg [`NUM_WARPS-1:0][ADDRW-1:0] used_r; - reg [`NUM_WARPS-1:0] full_r, empty_r, alm_empty_r; - - wire [`NUM_WARPS-1:0] q_full, q_empty, q_alm_empty; - wire [DATAW-1:0] q_data_in; - wire [`NUM_WARPS-1:0][DATAW-1:0] q_data_prev; - reg [`NUM_WARPS-1:0][DATAW-1:0] q_data_out; - - wire enq_fire = decode_if.valid && decode_if.ready; - wire deq_fire = ibuffer_if.valid && ibuffer_if.ready; - - for (genvar i = 0; i < `NUM_WARPS; ++i) begin - - wire writing = enq_fire && (i == decode_if.wid); - wire reading = deq_fire && (i == ibuffer_if.wid); - - wire going_empty = empty_r[i] || (alm_empty_r[i] && reading); - - VX_elastic_buffer #( - .DATAW (DATAW), - .SIZE (`IBUF_SIZE), - .OUT_REG (1) - ) queue ( - .clk (clk), - .reset (reset), - .valid_in (writing && !going_empty), - .data_in (q_data_in), - .ready_out(reading), - .data_out (q_data_prev[i]), - `UNUSED_PIN (ready_in), - `UNUSED_PIN (valid_out) - ); - - always @(posedge clk) begin - if (reset) begin - used_r[i] <= 0; - full_r[i] <= 0; - empty_r[i] <= 1; - alm_empty_r[i] <= 1; - end else begin - if (writing) begin - if (!reading) begin - empty_r[i] <= 0; - if (used_r[i] == 1) - alm_empty_r[i] <= 0; - if (used_r[i] == ADDRW'(`IBUF_SIZE)) - full_r[i] <= 1; - end - end else if (reading) begin - full_r[i] <= 0; - if (used_r[i] == ADDRW'(1)) - empty_r[i] <= 1; - if (used_r[i] == ADDRW'(2)) - alm_empty_r[i] <= 1; - end - used_r[i] <= used_r[i] + ADDRW'($signed(2'(writing) - 2'(reading))); - end - - if (writing && going_empty) begin - q_data_out[i] <= q_data_in; - end else if (reading) begin - q_data_out[i] <= q_data_prev[i]; - end - end - - assign q_full[i] = full_r[i]; - assign q_empty[i] = empty_r[i]; - assign q_alm_empty[i] = alm_empty_r[i]; - end - - /////////////////////////////////////////////////////////////////////////// - - reg [`NUM_WARPS-1:0] valid_table, valid_table_n; - reg [`NW_BITS-1:0] deq_wid, deq_wid_n; - reg [`NW_BITS-1:0] deq_wid_rr, deq_wid_rr_n; - reg deq_valid, deq_valid_n; - reg [DATAW-1:0] deq_instr, deq_instr_n; - reg [NWARPSW-1:0] num_warps; - - `UNUSED_VAR (deq_instr) - - // calculate valid table - always @(*) begin - valid_table_n = valid_table; - if (deq_fire) begin - valid_table_n[deq_wid] = !q_alm_empty[deq_wid]; - end - if (enq_fire) begin - valid_table_n[decode_if.wid] = 1; - end - end - - // round-robin warp scheduling - VX_rr_arbiter #( - .NUM_REQS (`NUM_WARPS) - ) rr_arbiter ( - .clk (clk), - .reset (reset), - .requests (valid_table_n), - .grant_index (deq_wid_rr_n), - `UNUSED_PIN (grant_valid), - `UNUSED_PIN (grant_onehot), - `UNUSED_PIN (enable) - ); - - // schedule the next instruction to issue - always @(*) begin - if (num_warps > 1) begin - deq_valid_n = 1; - deq_wid_n = deq_wid_rr; - deq_instr_n = q_data_out[deq_wid_rr]; - end else if (1 == num_warps && !(deq_fire && q_alm_empty[deq_wid])) begin - deq_valid_n = 1; - deq_wid_n = deq_wid; - deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid]; - end else begin - deq_valid_n = enq_fire; - deq_wid_n = decode_if.wid; - deq_instr_n = q_data_in; - end - end - - wire warp_added = enq_fire && q_empty[decode_if.wid]; - wire warp_removed = deq_fire && ~(enq_fire && decode_if.wid == deq_wid) && q_alm_empty[deq_wid]; - - always @(posedge clk) begin - if (reset) begin - valid_table <= 0; - deq_valid <= 0; - num_warps <= 0; - end else begin - valid_table <= valid_table_n; - deq_valid <= deq_valid_n; - - - if (warp_added && !warp_removed) begin - num_warps <= num_warps + NWARPSW'(1); - end else if (warp_removed && !warp_added) begin - num_warps <= num_warps - NWARPSW'(1); - end - end - - deq_wid <= deq_wid_n; - deq_wid_rr <= deq_wid_rr_n; - deq_instr <= deq_instr_n; - end - - assign decode_if.ready = ~q_full[decode_if.wid]; - - assign q_data_in = {decode_if.uuid, - decode_if.tmask, - decode_if.PC, - decode_if.ex_type, - decode_if.op_type, - decode_if.op_mod, - decode_if.wb, - decode_if.use_PC, - decode_if.use_imm, - decode_if.imm, - decode_if.rd, - decode_if.rs1, - decode_if.rs2, - decode_if.rs3}; - - assign ibuffer_if.valid = deq_valid; - assign ibuffer_if.wid = deq_wid; - assign {ibuffer_if.uuid, - ibuffer_if.tmask, - ibuffer_if.PC, - ibuffer_if.ex_type, - ibuffer_if.op_type, - ibuffer_if.op_mod, - ibuffer_if.wb, - ibuffer_if.use_PC, - ibuffer_if.use_imm, - ibuffer_if.imm, - ibuffer_if.rd, - ibuffer_if.rs1, - ibuffer_if.rs2, - ibuffer_if.rs3} = deq_instr; - - // scoreboard forwarding - assign ibuffer_if.wid_n = deq_wid_n; - assign ibuffer_if.rd_n = deq_instr_n[3*`NR_BITS +: `NR_BITS]; - assign ibuffer_if.rs1_n = deq_instr_n[2*`NR_BITS +: `NR_BITS]; - assign ibuffer_if.rs2_n = deq_instr_n[1*`NR_BITS +: `NR_BITS]; - assign ibuffer_if.rs3_n = deq_instr_n[0*`NR_BITS +: `NR_BITS]; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_icache_stage.sv b/hw/rtl/VX_icache_stage.sv deleted file mode 100644 index be096c5f..00000000 --- a/hw/rtl/VX_icache_stage.sv +++ /dev/null @@ -1,102 +0,0 @@ -`include "VX_define.vh" - -module VX_icache_stage #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_icache_stage - - input wire clk, - input wire reset, - - // Icache interface - VX_icache_req_if.master icache_req_if, - VX_icache_rsp_if.slave icache_rsp_if, - - // request - VX_ifetch_req_if.slave ifetch_req_if, - - // reponse - VX_ifetch_rsp_if.master ifetch_rsp_if -); - - `UNUSED_PARAM (CORE_ID) - `UNUSED_VAR (reset) - - localparam OUT_REG = 0; - - wire [`NW_BITS-1:0] req_tag, rsp_tag; - - wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; - - assign req_tag = ifetch_req_if.wid; - assign rsp_tag = icache_rsp_if.tag[`NW_BITS-1:0]; - - wire [`UUID_BITS-1:0] rsp_uuid; - wire [31:0] rsp_PC; - wire [`NUM_THREADS-1:0] rsp_tmask; - - VX_dp_ram #( - .DATAW (32 + `NUM_THREADS + `UUID_BITS), - .SIZE (`NUM_WARPS), - .LUTRAM (1) - ) req_metadata ( - .clk (clk), - .wren (icache_req_fire), - .waddr (req_tag), - .wdata ({ifetch_req_if.PC, ifetch_req_if.tmask, ifetch_req_if.uuid}), - .raddr (rsp_tag), - .rdata ({rsp_PC, rsp_tmask, rsp_uuid}) - ); - - `RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR), - ("%t: *** invalid PC=%0h, wid=%0d, tmask=%b (#%0d)", $time, ifetch_req_if.PC, ifetch_req_if.wid, ifetch_req_if.tmask, ifetch_req_if.uuid)) - - // Icache Request - assign icache_req_if.valid = ifetch_req_if.valid; - assign icache_req_if.addr = ifetch_req_if.PC[31:2]; - assign icache_req_if.tag = {ifetch_req_if.uuid, req_tag}; - - // Can accept new request? - assign ifetch_req_if.ready = icache_req_if.ready; - - wire [`NW_BITS-1:0] rsp_wid = rsp_tag; - - wire stall_out = ~ifetch_rsp_if.ready && (0 == OUT_REG && ifetch_rsp_if.valid); - - VX_pipe_register #( - .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `UUID_BITS), - .RESETW (1), - .DEPTH (OUT_REG) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_out), - .data_in ({icache_rsp_if.valid, rsp_wid, rsp_tmask, rsp_PC, icache_rsp_if.data, rsp_uuid}), - .data_out ({ifetch_rsp_if.valid, ifetch_rsp_if.wid, ifetch_rsp_if.tmask, ifetch_rsp_if.PC, ifetch_rsp_if.data, ifetch_rsp_if.uuid}) - ); - - // Can accept new response? - assign icache_rsp_if.ready = ~stall_out; - - `SCOPE_ASSIGN (icache_req_fire, icache_req_fire); - `SCOPE_ASSIGN (icache_req_uuid, ifetch_req_if.uuid); - `SCOPE_ASSIGN (icache_req_addr, {icache_req_if.addr, 2'b0}); - `SCOPE_ASSIGN (icache_req_tag, req_tag); - - `SCOPE_ASSIGN (icache_rsp_fire, icache_rsp_if.valid && icache_rsp_if.ready); - `SCOPE_ASSIGN (icache_rsp_uuid, rsp_uuid); - `SCOPE_ASSIGN (icache_rsp_data, icache_rsp_if.data); - `SCOPE_ASSIGN (icache_rsp_tag, rsp_tag); - -`ifdef DBG_TRACE_CORE_ICACHE - always @(posedge clk) begin - if (icache_req_fire) begin - dpi_trace("%d: I$%0d req: wid=%0d, PC=%0h (#%0d)\n", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC, ifetch_req_if.uuid); - end - if (ifetch_rsp_if.valid && ifetch_rsp_if.ready) begin - dpi_trace("%d: I$%0d rsp: wid=%0d, PC=%0h, data=%0h (#%0d)\n", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.data, ifetch_rsp_if.uuid); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_ipdom_stack.sv b/hw/rtl/VX_ipdom_stack.sv deleted file mode 100644 index 2c0cc322..00000000 --- a/hw/rtl/VX_ipdom_stack.sv +++ /dev/null @@ -1,68 +0,0 @@ -`include "VX_platform.vh" - -module VX_ipdom_stack #( - parameter WIDTH = 1, - parameter DEPTH = 1 -) ( - input wire clk, - input wire reset, - input wire pair, - input wire [WIDTH - 1:0] q1, - input wire [WIDTH - 1:0] q2, - output wire [WIDTH - 1:0] d, - input wire push, - input wire pop, - output wire index, - output wire empty, - output wire full -); - localparam ADDRW = $clog2(DEPTH); - - reg is_part [DEPTH-1:0]; - - reg [ADDRW-1:0] rd_ptr, wr_ptr; - - wire [WIDTH-1:0] d1, d2; - - always @(posedge clk) begin - if (reset) begin - rd_ptr <= 0; - wr_ptr <= 0; - end else begin - if (push) begin - rd_ptr <= wr_ptr; - wr_ptr <= wr_ptr + ADDRW'(1); - end else if (pop) begin - wr_ptr <= wr_ptr - ADDRW'(is_part[rd_ptr]); - rd_ptr <= rd_ptr - ADDRW'(is_part[rd_ptr]); - end - end - end - - VX_dp_ram #( - .DATAW (WIDTH * 2), - .SIZE (DEPTH), - .LUTRAM (1) - ) store ( - .clk (clk), - .wren (push), - .waddr (wr_ptr), - .wdata ({q2, q1}), - .raddr (rd_ptr), - .rdata ({d2, d1}) - ); - - always @(posedge clk) begin - if (push) begin - is_part[wr_ptr] <= ~pair; - end else if (pop) begin - is_part[rd_ptr] <= 1; - end - end - - assign index = is_part[rd_ptr]; - assign d = index ? d1 : d2; - assign empty = (ADDRW'(0) == wr_ptr); - assign full = (ADDRW'(DEPTH-1) == wr_ptr); - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_issue.sv b/hw/rtl/VX_issue.sv deleted file mode 100644 index 4abedc63..00000000 --- a/hw/rtl/VX_issue.sv +++ /dev/null @@ -1,256 +0,0 @@ -`include "VX_define.vh" - -module VX_issue #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_issue - - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE - VX_perf_pipeline_if.issue perf_issue_if, -`endif - - VX_decode_if.slave decode_if, - VX_writeback_if.slave writeback_if, - - VX_alu_req_if.master alu_req_if, - VX_lsu_req_if.master lsu_req_if, - VX_csr_req_if.master csr_req_if, -`ifdef EXT_F_ENABLE - VX_fpu_req_if.master fpu_req_if, -`endif - VX_gpu_req_if.master gpu_req_if -); - VX_ibuffer_if ibuffer_if(); - VX_gpr_req_if gpr_req_if(); - VX_gpr_rsp_if gpr_rsp_if(); - VX_writeback_if sboard_wb_if(); - VX_ibuffer_if scoreboard_if(); - VX_ibuffer_if dispatch_if(); - - // GPR request interface - assign gpr_req_if.wid = ibuffer_if.wid; - assign gpr_req_if.rs1 = ibuffer_if.rs1; - assign gpr_req_if.rs2 = ibuffer_if.rs2; - assign gpr_req_if.rs3 = ibuffer_if.rs3; - - // scoreboard writeback interface - assign sboard_wb_if.valid = writeback_if.valid; - assign sboard_wb_if.uuid = writeback_if.uuid; - assign sboard_wb_if.wid = writeback_if.wid; - assign sboard_wb_if.PC = writeback_if.PC; - assign sboard_wb_if.rd = writeback_if.rd; - assign sboard_wb_if.eop = writeback_if.eop; - - // scoreboard interface - assign scoreboard_if.valid = ibuffer_if.valid && dispatch_if.ready; - assign scoreboard_if.uuid = ibuffer_if.uuid; - assign scoreboard_if.wid = ibuffer_if.wid; - assign scoreboard_if.PC = ibuffer_if.PC; - assign scoreboard_if.wb = ibuffer_if.wb; - assign scoreboard_if.rd = ibuffer_if.rd; - assign scoreboard_if.rd_n = ibuffer_if.rd_n; - assign scoreboard_if.rs1_n = ibuffer_if.rs1_n; - assign scoreboard_if.rs2_n = ibuffer_if.rs2_n; - assign scoreboard_if.rs3_n = ibuffer_if.rs3_n; - assign scoreboard_if.wid_n = ibuffer_if.wid_n; - - // dispatch interface - assign dispatch_if.valid = ibuffer_if.valid && scoreboard_if.ready; - assign dispatch_if.uuid = ibuffer_if.uuid; - assign dispatch_if.wid = ibuffer_if.wid; - assign dispatch_if.tmask = ibuffer_if.tmask; - assign dispatch_if.PC = ibuffer_if.PC; - assign dispatch_if.ex_type = ibuffer_if.ex_type; - assign dispatch_if.op_type = ibuffer_if.op_type; - assign dispatch_if.op_mod = ibuffer_if.op_mod; - assign dispatch_if.wb = ibuffer_if.wb; - assign dispatch_if.rd = ibuffer_if.rd; - assign dispatch_if.rs1 = ibuffer_if.rs1; - assign dispatch_if.imm = ibuffer_if.imm; - assign dispatch_if.use_PC = ibuffer_if.use_PC; - assign dispatch_if.use_imm = ibuffer_if.use_imm; - - // issue the instruction - assign ibuffer_if.ready = scoreboard_if.ready && dispatch_if.ready; - - `RESET_RELAY (ibuf_reset); - `RESET_RELAY (scoreboard_reset); - `RESET_RELAY (gpr_reset); - `RESET_RELAY (dispatch_reset); - - VX_ibuffer #( - .CORE_ID(CORE_ID) - ) ibuffer ( - .clk (clk), - .reset (ibuf_reset), - .decode_if (decode_if), - .ibuffer_if (ibuffer_if) - ); - - VX_scoreboard #( - .CORE_ID(CORE_ID) - ) scoreboard ( - .clk (clk), - .reset (scoreboard_reset), - .writeback_if(sboard_wb_if), - .ibuffer_if (scoreboard_if) - ); - - VX_gpr_stage #( - .CORE_ID(CORE_ID) - ) gpr_stage ( - .clk (clk), - .reset (gpr_reset), - .writeback_if (writeback_if), - .gpr_req_if (gpr_req_if), - .gpr_rsp_if (gpr_rsp_if) - ); - - VX_dispatch dispatch ( - .clk (clk), - .reset (dispatch_reset), - .ibuffer_if (dispatch_if), - .gpr_rsp_if (gpr_rsp_if), - .alu_req_if (alu_req_if), - .lsu_req_if (lsu_req_if), - .csr_req_if (csr_req_if), - `ifdef EXT_F_ENABLE - .fpu_req_if (fpu_req_if), - `endif - .gpu_req_if (gpu_req_if) - ); - - `SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready); - `SCOPE_ASSIGN (issue_uuid, ibuffer_if.uuid); - `SCOPE_ASSIGN (issue_tmask, ibuffer_if.tmask); - `SCOPE_ASSIGN (issue_ex_type, ibuffer_if.ex_type); - `SCOPE_ASSIGN (issue_op_type, ibuffer_if.op_type); - `SCOPE_ASSIGN (issue_op_mod, ibuffer_if.op_mod); - `SCOPE_ASSIGN (issue_wb, ibuffer_if.wb); - `SCOPE_ASSIGN (issue_rd, ibuffer_if.rd); - `SCOPE_ASSIGN (issue_rs1, ibuffer_if.rs1); - `SCOPE_ASSIGN (issue_rs2, ibuffer_if.rs2); - `SCOPE_ASSIGN (issue_rs3, ibuffer_if.rs3); - `SCOPE_ASSIGN (issue_imm, ibuffer_if.imm); - `SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC); - `SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm); - `SCOPE_ASSIGN (scoreboard_delay, !scoreboard_if.ready); - `SCOPE_ASSIGN (dispatch_delay, !dispatch_if.ready); - `SCOPE_ASSIGN (gpr_rs1, gpr_rsp_if.rs1_data); - `SCOPE_ASSIGN (gpr_rs2, gpr_rsp_if.rs2_data); - `SCOPE_ASSIGN (gpr_rs3, gpr_rsp_if.rs3_data); - `SCOPE_ASSIGN (writeback_valid, writeback_if.valid); - `SCOPE_ASSIGN (writeback_uuid, writeback_if.uuid); - `SCOPE_ASSIGN (writeback_tmask, writeback_if.tmask); - `SCOPE_ASSIGN (writeback_rd, writeback_if.rd); - `SCOPE_ASSIGN (writeback_data, writeback_if.data); - `SCOPE_ASSIGN (writeback_eop, writeback_if.eop); - -`ifdef PERF_ENABLE - reg [`PERF_CTR_BITS-1:0] perf_ibf_stalls; - reg [`PERF_CTR_BITS-1:0] perf_scb_stalls; - reg [`PERF_CTR_BITS-1:0] perf_alu_stalls; - reg [`PERF_CTR_BITS-1:0] perf_lsu_stalls; - reg [`PERF_CTR_BITS-1:0] perf_csr_stalls; - reg [`PERF_CTR_BITS-1:0] perf_gpu_stalls; -`ifdef EXT_F_ENABLE - reg [`PERF_CTR_BITS-1:0] perf_fpu_stalls; -`endif - - always @(posedge clk) begin - if (reset) begin - perf_ibf_stalls <= 0; - perf_scb_stalls <= 0; - perf_alu_stalls <= 0; - perf_lsu_stalls <= 0; - perf_csr_stalls <= 0; - perf_gpu_stalls <= 0; - `ifdef EXT_F_ENABLE - perf_fpu_stalls <= 0; - `endif - end else begin - if (decode_if.valid & ~decode_if.ready) begin - perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1; - end - if (scoreboard_if.valid & ~scoreboard_if.ready) begin - perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1; - end - if (dispatch_if.valid & ~dispatch_if.ready) begin - case (dispatch_if.ex_type) - `EX_ALU: perf_alu_stalls <= perf_alu_stalls + `PERF_CTR_BITS'd1; - `ifdef EXT_F_ENABLE - `EX_FPU: perf_fpu_stalls <= perf_fpu_stalls + `PERF_CTR_BITS'd1; - `endif - `EX_LSU: perf_lsu_stalls <= perf_lsu_stalls + `PERF_CTR_BITS'd1; - `EX_CSR: perf_csr_stalls <= perf_csr_stalls + `PERF_CTR_BITS'd1; - //`EX_GPU: - default: perf_gpu_stalls <= perf_gpu_stalls + `PERF_CTR_BITS'd1; - endcase - end - end - end - - assign perf_issue_if.ibf_stalls = perf_ibf_stalls; - assign perf_issue_if.scb_stalls = perf_scb_stalls; - assign perf_issue_if.alu_stalls = perf_alu_stalls; - assign perf_issue_if.lsu_stalls = perf_lsu_stalls; - assign perf_issue_if.csr_stalls = perf_csr_stalls; - assign perf_issue_if.gpu_stalls = perf_gpu_stalls; -`ifdef EXT_F_ENABLE - assign perf_issue_if.fpu_stalls = perf_fpu_stalls; -`endif -`endif - -`ifdef DBG_TRACE_CORE_PIPELINE - always @(posedge clk) begin - if (alu_req_if.valid && alu_req_if.ready) begin - dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=", - $time, CORE_ID, alu_req_if.wid, alu_req_if.PC, alu_req_if.tmask, alu_req_if.rd); - `TRACE_ARRAY1D(alu_req_if.rs1_data, `NUM_THREADS); - dpi_trace(", rs2_data="); - `TRACE_ARRAY1D(alu_req_if.rs2_data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", alu_req_if.uuid); - end - if (lsu_req_if.valid && lsu_req_if.ready) begin - dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rd=%0d, offset=%0h, addr=", - $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rd, lsu_req_if.offset); - `TRACE_ARRAY1D(lsu_req_if.base_addr, `NUM_THREADS); - dpi_trace(", data="); - `TRACE_ARRAY1D(lsu_req_if.store_data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", lsu_req_if.uuid); - end - if (csr_req_if.valid && csr_req_if.ready) begin - dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, rd=%0d, addr=%0h, rs1_data=", - $time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.rd, csr_req_if.addr); - `TRACE_ARRAY1D(csr_req_if.rs1_data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", csr_req_if.uuid); - end - `ifdef EXT_F_ENABLE - if (fpu_req_if.valid && fpu_req_if.ready) begin - dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rd=%0d, rs1_data=", - $time, CORE_ID, fpu_req_if.wid, fpu_req_if.PC, fpu_req_if.tmask, fpu_req_if.rd); - `TRACE_ARRAY1D(fpu_req_if.rs1_data, `NUM_THREADS); - dpi_trace(", rs2_data="); - `TRACE_ARRAY1D(fpu_req_if.rs2_data, `NUM_THREADS); - dpi_trace(", rs3_data="); - `TRACE_ARRAY1D(fpu_req_if.rs3_data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", fpu_req_if.uuid); - end - `endif - if (gpu_req_if.valid && gpu_req_if.ready) begin - dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=GPU, tmask=%b, rd=%0d, rs1_data=", - $time, CORE_ID, gpu_req_if.wid, gpu_req_if.PC, gpu_req_if.tmask, gpu_req_if.rd); - `TRACE_ARRAY1D(gpu_req_if.rs1_data, `NUM_THREADS); - dpi_trace(", rs2_data="); - `TRACE_ARRAY1D(gpu_req_if.rs2_data, `NUM_THREADS); - dpi_trace(", rs3_data="); - `TRACE_ARRAY1D(gpu_req_if.rs3_data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", gpu_req_if.uuid); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_lsu_unit.sv b/hw/rtl/VX_lsu_unit.sv deleted file mode 100644 index 5116035f..00000000 --- a/hw/rtl/VX_lsu_unit.sv +++ /dev/null @@ -1,372 +0,0 @@ -`include "VX_define.vh" - -module VX_lsu_unit #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_lsu_unit - - input wire clk, - input wire reset, - - // Dcache interface - VX_dcache_req_if.master dcache_req_if, - VX_dcache_rsp_if.slave dcache_rsp_if, - - // inputs - VX_lsu_req_if.slave lsu_req_if, - - // outputs - VX_commit_if.master ld_commit_if, - VX_commit_if.master st_commit_if -); - localparam MEM_ASHIFT = `CLOG2(`MEM_BLOCK_SIZE); - localparam MEM_ADDRW = 32 - MEM_ASHIFT; - localparam REQ_ASHIFT = `CLOG2(`DCACHE_WORD_SIZE); - - `STATIC_ASSERT(0 == (`IO_BASE_ADDR % MEM_ASHIFT), ("invalid parameter")) - `STATIC_ASSERT(0 == (`SMEM_BASE_ADDR % MEM_ASHIFT), ("invalid parameter")) - `STATIC_ASSERT(`SMEM_SIZE == `MEM_BLOCK_SIZE * (`SMEM_SIZE / `MEM_BLOCK_SIZE), ("invalid parameter")) - - wire req_valid; - wire [`UUID_BITS-1:0] req_uuid; - wire [`NUM_THREADS-1:0] req_tmask; - wire [`NUM_THREADS-1:0][31:0] req_addr; - wire [`INST_LSU_BITS-1:0] req_type; - wire [`NUM_THREADS-1:0][31:0] req_data; - wire [`NR_BITS-1:0] req_rd; - wire req_wb; - wire [`NW_BITS-1:0] req_wid; - wire [31:0] req_pc; - wire req_is_dup; - wire req_is_prefetch; - - wire mbuf_empty; - - wire [`NUM_THREADS-1:0][`CACHE_ADDR_TYPE_BITS-1:0] lsu_addr_type, req_addr_type; - - // full address calculation - wire [`NUM_THREADS-1:0][31:0] full_addr; - for (genvar i = 0; i < `NUM_THREADS; i++) begin - assign full_addr[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset; - end - - // detect duplicate addresses - wire [`NUM_THREADS-2:0] addr_matches; - for (genvar i = 0; i < (`NUM_THREADS-1); i++) begin - assign addr_matches[i] = (lsu_req_if.base_addr[i+1] == lsu_req_if.base_addr[0]) || ~lsu_req_if.tmask[i+1]; - end - - wire lsu_is_dup = lsu_req_if.tmask[0] && (& addr_matches); - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - // is non-cacheable address - wire is_addr_nc = (full_addr[i][MEM_ASHIFT +: MEM_ADDRW] >= MEM_ADDRW'(`IO_BASE_ADDR >> MEM_ASHIFT)); - if (`SM_ENABLE) begin - // is shared memory address - wire is_addr_sm = (full_addr[i][MEM_ASHIFT +: MEM_ADDRW] >= MEM_ADDRW'((`SMEM_BASE_ADDR - `SMEM_SIZE) >> MEM_ASHIFT)) - & (full_addr[i][MEM_ASHIFT +: MEM_ADDRW] < MEM_ADDRW'(`SMEM_BASE_ADDR >> MEM_ASHIFT)); - assign lsu_addr_type[i] = {is_addr_nc, is_addr_sm}; - end else begin - assign lsu_addr_type[i] = is_addr_nc; - end - end - - // fence stalls the pipeline until all pending requests are sent - wire fence_wait = lsu_req_if.is_fence && (req_valid || !mbuf_empty); - - wire ready_in; - wire stall_in = ~ready_in && req_valid; - - wire lsu_valid = lsu_req_if.valid && ~fence_wait; - - wire lsu_wb = lsu_req_if.wb | lsu_req_if.is_prefetch; - - VX_pipe_register #( - .DATAW (1 + 1 + 1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * `CACHE_ADDR_TYPE_BITS) + `INST_LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)), - .RESETW (1) - ) req_pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_in), - .data_in ({lsu_valid, lsu_is_dup, lsu_req_if.is_prefetch, lsu_req_if.uuid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_addr, lsu_addr_type, lsu_req_if.op_type, lsu_req_if.rd, lsu_wb, lsu_req_if.store_data}), - .data_out ({req_valid, req_is_dup, req_is_prefetch, req_uuid, req_wid, req_tmask, req_pc, req_addr, req_addr_type, req_type, req_rd, req_wb, req_data}) - ); - - // Can accept new request? - assign lsu_req_if.ready = ~stall_in && ~fence_wait; - - wire [`UUID_BITS-1:0] rsp_uuid; - wire [`NW_BITS-1:0] rsp_wid; - wire [31:0] rsp_pc; - wire [`NR_BITS-1:0] rsp_rd; - wire rsp_wb; - wire [`INST_LSU_BITS-1:0] rsp_type; - wire rsp_is_dup; - wire rsp_is_prefetch; - - reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] rsp_rem_mask; - wire [`NUM_THREADS-1:0] rsp_rem_mask_n; - wire [`NUM_THREADS-1:0] rsp_tmask; - - reg [`NUM_THREADS-1:0] req_sent_mask; - reg is_req_start; - - wire [`LSUQ_ADDR_BITS-1:0] mbuf_waddr, mbuf_raddr; - wire mbuf_full; - - `UNUSED_VAR (rsp_type) - `UNUSED_VAR (rsp_is_prefetch) - - wire [`NUM_THREADS-1:0][REQ_ASHIFT-1:0] req_offset, rsp_offset; - for (genvar i = 0; i < `NUM_THREADS; i++) begin - assign req_offset[i] = req_addr[i][1:0]; - end - - wire [`NUM_THREADS-1:0] dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready; - - wire dcache_rsp_fire = dcache_rsp_if.valid && dcache_rsp_if.ready; - - wire [`NUM_THREADS-1:0] req_tmask_dup = req_tmask & {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1}; - - wire mbuf_push = ~mbuf_full - && (| ({`NUM_THREADS{req_valid}} & req_tmask_dup & dcache_req_if.ready)) - && is_req_start // first submission only - && req_wb; // loads only - - wire mbuf_pop = dcache_rsp_fire && (0 == rsp_rem_mask_n); - - assign mbuf_raddr = dcache_rsp_if.tag[`CACHE_ADDR_TYPE_BITS +: `LSUQ_ADDR_BITS]; - `UNUSED_VAR (dcache_rsp_if.tag) - - // do not writeback from software prefetch - wire req_wb2 = req_wb && ~req_is_prefetch; - - VX_index_buffer #( - .DATAW (`UUID_BITS + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1 + 1), - .SIZE (`LSUQ_SIZE) - ) req_metadata ( - .clk (clk), - .reset (reset), - .write_addr (mbuf_waddr), - .acquire_slot (mbuf_push), - .read_addr (mbuf_raddr), - .write_data ({req_uuid, req_wid, req_pc, req_tmask, req_rd, req_wb2, req_type, req_offset, req_is_dup, req_is_prefetch}), - .read_data ({rsp_uuid, rsp_wid, rsp_pc, rsp_tmask, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup, rsp_is_prefetch}), - .release_addr (mbuf_raddr), - .release_slot (mbuf_pop), - .full (mbuf_full), - .empty (mbuf_empty) - ); - - wire dcache_req_ready = &(dcache_req_if.ready | req_sent_mask | ~req_tmask_dup); - - wire [`NUM_THREADS-1:0] req_sent_mask_n = req_sent_mask | dcache_req_fire; - - always @(posedge clk) begin - if (reset) begin - req_sent_mask <= 0; - is_req_start <= 1; - end else begin - if (dcache_req_ready) begin - req_sent_mask <= 0; - is_req_start <= 1; - end else begin - req_sent_mask <= req_sent_mask_n; - is_req_start <= (0 == req_sent_mask_n); - end - end - end - - // need to hold the acquired tag index until the full request is submitted - reg [`LSUQ_ADDR_BITS-1:0] req_tag_hold; - wire [`LSUQ_ADDR_BITS-1:0] req_tag = is_req_start ? mbuf_waddr : req_tag_hold; - always @(posedge clk) begin - if (mbuf_push) begin - req_tag_hold <= mbuf_waddr; - end - end - - assign rsp_rem_mask_n = rsp_rem_mask[mbuf_raddr] & ~dcache_rsp_if.tmask; - - always @(posedge clk) begin - if (mbuf_push) begin - rsp_rem_mask[mbuf_waddr] <= req_tmask_dup; - end - if (dcache_rsp_fire) begin - rsp_rem_mask[mbuf_raddr] <= rsp_rem_mask_n; - end - end - - // ensure all dependencies for the requests are resolved - wire req_dep_ready = (req_wb && ~(mbuf_full && is_req_start)) - || (~req_wb && st_commit_if.ready); - - // DCache Request - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - - reg [3:0] mem_req_byteen; - reg [31:0] mem_req_data; - - always @(*) begin - mem_req_byteen = {4{req_wb}}; - case (`INST_LSU_WSIZE(req_type)) - 0: mem_req_byteen[req_offset[i]] = 1; - 1: begin - mem_req_byteen[req_offset[i]] = 1; - mem_req_byteen[{req_offset[i][1], 1'b1}] = 1; - end - default : mem_req_byteen = {4{1'b1}}; - endcase - end - - always @(*) begin - mem_req_data = req_data[i]; - case (req_offset[i]) - 1: mem_req_data[31:8] = req_data[i][23:0]; - 2: mem_req_data[31:16] = req_data[i][15:0]; - 3: mem_req_data[31:24] = req_data[i][7:0]; - default:; - endcase - end - - assign dcache_req_if.valid[i] = req_valid && req_dep_ready && req_tmask_dup[i] && !req_sent_mask[i]; - assign dcache_req_if.rw[i] = ~req_wb; - assign dcache_req_if.addr[i] = req_addr[i][31:2]; - assign dcache_req_if.byteen[i] = mem_req_byteen; - assign dcache_req_if.data[i] = mem_req_data; - assign dcache_req_if.tag[i] = {req_uuid, `LSU_TAG_ID_BITS'(req_tag), req_addr_type[i]}; - end - - assign ready_in = req_dep_ready && dcache_req_ready; - - // send store commit - - wire is_store_rsp = req_valid && ~req_wb && dcache_req_ready; - - assign st_commit_if.valid = is_store_rsp; - assign st_commit_if.uuid = req_uuid; - assign st_commit_if.wid = req_wid; - assign st_commit_if.tmask = req_tmask; - assign st_commit_if.PC = req_pc; - assign st_commit_if.rd = 0; - assign st_commit_if.wb = 0; - assign st_commit_if.eop = 1'b1; - assign st_commit_if.data = 0; - - // load response formatting - - reg [`NUM_THREADS-1:0][31:0] rsp_data; - wire [`NUM_THREADS-1:0] rsp_tmask_qual; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [31:0] rsp_data32 = (i == 0 || rsp_is_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i]; - wire [15:0] rsp_data16 = rsp_offset[i][1] ? rsp_data32[31:16] : rsp_data32[15:0]; - wire [7:0] rsp_data8 = rsp_offset[i][0] ? rsp_data16[15:8] : rsp_data16[7:0]; - - always @(*) begin - case (`INST_LSU_FMT(rsp_type)) - `INST_FMT_B: rsp_data[i] = 32'(signed'(rsp_data8)); - `INST_FMT_H: rsp_data[i] = 32'(signed'(rsp_data16)); - `INST_FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data8)); - `INST_FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data16)); - default: rsp_data[i] = rsp_data32; - endcase - end - end - - assign rsp_tmask_qual = rsp_is_dup ? rsp_tmask : dcache_rsp_if.tmask; - - // send load commit - - wire load_rsp_stall = ~ld_commit_if.ready && ld_commit_if.valid; - - VX_pipe_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1), - .RESETW (1) - ) rsp_pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!load_rsp_stall), - .data_in ({dcache_rsp_if.valid, rsp_uuid, rsp_wid, rsp_tmask_qual, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}), - .data_out ({ld_commit_if.valid, ld_commit_if.uuid, ld_commit_if.wid, ld_commit_if.tmask, ld_commit_if.PC, ld_commit_if.rd, ld_commit_if.wb, ld_commit_if.data, ld_commit_if.eop}) - ); - - // Can accept new cache response? - assign dcache_rsp_if.ready = ~load_rsp_stall; - - // scope registration - `SCOPE_ASSIGN (dcache_req_fire, dcache_req_fire); - `SCOPE_ASSIGN (dcache_req_uuid, req_uuid); - `SCOPE_ASSIGN (dcache_req_addr, req_addr); - `SCOPE_ASSIGN (dcache_req_rw, ~req_wb); - `SCOPE_ASSIGN (dcache_req_byteen,dcache_req_if.byteen); - `SCOPE_ASSIGN (dcache_req_data, dcache_req_if.data); - `SCOPE_ASSIGN (dcache_req_tag, req_tag); - `SCOPE_ASSIGN (dcache_rsp_fire, dcache_rsp_if.tmask & {`NUM_THREADS{dcache_rsp_fire}}); - `SCOPE_ASSIGN (dcache_rsp_uuid, rsp_uuid); - `SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data); - `SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr); - -`ifndef SYNTHESIS - reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + `UUID_BITS + 64 + 1)-1:0] pending_reqs; - wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); - - always @(posedge clk) begin - if (reset) begin - pending_reqs <= '0; - end begin - if (mbuf_push) begin - pending_reqs[mbuf_waddr] <= {req_wid, req_pc, req_rd, req_uuid, $time, 1'b1}; - end - if (mbuf_pop) begin - pending_reqs[mbuf_raddr] <= '0; - end - end - - for (integer i = 0; i < `LSUQ_SIZE; ++i) begin - if (pending_reqs[i][0]) begin - `ASSERT(($time - pending_reqs[i][1 +: 64]) < delay_timeout, - ("%t: *** D$%0d response timeout: remaining=%b, wid=%0d, PC=%0h, rd=%0d (#%0d)", - $time, CORE_ID, rsp_rem_mask[i], pending_reqs[i][1+64+`UUID_BITS+`NR_BITS+32 +: `NW_BITS], - pending_reqs[i][1+64+`UUID_BITS+`NR_BITS +: 32], - pending_reqs[i][1+64+`UUID_BITS +: `NR_BITS], - pending_reqs[i][1+64 +: `UUID_BITS])); - end - end - end -`endif - -`ifdef DBG_TRACE_CORE_DCACHE - wire dcache_req_fire_any = (| dcache_req_fire); - always @(posedge clk) begin - if (lsu_req_if.valid && fence_wait) begin - dpi_trace("%d: *** D$%0d fence wait\n", $time, CORE_ID); - end - if (dcache_req_fire_any) begin - if (dcache_req_if.rw[0]) begin - dpi_trace("%d: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire); - `TRACE_ARRAY1D(req_addr, `NUM_THREADS); - dpi_trace(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen); - `TRACE_ARRAY1D(req_addr_type, `NUM_THREADS); - dpi_trace(", data="); - `TRACE_ARRAY1D(dcache_req_if.data, `NUM_THREADS); - dpi_trace(", (#%0d)\n", req_uuid); - end else begin - dpi_trace("%d: D$%0d Rd Req: prefetch=%b, wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_is_prefetch, req_wid, req_pc, dcache_req_fire); - `TRACE_ARRAY1D(req_addr, `NUM_THREADS); - dpi_trace(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen); - `TRACE_ARRAY1D(req_addr_type, `NUM_THREADS); - dpi_trace(", rd=%0d, is_dup=%b (#%0d)\n", req_rd, req_is_dup, req_uuid); - end - end - if (dcache_rsp_fire) begin - dpi_trace("%d: D$%0d Rsp: prefetch=%b, wid=%0d, PC=%0h, tmask=%b, tag=%0h, rd=%0d, data=", - $time, CORE_ID, rsp_is_prefetch, rsp_wid, rsp_pc, dcache_rsp_if.tmask, mbuf_raddr, rsp_rd); - `TRACE_ARRAY1D(dcache_rsp_if.data, `NUM_THREADS); - dpi_trace(", is_dup=%b (#%0d)\n", rsp_is_dup, rsp_uuid); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_mem_arb.sv b/hw/rtl/VX_mem_arb.sv deleted file mode 100644 index 5a410476..00000000 --- a/hw/rtl/VX_mem_arb.sv +++ /dev/null @@ -1,146 +0,0 @@ -`include "VX_define.vh" - -module VX_mem_arb #( - parameter NUM_REQS = 1, - parameter DATA_WIDTH = 1, - parameter ADDR_WIDTH = 1, - parameter TAG_IN_WIDTH = 1, - parameter TAG_SEL_IDX = 0, - parameter BUFFERED_REQ = 0, - parameter BUFFERED_RSP = 0, - parameter TYPE = "P", - - parameter DATA_SIZE = (DATA_WIDTH / 8), - parameter LOG_NUM_REQS = `CLOG2(NUM_REQS), - parameter TAG_OUT_WIDTH = TAG_IN_WIDTH + LOG_NUM_REQS -) ( - input wire clk, - input wire reset, - - // input requests - input wire [NUM_REQS-1:0] req_valid_in, - input wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] req_tag_in, - input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_in, - input wire [NUM_REQS-1:0] req_rw_in, - input wire [NUM_REQS-1:0][DATA_SIZE-1:0] req_byteen_in, - input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_in, - output wire [NUM_REQS-1:0] req_ready_in, - - // output request - output wire req_valid_out, - output wire [TAG_OUT_WIDTH-1:0] req_tag_out, - output wire [ADDR_WIDTH-1:0] req_addr_out, - output wire req_rw_out, - output wire [DATA_SIZE-1:0] req_byteen_out, - output wire [DATA_WIDTH-1:0] req_data_out, - input wire req_ready_out, - - // input response - input wire rsp_valid_in, - input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in, - input wire [DATA_WIDTH-1:0] rsp_data_in, - output wire rsp_ready_in, - - // output responses - output wire [NUM_REQS-1:0] rsp_valid_out, - output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out, - output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_out, - input wire [NUM_REQS-1:0] rsp_ready_out -); - localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH; - localparam RSP_DATAW = TAG_IN_WIDTH + DATA_WIDTH; - - if (NUM_REQS > 1) begin - - wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in_merged; - - for (genvar i = 0; i < NUM_REQS; i++) begin - wire [TAG_OUT_WIDTH-1:0] req_tag_in_w; - - VX_bits_insert #( - .N (TAG_IN_WIDTH), - .S (LOG_NUM_REQS), - .POS (TAG_SEL_IDX) - ) bits_insert ( - .data_in (req_tag_in[i]), - .sel_in (LOG_NUM_REQS'(i)), - .data_out (req_tag_in_w) - ); - - assign req_data_in_merged[i] = {req_tag_in_w, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]}; - end - - VX_stream_arbiter #( - .NUM_REQS (NUM_REQS), - .DATAW (REQ_DATAW), - .BUFFERED (BUFFERED_REQ), - .TYPE (TYPE) - ) req_arb ( - .clk (clk), - .reset (reset), - .valid_in (req_valid_in), - .data_in (req_data_in_merged), - .ready_in (req_ready_in), - .valid_out (req_valid_out), - .data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}), - .ready_out (req_ready_out) - ); - - /////////////////////////////////////////////////////////////////////// - - wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out_merged; - - wire [LOG_NUM_REQS-1:0] rsp_sel = rsp_tag_in[TAG_SEL_IDX +: LOG_NUM_REQS]; - - wire [TAG_IN_WIDTH-1:0] rsp_tag_in_w; - - VX_bits_remove #( - .N (TAG_OUT_WIDTH), - .S (LOG_NUM_REQS), - .POS (TAG_SEL_IDX) - ) bits_remove ( - .data_in (rsp_tag_in), - .data_out (rsp_tag_in_w) - ); - - VX_stream_demux #( - .NUM_REQS (NUM_REQS), - .DATAW (RSP_DATAW), - .BUFFERED (BUFFERED_RSP) - ) rsp_demux ( - .clk (clk), - .reset (reset), - .sel_in (rsp_sel), - .valid_in (rsp_valid_in), - .data_in ({rsp_tag_in_w, rsp_data_in}), - .ready_in (rsp_ready_in), - .valid_out (rsp_valid_out), - .data_out (rsp_data_out_merged), - .ready_out (rsp_ready_out) - ); - - for (genvar i = 0; i < NUM_REQS; i++) begin - assign {rsp_tag_out[i], rsp_data_out[i]} = rsp_data_out_merged[i]; - end - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - assign req_valid_out = req_valid_in; - assign req_tag_out = req_tag_in; - assign req_addr_out = req_addr_in; - assign req_rw_out = req_rw_in; - assign req_byteen_out = req_byteen_in; - assign req_data_out = req_data_in; - assign req_ready_in = req_ready_out; - - assign rsp_valid_out = rsp_valid_in; - assign rsp_tag_out = rsp_tag_in; - assign rsp_data_out = rsp_data_in; - assign rsp_ready_in = rsp_ready_out; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_mem_unit.sv b/hw/rtl/VX_mem_unit.sv deleted file mode 100644 index ade9600f..00000000 --- a/hw/rtl/VX_mem_unit.sv +++ /dev/null @@ -1,420 +0,0 @@ -`include "VX_define.vh" - -module VX_mem_unit # ( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_mem_unit - - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE - VX_perf_memsys_if.master perf_memsys_if, -`endif - - // Core <-> Dcache - VX_dcache_req_if.slave dcache_req_if, - VX_dcache_rsp_if.master dcache_rsp_if, - - // Core <-> Icache - VX_icache_req_if.slave icache_req_if, - VX_icache_rsp_if.master icache_rsp_if, - - // Memory - VX_mem_req_if.master mem_req_if, - VX_mem_rsp_if.slave mem_rsp_if -); - -`ifdef PERF_ENABLE - VX_perf_cache_if perf_icache_if(), perf_dcache_if(), perf_smem_if(); -`endif - - VX_mem_req_if #( - .DATA_WIDTH (`ICACHE_MEM_DATA_WIDTH), - .ADDR_WIDTH (`ICACHE_MEM_ADDR_WIDTH), - .TAG_WIDTH (`ICACHE_MEM_TAG_WIDTH) - ) icache_mem_req_if(); - - VX_mem_rsp_if #( - .DATA_WIDTH (`ICACHE_MEM_DATA_WIDTH), - .TAG_WIDTH (`ICACHE_MEM_TAG_WIDTH) - ) icache_mem_rsp_if(); - - VX_mem_req_if #( - .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), - .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), - .TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH) - ) dcache_mem_req_if(); - - VX_mem_rsp_if #( - .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), - .TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH) - ) dcache_mem_rsp_if(); - - VX_dcache_req_if #( - .NUM_REQS (`DCACHE_NUM_REQS), - .WORD_SIZE (`DCACHE_WORD_SIZE), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) - ) dcache_req_tmp_if(); - - VX_dcache_rsp_if #( - .NUM_REQS (`DCACHE_NUM_REQS), - .WORD_SIZE (`DCACHE_WORD_SIZE), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) - ) dcache_rsp_tmp_if(); - - `RESET_RELAY (icache_reset); - `RESET_RELAY (dcache_reset); - `RESET_RELAY (mem_arb_reset); - - VX_cache #( - .CACHE_ID (`ICACHE_ID), - .CACHE_SIZE (`ICACHE_SIZE), - .CACHE_LINE_SIZE (`ICACHE_LINE_SIZE), - .NUM_BANKS (1), - .WORD_SIZE (`ICACHE_WORD_SIZE), - .NUM_REQS (1), - .CREQ_SIZE (`ICACHE_CREQ_SIZE), - .CRSQ_SIZE (`ICACHE_CRSQ_SIZE), - .MSHR_SIZE (`ICACHE_MSHR_SIZE), - .MRSQ_SIZE (`ICACHE_MRSQ_SIZE), - .MREQ_SIZE (`ICACHE_MREQ_SIZE), - .WRITE_ENABLE (0), - .CORE_TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`ICACHE_CORE_TAG_ID_BITS), - .MEM_TAG_WIDTH (`ICACHE_MEM_TAG_WIDTH) - ) icache ( - `SCOPE_BIND_VX_mem_unit_icache - - .clk (clk), - .reset (icache_reset), - - // Core request - .core_req_valid (icache_req_if.valid), - .core_req_rw (1'b0), - .core_req_byteen ('b0), - .core_req_addr (icache_req_if.addr), - .core_req_data ('x), - .core_req_tag (icache_req_if.tag), - .core_req_ready (icache_req_if.ready), - - // Core response - .core_rsp_valid (icache_rsp_if.valid), - .core_rsp_data (icache_rsp_if.data), - .core_rsp_tag (icache_rsp_if.tag), - .core_rsp_ready (icache_rsp_if.ready), - `UNUSED_PIN (core_rsp_tmask), - - `ifdef PERF_ENABLE - .perf_cache_if (perf_icache_if), - `endif - - // Memory Request - .mem_req_valid (icache_mem_req_if.valid), - .mem_req_rw (icache_mem_req_if.rw), - .mem_req_byteen (icache_mem_req_if.byteen), - .mem_req_addr (icache_mem_req_if.addr), - .mem_req_data (icache_mem_req_if.data), - .mem_req_tag (icache_mem_req_if.tag), - .mem_req_ready (icache_mem_req_if.ready), - - // Memory response - .mem_rsp_valid (icache_mem_rsp_if.valid), - .mem_rsp_data (icache_mem_rsp_if.data), - .mem_rsp_tag (icache_mem_rsp_if.tag), - .mem_rsp_ready (icache_mem_rsp_if.ready) - ); - - VX_cache #( - .CACHE_ID (`DCACHE_ID), - .CACHE_SIZE (`DCACHE_SIZE), - .CACHE_LINE_SIZE (`DCACHE_LINE_SIZE), - .NUM_BANKS (`DCACHE_NUM_BANKS), - .NUM_PORTS (`DCACHE_NUM_PORTS), - .WORD_SIZE (`DCACHE_WORD_SIZE), - .NUM_REQS (`DCACHE_NUM_REQS), - .CREQ_SIZE (`DCACHE_CREQ_SIZE), - .CRSQ_SIZE (`DCACHE_CRSQ_SIZE), - .MSHR_SIZE (`DCACHE_MSHR_SIZE), - .MRSQ_SIZE (`DCACHE_MRSQ_SIZE), - .MREQ_SIZE (`DCACHE_MREQ_SIZE), - .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE), - .CORE_TAG_ID_BITS (`DCACHE_CORE_TAG_ID_BITS-`SM_ENABLE), - .MEM_TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH), - .NC_ENABLE (1) - ) dcache ( - `SCOPE_BIND_VX_mem_unit_dcache - - .clk (clk), - .reset (dcache_reset), - - // Core req - .core_req_valid (dcache_req_tmp_if.valid), - .core_req_rw (dcache_req_tmp_if.rw), - .core_req_byteen (dcache_req_tmp_if.byteen), - .core_req_addr (dcache_req_tmp_if.addr), - .core_req_data (dcache_req_tmp_if.data), - .core_req_tag (dcache_req_tmp_if.tag), - .core_req_ready (dcache_req_tmp_if.ready), - - // Core response - .core_rsp_valid (dcache_rsp_tmp_if.valid), - .core_rsp_tmask (dcache_rsp_tmp_if.tmask), - .core_rsp_data (dcache_rsp_tmp_if.data), - .core_rsp_tag (dcache_rsp_tmp_if.tag), - .core_rsp_ready (dcache_rsp_tmp_if.ready), - - `ifdef PERF_ENABLE - .perf_cache_if (perf_dcache_if), - `endif - - // Memory request - .mem_req_valid (dcache_mem_req_if.valid), - .mem_req_rw (dcache_mem_req_if.rw), - .mem_req_byteen (dcache_mem_req_if.byteen), - .mem_req_addr (dcache_mem_req_if.addr), - .mem_req_data (dcache_mem_req_if.data), - .mem_req_tag (dcache_mem_req_if.tag), - .mem_req_ready (dcache_mem_req_if.ready), - - // Memory response - .mem_rsp_valid (dcache_mem_rsp_if.valid), - .mem_rsp_data (dcache_mem_rsp_if.data), - .mem_rsp_tag (dcache_mem_rsp_if.tag), - .mem_rsp_ready (dcache_mem_rsp_if.ready) - ); - - if (`SM_ENABLE) begin - VX_dcache_req_if #( - .NUM_REQS (`DCACHE_NUM_REQS), - .WORD_SIZE (`DCACHE_WORD_SIZE), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) - ) smem_req_if(); - - VX_dcache_rsp_if #( - .NUM_REQS (`DCACHE_NUM_REQS), - .WORD_SIZE (`DCACHE_WORD_SIZE), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE) - ) smem_rsp_if(); - - `RESET_RELAY (smem_arb_reset); - `RESET_RELAY (smem_reset); - - VX_smem_arb #( - .NUM_REQS (2), - .LANES (`NUM_THREADS), - .DATA_SIZE (4), - .TAG_IN_WIDTH (`DCACHE_CORE_TAG_WIDTH), - .TAG_SEL_IDX (0), // SM flag - .TYPE ("P"), - .BUFFERED_REQ (2), - .BUFFERED_RSP (1) - ) smem_arb ( - .clk (clk), - .reset (smem_arb_reset), - - // input request - .req_valid_in (dcache_req_if.valid), - .req_rw_in (dcache_req_if.rw), - .req_byteen_in (dcache_req_if.byteen), - .req_addr_in (dcache_req_if.addr), - .req_data_in (dcache_req_if.data), - .req_tag_in (dcache_req_if.tag), - .req_ready_in (dcache_req_if.ready), - - // output requests - .req_valid_out ({smem_req_if.valid, dcache_req_tmp_if.valid}), - .req_rw_out ({smem_req_if.rw, dcache_req_tmp_if.rw}), - .req_byteen_out ({smem_req_if.byteen, dcache_req_tmp_if.byteen}), - .req_addr_out ({smem_req_if.addr, dcache_req_tmp_if.addr}), - .req_data_out ({smem_req_if.data, dcache_req_tmp_if.data}), - .req_tag_out ({smem_req_if.tag, dcache_req_tmp_if.tag}), - .req_ready_out ({smem_req_if.ready, dcache_req_tmp_if.ready}), - - // input responses - .rsp_valid_in ({smem_rsp_if.valid, dcache_rsp_tmp_if.valid}), - .rsp_tmask_in ({smem_rsp_if.tmask, dcache_rsp_tmp_if.tmask}), - .rsp_data_in ({smem_rsp_if.data, dcache_rsp_tmp_if.data}), - .rsp_tag_in ({smem_rsp_if.tag, dcache_rsp_tmp_if.tag}), - .rsp_ready_in ({smem_rsp_if.ready, dcache_rsp_tmp_if.ready}), - - // output response - .rsp_valid_out (dcache_rsp_if.valid), - .rsp_tmask_out (dcache_rsp_if.tmask), - .rsp_tag_out (dcache_rsp_if.tag), - .rsp_data_out (dcache_rsp_if.data), - .rsp_ready_out (dcache_rsp_if.ready) - ); - - VX_shared_mem #( - .CACHE_ID (`SMEM_ID), - .CACHE_SIZE (`SMEM_SIZE), - .NUM_BANKS (`SMEM_NUM_BANKS), - .WORD_SIZE (`SMEM_WORD_SIZE), - .NUM_REQS (`SMEM_NUM_REQS), - .CREQ_SIZE (`SMEM_CREQ_SIZE), - .CRSQ_SIZE (`SMEM_CRSQ_SIZE), - .CORE_TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH-`SM_ENABLE), - .CORE_TAG_ID_BITS (`DCACHE_CORE_TAG_ID_BITS-`SM_ENABLE), - .BANK_ADDR_OFFSET (`SMEM_BANK_ADDR_OFFSET) - ) smem ( - .clk (clk), - .reset (smem_reset), - - `ifdef PERF_ENABLE - .perf_cache_if (perf_smem_if), - `endif - - // Core request - .core_req_valid (smem_req_if.valid), - .core_req_rw (smem_req_if.rw), - .core_req_byteen (smem_req_if.byteen), - .core_req_addr (smem_req_if.addr), - .core_req_data (smem_req_if.data), - .core_req_tag (smem_req_if.tag), - .core_req_ready (smem_req_if.ready), - - // Core response - .core_rsp_valid (smem_rsp_if.valid), - .core_rsp_tmask (smem_rsp_if.tmask), - .core_rsp_data (smem_rsp_if.data), - .core_rsp_tag (smem_rsp_if.tag), - .core_rsp_ready (smem_rsp_if.ready) - ); - end else begin - // core to D-cache request - for (genvar i = 0; i < `DCACHE_NUM_REQS; ++i) begin - VX_skid_buffer #( - .DATAW ((32-`CLOG2(`DCACHE_WORD_SIZE)) + 1 + `DCACHE_WORD_SIZE + (8*`DCACHE_WORD_SIZE) + `DCACHE_CORE_TAG_WIDTH) - ) req_buf ( - .clk (clk), - .reset (reset), - .valid_in (dcache_req_if.valid[i]), - .data_in ({dcache_req_if.addr[i], dcache_req_if.rw[i], dcache_req_if.byteen[i], dcache_req_if.data[i], dcache_req_if.tag[i]}), - .ready_in (dcache_req_if.ready[i]), - .valid_out (dcache_req_tmp_if.valid[i]), - .data_out ({dcache_req_tmp_if.addr[i], dcache_req_tmp_if.rw[i], dcache_req_tmp_if.byteen[i], dcache_req_tmp_if.data[i], dcache_req_tmp_if.tag[i]}), - .ready_out (dcache_req_tmp_if.ready[i]) - ); - end - - // D-cache to core reponse - assign dcache_rsp_if.valid = dcache_rsp_tmp_if.valid; - assign dcache_rsp_if.tmask = dcache_rsp_tmp_if.tmask; - assign dcache_rsp_if.tag = dcache_rsp_tmp_if.tag; - assign dcache_rsp_if.data = dcache_rsp_tmp_if.data; - assign dcache_rsp_tmp_if.ready = dcache_rsp_if.ready; - end - - wire [`DCACHE_MEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DCACHE_MEM_TAG_WIDTH'(icache_mem_req_if.tag); - wire [`DCACHE_MEM_TAG_WIDTH-1:0] icache_mem_rsp_tag; - assign icache_mem_rsp_if.tag = icache_mem_rsp_tag[`ICACHE_MEM_TAG_WIDTH-1:0]; - `UNUSED_VAR (icache_mem_rsp_tag) - - VX_mem_arb #( - .NUM_REQS (2), - .DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH), - .ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`DCACHE_MEM_TAG_WIDTH), - .TYPE ("R"), - .TAG_SEL_IDX (1), // Skip 0 for NC flag - .BUFFERED_REQ (1), - .BUFFERED_RSP (2) - ) mem_arb ( - .clk (clk), - .reset (mem_arb_reset), - - // Source request - .req_valid_in ({dcache_mem_req_if.valid, icache_mem_req_if.valid}), - .req_rw_in ({dcache_mem_req_if.rw, icache_mem_req_if.rw}), - .req_byteen_in ({dcache_mem_req_if.byteen, icache_mem_req_if.byteen}), - .req_addr_in ({dcache_mem_req_if.addr, icache_mem_req_if.addr}), - .req_data_in ({dcache_mem_req_if.data, icache_mem_req_if.data}), - .req_tag_in ({dcache_mem_req_if.tag, icache_mem_req_tag}), - .req_ready_in ({dcache_mem_req_if.ready, icache_mem_req_if.ready}), - - // Memory request - .req_valid_out (mem_req_if.valid), - .req_rw_out (mem_req_if.rw), - .req_byteen_out (mem_req_if.byteen), - .req_addr_out (mem_req_if.addr), - .req_data_out (mem_req_if.data), - .req_tag_out (mem_req_if.tag), - .req_ready_out (mem_req_if.ready), - - // Source response - .rsp_valid_out ({dcache_mem_rsp_if.valid, icache_mem_rsp_if.valid}), - .rsp_data_out ({dcache_mem_rsp_if.data, icache_mem_rsp_if.data}), - .rsp_tag_out ({dcache_mem_rsp_if.tag, icache_mem_rsp_tag}), - .rsp_ready_out ({dcache_mem_rsp_if.ready, icache_mem_rsp_if.ready}), - - // Memory response - .rsp_valid_in (mem_rsp_if.valid), - .rsp_tag_in (mem_rsp_if.tag), - .rsp_data_in (mem_rsp_if.data), - .rsp_ready_in (mem_rsp_if.ready) - ); - -`ifdef PERF_ENABLE - - `UNUSED_VAR (perf_dcache_if.mem_stalls) - `UNUSED_VAR (perf_dcache_if.crsp_stalls) - - assign perf_memsys_if.icache_reads = perf_icache_if.reads; - assign perf_memsys_if.icache_read_misses = perf_icache_if.read_misses; - assign perf_memsys_if.dcache_reads = perf_dcache_if.reads; - assign perf_memsys_if.dcache_writes = perf_dcache_if.writes; - assign perf_memsys_if.dcache_read_misses = perf_dcache_if.read_misses; - assign perf_memsys_if.dcache_write_misses= perf_dcache_if.write_misses; - assign perf_memsys_if.dcache_bank_stalls = perf_dcache_if.bank_stalls; - assign perf_memsys_if.dcache_mshr_stalls = perf_dcache_if.mshr_stalls; - -if (`SM_ENABLE) begin - assign perf_memsys_if.smem_reads = perf_smem_if.reads; - assign perf_memsys_if.smem_writes = perf_smem_if.writes; - assign perf_memsys_if.smem_bank_stalls = perf_smem_if.bank_stalls; -end else begin - assign perf_memsys_if.smem_reads = 0; - assign perf_memsys_if.smem_writes = 0; - assign perf_memsys_if.smem_bank_stalls = 0; -end - - reg [`PERF_CTR_BITS-1:0] perf_mem_pending_reads; - - always @(posedge clk) begin - if (reset) begin - perf_mem_pending_reads <= 0; - end else begin - perf_mem_pending_reads <= perf_mem_pending_reads + - `PERF_CTR_BITS'($signed(2'((mem_req_if.valid && mem_req_if.ready && !mem_req_if.rw) && !(mem_rsp_if.valid && mem_rsp_if.ready)) - - 2'((mem_rsp_if.valid && mem_rsp_if.ready) && !(mem_req_if.valid && mem_req_if.ready && !mem_req_if.rw)))); - end - end - - reg [`PERF_CTR_BITS-1:0] perf_mem_reads; - reg [`PERF_CTR_BITS-1:0] perf_mem_writes; - reg [`PERF_CTR_BITS-1:0] perf_mem_lat; - - always @(posedge clk) begin - if (reset) begin - perf_mem_reads <= 0; - perf_mem_writes <= 0; - perf_mem_lat <= 0; - end else begin - if (mem_req_if.valid && mem_req_if.ready && !mem_req_if.rw) begin - perf_mem_reads <= perf_mem_reads + `PERF_CTR_BITS'd1; - end - if (mem_req_if.valid && mem_req_if.ready && mem_req_if.rw) begin - perf_mem_writes <= perf_mem_writes + `PERF_CTR_BITS'd1; - end - perf_mem_lat <= perf_mem_lat + perf_mem_pending_reads; - end - end - - assign perf_memsys_if.mem_reads = perf_mem_reads; - assign perf_memsys_if.mem_writes = perf_mem_writes; - assign perf_memsys_if.mem_latency = perf_mem_lat; -`endif - -endmodule diff --git a/hw/rtl/VX_muldiv.sv b/hw/rtl/VX_muldiv.sv deleted file mode 100644 index ea992825..00000000 --- a/hw/rtl/VX_muldiv.sv +++ /dev/null @@ -1,226 +0,0 @@ -`include "VX_define.vh" - -module VX_muldiv ( - input wire clk, - input wire reset, - - // Inputs - input wire [`INST_MUL_BITS-1:0] alu_op, - input wire [`UUID_BITS-1:0] uuid_in, - input wire [`NW_BITS-1:0] wid_in, - input wire [`NUM_THREADS-1:0] tmask_in, - input wire [31:0] PC_in, - input wire [`NR_BITS-1:0] rd_in, - input wire wb_in, - input wire [`NUM_THREADS-1:0][31:0] alu_in1, - input wire [`NUM_THREADS-1:0][31:0] alu_in2, - - // Outputs - output wire [`UUID_BITS-1:0] uuid_out, - output wire [`NW_BITS-1:0] wid_out, - output wire [`NUM_THREADS-1:0] tmask_out, - output wire [31:0] PC_out, - output wire [`NR_BITS-1:0] rd_out, - output wire wb_out, - output wire [`NUM_THREADS-1:0][31:0] data_out, - - // handshake - input wire valid_in, - output wire ready_in, - output wire valid_out, - input wire ready_out -); - - wire is_div_op = `INST_MUL_IS_DIV(alu_op); - - wire [`NUM_THREADS-1:0][31:0] mul_result; - wire [`UUID_BITS-1:0] mul_uuid_out; - wire [`NW_BITS-1:0] mul_wid_out; - wire [`NUM_THREADS-1:0] mul_tmask_out; - wire [31:0] mul_PC_out; - wire [`NR_BITS-1:0] mul_rd_out; - wire mul_wb_out; - - wire stall_out; - - wire mul_valid_out; - wire mul_valid_in = valid_in && !is_div_op; - wire mul_ready_in = ~stall_out || ~mul_valid_out; - - wire is_mulh_in = (alu_op != `INST_MUL_MUL); - wire is_signed_mul_a = (alu_op != `INST_MUL_MULHU); - wire is_signed_mul_b = (alu_op != `INST_MUL_MULHU && alu_op != `INST_MUL_MULHSU); - -`ifdef IMUL_DPI - - wire [`NUM_THREADS-1:0][31:0] mul_result_tmp; - - wire mul_fire_in = mul_valid_in && mul_ready_in; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [31:0] mul_resultl, mul_resulth; - always @(*) begin - dpi_imul (mul_fire_in, alu_in1[i], alu_in2[i], is_signed_mul_a, is_signed_mul_b, mul_resultl, mul_resulth); - end - assign mul_result_tmp[i] = is_mulh_in ? mul_resulth : mul_resultl; - end - - VX_shift_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)), - .DEPTH (`LATENCY_IMUL), - .RESETW (1) - ) mul_shift_reg ( - .clk(clk), - .reset (reset), - .enable (mul_ready_in), - .data_in ({mul_valid_in, uuid_in, wid_in, tmask_in, PC_in, rd_in, wb_in, mul_result_tmp}), - .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_result}) - ); - -`else - - wire is_mulh_out; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [32:0] mul_in1 = {is_signed_mul_a & alu_in1[i][31], alu_in1[i]}; - wire [32:0] mul_in2 = {is_signed_mul_b & alu_in2[i][31], alu_in2[i]}; - `IGNORE_UNUSED_BEGIN - wire [65:0] mul_result_tmp; - `IGNORE_UNUSED_END - - VX_multiplier #( - .WIDTHA (33), - .WIDTHB (33), - .WIDTHP (66), - .SIGNED (1), - .LATENCY (`LATENCY_IMUL) - ) multiplier ( - .clk (clk), - .enable (mul_ready_in), - .dataa (mul_in1), - .datab (mul_in2), - .result (mul_result_tmp) - ); - - assign mul_result[i] = is_mulh_out ? mul_result_tmp[63:32] : mul_result_tmp[31:0]; - end - - VX_shift_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1), - .DEPTH (`LATENCY_IMUL), - .RESETW (1) - ) mul_shift_reg ( - .clk(clk), - .reset (reset), - .enable (mul_ready_in), - .data_in ({mul_valid_in, uuid_in, wid_in, tmask_in, PC_in, rd_in, wb_in, is_mulh_in}), - .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out}) - ); - -`endif - - /////////////////////////////////////////////////////////////////////////// - - wire [`NUM_THREADS-1:0][31:0] div_result; - wire [`UUID_BITS-1:0] div_uuid_out; - wire [`NW_BITS-1:0] div_wid_out; - wire [`NUM_THREADS-1:0] div_tmask_out; - wire [31:0] div_PC_out; - wire [`NR_BITS-1:0] div_rd_out; - wire div_wb_out; - - wire is_rem_op_in = (alu_op == `INST_MUL_REM) || (alu_op == `INST_MUL_REMU); - wire is_signed_div = (alu_op == `INST_MUL_DIV) || (alu_op == `INST_MUL_REM); - wire div_valid_in = valid_in && is_div_op; - wire div_ready_out = ~stall_out && ~mul_valid_out; // arbitration prioritizes MUL - wire div_ready_in; - wire div_valid_out; - -`ifdef IDIV_DPI - - wire [`NUM_THREADS-1:0][31:0] div_result_tmp; - - wire div_fire_in = div_valid_in && div_ready_in; - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [31:0] div_quotient, div_remainder; - always @(*) begin - dpi_idiv (div_fire_in, alu_in1[i], alu_in2[i], is_signed_div, div_quotient, div_remainder); - end - assign div_result_tmp[i] = is_rem_op_in ? div_remainder : div_quotient; - end - - VX_shift_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)), - .DEPTH (`LATENCY_IMUL), - .RESETW (1) - ) div_shift_reg ( - .clk(clk), - .reset (reset), - .enable (div_ready_in), - .data_in ({div_valid_in, uuid_in, wid_in, tmask_in, PC_in, rd_in, wb_in, div_result_tmp}), - .data_out ({div_valid_out, div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, div_result}) - ); - - assign div_ready_in = div_ready_out || ~div_valid_out; - -`else - - wire [`NUM_THREADS-1:0][31:0] div_result_tmp, rem_result_tmp; - wire is_rem_op_out; - - VX_serial_div #( - .WIDTHN (32), - .WIDTHD (32), - .WIDTHQ (32), - .WIDTHR (32), - .LANES (`NUM_THREADS), - .TAGW (64 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1) - ) divide ( - .clk (clk), - .reset (reset), - .valid_in (div_valid_in), - .ready_in (div_ready_in), - .signed_mode(is_signed_div), - .tag_in ({uuid_in, wid_in, tmask_in, PC_in, rd_in, wb_in, is_rem_op_in}), - .numer (alu_in1), - .denom (alu_in2), - .quotient (div_result_tmp), - .remainder (rem_result_tmp), - .ready_out (div_ready_out), - .valid_out (div_valid_out), - .tag_out ({div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out}) - ); - - assign div_result = is_rem_op_out ? rem_result_tmp : div_result_tmp; - -`endif - - /////////////////////////////////////////////////////////////////////////// - - wire rsp_valid = mul_valid_out || div_valid_out; - wire [`UUID_BITS-1:0] rsp_uuid = mul_valid_out ? mul_uuid_out : div_uuid_out; - wire [`NW_BITS-1:0] rsp_wid = mul_valid_out ? mul_wid_out : div_wid_out; - wire [`NUM_THREADS-1:0] rsp_tmask = mul_valid_out ? mul_tmask_out : div_tmask_out; - wire [31:0] rsp_PC = mul_valid_out ? mul_PC_out : div_PC_out; - wire [`NR_BITS-1:0] rsp_rd = mul_valid_out ? mul_rd_out : div_rd_out; - wire rsp_wb = mul_valid_out ? mul_wb_out : div_wb_out; - wire [`NUM_THREADS-1:0][31:0] rsp_data = mul_valid_out ? mul_result : div_result; - - assign stall_out = ~ready_out && valid_out; - - VX_pipe_register #( - .DATAW (1 + `UUID_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (~stall_out), - .data_in ({rsp_valid, rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}), - .data_out ({valid_out, uuid_out, wid_out, tmask_out, PC_out, rd_out, wb_out, data_out}) - ); - - // can accept new request? - assign ready_in = is_div_op ? div_ready_in : mul_ready_in; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_pipeline.sv b/hw/rtl/VX_pipeline.sv deleted file mode 100644 index 1ab20c4a..00000000 --- a/hw/rtl/VX_pipeline.sv +++ /dev/null @@ -1,261 +0,0 @@ -`include "VX_define.vh" - -module VX_pipeline #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_pipeline - - // Clock - input wire clk, - input wire reset, - - // Dcache core request - output wire [`NUM_THREADS-1:0] dcache_req_valid, - output wire [`NUM_THREADS-1:0] dcache_req_rw, - output wire [`NUM_THREADS-1:0][3:0] dcache_req_byteen, - output wire [`NUM_THREADS-1:0][29:0] dcache_req_addr, - output wire [`NUM_THREADS-1:0][31:0] dcache_req_data, - output wire [`NUM_THREADS-1:0][`DCACHE_CORE_TAG_WIDTH-1:0] dcache_req_tag, - input wire [`NUM_THREADS-1:0] dcache_req_ready, - - // Dcache core reponse - input wire dcache_rsp_valid, - input wire [`NUM_THREADS-1:0] dcache_rsp_tmask, - input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data, - input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag, - output wire dcache_rsp_ready, - - // Icache core request - output wire icache_req_valid, - output wire [29:0] icache_req_addr, - output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag, - input wire icache_req_ready, - - // Icache core response - input wire icache_rsp_valid, - input wire [31:0] icache_rsp_data, - input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag, - output wire icache_rsp_ready, - -`ifdef PERF_ENABLE - VX_perf_memsys_if.slave perf_memsys_if, -`endif - - // Status - output wire busy -); - // - // Dcache request - // - - VX_dcache_req_if #( - .NUM_REQS (`NUM_THREADS), - .WORD_SIZE (4), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) - ) dcache_req_if(); - - assign dcache_req_valid = dcache_req_if.valid; - assign dcache_req_rw = dcache_req_if.rw; - assign dcache_req_byteen = dcache_req_if.byteen; - assign dcache_req_addr = dcache_req_if.addr; - assign dcache_req_data = dcache_req_if.data; - assign dcache_req_tag = dcache_req_if.tag; - assign dcache_req_if.ready = dcache_req_ready; - - // - // Dcache response - // - - VX_dcache_rsp_if #( - .NUM_REQS (`NUM_THREADS), - .WORD_SIZE (4), - .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH) - ) dcache_rsp_if(); - - assign dcache_rsp_if.valid = dcache_rsp_valid; - assign dcache_rsp_if.tmask = dcache_rsp_tmask; - assign dcache_rsp_if.data = dcache_rsp_data; - assign dcache_rsp_if.tag = dcache_rsp_tag; - assign dcache_rsp_ready = dcache_rsp_if.ready; - - // - // Icache request - // - - VX_icache_req_if #( - .WORD_SIZE (4), - .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) - ) icache_req_if(); - - assign icache_req_valid = icache_req_if.valid; - assign icache_req_addr = icache_req_if.addr; - assign icache_req_tag = icache_req_if.tag; - assign icache_req_if.ready = icache_req_ready; - - // - // Icache response - // - - VX_icache_rsp_if #( - .WORD_SIZE (4), - .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH) - ) icache_rsp_if(); - - assign icache_rsp_if.valid = icache_rsp_valid; - assign icache_rsp_if.data = icache_rsp_data; - assign icache_rsp_if.tag = icache_rsp_tag; - assign icache_rsp_ready = icache_rsp_if.ready; - - /////////////////////////////////////////////////////////////////////////// - - VX_fetch_to_csr_if fetch_to_csr_if(); - VX_cmt_to_csr_if cmt_to_csr_if(); - VX_decode_if decode_if(); - VX_branch_ctl_if branch_ctl_if(); - VX_warp_ctl_if warp_ctl_if(); - VX_ifetch_rsp_if ifetch_rsp_if(); - VX_alu_req_if alu_req_if(); - VX_lsu_req_if lsu_req_if(); - VX_csr_req_if csr_req_if(); -`ifdef EXT_F_ENABLE - VX_fpu_req_if fpu_req_if(); -`endif - VX_gpu_req_if gpu_req_if(); - VX_writeback_if writeback_if(); - VX_wstall_if wstall_if(); - VX_join_if join_if(); - VX_commit_if alu_commit_if(); - VX_commit_if ld_commit_if(); - VX_commit_if st_commit_if(); - VX_commit_if csr_commit_if(); -`ifdef EXT_F_ENABLE - VX_commit_if fpu_commit_if(); -`endif - VX_commit_if gpu_commit_if(); - -`ifdef PERF_ENABLE - VX_perf_pipeline_if perf_pipeline_if(); -`endif - - `RESET_RELAY (fetch_reset); - `RESET_RELAY (decode_reset); - `RESET_RELAY (issue_reset); - `RESET_RELAY (execute_reset); - `RESET_RELAY (commit_reset); - - VX_fetch #( - .CORE_ID(CORE_ID) - ) fetch ( - `SCOPE_BIND_VX_pipeline_fetch - .clk (clk), - .reset (fetch_reset), - .icache_req_if (icache_req_if), - .icache_rsp_if (icache_rsp_if), - .wstall_if (wstall_if), - .join_if (join_if), - .warp_ctl_if (warp_ctl_if), - .branch_ctl_if (branch_ctl_if), - .ifetch_rsp_if (ifetch_rsp_if), - .fetch_to_csr_if(fetch_to_csr_if), - .busy (busy) - ); - - VX_decode #( - .CORE_ID(CORE_ID) - ) decode ( - .clk (clk), - .reset (decode_reset), - `ifdef PERF_ENABLE - .perf_decode_if (perf_pipeline_if.decode), - `endif - .ifetch_rsp_if (ifetch_rsp_if), - .decode_if (decode_if), - .wstall_if (wstall_if), - .join_if (join_if) - ); - - VX_issue #( - .CORE_ID(CORE_ID) - ) issue ( - `SCOPE_BIND_VX_pipeline_issue - - .clk (clk), - .reset (issue_reset), - - `ifdef PERF_ENABLE - .perf_issue_if (perf_pipeline_if.issue), - `endif - - .decode_if (decode_if), - .writeback_if (writeback_if), - - .alu_req_if (alu_req_if), - .lsu_req_if (lsu_req_if), - .csr_req_if (csr_req_if), - `ifdef EXT_F_ENABLE - .fpu_req_if (fpu_req_if), - `endif - .gpu_req_if (gpu_req_if) - ); - - VX_execute #( - .CORE_ID(CORE_ID) - ) execute ( - `SCOPE_BIND_VX_pipeline_execute - - .clk (clk), - .reset (execute_reset), - - `ifdef PERF_ENABLE - .perf_memsys_if (perf_memsys_if), - .perf_pipeline_if (perf_pipeline_if), - `endif - - .dcache_req_if (dcache_req_if), - .dcache_rsp_if (dcache_rsp_if), - - .cmt_to_csr_if (cmt_to_csr_if), - .fetch_to_csr_if(fetch_to_csr_if), - - .alu_req_if (alu_req_if), - .lsu_req_if (lsu_req_if), - .csr_req_if (csr_req_if), - `ifdef EXT_F_ENABLE - .fpu_req_if (fpu_req_if), - `endif - .gpu_req_if (gpu_req_if), - - .warp_ctl_if (warp_ctl_if), - .branch_ctl_if (branch_ctl_if), - .alu_commit_if (alu_commit_if), - .ld_commit_if (ld_commit_if), - .st_commit_if (st_commit_if), - .csr_commit_if (csr_commit_if), - `ifdef EXT_F_ENABLE - .fpu_commit_if (fpu_commit_if), - `endif - .gpu_commit_if (gpu_commit_if), - - .busy (busy) - ); - - VX_commit #( - .CORE_ID(CORE_ID) - ) commit ( - .clk (clk), - .reset (commit_reset), - - .alu_commit_if (alu_commit_if), - .ld_commit_if (ld_commit_if), - .st_commit_if (st_commit_if), - .csr_commit_if (csr_commit_if), - `ifdef EXT_F_ENABLE - .fpu_commit_if (fpu_commit_if), - `endif - .gpu_commit_if (gpu_commit_if), - - .writeback_if (writeback_if), - .cmt_to_csr_if (cmt_to_csr_if) - ); - -endmodule diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 908428b7..923ffa12 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -1,5 +1,18 @@ -`ifndef VX_PLATFORM -`define VX_PLATFORM +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_PLATFORM_VH +`define VX_PLATFORM_VH `ifndef SYNTHESIS `include "util_dpi.vh" @@ -9,8 +22,36 @@ /////////////////////////////////////////////////////////////////////////////// -`ifndef SYNTHESIS +`ifdef VIVADO +`define STRING +`else +`define STRING string +`endif +`ifdef SYNTHESIS +`define TRACING_ON +`define TRACING_OFF +`ifndef NDEBUG + `define DEBUG_BLOCK(x) x +`else + `define DEBUG_BLOCK(x) +`endif +`define IGNORE_UNOPTFLAT_BEGIN +`define IGNORE_UNOPTFLAT_END +`define IGNORE_UNUSED_BEGIN +`define IGNORE_UNUSED_END +`define IGNORE_WARNINGS_BEGIN +`define IGNORE_WARNINGS_END +`define UNUSED_PARAM(x) +`define UNUSED_SPARAM(x) +`define UNUSED_VAR(x) +`define UNUSED_PIN(x) . x () +`define UNUSED_ARG(x) x +`define TRACE(level, args) $write args +`else +`ifdef VERILATOR +`define TRACING_ON /* verilator tracing_on */ +`define TRACING_OFF /* verilator tracing_off */ `ifndef NDEBUG `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \ x \ @@ -19,6 +60,10 @@ `define DEBUG_BLOCK(x) `endif +`define IGNORE_UNOPTFLAT_BEGIN /* verilator lint_off UNOPTFLAT */ + +`define IGNORE_UNOPTFLAT_END /* verilator lint_off UNOPTFLAT */ + `define IGNORE_UNUSED_BEGIN /* verilator lint_off UNUSED */ `define IGNORE_UNUSED_END /* verilator lint_on UNUSED */ @@ -30,7 +75,9 @@ /* verilator lint_off UNDRIVEN */ \ /* verilator lint_off DECLFILENAME */ \ /* verilator lint_off IMPLICIT */ \ - /* verilator lint_off IMPORTSTAR */ + /* verilator lint_off PINMISSING */ \ + /* verilator lint_off IMPORTSTAR */ \ + /* verilator lint_off UNSIGNED */ `define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ /* verilator lint_on PINCONNECTEMPTY */ \ @@ -39,68 +86,80 @@ /* verilator lint_on UNDRIVEN */ \ /* verilator lint_on DECLFILENAME */ \ /* verilator lint_on IMPLICIT */ \ - /* verilator lint_on IMPORTSTAR */ + /* verilator lint_off PINMISSING */ \ + /* verilator lint_on IMPORTSTAR */ \ + /* verilator lint_on UNSIGNED */ `define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \ localparam __``x = x; \ /* verilator lint_on UNUSED */ -`define UNUSED_VAR(x) always @(x) begin end +`define UNUSED_SPARAM(x) /* verilator lint_off UNUSED */ \ + localparam `STRING __``x = x; \ + /* verilator lint_on UNUSED */ -`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ - . x () \ - /* verilator lint_on PINCONNECTEMPTY */ +`define UNUSED_VAR(x) if (1) begin \ + /* verilator lint_off UNUSED */ \ + wire [$bits(x)-1:0] __x = x; \ + /* verilator lint_on UNUSED */ \ + end -`define ERROR(msg) \ - $error msg +`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ + . x () \ + /* verilator lint_on PINCONNECTEMPTY */ +`define UNUSED_ARG(x) /* verilator lint_off UNUSED */ \ + x \ + /* verilator lint_on UNUSED */ +`define TRACE(level, args) dpi_trace(level, $sformatf args) +`endif +`endif -`define ASSERT(cond, msg) \ - assert(cond) else $error msg - -`define STATIC_ASSERT(cond, msg) \ +`ifdef SIMULATION + `define STATIC_ASSERT(cond, msg) \ generate \ if (!(cond)) $error msg; \ endgenerate -`define RUNTIME_ASSERT(cond, msg) \ - always @(posedge clk) begin \ - assert(cond) else $error msg; \ - end + `define ERROR(msg) \ + $error msg -`define TRACING_ON /* verilator tracing_on */ -`define TRACING_OFF /* verilator tracing_off */ + `define ASSERT(cond, msg) \ + assert(cond) else $error msg -`else // SYNTHESIS - -`define DEBUG_BLOCK(x) -`define IGNORE_UNUSED_BEGIN -`define IGNORE_UNUSED_END -`define IGNORE_WARNINGS_BEGIN -`define IGNORE_WARNINGS_END -`define UNUSED_PARAM(x) -`define UNUSED_VAR(x) -`define UNUSED_PIN(x) . x () -`define ERROR(msg) -`define ASSERT(cond, msg) if (cond); -`define STATIC_ASSERT(cond, msg) -`define RUNTIME_ASSERT(cond, msg) -`define TRACING_ON -`define TRACING_OFF - -`endif // SYNTHESIS + `define RUNTIME_ASSERT(cond, msg) \ + always @(posedge clk) begin \ + assert(cond) else $error msg; \ + end +`else + `define STATIC_ASSERT(cond, msg) + `define ERROR(msg) // + `define ASSERT(cond, msg) // + `define RUNTIME_ASSERT(cond, msg) +`endif /////////////////////////////////////////////////////////////////////////////// `ifdef QUARTUS +`define MAX_FANOUT 4 +`define IF_DATA_SIZE(x) $bits(x.data) `define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *) `define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *) `define DISABLE_BRAM (* ramstyle = "logic" *) -`define PRESERVE_REG (* preserve *) +`define PRESERVE_NET (* preserve *) +`elsif VIVADO +`define MAX_FANOUT 4 +`define IF_DATA_SIZE(x) $bits(x.data) +`define USE_FAST_BRAM (* ram_style = "distributed" *) +`define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *) +`define DISABLE_BRAM (* ram_style = "registers" *) +`define PRESERVE_NET (* keep = "true" *) `else +`define MAX_FANOUT 4 +`define IF_DATA_SIZE(x) x.DATA_WIDTH `define USE_FAST_BRAM `define NO_RW_RAM_CHECK `define DISABLE_BRAM -`define PRESERVE_REG +`define PRESERVE_NET `endif /////////////////////////////////////////////////////////////////////////////// @@ -112,52 +171,105 @@ `define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) `define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1)))) -`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : (x)); +`define ABS(x) (((x) < 0) ? (-(x)) : (x)); +`ifndef MIN `define MIN(x, y) (((x) < (y)) ? (x) : (y)) -`define MAX(x, y) (((x) > (y)) ? (x) : (y)) +`endif -`define UP(x) (((x) > 0) ? (x) : 1) +`ifndef MAX +`define MAX(x, y) (((x) > (y)) ? (x) : (y)) +`endif + +`ifndef CLAMP +`define CLAMP(x, lo, hi) (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x))) +`endif + +`ifndef UP +`define UP(x) (((x) != 0) ? (x) : 1) +`endif `define RTRIM(x, s) x[$bits(x)-1:($bits(x)-s)] `define LTRIM(x, s) x[s-1:0] -`define TRACE_ARRAY1D(a, m) \ - dpi_trace("{"); \ - for (integer i = (m-1); i >= 0; --i) begin \ - if (i != (m-1)) dpi_trace(", "); \ - dpi_trace("0x%0h", a[i]); \ +`define TRACE_ARRAY1D(lvl, arr, m) \ + `TRACE(lvl, ("{")); \ + for (integer __i = (m-1); __i >= 0; --__i) begin \ + if (__i != (m-1)) `TRACE(lvl, (", ")); \ + `TRACE(lvl, ("0x%0h", arr[__i])); \ end \ - dpi_trace("}"); \ + `TRACE(lvl, ("}")); -`define TRACE_ARRAY2D(a, m, n) \ - dpi_trace("{"); \ - for (integer i = n-1; i >= 0; --i) begin \ - if (i != (n-1)) dpi_trace(", "); \ - dpi_trace("{"); \ - for (integer j = (m-1); j >= 0; --j) begin \ - if (j != (m-1)) dpi_trace(", "); \ - dpi_trace("0x%0h", a[i][j]); \ +`define TRACE_ARRAY2D(lvl, arr, m, n) \ + `TRACE(lvl, ("{")); \ + for (integer __i = n-1; __i >= 0; --__i) begin \ + if (__i != (n-1)) `TRACE(lvl, (", ")); \ + `TRACE(lvl, ("{")); \ + for (integer __j = (m-1); __j >= 0; --__j) begin \ + if (__j != (m-1)) `TRACE(lvl, (", "));\ + `TRACE(lvl, ("0x%0h", arr[__i][__j])); \ end \ - dpi_trace("}"); \ + `TRACE(lvl, ("}")); \ end \ - dpi_trace("}") + `TRACE(lvl, ("}")) -`define RESET_RELAY(signal) \ - wire signal; \ - VX_reset_relay __``signal ( \ - .clk (clk), \ - .reset (reset), \ - .reset_o (signal) \ +`define RESET_RELAY_EX(dst, src, size, fanout) \ + wire [size-1:0] dst; \ + VX_reset_relay #(.N(size), .MAX_FANOUT(fanout)) __``dst ( \ + .clk (clk), \ + .reset (src), \ + .reset_o (dst) \ ) -`define POP_COUNT(out, in) \ - VX_popcount #( \ - .N ($bits(in)) \ - ) __``out ( \ - .in_i (in), \ - .cnt_o (out) \ - ) +`define RESET_RELAY_EN(dst, src, enable) \ + `RESET_RELAY_EX (dst, src, 1, ((enable) ? 0 : -1)) -`endif \ No newline at end of file +`define RESET_RELAY(dst, src) \ + `RESET_RELAY_EX (dst, src, 1, 0) + +// size(x): 0 -> 0, 1 -> 1, 2 -> 2, 3 -> 2, 4-> 2 +`define OUT_REG_TO_EB_SIZE(out_reg) `MIN(out_reg, 2) + +// reg(x): 0 -> 0, 1 -> 1, 2 -> 0, 3 -> 1, 4 -> 2 +`define OUT_REG_TO_EB_REG(out_reg) ((out_reg & 1) + ((out_reg >> 2) << 1)) + +`define REPEAT(n,f,s) `_REPEAT_``n(f,s) +`define _REPEAT_0(f,s) +`define _REPEAT_1(f,s) `f(0) +`define _REPEAT_2(f,s) `f(1) `s `_REPEAT_1(f,s) +`define _REPEAT_3(f,s) `f(2) `s `_REPEAT_2(f,s) +`define _REPEAT_4(f,s) `f(3) `s `_REPEAT_3(f,s) +`define _REPEAT_5(f,s) `f(4) `s `_REPEAT_4(f,s) +`define _REPEAT_6(f,s) `f(5) `s `_REPEAT_5(f,s) +`define _REPEAT_7(f,s) `f(6) `s `_REPEAT_6(f,s) +`define _REPEAT_8(f,s) `f(7) `s `_REPEAT_7(f,s) +`define _REPEAT_9(f,s) `f(8) `s `_REPEAT_8(f,s) +`define _REPEAT_10(f,s) `f(9) `s `_REPEAT_9(f,s) +`define _REPEAT_11(f,s) `f(10) `s `_REPEAT_10(f,s) +`define _REPEAT_12(f,s) `f(11) `s `_REPEAT_11(f,s) +`define _REPEAT_13(f,s) `f(12) `s `_REPEAT_12(f,s) +`define _REPEAT_14(f,s) `f(13) `s `_REPEAT_13(f,s) +`define _REPEAT_15(f,s) `f(14) `s `_REPEAT_14(f,s) +`define _REPEAT_16(f,s) `f(15) `s `_REPEAT_15(f,s) +`define _REPEAT_17(f,s) `f(16) `s `_REPEAT_16(f,s) +`define _REPEAT_18(f,s) `f(17) `s `_REPEAT_17(f,s) +`define _REPEAT_19(f,s) `f(18) `s `_REPEAT_18(f,s) +`define _REPEAT_20(f,s) `f(19) `s `_REPEAT_19(f,s) +`define _REPEAT_21(f,s) `f(20) `s `_REPEAT_20(f,s) +`define _REPEAT_22(f,s) `f(21) `s `_REPEAT_21(f,s) +`define _REPEAT_23(f,s) `f(22) `s `_REPEAT_22(f,s) +`define _REPEAT_24(f,s) `f(23) `s `_REPEAT_23(f,s) +`define _REPEAT_25(f,s) `f(24) `s `_REPEAT_24(f,s) +`define _REPEAT_26(f,s) `f(25) `s `_REPEAT_25(f,s) +`define _REPEAT_27(f,s) `f(26) `s `_REPEAT_26(f,s) +`define _REPEAT_28(f,s) `f(27) `s `_REPEAT_27(f,s) +`define _REPEAT_29(f,s) `f(28) `s `_REPEAT_28(f,s) +`define _REPEAT_30(f,s) `f(29) `s `_REPEAT_29(f,s) +`define _REPEAT_31(f,s) `f(30) `s `_REPEAT_30(f,s) +`define _REPEAT_32(f,s) `f(31) `s `_REPEAT_31(f,s) + +`define REPEAT_COMMA , +`define REPEAT_SEMICOLON ; + +`endif // VX_PLATFORM_VH diff --git a/hw/rtl/VX_scope.vh b/hw/rtl/VX_scope.vh index 721a3da8..a7477064 100644 --- a/hw/rtl/VX_scope.vh +++ b/hw/rtl/VX_scope.vh @@ -1,89 +1,68 @@ -`ifndef VX_SCOPE -`define VX_SCOPE +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_SCOPE_VH +`define VX_SCOPE_VH `ifdef SCOPE -`include "scope-defs.vh" +`define SCOPE_IO_DECL \ + input wire scope_reset, \ + input wire scope_bus_in, \ + output wire scope_bus_out, -`define SCOPE_ASSIGN(d,s) assign scope_``d = s +`define SCOPE_IO_SWITCH(__count) \ + wire scope_bus_in_w [__count]; \ + wire scope_bus_out_w [__count]; \ + `RESET_RELAY_EX(scope_reset_w, scope_reset, __count, 4); \ + VX_scope_switch #( \ + .N (__count) \ + ) scope_switch ( \ + .clk (clk), \ + .reset (scope_reset), \ + .req_in (scope_bus_in), \ + .rsp_out (scope_bus_out), \ + .req_out (scope_bus_in_w), \ + .rsp_in (scope_bus_out_w) \ + ); -`define SCOPE_SIZE 1024 +`define SCOPE_IO_BIND(__i) \ + .scope_reset (scope_reset_w[__i]), \ + .scope_bus_in (scope_bus_in_w[__i]), \ + .scope_bus_out (scope_bus_out_w[__i]), + +`define SCOPE_IO_UNUSED() \ + `UNUSED_VAR (scope_reset); \ + `UNUSED_VAR (scope_bus_in); \ + assign scope_bus_out = 0; + +`define SCOPE_IO_UNUSED_W(__i) \ + `UNUSED_VAR (scope_reset_w[__i]); \ + `UNUSED_VAR (scope_bus_in_w[__i]); \ + assign scope_bus_out_w[__i] = 0; `else -`define SCOPE_IO_VX_icache_stage +`define SCOPE_IO_DECL -`define SCOPE_IO_VX_fetch +`define SCOPE_IO_SWITCH(__count) -`define SCOPE_BIND_VX_fetch_icache_stage +`define SCOPE_IO_BIND(__i) -`define SCOPE_BIND_VX_fetch_warp_sched +`define SCOPE_IO_UNUSED_W(__i) -`define SCOPE_IO_VX_warp_sched - -`define SCOPE_IO_VX_pipeline - -`define SCOPE_BIND_VX_pipeline_fetch - -`define SCOPE_IO_VX_core - -`define SCOPE_BIND_VX_core_pipeline - -`define SCOPE_IO_VX_cluster - -`define SCOPE_BIND_VX_cluster_core(__i__) - -`define SCOPE_IO_Vortex - -`define SCOPE_BIND_Vortex_cluster(__i__) - -`define SCOPE_BIND_afu_vortex - -`define SCOPE_IO_VX_lsu_unit - -`define SCOPE_IO_VX_gpu_unit - -`define SCOPE_IO_VX_execute - -`define SCOPE_BIND_VX_execute_lsu_unit - -`define SCOPE_BIND_VX_execute_gpu_unit - -`define SCOPE_BIND_VX_pipeline_execute - -`define SCOPE_IO_VX_issue - -`define SCOPE_BIND_VX_pipeline_issue - -`define SCOPE_IO_VX_bank - -`define SCOPE_IO_VX_cache - -`define SCOPE_BIND_VX_cache_bank(__i__) - -`define SCOPE_BIND_Vortex_l3cache - -`define SCOPE_BIND_VX_cluster_l2cache - -`define SCOPE_IO_VX_mem_unit - -`define SCOPE_BIND_VX_mem_unit_dcache - -`define SCOPE_BIND_VX_core_mem_unit - -`define SCOPE_BIND_VX_mem_unit_icache - -`define SCOPE_BIND_VX_mem_unit_smem - -`define SCOPE_DECL_SIGNALS - -`define SCOPE_DATA_LIST - -`define SCOPE_UPDATE_LIST - -`define SCOPE_TRIGGER - -`define SCOPE_ASSIGN(d,s) +`define SCOPE_IO_UNUSED(__i) `endif -`endif \ No newline at end of file + +`endif // VX_SCOPE_VH diff --git a/hw/rtl/VX_scoreboard.sv b/hw/rtl/VX_scoreboard.sv deleted file mode 100644 index b4422d28..00000000 --- a/hw/rtl/VX_scoreboard.sv +++ /dev/null @@ -1,85 +0,0 @@ -`include "VX_define.vh" - -module VX_scoreboard #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - VX_ibuffer_if.slave ibuffer_if, - VX_writeback_if.slave writeback_if -); - reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; - - wire reserve_reg = ibuffer_if.valid && ibuffer_if.ready && ibuffer_if.wb; - - wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop; - - always @(*) begin - inuse_regs_n = inuse_regs; - if (reserve_reg) begin - inuse_regs_n[ibuffer_if.wid][ibuffer_if.rd] = 1; - end - if (release_reg) begin - inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0; - end - end - - always @(posedge clk) begin - if (reset) begin - inuse_regs <= '0; - end else begin - inuse_regs <= inuse_regs_n; - end - end - - reg deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3; - - always @(posedge clk) begin - deq_inuse_rd <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rd_n]; - deq_inuse_rs1 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs1_n]; - deq_inuse_rs2 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs2_n]; - deq_inuse_rs3 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs3_n]; - end - - assign writeback_if.ready = 1'b1; - - assign ibuffer_if.ready = ~(deq_inuse_rd - | deq_inuse_rs1 - | deq_inuse_rs2 - | deq_inuse_rs3); - - `UNUSED_VAR (writeback_if.PC) - - reg [31:0] deadlock_ctr; - wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); - - always @(posedge clk) begin - if (reset) begin - deadlock_ctr <= 0; - end else begin - `ifdef DBG_TRACE_CORE_PIPELINE - if (ibuffer_if.valid && ~ibuffer_if.ready) begin - dpi_trace("%d: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b (#%0d)\n", - $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, - deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3, ibuffer_if.uuid); - end - `endif - if (release_reg) begin - `ASSERT(inuse_regs[writeback_if.wid][writeback_if.rd] != 0, - ("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d (#%0d)", - $time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd,writeback_if.uuid)); - end - if (ibuffer_if.valid && ~ibuffer_if.ready) begin - deadlock_ctr <= deadlock_ctr + 1; - `ASSERT(deadlock_ctr < deadlock_timeout, - ("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b (#%0d)", - $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, - deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3, ibuffer_if.uuid)); - end else if (ibuffer_if.valid && ibuffer_if.ready) begin - deadlock_ctr <= 0; - end - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_smem_arb.sv b/hw/rtl/VX_smem_arb.sv deleted file mode 100644 index 24d64ff1..00000000 --- a/hw/rtl/VX_smem_arb.sv +++ /dev/null @@ -1,160 +0,0 @@ -`include "VX_define.vh" - -module VX_smem_arb #( - parameter NUM_REQS = 1, - parameter LANES = 1, - parameter DATA_SIZE = 1, - parameter TAG_IN_WIDTH = 1, - parameter TAG_SEL_IDX = 0, - parameter BUFFERED_REQ = 0, - parameter BUFFERED_RSP = 0, - parameter TYPE = "P", - - parameter ADDR_WIDTH = (32-`CLOG2(DATA_SIZE)), - parameter DATA_WIDTH = (8 * DATA_SIZE), - parameter LOG_NUM_REQS = `CLOG2(NUM_REQS), - parameter TAG_OUT_WIDTH = TAG_IN_WIDTH - LOG_NUM_REQS -) ( - input wire clk, - input wire reset, - - // input request - input wire [LANES-1:0] req_valid_in, - input wire [LANES-1:0] req_rw_in, - input wire [LANES-1:0][DATA_SIZE-1:0] req_byteen_in, - input wire [LANES-1:0][ADDR_WIDTH-1:0] req_addr_in, - input wire [LANES-1:0][DATA_WIDTH-1:0] req_data_in, - input wire [LANES-1:0][TAG_IN_WIDTH-1:0] req_tag_in, - output wire [LANES-1:0] req_ready_in, - - // output requests - output wire [NUM_REQS-1:0][LANES-1:0] req_valid_out, - output wire [NUM_REQS-1:0][LANES-1:0] req_rw_out, - output wire [NUM_REQS-1:0][LANES-1:0][DATA_SIZE-1:0] req_byteen_out, - output wire [NUM_REQS-1:0][LANES-1:0][ADDR_WIDTH-1:0] req_addr_out, - output wire [NUM_REQS-1:0][LANES-1:0][DATA_WIDTH-1:0] req_data_out, - output wire [NUM_REQS-1:0][LANES-1:0][TAG_OUT_WIDTH-1:0] req_tag_out, - input wire [NUM_REQS-1:0][LANES-1:0] req_ready_out, - - // input responses - input wire [NUM_REQS-1:0] rsp_valid_in, - input wire [NUM_REQS-1:0][LANES-1:0] rsp_tmask_in, - input wire [NUM_REQS-1:0][LANES-1:0][DATA_WIDTH-1:0] rsp_data_in, - input wire [NUM_REQS-1:0][TAG_OUT_WIDTH-1:0] rsp_tag_in, - output wire [NUM_REQS-1:0] rsp_ready_in, - - // output response - output wire rsp_valid_out, - output wire [LANES-1:0] rsp_tmask_out, - output wire [LANES-1:0][DATA_WIDTH-1:0] rsp_data_out, - output wire [TAG_IN_WIDTH-1:0] rsp_tag_out, - input wire rsp_ready_out -); - localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH; - localparam RSP_DATAW = LANES * (1 + DATA_WIDTH) + TAG_IN_WIDTH; - - if (NUM_REQS > 1) begin - - wire [LANES-1:0][REQ_DATAW-1:0] req_data_in_merged; - wire [NUM_REQS-1:0][LANES-1:0][REQ_DATAW-1:0] req_data_out_merged; - - wire [LANES-1:0][LOG_NUM_REQS-1:0] req_sel; - wire [LANES-1:0][TAG_OUT_WIDTH-1:0] req_tag_in_w; - - for (genvar i = 0; i < LANES; ++i) begin - assign req_sel[i] = req_tag_in[i][TAG_SEL_IDX +: LOG_NUM_REQS]; - - VX_bits_remove #( - .N (TAG_IN_WIDTH), - .S (LOG_NUM_REQS), - .POS (TAG_SEL_IDX) - ) bits_remove ( - .data_in (req_tag_in[i]), - .data_out (req_tag_in_w[i]) - ); - - assign req_data_in_merged[i] = {req_tag_in_w[i], req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]}; - end - - VX_stream_demux #( - .NUM_REQS (NUM_REQS), - .LANES (LANES), - .DATAW (REQ_DATAW), - .BUFFERED (BUFFERED_REQ) - ) req_demux ( - .clk (clk), - .reset (reset), - .sel_in (req_sel), - .valid_in (req_valid_in), - .data_in (req_data_in_merged), - .ready_in (req_ready_in), - .valid_out (req_valid_out), - .data_out (req_data_out_merged), - .ready_out (req_ready_out) - ); - - for (genvar i = 0; i < NUM_REQS; i++) begin - for (genvar j = 0; j < LANES; ++j) begin - assign {req_tag_out[i][j], req_addr_out[i][j], req_rw_out[i][j], req_byteen_out[i][j], req_data_out[i][j]} = req_data_out_merged[i][j]; - end - end - - /////////////////////////////////////////////////////////////////////// - - wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_in_merged; - - for (genvar i = 0; i < NUM_REQS; i++) begin - wire [TAG_IN_WIDTH-1:0] rsp_tag_in_w; - - VX_bits_insert #( - .N (TAG_OUT_WIDTH), - .S (LOG_NUM_REQS), - .POS (TAG_SEL_IDX) - ) bits_insert ( - .data_in (rsp_tag_in[i]), - .sel_in (LOG_NUM_REQS'(i)), - .data_out (rsp_tag_in_w) - ); - - assign rsp_data_in_merged[i] = {rsp_tag_in_w, rsp_tmask_in[i], rsp_data_in[i]}; - end - - VX_stream_arbiter #( - .NUM_REQS (NUM_REQS), - .LANES (1), - .DATAW (RSP_DATAW), - .BUFFERED (BUFFERED_RSP), - .TYPE (TYPE) - ) rsp_arb ( - .clk (clk), - .reset (reset), - .valid_in (rsp_valid_in), - .data_in (rsp_data_in_merged), - .ready_in (rsp_ready_in), - .valid_out (rsp_valid_out), - .data_out ({rsp_tag_out, rsp_tmask_out, rsp_data_out}), - .ready_out (rsp_ready_out) - ); - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - assign req_valid_out = req_valid_in; - assign req_tag_out = req_tag_in; - assign req_addr_out = req_addr_in; - assign req_rw_out = req_rw_in; - assign req_byteen_out = req_byteen_in; - assign req_data_out = req_data_in; - assign req_ready_in = req_ready_out; - - assign rsp_valid_out = rsp_valid_in; - assign rsp_tmask_out = rsp_tmask_in; - assign rsp_tag_out = rsp_tag_in; - assign rsp_data_out = rsp_data_in; - assign rsp_ready_in = rsp_ready_out; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_socket.sv b/hw/rtl/VX_socket.sv new file mode 100644 index 00000000..8c8f4b39 --- /dev/null +++ b/hw/rtl/VX_socket.sv @@ -0,0 +1,187 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_socket import VX_gpu_pkg::*; #( + parameter SOCKET_ID = 0 +) ( + `SCOPE_IO_DECL + + // Clock + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + VX_mem_perf_if.slave mem_perf_if, +`endif + + VX_dcr_bus_if.slave dcr_bus_if, + + VX_mem_bus_if.master dcache_bus_if [DCACHE_NUM_REQS], + + VX_mem_bus_if.master icache_bus_if, + +`ifdef GBAR_ENABLE + VX_gbar_bus_if.master gbar_bus_if, +`endif + + // simulation helper signals + output wire sim_ebreak, + output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value, + + // Status + output wire busy +); + +`ifdef GBAR_ENABLE + VX_gbar_bus_if per_core_gbar_bus_if[`SOCKET_SIZE](); + + `RESET_RELAY (gbar_arb_reset, reset); + + VX_gbar_arb #( + .NUM_REQS (`SOCKET_SIZE), + .OUT_REG ((`SOCKET_SIZE > 1) ? 2 : 0) + ) gbar_arb ( + .clk (clk), + .reset (gbar_arb_reset), + .bus_in_if (per_core_gbar_bus_if), + .bus_out_if (gbar_bus_if) + ); +`endif + + /////////////////////////////////////////////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH) + ) per_core_dcache_bus_if[`SOCKET_SIZE * DCACHE_NUM_REQS](); + + `RESET_RELAY (dcache_arb_reset, reset); + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_ARB_TAG_WIDTH) + ) dcache_bus_tmp_if[1](); + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH) + ) per_core_dcache_bus_tmp_if[`SOCKET_SIZE](); + + for (genvar j = 0; j < `SOCKET_SIZE; ++j) begin + `ASSIGN_VX_MEM_BUS_IF (per_core_dcache_bus_tmp_if[j], per_core_dcache_bus_if[j * DCACHE_NUM_REQS + i]); + end + + VX_mem_arb #( + .NUM_INPUTS (`SOCKET_SIZE), + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH), + .TAG_SEL_IDX (`CACHE_ADDR_TYPE_BITS), + .ARBITER ("R"), + .OUT_REG_REQ ((`SOCKET_SIZE > 1) ? 2 : 0), + .OUT_REG_RSP ((`SOCKET_SIZE > 1) ? 2 : 0) + ) dcache_arb ( + .clk (clk), + .reset (dcache_arb_reset), + .bus_in_if (per_core_dcache_bus_tmp_if), + .bus_out_if (dcache_bus_tmp_if) + ); + + `ASSIGN_VX_MEM_BUS_IF (dcache_bus_if[i], dcache_bus_tmp_if[0]); + end + + /////////////////////////////////////////////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_WORD_SIZE), + .TAG_WIDTH (ICACHE_TAG_WIDTH) + ) per_core_icache_bus_if[`SOCKET_SIZE](); + + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_WORD_SIZE), + .TAG_WIDTH (ICACHE_ARB_TAG_WIDTH) + ) icache_bus_tmp_if[1](); + + `RESET_RELAY (icache_arb_reset, reset); + + VX_mem_arb #( + .NUM_INPUTS (`SOCKET_SIZE), + .NUM_OUTPUTS (1), + .DATA_SIZE (ICACHE_WORD_SIZE), + .TAG_WIDTH (ICACHE_TAG_WIDTH), + .TAG_SEL_IDX (0), + .ARBITER ("R"), + .OUT_REG_REQ ((`SOCKET_SIZE > 1) ? 2 : 0), + .OUT_REG_RSP ((`SOCKET_SIZE > 1) ? 2 : 0) + ) icache_arb ( + .clk (clk), + .reset (icache_arb_reset), + .bus_in_if (per_core_icache_bus_if), + .bus_out_if (icache_bus_tmp_if) + ); + + `ASSIGN_VX_MEM_BUS_IF (icache_bus_if, icache_bus_tmp_if[0]); + + /////////////////////////////////////////////////////////////////////////// + + wire [`SOCKET_SIZE-1:0] per_core_sim_ebreak; + wire [`SOCKET_SIZE-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_core_sim_wb_value; + assign sim_ebreak = per_core_sim_ebreak[0]; + assign sim_wb_value = per_core_sim_wb_value[0]; + `UNUSED_VAR (per_core_sim_ebreak) + `UNUSED_VAR (per_core_sim_wb_value) + + wire [`SOCKET_SIZE-1:0] per_core_busy; + + `BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, (`SOCKET_SIZE > 1)); + + `SCOPE_IO_SWITCH (`SOCKET_SIZE) + + // Generate all cores + for (genvar i = 0; i < `SOCKET_SIZE; ++i) begin + + `RESET_RELAY (core_reset, reset); + + VX_core #( + .CORE_ID ((SOCKET_ID * `SOCKET_SIZE) + i) + ) core ( + `SCOPE_IO_BIND (i) + + .clk (clk), + .reset (core_reset), + + `ifdef PERF_ENABLE + .mem_perf_if (mem_perf_if), + `endif + + .dcr_bus_if (core_dcr_bus_if), + + .dcache_bus_if (per_core_dcache_bus_if[i * DCACHE_NUM_REQS +: DCACHE_NUM_REQS]), + + .icache_bus_if (per_core_icache_bus_if[i]), + + `ifdef GBAR_ENABLE + .gbar_bus_if (per_core_gbar_bus_if[i]), + `endif + + .sim_ebreak (per_core_sim_ebreak[i]), + .sim_wb_value (per_core_sim_wb_value[i]), + .busy (per_core_busy[i]) + ); + end + + `BUFFER_BUSY (busy, (| per_core_busy), (`SOCKET_SIZE > 1)); + +endmodule diff --git a/hw/rtl/VX_trace_instr.vh b/hw/rtl/VX_trace_instr.vh deleted file mode 100644 index 5e8e031e..00000000 --- a/hw/rtl/VX_trace_instr.vh +++ /dev/null @@ -1,148 +0,0 @@ -`ifndef VX_TRACE_INSTR -`define VX_TRACE_INSTR - -`include "VX_define.vh" - -task trace_ex_type ( - input [`EX_BITS-1:0] ex_type -); - case (ex_type) - `EX_ALU: dpi_trace("ALU"); - `EX_LSU: dpi_trace("LSU"); - `EX_CSR: dpi_trace("CSR"); - `EX_FPU: dpi_trace("FPU"); - `EX_GPU: dpi_trace("GPU"); - default: dpi_trace("NOP"); - endcase -endtask - -task trace_ex_op ( - input [`EX_BITS-1:0] ex_type, - input [`INST_OP_BITS-1:0] op_type, - input [`INST_MOD_BITS-1:0] op_mod -); - case (ex_type) - `EX_ALU: begin - if (`INST_ALU_IS_BR(op_mod)) begin - case (`INST_BR_BITS'(op_type)) - `INST_BR_EQ: dpi_trace("BEQ"); - `INST_BR_NE: dpi_trace("BNE"); - `INST_BR_LT: dpi_trace("BLT"); - `INST_BR_GE: dpi_trace("BGE"); - `INST_BR_LTU: dpi_trace("BLTU"); - `INST_BR_GEU: dpi_trace("BGEU"); - `INST_BR_JAL: dpi_trace("JAL"); - `INST_BR_JALR: dpi_trace("JALR"); - `INST_BR_ECALL: dpi_trace("ECALL"); - `INST_BR_EBREAK:dpi_trace("EBREAK"); - `INST_BR_URET: dpi_trace("URET"); - `INST_BR_SRET: dpi_trace("SRET"); - `INST_BR_MRET: dpi_trace("MRET"); - default: dpi_trace("?"); - endcase - end else if (`INST_ALU_IS_MUL(op_mod)) begin - case (`INST_MUL_BITS'(op_type)) - `INST_MUL_MUL: dpi_trace("MUL"); - `INST_MUL_MULH: dpi_trace("MULH"); - `INST_MUL_MULHSU:dpi_trace("MULHSU"); - `INST_MUL_MULHU: dpi_trace("MULHU"); - `INST_MUL_DIV: dpi_trace("DIV"); - `INST_MUL_DIVU: dpi_trace("DIVU"); - `INST_MUL_REM: dpi_trace("REM"); - `INST_MUL_REMU: dpi_trace("REMU"); - default: dpi_trace("?"); - endcase - end else begin - case (`INST_ALU_BITS'(op_type)) - `INST_ALU_ADD: dpi_trace("ADD"); - `INST_ALU_SUB: dpi_trace("SUB"); - `INST_ALU_SLL: dpi_trace("SLL"); - `INST_ALU_SRL: dpi_trace("SRL"); - `INST_ALU_SRA: dpi_trace("SRA"); - `INST_ALU_SLT: dpi_trace("SLT"); - `INST_ALU_SLTU: dpi_trace("SLTU"); - `INST_ALU_XOR: dpi_trace("XOR"); - `INST_ALU_OR: dpi_trace("OR"); - `INST_ALU_AND: dpi_trace("AND"); - `INST_ALU_LUI: dpi_trace("LUI"); - `INST_ALU_AUIPC: dpi_trace("AUIPC"); - default: dpi_trace("?"); - endcase - end - end - `EX_LSU: begin - if (op_mod == 0) begin - case (`INST_LSU_BITS'(op_type)) - `INST_LSU_LB: dpi_trace("LB"); - `INST_LSU_LH: dpi_trace("LH"); - `INST_LSU_LW: dpi_trace("LW"); - `INST_LSU_LBU:dpi_trace("LBU"); - `INST_LSU_LHU:dpi_trace("LHU"); - `INST_LSU_SB: dpi_trace("SB"); - `INST_LSU_SH: dpi_trace("SH"); - `INST_LSU_SW: dpi_trace("SW"); - default: dpi_trace("?"); - endcase - end else if (op_mod == 1) begin - case (`INST_FENCE_BITS'(op_type)) - `INST_FENCE_D: dpi_trace("DFENCE"); - `INST_FENCE_I: dpi_trace("IFENCE"); - default: dpi_trace("?"); - endcase - end - end - `EX_CSR: begin - case (`INST_CSR_BITS'(op_type)) - `INST_CSR_RW: dpi_trace("CSRW"); - `INST_CSR_RS: dpi_trace("CSRS"); - `INST_CSR_RC: dpi_trace("CSRC"); - default: dpi_trace("?"); - endcase - end - `EX_FPU: begin - case (`INST_FPU_BITS'(op_type)) - `INST_FPU_ADD: dpi_trace("ADD"); - `INST_FPU_SUB: dpi_trace("SUB"); - `INST_FPU_MUL: dpi_trace("MUL"); - `INST_FPU_DIV: dpi_trace("DIV"); - `INST_FPU_SQRT: dpi_trace("SQRT"); - `INST_FPU_MADD: dpi_trace("MADD"); - `INST_FPU_NMSUB: dpi_trace("NMSUB"); - `INST_FPU_NMADD: dpi_trace("NMADD"); - `INST_FPU_CVTWS: dpi_trace("CVTWS"); - `INST_FPU_CVTWUS:dpi_trace("CVTWUS"); - `INST_FPU_CVTSW: dpi_trace("CVTSW"); - `INST_FPU_CVTSWU:dpi_trace("CVTSWU"); - `INST_FPU_CLASS: dpi_trace("CLASS"); - `INST_FPU_CMP: dpi_trace("CMP"); - `INST_FPU_MISC: begin - case (op_mod) - 0: dpi_trace("SGNJ"); - 1: dpi_trace("SGNJN"); - 2: dpi_trace("SGNJX"); - 3: dpi_trace("MIN"); - 4: dpi_trace("MAX"); - 5: dpi_trace("MVXW"); - 6: dpi_trace("MVWX"); - endcase - end - default: dpi_trace("?"); - endcase - end - `EX_GPU: begin - case (`INST_GPU_BITS'(op_type)) - `INST_GPU_TMC: dpi_trace("TMC"); - `INST_GPU_WSPAWN:dpi_trace("WSPAWN"); - `INST_GPU_SPLIT: dpi_trace("SPLIT"); - `INST_GPU_JOIN: dpi_trace("JOIN"); - `INST_GPU_BAR: dpi_trace("BAR"); - `INST_GPU_PRED: dpi_trace("PRED"); - `INST_GPU_TEX: dpi_trace("TEX"); - default: dpi_trace("?"); - endcase - end - default: dpi_trace("?"); - endcase -endtask - -`endif diff --git a/hw/rtl/VX_types.vh b/hw/rtl/VX_types.vh new file mode 100644 index 00000000..9f5aa0d5 --- /dev/null +++ b/hw/rtl/VX_types.vh @@ -0,0 +1,177 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_TYPES_VH +`define VX_TYPES_VH + +// Device configuration registers + +`define VX_CSR_ADDR_BITS 12 +`define VX_DCR_ADDR_BITS 12 + +`define VX_DCR_BASE_STATE_BEGIN 12'h001 +`define VX_DCR_BASE_STARTUP_ADDR0 12'h001 +`define VX_DCR_BASE_STARTUP_ADDR1 12'h002 +`define VX_DCR_BASE_MPM_CLASS 12'h003 +`define VX_DCR_BASE_STATE_END 12'h004 + +`define VX_DCR_BASE_STATE(addr) ((addr) - `VX_DCR_BASE_STATE_BEGIN) +`define VX_DCR_BASE_STATE_COUNT (`VX_DCR_BASE_STATE_END-`VX_DCR_BASE_STATE_BEGIN) + +// Machine Performance-monitoring counters classes + +`define VX_DCR_MPM_CLASS_NONE 0 +`define VX_DCR_MPM_CLASS_CORE 1 +`define VX_DCR_MPM_CLASS_MEM 2 +`define VX_DCR_MPM_CLASS_TEX 3 +`define VX_DCR_MPM_CLASS_RASTER 4 +`define VX_DCR_MPM_CLASS_ROP 5 + +// User Floating-Point CSRs + +`define VX_CSR_FFLAGS 12'h001 +`define VX_CSR_FRM 12'h002 +`define VX_CSR_FCSR 12'h003 + +`define VX_CSR_SATP 12'h180 + +`define VX_CSR_PMPCFG0 12'h3A0 +`define VX_CSR_PMPADDR0 12'h3B0 + +`define VX_CSR_MSTATUS 12'h300 +`define VX_CSR_MISA 12'h301 +`define VX_CSR_MEDELEG 12'h302 +`define VX_CSR_MIDELEG 12'h303 +`define VX_CSR_MIE 12'h304 +`define VX_CSR_MTVEC 12'h305 + +`define VX_CSR_MEPC 12'h341 + +`define VX_CSR_MNSTATUS 12'h744 + +`define VX_CSR_MPM_BASE 12'hB00 +`define VX_CSR_MPM_BASE_H 12'hB80 + +// Machine Performance-monitoring core counters +// PERF: Standard +`define VX_CSR_MCYCLE 12'hB00 +`define VX_CSR_MCYCLE_H 12'hB80 +`define VX_CSR_MPM_RESERVED 12'hB01 +`define VX_CSR_MPM_RESERVED_H 12'hB81 +`define VX_CSR_MINSTRET 12'hB02 +`define VX_CSR_MINSTRET_H 12'hB82 +// PERF: pipeline +`define VX_CSR_MPM_IBUF_ST 12'hB03 +`define VX_CSR_MPM_IBUF_ST_H 12'hB83 +`define VX_CSR_MPM_SCRB_ST 12'hB04 +`define VX_CSR_MPM_SCRB_ST_H 12'hB84 +`define VX_CSR_MPM_ALU_ST 12'hB05 +`define VX_CSR_MPM_ALU_ST_H 12'hB85 +`define VX_CSR_MPM_LSU_ST 12'hB06 +`define VX_CSR_MPM_LSU_ST_H 12'hB86 +`define VX_CSR_MPM_FPU_ST 12'hB07 +`define VX_CSR_MPM_FPU_ST_H 12'hB87 +`define VX_CSR_MPM_SFU_ST 12'hB08 +`define VX_CSR_MPM_SFU_ST_H 12'hB88 +// PERF: memory +`define VX_CSR_MPM_IFETCHES 12'hB0A +`define VX_CSR_MPM_IFETCHES_H 12'hB8A +`define VX_CSR_MPM_LOADS 12'hB0B +`define VX_CSR_MPM_LOADS_H 12'hB8B +`define VX_CSR_MPM_STORES 12'hB0C +`define VX_CSR_MPM_STORES_H 12'hB8C +`define VX_CSR_MPM_IFETCH_LAT 12'hB0D +`define VX_CSR_MPM_IFETCH_LAT_H 12'hB8D +`define VX_CSR_MPM_LOAD_LAT 12'hB0E +`define VX_CSR_MPM_LOAD_LAT_H 12'hB8E + +// Machine Performance-monitoring memory counters +// PERF: icache +`define VX_CSR_MPM_ICACHE_READS 12'hB03 // total reads +`define VX_CSR_MPM_ICACHE_READS_H 12'hB83 +`define VX_CSR_MPM_ICACHE_MISS_R 12'hB04 // read misses +`define VX_CSR_MPM_ICACHE_MISS_R_H 12'hB84 +// PERF: dcache +`define VX_CSR_MPM_DCACHE_READS 12'hB05 // total reads +`define VX_CSR_MPM_DCACHE_READS_H 12'hB85 +`define VX_CSR_MPM_DCACHE_WRITES 12'hB06 // total writes +`define VX_CSR_MPM_DCACHE_WRITES_H 12'hB86 +`define VX_CSR_MPM_DCACHE_MISS_R 12'hB07 // read misses +`define VX_CSR_MPM_DCACHE_MISS_R_H 12'hB87 +`define VX_CSR_MPM_DCACHE_MISS_W 12'hB08 // write misses +`define VX_CSR_MPM_DCACHE_MISS_W_H 12'hB88 +`define VX_CSR_MPM_DCACHE_BANK_ST 12'hB09 // bank conflicts +`define VX_CSR_MPM_DCACHE_BANK_ST_H 12'hB89 +`define VX_CSR_MPM_DCACHE_MSHR_ST 12'hB0A // MSHR stalls +`define VX_CSR_MPM_DCACHE_MSHR_ST_H 12'hB8A +// PERF: smem +`define VX_CSR_MPM_SMEM_READS 12'hB0B // memory reads +`define VX_CSR_MPM_SMEM_READS_H 12'hB8B +`define VX_CSR_MPM_SMEM_WRITES 12'hB0C // memory writes +`define VX_CSR_MPM_SMEM_WRITES_H 12'hB8C +`define VX_CSR_MPM_SMEM_BANK_ST 12'hB0D // bank conflicts +`define VX_CSR_MPM_SMEM_BANK_ST_H 12'hB8D +// PERF: l2cache +`define VX_CSR_MPM_L2CACHE_READS 12'hB0E // total reads +`define VX_CSR_MPM_L2CACHE_READS_H 12'hB8E +`define VX_CSR_MPM_L2CACHE_WRITES 12'hB0F // total writes +`define VX_CSR_MPM_L2CACHE_WRITES_H 12'hB8F +`define VX_CSR_MPM_L2CACHE_MISS_R 12'hB10 // read misses +`define VX_CSR_MPM_L2CACHE_MISS_R_H 12'hB90 +`define VX_CSR_MPM_L2CACHE_MISS_W 12'hB11 // write misses +`define VX_CSR_MPM_L2CACHE_MISS_W_H 12'hB91 +`define VX_CSR_MPM_L2CACHE_BANK_ST 12'hB12 // bank conflicts +`define VX_CSR_MPM_L2CACHE_BANK_ST_H 12'hB92 +`define VX_CSR_MPM_L2CACHE_MSHR_ST 12'hB13 // MSHR stalls +`define VX_CSR_MPM_L2CACHE_MSHR_ST_H 12'hB93 +// PERF: l3cache +`define VX_CSR_MPM_L3CACHE_READS 12'hB14 // total reads +`define VX_CSR_MPM_L3CACHE_READS_H 12'hB94 +`define VX_CSR_MPM_L3CACHE_WRITES 12'hB15 // total writes +`define VX_CSR_MPM_L3CACHE_WRITES_H 12'hB95 +`define VX_CSR_MPM_L3CACHE_MISS_R 12'hB16 // read misses +`define VX_CSR_MPM_L3CACHE_MISS_R_H 12'hB96 +`define VX_CSR_MPM_L3CACHE_MISS_W 12'hB17 // write misses +`define VX_CSR_MPM_L3CACHE_MISS_W_H 12'hB97 +`define VX_CSR_MPM_L3CACHE_BANK_ST 12'hB18 // bank conflicts +`define VX_CSR_MPM_L3CACHE_BANK_ST_H 12'hB98 +`define VX_CSR_MPM_L3CACHE_MSHR_ST 12'hB19 // MSHR stalls +`define VX_CSR_MPM_L3CACHE_MSHR_ST_H 12'hB99 +// PERF: memory +`define VX_CSR_MPM_MEM_READS 12'hB1A // total reads +`define VX_CSR_MPM_MEM_READS_H 12'hB9A +`define VX_CSR_MPM_MEM_WRITES 12'hB1B // total writes +`define VX_CSR_MPM_MEM_WRITES_H 12'hB9B +`define VX_CSR_MPM_MEM_LAT 12'hB1C // memory latency +`define VX_CSR_MPM_MEM_LAT_H 12'hB9C + +// Machine Information Registers + +`define VX_CSR_MVENDORID 12'hF11 +`define VX_CSR_MARCHID 12'hF12 +`define VX_CSR_MIMPID 12'hF13 +`define VX_CSR_MHARTID 12'hF14 + +// GPGU CSRs + +`define VX_CSR_THREAD_ID 12'hCC0 +`define VX_CSR_WARP_ID 12'hCC1 +`define VX_CSR_CORE_ID 12'hCC2 +`define VX_CSR_WARP_MASK 12'hCC3 +`define VX_CSR_THREAD_MASK 12'hCC4 // warning! this value is also used in LLVM + +`define VX_CSR_NUM_THREADS 12'hFC0 +`define VX_CSR_NUM_WARPS 12'hFC1 +`define VX_CSR_NUM_CORES 12'hFC2 + +`endif // VX_TYPES_VH diff --git a/hw/rtl/VX_warp_sched.sv b/hw/rtl/VX_warp_sched.sv deleted file mode 100644 index dda8600b..00000000 --- a/hw/rtl/VX_warp_sched.sv +++ /dev/null @@ -1,254 +0,0 @@ -`include "VX_define.vh" - -module VX_warp_sched #( - parameter CORE_ID = 0 -) ( - `SCOPE_IO_VX_warp_sched - - input wire clk, - input wire reset, - - VX_warp_ctl_if.slave warp_ctl_if, - VX_wstall_if.slave wstall_if, - VX_join_if.slave join_if, - VX_branch_ctl_if.slave branch_ctl_if, - - VX_ifetch_req_if.master ifetch_req_if, - - VX_fetch_to_csr_if.master fetch_to_csr_if, - - output wire busy -); - - `UNUSED_PARAM (CORE_ID) - - wire join_else; - wire [31:0] join_pc; - wire [`NUM_THREADS-1:0] join_tmask; - - reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // real active warps (updated when a warp is activated or disabled) - reg [`NUM_WARPS-1:0] stalled_warps; // asserted when a branch/gpgpu instructions are issued - - reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks; - reg [`NUM_WARPS-1:0][31:0] warp_pcs; - - // barriers - reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks; // warps waiting on barrier - wire reached_barrier_limit; // the expected number of warps reached the barrier - - // wspawn - reg [31:0] wspawn_pc; - reg [`NUM_WARPS-1:0] use_wspawn; - - wire [`NW_BITS-1:0] schedule_wid; - wire [`NUM_THREADS-1:0] schedule_tmask; - wire [31:0] schedule_pc; - wire schedule_valid; - wire warp_scheduled; - - reg [`UUID_BITS-1:0] issued_instrs; - - wire ifetch_req_fire = ifetch_req_if.valid && ifetch_req_if.ready; - - wire tmc_active = (warp_ctl_if.tmc.tmask != 0); - - always @(*) begin - active_warps_n = active_warps; - if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin - active_warps_n = warp_ctl_if.wspawn.wmask; - end - if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin - active_warps_n[warp_ctl_if.wid] = tmc_active; - end - end - - always @(posedge clk) begin - if (reset) begin - barrier_masks <= '0; - use_wspawn <= '0; - stalled_warps <= '0; - warp_pcs <= '0; - active_warps <= '0; - thread_masks <= '0; - issued_instrs <= '0; - - // activate first warp - warp_pcs[0] <= `STARTUP_ADDR; - active_warps[0] <= 1; - thread_masks[0] <= 1; - end else begin - if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin - use_wspawn <= warp_ctl_if.wspawn.wmask & (~`NUM_WARPS'(1)); - wspawn_pc <= warp_ctl_if.wspawn.pc; - end - - if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin - stalled_warps[warp_ctl_if.wid] <= 0; - if (reached_barrier_limit) begin - barrier_masks[warp_ctl_if.barrier.id] <= 0; - end else begin - barrier_masks[warp_ctl_if.barrier.id][warp_ctl_if.wid] <= 1; - end - end - - if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin - thread_masks[warp_ctl_if.wid] <= warp_ctl_if.tmc.tmask; - stalled_warps[warp_ctl_if.wid] <= 0; - end - - if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin - stalled_warps[warp_ctl_if.wid] <= 0; - if (warp_ctl_if.split.diverged) begin - thread_masks[warp_ctl_if.wid] <= warp_ctl_if.split.then_tmask; - end - end - - // Branch - if (branch_ctl_if.valid) begin - if (branch_ctl_if.taken) begin - warp_pcs[branch_ctl_if.wid] <= branch_ctl_if.dest; - end - stalled_warps[branch_ctl_if.wid] <= 0; - end - - if (warp_scheduled) begin - // stall the warp until decode stage - stalled_warps[schedule_wid] <= 1; - - // release wspawn - use_wspawn[schedule_wid] <= 0; - if (use_wspawn[schedule_wid]) begin - thread_masks[schedule_wid] <= 1; - end - - issued_instrs <= issued_instrs + 1; - end - - if (ifetch_req_fire) begin - warp_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4; - end - - if (wstall_if.valid) begin - stalled_warps[wstall_if.wid] <= wstall_if.stalled; - end - - // join handling - if (join_if.valid) begin - if (join_else) begin - warp_pcs[join_if.wid] <= join_pc; - end - thread_masks[join_if.wid] <= join_tmask; - end - - active_warps <= active_warps_n; - end - end - - // export thread mask register - assign fetch_to_csr_if.thread_masks = thread_masks; - - // calculate active barrier status - -`IGNORE_UNUSED_BEGIN - wire [`NW_BITS:0] active_barrier_count; -`IGNORE_UNUSED_END - wire [`NUM_WARPS-1:0] barrier_mask = barrier_masks[warp_ctl_if.barrier.id]; - `POP_COUNT(active_barrier_count, barrier_mask); - - assign reached_barrier_limit = (active_barrier_count[`NW_BITS-1:0] == warp_ctl_if.barrier.size_m1); - - reg [`NUM_WARPS-1:0] barrier_stalls; - always @(*) begin - barrier_stalls = barrier_masks[0]; - for (integer i = 1; i < `NUM_BARRIERS; ++i) begin - barrier_stalls |= barrier_masks[i]; - end - end - - // split/join stack management - - wire [(32+`NUM_THREADS)-1:0] ipdom_data [`NUM_WARPS-1:0]; - wire ipdom_index [`NUM_WARPS-1:0]; - - for (genvar i = 0; i < `NUM_WARPS; i++) begin - wire push = warp_ctl_if.valid - && warp_ctl_if.split.valid - && (i == warp_ctl_if.wid); - - wire pop = join_if.valid && (i == join_if.wid); - - wire [`NUM_THREADS-1:0] else_tmask = warp_ctl_if.split.else_tmask; - wire [`NUM_THREADS-1:0] orig_tmask = thread_masks[warp_ctl_if.wid]; - - wire [(32+`NUM_THREADS)-1:0] q_else = {warp_ctl_if.split.pc, else_tmask}; - wire [(32+`NUM_THREADS)-1:0] q_end = {32'b0, orig_tmask}; - - VX_ipdom_stack #( - .WIDTH (32+`NUM_THREADS), - .DEPTH (2 ** (`NT_BITS+1)) - ) ipdom_stack ( - .clk (clk), - .reset (reset), - .push (push), - .pop (pop), - .pair (warp_ctl_if.split.diverged), - .q1 (q_end), - .q2 (q_else), - .d (ipdom_data[i]), - .index (ipdom_index[i]), - `UNUSED_PIN (empty), - `UNUSED_PIN (full) - ); - end - - assign {join_pc, join_tmask} = ipdom_data[join_if.wid]; - assign join_else = ~ipdom_index[join_if.wid]; - - // schedule the next ready warp - - wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls); - - VX_lzc #( - .N (`NUM_WARPS) - ) wid_select ( - .in_i (ready_warps), - .cnt_o (schedule_wid), - .valid_o (schedule_valid) - ); - - wire [`NUM_WARPS-1:0][(`NUM_THREADS + 32)-1:0] schedule_data; - for (genvar i = 0; i < `NUM_WARPS; ++i) begin - assign schedule_data[i] = {(use_wspawn[i] ? `NUM_THREADS'(1) : thread_masks[i]), - (use_wspawn[i] ? wspawn_pc : warp_pcs[i])}; - end - - assign {schedule_tmask, schedule_pc} = schedule_data[schedule_wid]; - - wire stall_out = ~ifetch_req_if.ready && ifetch_req_if.valid; - - assign warp_scheduled = schedule_valid && ~stall_out; - - wire [`UUID_BITS-1:0] instr_uuid = (issued_instrs * `NUM_CORES * `NUM_CLUSTERS) + `UUID_BITS'(CORE_ID); - - VX_pipe_register #( - .DATAW (1 + `UUID_BITS + `NUM_THREADS + 32 + `NW_BITS), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall_out), - .data_in ({schedule_valid, instr_uuid, schedule_tmask, schedule_pc, schedule_wid}), - .data_out ({ifetch_req_if.valid, ifetch_req_if.uuid, ifetch_req_if.tmask, ifetch_req_if.PC, ifetch_req_if.wid}) - ); - - assign busy = (active_warps != 0); - - `SCOPE_ASSIGN (wsched_scheduled, warp_scheduled); - `SCOPE_ASSIGN (wsched_schedule_uuid, instr_uuid); - `SCOPE_ASSIGN (wsched_active_warps, active_warps); - `SCOPE_ASSIGN (wsched_stalled_warps, stalled_warps); - `SCOPE_ASSIGN (wsched_schedule_wid, schedule_wid); - `SCOPE_ASSIGN (wsched_schedule_tmask, schedule_tmask); - `SCOPE_ASSIGN (wsched_schedule_pc, schedule_pc); - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_writeback.sv b/hw/rtl/VX_writeback.sv deleted file mode 100644 index f4471046..00000000 --- a/hw/rtl/VX_writeback.sv +++ /dev/null @@ -1,113 +0,0 @@ -`include "VX_define.vh" - -module VX_writeback #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // inputs - VX_commit_if.slave alu_commit_if, - VX_commit_if.slave ld_commit_if, - VX_commit_if.slave csr_commit_if, -`ifdef EXT_F_ENABLE - VX_commit_if.slave fpu_commit_if, -`endif - VX_commit_if.slave gpu_commit_if, - - // outputs - VX_writeback_if.master writeback_if -); - - `UNUSED_PARAM (CORE_ID) - - localparam DATAW = `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32) + 1; -`ifdef EXT_F_ENABLE - localparam NUM_RSPS = 5; -`else - localparam NUM_RSPS = 4; -`endif - - wire wb_valid; - wire [`NW_BITS-1:0] wb_wid; - wire [31:0] wb_PC; - wire [`NUM_THREADS-1:0] wb_tmask; - wire [`NR_BITS-1:0] wb_rd; - wire [`NUM_THREADS-1:0][31:0] wb_data; - wire wb_eop; - - wire [NUM_RSPS-1:0] rsp_valid; - wire [NUM_RSPS-1:0][DATAW-1:0] rsp_data; - wire [NUM_RSPS-1:0] rsp_ready; - wire stall; - - assign rsp_valid = { - gpu_commit_if.valid && gpu_commit_if.wb, - csr_commit_if.valid && csr_commit_if.wb, - alu_commit_if.valid && alu_commit_if.wb, - `ifdef EXT_F_ENABLE - fpu_commit_if.valid && fpu_commit_if.wb, - `endif - ld_commit_if.valid && ld_commit_if.wb - }; - - assign rsp_data = { - {gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.rd, gpu_commit_if.data, gpu_commit_if.eop}, - {csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.rd, csr_commit_if.data, csr_commit_if.eop}, - {alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.rd, alu_commit_if.data, alu_commit_if.eop}, - `ifdef EXT_F_ENABLE - {fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.rd, fpu_commit_if.data, fpu_commit_if.eop}, - `endif - { ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.rd, ld_commit_if.data, ld_commit_if.eop} - }; - - VX_stream_arbiter #( - .NUM_REQS (NUM_RSPS), - .DATAW (DATAW), - .BUFFERED (1), - .TYPE ("R") - ) rsp_arb ( - .clk (clk), - .reset (reset), - .valid_in (rsp_valid), - .data_in (rsp_data), - .ready_in (rsp_ready), - .valid_out (wb_valid), - .data_out ({wb_wid, wb_PC, wb_tmask, wb_rd, wb_data, wb_eop}), - .ready_out (~stall) - ); - - assign ld_commit_if.ready = rsp_ready[0] || ~ld_commit_if.wb; -`ifdef EXT_F_ENABLE - assign fpu_commit_if.ready = rsp_ready[1] || ~fpu_commit_if.wb; - assign alu_commit_if.ready = rsp_ready[2] || ~alu_commit_if.wb; - assign csr_commit_if.ready = rsp_ready[3] || ~csr_commit_if.wb; - assign gpu_commit_if.ready = rsp_ready[4] || ~gpu_commit_if.wb; -`else - assign alu_commit_if.ready = rsp_ready[1] || ~alu_commit_if.wb; - assign csr_commit_if.ready = rsp_ready[2] || ~csr_commit_if.wb; - assign gpu_commit_if.ready = rsp_ready[3] || ~gpu_commit_if.wb; -`endif - - assign stall = ~writeback_if.ready && writeback_if.valid; - - VX_pipe_register #( - .DATAW (1 + DATAW), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (~stall), - .data_in ({wb_valid, wb_wid, wb_PC, wb_tmask, wb_rd, wb_data, wb_eop}), - .data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop}) - ); - - // special workaround to get RISC-V tests Pass/Fail status - reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */; - always @(posedge clk) begin - if (writeback_if.valid && writeback_if.ready) begin - last_wb_value[writeback_if.rd] <= writeback_if.data[0]; - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex.sv b/hw/rtl/Vortex.sv index c97f6bcf..833c6860 100644 --- a/hw/rtl/Vortex.sv +++ b/hw/rtl/Vortex.sv @@ -1,7 +1,20 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_define.vh" -module Vortex ( - `SCOPE_IO_Vortex +module Vortex import VX_gpu_pkg::*; ( + `SCOPE_IO_DECL // Clock input wire clk, @@ -22,204 +35,224 @@ module Vortex ( input wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag, output wire mem_rsp_ready, + // DCR write request + input wire dcr_wr_valid, + input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr, + input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data, + // Status output wire busy ); - `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter")) - wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready; +`ifdef PERF_ENABLE + VX_mem_perf_if mem_perf_if[`NUM_CLUSTERS](); + VX_mem_perf_if perf_memsys_total_if(); + VX_cache_perf_if perf_l3cache_if(); +`endif - wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready; + VX_mem_bus_if #( + .DATA_SIZE (`L3_LINE_SIZE), + .TAG_WIDTH (L3_MEM_TAG_WIDTH) + ) mem_bus_if(); - wire [`NUM_CLUSTERS-1:0] per_cluster_busy; + assign mem_req_valid = mem_bus_if.req_valid; + assign mem_req_rw = mem_bus_if.req_data.rw; + assign mem_req_byteen= mem_bus_if.req_data.byteen; + assign mem_req_addr = mem_bus_if.req_data.addr; + assign mem_req_data = mem_bus_if.req_data.data; + assign mem_req_tag = mem_bus_if.req_data.tag; + assign mem_bus_if.req_ready = mem_req_ready; - for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin + assign mem_bus_if.rsp_valid = mem_rsp_valid; + assign mem_bus_if.rsp_data.data = mem_rsp_data; + assign mem_bus_if.rsp_data.tag = mem_rsp_tag; + assign mem_rsp_ready = mem_bus_if.rsp_ready; - `RESET_RELAY (cluster_reset); + wire mem_req_fire = mem_req_valid && mem_req_ready; + wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; + `UNUSED_VAR (mem_req_fire) + `UNUSED_VAR (mem_rsp_fire) + + wire sim_ebreak /* verilator public */; + wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value /* verilator public */; + wire [`NUM_CLUSTERS-1:0] per_cluster_sim_ebreak; + wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_cluster_sim_wb_value; + assign sim_ebreak = per_cluster_sim_ebreak[0]; + assign sim_wb_value = per_cluster_sim_wb_value[0]; + `UNUSED_VAR (per_cluster_sim_ebreak) + `UNUSED_VAR (per_cluster_sim_wb_value) + + VX_mem_bus_if #( + .DATA_SIZE (`L2_LINE_SIZE), + .TAG_WIDTH (L2_MEM_TAG_WIDTH) + ) per_cluster_mem_bus_if[`NUM_CLUSTERS](); + + VX_dcr_bus_if dcr_bus_if(); + assign dcr_bus_if.write_valid = dcr_wr_valid; + assign dcr_bus_if.write_addr = dcr_wr_addr; + assign dcr_bus_if.write_data = dcr_wr_data; + + wire [`NUM_CLUSTERS-1:0] per_cluster_busy; + + `SCOPE_IO_SWITCH (`NUM_CLUSTERS) + + // Generate all clusters + for (genvar i = 0; i < `NUM_CLUSTERS; ++i) begin + + `RESET_RELAY (cluster_reset, reset); + + `BUFFER_DCR_BUS_IF (cluster_dcr_bus_if, dcr_bus_if, (`NUM_CLUSTERS > 1)); VX_cluster #( - .CLUSTER_ID(i) + .CLUSTER_ID (i) ) cluster ( - `SCOPE_BIND_Vortex_cluster(i) + `SCOPE_IO_BIND (i) - .clk (clk), - .reset (cluster_reset), - - .mem_req_valid (per_cluster_mem_req_valid [i]), - .mem_req_rw (per_cluster_mem_req_rw [i]), - .mem_req_byteen (per_cluster_mem_req_byteen[i]), - .mem_req_addr (per_cluster_mem_req_addr [i]), - .mem_req_data (per_cluster_mem_req_data [i]), - .mem_req_tag (per_cluster_mem_req_tag [i]), - .mem_req_ready (per_cluster_mem_req_ready [i]), - - .mem_rsp_valid (per_cluster_mem_rsp_valid [i]), - .mem_rsp_data (per_cluster_mem_rsp_data [i]), - .mem_rsp_tag (per_cluster_mem_rsp_tag [i]), - .mem_rsp_ready (per_cluster_mem_rsp_ready [i]), - - .busy (per_cluster_busy [i]) - ); - end - - assign busy = (| per_cluster_busy); - - if (`L3_ENABLE) begin - `ifdef PERF_ENABLE - VX_perf_cache_if perf_l3cache_if(); - `endif - - `RESET_RELAY (l3_reset); - - VX_cache #( - .CACHE_ID (`L3_CACHE_ID), - .CACHE_SIZE (`L3_CACHE_SIZE), - .CACHE_LINE_SIZE (`L3_CACHE_LINE_SIZE), - .NUM_BANKS (`L3_NUM_BANKS), - .NUM_PORTS (`L3_NUM_PORTS), - .WORD_SIZE (`L3_WORD_SIZE), - .NUM_REQS (`L3_NUM_REQS), - .CREQ_SIZE (`L3_CREQ_SIZE), - .CRSQ_SIZE (`L3_CRSQ_SIZE), - .MSHR_SIZE (`L3_MSHR_SIZE), - .MRSQ_SIZE (`L3_MRSQ_SIZE), - .MREQ_SIZE (`L3_MREQ_SIZE), - .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`L2_MEM_TAG_WIDTH), - .CORE_TAG_ID_BITS (0), - .MEM_TAG_WIDTH (`L3_MEM_TAG_WIDTH), - .NC_ENABLE (1) - ) l3cache ( - `SCOPE_BIND_Vortex_l3cache - .clk (clk), - .reset (l3_reset), + .reset (cluster_reset), `ifdef PERF_ENABLE - .perf_cache_if (perf_l3cache_if), + .mem_perf_if (mem_perf_if[i]), + .perf_memsys_total_if (perf_memsys_total_if), `endif - - // Core request - .core_req_valid (per_cluster_mem_req_valid), - .core_req_rw (per_cluster_mem_req_rw), - .core_req_byteen (per_cluster_mem_req_byteen), - .core_req_addr (per_cluster_mem_req_addr), - .core_req_data (per_cluster_mem_req_data), - .core_req_tag (per_cluster_mem_req_tag), - .core_req_ready (per_cluster_mem_req_ready), - - // Core response - .core_rsp_valid (per_cluster_mem_rsp_valid), - .core_rsp_data (per_cluster_mem_rsp_data), - .core_rsp_tag (per_cluster_mem_rsp_tag), - .core_rsp_ready (per_cluster_mem_rsp_ready), - `UNUSED_PIN (core_rsp_tmask), - - // Memory request - .mem_req_valid (mem_req_valid), - .mem_req_rw (mem_req_rw), - .mem_req_byteen (mem_req_byteen), - .mem_req_addr (mem_req_addr), - .mem_req_data (mem_req_data), - .mem_req_tag (mem_req_tag), - .mem_req_ready (mem_req_ready), - - // Memory response - .mem_rsp_valid (mem_rsp_valid), - .mem_rsp_data (mem_rsp_data), - .mem_rsp_tag (mem_rsp_tag), - .mem_rsp_ready (mem_rsp_ready) - ); - - end else begin - - `RESET_RELAY (mem_arb_reset); - - VX_mem_arb #( - .NUM_REQS (`NUM_CLUSTERS), - .DATA_WIDTH (`L3_MEM_DATA_WIDTH), - .ADDR_WIDTH (`L3_MEM_ADDR_WIDTH), - .TAG_IN_WIDTH (`L2_MEM_TAG_WIDTH), - .TYPE ("R"), - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) - ) mem_arb ( - .clk (clk), - .reset (mem_arb_reset), - - // Core request - .req_valid_in (per_cluster_mem_req_valid), - .req_rw_in (per_cluster_mem_req_rw), - .req_byteen_in (per_cluster_mem_req_byteen), - .req_addr_in (per_cluster_mem_req_addr), - .req_data_in (per_cluster_mem_req_data), - .req_tag_in (per_cluster_mem_req_tag), - .req_ready_in (per_cluster_mem_req_ready), - - // Memory request - .req_valid_out (mem_req_valid), - .req_rw_out (mem_req_rw), - .req_byteen_out (mem_req_byteen), - .req_addr_out (mem_req_addr), - .req_data_out (mem_req_data), - .req_tag_out (mem_req_tag), - .req_ready_out (mem_req_ready), - - // Core response - .rsp_valid_out (per_cluster_mem_rsp_valid), - .rsp_data_out (per_cluster_mem_rsp_data), - .rsp_tag_out (per_cluster_mem_rsp_tag), - .rsp_ready_out (per_cluster_mem_rsp_ready), - // Memory response - .rsp_valid_in (mem_rsp_valid), - .rsp_tag_in (mem_rsp_tag), - .rsp_data_in (mem_rsp_data), - .rsp_ready_in (mem_rsp_ready) - ); + .dcr_bus_if (cluster_dcr_bus_if), + .mem_bus_if (per_cluster_mem_bus_if[i]), + + .sim_ebreak (per_cluster_sim_ebreak[i]), + .sim_wb_value (per_cluster_sim_wb_value[i]), + + .busy (per_cluster_busy[i]) + ); end - `SCOPE_ASSIGN (reset, reset); - `SCOPE_ASSIGN (mem_req_fire, mem_req_valid && mem_req_ready); - `SCOPE_ASSIGN (mem_req_addr, `TO_FULL_ADDR(mem_req_addr)); - `SCOPE_ASSIGN (mem_req_rw, mem_req_rw); - `SCOPE_ASSIGN (mem_req_byteen, mem_req_byteen); - `SCOPE_ASSIGN (mem_req_data, mem_req_data); - `SCOPE_ASSIGN (mem_req_tag, mem_req_tag); - `SCOPE_ASSIGN (mem_rsp_fire, mem_rsp_valid && mem_rsp_ready); - `SCOPE_ASSIGN (mem_rsp_data, mem_rsp_data); - `SCOPE_ASSIGN (mem_rsp_tag, mem_rsp_tag); - `SCOPE_ASSIGN (busy, busy); + `BUFFER_BUSY (busy, (| per_cluster_busy), (`NUM_CLUSTERS > 1)); + + `RESET_RELAY (l3_reset, reset); + + VX_cache_wrap #( + .INSTANCE_ID ("l3cache"), + .CACHE_SIZE (`L3_CACHE_SIZE), + .LINE_SIZE (`L3_LINE_SIZE), + .NUM_BANKS (`L3_NUM_BANKS), + .NUM_WAYS (`L3_NUM_WAYS), + .WORD_SIZE (L3_WORD_SIZE), + .NUM_REQS (L3_NUM_REQS), + .CRSQ_SIZE (`L3_CRSQ_SIZE), + .MSHR_SIZE (`L3_MSHR_SIZE), + .MRSQ_SIZE (`L3_MRSQ_SIZE), + .MREQ_SIZE (`L3_MREQ_SIZE), + .TAG_WIDTH (L2_MEM_TAG_WIDTH), + .WRITE_ENABLE (1), + .UUID_WIDTH (`UUID_WIDTH), + .CORE_OUT_REG (2), + .MEM_OUT_REG (2), + .NC_ENABLE (1), + .PASSTHRU (!`L3_ENABLED) + ) l3cache ( + .clk (clk), + .reset (l3_reset), + + `ifdef PERF_ENABLE + .cache_perf_if (perf_l3cache_if), + `endif + + .core_bus_if (per_cluster_mem_bus_if), + .mem_bus_if (mem_bus_if) + ); + +`ifdef PERF_ENABLE + + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, icache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, icache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, dcache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, dcache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, dcache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, dcache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, dcache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, dcache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, smem_reads, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, smem_writes, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, smem_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, l2cache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, l2cache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, l2cache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, l2cache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, l2cache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS); + `PERF_REDUCE (perf_memsys_total_if, mem_perf_if, l2cache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS); + +`ifdef L3_ENABLE + assign perf_memsys_total_if.l3cache_reads = perf_l3cache_if.reads; + assign perf_memsys_total_if.l3cache_writes = perf_l3cache_if.writes; + assign perf_memsys_total_if.l3cache_read_misses = perf_l3cache_if.read_misses; + assign perf_memsys_total_if.l3cache_write_misses= perf_l3cache_if.write_misses; + assign perf_memsys_total_if.l3cache_bank_stalls = perf_l3cache_if.bank_stalls; + assign perf_memsys_total_if.l3cache_mshr_stalls = perf_l3cache_if.mshr_stalls; +`else + assign perf_memsys_total_if.l3cache_reads = '0; + assign perf_memsys_total_if.l3cache_writes = '0; + assign perf_memsys_total_if.l3cache_read_misses = '0; + assign perf_memsys_total_if.l3cache_write_misses= '0; + assign perf_memsys_total_if.l3cache_bank_stalls = '0; + assign perf_memsys_total_if.l3cache_mshr_stalls = '0; +`endif + + reg [`PERF_CTR_BITS-1:0] perf_mem_pending_reads; + + always @(posedge clk) begin + if (reset) begin + perf_mem_pending_reads <= '0; + end else begin + perf_mem_pending_reads <= $signed(perf_mem_pending_reads) + + `PERF_CTR_BITS'($signed(2'(mem_req_fire && ~mem_bus_if.req_data.rw) - 2'(mem_rsp_fire))); + end + end + + reg [`PERF_CTR_BITS-1:0] perf_mem_reads; + reg [`PERF_CTR_BITS-1:0] perf_mem_writes; + reg [`PERF_CTR_BITS-1:0] perf_mem_lat; + + always @(posedge clk) begin + if (reset) begin + perf_mem_reads <= '0; + perf_mem_writes <= '0; + perf_mem_lat <= '0; + end else begin + if (mem_req_fire && ~mem_bus_if.req_data.rw) begin + perf_mem_reads <= perf_mem_reads + `PERF_CTR_BITS'(1); + end + if (mem_req_fire && mem_bus_if.req_data.rw) begin + perf_mem_writes <= perf_mem_writes + `PERF_CTR_BITS'(1); + end + perf_mem_lat <= perf_mem_lat + perf_mem_pending_reads; + end + end + + assign perf_memsys_total_if.mem_reads = perf_mem_reads; + assign perf_memsys_total_if.mem_writes = perf_mem_writes; + assign perf_memsys_total_if.mem_latency = perf_mem_lat; + +`endif `ifdef DBG_TRACE_CORE_MEM always @(posedge clk) begin - if (mem_req_valid && mem_req_ready) begin + if (mem_req_fire) begin if (mem_req_rw) - dpi_trace("%d: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data); + `TRACE(1, ("%d: MEM Wr Req: addr=0x%0h, tag=0x%0h, byteen=0x%0h data=0x%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data)); else - dpi_trace("%d: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen); + `TRACE(1, ("%d: MEM Rd Req: addr=0x%0h, tag=0x%0h, byteen=0x%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen)); end - if (mem_rsp_valid && mem_rsp_ready) begin - dpi_trace("%d: MEM Rsp: tag=%0h, data=%0h\n", $time, mem_rsp_tag, mem_rsp_data); + if (mem_rsp_fire) begin + `TRACE(1, ("%d: MEM Rsp: tag=0x%0h, data=0x%0h\n", $time, mem_rsp_tag, mem_rsp_data)); end end `endif - -`ifndef NDEBUG +`ifdef SIMULATION always @(posedge clk) begin $fflush(); // flush stdout buffer end `endif -endmodule \ No newline at end of file +endmodule diff --git a/hw/rtl/Vortex_axi.sv b/hw/rtl/Vortex_axi.sv index 000e0bcb..e68d4e7a 100644 --- a/hw/rtl/Vortex_axi.sv +++ b/hw/rtl/Vortex_axi.sv @@ -1,65 +1,91 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_define.vh" -module Vortex_axi #( - parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH, - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH, - parameter AXI_STROBE_WIDTH = (`VX_MEM_DATA_WIDTH / 8) +module Vortex_axi import VX_gpu_pkg::*; #( + parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH, + parameter AXI_ADDR_WIDTH = `XLEN, + parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH, + parameter AXI_NUM_BANKS = 1 )( + `SCOPE_IO_DECL + // Clock input wire clk, input wire reset, // AXI write request address channel - output wire [AXI_TID_WIDTH-1:0] m_axi_awid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [7:0] m_axi_awlen, - output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, - output wire m_axi_awlock, - output wire [3:0] m_axi_awcache, - output wire [2:0] m_axi_awprot, - output wire [3:0] m_axi_awqos, - output wire m_axi_awvalid, - input wire m_axi_awready, + output wire m_axi_awvalid [AXI_NUM_BANKS], + input wire m_axi_awready [AXI_NUM_BANKS], + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr [AXI_NUM_BANKS], + output wire [AXI_TID_WIDTH-1:0] m_axi_awid [AXI_NUM_BANKS], + output wire [7:0] m_axi_awlen [AXI_NUM_BANKS], + output wire [2:0] m_axi_awsize [AXI_NUM_BANKS], + output wire [1:0] m_axi_awburst [AXI_NUM_BANKS], + output wire [1:0] m_axi_awlock [AXI_NUM_BANKS], + output wire [3:0] m_axi_awcache [AXI_NUM_BANKS], + output wire [2:0] m_axi_awprot [AXI_NUM_BANKS], + output wire [3:0] m_axi_awqos [AXI_NUM_BANKS], + output wire [3:0] m_axi_awregion [AXI_NUM_BANKS], // AXI write request data channel - output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, - output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, - output wire m_axi_wlast, - output wire m_axi_wvalid, - input wire m_axi_wready, + output wire m_axi_wvalid [AXI_NUM_BANKS], + input wire m_axi_wready [AXI_NUM_BANKS], + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata [AXI_NUM_BANKS], + output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb [AXI_NUM_BANKS], + output wire m_axi_wlast [AXI_NUM_BANKS], // AXI write response channel - input wire [AXI_TID_WIDTH-1:0] m_axi_bid, - input wire [1:0] m_axi_bresp, - input wire m_axi_bvalid, - output wire m_axi_bready, + input wire m_axi_bvalid [AXI_NUM_BANKS], + output wire m_axi_bready [AXI_NUM_BANKS], + input wire [AXI_TID_WIDTH-1:0] m_axi_bid [AXI_NUM_BANKS], + input wire [1:0] m_axi_bresp [AXI_NUM_BANKS], // AXI read request channel - output wire [AXI_TID_WIDTH-1:0] m_axi_arid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, - output wire [7:0] m_axi_arlen, - output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [3:0] m_axi_arcache, - output wire [2:0] m_axi_arprot, - output wire [3:0] m_axi_arqos, - output wire m_axi_arvalid, - input wire m_axi_arready, + output wire m_axi_arvalid [AXI_NUM_BANKS], + input wire m_axi_arready [AXI_NUM_BANKS], + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr [AXI_NUM_BANKS], + output wire [AXI_TID_WIDTH-1:0] m_axi_arid [AXI_NUM_BANKS], + output wire [7:0] m_axi_arlen [AXI_NUM_BANKS], + output wire [2:0] m_axi_arsize [AXI_NUM_BANKS], + output wire [1:0] m_axi_arburst [AXI_NUM_BANKS], + output wire [1:0] m_axi_arlock [AXI_NUM_BANKS], + output wire [3:0] m_axi_arcache [AXI_NUM_BANKS], + output wire [2:0] m_axi_arprot [AXI_NUM_BANKS], + output wire [3:0] m_axi_arqos [AXI_NUM_BANKS], + output wire [3:0] m_axi_arregion [AXI_NUM_BANKS], // AXI read response channel - input wire [AXI_TID_WIDTH-1:0] m_axi_rid, - input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, - input wire [1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire m_axi_rvalid, - output wire m_axi_rready, + input wire m_axi_rvalid [AXI_NUM_BANKS], + output wire m_axi_rready [AXI_NUM_BANKS], + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata [AXI_NUM_BANKS], + input wire m_axi_rlast [AXI_NUM_BANKS], + input wire [AXI_TID_WIDTH-1:0] m_axi_rid [AXI_NUM_BANKS], + input wire [1:0] m_axi_rresp [AXI_NUM_BANKS], + + // DCR write request + input wire dcr_wr_valid, + input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr, + input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data, // Status output wire busy ); + `STATIC_ASSERT((AXI_DATA_WIDTH == `VX_MEM_DATA_WIDTH), ("invalid memory data size: current=%0d, expected=%0d", AXI_DATA_WIDTH, `VX_MEM_DATA_WIDTH)) + `STATIC_ASSERT((AXI_ADDR_WIDTH >= `XLEN), ("invalid memory address size: current=%0d, expected=%0d", AXI_ADDR_WIDTH, `VX_MEM_ADDR_WIDTH)) + //`STATIC_ASSERT((AXI_TID_WIDTH >= `VX_MEM_TAG_WIDTH), ("invalid memory tag size: current=%0d, expected=%0d", AXI_TID_WIDTH, `VX_MEM_TAG_WIDTH)) + wire mem_req_valid; wire mem_req_rw; wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen; @@ -72,16 +98,33 @@ module Vortex_axi #( wire [`VX_MEM_DATA_WIDTH-1:0] mem_rsp_data; wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag; wire mem_rsp_ready; + + wire [`XLEN-1:0] m_axi_awaddr_unqual [AXI_NUM_BANKS]; + wire [`XLEN-1:0] m_axi_araddr_unqual [AXI_NUM_BANKS]; + + wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_awid_unqual [AXI_NUM_BANKS]; + wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_arid_unqual [AXI_NUM_BANKS]; + + wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_bid_unqual [AXI_NUM_BANKS]; + wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_rid_unqual [AXI_NUM_BANKS]; + + for (genvar i = 0; i < AXI_NUM_BANKS; ++i) begin + assign m_axi_awaddr[i] = `XLEN'(m_axi_awaddr_unqual[i]); + assign m_axi_araddr[i] = `XLEN'(m_axi_araddr_unqual[i]); + + assign m_axi_awid[i] = AXI_TID_WIDTH'(m_axi_awid_unqual[i]); + assign m_axi_arid[i] = AXI_TID_WIDTH'(m_axi_arid_unqual[i]); + + assign m_axi_rid_unqual[i] = `VX_MEM_TAG_WIDTH'(m_axi_rid[i]); + assign m_axi_bid_unqual[i] = `VX_MEM_TAG_WIDTH'(m_axi_bid[i]); + end VX_axi_adapter #( - .VX_DATA_WIDTH (`VX_MEM_DATA_WIDTH), - .VX_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH), - .VX_TAG_WIDTH (`VX_MEM_TAG_WIDTH), - .VX_BYTEEN_WIDTH (AXI_STROBE_WIDTH), - .AXI_DATA_WIDTH (AXI_DATA_WIDTH), - .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), - .AXI_TID_WIDTH (AXI_TID_WIDTH), - .AXI_STROBE_WIDTH (AXI_STROBE_WIDTH) + .DATA_WIDTH (`VX_MEM_DATA_WIDTH), + .ADDR_WIDTH (`XLEN), + .TAG_WIDTH (`VX_MEM_TAG_WIDTH), + .NUM_BANKS (AXI_NUM_BANKS), + .OUT_REG_RSP((AXI_NUM_BANKS > 1) ? 2 : 0) ) axi_adapter ( .clk (clk), .reset (reset), @@ -98,9 +141,11 @@ module Vortex_axi #( .mem_rsp_data (mem_rsp_data), .mem_rsp_tag (mem_rsp_tag), .mem_rsp_ready (mem_rsp_ready), - - .m_axi_awid (m_axi_awid), - .m_axi_awaddr (m_axi_awaddr), + + .m_axi_awvalid (m_axi_awvalid), + .m_axi_awready (m_axi_awready), + .m_axi_awaddr (m_axi_awaddr_unqual), + .m_axi_awid (m_axi_awid_unqual), .m_axi_awlen (m_axi_awlen), .m_axi_awsize (m_axi_awsize), .m_axi_awburst (m_axi_awburst), @@ -108,22 +153,23 @@ module Vortex_axi #( .m_axi_awcache (m_axi_awcache), .m_axi_awprot (m_axi_awprot), .m_axi_awqos (m_axi_awqos), - .m_axi_awvalid (m_axi_awvalid), - .m_axi_awready (m_axi_awready), + .m_axi_awregion (m_axi_awregion), + .m_axi_wvalid (m_axi_wvalid), + .m_axi_wready (m_axi_wready), .m_axi_wdata (m_axi_wdata), .m_axi_wstrb (m_axi_wstrb), .m_axi_wlast (m_axi_wlast), - .m_axi_wvalid (m_axi_wvalid), - .m_axi_wready (m_axi_wready), - - .m_axi_bid (m_axi_bid), - .m_axi_bresp (m_axi_bresp), + .m_axi_bvalid (m_axi_bvalid), .m_axi_bready (m_axi_bready), + .m_axi_bid (m_axi_bid_unqual), + .m_axi_bresp (m_axi_bresp), - .m_axi_arid (m_axi_arid), - .m_axi_araddr (m_axi_araddr), + .m_axi_arvalid (m_axi_arvalid), + .m_axi_arready (m_axi_arready), + .m_axi_araddr (m_axi_araddr_unqual), + .m_axi_arid (m_axi_arid_unqual), .m_axi_arlen (m_axi_arlen), .m_axi_arsize (m_axi_arsize), .m_axi_arburst (m_axi_arburst), @@ -131,18 +177,21 @@ module Vortex_axi #( .m_axi_arcache (m_axi_arcache), .m_axi_arprot (m_axi_arprot), .m_axi_arqos (m_axi_arqos), - .m_axi_arvalid (m_axi_arvalid), - .m_axi_arready (m_axi_arready), + .m_axi_arregion (m_axi_arregion), - .m_axi_rid (m_axi_rid), - .m_axi_rdata (m_axi_rdata), - .m_axi_rresp (m_axi_rresp), - .m_axi_rlast (m_axi_rlast), .m_axi_rvalid (m_axi_rvalid), - .m_axi_rready (m_axi_rready) + .m_axi_rready (m_axi_rready), + .m_axi_rdata (m_axi_rdata), + .m_axi_rlast (m_axi_rlast) , + .m_axi_rid (m_axi_rid_unqual), + .m_axi_rresp (m_axi_rresp) ); + + `SCOPE_IO_SWITCH (1) Vortex vortex ( + `SCOPE_IO_BIND (0) + .clk (clk), .reset (reset), @@ -159,7 +208,11 @@ module Vortex_axi #( .mem_rsp_tag (mem_rsp_tag), .mem_rsp_ready (mem_rsp_ready), + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data), + .busy (busy) ); -endmodule \ No newline at end of file +endmodule diff --git a/hw/rtl/afu/VX_avs_wrapper.sv b/hw/rtl/afu/VX_avs_wrapper.sv deleted file mode 100644 index c9aaf0e7..00000000 --- a/hw/rtl/afu/VX_avs_wrapper.sv +++ /dev/null @@ -1,176 +0,0 @@ -`include "VX_define.vh" - -module VX_avs_wrapper #( - parameter AVS_DATA_WIDTH = 1, - parameter AVS_ADDR_WIDTH = 1, - parameter AVS_BURST_WIDTH = 1, - parameter AVS_BANKS = 1, - parameter REQ_TAG_WIDTH = 1, - parameter RD_QUEUE_SIZE = 1, - - parameter AVS_BYTEENW = (AVS_DATA_WIDTH / 8), - parameter RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1) -) ( - input wire clk, - input wire reset, - - // Memory request - input wire mem_req_valid, - input wire mem_req_rw, - input wire [AVS_BYTEENW-1:0] mem_req_byteen, - input wire [AVS_ADDR_WIDTH-1:0] mem_req_addr, - input wire [AVS_DATA_WIDTH-1:0] mem_req_data, - input wire [REQ_TAG_WIDTH-1:0] mem_req_tag, - output wire mem_req_ready, - - // Memory response - output wire mem_rsp_valid, - output wire [AVS_DATA_WIDTH-1:0] mem_rsp_data, - output wire [REQ_TAG_WIDTH-1:0] mem_rsp_tag, - input wire mem_rsp_ready, - - // AVS bus - output wire [AVS_DATA_WIDTH-1:0] avs_writedata [AVS_BANKS], - input wire [AVS_DATA_WIDTH-1:0] avs_readdata [AVS_BANKS], - output wire [AVS_ADDR_WIDTH-1:0] avs_address [AVS_BANKS], - input wire avs_waitrequest [AVS_BANKS], - output wire avs_write [AVS_BANKS], - output wire avs_read [AVS_BANKS], - output wire [AVS_BYTEENW-1:0] avs_byteenable [AVS_BANKS], - output wire [AVS_BURST_WIDTH-1:0] avs_burstcount [AVS_BANKS], - input avs_readdatavalid [AVS_BANKS] -); - - localparam BANK_ADDRW = `LOG2UP(AVS_BANKS); - - // Requests handling - - wire [AVS_BANKS-1:0] avs_reqq_push, avs_reqq_pop, avs_reqq_ready; - wire [AVS_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_tag_out; - wire [AVS_BANKS-1:0] req_queue_going_full; - wire [AVS_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size; - wire [BANK_ADDRW-1:0] req_bank_sel; - - if (AVS_BANKS >= 2) begin - assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0]; - end else begin - assign req_bank_sel = 0; - end - - for (genvar i = 0; i < AVS_BANKS; i++) begin - assign avs_reqq_ready[i] = !req_queue_going_full[i] && !avs_waitrequest[i]; - assign avs_reqq_push[i] = mem_req_valid && !mem_req_rw && avs_reqq_ready[i] && (req_bank_sel == i); - end - - for (genvar i = 0; i < AVS_BANKS; i++) begin - VX_pending_size #( - .SIZE (RD_QUEUE_SIZE) - ) pending_size ( - .clk (clk), - .reset (reset), - .incr (avs_reqq_push[i]), - .decr (avs_reqq_pop[i]), - .full (req_queue_going_full[i]), - .size (req_queue_size[i]), - `UNUSED_PIN (empty) - ); - `UNUSED_VAR (req_queue_size) - - VX_fifo_queue #( - .DATAW (REQ_TAG_WIDTH), - .SIZE (RD_QUEUE_SIZE) - ) rd_req_queue ( - .clk (clk), - .reset (reset), - .push (avs_reqq_push[i]), - .pop (avs_reqq_pop[i]), - .data_in (mem_req_tag), - .data_out (avs_reqq_tag_out[i]), - `UNUSED_PIN (empty), - `UNUSED_PIN (full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (alm_full), - `UNUSED_PIN (size) - ); - end - - for (genvar i = 0; i < AVS_BANKS; i++) begin - assign avs_read[i] = mem_req_valid && !mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i); - assign avs_write[i] = mem_req_valid && mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i); - assign avs_address[i] = mem_req_addr; - assign avs_byteenable[i] = mem_req_byteen; - assign avs_writedata[i] = mem_req_data; - assign avs_burstcount[i] = AVS_BURST_WIDTH'(1); - end - - if (AVS_BANKS >= 2) begin - assign mem_req_ready = avs_reqq_ready[req_bank_sel]; - end else begin - assign mem_req_ready = avs_reqq_ready; - end - - // Responses handling - - wire [AVS_BANKS-1:0] rsp_arb_valid_in; - wire [AVS_BANKS-1:0][AVS_DATA_WIDTH+REQ_TAG_WIDTH-1:0] rsp_arb_data_in; - wire [AVS_BANKS-1:0] rsp_arb_ready_in; - - wire [AVS_BANKS-1:0][AVS_DATA_WIDTH-1:0] avs_rspq_data_out; - wire [AVS_BANKS-1:0] avs_rspq_empty; - - for (genvar i = 0; i < AVS_BANKS; i++) begin - VX_fifo_queue #( - .DATAW (AVS_DATA_WIDTH), - .SIZE (RD_QUEUE_SIZE) - ) rd_rsp_queue ( - .clk (clk), - .reset (reset), - .push (avs_readdatavalid[i]), - .pop (avs_reqq_pop[i]), - .data_in (avs_readdata[i]), - .data_out (avs_rspq_data_out[i]), - .empty (avs_rspq_empty[i]), - `UNUSED_PIN (full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (alm_full), - `UNUSED_PIN (size) - ); - end - - for (genvar i = 0; i < AVS_BANKS; i++) begin - assign rsp_arb_valid_in[i] = !avs_rspq_empty[i]; - assign rsp_arb_data_in[i] = {avs_rspq_data_out[i], avs_reqq_tag_out[i]}; - assign avs_reqq_pop[i] = rsp_arb_valid_in[i] && rsp_arb_ready_in[i]; - end - - VX_stream_arbiter #( - .NUM_REQS (AVS_BANKS), - .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), - .TYPE ("R") - ) rsp_arb ( - .clk (clk), - .reset (reset), - .valid_in (rsp_arb_valid_in), - .data_in (rsp_arb_data_in), - .ready_in (rsp_arb_ready_in), - .valid_out (mem_rsp_valid), - .data_out ({mem_rsp_data, mem_rsp_tag}), - .ready_out (mem_rsp_ready) - ); - -`ifdef DBG_TRACE_AFU - always @(posedge clk) begin - if (mem_req_valid && mem_req_ready) begin - if (mem_req_rw) begin - dpi_trace("%d: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, mem_req_data); - end else begin - dpi_trace("%d: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, req_queue_size); - end - end - if (mem_rsp_valid && mem_rsp_ready) begin - dpi_trace("%d: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d\n", $time, mem_rsp_tag, mem_rsp_data, req_queue_size); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/afu/VX_to_mem.sv b/hw/rtl/afu/VX_to_mem.sv deleted file mode 100644 index acc2899b..00000000 --- a/hw/rtl/afu/VX_to_mem.sv +++ /dev/null @@ -1,181 +0,0 @@ -`include "VX_define.vh" - -module VX_to_mem #( - parameter SRC_DATA_WIDTH = 1, - parameter SRC_ADDR_WIDTH = 1, - parameter DST_DATA_WIDTH = 1, - parameter DST_ADDR_WIDTH = 1, - parameter SRC_TAG_WIDTH = 1, - parameter DST_TAG_WIDTH = 1, - parameter SRC_DATA_SIZE = (SRC_DATA_WIDTH / 8), - parameter DST_DATA_SIZE = (DST_DATA_WIDTH / 8) -) ( - input wire clk, - input wire reset, - - input wire mem_req_valid_in, - input wire [SRC_ADDR_WIDTH-1:0] mem_req_addr_in, - input wire mem_req_rw_in, - input wire [SRC_DATA_SIZE-1:0] mem_req_byteen_in, - input wire [SRC_DATA_WIDTH-1:0] mem_req_data_in, - input wire [SRC_TAG_WIDTH-1:0] mem_req_tag_in, - output wire mem_req_ready_in, - - output wire mem_req_valid_out, - output wire [DST_ADDR_WIDTH-1:0] mem_req_addr_out, - output wire mem_req_rw_out, - output wire [DST_DATA_SIZE-1:0] mem_req_byteen_out, - output wire [DST_DATA_WIDTH-1:0] mem_req_data_out, - output wire [DST_TAG_WIDTH-1:0] mem_req_tag_out, - input wire mem_req_ready_out, - - input wire mem_rsp_valid_in, - input wire [DST_DATA_WIDTH-1:0] mem_rsp_data_in, - input wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_in, - output wire mem_rsp_ready_in, - - output wire mem_rsp_valid_out, - output wire [SRC_DATA_WIDTH-1:0] mem_rsp_data_out, - output wire [SRC_TAG_WIDTH-1:0] mem_rsp_tag_out, - input wire mem_rsp_ready_out -); - `STATIC_ASSERT ((DST_TAG_WIDTH >= SRC_TAG_WIDTH), ("oops!")) - - localparam DST_LDATAW = $clog2(DST_DATA_WIDTH); - localparam SRC_LDATAW = $clog2(SRC_DATA_WIDTH); - localparam D = `ABS(DST_LDATAW - SRC_LDATAW); - localparam P = 2**D; - - `UNUSED_VAR (mem_rsp_tag_in) - - if (DST_LDATAW > SRC_LDATAW) begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - wire [D-1:0] req_idx = mem_req_addr_in[D-1:0]; - wire [D-1:0] rsp_idx = mem_rsp_tag_in[D-1:0]; - - wire [SRC_ADDR_WIDTH-D-1:0] mem_req_addr_in_qual = mem_req_addr_in[SRC_ADDR_WIDTH-1:D]; - - wire [P-1:0][SRC_DATA_WIDTH-1:0] mem_rsp_data_in_w = mem_rsp_data_in; - - if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH - D)) begin - `UNUSED_VAR (mem_req_addr_in_qual) - assign mem_req_addr_out = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0]; - end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH - D)) begin - assign mem_req_addr_out = DST_ADDR_WIDTH'(mem_req_addr_in_qual); - end else begin - assign mem_req_addr_out = mem_req_addr_in_qual; - end - - assign mem_req_valid_out = mem_req_valid_in; - assign mem_req_rw_out = mem_req_rw_in; - assign mem_req_byteen_out = DST_DATA_SIZE'(mem_req_byteen_in) << ((DST_LDATAW-3)'(req_idx) << (SRC_LDATAW-3)); - assign mem_req_data_out = DST_DATA_WIDTH'(mem_req_data_in) << ((DST_LDATAW'(req_idx)) << SRC_LDATAW); - assign mem_req_tag_out = DST_TAG_WIDTH'({mem_req_tag_in, req_idx}); - assign mem_req_ready_in = mem_req_ready_out; - - assign mem_rsp_valid_out = mem_rsp_valid_in; - assign mem_rsp_data_out = mem_rsp_data_in_w[rsp_idx]; - assign mem_rsp_tag_out = SRC_TAG_WIDTH'(mem_rsp_tag_in[SRC_TAG_WIDTH+D-1:D]); - assign mem_rsp_ready_in = mem_rsp_ready_out; - - end else if (DST_LDATAW < SRC_LDATAW) begin - - reg [D-1:0] req_ctr, rsp_ctr; - - reg [P-1:0][DST_DATA_WIDTH-1:0] mem_rsp_data_out_r, mem_rsp_data_out_n; - - wire mem_req_out_fire = mem_req_valid_out && mem_req_ready_out; - wire mem_rsp_in_fire = mem_rsp_valid_in && mem_rsp_ready_in; - - wire [P-1:0][DST_DATA_WIDTH-1:0] mem_req_data_in_w = mem_req_data_in; - wire [P-1:0][DST_DATA_SIZE-1:0] mem_req_byteen_in_w = mem_req_byteen_in; - - always @(*) begin - mem_rsp_data_out_n = mem_rsp_data_out_r; - if (mem_rsp_in_fire) begin - mem_rsp_data_out_n[rsp_ctr] = mem_rsp_data_in; - end - end - - always @(posedge clk) begin - if (reset) begin - req_ctr <= 0; - rsp_ctr <= 0; - end else begin - if (mem_req_out_fire) begin - req_ctr <= req_ctr + 1; - end - if (mem_rsp_in_fire) begin - rsp_ctr <= rsp_ctr + 1; - end - end - mem_rsp_data_out_r <= mem_rsp_data_out_n; - end - - reg [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_r; - wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_w; - - always @(posedge clk) begin - if (mem_rsp_in_fire) begin - mem_rsp_tag_in_r <= mem_rsp_tag_in; - end - end - assign mem_rsp_tag_in_w = (rsp_ctr != 0) ? mem_rsp_tag_in_r : mem_rsp_tag_in; - `RUNTIME_ASSERT(!mem_rsp_in_fire || (mem_rsp_tag_in_w == mem_rsp_tag_in), - ("%t: *** out-of-order memory reponse! cur=%d, expected=%d", $time, mem_rsp_tag_in_w, mem_rsp_tag_in)) - - wire [SRC_ADDR_WIDTH+D-1:0] mem_req_addr_in_qual = {mem_req_addr_in, req_ctr}; - - if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH + D)) begin - `UNUSED_VAR (mem_req_addr_in_qual) - assign mem_req_addr_out = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0]; - end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH + D)) begin - assign mem_req_addr_out = DST_ADDR_WIDTH'(mem_req_addr_in_qual); - end else begin - assign mem_req_addr_out = mem_req_addr_in_qual; - end - - assign mem_req_valid_out = mem_req_valid_in; - assign mem_req_rw_out = mem_req_rw_in; - assign mem_req_byteen_out = mem_req_byteen_in_w[req_ctr]; - assign mem_req_data_out = mem_req_data_in_w[req_ctr]; - assign mem_req_tag_out = DST_TAG_WIDTH'(mem_req_tag_in); - assign mem_req_ready_in = mem_req_ready_out && (req_ctr == (P-1)); - - assign mem_rsp_valid_out = mem_rsp_valid_in && (rsp_ctr == (P-1)); - assign mem_rsp_data_out = mem_rsp_data_out_n; - assign mem_rsp_tag_out = SRC_TAG_WIDTH'(mem_rsp_tag_in); - assign mem_rsp_ready_in = mem_rsp_ready_out; - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - if (DST_ADDR_WIDTH < SRC_ADDR_WIDTH) begin - `UNUSED_VAR (mem_req_addr_in) - assign mem_req_addr_out = mem_req_addr_in[DST_ADDR_WIDTH-1:0]; - end else if (DST_ADDR_WIDTH > SRC_ADDR_WIDTH) begin - assign mem_req_addr_out = DST_ADDR_WIDTH'(mem_req_addr_in); - end else begin - assign mem_req_addr_out = mem_req_addr_in; - end - - assign mem_req_valid_out = mem_req_valid_in; - assign mem_req_rw_out = mem_req_rw_in; - assign mem_req_byteen_out = mem_req_byteen_in; - assign mem_req_data_out = mem_req_data_in; - assign mem_req_tag_out = DST_TAG_WIDTH'(mem_req_tag_in); - assign mem_req_ready_in = mem_req_ready_out; - - assign mem_rsp_valid_out = mem_rsp_valid_in; - assign mem_rsp_data_out = mem_rsp_data_in; - assign mem_rsp_tag_out = SRC_TAG_WIDTH'(mem_rsp_tag_in); - assign mem_rsp_ready_in = mem_rsp_ready_out; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/afu/ccip/ccip_if_pkg.sv b/hw/rtl/afu/opae/ccip/ccip_if_pkg.sv similarity index 99% rename from hw/rtl/afu/ccip/ccip_if_pkg.sv rename to hw/rtl/afu/opae/ccip/ccip_if_pkg.sv index 930eaecb..ba399b7d 100644 --- a/hw/rtl/afu/ccip/ccip_if_pkg.sv +++ b/hw/rtl/afu/opae/ccip/ccip_if_pkg.sv @@ -241,4 +241,4 @@ typedef union packed { t_ccip_c0_ReqMmioHdr reqMmioHdr; } t_if_ccip_c0_RxHdr; -endpackage \ No newline at end of file +endpackage diff --git a/hw/rtl/afu/ccip_interface_reg.sv b/hw/rtl/afu/opae/ccip_interface_reg.sv similarity index 99% rename from hw/rtl/afu/ccip_interface_reg.sv rename to hw/rtl/afu/opae/ccip_interface_reg.sv index c61e843e..47e29e63 100644 --- a/hw/rtl/afu/ccip_interface_reg.sv +++ b/hw/rtl/afu/opae/ccip_interface_reg.sv @@ -45,4 +45,4 @@ begin pck_af2cp_sTx_T1 = pck_af2cp_sTx_T0_q; end -endmodule \ No newline at end of file +endmodule diff --git a/hw/rtl/afu/ccip_std_afu.sv b/hw/rtl/afu/opae/ccip_std_afu.sv similarity index 100% rename from hw/rtl/afu/ccip_std_afu.sv rename to hw/rtl/afu/opae/ccip_std_afu.sv diff --git a/hw/rtl/afu/ccip/local_mem_cfg_pkg.sv b/hw/rtl/afu/opae/local_mem_cfg_pkg.sv similarity index 98% rename from hw/rtl/afu/ccip/local_mem_cfg_pkg.sv rename to hw/rtl/afu/opae/local_mem_cfg_pkg.sv index 97205e3c..ef9fae28 100644 --- a/hw/rtl/afu/ccip/local_mem_cfg_pkg.sv +++ b/hw/rtl/afu/opae/local_mem_cfg_pkg.sv @@ -58,4 +58,4 @@ package local_mem_cfg_pkg; endpackage // local_mem_cfg_pkg -`endif // PLATFORM_PROVIDES_LOCAL_MEMORY \ No newline at end of file +`endif // PLATFORM_PROVIDES_LOCAL_MEMORY diff --git a/hw/rtl/afu/opae/vortex_afu.sv b/hw/rtl/afu/opae/vortex_afu.sv new file mode 100644 index 00000000..e039dca2 --- /dev/null +++ b/hw/rtl/afu/opae/vortex_afu.sv @@ -0,0 +1,1093 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef NOPAE +`include "afu_json_info.vh" +`else +`include "vortex_afu.vh" +`endif +`include "VX_define.vh" + +module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_gpu_pkg::*; #( + parameter NUM_LOCAL_MEM_BANKS = 2 +) ( + // global signals + input wire clk, + input wire reset, + + // IF signals between CCI and AFU + input t_if_ccip_Rx cp2af_sRxPort, + output t_if_ccip_Tx af2cp_sTxPort, + + // Avalon signals for local memory access + output t_local_mem_data avs_writedata [NUM_LOCAL_MEM_BANKS], + input t_local_mem_data avs_readdata [NUM_LOCAL_MEM_BANKS], + output t_local_mem_addr avs_address [NUM_LOCAL_MEM_BANKS], + input wire avs_waitrequest [NUM_LOCAL_MEM_BANKS], + output wire avs_write [NUM_LOCAL_MEM_BANKS], + output wire avs_read [NUM_LOCAL_MEM_BANKS], + output t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS], + output t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS], + input wire avs_readdatavalid [NUM_LOCAL_MEM_BANKS] +); + + localparam LMEM_DATA_WIDTH = $bits(t_local_mem_data); + localparam LMEM_DATA_SIZE = LMEM_DATA_WIDTH / 8; + localparam LMEM_ADDR_WIDTH = $bits(t_local_mem_addr); + localparam LMEM_BURST_CTRW = $bits(t_local_mem_burst_cnt); + + localparam CCI_DATA_WIDTH = $bits(t_ccip_clData); + localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8; + localparam CCI_ADDR_WIDTH = $bits(t_ccip_clAddr); + + localparam AVS_RD_QUEUE_SIZE = 32; + localparam _VX_MEM_TAG_WIDTH = `VX_MEM_TAG_WIDTH; + localparam _AVS_REQ_TAGW_VX = _VX_MEM_TAG_WIDTH + `CLOG2(LMEM_DATA_WIDTH) - `CLOG2(`VX_MEM_DATA_WIDTH); + localparam _AVS_REQ_TAGW_VX2 = `MAX(_VX_MEM_TAG_WIDTH, _AVS_REQ_TAGW_VX); + localparam _AVS_REQ_TAGW_CCI = CCI_ADDR_WIDTH + `CLOG2(LMEM_DATA_WIDTH) - `CLOG2(CCI_DATA_WIDTH); + localparam _AVS_REQ_TAGW_CCI2 = `MAX(CCI_ADDR_WIDTH, _AVS_REQ_TAGW_CCI); + localparam AVS_REQ_TAGW = `MAX(_AVS_REQ_TAGW_VX2, _AVS_REQ_TAGW_CCI2); + + localparam CCI_RD_WINDOW_SIZE = 8; + localparam CCI_RW_PENDING_SIZE= 256; + + localparam AFU_ID_L = 16'h0002; // AFU ID Lower + localparam AFU_ID_H = 16'h0004; // AFU ID Higher + + localparam CMD_MEM_READ = `AFU_IMAGE_CMD_MEM_READ; + localparam CMD_MEM_WRITE = `AFU_IMAGE_CMD_MEM_WRITE; + localparam CMD_DCR_WRITE = `AFU_IMAGE_CMD_DCR_WRITE; + localparam CMD_RUN = `AFU_IMAGE_CMD_RUN; + localparam CMD_TYPE_WIDTH = `CLOG2(`AFU_IMAGE_CMD_MAX_VALUE+1); + + localparam MMIO_CMD_TYPE = `AFU_IMAGE_MMIO_CMD_TYPE; + localparam MMIO_CMD_ARG0 = `AFU_IMAGE_MMIO_CMD_ARG0; + localparam MMIO_CMD_ARG1 = `AFU_IMAGE_MMIO_CMD_ARG1; + localparam MMIO_CMD_ARG2 = `AFU_IMAGE_MMIO_CMD_ARG2; + localparam MMIO_STATUS = `AFU_IMAGE_MMIO_STATUS; + + localparam COUT_TID_WIDTH = `CLOG2(`VX_MEM_BYTEEN_WIDTH); + localparam COUT_QUEUE_DATAW = COUT_TID_WIDTH + 8; + localparam COUT_QUEUE_SIZE = 64; + + localparam MMIO_DEV_CAPS = `AFU_IMAGE_MMIO_DEV_CAPS; + localparam MMIO_ISA_CAPS = `AFU_IMAGE_MMIO_ISA_CAPS; + + localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE; + localparam CCI_RD_QUEUE_TAGW = `CLOG2(CCI_RD_WINDOW_SIZE); + localparam CCI_RD_QUEUE_DATAW = CCI_DATA_WIDTH + CCI_ADDR_WIDTH; + + localparam STATE_IDLE = 0; + localparam STATE_MEM_WRITE = 1; + localparam STATE_MEM_READ = 2; + localparam STATE_RUN = 3; + localparam STATE_DCR_WRITE = 4; + localparam STATE_WIDTH = `CLOG2(STATE_DCR_WRITE+1); + + wire [127:0] afu_id = `AFU_ACCEL_UUID; + + wire [63:0] dev_caps = {16'b0, + 8'(`SM_ENABLED ? `SMEM_LOG_SIZE : 0), + 16'(`NUM_CORES * `NUM_CLUSTERS), + 8'(`NUM_WARPS), + 8'(`NUM_THREADS), + 8'(`IMPLEMENTATION_ID)}; + + wire [63:0] isa_caps = {32'(`MISA_EXT), + 2'(`CLOG2(`XLEN)-4), + 30'(`MISA_STD)}; + + reg [STATE_WIDTH-1:0] state; + + // Vortex ports /////////////////////////////////////////////////////////////// + + wire vx_mem_req_valid; + wire vx_mem_req_rw; + wire [`VX_MEM_BYTEEN_WIDTH-1:0] vx_mem_req_byteen; + wire [`VX_MEM_ADDR_WIDTH-1:0] vx_mem_req_addr; + wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_req_data; + wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_req_tag; + wire vx_mem_req_ready; + + wire vx_mem_rsp_valid; + wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_rsp_data; + wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag; + wire vx_mem_rsp_ready; + + // CMD variables ////////////////////////////////////////////////////////////// + + reg [2:0][63:0] cmd_args; + + t_ccip_clAddr cmd_io_addr; + assign cmd_io_addr = t_ccip_clAddr'(cmd_args[0]); + + wire [CCI_ADDR_WIDTH-1:0] cmd_mem_addr = CCI_ADDR_WIDTH'(cmd_args[1]); + wire [CCI_ADDR_WIDTH-1:0] cmd_data_size = CCI_ADDR_WIDTH'(cmd_args[2]); + + wire [`VX_DCR_ADDR_WIDTH-1:0] cmd_dcr_addr = `VX_DCR_ADDR_WIDTH'(cmd_args[0]); + wire [`VX_DCR_DATA_WIDTH-1:0] cmd_dcr_data = `VX_DCR_DATA_WIDTH'(cmd_args[1]); + + // MMIO controller //////////////////////////////////////////////////////////// + + t_ccip_c0_ReqMmioHdr mmio_hdr; + assign mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr); + `UNUSED_VAR (mmio_hdr) + + `STATIC_ASSERT(($bits(t_ccip_c0_ReqMmioHdr)-$bits(mmio_hdr.address)) == 12, ("Oops!")) + + t_if_ccip_c2_Tx mmio_tx; + assign af2cp_sTxPort.c2 = mmio_tx; + +`ifdef SCOPE + + localparam MMIO_SCOPE_READ = `AFU_IMAGE_MMIO_SCOPE_READ; + localparam MMIO_SCOPE_WRITE = `AFU_IMAGE_MMIO_SCOPE_WRITE; + + reg [63:0] cmd_scope_rdata; + reg [63:0] cmd_scope_wdata; + + reg cmd_scope_reading; + reg cmd_scope_writing; + + reg scope_bus_in; + wire scope_bus_out; + + reg [5:0] scope_bus_ctr; + + wire scope_reset = reset; + + always @(posedge clk) begin + if (reset) begin + cmd_scope_reading <= 0; + cmd_scope_writing <= 0; + scope_bus_in <= 0; + end else begin + if (scope_bus_out) begin + cmd_scope_reading <= 1; + scope_bus_ctr <= 63; + end + scope_bus_in <= 0; + if (cp2af_sRxPort.c0.mmioWrValid + && (MMIO_SCOPE_WRITE == mmio_hdr.address)) begin + cmd_scope_wdata <= 64'(cp2af_sRxPort.c0.data); + cmd_scope_writing <= 1; + scope_bus_ctr <= 63; + scope_bus_in <= 1; + end + end + if (cmd_scope_writing) begin + scope_bus_in <= 1'(cmd_scope_wdata >> scope_bus_ctr); + scope_bus_ctr <= scope_bus_ctr - 1; + if (scope_bus_ctr == 0) begin + cmd_scope_writing <= 0; + end + end + if (cmd_scope_reading) begin + cmd_scope_rdata <= {cmd_scope_rdata[62:0], scope_bus_out}; + scope_bus_ctr <= scope_bus_ctr - 1; + if (scope_bus_ctr == 0) begin + cmd_scope_reading <= 0; + end + end + end + +`endif + + wire [COUT_QUEUE_DATAW-1:0] cout_q_dout; + wire cout_q_full, cout_q_empty; + +`ifdef SIMULATION +`ifndef VERILATOR + // disable assertions until full reset + reg [`CLOG2(`RESET_DELAY+1)-1:0] assert_delay_ctr; + initial begin + $assertoff; + end + always @(posedge clk) begin + if (reset) begin + assert_delay_ctr <= '0; + end else begin + assert_delay_ctr <= assert_delay_ctr + $bits(assert_delay_ctr)'(1); + if (assert_delay_ctr == (`RESET_DELAY-1)) begin + $asserton; // enable assertions + end + end + end +`endif +`endif + + always @(posedge clk) begin + if (reset) begin + mmio_tx.mmioRdValid <= 0; + mmio_tx.hdr <= '0; + end else begin + mmio_tx.mmioRdValid <= cp2af_sRxPort.c0.mmioRdValid; + mmio_tx.hdr.tid <= mmio_hdr.tid; + end + // serve MMIO write request + if (cp2af_sRxPort.c0.mmioWrValid) begin + case (mmio_hdr.address) + MMIO_CMD_ARG0: begin + cmd_args[0] <= 64'(cp2af_sRxPort.c0.data); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: MMIO_CMD_ARG0: data=0x%0h\n", $time, 64'(cp2af_sRxPort.c0.data))); + `endif + end + MMIO_CMD_ARG1: begin + cmd_args[1] <= 64'(cp2af_sRxPort.c0.data); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: MMIO_CMD_ARG1: data=0x%0h\n", $time, 64'(cp2af_sRxPort.c0.data))); + `endif + end + MMIO_CMD_ARG2: begin + cmd_args[2] <= 64'(cp2af_sRxPort.c0.data); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: MMIO_CMD_ARG2: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data))); + `endif + end + MMIO_CMD_TYPE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: MMIO_CMD_TYPE: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data))); + `endif + end + `ifdef SCOPE + MMIO_SCOPE_WRITE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: MMIO_SCOPE_WRITE: data=0x%0h\n", $time, cmd_scope_wdata)); + `endif + end + `endif + default: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: Unknown MMIO Wr: addr=0x%0h, data=0x%0h\n", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data))); + `endif + end + endcase + end + + // serve MMIO read requests + if (cp2af_sRxPort.c0.mmioRdValid) begin + case (mmio_hdr.address) + // AFU header + 16'h0000: mmio_tx.data <= { + 4'b0001, // Feature type = AFU + 8'b0, // reserved + 4'b0, // afu minor revision = 0 + 7'b0, // reserved + 1'b1, // end of DFH list = 1 + 24'b0, // next DFH offset = 0 + 4'b0, // afu major revision = 0 + 12'b0 // feature ID = 0 + }; + AFU_ID_L: mmio_tx.data <= afu_id[63:0]; // afu id low + AFU_ID_H: mmio_tx.data <= afu_id[127:64]; // afu id hi + 16'h0006: mmio_tx.data <= 64'h0; // next AFU + 16'h0008: mmio_tx.data <= 64'h0; // reserved + MMIO_STATUS: begin + mmio_tx.data <= 64'({cout_q_dout, !cout_q_empty, 8'(state)}); + `ifdef DBG_TRACE_AFU + if (state != STATE_WIDTH'(mmio_tx.data)) begin + `TRACE(2, ("%d: MMIO_STATUS: addr=0x%0h, state=%0d\n", $time, mmio_hdr.address, state)); + end + `endif + end + `ifdef SCOPE + MMIO_SCOPE_READ: begin + mmio_tx.data <= cmd_scope_rdata; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: MMIO_SCOPE_READ: data=0x%0h\n", $time, cmd_scope_rdata)); + `endif + end + `endif + MMIO_DEV_CAPS: begin + mmio_tx.data <= dev_caps; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: MMIO_DEV_CAPS: data=0x%0h\n", $time, dev_caps)); + `endif + end + MMIO_ISA_CAPS: begin + mmio_tx.data <= isa_caps; + `ifdef DBG_TRACE_AFU + if (state != STATE_WIDTH'(mmio_tx.data)) begin + `TRACE(2, ("%d: MMIO_ISA_CAPS: data=%0d\n", $time, isa_caps)); + end + `endif + end + default: begin + mmio_tx.data <= 64'h0; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: Unknown MMIO Rd: addr=0x%0h\n", $time, mmio_hdr.address)); + `endif + end + endcase + end + end + + // COMMAND FSM //////////////////////////////////////////////////////////////// + + wire cmd_mem_rd_done; + reg cmd_mem_wr_done; + + reg vx_busy_wait; + reg vx_running; + wire vx_busy; + + reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr; + always @(posedge clk) begin + if (state == STATE_RUN) begin + vx_reset_ctr <= vx_reset_ctr + $bits(vx_reset_ctr)'(1); + end else begin + vx_reset_ctr <= '0; + end + end + + wire is_mmio_wr_cmd = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_hdr.address); + wire [CMD_TYPE_WIDTH-1:0] cmd_type = is_mmio_wr_cmd ? + CMD_TYPE_WIDTH'(cp2af_sRxPort.c0.data) : CMD_TYPE_WIDTH'(0); + + always @(posedge clk) begin + if (reset) begin + state <= STATE_IDLE; + vx_busy_wait <= 0; + vx_running <= 0; + end else begin + case (state) + STATE_IDLE: begin + case (cmd_type) + CMD_MEM_READ: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE MEM_READ: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size)); + `endif + state <= STATE_MEM_READ; + end + CMD_MEM_WRITE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE MEM_WRITE: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size)); + `endif + state <= STATE_MEM_WRITE; + end + CMD_DCR_WRITE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE DCR_WRITE: addr=0x%0h data=%0d\n", $time, cmd_dcr_addr, cmd_dcr_data)); + `endif + state <= STATE_DCR_WRITE; + end + CMD_RUN: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE RUN\n", $time)); + `endif + state <= STATE_RUN; + vx_running <= 0; + end + default: begin + state <= state; + end + endcase + end + STATE_MEM_READ: begin + if (cmd_mem_rd_done) begin + state <= STATE_IDLE; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE IDLE\n", $time)); + `endif + end + end + STATE_MEM_WRITE: begin + if (cmd_mem_wr_done) begin + state <= STATE_IDLE; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE IDLE\n", $time)); + `endif + end + end + STATE_DCR_WRITE: begin + state <= STATE_IDLE; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE IDLE\n", $time)); + `endif + end + STATE_RUN: begin + if (vx_running) begin + if (vx_busy_wait) begin + // wait until the gpu goes busy + if (vx_busy) begin + vx_busy_wait <= 0; + end + end else begin + // wait until the gpu is not busy + if (~vx_busy) begin + state <= STATE_IDLE; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: AFU: End execution\n", $time)); + `TRACE(2, ("%d: STATE IDLE\n", $time)); + `endif + end + end + end else begin + // wait until the reset sequence is complete + if (vx_reset_ctr == (`RESET_DELAY-1)) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: AFU: Begin execution\n", $time)); + `endif + vx_running <= 1; + vx_busy_wait <= 1; + end + end + end + default:; + endcase + end + end + + // AVS Controller ///////////////////////////////////////////////////////////// + + wire cci_mem_rd_req_valid; + wire cci_mem_wr_req_valid; + wire [CCI_RD_QUEUE_DATAW-1:0] cci_rdq_dout; + + wire cci_mem_req_valid; + wire cci_mem_req_rw; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_addr; + wire [CCI_DATA_WIDTH-1:0] cci_mem_req_data; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_tag; + wire cci_mem_req_ready; + + wire cci_mem_rsp_valid; + wire [CCI_DATA_WIDTH-1:0] cci_mem_rsp_data; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_rsp_tag; + wire cci_mem_rsp_ready; + + //-- + + VX_mem_bus_if #( + .DATA_SIZE (LMEM_DATA_SIZE), + .ADDR_WIDTH (LMEM_ADDR_WIDTH), + .TAG_WIDTH (AVS_REQ_TAGW) + ) cci_vx_mem_bus_if[2](); + + VX_mem_adapter #( + .SRC_DATA_WIDTH (CCI_DATA_WIDTH), + .DST_DATA_WIDTH (LMEM_DATA_WIDTH), + .SRC_ADDR_WIDTH (CCI_ADDR_WIDTH), + .DST_ADDR_WIDTH (LMEM_ADDR_WIDTH), + .SRC_TAG_WIDTH (CCI_ADDR_WIDTH), + .DST_TAG_WIDTH (AVS_REQ_TAGW), + .OUT_REG_REQ (0), + .OUT_REG_RSP (0) + ) cci_mem_adapter ( + .clk (clk), + .reset (reset), + + .mem_req_valid_in (cci_mem_req_valid), + .mem_req_addr_in (cci_mem_req_addr), + .mem_req_rw_in (cci_mem_req_rw), + .mem_req_byteen_in ({CCI_DATA_SIZE{1'b1}}), + .mem_req_data_in (cci_mem_req_data), + .mem_req_tag_in (cci_mem_req_tag), + .mem_req_ready_in (cci_mem_req_ready), + + .mem_rsp_valid_in (cci_mem_rsp_valid), + .mem_rsp_data_in (cci_mem_rsp_data), + .mem_rsp_tag_in (cci_mem_rsp_tag), + .mem_rsp_ready_in (cci_mem_rsp_ready), + + .mem_req_valid_out (cci_vx_mem_bus_if[1].req_valid), + .mem_req_addr_out (cci_vx_mem_bus_if[1].req_data.addr), + .mem_req_rw_out (cci_vx_mem_bus_if[1].req_data.rw), + .mem_req_byteen_out (cci_vx_mem_bus_if[1].req_data.byteen), + .mem_req_data_out (cci_vx_mem_bus_if[1].req_data.data), + .mem_req_tag_out (cci_vx_mem_bus_if[1].req_data.tag), + .mem_req_ready_out (cci_vx_mem_bus_if[1].req_ready), + + .mem_rsp_valid_out (cci_vx_mem_bus_if[1].rsp_valid), + .mem_rsp_data_out (cci_vx_mem_bus_if[1].rsp_data.data), + .mem_rsp_tag_out (cci_vx_mem_bus_if[1].rsp_data.tag), + .mem_rsp_ready_out (cci_vx_mem_bus_if[1].rsp_ready) + ); + + //-- + + wire vx_mem_is_cout; + wire vx_mem_req_valid_qual; + wire vx_mem_req_ready_qual; + + assign vx_mem_req_valid_qual = vx_mem_req_valid && ~vx_mem_is_cout; + + VX_mem_adapter #( + .SRC_DATA_WIDTH (`VX_MEM_DATA_WIDTH), + .DST_DATA_WIDTH (LMEM_DATA_WIDTH), + .SRC_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH), + .DST_ADDR_WIDTH (LMEM_ADDR_WIDTH), + .SRC_TAG_WIDTH (`VX_MEM_TAG_WIDTH), + .DST_TAG_WIDTH (AVS_REQ_TAGW), + .OUT_REG_REQ (0), + .OUT_REG_RSP (2) + ) vx_mem_adapter ( + .clk (clk), + .reset (reset), + + .mem_req_valid_in (vx_mem_req_valid_qual), + .mem_req_addr_in (vx_mem_req_addr), + .mem_req_rw_in (vx_mem_req_rw), + .mem_req_byteen_in (vx_mem_req_byteen), + .mem_req_data_in (vx_mem_req_data), + .mem_req_tag_in (vx_mem_req_tag), + .mem_req_ready_in (vx_mem_req_ready_qual), + + .mem_rsp_valid_in (vx_mem_rsp_valid), + .mem_rsp_data_in (vx_mem_rsp_data), + .mem_rsp_tag_in (vx_mem_rsp_tag), + .mem_rsp_ready_in (vx_mem_rsp_ready), + + .mem_req_valid_out (cci_vx_mem_bus_if[0].req_valid), + .mem_req_addr_out (cci_vx_mem_bus_if[0].req_data.addr), + .mem_req_rw_out (cci_vx_mem_bus_if[0].req_data.rw), + .mem_req_byteen_out (cci_vx_mem_bus_if[0].req_data.byteen), + .mem_req_data_out (cci_vx_mem_bus_if[0].req_data.data), + .mem_req_tag_out (cci_vx_mem_bus_if[0].req_data.tag), + .mem_req_ready_out (cci_vx_mem_bus_if[0].req_ready), + + .mem_rsp_valid_out (cci_vx_mem_bus_if[0].rsp_valid), + .mem_rsp_data_out (cci_vx_mem_bus_if[0].rsp_data.data), + .mem_rsp_tag_out (cci_vx_mem_bus_if[0].rsp_data.tag), + .mem_rsp_ready_out (cci_vx_mem_bus_if[0].rsp_ready) + ); + + //-- + VX_mem_bus_if #( + .DATA_SIZE (LMEM_DATA_SIZE), + .ADDR_WIDTH (LMEM_ADDR_WIDTH), + .TAG_WIDTH (AVS_REQ_TAGW+1) + ) mem_bus_if[1](); + + `RESET_RELAY (mem_arb_reset, reset); + + VX_mem_arb #( + .NUM_INPUTS (2), + .DATA_SIZE (LMEM_DATA_SIZE), + .ADDR_WIDTH (LMEM_ADDR_WIDTH), + .TAG_WIDTH (AVS_REQ_TAGW), + .ARBITER ("P"), + .OUT_REG_REQ (0), + .OUT_REG_RSP (0) + ) mem_arb ( + .clk (clk), + .reset (mem_arb_reset), + .bus_in_if (cci_vx_mem_bus_if), + .bus_out_if (mem_bus_if) + ); + + //-- + + `RESET_RELAY (avs_adapter_reset, reset); + + VX_avs_adapter #( + .DATA_WIDTH (LMEM_DATA_WIDTH), + .ADDR_WIDTH (LMEM_ADDR_WIDTH), + .BURST_WIDTH (LMEM_BURST_CTRW), + .NUM_BANKS (NUM_LOCAL_MEM_BANKS), + .TAG_WIDTH (AVS_REQ_TAGW + 1), + .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE), + .OUT_REG_REQ (2), + .OUT_REG_RSP (0) + ) avs_adapter ( + .clk (clk), + .reset (avs_adapter_reset), + + // Memory request + .mem_req_valid (mem_bus_if[0].req_valid), + .mem_req_rw (mem_bus_if[0].req_data.rw), + .mem_req_byteen (mem_bus_if[0].req_data.byteen), + .mem_req_addr (mem_bus_if[0].req_data.addr), + .mem_req_data (mem_bus_if[0].req_data.data), + .mem_req_tag (mem_bus_if[0].req_data.tag), + .mem_req_ready (mem_bus_if[0].req_ready), + + // Memory response + .mem_rsp_valid (mem_bus_if[0].rsp_valid), + .mem_rsp_data (mem_bus_if[0].rsp_data.data), + .mem_rsp_tag (mem_bus_if[0].rsp_data.tag), + .mem_rsp_ready (mem_bus_if[0].rsp_ready), + + // AVS bus + .avs_writedata (avs_writedata), + .avs_readdata (avs_readdata), + .avs_address (avs_address), + .avs_waitrequest (avs_waitrequest), + .avs_write (avs_write), + .avs_read (avs_read), + .avs_byteenable (avs_byteenable), + .avs_burstcount (avs_burstcount), + .avs_readdatavalid(avs_readdatavalid) + ); + + // CCI-P Read Request /////////////////////////////////////////////////////////// + + reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_ctr; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr; + reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr_base; + + wire cci_rd_req_fire; + t_ccip_clAddr cci_rd_req_addr; + reg cci_rd_req_valid, cci_rd_req_wait; + reg [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr; + wire [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr_next; + wire [CCI_RD_QUEUE_TAGW-1:0] cci_rd_req_tag; + + wire [CCI_RD_QUEUE_TAGW-1:0] cci_rd_rsp_tag; + reg [CCI_RD_QUEUE_TAGW-1:0] cci_rd_rsp_ctr; + + wire cci_rdq_push, cci_rdq_pop; + wire [CCI_RD_QUEUE_DATAW-1:0] cci_rdq_din; + wire cci_rdq_empty; + + always @(*) begin + af2cp_sTxPort.c0.valid = cci_rd_req_fire; + af2cp_sTxPort.c0.hdr = t_ccip_c0_ReqMemHdr'(0); + af2cp_sTxPort.c0.hdr.address = cci_rd_req_addr; + af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(cci_rd_req_tag); + end + + wire cci_mem_wr_req_fire = cci_mem_wr_req_valid && cci_mem_req_ready; + + wire cci_rd_rsp_fire = cp2af_sRxPort.c0.rspValid + && (cp2af_sRxPort.c0.hdr.resp_type == eRSP_RDLINE); + + assign cci_rd_req_tag = CCI_RD_QUEUE_TAGW'(cci_rd_req_ctr); + assign cci_rd_rsp_tag = CCI_RD_QUEUE_TAGW'(cp2af_sRxPort.c0.hdr.mdata); + + assign cci_rdq_push = cci_rd_rsp_fire; + assign cci_rdq_pop = cci_mem_wr_req_fire; + assign cci_rdq_din = {cp2af_sRxPort.c0.data, cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(cci_rd_rsp_tag)}; + + wire [`CLOG2(CCI_RD_QUEUE_SIZE+1)-1:0] cci_pending_reads; + wire cci_pending_reads_full; + VX_pending_size #( + .SIZE (CCI_RD_QUEUE_SIZE) + ) cci_rd_pending_size ( + .clk (clk), + .reset (reset), + .incr (cci_rd_req_fire), + .decr (cci_rdq_pop), + .full (cci_pending_reads_full), + .size (cci_pending_reads), + `UNUSED_PIN (empty) + ); + + `UNUSED_VAR (cci_pending_reads) + + assign cci_rd_req_ctr_next = cci_rd_req_ctr + CCI_ADDR_WIDTH'(cci_rd_req_fire ? 1 : 0); + + assign cci_rd_req_fire = cci_rd_req_valid && !(cci_rd_req_wait || cci_pending_reads_full); + + assign cci_mem_wr_req_valid = !cci_rdq_empty; + + assign cci_mem_wr_req_addr = cci_rdq_dout[CCI_ADDR_WIDTH-1:0]; + + // Send read requests to CCI + always @(posedge clk) begin + if (reset) begin + cci_rd_req_valid <= 0; + cci_rd_req_wait <= 0; + end else begin + if ((STATE_IDLE == state) + && (CMD_MEM_WRITE == cmd_type)) begin + cci_rd_req_valid <= (cmd_data_size != 0); + cci_rd_req_wait <= 0; + end + + cci_rd_req_valid <= (STATE_MEM_WRITE == state) + && (cci_rd_req_ctr_next != cmd_data_size) + && !cp2af_sRxPort.c0TxAlmFull; + + if (cci_rd_req_fire + && (cci_rd_req_tag == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1))) begin + cci_rd_req_wait <= 1; // end current request batch + end + + if (cci_rd_rsp_fire + && (cci_rd_rsp_ctr == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1))) begin + cci_rd_req_wait <= 0; // begin new request batch + end + end + + if ((STATE_IDLE == state) + && (CMD_MEM_WRITE == cmd_type)) begin + cci_rd_req_addr <= cmd_io_addr; + cci_rd_req_ctr <= '0; + cci_rd_rsp_ctr <= '0; + cci_mem_wr_req_ctr <= '0; + cci_mem_wr_req_addr_base <= cmd_mem_addr; + cmd_mem_wr_done <= 0; + end + + if (cci_rd_req_fire) begin + cci_rd_req_addr <= cci_rd_req_addr + 1; + cci_rd_req_ctr <= cci_rd_req_ctr + $bits(cci_rd_req_ctr)'(1); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: CCI Rd Req: addr=0x%0h, tag=0x%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads)); + `endif + end + + if (cci_rd_rsp_fire) begin + cci_rd_rsp_ctr <= cci_rd_rsp_ctr + CCI_RD_QUEUE_TAGW'(1); + if (CCI_RD_QUEUE_TAGW'(cci_rd_rsp_ctr) == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin + cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE); + end + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: CCI Rd Rsp: idx=%0d, ctr=%0d, data=0x%0h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data)); + `endif + end + + if (cci_rdq_pop) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads)); + `endif + end + + if (cci_mem_wr_req_fire) begin + cci_mem_wr_req_ctr <= cci_mem_wr_req_ctr + CCI_ADDR_WIDTH'(1); + if (cci_mem_wr_req_ctr == (cmd_data_size-1)) begin + cmd_mem_wr_done <= 1; + end + end + end + + `RESET_RELAY (cci_rdq_reset, reset); + + VX_fifo_queue #( + .DATAW (CCI_RD_QUEUE_DATAW), + .DEPTH (CCI_RD_QUEUE_SIZE) + ) cci_rd_req_queue ( + .clk (clk), + .reset (cci_rdq_reset), + .push (cci_rdq_push), + .pop (cci_rdq_pop), + .data_in (cci_rdq_din), + .data_out (cci_rdq_dout), + .empty (cci_rdq_empty), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + +`DEBUG_BLOCK( + reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask; + always @(posedge clk) begin + if (reset) begin + dbg_cci_rd_rsp_mask <= '0; + end else begin + if (cci_rd_rsp_fire) begin + if (cci_rd_rsp_ctr == 0) begin + dbg_cci_rd_rsp_mask <= (CCI_RD_WINDOW_SIZE'(1) << cci_rd_rsp_tag); + end else begin + assert(!dbg_cci_rd_rsp_mask[cci_rd_rsp_tag]); + dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] <= 1; + end + end + end + end +) + + // CCI-P Write Request ////////////////////////////////////////////////////////// + + reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_ctr; + reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr; + reg cci_mem_rd_req_done; + + reg [CCI_ADDR_WIDTH-1:0] cci_wr_req_ctr; + reg cci_wr_req_fire; + t_ccip_clAddr cci_wr_req_addr; + t_ccip_clData cci_wr_req_data; + reg cci_wr_req_done; + + always @(*) begin + af2cp_sTxPort.c1.valid = cci_wr_req_fire; + af2cp_sTxPort.c1.hdr = t_ccip_c1_ReqMemHdr'(0); + af2cp_sTxPort.c1.hdr.sop = 1; // single line write mode + af2cp_sTxPort.c1.hdr.address = cci_wr_req_addr; + af2cp_sTxPort.c1.data = cci_wr_req_data; + end + + wire cci_mem_rd_req_fire = cci_mem_rd_req_valid && cci_mem_req_ready; + wire cci_mem_rd_rsp_fire = cci_mem_rsp_valid && cci_mem_rsp_ready; + + wire cci_wr_rsp_fire = (STATE_MEM_READ == state) + && cp2af_sRxPort.c1.rspValid + && (cp2af_sRxPort.c1.hdr.resp_type == eRSP_WRLINE); + + wire [`CLOG2(CCI_RW_PENDING_SIZE+1)-1:0] cci_pending_writes; + wire cci_pending_writes_empty; + wire cci_pending_writes_full; + + VX_pending_size #( + .SIZE (CCI_RW_PENDING_SIZE) + ) cci_wr_pending_size ( + .clk (clk), + .reset (reset), + .incr (cci_mem_rd_rsp_fire), + .decr (cci_wr_rsp_fire), + .empty (cci_pending_writes_empty), + .full (cci_pending_writes_full), + .size (cci_pending_writes) + ); + + `UNUSED_VAR (cci_pending_writes) + + assign cci_mem_rd_req_valid = (STATE_MEM_READ == state) + && ~cci_mem_rd_req_done; + + assign cci_mem_rsp_ready = ~cp2af_sRxPort.c1TxAlmFull + && ~cci_pending_writes_full; + + assign cmd_mem_rd_done = cci_wr_req_done + && cci_pending_writes_empty; + + // Send write requests to CCI + always @(posedge clk) begin + if (reset) begin + cci_wr_req_fire <= 0; + end else begin + cci_wr_req_fire <= cci_mem_rd_rsp_fire; + end + + if ((STATE_IDLE == state) + && (CMD_MEM_READ == cmd_type)) begin + cci_mem_rd_req_ctr <= '0; + cci_mem_rd_req_addr <= cmd_mem_addr; + cci_mem_rd_req_done <= 0; + cci_wr_req_ctr <= cmd_data_size; + cci_wr_req_done <= 0; + end + + if (cci_mem_rd_req_fire) begin + cci_mem_rd_req_addr <= cci_mem_rd_req_addr + CCI_ADDR_WIDTH'(1); + cci_mem_rd_req_ctr <= cci_mem_rd_req_ctr + CCI_ADDR_WIDTH'(1); + if (cci_mem_rd_req_ctr == (cmd_data_size-1)) begin + cci_mem_rd_req_done <= 1; + end + end + + cci_wr_req_addr <= cmd_io_addr + t_ccip_clAddr'(cci_mem_rsp_tag); + cci_wr_req_data <= t_ccip_clData'(cci_mem_rsp_data); + + if (cci_wr_req_fire) begin + `ASSERT(cci_wr_req_ctr != 0, ("runtime error")); + cci_wr_req_ctr <= cci_wr_req_ctr - CCI_ADDR_WIDTH'(1); + if (cci_wr_req_ctr == CCI_ADDR_WIDTH'(1)) begin + cci_wr_req_done <= 1; + end + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: CCI Wr Req: addr=0x%0h, rem=%0d, pending=%0d, data=0x%0h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data)); + `endif + end + + if (cci_wr_rsp_fire) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes)); + `endif + end + end + + //-- + + assign cci_mem_req_rw = state[0]; + `STATIC_ASSERT(STATE_MEM_WRITE == 1, ("invalid value")); // 01 + `STATIC_ASSERT(STATE_MEM_READ == 2, ("invalid value")); // 10 + + assign cci_mem_req_valid = cci_mem_req_rw ? cci_mem_wr_req_valid : cci_mem_rd_req_valid; + assign cci_mem_req_addr = cci_mem_req_rw ? cci_mem_wr_req_addr : cci_mem_rd_req_addr; + assign cci_mem_req_data = cci_rdq_dout[CCI_RD_QUEUE_DATAW-1:CCI_ADDR_WIDTH]; + assign cci_mem_req_tag = cci_mem_req_rw ? cci_mem_wr_req_ctr : cci_mem_rd_req_ctr; + + // Vortex /////////////////////////////////////////////////////////////////// + + wire vx_dcr_wr_valid = (STATE_DCR_WRITE == state); + wire [`VX_DCR_ADDR_WIDTH-1:0] vx_dcr_wr_addr = cmd_dcr_addr; + wire [`VX_DCR_DATA_WIDTH-1:0] vx_dcr_wr_data = cmd_dcr_data; + + `SCOPE_IO_SWITCH (2) + + Vortex vortex ( + `SCOPE_IO_BIND (1) + + .clk (clk), + .reset (reset || ~vx_running), + + // Memory request + .mem_req_valid (vx_mem_req_valid), + .mem_req_rw (vx_mem_req_rw), + .mem_req_byteen (vx_mem_req_byteen), + .mem_req_addr (vx_mem_req_addr), + .mem_req_data (vx_mem_req_data), + .mem_req_tag (vx_mem_req_tag), + .mem_req_ready (vx_mem_req_ready), + + // Memory response + .mem_rsp_valid (vx_mem_rsp_valid), + .mem_rsp_data (vx_mem_rsp_data), + .mem_rsp_tag (vx_mem_rsp_tag), + .mem_rsp_ready (vx_mem_rsp_ready), + + // DCR write request + .dcr_wr_valid (vx_dcr_wr_valid), + .dcr_wr_addr (vx_dcr_wr_addr), + .dcr_wr_data (vx_dcr_wr_data), + + // Status + .busy (vx_busy) + ); + + // COUT HANDLING ////////////////////////////////////////////////////////////// + + wire [COUT_TID_WIDTH-1:0] cout_tid; + + VX_onehot_encoder #( + .N (`VX_MEM_BYTEEN_WIDTH) + ) cout_tid_enc ( + .data_in (vx_mem_req_byteen), + .data_out (cout_tid), + `UNUSED_PIN (valid_out) + ); + + wire [`VX_MEM_ADDR_WIDTH-1:0] io_cout_addr_b = `VX_MEM_ADDR_WIDTH'(`IO_COUT_ADDR >> `CLOG2(`MEM_BLOCK_SIZE)); + + assign vx_mem_is_cout = (vx_mem_req_addr == io_cout_addr_b); + + assign vx_mem_req_ready = vx_mem_is_cout ? ~cout_q_full : vx_mem_req_ready_qual; + + wire [`VX_MEM_BYTEEN_WIDTH-1:0][7:0] vx_mem_req_data_m = vx_mem_req_data; + + wire [7:0] cout_char = vx_mem_req_data_m[cout_tid]; + + wire cout_q_push = vx_mem_req_valid && vx_mem_is_cout && ~cout_q_full; + + wire cout_q_pop = cp2af_sRxPort.c0.mmioRdValid + && (mmio_hdr.address == MMIO_STATUS) + && ~cout_q_empty; + + VX_fifo_queue #( + .DATAW (COUT_QUEUE_DATAW), + .DEPTH (COUT_QUEUE_SIZE) + ) cout_queue ( + .clk (clk), + .reset (reset), + .push (cout_q_push), + .pop (cout_q_pop), + .data_in ({cout_tid, cout_char}), + .data_out (cout_q_dout), + .empty (cout_q_empty), + .full (cout_q_full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + // SCOPE ////////////////////////////////////////////////////////////////////// + +`ifdef DBG_SCOPE_AFU +`ifdef SCOPE + wire mem_req_fire = mem_bus_if[0].req_valid && mem_bus_if[0].req_ready; + wire mem_rsp_fire = mem_bus_if[0].rsp_valid && mem_bus_if[0].rsp_ready; + wire avs_write_fire = avs_write[0] && ~avs_waitrequest[0]; + wire avs_read_fire = avs_read[0] && ~avs_waitrequest[0]; + wire [$bits(t_local_mem_addr)-1:0] mem_bus_if_addr = mem_bus_if[0].req_data.addr; + + reg [STATE_WIDTH-1:0] state_prev; + always @(posedge clk) begin + state_prev <= state; + end + wire state_changed = (state != state_prev); + + VX_scope_tap #( + .SCOPE_ID (0), + .TRIGGERW (24), + .PROBEW (431) + ) scope_tap ( + .clk(clk), + .reset(scope_reset_w[0]), + .start(1'b0), + .stop(1'b0), + .triggers({ + reset, + state_changed, + mem_req_fire, + mem_rsp_fire, + avs_write_fire, + avs_read_fire, + avs_waitrequest[0], + avs_readdatavalid[0], + cp2af_sRxPort.c0.mmioRdValid, + cp2af_sRxPort.c0.mmioWrValid, + cp2af_sRxPort.c0.rspValid, + cp2af_sRxPort.c1.rspValid, + af2cp_sTxPort.c0.valid, + af2cp_sTxPort.c1.valid, + cp2af_sRxPort.c0TxAlmFull, + cp2af_sRxPort.c1TxAlmFull, + af2cp_sTxPort.c2.mmioRdValid, + cci_wr_req_fire, + cci_wr_rsp_fire, + cci_rd_req_fire, + cci_rd_rsp_fire, + cci_pending_reads_full, + cci_pending_writes_empty, + cci_pending_writes_full + }), + .probes({ + cmd_type, + state, + mmio_hdr.address, + mmio_hdr.length, + cp2af_sRxPort.c0.hdr.mdata, + af2cp_sTxPort.c0.hdr.address, + af2cp_sTxPort.c0.hdr.mdata, + af2cp_sTxPort.c1.hdr.address, + avs_address[0], + avs_byteenable[0], + avs_burstcount[0], + cci_mem_rd_req_ctr, + cci_mem_wr_req_ctr, + cci_rd_req_ctr, + cci_rd_rsp_ctr, + cci_wr_req_ctr, + mem_bus_if_addr + }), + .bus_in(scope_bus_in_w[0]), + .bus_out(scope_bus_out_w[0]) + ); +`endif +`else + `SCOPE_IO_UNUSED_W(0) +`endif + + /////////////////////////////////////////////////////////////////////////////// + +`ifdef DBG_TRACE_AFU + always @(posedge clk) begin + for (integer i = 0; i < NUM_LOCAL_MEM_BANKS; ++i) begin + if (avs_write[i] && ~avs_waitrequest[i]) begin + `TRACE(2, ("%d: AVS Wr Req [%0d]: addr=0x%0h, byteen=0x%0h, burst=0x%0h, data=0x%0h\n", $time, i, `TO_FULL_ADDR(avs_address[i]), avs_byteenable[i], avs_burstcount[i], avs_writedata[i])); + end + if (avs_read[i] && ~avs_waitrequest[i]) begin + `TRACE(2, ("%d: AVS Rd Req [%0d]: addr=0x%0h, byteen=0x%0h, burst=0x%0h\n", $time, i, `TO_FULL_ADDR(avs_address[i]), avs_byteenable[i], avs_burstcount[i])); + end + if (avs_readdatavalid[i]) begin + `TRACE(2, ("%d: AVS Rd Rsp [%0d]: data=0x%0h\n", $time, i, avs_readdata[i])); + end + end + end +`endif + +endmodule diff --git a/hw/rtl/afu/opae/vortex_afu.vh b/hw/rtl/afu/opae/vortex_afu.vh new file mode 100644 index 00000000..6aa53298 --- /dev/null +++ b/hw/rtl/afu/opae/vortex_afu.vh @@ -0,0 +1,39 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VORTEX_AFU_VH +`define VORTEX_AFU_VH + +`define AFU_ACCEL_NAME "vortex_afu" +`define AFU_ACCEL_UUID 128'h35F9452B_25C2_434C_93D5_6F8C60DB361C + +`define AFU_IMAGE_CMD_MEM_READ 1 +`define AFU_IMAGE_CMD_MEM_WRITE 2 +`define AFU_IMAGE_CMD_RUN 3 +`define AFU_IMAGE_CMD_DCR_WRITE 4 +`define AFU_IMAGE_CMD_MAX_VALUE 4 + +`define AFU_IMAGE_MMIO_CMD_TYPE 10 +`define AFU_IMAGE_MMIO_CMD_ARG0 12 +`define AFU_IMAGE_MMIO_CMD_ARG1 14 +`define AFU_IMAGE_MMIO_CMD_ARG2 16 +`define AFU_IMAGE_MMIO_STATUS 18 +`define AFU_IMAGE_MMIO_SCOPE_READ 20 +`define AFU_IMAGE_MMIO_SCOPE_WRITE 22 +`define AFU_IMAGE_MMIO_DEV_CAPS 24 +`define AFU_IMAGE_MMIO_ISA_CAPS 26 + +`define AFU_IMAGE_POWER 0 +`define AFU_TOP_IFC "ccip_std_afu_avalon_mm" + +`endif // VORTEX_AFU_VH diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv deleted file mode 100644 index 7ef76233..00000000 --- a/hw/rtl/afu/vortex_afu.sv +++ /dev/null @@ -1,1033 +0,0 @@ -`include "VX_platform.vh" -`ifdef NOPAE -`IGNORE_WARNINGS_BEGIN -`include "vortex_afu.vh" -`IGNORE_WARNINGS_END -`else -`include "afu_json_info.vh" -`endif - -/* verilator lint_off IMPORTSTAR */ -import ccip_if_pkg::*; -import local_mem_cfg_pkg::*; -/* verilator lint_on IMPORTSTAR */ - -`include "VX_define.vh" - -module vortex_afu #( - parameter NUM_LOCAL_MEM_BANKS = 2 -) ( - // global signals - input clk, - input reset, - - // IF signals between CCI and AFU - input t_if_ccip_Rx cp2af_sRxPort, - output t_if_ccip_Tx af2cp_sTxPort, - - // Avalon signals for local memory access - output t_local_mem_data avs_writedata [NUM_LOCAL_MEM_BANKS], - input t_local_mem_data avs_readdata [NUM_LOCAL_MEM_BANKS], - output t_local_mem_addr avs_address [NUM_LOCAL_MEM_BANKS], - input logic avs_waitrequest [NUM_LOCAL_MEM_BANKS], - output logic avs_write [NUM_LOCAL_MEM_BANKS], - output logic avs_read [NUM_LOCAL_MEM_BANKS], - output t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS], - output t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS], - input avs_readdatavalid [NUM_LOCAL_MEM_BANKS] -); - -localparam LMEM_DATA_WIDTH = $bits(t_local_mem_data); -localparam LMEM_ADDR_WIDTH = $bits(t_local_mem_addr); -localparam LMEM_BURST_CTRW = $bits(t_local_mem_burst_cnt); - -localparam CCI_DATA_WIDTH = $bits(t_ccip_clData); -localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8; -localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_DATA_SIZE); - - -localparam AVS_RD_QUEUE_SIZE = 4; -localparam _VX_MEM_TAG_WIDTH = `VX_MEM_TAG_WIDTH; -localparam _AVS_REQ_TAGW_VX = _VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH); -localparam _AVS_REQ_TAGW_VX2 = `MAX(_VX_MEM_TAG_WIDTH, _AVS_REQ_TAGW_VX); -localparam _AVS_REQ_TAGW_CCI = CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH); -localparam _AVS_REQ_TAGW_CCI2 = `MAX(CCI_ADDR_WIDTH, _AVS_REQ_TAGW_CCI); -localparam AVS_REQ_TAGW = `MAX(_AVS_REQ_TAGW_VX2, _AVS_REQ_TAGW_CCI2); - -localparam CCI_RD_WINDOW_SIZE = 8; -localparam CCI_RW_PENDING_SIZE= 256; - -localparam AFU_ID_L = 16'h0002; // AFU ID Lower -localparam AFU_ID_H = 16'h0004; // AFU ID Higher - -localparam CMD_MEM_READ = `AFU_IMAGE_CMD_MEM_READ; -localparam CMD_MEM_WRITE = `AFU_IMAGE_CMD_MEM_WRITE; -localparam CMD_RUN = `AFU_IMAGE_CMD_RUN; - -localparam MMIO_CMD_TYPE = `AFU_IMAGE_MMIO_CMD_TYPE; -localparam MMIO_IO_ADDR = `AFU_IMAGE_MMIO_IO_ADDR; -localparam MMIO_MEM_ADDR = `AFU_IMAGE_MMIO_MEM_ADDR; -localparam MMIO_DATA_SIZE = `AFU_IMAGE_MMIO_DATA_SIZE; -localparam MMIO_STATUS = `AFU_IMAGE_MMIO_STATUS; - -localparam COUT_TID_WIDTH = $clog2(`IO_COUT_SIZE); -localparam COUT_QUEUE_DATAW = COUT_TID_WIDTH + 8; -localparam COUT_QUEUE_SIZE = 64; - -localparam MMIO_SCOPE_READ = `AFU_IMAGE_MMIO_SCOPE_READ; -localparam MMIO_SCOPE_WRITE = `AFU_IMAGE_MMIO_SCOPE_WRITE; - -localparam MMIO_DEV_CAPS = `AFU_IMAGE_MMIO_DEV_CAPS; - -localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE; -localparam CCI_RD_QUEUE_TAGW = $clog2(CCI_RD_WINDOW_SIZE); -localparam CCI_RD_QUEUE_DATAW = CCI_DATA_WIDTH + CCI_ADDR_WIDTH; - -localparam STATE_IDLE = 0; -localparam STATE_WRITE = 1; -localparam STATE_READ = 2; -localparam STATE_START = 3; -localparam STATE_MAX_VALUE = 4; -localparam STATE_WIDTH = $clog2(STATE_MAX_VALUE); - -`ifdef SCOPE -`SCOPE_DECL_SIGNALS -`endif - -wire [127:0] afu_id = `AFU_ACCEL_UUID; - -wire [63:0] dev_caps = {16'(`NUM_THREADS), 16'(`NUM_WARPS), 16'(`NUM_CORES * `NUM_CLUSTERS), 16'(`IMPLEMENTATION_ID)}; - -reg [STATE_WIDTH-1:0] state; - -// Vortex ports /////////////////////////////////////////////////////////////// - -wire vx_mem_req_valid; -wire vx_mem_req_rw; -wire [`VX_MEM_BYTEEN_WIDTH-1:0] vx_mem_req_byteen; -wire [`VX_MEM_ADDR_WIDTH-1:0] vx_mem_req_addr; -wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_req_data; -wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_req_tag; -wire vx_mem_req_ready; - -wire vx_mem_rsp_valid; -wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_rsp_data; -wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag; -wire vx_mem_rsp_ready; - -reg vx_reset; -wire vx_busy; - -// CMD variables ////////////////////////////////////////////////////////////// - -t_ccip_clAddr cmd_io_addr; -reg [CCI_ADDR_WIDTH-1:0] cmd_mem_addr; -reg [CCI_ADDR_WIDTH-1:0] cmd_data_size; - -`ifdef SCOPE -wire [63:0] cmd_scope_rdata; -wire [63:0] cmd_scope_wdata; -wire cmd_scope_read; -wire cmd_scope_write; -`endif - -// MMIO controller //////////////////////////////////////////////////////////// - -`IGNORE_UNUSED_BEGIN -t_ccip_c0_ReqMmioHdr mmio_hdr; -`IGNORE_UNUSED_END -assign mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr); - -`STATIC_ASSERT(($bits(t_ccip_c0_ReqMmioHdr)-$bits(mmio_hdr.address)) == 12, ("Oops!")) - -t_if_ccip_c2_Tx mmio_tx; -assign af2cp_sTxPort.c2 = mmio_tx; - -`ifdef SCOPE -assign cmd_scope_wdata = 64'(cp2af_sRxPort.c0.data); -assign cmd_scope_read = cp2af_sRxPort.c0.mmioRdValid && (MMIO_SCOPE_READ == mmio_hdr.address); -assign cmd_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_SCOPE_WRITE == mmio_hdr.address); -`endif - -wire [COUT_QUEUE_DATAW-1:0] cout_q_dout; -wire cout_q_full, cout_q_empty; - -wire [2:0] cmd_type = (cp2af_sRxPort.c0.mmioWrValid - && (MMIO_CMD_TYPE == mmio_hdr.address)) ? 3'(cp2af_sRxPort.c0.data) : 3'h0; - -// disable assertions until full reset -`ifndef VERILATOR -reg [$clog2(`RESET_DELAY+1)-1:0] assert_delay_ctr; -initial begin - $assertoff; -end -always @(posedge clk) begin - if (reset) begin - assert_delay_ctr <= 0; - end else begin - assert_delay_ctr <= assert_delay_ctr + 1; - if (assert_delay_ctr == (`RESET_DELAY-1)) begin - $asserton; // enable assertions - end - end -end -`endif - -always @(posedge clk) begin - if (reset) begin - mmio_tx.mmioRdValid <= 0; - mmio_tx.hdr <= 0; - end else begin - mmio_tx.mmioRdValid <= cp2af_sRxPort.c0.mmioRdValid; - mmio_tx.hdr.tid <= mmio_hdr.tid; - end - - // serve MMIO write request - if (cp2af_sRxPort.c0.mmioWrValid) begin - case (mmio_hdr.address) - MMIO_IO_ADDR: begin - cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); - `ifdef DBG_TRACE_AFU - dpi_trace("%d: MMIO_IO_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); - `endif - end - MMIO_MEM_ADDR: begin - cmd_mem_addr <= $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data); - `ifdef DBG_TRACE_AFU - dpi_trace("%d: MMIO_MEM_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data)); - `endif - end - MMIO_DATA_SIZE: begin - cmd_data_size <= $bits(cmd_data_size)'(cp2af_sRxPort.c0.data); - `ifdef DBG_TRACE_AFU - dpi_trace("%d: MMIO_DATA_SIZE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); - `endif - end - MMIO_CMD_TYPE: begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: MMIO_CMD_TYPE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_type)'(cp2af_sRxPort.c0.data)); - `endif - end - `ifdef SCOPE - MMIO_SCOPE_WRITE: begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: MMIO_SCOPE_WRITE: addr=%0h, data=%0h\n", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data)); - `endif - end - `endif - default: begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: Unknown MMIO Wr: addr=%0h, data=%0h\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); - `endif - end - endcase - end - - // serve MMIO read requests - if (cp2af_sRxPort.c0.mmioRdValid) begin - case (mmio_hdr.address) - // AFU header - 16'h0000: mmio_tx.data <= { - 4'b0001, // Feature type = AFU - 8'b0, // reserved - 4'b0, // afu minor revision = 0 - 7'b0, // reserved - 1'b1, // end of DFH list = 1 - 24'b0, // next DFH offset = 0 - 4'b0, // afu major revision = 0 - 12'b0 // feature ID = 0 - }; - AFU_ID_L: mmio_tx.data <= afu_id[63:0]; // afu id low - AFU_ID_H: mmio_tx.data <= afu_id[127:64]; // afu id hi - 16'h0006: mmio_tx.data <= 64'h0; // next AFU - 16'h0008: mmio_tx.data <= 64'h0; // reserved - MMIO_STATUS: begin - mmio_tx.data <= 64'({cout_q_dout, !cout_q_empty, 8'(state)}); - `ifdef DBG_TRACE_AFU - if (state != STATE_WIDTH'(mmio_tx.data)) begin - dpi_trace("%d: MMIO_STATUS: addr=%0h, state=%0d\n", $time, mmio_hdr.address, state); - end - `endif - end - `ifdef SCOPE - MMIO_SCOPE_READ: begin - mmio_tx.data <= cmd_scope_rdata; - `ifdef DBG_TRACE_AFU - dpi_trace("%d: MMIO_SCOPE_READ: addr=%0h, data=%0h\n", $time, mmio_hdr.address, cmd_scope_rdata); - `endif - end - `endif - MMIO_DEV_CAPS: begin - mmio_tx.data <= dev_caps; - `ifdef DBG_TRACE_AFU - dpi_trace("%d: MMIO_DEV_CAPS: addr=%0h, data=%0h\n", $time, mmio_hdr.address, dev_caps); - `endif - end - default: begin - mmio_tx.data <= 64'h0; - `ifdef DBG_TRACE_AFU - dpi_trace("%d: Unknown MMIO Rd: addr=%0h\n", $time, mmio_hdr.address); - `endif - end - endcase - end -end - -// COMMAND FSM //////////////////////////////////////////////////////////////// - -wire cmd_read_done; -reg cmd_write_done; -wire cmd_run_done; -reg vx_started; - -reg [$clog2(`RESET_DELAY+1)-1:0] vx_reset_ctr; -always @(posedge clk) begin - if (state == STATE_IDLE) begin - vx_reset_ctr <= 0; - end else if (state == STATE_START) begin - vx_reset_ctr <= vx_reset_ctr + 1; - end -end - -always @(posedge clk) begin - if (reset) begin - state <= STATE_IDLE; - vx_started <= 0; - vx_reset <= 0; - end else begin - case (state) - STATE_IDLE: begin - case (cmd_type) - CMD_MEM_READ: begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: STATE READ: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); - `endif - state <= STATE_READ; - end - CMD_MEM_WRITE: begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: STATE WRITE: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); - `endif - state <= STATE_WRITE; - end - CMD_RUN: begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: STATE START\n", $time); - `endif - vx_reset <= 1; - state <= STATE_START; - end - default: begin - state <= state; - end - endcase - end - - STATE_READ: begin - if (cmd_read_done) begin - state <= STATE_IDLE; - `ifdef DBG_TRACE_AFU - dpi_trace("%d: STATE IDLE\n", $time); - `endif - end - end - - STATE_WRITE: begin - if (cmd_write_done) begin - state <= STATE_IDLE; - `ifdef DBG_TRACE_AFU - dpi_trace("%d: STATE IDLE\n", $time); - `endif - end - end - - STATE_START: begin - // vortex reset cycles - if (vx_started) begin - if (cmd_run_done) begin - vx_started <= 0; - state <= STATE_IDLE; - `ifdef DBG_TRACE_AFU - dpi_trace("%d: STATE IDLE\n", $time); - `endif - end - end else begin - if (vx_reset_ctr == (`RESET_DELAY-1)) begin - vx_started <= 1; - vx_reset <= 0; - end - end - end - - default: begin - state <= state; - end - - endcase - end -end - -// AVS Controller ///////////////////////////////////////////////////////////// - -wire cci_mem_rd_req_valid; -wire cci_mem_wr_req_valid; -wire [CCI_RD_QUEUE_DATAW-1:0] cci_rdq_dout; - -wire cci_mem_req_valid; -wire cci_mem_req_rw; -wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_addr; -wire [CCI_DATA_WIDTH-1:0] cci_mem_req_data; -wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_tag; -wire cci_mem_req_ready; - -wire cci_mem_rsp_valid; -wire [CCI_DATA_WIDTH-1:0] cci_mem_rsp_data; -wire [CCI_ADDR_WIDTH-1:0] cci_mem_rsp_tag; -wire cci_mem_rsp_ready; - -//-- - -wire cci_mem_req_arb_valid; -wire cci_mem_req_arb_rw; -t_local_mem_byte_mask cci_mem_req_arb_byteen; -t_local_mem_addr cci_mem_req_arb_addr; -t_local_mem_data cci_mem_req_arb_data; -wire [AVS_REQ_TAGW-1:0] cci_mem_req_arb_tag; -wire cci_mem_req_arb_ready; - -wire cci_mem_rsp_arb_valid; -t_local_mem_data cci_mem_rsp_arb_data; -wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_arb_tag; -wire cci_mem_rsp_arb_ready; - -VX_to_mem #( - .SRC_DATA_WIDTH (CCI_DATA_WIDTH), - .DST_DATA_WIDTH (LMEM_DATA_WIDTH), - .SRC_ADDR_WIDTH (CCI_ADDR_WIDTH), - .DST_ADDR_WIDTH (LMEM_ADDR_WIDTH), - .SRC_TAG_WIDTH (CCI_ADDR_WIDTH), - .DST_TAG_WIDTH (AVS_REQ_TAGW) -) cci_to_mem ( - .clk (clk), - .reset (reset), - - .mem_req_valid_in (cci_mem_req_valid), - .mem_req_addr_in (cci_mem_req_addr), - .mem_req_rw_in (cci_mem_req_rw), - .mem_req_byteen_in ({CCI_DATA_SIZE{1'b1}}), - .mem_req_data_in (cci_mem_req_data), - .mem_req_tag_in (cci_mem_req_tag), - .mem_req_ready_in (cci_mem_req_ready), - - .mem_req_valid_out (cci_mem_req_arb_valid), - .mem_req_addr_out (cci_mem_req_arb_addr), - .mem_req_rw_out (cci_mem_req_arb_rw), - .mem_req_byteen_out (cci_mem_req_arb_byteen), - .mem_req_data_out (cci_mem_req_arb_data), - .mem_req_tag_out (cci_mem_req_arb_tag), - .mem_req_ready_out (cci_mem_req_arb_ready), - - .mem_rsp_valid_in (cci_mem_rsp_arb_valid), - .mem_rsp_data_in (cci_mem_rsp_arb_data), - .mem_rsp_tag_in (cci_mem_rsp_arb_tag), - .mem_rsp_ready_in (cci_mem_rsp_arb_ready), - - .mem_rsp_valid_out (cci_mem_rsp_valid), - .mem_rsp_data_out (cci_mem_rsp_data), - .mem_rsp_tag_out (cci_mem_rsp_tag), - .mem_rsp_ready_out (cci_mem_rsp_ready) -); - -//-- - -wire vx_mem_req_arb_valid; -wire vx_mem_req_arb_rw; -t_local_mem_byte_mask vx_mem_req_arb_byteen; -t_local_mem_addr vx_mem_req_arb_addr; -t_local_mem_data vx_mem_req_arb_data; -wire [AVS_REQ_TAGW-1:0] vx_mem_req_arb_tag; -wire vx_mem_req_arb_ready; - -wire vx_mem_rsp_arb_valid; -t_local_mem_data vx_mem_rsp_arb_data; -wire [AVS_REQ_TAGW-1:0] vx_mem_rsp_arb_tag; -wire vx_mem_rsp_arb_ready; - -wire vx_mem_is_cout; -wire vx_mem_req_valid_qual; -wire vx_mem_req_ready_qual; - -assign vx_mem_req_valid_qual = vx_mem_req_valid && vx_started; - -assign vx_mem_req_ready = vx_mem_is_cout ? ~cout_q_full : vx_mem_req_ready_qual; - -VX_to_mem #( - .SRC_DATA_WIDTH (`VX_MEM_DATA_WIDTH), - .DST_DATA_WIDTH (LMEM_DATA_WIDTH), - .SRC_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH), - .DST_ADDR_WIDTH (LMEM_ADDR_WIDTH), - .SRC_TAG_WIDTH (`VX_MEM_TAG_WIDTH), - .DST_TAG_WIDTH (AVS_REQ_TAGW) -) vx_to_mem ( - .clk (clk), - .reset (reset), - - .mem_req_valid_in (vx_mem_req_valid_qual), - .mem_req_addr_in (vx_mem_req_addr), - .mem_req_rw_in (vx_mem_req_rw), - .mem_req_byteen_in (vx_mem_req_byteen), - .mem_req_data_in (vx_mem_req_data), - .mem_req_tag_in (vx_mem_req_tag), - .mem_req_ready_in (vx_mem_req_ready_qual), - - .mem_req_valid_out (vx_mem_req_arb_valid), - .mem_req_addr_out (vx_mem_req_arb_addr), - .mem_req_rw_out (vx_mem_req_arb_rw), - .mem_req_byteen_out (vx_mem_req_arb_byteen), - .mem_req_data_out (vx_mem_req_arb_data), - .mem_req_tag_out (vx_mem_req_arb_tag), - .mem_req_ready_out (vx_mem_req_arb_ready), - - .mem_rsp_valid_in (vx_mem_rsp_arb_valid), - .mem_rsp_data_in (vx_mem_rsp_arb_data), - .mem_rsp_tag_in (vx_mem_rsp_arb_tag), - .mem_rsp_ready_in (vx_mem_rsp_arb_ready), - - .mem_rsp_valid_out (vx_mem_rsp_valid), - .mem_rsp_data_out (vx_mem_rsp_data), - .mem_rsp_tag_out (vx_mem_rsp_tag), - .mem_rsp_ready_out (vx_mem_rsp_ready) -); - -//-- - -wire mem_req_valid; -wire mem_req_rw; -t_local_mem_byte_mask mem_req_byteen; -t_local_mem_addr mem_req_addr; -t_local_mem_data mem_req_data; -wire [AVS_REQ_TAGW:0] mem_req_tag; -wire mem_req_ready; - -wire mem_rsp_valid; -t_local_mem_data mem_rsp_data; -wire [AVS_REQ_TAGW:0] mem_rsp_tag; -wire mem_rsp_ready; - -`RESET_RELAY (mem_arb_reset); - -VX_mem_arb #( - .NUM_REQS (2), - .DATA_WIDTH (LMEM_DATA_WIDTH), - .ADDR_WIDTH (LMEM_ADDR_WIDTH), - .TAG_IN_WIDTH (AVS_REQ_TAGW), - .TYPE ("P"), - .BUFFERED_REQ (2), - .BUFFERED_RSP (2) -) mem_arb ( - .clk (clk), - .reset (mem_arb_reset), - - // Source request - .req_valid_in ({vx_mem_req_arb_valid, cci_mem_req_arb_valid}), - .req_rw_in ({vx_mem_req_arb_rw, cci_mem_req_arb_rw}), - .req_byteen_in ({vx_mem_req_arb_byteen, cci_mem_req_arb_byteen}), - .req_addr_in ({vx_mem_req_arb_addr, cci_mem_req_arb_addr}), - .req_data_in ({vx_mem_req_arb_data, cci_mem_req_arb_data}), - .req_tag_in ({vx_mem_req_arb_tag, cci_mem_req_arb_tag}), - .req_ready_in ({vx_mem_req_arb_ready, cci_mem_req_arb_ready}), - - // Memory request - .req_valid_out (mem_req_valid), - .req_rw_out (mem_req_rw), - .req_byteen_out (mem_req_byteen), - .req_addr_out (mem_req_addr), - .req_data_out (mem_req_data), - .req_tag_out (mem_req_tag), - .req_ready_out (mem_req_ready), - - // Source response - .rsp_valid_out ({vx_mem_rsp_arb_valid, cci_mem_rsp_arb_valid}), - .rsp_data_out ({vx_mem_rsp_arb_data, cci_mem_rsp_arb_data}), - .rsp_tag_out ({vx_mem_rsp_arb_tag, cci_mem_rsp_arb_tag}), - .rsp_ready_out ({vx_mem_rsp_arb_ready, cci_mem_rsp_arb_ready}), - - // Memory response - .rsp_valid_in (mem_rsp_valid), - .rsp_tag_in (mem_rsp_tag), - .rsp_data_in (mem_rsp_data), - .rsp_ready_in (mem_rsp_ready) -); - -//-- - -`RESET_RELAY (avs_wrapper_reset); - -VX_avs_wrapper #( - .AVS_DATA_WIDTH (LMEM_DATA_WIDTH), - .AVS_ADDR_WIDTH (LMEM_ADDR_WIDTH), - .AVS_BURST_WIDTH (LMEM_BURST_CTRW), - .AVS_BANKS (NUM_LOCAL_MEM_BANKS), - .REQ_TAG_WIDTH (AVS_REQ_TAGW + 1), - .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE) -) avs_wrapper ( - .clk (clk), - .reset (avs_wrapper_reset), - - // Memory request - .mem_req_valid (mem_req_valid), - .mem_req_rw (mem_req_rw), - .mem_req_byteen (mem_req_byteen), - .mem_req_addr (mem_req_addr), - .mem_req_data (mem_req_data), - .mem_req_tag (mem_req_tag), - .mem_req_ready (mem_req_ready), - - // Memory response - .mem_rsp_valid (mem_rsp_valid), - .mem_rsp_data (mem_rsp_data), - .mem_rsp_tag (mem_rsp_tag), - .mem_rsp_ready (mem_rsp_ready), - - // AVS bus - .avs_writedata (avs_writedata), - .avs_readdata (avs_readdata), - .avs_address (avs_address), - .avs_waitrequest (avs_waitrequest), - .avs_write (avs_write), - .avs_read (avs_read), - .avs_byteenable (avs_byteenable), - .avs_burstcount (avs_burstcount), - .avs_readdatavalid(avs_readdatavalid) -); - -// CCI-P Read Request /////////////////////////////////////////////////////////// - -reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_ctr; -wire [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr; -reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr_base; - -wire cci_rd_req_fire; -t_ccip_clAddr cci_rd_req_addr; -reg cci_rd_req_valid, cci_rd_req_wait; -reg [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr; -wire [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr_next; -wire [CCI_RD_QUEUE_TAGW-1:0] cci_rd_req_tag; - -wire [CCI_RD_QUEUE_TAGW-1:0] cci_rd_rsp_tag; -reg [CCI_RD_QUEUE_TAGW-1:0] cci_rd_rsp_ctr; - -wire cci_rdq_push, cci_rdq_pop; -wire [CCI_RD_QUEUE_DATAW-1:0] cci_rdq_din; -wire cci_rdq_empty; - -always @(*) begin - af2cp_sTxPort.c0.valid = cci_rd_req_fire; - af2cp_sTxPort.c0.hdr = t_ccip_c0_ReqMemHdr'(0); - af2cp_sTxPort.c0.hdr.address = cci_rd_req_addr; - af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(cci_rd_req_tag); -end - -wire cci_mem_wr_req_fire = cci_mem_wr_req_valid && cci_mem_req_ready; - -wire cci_rd_rsp_fire = cp2af_sRxPort.c0.rspValid - && (cp2af_sRxPort.c0.hdr.resp_type == eRSP_RDLINE); - -assign cci_rd_req_tag = CCI_RD_QUEUE_TAGW'(cci_rd_req_ctr); -assign cci_rd_rsp_tag = CCI_RD_QUEUE_TAGW'(cp2af_sRxPort.c0.hdr.mdata); - -assign cci_rdq_push = cci_rd_rsp_fire; -assign cci_rdq_pop = cci_mem_wr_req_fire; -assign cci_rdq_din = {cp2af_sRxPort.c0.data, cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(cci_rd_rsp_tag)}; - -wire [$clog2(CCI_RD_QUEUE_SIZE+1)-1:0] cci_pending_reads; -wire cci_pending_reads_full; -VX_pending_size #( - .SIZE (CCI_RD_QUEUE_SIZE) -) cci_rd_pending_size ( - .clk (clk), - .reset (reset), - .incr (cci_rd_req_fire), - .decr (cci_rdq_pop), - .full (cci_pending_reads_full), - .size (cci_pending_reads), - `UNUSED_PIN (empty) -); -`UNUSED_VAR (cci_pending_reads) - -assign cci_rd_req_ctr_next = cci_rd_req_ctr + CCI_ADDR_WIDTH'(cci_rd_req_fire ? 1 : 0); - -assign cci_rd_req_fire = cci_rd_req_valid && !(cci_rd_req_wait || cci_pending_reads_full); - -assign cci_mem_wr_req_valid = !cci_rdq_empty; - -assign cci_mem_wr_req_addr = cci_rdq_dout[CCI_ADDR_WIDTH-1:0]; - -// Send read requests to CCI -always @(posedge clk) begin - if (reset) begin - cci_rd_req_valid <= 0; - cci_rd_req_wait <= 0; - end else begin - if ((STATE_IDLE == state) - && (CMD_MEM_WRITE == cmd_type)) begin - cci_rd_req_valid <= (cmd_data_size != 0); - cci_rd_req_wait <= 0; - end - - cci_rd_req_valid <= (STATE_WRITE == state) - && (cci_rd_req_ctr_next != cmd_data_size) - && !cp2af_sRxPort.c0TxAlmFull; - - if (cci_rd_req_fire && (cci_rd_req_tag == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1))) begin - cci_rd_req_wait <= 1; // end current request batch - end - - if (cci_rd_rsp_fire && (cci_rd_rsp_ctr == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1))) begin - cci_rd_req_wait <= 0; // begin new request batch - end - end - - if ((STATE_IDLE == state) - && (CMD_MEM_WRITE == cmd_type)) begin - cci_rd_req_addr <= cmd_io_addr; - cci_rd_req_ctr <= 0; - cci_rd_rsp_ctr <= 0; - cci_mem_wr_req_ctr <= 0; - cci_mem_wr_req_addr_base <= cmd_mem_addr; - cmd_write_done <= 0; - end - - if (cci_rd_req_fire) begin - cci_rd_req_addr <= cci_rd_req_addr + 1; - cci_rd_req_ctr <= cci_rd_req_ctr + 1; - `ifdef DBG_TRACE_AFU - dpi_trace("%d: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads); - `endif - end - - if (cci_rd_rsp_fire) begin - cci_rd_rsp_ctr <= cci_rd_rsp_ctr + CCI_RD_QUEUE_TAGW'(1); - if (CCI_RD_QUEUE_TAGW'(cci_rd_rsp_ctr) == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin - cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE); - end - `ifdef DBG_TRACE_AFU - dpi_trace("%d: CCI Rd Rsp: idx=%0d, ctr=%0d, data=%0h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data); - `endif - end - - if (cci_rdq_pop) begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads); - `endif - end - - if (cci_mem_wr_req_fire) begin - cci_mem_wr_req_ctr <= cci_mem_wr_req_ctr + CCI_ADDR_WIDTH'(1); - if (cci_mem_wr_req_ctr == (cmd_data_size-1)) begin - cmd_write_done <= 1; - end - end -end - -`RESET_RELAY (cci_rdq_reset); - -VX_fifo_queue #( - .DATAW (CCI_RD_QUEUE_DATAW), - .SIZE (CCI_RD_QUEUE_SIZE), - .OUT_REG (1) -) cci_rd_req_queue ( - .clk (clk), - .reset (cci_rdq_reset), - .push (cci_rdq_push), - .pop (cci_rdq_pop), - .data_in (cci_rdq_din), - .data_out (cci_rdq_dout), - .empty (cci_rdq_empty), - `UNUSED_PIN (full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (alm_full), - `UNUSED_PIN (size) -); - -`ifdef VERILATOR -`DEBUG_BLOCK( - reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask; - always @(posedge clk) begin - if (reset) begin - dbg_cci_rd_rsp_mask <= 0; - end else begin - if (cci_rd_rsp_fire) begin - if (cci_rd_rsp_ctr == 0) begin - dbg_cci_rd_rsp_mask <= (CCI_RD_WINDOW_SIZE'(1) << cci_rd_rsp_tag); - end else begin - assert(!dbg_cci_rd_rsp_mask[cci_rd_rsp_tag]); - dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] <= 1; - end - end - end - end -) -`endif - -// CCI-P Write Request ////////////////////////////////////////////////////////// - -reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_ctr; -reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr; -reg cci_mem_rd_req_done; - -reg [CCI_ADDR_WIDTH-1:0] cci_wr_req_ctr; -reg cci_wr_req_fire; -t_ccip_clAddr cci_wr_req_addr; -t_ccip_clData cci_wr_req_data; -reg cci_wr_req_done; - -always @(*) begin - af2cp_sTxPort.c1.valid = cci_wr_req_fire; - af2cp_sTxPort.c1.hdr = t_ccip_c1_ReqMemHdr'(0); - af2cp_sTxPort.c1.hdr.sop = 1; // single line write mode - af2cp_sTxPort.c1.hdr.address = cci_wr_req_addr; - af2cp_sTxPort.c1.data = cci_wr_req_data; -end - -wire cci_mem_rd_req_fire = cci_mem_rd_req_valid && cci_mem_req_ready; -wire cci_mem_rd_rsp_fire = cci_mem_rsp_valid && cci_mem_rsp_ready; - -wire cci_wr_rsp_fire = (STATE_READ == state) - && cp2af_sRxPort.c1.rspValid - && (cp2af_sRxPort.c1.hdr.resp_type == eRSP_WRLINE); - -wire [$clog2(CCI_RW_PENDING_SIZE+1)-1:0] cci_pending_writes; -wire cci_pending_writes_empty; -wire cci_pending_writes_full; - -VX_pending_size #( - .SIZE (CCI_RW_PENDING_SIZE) -) cci_wr_pending_size ( - .clk (clk), - .reset (reset), - .incr (cci_mem_rd_rsp_fire), - .decr (cci_wr_rsp_fire), - .empty (cci_pending_writes_empty), - .full (cci_pending_writes_full), - .size (cci_pending_writes) -); -`UNUSED_VAR (cci_pending_writes) - -assign cci_mem_rd_req_valid = (STATE_READ == state) - && !cci_mem_rd_req_done; - -assign cci_mem_rsp_ready = !cp2af_sRxPort.c1TxAlmFull - && !cci_pending_writes_full; - -assign cmd_read_done = cci_wr_req_done - && cci_pending_writes_empty; - -// Send write requests to CCI -always @(posedge clk) -begin - if (reset) begin - cci_wr_req_fire <= 0; - end else begin - cci_wr_req_fire <= cci_mem_rd_rsp_fire; - end - - if ((STATE_IDLE == state) - && (CMD_MEM_READ == cmd_type)) begin - cci_mem_rd_req_ctr <= 0; - cci_mem_rd_req_addr <= cmd_mem_addr; - cci_mem_rd_req_done <= 0; - cci_wr_req_ctr <= cmd_data_size; - cci_wr_req_done <= 0; - end - - if (cci_mem_rd_req_fire) begin - cci_mem_rd_req_addr <= cci_mem_rd_req_addr + CCI_ADDR_WIDTH'(1); - cci_mem_rd_req_ctr <= cci_mem_rd_req_ctr + CCI_ADDR_WIDTH'(1); - if (cci_mem_rd_req_ctr == (cmd_data_size-1)) begin - cci_mem_rd_req_done <= 1; - end - end - - cci_wr_req_addr <= cmd_io_addr + t_ccip_clAddr'(cci_mem_rsp_tag); - cci_wr_req_data <= t_ccip_clData'(cci_mem_rsp_data); - - if (cci_wr_req_fire) begin - `ASSERT(cci_wr_req_ctr != 0, ("runtime error")); - cci_wr_req_ctr <= cci_wr_req_ctr - CCI_ADDR_WIDTH'(1); - if (cci_wr_req_ctr == CCI_ADDR_WIDTH'(1)) begin - cci_wr_req_done <= 1; - end - `ifdef DBG_TRACE_AFU - dpi_trace("%d: CCI Wr Req: addr=%0h, rem=%0d, pending=%0d, data=%0h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data); - `endif - end - - if (cci_wr_rsp_fire) begin - `ifdef DBG_TRACE_AFU - dpi_trace("%d: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes); - `endif - end -end - -//-- - -assign cci_mem_req_rw = state[0]; // STATE_WRITE=00, STATE_WRITE=01 -assign cci_mem_req_valid = cci_mem_req_rw ? cci_mem_wr_req_valid : cci_mem_rd_req_valid; -assign cci_mem_req_addr = cci_mem_req_rw ? cci_mem_wr_req_addr : cci_mem_rd_req_addr; -assign cci_mem_req_data = cci_rdq_dout[CCI_RD_QUEUE_DATAW-1:CCI_ADDR_WIDTH]; -assign cci_mem_req_tag = cci_mem_req_rw ? cci_mem_wr_req_ctr : cci_mem_rd_req_ctr; - -// Vortex ///////////////////////////////////////////////////////////////////// - -assign cmd_run_done = !vx_busy; - -Vortex vortex ( - `SCOPE_BIND_afu_vortex - - .clk (clk), - .reset (reset || vx_reset), - - // Memory request - .mem_req_valid (vx_mem_req_valid), - .mem_req_rw (vx_mem_req_rw), - .mem_req_byteen (vx_mem_req_byteen), - .mem_req_addr (vx_mem_req_addr), - .mem_req_data (vx_mem_req_data), - .mem_req_tag (vx_mem_req_tag), - .mem_req_ready (vx_mem_req_ready), - - // Memory response - .mem_rsp_valid (vx_mem_rsp_valid), - .mem_rsp_data (vx_mem_rsp_data), - .mem_rsp_tag (vx_mem_rsp_tag), - .mem_rsp_ready (vx_mem_rsp_ready), - - // status - .busy (vx_busy) -); - -// COUT HANDLING ////////////////////////////////////////////////////////////// - -wire [COUT_TID_WIDTH-1:0] cout_tid; -wire [7:0] cout_char; - -VX_onehot_encoder #( - .N (`VX_MEM_BYTEEN_WIDTH) -) cout_tid_enc ( - .data_in (vx_mem_req_byteen), - .data_out (cout_tid), - `UNUSED_PIN (valid_out) -); - -VX_onehot_mux #( - .DATAW (8), - .N (`VX_MEM_BYTEEN_WIDTH) -) cout_char_mux ( - .data_in (vx_mem_req_data), - .sel_in (vx_mem_req_byteen), - .data_out (cout_char) -); - -assign vx_mem_is_cout = (vx_mem_req_addr == `VX_MEM_ADDR_WIDTH'(`IO_COUT_ADDR >> (32 - `VX_MEM_ADDR_WIDTH))); - -wire cout_q_push = vx_mem_req_valid - && vx_started - && vx_mem_is_cout - && ~cout_q_full; - -wire cout_q_pop = cp2af_sRxPort.c0.mmioRdValid - && (mmio_hdr.address == MMIO_STATUS) - && ~cout_q_empty; - -VX_fifo_queue #( - .DATAW (COUT_QUEUE_DATAW), - .SIZE (COUT_QUEUE_SIZE) -) cout_queue ( - .clk (clk), - .reset (reset), - .push (cout_q_push), - .pop (cout_q_pop), - .data_in ({cout_tid, cout_char}), - .data_out (cout_q_dout), - .empty (cout_q_empty), - .full (cout_q_full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (alm_full), - `UNUSED_PIN (size) -); - -// SCOPE ////////////////////////////////////////////////////////////////////// - -`ifdef SCOPE - -`SCOPE_ASSIGN (cmd_type, cmd_type); -`SCOPE_ASSIGN (state, state); -`SCOPE_ASSIGN (cci_sRxPort_c0_mmioRdValid, cp2af_sRxPort.c0.mmioRdValid); -`SCOPE_ASSIGN (cci_sRxPort_c0_mmioWrValid, cp2af_sRxPort.c0.mmioWrValid); -`SCOPE_ASSIGN (mmio_hdr_address, mmio_hdr.address); -`SCOPE_ASSIGN (mmio_hdr_length, mmio_hdr.length); -`SCOPE_ASSIGN (cci_sRxPort_c0_hdr_mdata, cp2af_sRxPort.c0.hdr.mdata); -`SCOPE_ASSIGN (cci_sRxPort_c0_rspValid, cp2af_sRxPort.c0.rspValid); -`SCOPE_ASSIGN (cci_sRxPort_c1_rspValid, cp2af_sRxPort.c1.rspValid); -`SCOPE_ASSIGN (cci_sTxPort_c0_valid, af2cp_sTxPort.c0.valid); -`SCOPE_ASSIGN (cci_sTxPort_c0_hdr_address, af2cp_sTxPort.c0.hdr.address); -`SCOPE_ASSIGN (cci_sTxPort_c0_hdr_mdata, af2cp_sTxPort.c0.hdr.mdata); -`SCOPE_ASSIGN (cci_sTxPort_c1_valid, af2cp_sTxPort.c1.valid); -`SCOPE_ASSIGN (cci_sTxPort_c1_hdr_address, af2cp_sTxPort.c1.hdr.address); -`SCOPE_ASSIGN (cci_sTxPort_c2_mmioRdValid, af2cp_sTxPort.c2.mmioRdValid); -`SCOPE_ASSIGN (cci_sRxPort_c0TxAlmFull, cp2af_sRxPort.c0TxAlmFull); -`SCOPE_ASSIGN (cci_sRxPort_c1TxAlmFull, cp2af_sRxPort.c1TxAlmFull); -`SCOPE_ASSIGN (avs_address, avs_address[0]); -`SCOPE_ASSIGN (avs_waitrequest, avs_waitrequest[0]); -`SCOPE_ASSIGN (avs_write_fire, avs_write[0] && !avs_waitrequest[0]); -`SCOPE_ASSIGN (avs_read_fire, avs_read[0] && !avs_waitrequest[0]); -`SCOPE_ASSIGN (avs_byteenable, avs_byteenable[0]); -`SCOPE_ASSIGN (avs_burstcount, avs_burstcount[0]); -`SCOPE_ASSIGN (avs_readdatavalid, avs_readdatavalid[0]); -`SCOPE_ASSIGN (cci_mem_rd_req_ctr, cci_mem_rd_req_ctr); -`SCOPE_ASSIGN (cci_mem_wr_req_ctr, cci_mem_wr_req_ctr); -`SCOPE_ASSIGN (cci_rd_req_ctr, cci_rd_req_ctr); -`SCOPE_ASSIGN (cci_rd_rsp_ctr, cci_rd_rsp_ctr); -`SCOPE_ASSIGN (cci_wr_req_ctr, cci_wr_req_ctr); -`SCOPE_ASSIGN (cci_wr_req_fire, cci_wr_req_fire); -`SCOPE_ASSIGN (cci_wr_rsp_fire, cci_wr_rsp_fire); -`SCOPE_ASSIGN (cci_rd_req_fire, cci_rd_req_fire); -`SCOPE_ASSIGN (cci_rd_rsp_fire, cci_rd_rsp_fire); -`SCOPE_ASSIGN (cci_pending_reads_full, cci_pending_reads_full); -`SCOPE_ASSIGN (cci_pending_writes_empty, cci_pending_writes_empty); -`SCOPE_ASSIGN (cci_pending_writes_full, cci_pending_writes_full); -`SCOPE_ASSIGN (afu_mem_req_fire, (mem_req_valid && mem_req_ready)); -`SCOPE_ASSIGN (afu_mem_req_addr, mem_req_addr); -`SCOPE_ASSIGN (afu_mem_req_tag, mem_req_tag); -`SCOPE_ASSIGN (afu_mem_rsp_fire, (mem_rsp_valid && mem_rsp_ready)); -`SCOPE_ASSIGN (afu_mem_rsp_tag, mem_rsp_tag); - -wire scope_changed = `SCOPE_TRIGGER; - -`RESET_RELAY (scope_reset); - -VX_scope #( - .DATAW ($bits({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST})), - .BUSW (64), - .SIZE (`SCOPE_SIZE), - .UPDW ($bits({`SCOPE_UPDATE_LIST})) -) scope ( - .clk (clk), - .reset (scope_reset), - .start (1'b0), - .stop (1'b0), - .changed (scope_changed), - .data_in ({`SCOPE_DATA_LIST,`SCOPE_UPDATE_LIST}), - .bus_in (cmd_scope_wdata), - .bus_out (cmd_scope_rdata), - .bus_read (cmd_scope_read), - .bus_write(cmd_scope_write) -); - -`else - `UNUSED_PARAM (MMIO_SCOPE_READ) - `UNUSED_PARAM (MMIO_SCOPE_WRITE) -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/afu/vortex_afu.vh b/hw/rtl/afu/vortex_afu.vh deleted file mode 100644 index 386710e5..00000000 --- a/hw/rtl/afu/vortex_afu.vh +++ /dev/null @@ -1,44 +0,0 @@ -`ifndef __VORTEX_AFU__ -`define __VORTEX_AFU__ - -`include "ccip_if_pkg.sv" - -`define PLATFORM_PROVIDES_LOCAL_MEMORY - -`ifndef PLATFORM_PARAM_LOCAL_MEMORY_BANKS -`define PLATFORM_PARAM_LOCAL_MEMORY_BANKS 2 -`endif - -`ifndef PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH -`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26 -`endif - -`ifndef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH -`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512 -`endif - -`ifndef PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH -`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4 -`endif - -`include "local_mem_cfg_pkg.sv" - -`define AFU_ACCEL_NAME "vortex_afu" -`define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c - -`define AFU_IMAGE_CMD_MEM_READ 1 -`define AFU_IMAGE_CMD_MEM_WRITE 2 -`define AFU_IMAGE_CMD_RUN 3 -`define AFU_IMAGE_MMIO_CMD_TYPE 10 -`define AFU_IMAGE_MMIO_DATA_SIZE 16 -`define AFU_IMAGE_MMIO_IO_ADDR 12 -`define AFU_IMAGE_MMIO_MEM_ADDR 14 -`define AFU_IMAGE_MMIO_SCOPE_READ 20 -`define AFU_IMAGE_MMIO_SCOPE_WRITE 22 -`define AFU_IMAGE_MMIO_DEV_CAPS 24 -`define AFU_IMAGE_MMIO_STATUS 18 - -`define AFU_IMAGE_POWER 0 -`define AFU_TOP_IFC "ccip_std_afu_avalon_mm" - -`endif \ No newline at end of file diff --git a/hw/rtl/afu/xrt/VX_afu_ctrl.sv b/hw/rtl/afu/xrt/VX_afu_ctrl.sv new file mode 100644 index 00000000..5dcdb8f6 --- /dev/null +++ b/hw/rtl/afu/xrt/VX_afu_ctrl.sv @@ -0,0 +1,419 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "vortex_afu.vh" + +module VX_afu_ctrl #( + parameter AXI_ADDR_WIDTH = 8, + parameter AXI_DATA_WIDTH = 32, + parameter AXI_NUM_BANKS = 1 +) ( + // axi4 lite slave signals + input wire clk, + input wire reset, + input wire clk_en, + + input wire s_axi_awvalid, + input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + output wire s_axi_awready, + + input wire s_axi_wvalid, + input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + output wire s_axi_wready, + + output wire s_axi_bvalid, + output wire [1:0] s_axi_bresp, + input wire s_axi_bready, + + input wire s_axi_arvalid, + input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, + output wire s_axi_arready, + + output wire s_axi_rvalid, + output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + input wire s_axi_rready, + + output wire ap_reset, + output wire ap_start, + input wire ap_done, + input wire ap_ready, + input wire ap_idle, + output wire interrupt, + +`ifdef SCOPE + input wire scope_bus_in, + output wire scope_bus_out, +`endif + + output wire [63:0] mem_base [AXI_NUM_BANKS], + + output wire dcr_wr_valid, + output wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr, + output wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data +); + + // Address Info + // 0x00 : Control signals + // bit 0 - ap_start (Read/Write/COH) + // bit 1 - ap_done (Read/COR) + // bit 2 - ap_idle (Read) + // bit 3 - ap_ready (Read) + // bit 4 - ap_reset (Write) + // bit 7 - auto_restart (Read/Write) + // others - reserved + // 0x04 : Global Interrupt Enable Register + // bit 0 - Global Interrupt Enable (Read/Write) + // others - reserved + // 0x08 : IP Interrupt Enable Register (Read/Write) + // bit 0 - Channel 0 (ap_done) + // bit 1 - Channel 1 (ap_ready) + // others - reserved + // 0x0c : IP Interrupt Status Register (Read/TOW) + // bit 0 - Channel 0 (ap_done) + // bit 1 - Channel 1 (ap_ready) + // others - reserved + // 0x10 : Low 32-bit Data signal of DEV_CAPS + // 0x14 : High 32-bit Data signal of DEV_CAPS + // 0x18 : Control signal of DEV_CAPS + // 0x1C : Low 32-bit Data signal of ISA_CAPS + // 0x20 : High 32-bit Data signal of ISA_CAPS + // 0x24 : Control signal of ISA_CAPS + // 0x28 : Low 32-bit Data signal of DCR + // 0x2C : High 32-bit Data signal of DCR + // 0x30 : Control signal of DCR + // 0x34 : Low 32-bit Data signal of SCP + // 0x38 : High 32-bit Data signal of SCP + // 0x3C : Control signal of SCP + // 0x40 : Low 32-bit Data signal of MEM + // 0x44 : High 32-bit Data signal of MEM + // 0x48 : Control signal of MEM + // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) + + // Parameters + localparam + ADDR_AP_CTRL = 8'h00, + ADDR_GIE = 8'h04, + ADDR_IER = 8'h08, + ADDR_ISR = 8'h0C, + + ADDR_DEV_0 = 8'h10, + ADDR_DEV_1 = 8'h14, + ADDR_DEV_CTRL = 8'h18, + + ADDR_ISA_0 = 8'h1C, + ADDR_ISA_1 = 8'h20, + ADDR_ISA_CTRL = 8'h24, + + ADDR_DCR_0 = 8'h28, + ADDR_DCR_1 = 8'h2C, + ADDR_DCR_CTRL = 8'h30, + + ADDR_SCP_0 = 8'h34, + ADDR_SCP_1 = 8'h38, + ADDR_SCP_CTRL = 8'h3C, + + ADDR_MEM_0 = 8'h40, + ADDR_MEM_1 = 8'h44, + ADDR_MEM_CTRL = 8'h48, + + ADDR_BITS = 8; + + localparam + WSTATE_IDLE = 2'd0, + WSTATE_DATA = 2'd1, + WSTATE_RESP = 2'd2; + + localparam + RSTATE_IDLE = 2'd0, + RSTATE_DATA = 2'd1; + + // device caps + wire [63:0] dev_caps = {16'b0, + 8'(`SM_ENABLED ? `SMEM_LOG_SIZE : 0), + 16'(`NUM_CORES * `NUM_CLUSTERS), + 8'(`NUM_WARPS), + 8'(`NUM_THREADS), + 8'(`IMPLEMENTATION_ID)}; + + wire [63:0] isa_caps = {32'(`MISA_EXT), + 2'(`CLOG2(`XLEN)-4), + 30'(`MISA_STD)}; + + reg [1:0] wstate; + reg [ADDR_BITS-1:0] waddr; + wire [31:0] wmask; + wire s_axi_aw_fire; + wire s_axi_w_fire; + + reg [1:0] rstate; + reg [31:0] rdata; + wire [ADDR_BITS-1:0] raddr; + wire s_axi_ar_fire; + + reg ap_reset_r; + reg ap_start_r; + reg auto_restart_r; + reg gie_r; + reg [1:0] ier_r; + reg [1:0] isr_r; + reg [63:0] mem_r [AXI_NUM_BANKS]; + reg [31:0] dcra_r; + reg [31:0] dcrv_r; + reg dcr_wr_valid_r; + +`ifdef SCOPE + + reg [63:0] scope_bus_wdata; + reg [63:0] scope_bus_rdata; + reg [5:0] scope_bus_ctr; + + reg cmd_scope_reading; + reg cmd_scope_writing; + reg scope_bus_out_r; + + always @(posedge clk) begin + if (reset) begin + cmd_scope_reading <= 0; + cmd_scope_writing <= 0; + scope_bus_ctr <= '0; + scope_bus_out_r <= 0; + end else if (clk_en) begin + if (s_axi_w_fire && waddr == ADDR_SCP_0) begin + scope_bus_wdata[31:0] <= (s_axi_wdata & wmask) | (scope_bus_wdata[31:0] & ~wmask); + end + if (s_axi_w_fire && waddr == ADDR_SCP_1) begin + scope_bus_wdata[63:32] <= (s_axi_wdata & wmask) | (scope_bus_wdata[63:32] & ~wmask); + cmd_scope_writing <= 1; + scope_bus_out_r <= 1; + scope_bus_ctr <= 63; + end + if (scope_bus_in) begin + cmd_scope_reading <= 1; + scope_bus_ctr <= 63; + end + if (cmd_scope_reading) begin + scope_bus_rdata <= {scope_bus_rdata[62:0], scope_bus_in}; + scope_bus_ctr <= scope_bus_ctr - 1; + if (scope_bus_ctr == 0) begin + cmd_scope_reading <= 0; + end + end + if (cmd_scope_writing) begin + scope_bus_out_r <= 1'(scope_bus_wdata >> scope_bus_ctr); + scope_bus_ctr <= scope_bus_ctr - 1; + if (scope_bus_ctr == 0) begin + cmd_scope_writing <= 0; + end + end + end + end + + assign scope_bus_out = scope_bus_out_r; + +`endif + + // AXI Write + + assign s_axi_awready = (wstate == WSTATE_IDLE); + assign s_axi_wready = (wstate == WSTATE_DATA); + assign s_axi_bvalid = (wstate == WSTATE_RESP); + assign s_axi_bresp = 2'b00; // OKAY + + assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready; + assign s_axi_w_fire = s_axi_wvalid && s_axi_wready; + + for (genvar i = 0; i < 4; ++i) begin + assign wmask[8 * i +: 8] = {8{s_axi_wstrb[i]}}; + end + + // wstate + always @(posedge clk) begin + if (reset) begin + wstate <= WSTATE_IDLE; + end else if (clk_en) begin + case (wstate) + WSTATE_IDLE: wstate <= s_axi_awvalid ? WSTATE_DATA : WSTATE_IDLE; + WSTATE_DATA: wstate <= s_axi_wvalid ? WSTATE_RESP : WSTATE_DATA; + WSTATE_RESP: wstate <= s_axi_bready ? WSTATE_IDLE : WSTATE_RESP; + default: wstate <= WSTATE_IDLE; + endcase + end + end + + // waddr + always @(posedge clk) begin + if (clk_en) begin + if (s_axi_aw_fire) + waddr <= s_axi_awaddr[ADDR_BITS-1:0]; + end + end + + // wdata + always @(posedge clk) begin + if (reset) begin + ap_start_r <= 0; + ap_reset_r <= 0; + auto_restart_r <= 0; + + gie_r <= 0; + ier_r <= '0; + isr_r <= '0; + + dcra_r <= '0; + dcrv_r <= '0; + dcr_wr_valid_r <= 0; + + for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin + mem_r[i] <= '0; + end + end else if (clk_en) begin + if (ap_ready) + ap_start_r <= auto_restart_r; + + dcr_wr_valid_r <= 0; + + if (s_axi_w_fire) begin + case (waddr) + ADDR_AP_CTRL: begin + if (s_axi_wstrb[0]) begin + if (s_axi_wdata[0]) + ap_start_r <= 1; + if (s_axi_wdata[4]) + ap_reset_r <= 1; + if (s_axi_wdata[7]) + auto_restart_r <= 1; + end + end + ADDR_GIE: begin + if (s_axi_wstrb[0]) + gie_r <= s_axi_wdata[0]; + end + ADDR_IER: begin + if (s_axi_wstrb[0]) + ier_r <= s_axi_wdata[1:0]; + end + ADDR_ISR: begin + if (s_axi_wstrb[0]) + isr_r <= isr_r ^ s_axi_wdata[1:0]; + end + ADDR_DCR_0: begin + dcra_r <= (s_axi_wdata & wmask) | (dcra_r & ~wmask); + end + ADDR_DCR_1: begin + dcrv_r <= (s_axi_wdata & wmask) | (dcrv_r & ~wmask); + dcr_wr_valid_r <= 1; + end + default: begin + for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin + if (waddr == (ADDR_MEM_0 + i * 12)) begin + mem_r[i][31:0] <= (s_axi_wdata & wmask) | (mem_r[i][31:0] & ~wmask); + end + if (waddr == (ADDR_MEM_1 + i * 12)) begin + mem_r[i][63:32] <= (s_axi_wdata & wmask) | (mem_r[i][63:32] & ~wmask); + end + end + end + endcase + + if (ier_r[0] & ap_done) + isr_r[0] <= 1'b1; + if (ier_r[1] & ap_ready) + isr_r[1] <= 1'b1; + end + end + end + + // AXI Read + + assign s_axi_arready = (rstate == RSTATE_IDLE); + assign s_axi_rvalid = (rstate == RSTATE_DATA); + assign s_axi_rdata = rdata; + assign s_axi_rresp = 2'b00; // OKAY + + assign s_axi_ar_fire = s_axi_arvalid && s_axi_arready; + assign raddr = s_axi_araddr[ADDR_BITS-1:0]; + + // rstate + always @(posedge clk) begin + if (reset) begin + rstate <= RSTATE_IDLE; + end else if (clk_en) begin + case (rstate) + RSTATE_IDLE: rstate <= s_axi_arvalid ? RSTATE_DATA : RSTATE_IDLE; + RSTATE_DATA: rstate <= (s_axi_rready & s_axi_rvalid) ? RSTATE_IDLE : RSTATE_DATA; + default: rstate <= RSTATE_IDLE; + endcase + end + end + + // rdata + always @(posedge clk) begin + if (clk_en) begin + if (s_axi_ar_fire) begin + rdata <= '0; + case (raddr) + ADDR_AP_CTRL: begin + rdata[0] <= ap_start_r; + rdata[1] <= ap_done; + rdata[2] <= ap_idle; + rdata[3] <= ap_ready; + rdata[7] <= auto_restart_r; + end + ADDR_GIE: begin + rdata <= 32'(gie_r); + end + ADDR_IER: begin + rdata <= 32'(ier_r); + end + ADDR_ISR: begin + rdata <= 32'(isr_r); + end + ADDR_DEV_0: begin + rdata <= dev_caps[31:0]; + end + ADDR_DEV_1: begin + rdata <= dev_caps[63:32]; + end + ADDR_ISA_0: begin + rdata <= isa_caps[31:0]; + end + ADDR_ISA_1: begin + rdata <= isa_caps[63:32]; + end + `ifdef SCOPE + ADDR_SCP_0: begin + rdata <= scope_bus_rdata[31:0]; + end + ADDR_SCP_1: begin + rdata <= scope_bus_rdata[63:32]; + end + `endif + default:; + endcase + end + end + end + + assign ap_reset = ap_reset_r; + assign ap_start = ap_start_r; + assign interrupt = gie_r & (| isr_r); + + assign mem_base = mem_r; + + assign dcr_wr_valid = dcr_wr_valid_r; + assign dcr_wr_addr = `VX_DCR_ADDR_WIDTH'(dcra_r); + assign dcr_wr_data = `VX_DCR_DATA_WIDTH'(dcrv_r); + +endmodule diff --git a/hw/rtl/afu/xrt/VX_afu_wrap.sv b/hw/rtl/afu/xrt/VX_afu_wrap.sv new file mode 100644 index 00000000..3c4b3947 --- /dev/null +++ b/hw/rtl/afu/xrt/VX_afu_wrap.sv @@ -0,0 +1,412 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "vortex_afu.vh" + +module VX_afu_wrap #( + parameter C_S_AXI_CTRL_ADDR_WIDTH = 8, + parameter C_S_AXI_CTRL_DATA_WIDTH = 32, + parameter C_M_AXI_MEM_ID_WIDTH = 16, + parameter C_M_AXI_MEM_ADDR_WIDTH = 32, + parameter C_M_AXI_MEM_DATA_WIDTH = 512 +) ( + // System signals + input wire ap_clk, + input wire ap_rst_n, + + // AXI4 master interface + `REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA), + + // AXI4-Lite slave interface + input wire s_axi_ctrl_awvalid, + output wire s_axi_ctrl_awready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr, + input wire s_axi_ctrl_wvalid, + output wire s_axi_ctrl_wready, + input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata, + input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb, + input wire s_axi_ctrl_arvalid, + output wire s_axi_ctrl_arready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr, + output wire s_axi_ctrl_rvalid, + input wire s_axi_ctrl_rready, + output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata, + output wire [1:0] s_axi_ctrl_rresp, + output wire s_axi_ctrl_bvalid, + input wire s_axi_ctrl_bready, + output wire [1:0] s_axi_ctrl_bresp, + + output wire interrupt +); + localparam C_M_AXI_MEM_NUM_BANKS = `M_AXI_MEM_NUM_BANKS; + + localparam STATE_IDLE = 0; + localparam STATE_RUN = 1; + + wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS]; + + // convert memory interface to array + `REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON); + + wire clk = ap_clk; + wire reset = ~ap_rst_n; + + reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr; + reg [15:0] vx_pending_writes; + reg vx_busy_wait; + reg vx_running; + + wire vx_busy; + + wire [63:0] mem_base [C_M_AXI_MEM_NUM_BANKS]; + + wire dcr_wr_valid; + wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr; + wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data; + + reg state; + + wire ap_reset; + wire ap_start; + wire ap_idle = ~vx_running; + wire ap_done = ~(state == STATE_RUN || vx_pending_writes != 0); + wire ap_ready = 1'b1; + +`ifdef SCOPE + wire scope_bus_in; + wire scope_bus_out; + wire scope_reset = reset; +`endif + + always @(posedge ap_clk) begin + if (reset || ap_reset) begin + state <= STATE_IDLE; + vx_busy_wait <= 0; + vx_running <= 0; + end else begin + case (state) + STATE_IDLE: begin + if (ap_start) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: STATE RUN\n", $time)); + `endif + state <= STATE_RUN; + vx_running <= 0; + end + end + STATE_RUN: begin + if (vx_running) begin + if (vx_busy_wait) begin + // wait until processor goes busy + if (vx_busy) begin + vx_busy_wait <= 0; + end + end else begin + // wait until the processor is not busy + if (~vx_busy) begin + state <= STATE_IDLE; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: AFU: End execution\n", $time)); + `TRACE(2, ("%d: STATE IDLE\n", $time)); + `endif + end + end + end else begin + // wait until the reset sequence is complete + if (vx_reset_ctr == (`RESET_DELAY-1)) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%d: AFU: Begin execution\n", $time)); + `endif + vx_running <= 1; + vx_busy_wait <= 1; + end + end + end + endcase + end + end + + reg m_axi_mem_wfire; + reg m_axi_mem_bfire; + + always @(*) begin + m_axi_mem_wfire = 0; + m_axi_mem_bfire = 0; + for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin + m_axi_mem_wfire |= m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]; + m_axi_mem_bfire |= m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i]; + end + end + + always @(posedge ap_clk) begin + if (reset || ap_reset) begin + vx_pending_writes <= '0; + end else begin + if (m_axi_mem_wfire && ~m_axi_mem_bfire) + vx_pending_writes <= vx_pending_writes + 1; + if (~m_axi_mem_wfire && m_axi_mem_bfire) + vx_pending_writes <= vx_pending_writes - 1; + end + end + + always @(posedge ap_clk) begin + if (state == STATE_RUN) begin + vx_reset_ctr <= vx_reset_ctr + 1; + end else begin + vx_reset_ctr <= '0; + end + end + + VX_afu_ctrl #( + .AXI_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH), + .AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH), + .AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS) + ) afu_ctrl ( + .clk (ap_clk), + .reset (reset || ap_reset), + .clk_en (1'b1), + + .s_axi_awvalid (s_axi_ctrl_awvalid), + .s_axi_awready (s_axi_ctrl_awready), + .s_axi_awaddr (s_axi_ctrl_awaddr), + .s_axi_wvalid (s_axi_ctrl_wvalid), + .s_axi_wready (s_axi_ctrl_wready), + .s_axi_wdata (s_axi_ctrl_wdata), + .s_axi_wstrb (s_axi_ctrl_wstrb), + .s_axi_arvalid (s_axi_ctrl_arvalid), + .s_axi_arready (s_axi_ctrl_arready), + .s_axi_araddr (s_axi_ctrl_araddr), + .s_axi_rvalid (s_axi_ctrl_rvalid), + .s_axi_rready (s_axi_ctrl_rready), + .s_axi_rdata (s_axi_ctrl_rdata), + .s_axi_rresp (s_axi_ctrl_rresp), + .s_axi_bvalid (s_axi_ctrl_bvalid), + .s_axi_bready (s_axi_ctrl_bready), + .s_axi_bresp (s_axi_ctrl_bresp), + + .ap_reset (ap_reset), + .ap_start (ap_start), + .ap_done (ap_done), + .ap_ready (ap_ready), + .ap_idle (ap_idle), + .interrupt (interrupt), + + `ifdef SCOPE + .scope_bus_in (scope_bus_out), + .scope_bus_out (scope_bus_in), + `endif + + .mem_base (mem_base), + + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data) + ); + + wire [`XLEN-1:0] m_axi_mem_awaddr_w [C_M_AXI_MEM_NUM_BANKS]; + wire [`XLEN-1:0] m_axi_mem_araddr_w [C_M_AXI_MEM_NUM_BANKS]; + + for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin + assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]); + assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]); + end + + `SCOPE_IO_SWITCH (2) + + Vortex_axi #( + .AXI_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH), + .AXI_ADDR_WIDTH (`XLEN), + .AXI_TID_WIDTH (C_M_AXI_MEM_ID_WIDTH), + .AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS) + ) vortex_axi ( + `SCOPE_IO_BIND (1) + + .clk (ap_clk), + .reset (reset || ap_reset || ~vx_running), + + .m_axi_awvalid (m_axi_mem_awvalid_a), + .m_axi_awready (m_axi_mem_awready_a), + .m_axi_awaddr (m_axi_mem_awaddr_w), + .m_axi_awid (m_axi_mem_awid_a), + `UNUSED_PIN (m_axi_awlen), + `UNUSED_PIN (m_axi_awsize), + `UNUSED_PIN (m_axi_awburst), + `UNUSED_PIN (m_axi_awlock), + `UNUSED_PIN (m_axi_awcache), + `UNUSED_PIN (m_axi_awprot), + `UNUSED_PIN (m_axi_awqos), + `UNUSED_PIN (m_axi_awregion), + + .m_axi_wvalid (m_axi_mem_wvalid_a), + .m_axi_wready (m_axi_mem_wready_a), + .m_axi_wdata (m_axi_mem_wdata_a), + .m_axi_wstrb (m_axi_mem_wstrb_a), + .m_axi_wlast (m_axi_mem_wlast_a), + + .m_axi_bvalid (m_axi_mem_bvalid_a), + .m_axi_bready (m_axi_mem_bready_a), + .m_axi_bid (m_axi_mem_bid_a), + .m_axi_bresp (m_axi_mem_bresp_a), + + .m_axi_arvalid (m_axi_mem_arvalid_a), + .m_axi_arready (m_axi_mem_arready_a), + .m_axi_araddr (m_axi_mem_araddr_w), + .m_axi_arid (m_axi_mem_arid_a), + .m_axi_arlen (m_axi_mem_arlen_a), + `UNUSED_PIN (m_axi_arsize), + `UNUSED_PIN (m_axi_arburst), + `UNUSED_PIN (m_axi_arlock), + `UNUSED_PIN (m_axi_arcache), + `UNUSED_PIN (m_axi_arprot), + `UNUSED_PIN (m_axi_arqos), + `UNUSED_PIN (m_axi_arregion), + + .m_axi_rvalid (m_axi_mem_rvalid_a), + .m_axi_rready (m_axi_mem_rready_a), + .m_axi_rdata (m_axi_mem_rdata_a), + .m_axi_rlast (m_axi_mem_rlast_a), + .m_axi_rid (m_axi_mem_rid_a), + .m_axi_rresp (m_axi_mem_rresp_a), + + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data), + + .busy (vx_busy) + ); + + // SCOPE ////////////////////////////////////////////////////////////////////// + +`ifdef DBG_SCOPE_AFU +`ifdef SCOPE + `define TRIGGERS { \ + reset, \ + ap_start, \ + ap_done, \ + ap_idle, \ + interrupt, \ + vx_busy_wait, \ + vx_busy, \ + vx_running \ + } + + `define PROBES { \ + vx_pending_writes \ + } + + VX_scope_tap #( + .SCOPE_ID (0), + .TRIGGERW ($bits(`TRIGGERS)), + .PROBEW ($bits(`PROBES)) + ) scope_tap ( + .clk(clk), + .reset(scope_reset_w[0]), + .start(1'b0), + .stop(1'b0), + .triggers(`TRIGGERS), + .probes(`PROBES), + .bus_in(scope_bus_in_w[0]), + .bus_out(scope_bus_out_w[0]) + ); +`endif +`ifdef CHIPSCOPE + ila_afu ila_afu_inst ( + .clk (ap_clk), + .probe0 ({ + ap_start, + ap_done, + ap_idle, + interrupt + }), + .probe1 ({ + vx_pending_writes, + vx_busy_wait, + vx_busy, + vx_running + }) + ); +`endif +`else + `SCOPE_IO_UNUSED_W(0) +`endif + +`ifdef SIMULATION +`ifndef VERILATOR + // disable assertions until full reset + reg [`CLOG2(`RESET_DELAY+1)-1:0] assert_delay_ctr; + reg assert_enabled; + initial begin + $assertoff(0, vortex_axi); + end + always @(posedge ap_clk) begin + if (reset) begin + assert_delay_ctr <= '0; + assert_enabled <= 0; + end else begin + if (~assert_enabled) begin + if (assert_delay_ctr == (`RESET_DELAY-1)) begin + assert_enabled <= 1; + $asserton(0, vortex_axi); // enable assertions + end else begin + assert_delay_ctr <= assert_delay_ctr + 1; + end + end + end + end +`endif +`endif + +`ifdef DBG_TRACE_AFU + always @(posedge ap_clk) begin + for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin + if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin + `TRACE(2, ("%d: AFU Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i])); + end + if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin + `TRACE(2, ("%d: AFU Wr Req [%0d]: data=0x%0h\n", $time, i, m_axi_mem_wdata_a[i])); + end + if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin + `TRACE(2, ("%d: AFU Rd Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i])); + end + if (m_axi_mem_rvalid_a[i] && m_axi_mem_rready_a[i]) begin + `TRACE(2, ("%d: AVS Rd Rsp [%0d]: data=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i])); + end + end + end +`endif + +endmodule diff --git a/hw/rtl/afu/xrt/vortex_afu.v b/hw/rtl/afu/xrt/vortex_afu.v new file mode 100644 index 00000000..2c31900c --- /dev/null +++ b/hw/rtl/afu/xrt/vortex_afu.v @@ -0,0 +1,85 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "vortex_afu.vh" + +module vortex_afu #( + parameter C_S_AXI_CTRL_ADDR_WIDTH = 8, + parameter C_S_AXI_CTRL_DATA_WIDTH = 32, + parameter C_M_AXI_MEM_ID_WIDTH = `M_AXI_MEM_ID_WIDTH, + parameter C_M_AXI_MEM_ADDR_WIDTH = 64, + parameter C_M_AXI_MEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH +) ( + // System signals + input wire ap_clk, + input wire ap_rst_n, + + // AXI4 master interface + `REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA), + + // AXI4-Lite slave interface + input wire s_axi_ctrl_awvalid, + output wire s_axi_ctrl_awready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr, + input wire s_axi_ctrl_wvalid, + output wire s_axi_ctrl_wready, + input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata, + input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb, + input wire s_axi_ctrl_arvalid, + output wire s_axi_ctrl_arready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr, + output wire s_axi_ctrl_rvalid, + input wire s_axi_ctrl_rready, + output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata, + output wire [1:0] s_axi_ctrl_rresp, + output wire s_axi_ctrl_bvalid, + input wire s_axi_ctrl_bready, + output wire [1:0] s_axi_ctrl_bresp, + + output wire interrupt +); + + VX_afu_wrap #( + .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH), + .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH), + .C_M_AXI_MEM_ID_WIDTH (C_M_AXI_MEM_ID_WIDTH), + .C_M_AXI_MEM_ADDR_WIDTH (C_M_AXI_MEM_ADDR_WIDTH), + .C_M_AXI_MEM_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH) + ) afu_wrap ( + .ap_clk (ap_clk), + .ap_rst_n (ap_rst_n), + + `REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA), + + .s_axi_ctrl_awvalid (s_axi_ctrl_awvalid), + .s_axi_ctrl_awready (s_axi_ctrl_awready), + .s_axi_ctrl_awaddr (s_axi_ctrl_awaddr), + .s_axi_ctrl_wvalid (s_axi_ctrl_wvalid), + .s_axi_ctrl_wready (s_axi_ctrl_wready), + .s_axi_ctrl_wdata (s_axi_ctrl_wdata), + .s_axi_ctrl_wstrb (s_axi_ctrl_wstrb), + .s_axi_ctrl_arvalid (s_axi_ctrl_arvalid), + .s_axi_ctrl_arready (s_axi_ctrl_arready), + .s_axi_ctrl_araddr (s_axi_ctrl_araddr), + .s_axi_ctrl_rvalid (s_axi_ctrl_rvalid), + .s_axi_ctrl_rready (s_axi_ctrl_rready), + .s_axi_ctrl_rdata (s_axi_ctrl_rdata), + .s_axi_ctrl_rresp (s_axi_ctrl_rresp), + .s_axi_ctrl_bvalid (s_axi_ctrl_bvalid), + .s_axi_ctrl_bready (s_axi_ctrl_bready), + .s_axi_ctrl_bresp (s_axi_ctrl_bresp), + + .interrupt (interrupt) + ); + +endmodule diff --git a/hw/rtl/afu/xrt/vortex_afu.vh b/hw/rtl/afu/xrt/vortex_afu.vh new file mode 100644 index 00000000..3616b079 --- /dev/null +++ b/hw/rtl/afu/xrt/vortex_afu.vh @@ -0,0 +1,108 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VORTEX_AFU_VH +`define VORTEX_AFU_VH + +`ifndef M_AXI_MEM_NUM_BANKS +`define M_AXI_MEM_NUM_BANKS 1 +`endif + +`ifndef M_AXI_MEM_ID_WIDTH +`define M_AXI_MEM_ID_WIDTH 32 +`endif + +`define GEN_AXI_MEM(i) \ + output wire m_axi_mem_``i``_awvalid, \ + input wire m_axi_mem_``i``_awready, \ + output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_awaddr, \ + output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_awid, \ + output wire [7:0] m_axi_mem_``i``_awlen, \ + output wire m_axi_mem_``i``_wvalid, \ + input wire m_axi_mem_``i``_wready, \ + output wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_wdata, \ + output wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_``i``_wstrb, \ + output wire m_axi_mem_``i``_wlast, \ + output wire m_axi_mem_``i``_arvalid, \ + input wire m_axi_mem_``i``_arready, \ + output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_araddr, \ + output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_arid, \ + output wire [7:0] m_axi_mem_``i``_arlen, \ + input wire m_axi_mem_``i``_rvalid, \ + output wire m_axi_mem_``i``_rready, \ + input wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_rdata, \ + input wire m_axi_mem_``i``_rlast, \ + input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_rid, \ + input wire [1:0] m_axi_mem_``i``_rresp, \ + input wire m_axi_mem_``i``_bvalid, \ + output wire m_axi_mem_``i``_bready, \ + input wire [1:0] m_axi_mem_``i``_bresp, \ + input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_bid + +`define AXI_MEM_ARGS(i) \ + .m_axi_mem_``i``_awvalid(m_axi_mem_``i``_awvalid), \ + .m_axi_mem_``i``_awready(m_axi_mem_``i``_awready), \ + .m_axi_mem_``i``_awaddr(m_axi_mem_``i``_awaddr), \ + .m_axi_mem_``i``_awid(m_axi_mem_``i``_awid), \ + .m_axi_mem_``i``_awlen(m_axi_mem_``i``_awlen), \ + .m_axi_mem_``i``_wvalid(m_axi_mem_``i``_wvalid), \ + .m_axi_mem_``i``_wready(m_axi_mem_``i``_wready), \ + .m_axi_mem_``i``_wdata(m_axi_mem_``i``_wdata), \ + .m_axi_mem_``i``_wstrb(m_axi_mem_``i``_wstrb), \ + .m_axi_mem_``i``_wlast(m_axi_mem_``i``_wlast), \ + .m_axi_mem_``i``_arvalid(m_axi_mem_``i``_arvalid), \ + .m_axi_mem_``i``_arready(m_axi_mem_``i``_arready), \ + .m_axi_mem_``i``_araddr(m_axi_mem_``i``_araddr), \ + .m_axi_mem_``i``_arid(m_axi_mem_``i``_arid), \ + .m_axi_mem_``i``_arlen(m_axi_mem_``i``_arlen), \ + .m_axi_mem_``i``_rvalid(m_axi_mem_``i``_rvalid), \ + .m_axi_mem_``i``_rready(m_axi_mem_``i``_rready), \ + .m_axi_mem_``i``_rdata(m_axi_mem_``i``_rdata), \ + .m_axi_mem_``i``_rlast(m_axi_mem_``i``_rlast), \ + .m_axi_mem_``i``_rid(m_axi_mem_``i``_rid), \ + .m_axi_mem_``i``_rresp(m_axi_mem_``i``_rresp), \ + .m_axi_mem_``i``_bvalid(m_axi_mem_``i``_bvalid), \ + .m_axi_mem_``i``_bready(m_axi_mem_``i``_bready), \ + .m_axi_mem_``i``_bresp(m_axi_mem_``i``_bresp), \ + .m_axi_mem_``i``_bid(m_axi_mem_``i``_bid) + +`define AXI_MEM_TO_ARRAY(i) \ + assign m_axi_mem_``i``_awvalid = m_axi_mem_awvalid_a[i]; \ + assign m_axi_mem_awready_a[i] = m_axi_mem_``i``_awready; \ + assign m_axi_mem_``i``_awaddr = m_axi_mem_awaddr_a[i]; \ + assign m_axi_mem_``i``_awid = m_axi_mem_awid_a[i]; \ + assign m_axi_mem_``i``_awlen = m_axi_mem_awlen_a[i]; \ + assign m_axi_mem_``i``_wvalid = m_axi_mem_wvalid_a[i]; \ + assign m_axi_mem_wready_a[i] = m_axi_mem_``i``_wready; \ + assign m_axi_mem_``i``_wdata = m_axi_mem_wdata_a[i]; \ + assign m_axi_mem_``i``_wstrb = m_axi_mem_wstrb_a[i]; \ + assign m_axi_mem_``i``_wlast = m_axi_mem_wlast_a[i]; \ + assign m_axi_mem_``i``_arvalid = m_axi_mem_arvalid_a[i]; \ + assign m_axi_mem_arready_a[i] = m_axi_mem_``i``_arready; \ + assign m_axi_mem_``i``_araddr = m_axi_mem_araddr_a[i]; \ + assign m_axi_mem_``i``_arid = m_axi_mem_arid_a[i]; \ + assign m_axi_mem_``i``_arlen = m_axi_mem_arlen_a[i]; \ + assign m_axi_mem_rvalid_a[i] = m_axi_mem_``i``_rvalid; \ + assign m_axi_mem_``i``_rready = m_axi_mem_rready_a[i]; \ + assign m_axi_mem_rdata_a[i] = m_axi_mem_``i``_rdata; \ + assign m_axi_mem_rlast_a[i] = m_axi_mem_``i``_rlast; \ + assign m_axi_mem_rid_a[i] = m_axi_mem_``i``_rid; \ + assign m_axi_mem_rresp_a[i] = m_axi_mem_``i``_rresp; \ + assign m_axi_mem_bvalid_a[i] = m_axi_mem_``i``_bvalid; \ + assign m_axi_mem_``i``_bready = m_axi_mem_bready_a[i]; \ + assign m_axi_mem_bresp_a[i] = m_axi_mem_``i``_bresp; \ + assign m_axi_mem_bid_a[i] = m_axi_mem_``i``_bid + +`include "VX_define.vh" + +`endif // VORTEX_AFU_VH diff --git a/hw/rtl/cache/VX_bank.sv b/hw/rtl/cache/VX_bank.sv deleted file mode 100644 index 22e5887b..00000000 --- a/hw/rtl/cache/VX_bank.sv +++ /dev/null @@ -1,511 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_bank #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - - // Number of Word requests per cycle - parameter NUM_REQS = 1, - - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of bankS - parameter NUM_BANKS = 1, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - - // Core Request Queue Size - parameter CREQ_SIZE = 1, - // Core Response Queue Size - parameter CRSQ_SIZE = 1, - // Miss Reserv Queue Knob - parameter MSHR_SIZE = 1, - // Memory Request Queue Size - parameter MREQ_SIZE = 1, - - // Enable cache writeable - parameter WRITE_ENABLE = 1, - - // core request tag size - parameter CORE_TAG_WIDTH = 1, - - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0, - - parameter MSHR_ADDR_WIDTH = $clog2(MSHR_SIZE), - parameter WORD_SELECT_BITS = `UP(`WORD_SELECT_BITS) -) ( - `SCOPE_IO_VX_bank - - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE - output wire perf_read_misses, - output wire perf_write_misses, - output wire perf_mshr_stalls, -`endif - - // Core Request - input wire core_req_valid, - input wire [NUM_PORTS-1:0] core_req_pmask, - input wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] core_req_wsel, - input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] core_req_byteen, - input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_req_data, - input wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_req_tid, - input wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag, - input wire core_req_rw, - input wire [`LINE_ADDR_WIDTH-1:0] core_req_addr, - output wire core_req_ready, - - // Core Response - output wire core_rsp_valid, - output wire [NUM_PORTS-1:0] core_rsp_pmask, - output wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_rsp_tid, - output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_rsp_data, - output wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, - input wire core_rsp_ready, - - // Memory request - output wire mem_req_valid, - output wire mem_req_rw, - output wire [NUM_PORTS-1:0] mem_req_pmask, - output wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mem_req_byteen, - output wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mem_req_wsel, - output wire [`LINE_ADDR_WIDTH-1:0] mem_req_addr, - output wire [MSHR_ADDR_WIDTH-1:0] mem_req_id, - output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mem_req_data, - input wire mem_req_ready, - - // Memory response - input wire mem_rsp_valid, - input wire [MSHR_ADDR_WIDTH-1:0] mem_rsp_id, - input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data, - output wire mem_rsp_ready, - - // flush - input wire flush_enable, - input wire [`LINE_SELECT_BITS-1:0] flush_addr -); - -`IGNORE_UNUSED_BEGIN - wire [`DBG_CACHE_REQ_IDW-1:0] req_id_sel, req_id_st0, req_id_st1; -`IGNORE_UNUSED_END - - wire [NUM_PORTS-1:0] creq_pmask; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] creq_wsel; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] creq_byteen; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] creq_tid; - wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] creq_tag; - wire creq_rw; - wire [`LINE_ADDR_WIDTH-1:0] creq_addr; - - wire creq_valid, creq_ready; - - VX_elastic_buffer #( - .DATAW (1 + `LINE_ADDR_WIDTH + NUM_PORTS * (1 + WORD_SELECT_BITS + WORD_SIZE + `WORD_WIDTH + `REQS_BITS + CORE_TAG_WIDTH)), - .SIZE (CREQ_SIZE) - ) core_req_queue ( - .clk (clk), - .reset (reset), - .ready_in (core_req_ready), - .valid_in (core_req_valid), - .data_in ({core_req_rw, core_req_addr, core_req_pmask, core_req_wsel, core_req_byteen, core_req_data, core_req_tid, core_req_tag}), - .data_out ({creq_rw, creq_addr, creq_pmask, creq_wsel, creq_byteen, creq_data, creq_tid, creq_tag}), - .ready_out (creq_ready), - .valid_out (creq_valid) - ); - - wire mreq_alm_full; - wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr; - wire crsq_valid, crsq_ready; - wire crsq_stall; - - wire mshr_valid; - wire mshr_ready; - wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id; - wire mshr_alm_full; - wire [MSHR_ADDR_WIDTH-1:0] mshr_dequeue_id; - wire [`LINE_ADDR_WIDTH-1:0] mshr_addr; - wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] mshr_tag; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mshr_wsel; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] mshr_tid; - wire [NUM_PORTS-1:0] mshr_pmask; - - wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1; - wire is_read_st0, is_read_st1; - wire is_write_st0, is_write_st1; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] wsel_st0, wsel_st1; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] req_tid_st0, req_tid_st1; - wire [NUM_PORTS-1:0] pmask_st0, pmask_st1; - wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] tag_st0, tag_st1; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] rdata_st1; - wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1; - wire [MSHR_ADDR_WIDTH-1:0] mshr_id_st0, mshr_id_st1; - wire valid_st0, valid_st1; - wire is_fill_st0, is_fill_st1; - wire is_mshr_st0, is_mshr_st1; - wire miss_st0, miss_st1; - wire is_flush_st0; - wire mshr_pending_st0, mshr_pending_st1; - - // prevent read-during-write hazard when accessing tags/data block RAMs - wire rdw_fill_hazard = valid_st0 && is_fill_st0; - wire rdw_write_hazard = valid_st0 && is_write_st0 && ~creq_rw; - - // determine which queue to pop next in priority order - wire mshr_grant = !flush_enable; - wire mshr_enable = mshr_grant && mshr_valid; - - wire mrsq_grant = !flush_enable && !mshr_enable; - wire mrsq_enable = mrsq_grant && mem_rsp_valid; - wire creq_grant = !flush_enable && !mshr_enable && !mrsq_enable; - - wire creq_enable = creq_grant && creq_valid; - - assign mshr_ready = mshr_grant - && !rdw_fill_hazard // prevent read-during-write hazard - && !crsq_stall; // ensure core_rsp_queue not full - - - assign mem_rsp_ready = mrsq_grant - && !crsq_stall; // ensure core_rsp_queue not full - - assign creq_ready = creq_grant - && !rdw_write_hazard // prevent read-during-write hazard - && !mreq_alm_full // ensure mem_req_queue not full - && !mshr_alm_full // ensure mshr not full - && !crsq_stall; // ensure core_rsp_queue not full - - wire flush_fire = flush_enable; - wire mshr_fire = mshr_valid && mshr_ready; - wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; - wire creq_fire = creq_valid && creq_ready; - - assign req_id_sel = mshr_enable ? mshr_tag[0][`CACHE_REQ_ID_RNG] : creq_tag[0][`CACHE_REQ_ID_RNG]; - - wire [`CACHE_LINE_WIDTH-1:0] wdata_sel; - assign wdata_sel[(NUM_PORTS * `WORD_WIDTH)-1:0] = (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data[(NUM_PORTS * `WORD_WIDTH)-1:0] : creq_data; - for (genvar i = NUM_PORTS * `WORD_WIDTH; i < `CACHE_LINE_WIDTH; ++i) begin - assign wdata_sel[i] = mem_rsp_data[i]; - end - - VX_pipe_register #( - .DATAW (1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + NUM_PORTS * (WORD_SELECT_BITS + WORD_SIZE + `REQS_BITS + 1 + CORE_TAG_WIDTH) + MSHR_ADDR_WIDTH), - .RESETW (1) - ) pipe_reg0 ( - .clk (clk), - .reset (reset), - .enable (!crsq_stall), - .data_in ({ - flush_fire || mshr_fire || mem_rsp_fire || creq_fire, - flush_enable, - mshr_enable, - mrsq_enable, - creq_enable && ~creq_rw, - creq_enable && creq_rw, - flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : (mshr_valid ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : creq_addr)), - wdata_sel, - mshr_valid ? mshr_wsel : creq_wsel, - creq_byteen, - mshr_valid ? mshr_tid : creq_tid, - mshr_valid ? mshr_pmask : creq_pmask, - mshr_valid ? mshr_tag : creq_tag, - mshr_valid ? mshr_dequeue_id : mem_rsp_id - }), - .data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_id_st0}) - ); - - assign req_id_st0 = tag_st0[0][`CACHE_REQ_ID_RNG]; - - wire do_fill_st0 = valid_st0 && is_fill_st0; - wire do_flush_st0 = valid_st0 && is_flush_st0; - wire do_lookup_st0 = valid_st0 && ~(is_fill_st0 || is_flush_st0); - - wire tag_match_st0; - - VX_tag_access #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET) - ) tag_access ( - .clk (clk), - .reset (reset), - - .req_id (req_id_st0), - - .stall (crsq_stall), - - // read/Fill - .lookup (do_lookup_st0), - .addr (addr_st0), - .fill (do_fill_st0), - .flush (do_flush_st0), - .tag_match (tag_match_st0) - ); - - // we have a core request hit - assign miss_st0 = (is_read_st0 || is_write_st0) && ~tag_match_st0; - - wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = (is_read_st0 || is_write_st0) ? mshr_alloc_id : mshr_id_st0; - - VX_pipe_register #( - .DATAW (1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + NUM_PORTS * (WORD_SELECT_BITS + WORD_SIZE + `REQS_BITS + 1 + CORE_TAG_WIDTH) + MSHR_ADDR_WIDTH + 1), - .RESETW (1) - ) pipe_reg1 ( - .clk (clk), - .reset (reset), - .enable (!crsq_stall), - .data_in ({valid_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, miss_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_id_a_st0, mshr_pending_st0}), - .data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, miss_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1, mshr_id_st1, mshr_pending_st1}) - ); - - assign req_id_st1 = tag_st1[0][`CACHE_REQ_ID_RNG]; - - wire do_read_st0 = valid_st0 && is_read_st0; - wire do_read_st1 = valid_st1 && is_read_st1; - wire do_fill_st1 = valid_st1 && is_fill_st1; - wire do_write_st1 = valid_st1 && is_write_st1; - wire do_mshr_st1 = valid_st1 && is_mshr_st1; - - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data_st1 = wdata_st1[0 +: NUM_PORTS * `WORD_WIDTH]; - `UNUSED_VAR (wdata_st1) - - VX_data_access #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE(CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .NUM_PORTS (NUM_PORTS), - .WORD_SIZE (WORD_SIZE), - .WRITE_ENABLE (WRITE_ENABLE) - ) data_access ( - .clk (clk), - .reset (reset), - - .req_id (req_id_st1), - - .stall (crsq_stall), - - .read (do_read_st1 || do_mshr_st1), - .fill (do_fill_st1), - .write (do_write_st1 && !miss_st1), - .addr (addr_st1), - .wsel (wsel_st1), - .pmask (pmask_st1), - .byteen (byteen_st1), - .fill_data (wdata_st1), - .write_data (creq_data_st1), - .read_data (rdata_st1) - ); - - wire mshr_allocate = do_read_st0 && !crsq_stall; - wire mshr_replay = do_fill_st0 && !crsq_stall; - wire mshr_lookup = mshr_allocate; - wire mshr_release = do_read_st1 && !miss_st1 && !crsq_stall; - - VX_pending_size #( - .SIZE (MSHR_SIZE) - ) mshr_pending_size ( - .clk (clk), - .reset (reset), - .incr (creq_fire && ~creq_rw), - .decr (mshr_fire || mshr_release), - .full (mshr_alm_full), - `UNUSED_PIN (size), - `UNUSED_PIN (empty) - ); - - VX_miss_resrv #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .NUM_PORTS (NUM_PORTS), - .WORD_SIZE (WORD_SIZE), - .NUM_REQS (NUM_REQS), - .MSHR_SIZE (MSHR_SIZE), - .CORE_TAG_WIDTH (CORE_TAG_WIDTH) - ) miss_resrv ( - .clk (clk), - .reset (reset), - - .deq_req_id (req_id_sel), - .lkp_req_id (req_id_st0), - .rel_req_id (req_id_st1), - - // allocate - .allocate_valid (mshr_allocate), - .allocate_addr (addr_st0), - .allocate_data ({wsel_st0, tag_st0, req_tid_st0, pmask_st0}), - .allocate_id (mshr_alloc_id), - `UNUSED_PIN (allocate_ready), - - // lookup - .lookup_valid (mshr_lookup), - .lookup_replay (mshr_replay), - .lookup_id (mshr_alloc_id), - .lookup_addr (addr_st0), - .lookup_match (mshr_pending_st0), - - // fill - .fill_valid (mem_rsp_fire), - .fill_id (mem_rsp_id), - .fill_addr (mem_rsp_addr), - - // dequeue - .dequeue_valid (mshr_valid), - .dequeue_id (mshr_dequeue_id), - .dequeue_addr (mshr_addr), - .dequeue_data ({mshr_wsel, mshr_tag, mshr_tid, mshr_pmask}), - .dequeue_ready (mshr_ready), - - // release - .release_valid (mshr_release), - .release_id (mshr_id_st1) - ); - - // Enqueue core response - - wire [NUM_PORTS-1:0] crsq_pmask; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] crsq_data; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] crsq_tid; - wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] crsq_tag; - - assign crsq_valid = (do_read_st1 && !miss_st1) - || do_mshr_st1; - - assign crsq_stall = crsq_valid && !crsq_ready; - - assign crsq_pmask = pmask_st1; - assign crsq_tid = req_tid_st1; - assign crsq_data = rdata_st1; - assign crsq_tag = tag_st1; - - VX_elastic_buffer #( - .DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)), - .SIZE (CRSQ_SIZE), - .OUT_REG (1) - ) core_rsp_req ( - .clk (clk), - .reset (reset), - .valid_in (crsq_valid), - .data_in ({crsq_tag, crsq_pmask, crsq_data, crsq_tid}), - .ready_in (crsq_ready), - .valid_out (core_rsp_valid), - .data_out ({core_rsp_tag, core_rsp_pmask, core_rsp_data, core_rsp_tid}), - .ready_out (core_rsp_ready) - ); - - // Enqueue memory request - - wire mreq_push, mreq_pop, mreq_empty; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mreq_data; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mreq_byteen; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mreq_wsel; - wire [NUM_PORTS-1:0] mreq_pmask; - wire [`LINE_ADDR_WIDTH-1:0] mreq_addr; - wire [MSHR_ADDR_WIDTH-1:0] mreq_id; - wire mreq_rw; - - assign mreq_push = (do_read_st1 && miss_st1 && !mshr_pending_st1) - || do_write_st1; - - assign mreq_pop = mem_req_valid && mem_req_ready; - - assign mreq_rw = WRITE_ENABLE && is_write_st1; - assign mreq_addr = addr_st1; - assign mreq_id = mshr_id_st1; - assign mreq_pmask= pmask_st1; - assign mreq_wsel = wsel_st1; - assign mreq_byteen = byteen_st1; - assign mreq_data = creq_data_st1; - - VX_fifo_queue #( - .DATAW (1 + `LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_PORTS * (1 + WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)), - .SIZE (MREQ_SIZE), - .ALM_FULL (MREQ_SIZE-2), - .OUT_REG (1 == NUM_BANKS) - ) mem_req_queue ( - .clk (clk), - .reset (reset), - .push (mreq_push), - .pop (mreq_pop), - .data_in ({mreq_rw, mreq_addr, mreq_id, mreq_pmask, mreq_byteen, mreq_wsel, mreq_data}), - .data_out ({mem_req_rw, mem_req_addr, mem_req_id, mem_req_pmask, mem_req_byteen, mem_req_wsel, mem_req_data}), - .empty (mreq_empty), - .alm_full (mreq_alm_full), - `UNUSED_PIN (full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (size) - ); - - assign mem_req_valid = !mreq_empty; - -/////////////////////////////////////////////////////////////////////////////// - - `SCOPE_ASSIGN (valid_st0, valid_st0); - `SCOPE_ASSIGN (valid_st1, valid_st1); - `SCOPE_ASSIGN (is_fill_st0, is_fill_st0); - `SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0); - `SCOPE_ASSIGN (miss_st0, miss_st0); - `SCOPE_ASSIGN (crsq_stall, crsq_stall); - `SCOPE_ASSIGN (mreq_alm_full, mreq_alm_full); - `SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full); - `SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID)); - `SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); - -`ifdef PERF_ENABLE - assign perf_read_misses = do_read_st1 && miss_st1; - assign perf_write_misses = do_write_st1 && miss_st1; - assign perf_mshr_stalls = mshr_alm_full; -`endif - -`ifdef DBG_TRACE_CACHE_BANK - wire crsq_fire = crsq_valid && crsq_ready; - wire pipeline_stall = (mshr_valid || mem_rsp_valid || creq_valid) - && ~(mshr_fire || mem_rsp_fire || creq_fire); - - always @(posedge clk) begin - if (pipeline_stall) begin - dpi_trace("%d: *** cache%0d:%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, CACHE_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full); - end - if (flush_enable) begin - dpi_trace("%d: cache%0d:%0d flush: addr=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(flush_addr, BANK_ID)); - end - if (mem_rsp_fire) begin - dpi_trace("%d: cache%0d:%0d fill-rsp: addr=%0h, id=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data); - end - if (mshr_fire) begin - dpi_trace("%d: cache%0d:%0d mshr-pop: addr=%0h, tag=%0h, pmask=%b, tid=%0d (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mshr_addr, BANK_ID), mshr_tag, mshr_pmask, mshr_tid, req_id_sel); - end - if (creq_fire) begin - if (creq_rw) - dpi_trace("%d: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, pmask=%b, tid=%0d, byteen=%b, data=%0h (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, creq_byteen, creq_data, req_id_sel); - else - dpi_trace("%d: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, pmask=%b, tid=%0d (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, req_id_sel); - end - if (crsq_fire) begin - dpi_trace("%d: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, pmask=%b, tid=%0d, data=%0h (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_pmask, crsq_tid, crsq_data, req_id_st1); - end - if (mreq_push) begin - if (is_write_st1) - dpi_trace("%d: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), mreq_data, mreq_byteen, req_id_st1); - else - dpi_trace("%d: cache%0d:%0d fill-req: addr=%0h, id=%0d (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), mreq_id, req_id_st1); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache.sv b/hw/rtl/cache/VX_cache.sv index 1b7d7abf..adf4f7c8 100644 --- a/hw/rtl/cache/VX_cache.sv +++ b/hw/rtl/cache/VX_cache.sv @@ -1,102 +1,89 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_cache_define.vh" module VX_cache #( - parameter CACHE_ID = 0, + parameter `STRING INSTANCE_ID = "", // Number of Word requests per cycle - parameter NUM_REQS = 4, + parameter NUM_REQS = 4, // Size of cache in bytes - parameter CACHE_SIZE = 16384, + parameter CACHE_SIZE = 4096, // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 64, + parameter LINE_SIZE = 64, // Number of banks - parameter NUM_BANKS = NUM_REQS, - // Number of ports per banks - parameter NUM_PORTS = 1, + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, // Size of a word in bytes - parameter WORD_SIZE = 4, + parameter WORD_SIZE = `XLEN/8, - // Core Request Queue Size - parameter CREQ_SIZE = 0, // Core Response Queue Size - parameter CRSQ_SIZE = 2, + parameter CRSQ_SIZE = 2, // Miss Reserv Queue Knob - parameter MSHR_SIZE = 8, + parameter MSHR_SIZE = 8, // Memory Response Queue Size - parameter MRSQ_SIZE = 0, + parameter MRSQ_SIZE = 0, // Memory Request Queue Size - parameter MREQ_SIZE = 4, + parameter MREQ_SIZE = 4, // Enable cache writeable - parameter WRITE_ENABLE = 1, + parameter WRITE_ENABLE = 1, + + // Request debug identifier + parameter UUID_WIDTH = 0, // core request tag size - parameter CORE_TAG_WIDTH = $clog2(MSHR_SIZE), - - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = CORE_TAG_WIDTH, + parameter TAG_WIDTH = UUID_WIDTH + 1, - // Memory request tag size - parameter MEM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)), + // Core response output register + parameter CORE_OUT_REG = 0, - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0, - - // enable bypass for non-cacheable addresses - parameter NC_ENABLE = 0, - - parameter WORD_SELECT_BITS = `UP(`WORD_SELECT_BITS) - ) ( - `SCOPE_IO_VX_cache - + // Memory request output register + parameter MEM_OUT_REG = 0 + ) ( // PERF `ifdef PERF_ENABLE - VX_perf_cache_if.master perf_cache_if, + VX_cache_perf_if.master cache_perf_if, `endif input wire clk, input wire reset, - // Core request - input wire [NUM_REQS-1:0] core_req_valid, - input wire [NUM_REQS-1:0] core_req_rw, - input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr, - input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen, - input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data, - input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag, - output wire [NUM_REQS-1:0] core_req_ready, - - // Core response - output wire [`CORE_RSP_TAGS-1:0] core_rsp_valid, - output wire [NUM_REQS-1:0] core_rsp_tmask, - output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data, - output wire [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, - input wire [`CORE_RSP_TAGS-1:0] core_rsp_ready, - - // Memory request - output wire mem_req_valid, - output wire mem_req_rw, - output wire [CACHE_LINE_SIZE-1:0] mem_req_byteen, - output wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr, - output wire [`CACHE_LINE_WIDTH-1:0] mem_req_data, - output wire [MEM_TAG_WIDTH-1:0] mem_req_tag, - input wire mem_req_ready, - - // Memory response - input wire mem_rsp_valid, - input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data, - input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag, - output wire mem_rsp_ready + VX_mem_bus_if.slave core_bus_if [NUM_REQS], + VX_mem_bus_if.master mem_bus_if ); - `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) - `STATIC_ASSERT(NUM_PORTS <= NUM_BANKS, ("invalid value")) + `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter")) + `STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter")) - localparam MSHR_ADDR_WIDTH = $clog2(MSHR_SIZE); - localparam MEM_TAG_IN_WIDTH = `BANK_SELECT_BITS + MSHR_ADDR_WIDTH; - localparam CORE_TAG_X_WIDTH = CORE_TAG_WIDTH - NC_ENABLE; - localparam CORE_TAG_ID_X_BITS = (CORE_TAG_ID_BITS != 0) ? (CORE_TAG_ID_BITS - NC_ENABLE) : CORE_TAG_ID_BITS; + localparam REQ_SEL_WIDTH = `UP(`CS_REQ_SEL_BITS); + localparam WORD_SEL_WIDTH = `UP(`CS_WORD_SEL_BITS); + localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE); + localparam MEM_TAG_WIDTH = MSHR_ADDR_WIDTH + `CS_BANK_SEL_BITS; + localparam WORDS_PER_LINE = LINE_SIZE / WORD_SIZE; + localparam WORD_WIDTH = WORD_SIZE * 8; + localparam WORD_SEL_BITS = `CLOG2(WORDS_PER_LINE); + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam LINE_ADDR_WIDTH = (`CS_WORD_ADDR_WIDTH - BANK_SEL_BITS - WORD_SEL_BITS); + localparam CORE_REQ_DATAW = LINE_ADDR_WIDTH + 1 + WORD_SEL_WIDTH + WORD_SIZE + WORD_WIDTH + TAG_WIDTH; + localparam CORE_RSP_DATAW = WORD_WIDTH + TAG_WIDTH; + + localparam CORE_REQ_BUF_ENABLE = (NUM_BANKS != 1) || (NUM_REQS != 1); + localparam MEM_REQ_BUF_ENABLE = (NUM_BANKS != 1); `ifdef PERF_ENABLE wire [NUM_BANKS-1:0] perf_read_miss_per_bank; @@ -104,486 +91,260 @@ module VX_cache #( wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank; `endif + wire [NUM_REQS-1:0] core_req_valid; + wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr; + wire [NUM_REQS-1:0] core_req_rw; + wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data; + wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_req_tag; + wire [NUM_REQS-1:0] core_req_ready; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_req_valid[i] = core_bus_if[i].req_valid; + assign core_req_addr[i] = core_bus_if[i].req_data.addr; + assign core_req_rw[i] = core_bus_if[i].req_data.rw; + assign core_req_byteen[i] = core_bus_if[i].req_data.byteen; + assign core_req_data[i] = core_bus_if[i].req_data.data; + assign core_req_tag[i] = core_bus_if[i].req_data.tag; + assign core_bus_if[i].req_ready = core_req_ready[i]; + end + /////////////////////////////////////////////////////////////////////////// - wire mem_req_valid_sb; - wire mem_req_rw_sb; - wire [CACHE_LINE_SIZE-1:0] mem_req_byteen_sb; - wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr_sb; - wire [`CACHE_LINE_WIDTH-1:0] mem_req_data_sb; - wire [MEM_TAG_WIDTH-1:0] mem_req_tag_sb; - wire mem_req_ready_sb; + // Core response buffering + wire [NUM_REQS-1:0] core_rsp_valid_s; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_s; + wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s; + wire [NUM_REQS-1:0] core_rsp_ready_s; - VX_skid_buffer #( - .DATAW (1+CACHE_LINE_SIZE+`MEM_ADDR_WIDTH+`CACHE_LINE_WIDTH+MEM_TAG_WIDTH), - .PASSTHRU (1 == NUM_BANKS) - ) mem_req_sbuf ( + for (genvar i = 0; i < NUM_REQS; ++i) begin + + `RESET_RELAY (core_rsp_reset, reset); + + VX_elastic_buffer #( + .DATAW (`CS_WORD_WIDTH + TAG_WIDTH), + .SIZE (CORE_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0), + .OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG)) + ) core_rsp_buf ( + .clk (clk), + .reset (core_rsp_reset), + .valid_in (core_rsp_valid_s[i]), + .ready_in (core_rsp_ready_s[i]), + .data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}), + .data_out ({core_bus_if[i].rsp_data.data, core_bus_if[i].rsp_data.tag}), + .valid_out (core_bus_if[i].rsp_valid), + .ready_out (core_bus_if[i].rsp_ready) + ); + end + + /////////////////////////////////////////////////////////////////////////// + + // Memory request buffering + wire mem_req_valid_s; + wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_s; + wire mem_req_rw_s; + wire [LINE_SIZE-1:0] mem_req_byteen_s; + wire [`CS_LINE_WIDTH-1:0] mem_req_data_s; + wire [MEM_TAG_WIDTH-1:0] mem_req_tag_s; + wire mem_req_ready_s; + + `RESET_RELAY (mem_req_buf_reset, reset); + + VX_elastic_buffer #( + .DATAW (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH), + .SIZE (MEM_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0), + .OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG)) + ) mem_req_buf ( .clk (clk), - .reset (reset), - .valid_in (mem_req_valid_sb), - .ready_in (mem_req_ready_sb), - .data_in ({mem_req_rw_sb, mem_req_byteen_sb, mem_req_addr_sb, mem_req_data_sb, mem_req_tag_sb}), - .data_out ({mem_req_rw, mem_req_byteen, mem_req_addr, mem_req_data, mem_req_tag}), - .valid_out (mem_req_valid), - .ready_out (mem_req_ready) + .reset (mem_req_buf_reset), + .valid_in (mem_req_valid_s), + .ready_in (mem_req_ready_s), + .data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}), + .data_out ({mem_bus_if.req_data.rw, mem_bus_if.req_data.byteen, mem_bus_if.req_data.addr, mem_bus_if.req_data.data, mem_bus_if.req_data.tag}), + .valid_out (mem_bus_if.req_valid), + .ready_out (mem_bus_if.req_ready) ); /////////////////////////////////////////////////////////////////////////// - wire [`CORE_RSP_TAGS-1:0] core_rsp_valid_sb; - wire [NUM_REQS-1:0] core_rsp_tmask_sb; - wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_sb; - wire [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_sb; - wire [`CORE_RSP_TAGS-1:0] core_rsp_ready_sb; + // Memory response buffering + wire mem_rsp_valid_s; + wire [`CS_LINE_WIDTH-1:0] mem_rsp_data_s; + wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_s; + wire mem_rsp_ready_s; - if (CORE_TAG_ID_BITS != 0) begin - VX_skid_buffer #( - .DATAW (NUM_REQS + NUM_REQS*`WORD_WIDTH + CORE_TAG_WIDTH), - .PASSTHRU (1 == NUM_BANKS) - ) core_rsp_sbuf ( - .clk (clk), - .reset (reset), - .valid_in (core_rsp_valid_sb), - .ready_in (core_rsp_ready_sb), - .data_in ({core_rsp_tmask_sb, core_rsp_data_sb, core_rsp_tag_sb}), - .data_out ({core_rsp_tmask, core_rsp_data, core_rsp_tag}), - .valid_out (core_rsp_valid), - .ready_out (core_rsp_ready) - ); - end else begin - for (genvar i = 0; i < NUM_REQS; i++) begin - VX_skid_buffer #( - .DATAW (1 + `WORD_WIDTH + CORE_TAG_WIDTH), - .PASSTHRU (1 == NUM_BANKS) - ) core_rsp_sbuf ( - .clk (clk), - .reset (reset), - .valid_in (core_rsp_valid_sb[i]), - .ready_in (core_rsp_ready_sb[i]), - .data_in ({core_rsp_tmask_sb[i], core_rsp_data_sb[i], core_rsp_tag_sb[i]}), - .data_out ({core_rsp_tmask[i], core_rsp_data[i], core_rsp_tag[i]}), - .valid_out (core_rsp_valid[i]), - .ready_out (core_rsp_ready[i]) - ); - end - end - - - /////////////////////////////////////////////////////////////////////////// - - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mem_req_byteen_p; - wire [NUM_PORTS-1:0] mem_req_pmask_p; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mem_req_wsel_p; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mem_req_data_p; - wire mem_req_rw_p; - - if (WRITE_ENABLE) begin - if (`WORDS_PER_LINE > 1) begin - reg [CACHE_LINE_SIZE-1:0] mem_req_byteen_r; - reg [`CACHE_LINE_WIDTH-1:0] mem_req_data_r; - - always @(*) begin - mem_req_byteen_r = 0; - mem_req_data_r = 'x; - for (integer i = 0; i < NUM_PORTS; ++i) begin - if ((1 == NUM_PORTS) || mem_req_pmask_p[i]) begin - mem_req_byteen_r[mem_req_wsel_p[i] * WORD_SIZE +: WORD_SIZE] = mem_req_byteen_p[i]; - mem_req_data_r[mem_req_wsel_p[i] * `WORD_WIDTH +: `WORD_WIDTH] = mem_req_data_p[i]; - end - end - end - - assign mem_req_rw_sb = mem_req_rw_p; - assign mem_req_byteen_sb = mem_req_byteen_r; - assign mem_req_data_sb = mem_req_data_r; - end else begin - `UNUSED_VAR (mem_req_pmask_p) - `UNUSED_VAR (mem_req_wsel_p) - assign mem_req_rw_sb = mem_req_rw_p; - assign mem_req_byteen_sb = mem_req_byteen_p; - assign mem_req_data_sb = mem_req_data_p; - end - end else begin - `UNUSED_VAR (mem_req_byteen_p) - `UNUSED_VAR (mem_req_pmask_p) - `UNUSED_VAR (mem_req_wsel_p) - `UNUSED_VAR (mem_req_data_p) - `UNUSED_VAR (mem_req_rw_p) + `RESET_RELAY (mem_rsp_reset, reset); - assign mem_req_rw_sb = 0; - assign mem_req_byteen_sb = 'x; - assign mem_req_data_sb = 'x; - end - - /////////////////////////////////////////////////////////////////////////// - - // Core request - wire [NUM_REQS-1:0] core_req_valid_c; - wire [NUM_REQS-1:0] core_req_rw_c; - wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr_c; - wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen_c; - wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data_c; - wire [NUM_REQS-1:0][CORE_TAG_X_WIDTH-1:0] core_req_tag_c; - wire [NUM_REQS-1:0] core_req_ready_c; - - // Core response - wire [`CORE_RSP_TAGS-1:0] core_rsp_valid_c; - wire [NUM_REQS-1:0] core_rsp_tmask_c; - wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_c; - wire [`CORE_RSP_TAGS-1:0][CORE_TAG_X_WIDTH-1:0] core_rsp_tag_c; - wire [`CORE_RSP_TAGS-1:0] core_rsp_ready_c; - - // Memory request - wire mem_req_valid_c; - wire mem_req_rw_c; - wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr_c; - wire [NUM_PORTS-1:0] mem_req_pmask_c; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mem_req_byteen_c; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] mem_req_wsel_c; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] mem_req_data_c; - wire [MEM_TAG_IN_WIDTH-1:0] mem_req_tag_c; - wire mem_req_ready_c; - - // Memory response - wire mem_rsp_valid_c; - wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_c; - wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_c; - wire mem_rsp_ready_c; - - if (NC_ENABLE) begin - VX_nc_bypass #( - .NUM_PORTS (NUM_PORTS), - .NUM_REQS (NUM_REQS), - .NUM_RSP_TAGS (`CORE_RSP_TAGS), - .NC_TAG_BIT (0), - - .CORE_ADDR_WIDTH (`WORD_ADDR_WIDTH), - .CORE_DATA_SIZE (WORD_SIZE), - .CORE_TAG_IN_WIDTH (CORE_TAG_WIDTH), - - .MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH), - .MEM_DATA_SIZE (CACHE_LINE_SIZE), - .MEM_TAG_IN_WIDTH (MEM_TAG_IN_WIDTH), - .MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH) - ) nc_bypass ( - .clk (clk), - .reset (reset), - - // Core request in - .core_req_valid_in (core_req_valid), - .core_req_rw_in (core_req_rw), - .core_req_byteen_in (core_req_byteen), - .core_req_addr_in (core_req_addr), - .core_req_data_in (core_req_data), - .core_req_tag_in (core_req_tag), - .core_req_ready_in (core_req_ready), - - // Core request out - .core_req_valid_out (core_req_valid_c), - .core_req_rw_out (core_req_rw_c), - .core_req_byteen_out(core_req_byteen_c), - .core_req_addr_out (core_req_addr_c), - .core_req_data_out (core_req_data_c), - .core_req_tag_out (core_req_tag_c), - .core_req_ready_out (core_req_ready_c), - - // Core response in - .core_rsp_valid_in (core_rsp_valid_c), - .core_rsp_tmask_in (core_rsp_tmask_c), - .core_rsp_data_in (core_rsp_data_c), - .core_rsp_tag_in (core_rsp_tag_c), - .core_rsp_ready_in (core_rsp_ready_c), - - // Core response out - .core_rsp_valid_out (core_rsp_valid_sb), - .core_rsp_tmask_out (core_rsp_tmask_sb), - .core_rsp_data_out (core_rsp_data_sb), - .core_rsp_tag_out (core_rsp_tag_sb), - .core_rsp_ready_out (core_rsp_ready_sb), - - // Memory request in - .mem_req_valid_in (mem_req_valid_c), - .mem_req_rw_in (mem_req_rw_c), - .mem_req_addr_in (mem_req_addr_c), - .mem_req_pmask_in (mem_req_pmask_c), - .mem_req_byteen_in (mem_req_byteen_c), - .mem_req_wsel_in (mem_req_wsel_c), - .mem_req_data_in (mem_req_data_c), - .mem_req_tag_in (mem_req_tag_c), - .mem_req_ready_in (mem_req_ready_c), - - // Memory request out - .mem_req_valid_out (mem_req_valid_sb), - .mem_req_addr_out (mem_req_addr_sb), - .mem_req_rw_out (mem_req_rw_p), - .mem_req_pmask_out (mem_req_pmask_p), - .mem_req_byteen_out (mem_req_byteen_p), - .mem_req_wsel_out (mem_req_wsel_p), - .mem_req_data_out (mem_req_data_p), - .mem_req_tag_out (mem_req_tag_sb), - .mem_req_ready_out (mem_req_ready_sb), - - // Memory response in - .mem_rsp_valid_in (mem_rsp_valid), - .mem_rsp_data_in (mem_rsp_data), - .mem_rsp_tag_in (mem_rsp_tag), - .mem_rsp_ready_in (mem_rsp_ready), - - // Memory response out - .mem_rsp_valid_out (mem_rsp_valid_c), - .mem_rsp_data_out (mem_rsp_data_c), - .mem_rsp_tag_out (mem_rsp_tag_c), - .mem_rsp_ready_out (mem_rsp_ready_c) - ); - end else begin - assign core_req_valid_c = core_req_valid; - assign core_req_rw_c = core_req_rw; - assign core_req_addr_c = core_req_addr; - assign core_req_byteen_c = core_req_byteen; - assign core_req_data_c = core_req_data; - assign core_req_tag_c = core_req_tag; - assign core_req_ready = core_req_ready_c; - - assign core_rsp_valid_sb = core_rsp_valid_c; - assign core_rsp_tmask_sb = core_rsp_tmask_c; - assign core_rsp_data_sb = core_rsp_data_c; - assign core_rsp_tag_sb = core_rsp_tag_c; - assign core_rsp_ready_c = core_rsp_ready_sb; - - assign mem_req_valid_sb = mem_req_valid_c; - assign mem_req_addr_sb = mem_req_addr_c; - assign mem_req_rw_p = mem_req_rw_c; - assign mem_req_pmask_p = mem_req_pmask_c; - assign mem_req_byteen_p = mem_req_byteen_c; - assign mem_req_wsel_p = mem_req_wsel_c; - assign mem_req_data_p = mem_req_data_c; - assign mem_req_tag_sb = mem_req_tag_c; - assign mem_req_ready_c = mem_req_ready_sb; - - assign mem_rsp_valid_c = mem_rsp_valid; - assign mem_rsp_data_c = mem_rsp_data; - assign mem_rsp_tag_c = mem_rsp_tag; - assign mem_rsp_ready = mem_rsp_ready_c; - end - - /////////////////////////////////////////////////////////////////////////// - - wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_qual; - wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_qual; - - wire mrsq_out_valid, mrsq_out_ready; - - `RESET_RELAY (mrsq_reset); - VX_elastic_buffer #( - .DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH), + .DATAW (MEM_TAG_WIDTH + `CS_LINE_WIDTH), .SIZE (MRSQ_SIZE), .OUT_REG (MRSQ_SIZE > 2) ) mem_rsp_queue ( .clk (clk), - .reset (mrsq_reset), - .ready_in (mem_rsp_ready_c), - .valid_in (mem_rsp_valid_c), - .data_in ({mem_rsp_tag_c, mem_rsp_data_c}), - .data_out ({mem_rsp_tag_qual, mem_rsp_data_qual}), - .ready_out (mrsq_out_ready), - .valid_out (mrsq_out_valid) + .reset (mem_rsp_reset), + .valid_in (mem_bus_if.rsp_valid), + .ready_in (mem_bus_if.rsp_ready), + .data_in ({mem_bus_if.rsp_data.tag, mem_bus_if.rsp_data.data}), + .data_out ({mem_rsp_tag_s, mem_rsp_data_s}), + .valid_out (mem_rsp_valid_s), + .ready_out (mem_rsp_ready_s) ); - `UNUSED_VAR (mem_rsp_tag_c) + /////////////////////////////////////////////////////////////////////// - /////////////////////////////////////////////////////////////////////////// + wire [`CS_LINE_SEL_BITS-1:0] init_line_sel; + wire init_enable; - wire [`LINE_SELECT_BITS-1:0] flush_addr; - wire flush_enable; + `RESET_RELAY (init_reset, reset); - `RESET_RELAY (flush_reset); - - VX_flush_ctrl #( + VX_cache_init #( .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS) - ) flush_ctrl ( + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS) + ) cache_init ( .clk (clk), - .reset (flush_reset), - .addr_out (flush_addr), - .valid_out (flush_enable) + .reset (init_reset), + .addr_out (init_line_sel), + .valid_out (init_enable) ); - /////////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////// wire [NUM_BANKS-1:0] per_bank_core_req_valid; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] per_bank_core_req_wsel; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] per_bank_core_req_tag; - wire [NUM_BANKS-1:0] per_bank_core_req_rw; - wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr; + wire [NUM_BANKS-1:0][`CS_LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr; + wire [NUM_BANKS-1:0] per_bank_core_req_rw; + wire [NUM_BANKS-1:0][WORD_SEL_WIDTH-1:0] per_bank_core_req_wsel; + wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen; + wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_core_req_data; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_core_req_tag; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_core_req_idx; wire [NUM_BANKS-1:0] per_bank_core_req_ready; wire [NUM_BANKS-1:0] per_bank_core_rsp_valid; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_pmask; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] per_bank_core_rsp_tag; + wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_core_rsp_data; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_core_rsp_tag; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_core_rsp_idx; wire [NUM_BANKS-1:0] per_bank_core_rsp_ready; wire [NUM_BANKS-1:0] per_bank_mem_req_valid; + wire [NUM_BANKS-1:0][`CS_MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr; wire [NUM_BANKS-1:0] per_bank_mem_req_rw; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_mem_req_pmask; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_mem_req_byteen; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] per_bank_mem_req_wsel; - wire [NUM_BANKS-1:0][`MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr; + wire [NUM_BANKS-1:0][WORD_SEL_WIDTH-1:0] per_bank_mem_req_wsel; + wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_mem_req_byteen; + wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_mem_req_data; wire [NUM_BANKS-1:0][MSHR_ADDR_WIDTH-1:0] per_bank_mem_req_id; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_mem_req_data; wire [NUM_BANKS-1:0] per_bank_mem_req_ready; wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready; if (NUM_BANKS == 1) begin - assign mrsq_out_ready = per_bank_mem_rsp_ready; + assign mem_rsp_ready_s = per_bank_mem_rsp_ready; end else begin - assign mrsq_out_ready = per_bank_mem_rsp_ready[`MEM_TAG_TO_BANK_ID(mem_rsp_tag_qual)]; + assign mem_rsp_ready_s = per_bank_mem_rsp_ready[`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s)]; end - VX_core_req_bank_sel #( - .CACHE_ID (CACHE_ID), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .NUM_PORTS (NUM_PORTS), - .WORD_SIZE (WORD_SIZE), - .NUM_REQS (NUM_REQS), - .CORE_TAG_WIDTH (CORE_TAG_X_WIDTH), - .BANK_ADDR_OFFSET(BANK_ADDR_OFFSET) - ) core_req_bank_sel ( - .clk (clk), - .reset (reset), - `ifdef PERF_ENABLE - .bank_stalls(perf_cache_if.bank_stalls), - `endif - .core_req_valid (core_req_valid_c), - .core_req_rw (core_req_rw_c), - .core_req_addr (core_req_addr_c), - .core_req_byteen (core_req_byteen_c), - .core_req_data (core_req_data_c), - .core_req_tag (core_req_tag_c), - .core_req_ready (core_req_ready_c), - .per_bank_core_req_valid (per_bank_core_req_valid), - .per_bank_core_req_pmask (per_bank_core_req_pmask), - .per_bank_core_req_rw (per_bank_core_req_rw), - .per_bank_core_req_addr (per_bank_core_req_addr), - .per_bank_core_req_wsel (per_bank_core_req_wsel), - .per_bank_core_req_byteen(per_bank_core_req_byteen), - .per_bank_core_req_data (per_bank_core_req_data), - .per_bank_core_req_tag (per_bank_core_req_tag), - .per_bank_core_req_tid (per_bank_core_req_tid), - .per_bank_core_req_ready (per_bank_core_req_ready) + // Bank requests dispatch + + wire [NUM_REQS-1:0][CORE_REQ_DATAW-1:0] core_req_data_in; + wire [NUM_BANKS-1:0][CORE_REQ_DATAW-1:0] core_req_data_out; + wire [NUM_REQS-1:0][LINE_ADDR_WIDTH-1:0] core_req_line_addr; + wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] core_req_bid; + wire [NUM_REQS-1:0][WORD_SEL_WIDTH-1:0] core_req_wsel; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + if (WORDS_PER_LINE > 1) begin + assign core_req_wsel[i] = core_req_addr[i][0 +: WORD_SEL_BITS]; + end else begin + assign core_req_wsel[i] = '0; + end + assign core_req_line_addr[i] = core_req_addr[i][(BANK_SEL_BITS + WORD_SEL_BITS) +: LINE_ADDR_WIDTH]; + end + + if (NUM_BANKS > 1) begin + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS]; + end + end else begin + assign core_req_bid = '0; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_req_data_in[i] = { + core_req_line_addr[i], + core_req_rw[i], + core_req_wsel[i], + core_req_byteen[i], + core_req_data[i], + core_req_tag[i]}; + end + + `RESET_RELAY (req_xbar_reset, reset); + + VX_stream_xbar #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS (NUM_BANKS), + .DATAW (CORE_REQ_DATAW), + .PERF_CTR_BITS (`PERF_CTR_BITS) + ) req_xbar ( + .clk (clk), + .reset (req_xbar_reset), + `ifdef PERF_ENABLE + .collisions (cache_perf_if.bank_stalls), + `else + `UNUSED_PIN (collisions), + `endif + .valid_in (core_req_valid), + .data_in (core_req_data_in), + .sel_in (core_req_bid), + .ready_in (core_req_ready), + .valid_out (per_bank_core_req_valid), + .data_out (core_req_data_out), + .sel_out (per_bank_core_req_idx), + .ready_out (per_bank_core_req_ready) ); - /////////////////////////////////////////////////////////////////////////// + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign { + per_bank_core_req_addr[i], + per_bank_core_req_rw[i], + per_bank_core_req_wsel[i], + per_bank_core_req_byteen[i], + per_bank_core_req_data[i], + per_bank_core_req_tag[i]} = core_req_data_out[i]; + end - for (genvar i = 0; i < NUM_BANKS; i++) begin - wire curr_bank_core_req_valid; - wire [NUM_PORTS-1:0] curr_bank_core_req_pmask; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] curr_bank_core_req_wsel; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] curr_bank_core_req_tid; - wire [NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] curr_bank_core_req_tag; - wire curr_bank_core_req_rw; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_core_req_addr; - wire curr_bank_core_req_ready; + // Banks access + for (genvar i = 0; i < NUM_BANKS; ++i) begin + wire [`CS_LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr; + wire curr_bank_mem_rsp_valid; - wire curr_bank_core_rsp_valid; - wire [NUM_PORTS-1:0] curr_bank_core_rsp_pmask; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_rsp_data; - wire [NUM_PORTS-1:0][`REQS_BITS-1:0] curr_bank_core_rsp_tid; - wire [NUM_PORTS-1:0][CORE_TAG_X_WIDTH-1:0] curr_bank_core_rsp_tag; - wire curr_bank_core_rsp_ready; - - wire curr_bank_mem_req_valid; - wire curr_bank_mem_req_rw; - wire [NUM_PORTS-1:0] curr_bank_mem_req_pmask; - wire [NUM_PORTS-1:0][WORD_SIZE-1:0] curr_bank_mem_req_byteen; - wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] curr_bank_mem_req_wsel; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr; - wire [MSHR_ADDR_WIDTH-1:0] curr_bank_mem_req_id; - wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_mem_req_data; - wire curr_bank_mem_req_ready; - - wire curr_bank_mem_rsp_valid; - wire [MSHR_ADDR_WIDTH-1:0] curr_bank_mem_rsp_id; - wire [`CACHE_LINE_WIDTH-1:0] curr_bank_mem_rsp_data; - wire curr_bank_mem_rsp_ready; - - // Core Req - assign curr_bank_core_req_valid = per_bank_core_req_valid[i]; - assign curr_bank_core_req_pmask = per_bank_core_req_pmask[i]; - assign curr_bank_core_req_addr = per_bank_core_req_addr[i]; - assign curr_bank_core_req_rw = per_bank_core_req_rw[i]; - assign curr_bank_core_req_wsel = per_bank_core_req_wsel[i]; - assign curr_bank_core_req_byteen = per_bank_core_req_byteen[i]; - assign curr_bank_core_req_data = per_bank_core_req_data[i]; - assign curr_bank_core_req_tag = per_bank_core_req_tag[i]; - assign curr_bank_core_req_tid = per_bank_core_req_tid[i]; - assign per_bank_core_req_ready[i] = curr_bank_core_req_ready; - - // Core WB - assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i]; - assign per_bank_core_rsp_valid[i] = curr_bank_core_rsp_valid; - assign per_bank_core_rsp_pmask[i] = curr_bank_core_rsp_pmask; - assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid; - assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag; - assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; - - // Memory request - assign per_bank_mem_req_valid[i] = curr_bank_mem_req_valid; - assign per_bank_mem_req_rw[i] = curr_bank_mem_req_rw; - assign per_bank_mem_req_pmask[i] = curr_bank_mem_req_pmask; - assign per_bank_mem_req_byteen[i] = curr_bank_mem_req_byteen; - assign per_bank_mem_req_wsel[i] = curr_bank_mem_req_wsel; - if (NUM_BANKS == 1) begin - assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr; - end else begin - assign per_bank_mem_req_addr[i] = `LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i); - end - assign per_bank_mem_req_id[i] = curr_bank_mem_req_id; - assign per_bank_mem_req_data[i] = curr_bank_mem_req_data; - assign curr_bank_mem_req_ready = per_bank_mem_req_ready[i]; - - // Memory response if (NUM_BANKS == 1) begin - assign curr_bank_mem_rsp_valid = mrsq_out_valid; + assign curr_bank_mem_rsp_valid = mem_rsp_valid_s; end else begin - assign curr_bank_mem_rsp_valid = mrsq_out_valid && (`MEM_TAG_TO_BANK_ID(mem_rsp_tag_qual) == i); + assign curr_bank_mem_rsp_valid = mem_rsp_valid_s && (`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s) == i); end - assign curr_bank_mem_rsp_id = `MEM_TAG_TO_REQ_ID(mem_rsp_tag_qual); - assign curr_bank_mem_rsp_data = mem_rsp_data_qual; - assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready; - `RESET_RELAY (bank_reset); + `RESET_RELAY (bank_reset, reset); - VX_bank #( - .BANK_ID (i), - .CACHE_ID (CACHE_ID), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .NUM_PORTS (NUM_PORTS), - .WORD_SIZE (WORD_SIZE), - .NUM_REQS (NUM_REQS), - .CREQ_SIZE (CREQ_SIZE), - .CRSQ_SIZE (CRSQ_SIZE), - .MSHR_SIZE (MSHR_SIZE), - .MREQ_SIZE (MREQ_SIZE), - .WRITE_ENABLE (WRITE_ENABLE), - .CORE_TAG_WIDTH (CORE_TAG_X_WIDTH), - .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET) - ) bank ( - `SCOPE_BIND_VX_cache_bank(i) - + VX_cache_bank #( + .BANK_ID (i), + .INSTANCE_ID (INSTANCE_ID), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .WRITE_ENABLE (WRITE_ENABLE), + .UUID_WIDTH (UUID_WIDTH), + .TAG_WIDTH (TAG_WIDTH), + .CORE_OUT_REG (CORE_REQ_BUF_ENABLE ? 0 : CORE_OUT_REG), + .MEM_OUT_REG (MEM_REQ_BUF_ENABLE ? 0 : MEM_OUT_REG) + ) bank ( .clk (clk), .reset (bank_reset), @@ -592,134 +353,202 @@ module VX_cache #( .perf_write_misses (perf_write_miss_per_bank[i]), .perf_mshr_stalls (perf_mshr_stall_per_bank[i]), `endif - + // Core request - .core_req_valid (curr_bank_core_req_valid), - .core_req_pmask (curr_bank_core_req_pmask), - .core_req_rw (curr_bank_core_req_rw), - .core_req_byteen (curr_bank_core_req_byteen), - .core_req_addr (curr_bank_core_req_addr), - .core_req_wsel (curr_bank_core_req_wsel), - .core_req_data (curr_bank_core_req_data), - .core_req_tag (curr_bank_core_req_tag), - .core_req_tid (curr_bank_core_req_tid), - .core_req_ready (curr_bank_core_req_ready), + .core_req_valid (per_bank_core_req_valid[i]), + .core_req_addr (per_bank_core_req_addr[i]), + .core_req_rw (per_bank_core_req_rw[i]), + .core_req_wsel (per_bank_core_req_wsel[i]), + .core_req_byteen (per_bank_core_req_byteen[i]), + .core_req_data (per_bank_core_req_data[i]), + .core_req_tag (per_bank_core_req_tag[i]), + .core_req_idx (per_bank_core_req_idx[i]), + .core_req_ready (per_bank_core_req_ready[i]), // Core response - .core_rsp_valid (curr_bank_core_rsp_valid), - .core_rsp_pmask (curr_bank_core_rsp_pmask), - .core_rsp_tid (curr_bank_core_rsp_tid), - .core_rsp_data (curr_bank_core_rsp_data), - .core_rsp_tag (curr_bank_core_rsp_tag), - .core_rsp_ready (curr_bank_core_rsp_ready), + .core_rsp_valid (per_bank_core_rsp_valid[i]), + .core_rsp_data (per_bank_core_rsp_data[i]), + .core_rsp_tag (per_bank_core_rsp_tag[i]), + .core_rsp_idx (per_bank_core_rsp_idx[i]), + .core_rsp_ready (per_bank_core_rsp_ready[i]), // Memory request - .mem_req_valid (curr_bank_mem_req_valid), - .mem_req_rw (curr_bank_mem_req_rw), - .mem_req_pmask (curr_bank_mem_req_pmask), - .mem_req_byteen (curr_bank_mem_req_byteen), - .mem_req_wsel (curr_bank_mem_req_wsel), + .mem_req_valid (per_bank_mem_req_valid[i]), .mem_req_addr (curr_bank_mem_req_addr), - .mem_req_id (curr_bank_mem_req_id), - .mem_req_data (curr_bank_mem_req_data), - .mem_req_ready (curr_bank_mem_req_ready), + .mem_req_rw (per_bank_mem_req_rw[i]), + .mem_req_wsel (per_bank_mem_req_wsel[i]), + .mem_req_byteen (per_bank_mem_req_byteen[i]), + .mem_req_data (per_bank_mem_req_data[i]), + .mem_req_id (per_bank_mem_req_id[i]), + .mem_req_ready (per_bank_mem_req_ready[i]), // Memory response - .mem_rsp_valid (curr_bank_mem_rsp_valid), - .mem_rsp_id (curr_bank_mem_rsp_id), - .mem_rsp_data (curr_bank_mem_rsp_data), - .mem_rsp_ready (curr_bank_mem_rsp_ready), + .mem_rsp_valid (curr_bank_mem_rsp_valid), + .mem_rsp_data (mem_rsp_data_s), + .mem_rsp_id (`CS_MEM_TAG_TO_REQ_ID(mem_rsp_tag_s)), + .mem_rsp_ready (per_bank_mem_rsp_ready[i]), - // flush - .flush_enable (flush_enable), - .flush_addr (flush_addr) + // initialization + .init_enable (init_enable), + .init_line_sel (init_line_sel) ); + + if (NUM_BANKS == 1) begin + assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr; + end else begin + assign per_bank_mem_req_addr[i] = `CS_LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i); + end end - VX_core_rsp_merge #( - .CACHE_ID (CACHE_ID), - .NUM_BANKS (NUM_BANKS), - .NUM_PORTS (NUM_PORTS), - .WORD_SIZE (WORD_SIZE), - .NUM_REQS (NUM_REQS), - .CORE_TAG_WIDTH (CORE_TAG_X_WIDTH), - .CORE_TAG_ID_BITS (CORE_TAG_ID_X_BITS) - ) core_rsp_merge ( - .clk (clk), - .reset (reset), - .per_bank_core_rsp_valid (per_bank_core_rsp_valid), - .per_bank_core_rsp_pmask (per_bank_core_rsp_pmask), - .per_bank_core_rsp_data (per_bank_core_rsp_data), - .per_bank_core_rsp_tag (per_bank_core_rsp_tag), - .per_bank_core_rsp_tid (per_bank_core_rsp_tid), - .per_bank_core_rsp_ready (per_bank_core_rsp_ready), - .core_rsp_valid (core_rsp_valid_c), - .core_rsp_tmask (core_rsp_tmask_c), - .core_rsp_tag (core_rsp_tag_c), - .core_rsp_data (core_rsp_data_c), - .core_rsp_ready (core_rsp_ready_c) - ); + // Bank responses gather + + wire [NUM_BANKS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_in; + wire [NUM_REQS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_out; - wire [NUM_BANKS-1:0][(`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + NUM_PORTS * (1 + WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH))-1:0] data_in; for (genvar i = 0; i < NUM_BANKS; ++i) begin - assign data_in[i] = {per_bank_mem_req_addr[i], per_bank_mem_req_id[i], per_bank_mem_req_rw[i], per_bank_mem_req_pmask[i], per_bank_mem_req_byteen[i], per_bank_mem_req_wsel[i], per_bank_mem_req_data[i]}; + assign core_rsp_data_in[i] = {per_bank_core_rsp_data[i], per_bank_core_rsp_tag[i]}; end - wire [MSHR_ADDR_WIDTH-1:0] mem_req_id; + `RESET_RELAY (rsp_xbar_reset, reset); - `RESET_RELAY (mreq_reset); - - VX_stream_arbiter #( - .NUM_REQS (NUM_BANKS), - .DATAW (`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + NUM_PORTS * (1 + WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)), - .TYPE ("R") - ) mem_req_arb ( + VX_stream_xbar #( + .NUM_INPUTS (NUM_BANKS), + .NUM_OUTPUTS (NUM_REQS), + .DATAW (CORE_RSP_DATAW) + ) rsp_xbar ( .clk (clk), - .reset (mreq_reset), - .valid_in (per_bank_mem_req_valid), - .data_in (data_in), - .ready_in (per_bank_mem_req_ready), - .valid_out (mem_req_valid_c), - .data_out ({mem_req_addr_c, mem_req_id, mem_req_rw_c, mem_req_pmask_c, mem_req_byteen_c, mem_req_wsel_c, mem_req_data_c}), - .ready_out (mem_req_ready_c) + .reset (rsp_xbar_reset), + `UNUSED_PIN (collisions), + .valid_in (per_bank_core_rsp_valid), + .data_in (core_rsp_data_in), + .sel_in (per_bank_core_rsp_idx), + .ready_in (per_bank_core_rsp_ready), + .valid_out (core_rsp_valid_s), + .data_out (core_rsp_data_out), + .ready_out (core_rsp_ready_s), + `UNUSED_PIN (sel_out) ); - if (NUM_BANKS == 1) begin - assign mem_req_tag_c = MEM_TAG_IN_WIDTH'(mem_req_id); + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign {core_rsp_data_s[i], core_rsp_tag_s[i]} = core_rsp_data_out[i]; + end + + /////////////////////////////////////////////////////////////////////////// + + wire mem_req_valid_p; + wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_p; + wire mem_req_rw_p; + wire [WORD_SEL_WIDTH-1:0] mem_req_wsel_p; + wire [WORD_SIZE-1:0] mem_req_byteen_p; + wire [`CS_WORD_WIDTH-1:0] mem_req_data_p; + wire [MEM_TAG_WIDTH-1:0] mem_req_tag_p; + wire [MSHR_ADDR_WIDTH-1:0] mem_req_id_p; + wire mem_req_ready_p; + + // Memory request arbitration + + wire [NUM_BANKS-1:0][(`CS_MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH)-1:0] data_in; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign data_in[i] = {per_bank_mem_req_addr[i], + per_bank_mem_req_rw[i], + per_bank_mem_req_wsel[i], + per_bank_mem_req_byteen[i], + per_bank_mem_req_data[i], + per_bank_mem_req_id[i]}; + end + + `RESET_RELAY (mem_req_arb_reset, reset); + + VX_stream_arb #( + .NUM_INPUTS (NUM_BANKS), + .DATAW (`CS_MEM_ADDR_WIDTH + 1 + WORD_SEL_WIDTH + WORD_SIZE + `CS_WORD_WIDTH + MSHR_ADDR_WIDTH), + .ARBITER ("R") + ) mem_req_arb ( + .clk (clk), + .reset (mem_req_arb_reset), + .valid_in (per_bank_mem_req_valid), + .ready_in (per_bank_mem_req_ready), + .data_in (data_in), + .data_out ({mem_req_addr_p, mem_req_rw_p, mem_req_wsel_p, mem_req_byteen_p, mem_req_data_p, mem_req_id_p}), + .valid_out (mem_req_valid_p), + .ready_out (mem_req_ready_p), + `UNUSED_PIN (sel_out) + ); + + if (NUM_BANKS > 1) begin + wire [`CS_BANK_SEL_BITS-1:0] mem_req_bank_id = `CS_MEM_ADDR_TO_BANK_ID(mem_req_addr_p); + assign mem_req_tag_p = MEM_TAG_WIDTH'({mem_req_bank_id, mem_req_id_p}); end else begin - assign mem_req_tag_c = MEM_TAG_IN_WIDTH'({`MEM_ADDR_TO_BANK_ID(mem_req_addr_c), mem_req_id}); - end + assign mem_req_tag_p = MEM_TAG_WIDTH'(mem_req_id_p); + end + + // Memory request multi-port handling + + assign mem_req_valid_s = mem_req_valid_p; + assign mem_req_addr_s = mem_req_addr_p; + assign mem_req_tag_s = mem_req_tag_p; + assign mem_req_ready_p = mem_req_ready_s; + + if (WRITE_ENABLE != 0) begin + if (`CS_WORDS_PER_LINE > 1) begin + reg [LINE_SIZE-1:0] mem_req_byteen_r; + reg [`CS_LINE_WIDTH-1:0] mem_req_data_r; + + always @(*) begin + mem_req_byteen_r = '0; + mem_req_data_r = 'x; + mem_req_byteen_r[mem_req_wsel_p * WORD_SIZE +: WORD_SIZE] = mem_req_byteen_p; + mem_req_data_r[mem_req_wsel_p * `CS_WORD_WIDTH +: `CS_WORD_WIDTH] = mem_req_data_p; + end + assign mem_req_rw_s = mem_req_rw_p; + assign mem_req_byteen_s = mem_req_byteen_r; + assign mem_req_data_s = mem_req_data_r; + end else begin + `UNUSED_VAR (mem_req_wsel_p) + assign mem_req_rw_s = mem_req_rw_p; + assign mem_req_byteen_s = mem_req_byteen_p; + assign mem_req_data_s = mem_req_data_p; + end + end else begin + `UNUSED_VAR (mem_req_byteen_p) + `UNUSED_VAR (mem_req_wsel_p) + `UNUSED_VAR (mem_req_data_p) + `UNUSED_VAR (mem_req_rw_p) + + assign mem_req_rw_s = 0; + assign mem_req_byteen_s = {LINE_SIZE{1'b1}}; + assign mem_req_data_s = '0; + end `ifdef PERF_ENABLE // per cycle: core_reads, core_writes - wire [$clog2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; - wire [$clog2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; - wire [$clog2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; - wire [NUM_REQS-1:0] perf_core_reads_per_mask = core_req_valid_c & core_req_ready_c & ~core_req_rw; - wire [NUM_REQS-1:0] perf_core_writes_per_mask = core_req_valid_c & core_req_ready_c & core_req_rw; - + wire [NUM_REQS-1:0] perf_core_reads_per_req = core_req_valid & core_req_ready & ~core_req_rw; + wire [NUM_REQS-1:0] perf_core_writes_per_req = core_req_valid & core_req_ready & core_req_rw; + // per cycle: read misses, write misses, msrq stalls, pipeline stalls - wire [$clog2(NUM_BANKS+1)-1:0] perf_read_miss_per_cycle; - wire [$clog2(NUM_BANKS+1)-1:0] perf_write_miss_per_cycle; - wire [$clog2(NUM_BANKS+1)-1:0] perf_mshr_stall_per_cycle; - wire [$clog2(NUM_BANKS+1)-1:0] perf_crsp_stall_per_cycle; + wire [`CLOG2(NUM_BANKS+1)-1:0] perf_read_miss_per_cycle; + wire [`CLOG2(NUM_BANKS+1)-1:0] perf_write_miss_per_cycle; + wire [`CLOG2(NUM_BANKS+1)-1:0] perf_mshr_stall_per_cycle; + wire [`CLOG2(NUM_BANKS+1)-1:0] perf_crsp_stall_per_cycle; - `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_mask); - `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_mask); - `POP_COUNT(perf_read_miss_per_cycle, perf_read_miss_per_bank); - `POP_COUNT(perf_write_miss_per_cycle, perf_write_miss_per_bank); - `POP_COUNT(perf_mshr_stall_per_cycle, perf_mshr_stall_per_bank); + `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_req); + `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_req); + `POP_COUNT(perf_read_miss_per_cycle, perf_read_miss_per_bank); + `POP_COUNT(perf_write_miss_per_cycle, perf_write_miss_per_bank); + `POP_COUNT(perf_mshr_stall_per_cycle, perf_mshr_stall_per_bank); - if (CORE_TAG_ID_BITS != 0) begin - wire [NUM_REQS-1:0] perf_crsp_stall_per_mask = core_rsp_tmask & {NUM_REQS{core_rsp_valid && ~core_rsp_ready}}; - `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_mask); - end else begin - wire [NUM_REQS-1:0] perf_crsp_stall_per_mask = core_rsp_valid & ~core_rsp_ready; - `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_mask); + wire [NUM_REQS-1:0] perf_crsp_stall_per_req; + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign perf_crsp_stall_per_req[i] = core_bus_if[i].rsp_valid && ~core_bus_if[i].rsp_ready; end - wire perf_mem_stall_per_cycle = mem_req_valid & ~mem_req_ready; + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req); + + wire perf_mem_stall_per_cycle = mem_bus_if.req_valid && ~mem_bus_if.req_ready; reg [`PERF_CTR_BITS-1:0] perf_core_reads; reg [`PERF_CTR_BITS-1:0] perf_core_writes; @@ -731,13 +560,13 @@ module VX_cache #( always @(posedge clk) begin if (reset) begin - perf_core_reads <= 0; - perf_core_writes <= 0; - perf_read_misses <= 0; - perf_write_misses <= 0; - perf_mshr_stalls <= 0; - perf_mem_stalls <= 0; - perf_crsp_stalls <= 0; + perf_core_reads <= '0; + perf_core_writes <= '0; + perf_read_misses <= '0; + perf_write_misses <= '0; + perf_mshr_stalls <= '0; + perf_mem_stalls <= '0; + perf_crsp_stalls <= '0; end else begin perf_core_reads <= perf_core_reads + `PERF_CTR_BITS'(perf_core_reads_per_cycle); perf_core_writes <= perf_core_writes + `PERF_CTR_BITS'(perf_core_writes_per_cycle); @@ -749,13 +578,13 @@ module VX_cache #( end end - assign perf_cache_if.reads = perf_core_reads; - assign perf_cache_if.writes = perf_core_writes; - assign perf_cache_if.read_misses = perf_read_misses; - assign perf_cache_if.write_misses = perf_write_misses; - assign perf_cache_if.mshr_stalls = perf_mshr_stalls; - assign perf_cache_if.mem_stalls = perf_mem_stalls; - assign perf_cache_if.crsp_stalls = perf_crsp_stalls; + assign cache_perf_if.reads = perf_core_reads; + assign cache_perf_if.writes = perf_core_writes; + assign cache_perf_if.read_misses = perf_read_misses; + assign cache_perf_if.write_misses = perf_write_misses; + assign cache_perf_if.mshr_stalls = perf_mshr_stalls; + assign cache_perf_if.mem_stalls = perf_mem_stalls; + assign cache_perf_if.crsp_stalls = perf_crsp_stalls; `endif endmodule diff --git a/hw/rtl/cache/VX_cache_bank.sv b/hw/rtl/cache/VX_cache_bank.sv new file mode 100644 index 00000000..937ef63b --- /dev/null +++ b/hw/rtl/cache/VX_cache_bank.sv @@ -0,0 +1,549 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_bank #( + parameter `STRING INSTANCE_ID= "", + parameter BANK_ID = 0, + + // Number of Word requests per cycle + parameter NUM_REQS = 1, + + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 4, + + // Core Response Queue Size + parameter CRSQ_SIZE = 1, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 1, + // Memory Request Queue Size + parameter MREQ_SIZE = 1, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Request debug identifier + parameter UUID_WIDTH = 0, + + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + + // Core response output register + parameter CORE_OUT_REG = 0, + + // Memory request output register + parameter MEM_OUT_REG = 0, + + parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE), + parameter REQ_SEL_WIDTH = `UP(`CS_REQ_SEL_BITS), + parameter WORD_SEL_WIDTH = `UP(`CS_WORD_SEL_BITS) +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire perf_read_misses, + output wire perf_write_misses, + output wire perf_mshr_stalls, +`endif + + // Core Request + input wire core_req_valid, + input wire [`CS_LINE_ADDR_WIDTH-1:0] core_req_addr, + input wire core_req_rw, + input wire [WORD_SEL_WIDTH-1:0] core_req_wsel, + input wire [WORD_SIZE-1:0] core_req_byteen, + input wire [`CS_WORD_WIDTH-1:0] core_req_data, + input wire [TAG_WIDTH-1:0] core_req_tag, + input wire [REQ_SEL_WIDTH-1:0] core_req_idx, + output wire core_req_ready, + + // Core Response + output wire core_rsp_valid, + output wire [`CS_WORD_WIDTH-1:0] core_rsp_data, + output wire [TAG_WIDTH-1:0] core_rsp_tag, + output wire [REQ_SEL_WIDTH-1:0] core_rsp_idx, + input wire core_rsp_ready, + + // Memory request + output wire mem_req_valid, + output wire [`CS_LINE_ADDR_WIDTH-1:0] mem_req_addr, + output wire mem_req_rw, + output wire [WORD_SEL_WIDTH-1:0] mem_req_wsel, + output wire [WORD_SIZE-1:0] mem_req_byteen, + output wire [`CS_WORD_WIDTH-1:0] mem_req_data, + output wire [MSHR_ADDR_WIDTH-1:0] mem_req_id, + input wire mem_req_ready, + + // Memory response + input wire mem_rsp_valid, + input wire [`CS_LINE_WIDTH-1:0] mem_rsp_data, + input wire [MSHR_ADDR_WIDTH-1:0] mem_rsp_id, + output wire mem_rsp_ready, + + // initialization + input wire init_enable, + input wire [`CS_LINE_SEL_BITS-1:0] init_line_sel +); + +`IGNORE_UNUSED_BEGIN + wire [`UP(UUID_WIDTH)-1:0] req_uuid_sel, req_uuid_st0, req_uuid_st1; +`IGNORE_UNUSED_END + + wire crsq_stall; + wire mshr_alm_full; + wire mreq_alm_full; + + wire [`CS_LINE_ADDR_WIDTH-1:0] mem_rsp_addr; + + wire replay_valid; + wire [`CS_LINE_ADDR_WIDTH-1:0] replay_addr; + wire replay_rw; + wire [WORD_SEL_WIDTH-1:0] replay_wsel; + wire [WORD_SIZE-1:0] replay_byteen; + wire [`CS_WORD_WIDTH-1:0] replay_data; + wire [TAG_WIDTH-1:0] replay_tag; + wire [REQ_SEL_WIDTH-1:0] replay_idx; + wire [MSHR_ADDR_WIDTH-1:0] replay_id; + wire replay_ready; + + wire [`CS_LINE_ADDR_WIDTH-1:0] addr_sel, addr_st0, addr_st1; + wire rw_st0, rw_st1; + wire [WORD_SEL_WIDTH-1:0] wsel_st0, wsel_st1; + wire [WORD_SIZE-1:0] byteen_st0, byteen_st1; + wire [REQ_SEL_WIDTH-1:0] req_idx_st0, req_idx_st1; + wire [TAG_WIDTH-1:0] tag_st0, tag_st1; + wire [`CS_WORD_WIDTH-1:0] read_data_st1; + wire [`CS_LINE_WIDTH-1:0] data_sel, data_st0, data_st1; + wire [MSHR_ADDR_WIDTH-1:0] replay_id_st0, mshr_id_st0, mshr_id_st1; + wire valid_sel, valid_st0, valid_st1; + wire is_init_st0; + wire is_creq_st0, is_creq_st1; + wire is_fill_st0, is_fill_st1; + wire is_replay_st0, is_replay_st1; + wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id_st0; + wire [MSHR_ADDR_WIDTH-1:0] mshr_tail_st0, mshr_tail_st1; + wire mshr_pending_st0, mshr_pending_st1; + + wire rdw_hazard_st0; + reg rdw_hazard_st1; + + wire pipe_stall = crsq_stall || rdw_hazard_st1; + + // inputs arbitration: + // mshr replay has highest priority to maximize utilization since there is no miss. + // handle memory responses next to prevent deadlock with potential memory request from a miss. + wire replay_grant = ~init_enable; + wire replay_enable = replay_grant && replay_valid; + + wire fill_grant = ~init_enable && ~replay_enable; + wire fill_enable = fill_grant && mem_rsp_valid; + + wire creq_grant = ~init_enable && ~replay_enable && ~fill_enable; + wire creq_enable = creq_grant && core_req_valid; + + assign replay_ready = replay_grant + && ~rdw_hazard_st0 + && ~pipe_stall; + + assign mem_rsp_ready = fill_grant + && ~pipe_stall; + + assign core_req_ready = creq_grant + && ~mreq_alm_full + && ~mshr_alm_full + && ~pipe_stall; + + wire init_fire = init_enable; + wire replay_fire = replay_valid && replay_ready; + wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; + wire core_req_fire = core_req_valid && core_req_ready; + + wire [TAG_WIDTH-1:0] mshr_creq_tag = replay_enable ? replay_tag : core_req_tag; + + if (UUID_WIDTH != 0) begin + assign req_uuid_sel = mshr_creq_tag[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin + assign req_uuid_sel = 0; + end + + `UNUSED_VAR (mshr_creq_tag) + + assign valid_sel = init_fire || replay_fire || mem_rsp_fire || core_req_fire; + + assign addr_sel = init_enable ? `CS_LINE_ADDR_WIDTH'(init_line_sel) : + (replay_valid ? replay_addr : + (mem_rsp_valid ? mem_rsp_addr : core_req_addr)); + + assign data_sel[`CS_WORD_WIDTH-1:0] = (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data[`CS_WORD_WIDTH-1:0] : (replay_valid ? replay_data : core_req_data); + for (genvar i = `CS_WORD_WIDTH; i < `CS_LINE_WIDTH; ++i) begin + assign data_sel[i] = mem_rsp_data[i]; + end + + VX_pipe_register #( + .DATAW (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + 1 + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH), + .RESETW (1) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (~pipe_stall), + .data_in ({ + valid_sel, + init_enable, + replay_enable, + fill_enable, + creq_enable, + addr_sel, + data_sel, + replay_valid ? replay_rw : core_req_rw, + replay_valid ? replay_byteen : core_req_byteen, + replay_valid ? replay_wsel : core_req_wsel, + replay_valid ? replay_idx : core_req_idx, + replay_valid ? replay_tag : core_req_tag, + replay_id + }), + .data_out ({valid_st0, is_init_st0, is_replay_st0, is_fill_st0, is_creq_st0, addr_st0, data_st0, rw_st0, byteen_st0, wsel_st0, req_idx_st0, tag_st0, replay_id_st0}) + ); + + if (UUID_WIDTH != 0) begin + assign req_uuid_st0 = tag_st0[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin + assign req_uuid_st0 = 0; + end + + wire do_creq_rd_st0 = valid_st0 && is_creq_st0 && ~rw_st0; + wire do_fill_st0 = valid_st0 && is_fill_st0; + wire do_init_st0 = valid_st0 && is_init_st0; + wire do_lookup_st0 = valid_st0 && ~(is_fill_st0 || is_init_st0); + + wire [`CS_WORD_WIDTH-1:0] write_data_st0 = data_st0[`CS_WORD_WIDTH-1:0]; + + wire [NUM_WAYS-1:0] tag_matches_st0, tag_matches_st1; + wire [NUM_WAYS-1:0] way_sel_st0, way_sel_st1; + + `RESET_RELAY (tag_reset, reset); + + VX_cache_tags #( + .INSTANCE_ID(INSTANCE_ID), + .BANK_ID (BANK_ID), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .UUID_WIDTH (UUID_WIDTH) + ) cache_tags ( + .clk (clk), + .reset (tag_reset), + + .req_uuid (req_uuid_st0), + + .stall (pipe_stall), + + // read/Fill + .lookup (do_lookup_st0), + .line_addr (addr_st0), + .fill (do_fill_st0), + .init (do_init_st0), + .way_sel (way_sel_st0), + .tag_matches(tag_matches_st0) + ); + + assign mshr_id_st0 = is_creq_st0 ? mshr_alloc_id_st0 : replay_id_st0; + + VX_pipe_register #( + .DATAW (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_WAYS + NUM_WAYS + 1), + .RESETW (1) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (~pipe_stall), + .data_in ({valid_st0, is_replay_st0, is_fill_st0, is_creq_st0, rw_st0, addr_st0, data_st0, byteen_st0, wsel_st0, req_idx_st0, tag_st0, mshr_id_st0, mshr_tail_st0, tag_matches_st0, way_sel_st0, mshr_pending_st0}), + .data_out ({valid_st1, is_replay_st1, is_fill_st1, is_creq_st1, rw_st1, addr_st1, data_st1, byteen_st1, wsel_st1, req_idx_st1, tag_st1, mshr_id_st1, mshr_tail_st1, tag_matches_st1, way_sel_st1, mshr_pending_st1}) + ); + + // we have a tag hit + wire is_hit_st1 = (| tag_matches_st1); + + if (UUID_WIDTH != 0) begin + assign req_uuid_st1 = tag_st1[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin + assign req_uuid_st1 = 0; + end + + wire do_creq_rd_st1 = valid_st1 && is_creq_st1 && ~rw_st1; + wire do_creq_wr_st1 = valid_st1 && is_creq_st1 && rw_st1; + wire do_fill_st1 = valid_st1 && is_fill_st1; + wire do_replay_rd_st1 = valid_st1 && is_replay_st1 && ~rw_st1; + wire do_replay_wr_st1 = valid_st1 && is_replay_st1 && rw_st1; + + wire do_read_hit_st1 = do_creq_rd_st1 && is_hit_st1; + wire do_read_miss_st1 = do_creq_rd_st1 && ~is_hit_st1; + + wire do_write_hit_st1 = do_creq_wr_st1 && is_hit_st1; + wire do_write_miss_st1= do_creq_wr_st1 && ~is_hit_st1; + + `UNUSED_VAR (do_write_miss_st1) + + // ensure mshr replay always get a hit + `RUNTIME_ASSERT (~(valid_st1 && is_replay_st1) || is_hit_st1, ("runtime error: invalid mshr replay")); + + // detect BRAM's read-during-write hazard + assign rdw_hazard_st0 = do_fill_st0; // after a fill + always @(posedge clk) begin + rdw_hazard_st1 <= (do_creq_rd_st0 && do_write_hit_st1 && (addr_st0 == addr_st1)) + && ~rdw_hazard_st1; // after a write to same address + end + + wire [`CS_WORD_WIDTH-1:0] write_data_st1 = data_st1[`CS_WORD_WIDTH-1:0]; + wire [`CS_LINE_WIDTH-1:0] fill_data_st1 = data_st1; + + `RESET_RELAY (data_reset, reset); + + VX_cache_data #( + .INSTANCE_ID (INSTANCE_ID), + .BANK_ID (BANK_ID), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .WRITE_ENABLE (WRITE_ENABLE), + .UUID_WIDTH (UUID_WIDTH) + ) cache_data ( + .clk (clk), + .reset (data_reset), + + .req_uuid (req_uuid_st1), + + .stall (pipe_stall), + + .read (do_read_hit_st1 || do_replay_rd_st1), + .fill (do_fill_st1), + .write (do_write_hit_st1 || do_replay_wr_st1), + .way_sel (way_sel_st1 | tag_matches_st1), + .line_addr (addr_st1), + .wsel (wsel_st1), + .byteen (byteen_st1), + .fill_data (fill_data_st1), + .write_data (write_data_st1), + .read_data (read_data_st1) + ); + + wire [MSHR_SIZE-1:0] mshr_matches_st0; + wire mshr_allocate_st0 = valid_st0 && is_creq_st0 && ~pipe_stall; + wire mshr_lookup_st0 = mshr_allocate_st0; + wire mshr_finalize_st1 = valid_st1 && is_creq_st1 && ~pipe_stall; + wire mshr_release_st1 = is_hit_st1 || (rw_st1 && ~mshr_pending_st1); + + VX_pending_size #( + .SIZE (MSHR_SIZE) + ) mshr_pending_size ( + .clk (clk), + .reset (reset), + .incr (core_req_fire), + .decr (replay_fire || (mshr_finalize_st1 && mshr_release_st1)), + .full (mshr_alm_full), + `UNUSED_PIN (size), + `UNUSED_PIN (empty) + ); + + `RESET_RELAY (mshr_reset, reset); + + VX_cache_mshr #( + .INSTANCE_ID (INSTANCE_ID), + .BANK_ID (BANK_ID), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .MSHR_SIZE (MSHR_SIZE), + .UUID_WIDTH (UUID_WIDTH), + .DATA_WIDTH (WORD_SEL_WIDTH + WORD_SIZE + `CS_WORD_WIDTH + TAG_WIDTH + REQ_SEL_WIDTH) + ) cache_mshr ( + .clk (clk), + .reset (mshr_reset), + + .deq_req_uuid (req_uuid_sel), + .lkp_req_uuid (req_uuid_st0), + .fin_req_uuid (req_uuid_st1), + + // memory fill + .fill_valid (mem_rsp_fire), + .fill_id (mem_rsp_id), + .fill_addr (mem_rsp_addr), + + // dequeue + .dequeue_valid (replay_valid), + .dequeue_addr (replay_addr), + .dequeue_rw (replay_rw), + .dequeue_data ({replay_wsel, replay_byteen, replay_data, replay_tag, replay_idx}), + .dequeue_id (replay_id), + .dequeue_ready (replay_ready), + + // allocate + .allocate_valid (mshr_allocate_st0), + .allocate_addr (addr_st0), + .allocate_rw (rw_st0), + .allocate_data ({wsel_st0, byteen_st0, write_data_st0, tag_st0, req_idx_st0}), + .allocate_id (mshr_alloc_id_st0), + .allocate_tail (mshr_tail_st0), + `UNUSED_PIN (allocate_ready), + + // lookup + .lookup_valid (mshr_lookup_st0), + .lookup_addr (addr_st0), + .lookup_matches (mshr_matches_st0), + + // finalize + .finalize_valid (mshr_finalize_st1), + .finalize_release(mshr_release_st1), + .finalize_pending(mshr_pending_st1), + .finalize_id (mshr_id_st1), + .finalize_tail (mshr_tail_st1) + ); + + // ignore allocated id from mshr matches + wire [MSHR_SIZE-1:0] lookup_matches; + for (genvar i = 0; i < MSHR_SIZE; ++i) begin + assign lookup_matches[i] = (i != mshr_alloc_id_st0) && mshr_matches_st0[i]; + end + assign mshr_pending_st0 = (| lookup_matches); + + // schedule core response + + wire crsq_valid, crsq_ready; + wire [`CS_WORD_WIDTH-1:0] crsq_data; + wire [REQ_SEL_WIDTH-1:0] crsq_idx; + wire [TAG_WIDTH-1:0] crsq_tag; + + assign crsq_valid = do_read_hit_st1 || do_replay_rd_st1; + assign crsq_idx = req_idx_st1; + assign crsq_data = read_data_st1; + assign crsq_tag = tag_st1; + + `RESET_RELAY (crsp_reset, reset); + + VX_elastic_buffer #( + .DATAW (TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH), + .SIZE (CRSQ_SIZE), + .OUT_REG (CORE_OUT_REG) + ) core_rsp_queue ( + .clk (clk), + .reset (crsp_reset), + .valid_in (crsq_valid && ~rdw_hazard_st1), + .ready_in (crsq_ready), + .data_in ({crsq_tag, crsq_data, crsq_idx}), + .data_out ({core_rsp_tag, core_rsp_data, core_rsp_idx}), + .valid_out (core_rsp_valid), + .ready_out (core_rsp_ready) + ); + + assign crsq_stall = crsq_valid && ~crsq_ready; + + // schedule memory request + + wire mreq_push, mreq_pop, mreq_empty; + wire [`CS_WORD_WIDTH-1:0] mreq_data; + wire [WORD_SIZE-1:0] mreq_byteen; + wire [WORD_SEL_WIDTH-1:0] mreq_wsel; + wire [`CS_LINE_ADDR_WIDTH-1:0] mreq_addr; + wire [MSHR_ADDR_WIDTH-1:0] mreq_id; + wire mreq_rw; + + assign mreq_push = (do_read_miss_st1 && ~mshr_pending_st1) + || do_creq_wr_st1; + + assign mreq_pop = mem_req_valid && mem_req_ready; + + assign mreq_rw = WRITE_ENABLE && rw_st1; + assign mreq_addr = addr_st1; + assign mreq_id = mshr_id_st1; + assign mreq_wsel = wsel_st1; + assign mreq_byteen = byteen_st1; + assign mreq_data = write_data_st1; + + `RESET_RELAY (mreq_reset, reset); + + VX_fifo_queue #( + .DATAW (1 + `CS_LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH), + .DEPTH (MREQ_SIZE), + .ALM_FULL (MREQ_SIZE-2), + .OUT_REG (MEM_OUT_REG) + ) mem_req_queue ( + .clk (clk), + .reset (mreq_reset), + .push (mreq_push), + .pop (mreq_pop), + .data_in ({mreq_rw, mreq_addr, mreq_id, mreq_byteen, mreq_wsel, mreq_data}), + .data_out ({mem_req_rw, mem_req_addr, mem_req_id, mem_req_byteen, mem_req_wsel, mem_req_data}), + .empty (mreq_empty), + .alm_full (mreq_alm_full), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (size) + ); + + assign mem_req_valid = ~mreq_empty; + +/////////////////////////////////////////////////////////////////////////////// + +`ifdef PERF_ENABLE + assign perf_read_misses = do_read_miss_st1; + assign perf_write_misses = do_write_miss_st1; + assign perf_mshr_stalls = mshr_alm_full; +`endif + +`ifdef DBG_TRACE_CACHE_BANK + wire crsq_fire = crsq_valid && crsq_ready; + wire pipeline_stall = (replay_valid || mem_rsp_valid || core_req_valid) + && ~(replay_fire || mem_rsp_fire || core_req_fire); + always @(posedge clk) begin + if (pipeline_stall) begin + `TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full)); + end + if (init_enable) begin + `TRACE(2, ("%d: %s-bank%0d init: addr=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID))); + end + if (mem_rsp_fire) begin + `TRACE(2, ("%d: %s-bank%0d fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data)); + end + if (replay_fire) begin + `TRACE(2, ("%d: %s-bank%0d mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel)); + end + if (core_req_fire) begin + if (core_req_rw) + `TRACE(2, ("%d: %s-bank%0d core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel)); + else + `TRACE(2, ("%d: %s-bank%0d core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel)); + end + if (crsq_fire) begin + `TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_idx, crsq_data, req_uuid_st1)); + end + if (mreq_push) begin + if (do_creq_wr_st1) + `TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_byteen, mreq_data, req_uuid_st1)); + else + `TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_id, req_uuid_st1)); + end + end +`endif + +endmodule diff --git a/hw/rtl/cache/VX_cache_bypass.sv b/hw/rtl/cache/VX_cache_bypass.sv new file mode 100644 index 00000000..4a281f19 --- /dev/null +++ b/hw/rtl/cache/VX_cache_bypass.sv @@ -0,0 +1,348 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +module VX_cache_bypass #( + parameter NUM_REQS = 1, + parameter NC_TAG_BIT = 0, + + parameter NC_ENABLE = 0, + parameter PASSTHRU = 0, + + parameter CORE_ADDR_WIDTH = 1, + parameter CORE_DATA_SIZE = 1, + parameter CORE_TAG_IN_WIDTH = 1, + + parameter MEM_ADDR_WIDTH = 1, + parameter MEM_DATA_SIZE = 1, + parameter MEM_TAG_IN_WIDTH = 1, + parameter MEM_TAG_OUT_WIDTH = 1, + + parameter UUID_WIDTH = 0, + + parameter CORE_DATA_WIDTH = CORE_DATA_SIZE * 8, + parameter MEM_DATA_WIDTH = MEM_DATA_SIZE * 8, + parameter CORE_TAG_OUT_WIDTH= CORE_TAG_IN_WIDTH - NC_ENABLE + ) ( + input wire clk, + input wire reset, + + // Core request in + input wire [NUM_REQS-1:0] core_req_valid_in, + input wire [NUM_REQS-1:0] core_req_rw_in, + input wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_in, + input wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_in, + input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_in, + input wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_req_tag_in, + output wire [NUM_REQS-1:0] core_req_ready_in, + + // Core request out + output wire [NUM_REQS-1:0] core_req_valid_out, + output wire [NUM_REQS-1:0] core_req_rw_out, + output wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_out, + output wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_out, + output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_out, + output wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_req_tag_out, + input wire [NUM_REQS-1:0] core_req_ready_out, + + // Core response in + input wire [NUM_REQS-1:0] core_rsp_valid_in, + input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_in, + input wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_rsp_tag_in, + output wire [NUM_REQS-1:0] core_rsp_ready_in, + + // Core response out + output wire [NUM_REQS-1:0] core_rsp_valid_out, + output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_out, + output wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out, + input wire [NUM_REQS-1:0] core_rsp_ready_out, + + // Memory request in + input wire mem_req_valid_in, + input wire mem_req_rw_in, + input wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_in, + input wire [MEM_DATA_SIZE-1:0] mem_req_byteen_in, + input wire [MEM_DATA_WIDTH-1:0] mem_req_data_in, + input wire [MEM_TAG_IN_WIDTH-1:0] mem_req_tag_in, + output wire mem_req_ready_in, + + // Memory request out + output wire mem_req_valid_out, + output wire mem_req_rw_out, + output wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_out, + output wire [MEM_DATA_SIZE-1:0] mem_req_byteen_out, + output wire [MEM_DATA_WIDTH-1:0] mem_req_data_out, + output wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_out, + input wire mem_req_ready_out, + + // Memory response in + input wire mem_rsp_valid_in, + input wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_in, + input wire [MEM_TAG_OUT_WIDTH-1:0] mem_rsp_tag_in, + output wire mem_rsp_ready_in, + + // Memory response out + output wire mem_rsp_valid_out, + output wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_out, + output wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_out, + input wire mem_rsp_ready_out +); + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + localparam REQ_SEL_BITS = `CLOG2(NUM_REQS); + localparam MUX_DATAW = CORE_TAG_IN_WIDTH + CORE_DATA_WIDTH + CORE_DATA_SIZE + CORE_ADDR_WIDTH + 1; + + localparam WORDS_PER_LINE = MEM_DATA_SIZE / CORE_DATA_SIZE; + localparam WSEL_BITS = `CLOG2(WORDS_PER_LINE); + + localparam CORE_TAG_ID_BITS = CORE_TAG_IN_WIDTH - UUID_WIDTH; + localparam MEM_TAG_ID_BITS = REQ_SEL_BITS + WSEL_BITS + CORE_TAG_ID_BITS; + + localparam MEM_TAG_OUT_NC_WIDTH = MEM_TAG_OUT_WIDTH - 1 + NC_ENABLE; + + // core request handling + + wire [NUM_REQS-1:0] core_req_valid_in_nc; + wire [NUM_REQS-1:0] core_req_nc_idxs; + wire [`UP(REQ_SEL_BITS)-1:0] core_req_nc_idx; + wire [NUM_REQS-1:0] core_req_nc_sel; + wire core_req_nc_valid; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + if (PASSTHRU != 0) begin + assign core_req_nc_idxs[i] = 1'b1; + end else begin + assign core_req_nc_idxs[i] = core_req_tag_in[i][NC_TAG_BIT]; + end + end + + assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_idxs; + + wire core_req_in_fire = | (core_req_valid_in & core_req_ready_in); + + VX_generic_arbiter #( + .NUM_REQS (NUM_REQS), + .TYPE (PASSTHRU ? "R" : "P"), + .LOCK_ENABLE (1) + ) req_arb ( + .clk (clk), + .reset (reset), + .unlock (core_req_in_fire), + .requests (core_req_valid_in_nc), + .grant_index (core_req_nc_idx), + .grant_onehot (core_req_nc_sel), + .grant_valid (core_req_nc_valid) + ); + + assign core_req_valid_out = core_req_valid_in & ~core_req_nc_idxs; + assign core_req_rw_out = core_req_rw_in; + assign core_req_addr_out = core_req_addr_in; + assign core_req_byteen_out = core_req_byteen_in; + assign core_req_data_out = core_req_data_in; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + VX_bits_remove #( + .N (CORE_TAG_IN_WIDTH), + .S (NC_ENABLE), + .POS (NC_TAG_BIT) + ) core_req_tag_nc_remove ( + .data_in (core_req_tag_in[i]), + .data_out (core_req_tag_out[i]) + ); + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_req_ready_in[i] = core_req_valid_in_nc[i] ? (~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i]) + : core_req_ready_out[i]; + end + + // memory request handling + + assign mem_req_valid_out = mem_req_valid_in || core_req_nc_valid; + assign mem_req_ready_in = mem_req_ready_out; + + wire [CORE_TAG_IN_WIDTH-1:0] core_req_tag_in_sel; + wire [CORE_DATA_WIDTH-1:0] core_req_data_in_sel; + wire [CORE_DATA_SIZE-1:0] core_req_byteen_in_sel; + wire [CORE_ADDR_WIDTH-1:0] core_req_addr_in_sel; + wire core_req_rw_in_sel; + + wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in; + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_req_nc_mux_in[i] = {core_req_tag_in[i], core_req_data_in[i], core_req_byteen_in[i], core_req_addr_in[i], core_req_rw_in[i]}; + end + assign {core_req_tag_in_sel, core_req_data_in_sel, core_req_byteen_in_sel, core_req_addr_in_sel, core_req_rw_in_sel} = core_req_nc_mux_in[core_req_nc_idx]; + + wire [CORE_TAG_ID_BITS-1:0] core_req_in_id = core_req_tag_in_sel[CORE_TAG_ID_BITS-1:0]; + + assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in_sel; + assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in_sel[WSEL_BITS +: MEM_ADDR_WIDTH]; + + wire [MEM_TAG_ID_BITS-1:0] mem_req_tag_id_bypass; + + if (WORDS_PER_LINE > 1) begin + reg [WORDS_PER_LINE-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_in_r; + reg [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_r; + + wire [WSEL_BITS-1:0] req_wsel = core_req_addr_in_sel[WSEL_BITS-1:0]; + + always @(*) begin + mem_req_byteen_in_r = '0; + mem_req_byteen_in_r[req_wsel] = core_req_byteen_in_sel; + + mem_req_data_in_r = 'x; + mem_req_data_in_r[req_wsel] = core_req_data_in_sel; + end + + assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r; + assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : mem_req_data_in_r; + if (NUM_REQS > 1) begin + assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, req_wsel, core_req_in_id}); + end else begin + assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({req_wsel, core_req_in_id}); + end + end else begin + assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in_sel; + assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : core_req_data_in_sel; + if (NUM_REQS > 1) begin + assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, core_req_in_id}); + end else begin + assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_in_id}); + end + end + + wire [MEM_TAG_OUT_NC_WIDTH-1:0] mem_req_tag_bypass; + + if (UUID_WIDTH != 0) begin + assign mem_req_tag_bypass = {core_req_tag_in_sel[CORE_TAG_ID_BITS +: UUID_WIDTH], mem_req_tag_id_bypass}; + end else begin + assign mem_req_tag_bypass = mem_req_tag_id_bypass; + end + + wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_bypass_nc; + wire [(MEM_TAG_IN_WIDTH + 1)-1:0] mem_req_tag_in_nc; + + VX_bits_insert #( + .N (MEM_TAG_OUT_NC_WIDTH), + .S (NC_ENABLE ? 0 : 1), + .POS (NC_TAG_BIT) + ) mem_req_tag_bypass_nc_insert ( + .data_in (mem_req_tag_bypass), + .sel_in (1'b0), + .data_out (mem_req_tag_bypass_nc) + ); + + VX_bits_insert #( + .N (MEM_TAG_IN_WIDTH), + .POS (NC_TAG_BIT) + ) mem_req_tag_in_nc_insert ( + .data_in (mem_req_tag_in), + .sel_in (1'b0), + .data_out (mem_req_tag_in_nc) + ); + + assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : mem_req_tag_bypass_nc; + + // core response handling + + wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_in_nc; + + wire is_mem_rsp_nc; + if (PASSTHRU != 0) begin + assign is_mem_rsp_nc = mem_rsp_valid_in; + end else begin + assign is_mem_rsp_nc = mem_rsp_valid_in && mem_rsp_tag_in[NC_TAG_BIT]; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin + VX_bits_insert #( + .N (CORE_TAG_OUT_WIDTH), + .S (NC_ENABLE), + .POS (NC_TAG_BIT) + ) core_rsp_tag_in_nc_insert ( + .data_in (core_rsp_tag_in[i]), + .sel_in ('0), + .data_out (core_rsp_tag_in_nc[i]) + ); + end + + wire [MEM_TAG_OUT_NC_WIDTH-1:0] mem_rsp_tag_in_nc; + + VX_bits_remove #( + .N (MEM_TAG_OUT_WIDTH), + .S (NC_ENABLE ? 0 : 1), + .POS (NC_TAG_BIT) + ) mem_rsp_tag_in_nc_remove ( + .data_in (mem_rsp_tag_in), + .data_out (mem_rsp_tag_in_nc) + ); + + wire [`UP(REQ_SEL_BITS)-1:0] rsp_idx; + if (NUM_REQS > 1) begin + assign rsp_idx = mem_rsp_tag_in_nc[(CORE_TAG_ID_BITS + WSEL_BITS) +: REQ_SEL_BITS]; + end else begin + assign rsp_idx = 1'b0; + end + + reg [NUM_REQS-1:0] rsp_nc_valid_r; + always @(*) begin + rsp_nc_valid_r = '0; + rsp_nc_valid_r[rsp_idx] = is_mem_rsp_nc; + end + + assign core_rsp_valid_out = core_rsp_valid_in | rsp_nc_valid_r; + assign core_rsp_ready_in = core_rsp_ready_out; + + if (WORDS_PER_LINE > 1) begin + wire [WSEL_BITS-1:0] rsp_wsel = mem_rsp_tag_in_nc[CORE_TAG_ID_BITS +: WSEL_BITS]; + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? + core_rsp_data_in[i] : mem_rsp_data_in[rsp_wsel * CORE_DATA_WIDTH +: CORE_DATA_WIDTH]; + end + end else begin + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? core_rsp_data_in[i] : mem_rsp_data_in; + end + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin + if (UUID_WIDTH != 0) begin + assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_in_nc[i] : {mem_rsp_tag_in_nc[MEM_TAG_OUT_NC_WIDTH-1 -: UUID_WIDTH], mem_rsp_tag_in_nc[CORE_TAG_ID_BITS-1:0]}; + end else begin + assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_in_nc[i] : mem_rsp_tag_in_nc[CORE_TAG_ID_BITS-1:0]; + end + end + + // memory response handling + + if (PASSTHRU != 0) begin + assign mem_rsp_valid_out = 1'b0; + end else begin + assign mem_rsp_valid_out = mem_rsp_valid_in && ~mem_rsp_tag_in[NC_TAG_BIT]; + end + + assign mem_rsp_data_out = mem_rsp_data_in; + + VX_bits_remove #( + .N (MEM_TAG_IN_WIDTH + 1), + .POS (NC_TAG_BIT) + ) mem_rsp_tag_out_remove ( + .data_in (mem_rsp_tag_in[(MEM_TAG_IN_WIDTH + 1)-1:0]), + .data_out (mem_rsp_tag_out) + ); + + assign mem_rsp_ready_in = is_mem_rsp_nc ? (~core_rsp_valid_in[rsp_idx] && core_rsp_ready_out[rsp_idx]) : mem_rsp_ready_out; + +endmodule diff --git a/hw/rtl/cache/VX_cache_cluster.sv b/hw/rtl/cache/VX_cache_cluster.sv new file mode 100644 index 00000000..b1c846a3 --- /dev/null +++ b/hw/rtl/cache/VX_cache_cluster.sv @@ -0,0 +1,368 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_cluster #( + parameter `STRING INSTANCE_ID = "", + + parameter NUM_UNITS = 1, + parameter NUM_INPUTS = 1, + parameter TAG_SEL_IDX = 0, + + // Number of requests per cycle + parameter NUM_REQS = 4, + + // Size of cache in bytes + parameter CACHE_SIZE = 16384, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 4, + // Size of a word in bytes + parameter WORD_SIZE = 4, + + // Core Response Queue Size + parameter CRSQ_SIZE = 2, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 8, + // Memory Response Queue Size + parameter MRSQ_SIZE = 0, + // Memory Request Queue Size + parameter MREQ_SIZE = 4, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Request debug identifier + parameter UUID_WIDTH = 0, + + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + + // enable bypass for non-cacheable addresses + parameter NC_ENABLE = 0, + + // Core response output register + parameter CORE_OUT_REG = 0, + + // Memory request output register + parameter MEM_OUT_REG = 0 + ) ( + input wire clk, + input wire reset, + + // PERF +`ifdef PERF_ENABLE + VX_cache_perf_if.master cache_perf_if, +`endif + + VX_mem_bus_if.slave core_bus_if [NUM_INPUTS * NUM_REQS], + VX_mem_bus_if.master mem_bus_if +); + localparam NUM_CACHES = `UP(NUM_UNITS); + localparam PASSTHRU = (NUM_UNITS == 0); + localparam ARB_TAG_WIDTH = TAG_WIDTH + `ARB_SEL_BITS(NUM_INPUTS, NUM_CACHES); + localparam MEM_TAG_WIDTH = PASSTHRU ? (NC_ENABLE ? `CACHE_NC_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH) : + `CACHE_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH)) : + (NC_ENABLE ? `CACHE_NC_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH) : + `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS)); + + `STATIC_ASSERT(NUM_INPUTS >= NUM_CACHES, ("invalid parameter")) + +`ifdef PERF_ENABLE + VX_cache_perf_if perf_cache_unit_if[NUM_CACHES](); + `PERF_CACHE_ADD (cache_perf_if, perf_cache_unit_if, NUM_CACHES); +`endif + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH) + ) cache_mem_bus_if[NUM_CACHES](); + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (ARB_TAG_WIDTH) + ) arb_core_bus_if[NUM_CACHES * NUM_REQS](); + + + for (genvar i = 0; i < NUM_REQS; ++i) begin + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH) + ) core_bus_tmp_if[NUM_INPUTS](); + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (ARB_TAG_WIDTH) + ) arb_core_bus_tmp_if[NUM_CACHES](); + + for (genvar j = 0; j < NUM_INPUTS; ++j) begin + `ASSIGN_VX_MEM_BUS_IF (core_bus_tmp_if[j], core_bus_if[j * NUM_REQS + i]); + end + + `RESET_RELAY (cache_arb_reset, reset); + + VX_mem_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_CACHES), + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .TAG_SEL_IDX (TAG_SEL_IDX), + .ARBITER ("R"), + .OUT_REG_REQ ((NUM_INPUTS != NUM_CACHES) ? 2 : 0), + .OUT_REG_RSP ((NUM_INPUTS != NUM_CACHES) ? 2 : 0) + ) cache_arb ( + .clk (clk), + .reset (cache_arb_reset), + .bus_in_if (core_bus_tmp_if), + .bus_out_if (arb_core_bus_tmp_if) + ); + + for (genvar k = 0; k < NUM_CACHES; ++k) begin + `ASSIGN_VX_MEM_BUS_IF (arb_core_bus_if[k * NUM_REQS + i], arb_core_bus_tmp_if[k]); + end + end + + for (genvar i = 0; i < NUM_CACHES; ++i) begin + + `RESET_RELAY (cache_reset, reset); + + VX_cache_wrap #( + .INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, i)), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MRSQ_SIZE (MRSQ_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .WRITE_ENABLE (WRITE_ENABLE), + .UUID_WIDTH (UUID_WIDTH), + .TAG_WIDTH (ARB_TAG_WIDTH), + .CORE_OUT_REG ((NUM_INPUTS != NUM_CACHES) ? 2 : CORE_OUT_REG), + .MEM_OUT_REG ((NUM_CACHES > 1) ? 2 : MEM_OUT_REG), + .NC_ENABLE (NC_ENABLE), + .PASSTHRU (PASSTHRU) + ) cache_wrap ( + `ifdef PERF_ENABLE + .cache_perf_if (perf_cache_unit_if[i]), + `endif + .clk (clk), + .reset (cache_reset), + .core_bus_if (arb_core_bus_if[i * NUM_REQS +: NUM_REQS]), + .mem_bus_if (cache_mem_bus_if[i]) + ); + end + + `RESET_RELAY (mem_arb_reset, reset); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH + `ARB_SEL_BITS(NUM_CACHES, 1)) + ) mem_bus_tmp_if[1](); + + VX_mem_arb #( + .NUM_INPUTS (NUM_CACHES), + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH), + .TAG_SEL_IDX (1), // Skip 0 for NC flag + .ARBITER ("R"), + .OUT_REG_REQ ((NUM_CACHES > 1) ? 2 : 0), + .OUT_REG_RSP ((NUM_CACHES > 1) ? 2 : 0) + ) mem_arb ( + .clk (clk), + .reset (mem_arb_reset), + .bus_in_if (cache_mem_bus_if), + .bus_out_if (mem_bus_tmp_if) + ); + + `ASSIGN_VX_MEM_BUS_IF (mem_bus_if, mem_bus_tmp_if[0]); + +endmodule + +/////////////////////////////////////////////////////////////////////////////// + +module VX_cache_cluster_top #( + parameter `STRING INSTANCE_ID = "", + + parameter NUM_UNITS = 2, + parameter NUM_INPUTS = 4, + parameter TAG_SEL_IDX = 0, + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + + // Size of cache in bytes + parameter CACHE_SIZE = 16384, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 4, + // Number of associative ways + parameter NUM_WAYS = 4, + // Size of a word in bytes + parameter WORD_SIZE = 4, + + // Core Response Queue Size + parameter CRSQ_SIZE = 2, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 16, + // Memory Response Queue Size + parameter MRSQ_SIZE = 0, + // Memory Request Queue Size + parameter MREQ_SIZE = 4, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Request debug identifier + parameter UUID_WIDTH = 0, + + // core request tag size + parameter TAG_WIDTH = 16, + + // enable bypass for non-cacheable addresses + parameter NC_ENABLE = 1, + + // Core response output register + parameter CORE_OUT_REG = 2, + + // Memory request output register + parameter MEM_OUT_REG = 2, + + parameter NUM_CACHES = `UP(NUM_UNITS), + parameter PASSTHRU = (NUM_UNITS == 0), + parameter ARB_TAG_WIDTH = TAG_WIDTH + `ARB_SEL_BITS(NUM_INPUTS, NUM_CACHES), + parameter MEM_TAG_WIDTH = PASSTHRU ? (NC_ENABLE ? `CACHE_NC_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH) : + `CACHE_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH)) : + (NC_ENABLE ? `CACHE_NC_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH) : + `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS)) + ) ( + input wire clk, + input wire reset, + + // Core request + input wire [NUM_INPUTS-1:0][NUM_REQS-1:0] core_req_valid, + input wire [NUM_INPUTS-1:0][NUM_REQS-1:0] core_req_rw, + input wire [NUM_INPUTS-1:0][NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen, + input wire [NUM_INPUTS-1:0][NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr, + input wire [NUM_INPUTS-1:0][NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data, + input wire [NUM_INPUTS-1:0][NUM_REQS-1:0][TAG_WIDTH-1:0] core_req_tag, + output wire [NUM_INPUTS-1:0][NUM_REQS-1:0] core_req_ready, + + // Core response + output wire [NUM_INPUTS-1:0][NUM_REQS-1:0] core_rsp_valid, + output wire [NUM_INPUTS-1:0][NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data, + output wire [NUM_INPUTS-1:0][NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag, + input wire [NUM_INPUTS-1:0][NUM_REQS-1:0] core_rsp_ready, + + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [LINE_SIZE-1:0] mem_req_byteen, + output wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`CS_LINE_WIDTH-1:0] mem_req_data, + output wire [MEM_TAG_WIDTH-1:0] mem_req_tag, + input wire mem_req_ready, + + // Memory response + input wire mem_rsp_valid, + input wire [`CS_LINE_WIDTH-1:0] mem_rsp_data, + input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_rsp_ready +); + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH) + ) core_bus_if[NUM_INPUTS * NUM_REQS](); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH) + ) mem_bus_if(); + + // Core request + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + for (genvar r = 0; r < NUM_REQS; ++r) begin + assign core_bus_if[i * NUM_REQS + r].req_valid = core_req_valid[i][r]; + assign core_bus_if[i * NUM_REQS + r].req_data.rw = core_req_rw[i][r]; + assign core_bus_if[i * NUM_REQS + r].req_data.byteen = core_req_byteen[i][r]; + assign core_bus_if[i * NUM_REQS + r].req_data.addr = core_req_addr[i][r]; + assign core_bus_if[i * NUM_REQS + r].req_data.data = core_req_data[i][r]; + assign core_bus_if[i * NUM_REQS + r].req_data.tag = core_req_tag[i][r]; + assign core_req_ready[i][r] = core_bus_if[i * NUM_REQS + r].req_ready; + end + end + + // Core response + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + for (genvar r = 0; r < NUM_REQS; ++r) begin + assign core_rsp_valid[i][r] = core_bus_if[i * NUM_REQS + r].rsp_valid; + assign core_rsp_data[i][r] = core_bus_if[i * NUM_REQS + r].rsp_data.data; + assign core_rsp_tag[i][r] = core_bus_if[i * NUM_REQS + r].rsp_data.tag; + assign core_bus_if[i * NUM_REQS + r].rsp_ready = core_rsp_ready[i][r]; + end + end + + // Memory request + assign mem_req_valid = mem_bus_if.req_valid; + assign mem_req_rw = mem_bus_if.req_data.rw; + assign mem_req_byteen = mem_bus_if.req_data.byteen; + assign mem_req_addr = mem_bus_if.req_data.addr; + assign mem_req_data = mem_bus_if.req_data.data; + assign mem_req_tag = mem_bus_if.req_data.tag; + assign mem_bus_if.req_ready = mem_req_ready; + + // Memory response + assign mem_bus_if.rsp_valid = mem_rsp_valid; + assign mem_bus_if.rsp_data.data = mem_rsp_data; + assign mem_bus_if.rsp_data.tag = mem_rsp_tag; + assign mem_rsp_ready = mem_bus_if.rsp_ready; + + VX_cache_cluster #( + .INSTANCE_ID (INSTANCE_ID), + .NUM_UNITS (NUM_UNITS), + .NUM_INPUTS (NUM_INPUTS), + .TAG_SEL_IDX (TAG_SEL_IDX), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MRSQ_SIZE (MRSQ_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .UUID_WIDTH (UUID_WIDTH), + .WRITE_ENABLE (WRITE_ENABLE), + .CORE_OUT_REG (CORE_OUT_REG), + .MEM_OUT_REG (MEM_OUT_REG) + ) cache ( + `ifdef PERF_ENABLE + .cache_perf_if (perf_icache_if), + `endif + .clk (clk), + .reset (reset), + .core_bus_if (core_bus_if), + .mem_bus_if (mem_bus_if) + ); + + endmodule diff --git a/hw/rtl/cache/VX_cache_data.sv b/hw/rtl/cache/VX_cache_data.sv new file mode 100644 index 00000000..493e4884 --- /dev/null +++ b/hw/rtl/cache/VX_cache_data.sv @@ -0,0 +1,152 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_data #( + parameter `STRING INSTANCE_ID= "", + parameter BANK_ID = 0, + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // Enable cache writeable + parameter WRITE_ENABLE = 1, + // Request debug identifier + parameter UUID_WIDTH = 0 +) ( + input wire clk, + input wire reset, + +`IGNORE_UNUSED_BEGIN + input wire[`UP(UUID_WIDTH)-1:0] req_uuid, +`IGNORE_UNUSED_END + + input wire stall, + + input wire read, + input wire fill, + input wire write, + input wire [`CS_LINE_ADDR_WIDTH-1:0] line_addr, + input wire [`UP(`CS_WORD_SEL_BITS)-1:0] wsel, + input wire [WORD_SIZE-1:0] byteen, + input wire [`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] fill_data, + input wire [`CS_WORD_WIDTH-1:0] write_data, + input wire [NUM_WAYS-1:0] way_sel, + + output wire [`CS_WORD_WIDTH-1:0] read_data +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (BANK_ID) + `UNUSED_PARAM (WORD_SIZE) + `UNUSED_VAR (reset) + `UNUSED_VAR (line_addr) + `UNUSED_VAR (read) + + localparam BYTEENW = (WRITE_ENABLE != 0 || (NUM_WAYS > 1)) ? (LINE_SIZE * NUM_WAYS) : 1; + + wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] wdata; + wire [BYTEENW-1:0] wren; + + if (WRITE_ENABLE != 0 || (NUM_WAYS > 1)) begin + reg [`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] wdata_r; + reg [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wren_r; + + always @(*) begin + wdata_r = {`CS_WORDS_PER_LINE{write_data}}; + wren_r = '0; + wren_r[wsel] = byteen; + end + + // order the data layout to perform ways multiplexing last + // this allows performing onehot encoding of the way index in parallel with BRAM read. + wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][WORD_SIZE-1:0] wren_w; + for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin + assign wdata[i] = fill ? {NUM_WAYS{fill_data[i]}} : {NUM_WAYS{wdata_r[i]}}; + for (genvar j = 0; j < NUM_WAYS; ++j) begin + assign wren_w[i][j] = (fill ? {WORD_SIZE{1'b1}} : wren_r[i]) + & {WORD_SIZE{((NUM_WAYS == 1) || way_sel[j])}}; + end + end + assign wren = wren_w; + end else begin + `UNUSED_VAR (write) + `UNUSED_VAR (byteen) + `UNUSED_VAR (write_data) + assign wdata = fill_data; + assign wren = fill; + end + + wire [`CLOG2(NUM_WAYS)-1:0] way_idx; + + VX_onehot_encoder #( + .N (NUM_WAYS) + ) way_enc ( + .data_in (way_sel), + .data_out (way_idx), + `UNUSED_PIN (valid_out) + ); + + wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] rdata; + + wire [`CS_LINE_SEL_BITS-1:0] line_sel = line_addr[`CS_LINE_SEL_BITS-1:0]; + + VX_sp_ram #( + .DATAW (`CS_LINE_WIDTH * NUM_WAYS), + .SIZE (`CS_LINES_PER_BANK), + .WRENW (BYTEENW), + .NO_RWCHECK (1) + ) data_store ( + .clk (clk), + .read (1'b1), + .write (write || fill), + .wren (wren), + .addr (line_sel), + .wdata (wdata), + .rdata (rdata) + ); + + wire [NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] per_way_rdata; + + if (`CS_WORDS_PER_LINE > 1) begin + assign per_way_rdata = rdata[wsel]; + end else begin + `UNUSED_VAR (wsel) + assign per_way_rdata = rdata; + end + + assign read_data = per_way_rdata[way_idx]; + + `UNUSED_VAR (stall) + +`ifdef DBG_TRACE_CACHE_DATA + always @(posedge clk) begin + if (fill && ~stall) begin + `TRACE(3, ("%d: %s-bank%0d data-fill: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, fill_data)); + end + if (read && ~stall) begin + `TRACE(3, ("%d: %s-bank%0d data-read: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, read_data, req_uuid)); + end + if (write && ~stall) begin + `TRACE(3, ("%d: %s-bank%0d data-write: addr=0x%0h, way=%b, blk_addr=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, byteen, write_data, req_uuid)); + end + end +`endif + +endmodule diff --git a/hw/rtl/cache/VX_cache_define.vh b/hw/rtl/cache/VX_cache_define.vh index 647ea0be..0bb675fa 100644 --- a/hw/rtl/cache/VX_cache_define.vh +++ b/hw/rtl/cache/VX_cache_define.vh @@ -1,72 +1,65 @@ -`ifndef VX_CACHE_DEFINE -`define VX_CACHE_DEFINE +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. -`include "VX_platform.vh" +`ifndef VX_CACHE_DEFINE_VH +`define VX_CACHE_DEFINE_VH -// cache request identifier -`define DBG_CACHE_REQ_IDW 44 +`include "VX_define.vh" -`define REQS_BITS `LOG2UP(NUM_REQS) +`define CS_REQ_SEL_BITS `CLOG2(NUM_REQS) -`define PORTS_BITS `LOG2UP(NUM_PORTS) +`define CS_WORD_WIDTH (8 * WORD_SIZE) +`define CS_LINE_WIDTH (8 * LINE_SIZE) +`define CS_BANK_SIZE (CACHE_SIZE / NUM_BANKS) +`define CS_WAY_SEL_BITS `CLOG2(NUM_WAYS) -// tag valid tid word_sel -`define MSHR_DATA_WIDTH ((CORE_TAG_WIDTH + 1 + `REQS_BITS + `UP(`WORD_SELECT_BITS)) * NUM_PORTS) +`define CS_LINES_PER_BANK (`CS_BANK_SIZE / (LINE_SIZE * NUM_WAYS)) +`define CS_WORDS_PER_LINE (LINE_SIZE / WORD_SIZE) -`define WORD_WIDTH (8 * WORD_SIZE) - -`define CACHE_LINE_WIDTH (8 * CACHE_LINE_SIZE) - -`define BANK_SIZE (CACHE_SIZE / NUM_BANKS) -`define LINES_PER_BANK (`BANK_SIZE / CACHE_LINE_SIZE) -`define WORDS_PER_LINE (CACHE_LINE_SIZE / WORD_SIZE) - -`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE)) -`define MEM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE)) -`define LINE_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(NUM_BANKS)) +`define CS_WORD_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(WORD_SIZE)) +`define CS_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(LINE_SIZE)) +`define CS_LINE_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH-`CLOG2(NUM_BANKS)) // Word select -`define WORD_SELECT_BITS `CLOG2(`WORDS_PER_LINE) -`define WORD_SELECT_ADDR_START 0 -`define WORD_SELECT_ADDR_END (`WORD_SELECT_ADDR_START+`WORD_SELECT_BITS-1) +`define CS_WORD_SEL_BITS `CLOG2(`CS_WORDS_PER_LINE) +`define CS_WORD_SEL_ADDR_START 0 +`define CS_WORD_SEL_ADDR_END (`CS_WORD_SEL_ADDR_START+`CS_WORD_SEL_BITS-1) // Bank select -`define BANK_SELECT_BITS `CLOG2(NUM_BANKS) -`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END+BANK_ADDR_OFFSET) -`define BANK_SELECT_ADDR_END (`BANK_SELECT_ADDR_START+`BANK_SELECT_BITS-1) +`define CS_BANK_SEL_BITS `CLOG2(NUM_BANKS) +`define CS_BANK_SEL_ADDR_START (1+`CS_WORD_SEL_ADDR_END) +`define CS_BANK_SEL_ADDR_END (`CS_BANK_SEL_ADDR_START+`CS_BANK_SEL_BITS-1) // Line select -`define LINE_SELECT_BITS `CLOG2(`LINES_PER_BANK) -`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END) -`define LINE_SELECT_ADDR_END (`LINE_SELECT_ADDR_START-BANK_ADDR_OFFSET+`LINE_SELECT_BITS-1) +`define CS_LINE_SEL_BITS `CLOG2(`CS_LINES_PER_BANK) +`define CS_LINE_SEL_ADDR_START (1+`CS_BANK_SEL_ADDR_END) +`define CS_LINE_SEL_ADDR_END (`CS_LINE_SEL_ADDR_START+`CS_LINE_SEL_BITS-1) // Tag select -`define TAG_SELECT_BITS (`WORD_ADDR_WIDTH-1-`LINE_SELECT_ADDR_END) -`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END) -`define TAG_SELECT_ADDR_END (`WORD_ADDR_WIDTH-1) +`define CS_TAG_SEL_BITS (`CS_WORD_ADDR_WIDTH-1-`CS_LINE_SEL_ADDR_END) +`define CS_TAG_SEL_ADDR_START (1+`CS_LINE_SEL_ADDR_END) +`define CS_TAG_SEL_ADDR_END (`CS_WORD_ADDR_WIDTH-1) -`define SELECT_BANK_ID(x) x[`BANK_SELECT_ADDR_END : `BANK_SELECT_ADDR_START] -`define SELECT_LINE_ADDR0(x) x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START] -`define SELECT_LINE_ADDRX(x) {x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START], x[`BANK_SELECT_ADDR_START-1 : 1+`WORD_SELECT_ADDR_END]} - -`define LINE_TAG_ADDR(x) x[`LINE_ADDR_WIDTH-1 : `LINE_SELECT_BITS] - -`define CACHE_REQ_ID_RNG CORE_TAG_WIDTH-1 : (CORE_TAG_WIDTH-`DBG_CACHE_REQ_IDW) +`define CS_LINE_TAG_ADDR(x) x[`CS_LINE_ADDR_WIDTH-1 : `CS_LINE_SEL_BITS] /////////////////////////////////////////////////////////////////////////////// -`define CORE_RSP_TAGS ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQS) +`define CS_LINE_TO_MEM_ADDR(x, i) {x, `CS_BANK_SEL_BITS'(i)} +`define CS_MEM_ADDR_TO_BANK_ID(x) x[0 +: `CS_BANK_SEL_BITS] +`define CS_MEM_TAG_TO_REQ_ID(x) x[MSHR_ADDR_WIDTH-1:0] +`define CS_MEM_TAG_TO_BANK_ID(x) x[MSHR_ADDR_WIDTH +: `CS_BANK_SEL_BITS] -`define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)} +`define CS_LINE_TO_FULL_ADDR(x, i) {x, (`XLEN-$bits(x))'(i << (`XLEN-$bits(x)-`CS_BANK_SEL_BITS))} +`define CS_MEM_TO_FULL_ADDR(x) {x, (`XLEN-$bits(x))'(0)} -`define MEM_ADDR_TO_BANK_ID(x) x[0 +: `BANK_SELECT_BITS] - -`define MEM_TAG_TO_REQ_ID(x) x[MSHR_ADDR_WIDTH-1:0] - -`define MEM_TAG_TO_BANK_ID(x) x[MSHR_ADDR_WIDTH +: `BANK_SELECT_BITS] - -`define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))} - -`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)} - -`endif \ No newline at end of file +`endif // VX_CACHE_DEFINE_VH diff --git a/hw/rtl/cache/VX_cache_init.sv b/hw/rtl/cache/VX_cache_init.sv new file mode 100644 index 00000000..7aa4b3ae --- /dev/null +++ b/hw/rtl/cache/VX_cache_init.sv @@ -0,0 +1,51 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_init #( + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1 +) ( + input wire clk, + input wire reset, + output wire [`CS_LINE_SEL_BITS-1:0] addr_out, + output wire valid_out +); + reg enabled; + reg [`CS_LINE_SEL_BITS-1:0] line_ctr; + + always @(posedge clk) begin + if (reset) begin + enabled <= 1; + line_ctr <= '0; + end else begin + if (enabled) begin + if (line_ctr == ((2 ** `CS_LINE_SEL_BITS)-1)) begin + enabled <= 0; + end + line_ctr <= line_ctr + `CS_LINE_SEL_BITS'(1); + end + end + end + + assign addr_out = line_ctr; + assign valid_out = enabled; + +endmodule diff --git a/hw/rtl/cache/VX_cache_mshr.sv b/hw/rtl/cache/VX_cache_mshr.sv new file mode 100644 index 00000000..fa6d4147 --- /dev/null +++ b/hw/rtl/cache/VX_cache_mshr.sv @@ -0,0 +1,271 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +// this is an implementation of a pipelined multi-banked cache +// we allocate a free slot from the MSHR before processing a core request +// and release the slot when we get a cache hit. +// during a memory fill response we initiate the replay sequence +// and dequeue all associated pending entries. + +// Warning: This MSHR implementation is strongly coupled with the bank pipeline +// and as such changes to either module requires careful evaluation. +// This implementation makes the following assumptions: +// (1) two-cycle pipeline: st0 and st1. +// (2) core request flow: st0: allocate / lookup, st1: finalize. +// (3) the first dequeue after the fill should happen in st0, when the fill is in st1 +// this is enforced inside the bank by "rdw_hazard_st0". + +module VX_cache_mshr #( + parameter `STRING INSTANCE_ID= "", + parameter BANK_ID = 0, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 4, + // Request debug identifier + parameter UUID_WIDTH = 0, + // MSHR parameters + parameter DATA_WIDTH = 1, + parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE) +) ( + input wire clk, + input wire reset, + +`IGNORE_UNUSED_BEGIN + input wire[`UP(UUID_WIDTH)-1:0] deq_req_uuid, + input wire[`UP(UUID_WIDTH)-1:0] lkp_req_uuid, + input wire[`UP(UUID_WIDTH)-1:0] fin_req_uuid, +`IGNORE_UNUSED_END + + // allocate + input wire allocate_valid, + input wire [`CS_LINE_ADDR_WIDTH-1:0] allocate_addr, + input wire allocate_rw, + input wire [DATA_WIDTH-1:0] allocate_data, + output wire [MSHR_ADDR_WIDTH-1:0] allocate_id, + output wire [MSHR_ADDR_WIDTH-1:0] allocate_tail, + output wire allocate_ready, + + // lookup + input wire lookup_valid, + input wire [`CS_LINE_ADDR_WIDTH-1:0] lookup_addr, + output wire [MSHR_SIZE-1:0] lookup_matches, + + // memory fill + input wire fill_valid, + input wire [MSHR_ADDR_WIDTH-1:0] fill_id, + output wire [`CS_LINE_ADDR_WIDTH-1:0] fill_addr, + + // dequeue + output wire dequeue_valid, + output wire [`CS_LINE_ADDR_WIDTH-1:0] dequeue_addr, + output wire dequeue_rw, + output wire [DATA_WIDTH-1:0] dequeue_data, + output wire [MSHR_ADDR_WIDTH-1:0] dequeue_id, + input wire dequeue_ready, + + // finalize + input wire finalize_valid, + input wire finalize_release, + input wire finalize_pending, + input wire [MSHR_ADDR_WIDTH-1:0] finalize_id, + input wire [MSHR_ADDR_WIDTH-1:0] finalize_tail +); + `UNUSED_PARAM (BANK_ID) + + reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0]; + reg [MSHR_ADDR_WIDTH-1:0] next_index [MSHR_SIZE-1:0]; + + reg [MSHR_SIZE-1:0] valid_table, valid_table_n; + reg [MSHR_SIZE-1:0] next_table, next_table_x, next_table_n; + reg [MSHR_SIZE-1:0] write_table; + + reg allocate_rdy, allocate_rdy_n; + reg [MSHR_ADDR_WIDTH-1:0] allocate_id_r, allocate_id_n; + + reg dequeue_val, dequeue_val_n; + reg [MSHR_ADDR_WIDTH-1:0] dequeue_id_r, dequeue_id_n; + + wire [MSHR_ADDR_WIDTH-1:0] tail_idx; + + wire allocate_fire = allocate_valid && allocate_ready; + wire dequeue_fire = dequeue_valid && dequeue_ready; + + wire [MSHR_SIZE-1:0] addr_matches; + for (genvar i = 0; i < MSHR_SIZE; ++i) begin + assign addr_matches[i] = valid_table[i] && (addr_table[i] == lookup_addr); + end + + VX_lzc #( + .N (MSHR_SIZE), + .REVERSE (1) + ) allocate_sel ( + .data_in (~valid_table_n), + .data_out (allocate_id_n), + .valid_out (allocate_rdy_n) + ); + + VX_onehot_encoder #( + .N (MSHR_SIZE) + ) tail_sel ( + .data_in (addr_matches & ~next_table_x), + .data_out (tail_idx), + `UNUSED_PIN (valid_out) + ); + + always @(*) begin + valid_table_n = valid_table; + next_table_x = next_table; + dequeue_val_n = dequeue_val; + dequeue_id_n = dequeue_id; + + if (fill_valid) begin + dequeue_val_n = 1; + dequeue_id_n = fill_id; + end + + if (dequeue_fire) begin + valid_table_n[dequeue_id] = 0; + if (next_table[dequeue_id]) begin + dequeue_id_n = next_index[dequeue_id]; + end else begin + dequeue_val_n = 0; + end + end + + if (finalize_valid) begin + if (finalize_release) begin + valid_table_n[finalize_id] = 0; + end + if (finalize_pending) begin + next_table_x[finalize_tail] = 1; + end + end + + next_table_n = next_table_x; + if (allocate_fire) begin + valid_table_n[allocate_id] = 1; + next_table_n[allocate_id] = 0; + end + end + + always @(posedge clk) begin + if (reset) begin + valid_table <= '0; + allocate_rdy <= 0; + dequeue_val <= 0; + end else begin + valid_table <= valid_table_n; + allocate_rdy <= allocate_rdy_n; + dequeue_val <= dequeue_val_n; + end + + if (allocate_fire) begin + addr_table[allocate_id] <= allocate_addr; + write_table[allocate_id] <= allocate_rw; + end + + if (finalize_valid && finalize_pending) begin + next_index[finalize_tail] <= finalize_id; + end + + dequeue_id_r <= dequeue_id_n; + allocate_id_r <= allocate_id_n; + next_table <= next_table_n; + end + + `RUNTIME_ASSERT((~allocate_fire || ~valid_table[allocate_id_r]), ("%t: *** %s-bank%0d inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID, + `CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_id_r, lkp_req_uuid)) + + `RUNTIME_ASSERT((~finalize_valid || valid_table[finalize_id]), ("%t: *** %s-bank%0d invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID, + `CS_LINE_TO_FULL_ADDR(addr_table[finalize_id], BANK_ID), finalize_id, fin_req_uuid)) + + `RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s-bank%0d invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID, BANK_ID, + `CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), fill_id)) + + VX_dp_ram #( + .DATAW (DATA_WIDTH), + .SIZE (MSHR_SIZE), + .LUTRAM (1) + ) entries ( + .clk (clk), + .read (1'b1), + .write (allocate_valid), + `UNUSED_PIN (wren), + .waddr (allocate_id_r), + .wdata (allocate_data), + .raddr (dequeue_id_r), + .rdata (dequeue_data) + ); + + assign fill_addr = addr_table[fill_id]; + + assign allocate_ready = allocate_rdy; + assign allocate_id = allocate_id_r; + assign allocate_tail = tail_idx; + + assign dequeue_valid = dequeue_val; + assign dequeue_addr = addr_table[dequeue_id_r]; + assign dequeue_rw = write_table[dequeue_id_r]; + assign dequeue_id = dequeue_id_r; + + assign lookup_matches = addr_matches & ~write_table; + + `UNUSED_VAR (lookup_valid) + +`ifdef DBG_TRACE_CACHE_MSHR + reg show_table; + always @(posedge clk) begin + if (reset) begin + show_table <= 0; + end else begin + show_table <= allocate_fire || lookup_valid || finalize_valid || fill_valid || dequeue_fire; + end + if (allocate_fire) + `TRACE(3, ("%d: %s-bank%0d mshr-allocate: addr=0x%0h, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + `CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_tail, allocate_id, lkp_req_uuid)); + if (lookup_valid) + `TRACE(3, ("%d: %s-bank%0d mshr-lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + `CS_LINE_TO_FULL_ADDR(lookup_addr, BANK_ID), lookup_matches, lkp_req_uuid)); + if (finalize_valid) + `TRACE(3, ("%d: %s-bank%0d mshr-finalize release=%b, pending=%b, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + finalize_release, finalize_pending, finalize_tail, finalize_id, fin_req_uuid)); + if (fill_valid) + `TRACE(3, ("%d: %s-bank%0d mshr-fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INSTANCE_ID, BANK_ID, + `CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), `CS_LINE_TO_FULL_ADDR(fill_addr, BANK_ID), fill_id)); + if (dequeue_fire) + `TRACE(3, ("%d: %s-bank%0d mshr-dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, + `CS_LINE_TO_FULL_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_uuid)); + if (show_table) begin + `TRACE(3, ("%d: %s-bank%0d mshr-table", $time, INSTANCE_ID, BANK_ID)); + for (integer i = 0; i < MSHR_SIZE; ++i) begin + if (valid_table[i]) begin + `TRACE(3, (" %0d=0x%0h", i, `CS_LINE_TO_FULL_ADDR(addr_table[i], BANK_ID))); + if (write_table[i]) + `TRACE(3, ("(w)")); + else + `TRACE(3, ("(r)")); + if (next_table[i]) + `TRACE(3, ("->%0d", next_index[i])); + end + end + `TRACE(3, ("\n")); + end + end +`endif + +endmodule diff --git a/hw/rtl/interfaces/VX_perf_cache_if.sv b/hw/rtl/cache/VX_cache_perf_if.sv similarity index 58% rename from hw/rtl/interfaces/VX_perf_cache_if.sv rename to hw/rtl/cache/VX_cache_perf_if.sv index 0ec8d582..6e68b1b3 100644 --- a/hw/rtl/interfaces/VX_perf_cache_if.sv +++ b/hw/rtl/cache/VX_cache_perf_if.sv @@ -1,9 +1,19 @@ -`ifndef VX_PERF_CACHE_IF -`define VX_PERF_CACHE_IF +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. `include "VX_define.vh" -interface VX_perf_cache_if (); +interface VX_cache_perf_if (); wire [`PERF_CTR_BITS-1:0] reads; wire [`PERF_CTR_BITS-1:0] writes; @@ -37,5 +47,3 @@ interface VX_perf_cache_if (); ); endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache_tags.sv b/hw/rtl/cache/VX_cache_tags.sv new file mode 100644 index 00000000..dac0b6de --- /dev/null +++ b/hw/rtl/cache/VX_cache_tags.sv @@ -0,0 +1,116 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_tags #( + parameter `STRING INSTANCE_ID = "", + parameter BANK_ID = 0, + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // Request debug identifier + parameter UUID_WIDTH = 0 +) ( + input wire clk, + input wire reset, + +`IGNORE_UNUSED_BEGIN + input wire [`UP(UUID_WIDTH)-1:0] req_uuid, +`IGNORE_UNUSED_END + + input wire stall, + + // read/fill + input wire lookup, + input wire [`CS_LINE_ADDR_WIDTH-1:0] line_addr, + input wire fill, + input wire init, + output wire [NUM_WAYS-1:0] way_sel, + output wire [NUM_WAYS-1:0] tag_matches +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (BANK_ID) + `UNUSED_VAR (reset) + `UNUSED_VAR (lookup) + + localparam TAG_WIDTH = 1 + `CS_TAG_SEL_BITS; + + wire [`CS_LINE_SEL_BITS-1:0] line_sel = line_addr[`CS_LINE_SEL_BITS-1:0]; + wire [`CS_TAG_SEL_BITS-1:0] line_tag = `CS_LINE_TAG_ADDR(line_addr); + + if (NUM_WAYS > 1) begin + reg [NUM_WAYS-1:0] repl_way; + // cyclic assignment of replacement way + always @(posedge clk) begin + if (reset) begin + repl_way <= 1; + end else if (~stall) begin // hold the value on stalls prevent filling different slots twice + repl_way <= {repl_way[NUM_WAYS-2:0], repl_way[NUM_WAYS-1]}; + end + end + for (genvar i = 0; i < NUM_WAYS; ++i) begin + assign way_sel[i] = fill && repl_way[i]; + end + end else begin + `UNUSED_VAR (stall) + assign way_sel = fill; + end + + for (genvar i = 0; i < NUM_WAYS; ++i) begin + wire [`CS_TAG_SEL_BITS-1:0] read_tag; + wire read_valid; + + VX_sp_ram #( + .DATAW (TAG_WIDTH), + .SIZE (`CS_LINES_PER_BANK), + .NO_RWCHECK (1) + ) tag_store ( + .clk (clk), + .read (1'b1), + .write (way_sel[i] || init), + `UNUSED_PIN (wren), + .addr (line_sel), + .wdata ({~init, line_tag}), + .rdata ({read_valid, read_tag}) + ); + + assign tag_matches[i] = read_valid && (line_tag == read_tag); + end + +`ifdef DBG_TRACE_CACHE_TAG + always @(posedge clk) begin + if (fill && ~stall) begin + `TRACE(3, ("%d: %s-bank%0d tag-fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag)); + end + if (init) begin + `TRACE(3, ("%d: %s-bank%0d tag-init: addr=0x%0h, blk_addr=%0d\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel)); + end + if (lookup && ~stall) begin + if (tag_matches != 0) begin + `TRACE(3, ("%d: %s-bank%0d tag-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag, req_uuid)); + end else begin + `TRACE(3, ("%d: %s-bank%0d tag-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid)); + end + end + end +`endif + +endmodule diff --git a/hw/rtl/cache/VX_cache_wrap.sv b/hw/rtl/cache/VX_cache_wrap.sv new file mode 100644 index 00000000..22ab57ae --- /dev/null +++ b/hw/rtl/cache/VX_cache_wrap.sv @@ -0,0 +1,501 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_wrap #( + parameter `STRING INSTANCE_ID = "", + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + + // Size of cache in bytes + parameter CACHE_SIZE = 4096, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 4, + + // Core Response Queue Size + parameter CRSQ_SIZE = 2, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 8, + // Memory Response Queue Size + parameter MRSQ_SIZE = 0, + // Memory Request Queue Size + parameter MREQ_SIZE = 4, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Request debug identifier + parameter UUID_WIDTH = 0, + + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + + // enable bypass for non-cacheable addresses + parameter NC_TAG_BIT = 0, + parameter NC_ENABLE = 0, + + // Force bypass for all requests + parameter PASSTHRU = 0, + + // Core response output register + parameter CORE_OUT_REG = 0, + + // Memory request output register + parameter MEM_OUT_REG = 0 + ) ( + + input wire clk, + input wire reset, + + // PERF +`ifdef PERF_ENABLE + VX_cache_perf_if.master cache_perf_if, +`endif + + VX_mem_bus_if.slave core_bus_if [NUM_REQS], + VX_mem_bus_if.master mem_bus_if +); + + `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter")) + `STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter")) + + localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE); + localparam CORE_TAG_X_WIDTH = TAG_WIDTH - NC_ENABLE; + localparam MEM_TAG_X_WIDTH = MSHR_ADDR_WIDTH + `CS_BANK_SEL_BITS; + localparam MEM_TAG_WIDTH = PASSTHRU ? (NC_ENABLE ? `CACHE_NC_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH) : + `CACHE_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH)) : + (NC_ENABLE ? `CACHE_NC_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH) : + `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS)); + + localparam NC_BYPASS = (NC_ENABLE || PASSTHRU); + localparam DIRECT_PASSTHRU = PASSTHRU && (`CS_WORD_SEL_BITS == 0) && (NUM_REQS == 1); + + wire [NUM_REQS-1:0] core_req_valid; + wire [NUM_REQS-1:0] core_req_rw; + wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr; + wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data; + wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_req_tag; + wire [NUM_REQS-1:0] core_req_ready; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_req_valid[i] = core_bus_if[i].req_valid; + assign core_req_rw[i] = core_bus_if[i].req_data.rw; + assign core_req_addr[i] = core_bus_if[i].req_data.addr; + assign core_req_byteen[i] = core_bus_if[i].req_data.byteen; + assign core_req_data[i] = core_bus_if[i].req_data.data; + assign core_req_tag[i] = core_bus_if[i].req_data.tag; + assign core_bus_if[i].req_ready = core_req_ready[i]; + end + + /////////////////////////////////////////////////////////////////////////// + + // Core response buffering + wire [NUM_REQS-1:0] core_rsp_valid_s; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_s; + wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s; + wire [NUM_REQS-1:0] core_rsp_ready_s; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + + `RESET_RELAY (core_rsp_reset, reset); + + VX_elastic_buffer #( + .DATAW (`CS_WORD_WIDTH + TAG_WIDTH), + .SIZE ((NC_BYPASS && !DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0), + .OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG)) + ) core_rsp_buf ( + .clk (clk), + .reset (core_rsp_reset), + .valid_in (core_rsp_valid_s[i]), + .ready_in (core_rsp_ready_s[i]), + .data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}), + .data_out ({core_bus_if[i].rsp_data.data, core_bus_if[i].rsp_data.tag}), + .valid_out (core_bus_if[i].rsp_valid), + .ready_out (core_bus_if[i].rsp_ready) + ); + end + + /////////////////////////////////////////////////////////////////////////// + + // Memory request buffering + wire mem_req_valid_s; + wire mem_req_rw_s; + wire [LINE_SIZE-1:0] mem_req_byteen_s; + wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_s; + wire [`CS_LINE_WIDTH-1:0] mem_req_data_s; + wire [MEM_TAG_WIDTH-1:0] mem_req_tag_s; + wire mem_req_ready_s; + + VX_elastic_buffer #( + .DATAW (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH), + .SIZE ((NC_BYPASS && !DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0), + .OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG)) + ) mem_req_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_valid_s), + .ready_in (mem_req_ready_s), + .data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}), + .data_out ({mem_bus_if.req_data.rw, mem_bus_if.req_data.byteen, mem_bus_if.req_data.addr, mem_bus_if.req_data.data, mem_bus_if.req_data.tag}), + .valid_out (mem_bus_if.req_valid), + .ready_out (mem_bus_if.req_ready) + ); + + /////////////////////////////////////////////////////////////////////////// + + // Core request + wire [NUM_REQS-1:0] core_req_valid_b; + wire [NUM_REQS-1:0] core_req_rw_b; + wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr_b; + wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen_b; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data_b; + wire [NUM_REQS-1:0][CORE_TAG_X_WIDTH-1:0] core_req_tag_b; + wire [NUM_REQS-1:0] core_req_ready_b; + + // Core response + wire [NUM_REQS-1:0] core_rsp_valid_b; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_b; + wire [NUM_REQS-1:0][CORE_TAG_X_WIDTH-1:0] core_rsp_tag_b; + wire [NUM_REQS-1:0] core_rsp_ready_b; + + // Memory request + wire mem_req_valid_b; + wire mem_req_rw_b; + wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_b; + wire [LINE_SIZE-1:0] mem_req_byteen_b; + wire [`CS_LINE_WIDTH-1:0] mem_req_data_b; + wire [MEM_TAG_X_WIDTH-1:0] mem_req_tag_b; + wire mem_req_ready_b; + + // Memory response + wire mem_rsp_valid_b; + wire [`CS_LINE_WIDTH-1:0] mem_rsp_data_b; + wire [MEM_TAG_X_WIDTH-1:0] mem_rsp_tag_b; + wire mem_rsp_ready_b; + + if (NC_BYPASS) begin + + `RESET_RELAY (nc_bypass_reset, reset); + + VX_cache_bypass #( + .NUM_REQS (NUM_REQS), + .NC_TAG_BIT (NC_TAG_BIT), + + .NC_ENABLE (NC_ENABLE), + .PASSTHRU (PASSTHRU), + + .CORE_ADDR_WIDTH (`CS_WORD_ADDR_WIDTH), + .CORE_DATA_SIZE (WORD_SIZE), + .CORE_TAG_IN_WIDTH (TAG_WIDTH), + + .MEM_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH), + .MEM_DATA_SIZE (LINE_SIZE), + .MEM_TAG_IN_WIDTH (MEM_TAG_X_WIDTH), + .MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH), + + .UUID_WIDTH (UUID_WIDTH) + ) cache_bypass ( + .clk (clk), + .reset (nc_bypass_reset), + + // Core request in + .core_req_valid_in (core_req_valid), + .core_req_rw_in (core_req_rw), + .core_req_byteen_in (core_req_byteen), + .core_req_addr_in (core_req_addr), + .core_req_data_in (core_req_data), + .core_req_tag_in (core_req_tag), + .core_req_ready_in (core_req_ready), + + // Core request out + .core_req_valid_out (core_req_valid_b), + .core_req_rw_out (core_req_rw_b), + .core_req_byteen_out(core_req_byteen_b), + .core_req_addr_out (core_req_addr_b), + .core_req_data_out (core_req_data_b), + .core_req_tag_out (core_req_tag_b), + .core_req_ready_out (core_req_ready_b), + + // Core response in + .core_rsp_valid_in (core_rsp_valid_b), + .core_rsp_data_in (core_rsp_data_b), + .core_rsp_tag_in (core_rsp_tag_b), + .core_rsp_ready_in (core_rsp_ready_b), + + // Core response out + .core_rsp_valid_out (core_rsp_valid_s), + .core_rsp_data_out (core_rsp_data_s), + .core_rsp_tag_out (core_rsp_tag_s), + .core_rsp_ready_out (core_rsp_ready_s), + + // Memory request in + .mem_req_valid_in (mem_req_valid_b), + .mem_req_rw_in (mem_req_rw_b), + .mem_req_addr_in (mem_req_addr_b), + .mem_req_byteen_in (mem_req_byteen_b), + .mem_req_data_in (mem_req_data_b), + .mem_req_tag_in (mem_req_tag_b), + .mem_req_ready_in (mem_req_ready_b), + + // Memory request out + .mem_req_valid_out (mem_req_valid_s), + .mem_req_addr_out (mem_req_addr_s), + .mem_req_rw_out (mem_req_rw_s), + .mem_req_byteen_out (mem_req_byteen_s), + .mem_req_data_out (mem_req_data_s), + .mem_req_tag_out (mem_req_tag_s), + .mem_req_ready_out (mem_req_ready_s), + + // Memory response in + .mem_rsp_valid_in (mem_bus_if.rsp_valid), + .mem_rsp_data_in (mem_bus_if.rsp_data.data), + .mem_rsp_tag_in (mem_bus_if.rsp_data.tag), + .mem_rsp_ready_in (mem_bus_if.rsp_ready), + + // Memory response out + .mem_rsp_valid_out (mem_rsp_valid_b), + .mem_rsp_data_out (mem_rsp_data_b), + .mem_rsp_tag_out (mem_rsp_tag_b), + .mem_rsp_ready_out (mem_rsp_ready_b) + ); + end else begin + assign core_req_valid_b = core_req_valid; + assign core_req_rw_b = core_req_rw; + assign core_req_addr_b = core_req_addr; + assign core_req_byteen_b= core_req_byteen; + assign core_req_data_b = core_req_data; + assign core_req_tag_b = core_req_tag; + assign core_req_ready = core_req_ready_b; + + assign core_rsp_valid_s = core_rsp_valid_b; + assign core_rsp_data_s = core_rsp_data_b; + assign core_rsp_tag_s = core_rsp_tag_b; + assign core_rsp_ready_b = core_rsp_ready_s; + + assign mem_req_valid_s = mem_req_valid_b; + assign mem_req_addr_s = mem_req_addr_b; + assign mem_req_rw_s = mem_req_rw_b; + assign mem_req_byteen_s = mem_req_byteen_b; + assign mem_req_data_s = mem_req_data_b; + assign mem_req_ready_b = mem_req_ready_s; + + // Add explicit NC=0 flag to the memory request tag + + VX_bits_insert #( + .N (MEM_TAG_WIDTH-1), + .POS (NC_TAG_BIT) + ) mem_req_tag_insert ( + .data_in (mem_req_tag_b), + .sel_in (1'b0), + .data_out (mem_req_tag_s) + ); + + assign mem_rsp_valid_b = mem_bus_if.rsp_valid; + assign mem_rsp_data_b = mem_bus_if.rsp_data.data; + assign mem_bus_if.rsp_ready = mem_rsp_ready_b; + + // Remove NC flag from the memory response tag + + VX_bits_remove #( + .N (MEM_TAG_WIDTH), + .POS (NC_TAG_BIT) + ) mem_rsp_tag_remove ( + .data_in (mem_bus_if.rsp_data.tag), + .data_out (mem_rsp_tag_b) + ); + end + + if (PASSTHRU != 0) begin + + `UNUSED_VAR (core_req_valid_b) + `UNUSED_VAR (core_req_rw_b) + `UNUSED_VAR (core_req_addr_b) + `UNUSED_VAR (core_req_byteen_b) + `UNUSED_VAR (core_req_data_b) + `UNUSED_VAR (core_req_tag_b) + assign core_req_ready_b = '0; + + assign core_rsp_valid_b = '0; + assign core_rsp_data_b = '0; + assign core_rsp_tag_b = '0; + `UNUSED_VAR (core_rsp_ready_b) + + assign mem_req_valid_b = 0; + assign mem_req_addr_b = '0; + assign mem_req_rw_b = '0; + assign mem_req_byteen_b = '0; + assign mem_req_data_b = '0; + assign mem_req_tag_b = '0; + `UNUSED_VAR (mem_req_ready_b) + + `UNUSED_VAR (mem_rsp_valid_b) + `UNUSED_VAR (mem_rsp_data_b) + `UNUSED_VAR (mem_rsp_tag_b) + assign mem_rsp_ready_b = 0; + + `ifdef PERF_ENABLE + assign cache_perf_if.reads = '0; + assign cache_perf_if.writes = '0; + assign cache_perf_if.read_misses = '0; + assign cache_perf_if.write_misses = '0; + assign cache_perf_if.bank_stalls = '0; + assign cache_perf_if.mshr_stalls = '0; + assign cache_perf_if.mem_stalls = '0; + assign cache_perf_if.crsp_stalls = '0; + `endif + + end else begin + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (CORE_TAG_X_WIDTH) + ) core_bus_wrap_if[NUM_REQS](); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_X_WIDTH) + ) mem_bus_wrap_if(); + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_bus_wrap_if[i].req_valid = core_req_valid_b[i]; + assign core_bus_wrap_if[i].req_data.rw = core_req_rw_b[i]; + assign core_bus_wrap_if[i].req_data.addr = core_req_addr_b[i]; + assign core_bus_wrap_if[i].req_data.byteen = core_req_byteen_b[i]; + assign core_bus_wrap_if[i].req_data.data = core_req_data_b[i]; + assign core_bus_wrap_if[i].req_data.tag = core_req_tag_b[i]; + assign core_req_ready_b[i] = core_bus_wrap_if[i].req_ready; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_rsp_valid_b[i] = core_bus_wrap_if[i].rsp_valid; + assign core_rsp_data_b[i] = core_bus_wrap_if[i].rsp_data.data; + assign core_rsp_tag_b[i] = core_bus_wrap_if[i].rsp_data.tag; + assign core_bus_wrap_if[i].rsp_ready = core_rsp_ready_b[i]; + end + + assign mem_req_valid_b = mem_bus_wrap_if.req_valid; + assign mem_req_addr_b = mem_bus_wrap_if.req_data.addr; + assign mem_req_rw_b = mem_bus_wrap_if.req_data.rw; + assign mem_req_byteen_b = mem_bus_wrap_if.req_data.byteen; + assign mem_req_data_b = mem_bus_wrap_if.req_data.data; + assign mem_req_tag_b = mem_bus_wrap_if.req_data.tag; + assign mem_bus_wrap_if.req_ready = mem_req_ready_b; + + assign mem_bus_wrap_if.rsp_valid = mem_rsp_valid_b; + assign mem_bus_wrap_if.rsp_data.data = mem_rsp_data_b; + assign mem_bus_wrap_if.rsp_data.tag = mem_rsp_tag_b; + assign mem_rsp_ready_b = mem_bus_wrap_if.rsp_ready; + + `RESET_RELAY (cache_reset, reset); + + VX_cache #( + .INSTANCE_ID (INSTANCE_ID), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MRSQ_SIZE (MRSQ_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .WRITE_ENABLE (WRITE_ENABLE), + .UUID_WIDTH (UUID_WIDTH), + .TAG_WIDTH (CORE_TAG_X_WIDTH), + .CORE_OUT_REG (NC_BYPASS ? 1 : CORE_OUT_REG), + .MEM_OUT_REG (NC_BYPASS ? 1 : MEM_OUT_REG) + ) cache ( + .clk (clk), + .reset (cache_reset), + + `ifdef PERF_ENABLE + .cache_perf_if (cache_perf_if), + `endif + + .core_bus_if (core_bus_wrap_if), + .mem_bus_if (mem_bus_wrap_if) + ); + + end + +`ifdef DBG_TRACE_CACHE_BANK + + for (genvar i = 0; i < NUM_REQS; ++i) begin + wire [`UP(UUID_WIDTH)-1:0] core_req_uuid; + wire [`UP(UUID_WIDTH)-1:0] core_rsp_uuid; + + if (UUID_WIDTH != 0) begin + assign core_req_uuid = core_bus_if[i].req_data.tag[TAG_WIDTH-1 -: UUID_WIDTH]; + assign core_rsp_uuid = core_bus_if[i].rsp_data.tag[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin + assign core_req_uuid = 0; + assign core_rsp_uuid = 0; + end + + wire core_req_fire = core_bus_if[i].req_valid && core_bus_if[i].req_ready; + wire core_rsp_fire = core_bus_if[i].rsp_valid && core_bus_if[i].rsp_ready; + + always @(posedge clk) begin + if (core_req_fire) begin + if (core_bus_if[i].req_data.rw) + `TRACE(1, ("%d: %s core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_bus_if[i].req_data.byteen, core_bus_if[i].req_data.data, core_req_uuid)); + else + `TRACE(1, ("%d: %s core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_req_uuid)); + end + if (core_rsp_fire) begin + `TRACE(1, ("%d: %s core-rd-rsp: tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, core_bus_if[i].rsp_data.tag, i, core_bus_if[i].rsp_data.data, core_rsp_uuid)); + end + end + end + + wire [`UP(UUID_WIDTH)-1:0] mem_req_uuid; + wire [`UP(UUID_WIDTH)-1:0] mem_rsp_uuid; + + if ((UUID_WIDTH != 0) && (NC_BYPASS != 0)) begin + assign mem_req_uuid = mem_bus_if.req_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH]; + assign mem_rsp_uuid = mem_bus_if.rsp_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin + assign mem_req_uuid = 0; + assign mem_rsp_uuid = 0; + end + + wire mem_req_fire = mem_bus_if.req_valid && mem_bus_if.req_ready; + wire mem_rsp_fire = mem_bus_if.rsp_valid && mem_bus_if.rsp_ready; + + always @(posedge clk) begin + if (mem_req_fire) begin + if (mem_bus_if.req_data.rw) + `TRACE(1, ("%d: %s mem-wr-req: addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", + $time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_bus_if.req_data.byteen, mem_bus_if.req_data.data, mem_req_uuid)); + else + `TRACE(1, ("%d: %s mem-rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_req_uuid)); + end + if (mem_rsp_fire) begin + `TRACE(1, ("%d: %s mem-rd-rsp: tag=0x%0h, data=0x%0h (#%0d)\n", + $time, INSTANCE_ID, mem_bus_if.rsp_data.tag, mem_bus_if.rsp_data.data, mem_rsp_uuid)); + end + end +`endif + +endmodule diff --git a/hw/rtl/cache/VX_core_req_bank_sel.sv b/hw/rtl/cache/VX_core_req_bank_sel.sv deleted file mode 100644 index 0e5f3393..00000000 --- a/hw/rtl/cache/VX_core_req_bank_sel.sv +++ /dev/null @@ -1,314 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_core_req_bank_sel #( - parameter CACHE_ID = 0, - - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 64, - // Size of a word in bytes - parameter WORD_SIZE = 4, - // Number of banks - parameter NUM_BANKS = 4, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Number of Word requests per cycle - parameter NUM_REQS = 4, - // core request tag size - parameter CORE_TAG_WIDTH = 3, - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0 -) ( - input wire clk, - input wire reset, - -`ifdef PERF_ENABLE - output wire [`PERF_CTR_BITS-1:0] bank_stalls, -`endif - - input wire [NUM_REQS-1:0] core_req_valid, - input wire [NUM_REQS-1:0] core_req_rw, - input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr, - input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen, - input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data, - input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag, - output wire [NUM_REQS-1:0] core_req_ready, - - output wire [NUM_BANKS-1:0] per_bank_core_req_valid, - output wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask, - output wire [NUM_BANKS-1:0] per_bank_core_req_rw, - output wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr, - output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel, - output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen, - output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data, - output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid, - output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag, - input wire [NUM_BANKS-1:0] per_bank_core_req_ready -); - `UNUSED_PARAM (CACHE_ID) - `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) - `STATIC_ASSERT(NUM_PORTS <= NUM_BANKS, ("invalid value")) - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - wire [NUM_REQS-1:0][`LINE_ADDR_WIDTH-1:0] core_req_line_addr; - wire [NUM_REQS-1:0][`UP(`WORD_SELECT_BITS)-1:0] core_req_wsel; - wire [NUM_REQS-1:0][`UP(`BANK_SELECT_BITS)-1:0] core_req_bid; - - for (genvar i = 0; i < NUM_REQS; i++) begin - if (BANK_ADDR_OFFSET == 0) begin - assign core_req_line_addr[i] = `SELECT_LINE_ADDR0(core_req_addr[i]); - end else begin - assign core_req_line_addr[i] = `SELECT_LINE_ADDRX(core_req_addr[i]); - end - assign core_req_wsel[i] = core_req_addr[i][`UP(`WORD_SELECT_BITS)-1:0]; - end - - for (genvar i = 0; i < NUM_REQS; ++i) begin - if (NUM_BANKS > 1) begin - assign core_req_bid[i] = `SELECT_BANK_ID(core_req_addr[i]); - end else begin - assign core_req_bid[i] = 0; - end - end - - reg [NUM_BANKS-1:0] per_bank_core_req_valid_r; - reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask_r; - reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel_r; - reg [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_r; - reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_r; - reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_r; - reg [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r; - reg [NUM_BANKS-1:0] per_bank_core_req_rw_r; - reg [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_r; - reg [NUM_REQS-1:0] core_req_ready_r; - - if (NUM_REQS > 1) begin - - if (NUM_PORTS > 1) begin - - reg [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_line_addr_r; - reg [NUM_BANKS-1:0] per_bank_rw_r; - wire [NUM_REQS-1:0] core_req_line_match; - - always @(*) begin - per_bank_line_addr_r = 'x; - per_bank_rw_r = 'x; - for (integer i = NUM_REQS-1; i >= 0; --i) begin - if (core_req_valid[i]) begin - per_bank_line_addr_r[core_req_bid[i]] = core_req_line_addr[i]; - per_bank_rw_r[core_req_bid[i]] = core_req_rw[i]; - end - end - end - - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_req_line_match[i] = (core_req_line_addr[i] == per_bank_line_addr_r[core_req_bid[i]]) - && (core_req_rw[i] == per_bank_rw_r[core_req_bid[i]]); - end - - if (NUM_PORTS < NUM_REQS) begin - - reg [NUM_BANKS-1:0][NUM_PORTS-1:0][NUM_REQS-1:0] req_select_table_r; - - always @(*) begin - per_bank_core_req_valid_r = 0; - per_bank_core_req_pmask_r = 0; - per_bank_core_req_rw_r = 'x; - per_bank_core_req_addr_r = 'x; - per_bank_core_req_wsel_r = 'x; - per_bank_core_req_byteen_r= 'x; - per_bank_core_req_data_r = 'x; - per_bank_core_req_tag_r = 'x; - per_bank_core_req_tid_r = 'x; - req_select_table_r = 'x; - - for (integer i = NUM_REQS-1; i >= 0; --i) begin - if (core_req_valid[i]) begin - per_bank_core_req_valid_r[core_req_bid[i]] = 1; - per_bank_core_req_pmask_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i]; - per_bank_core_req_wsel_r[core_req_bid[i]][i % NUM_PORTS] = core_req_wsel[i]; - per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i]; - per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i]; - per_bank_core_req_tid_r[core_req_bid[i]][i % NUM_PORTS] = `REQS_BITS'(i); - per_bank_core_req_tag_r[core_req_bid[i]][i % NUM_PORTS] = core_req_tag[i]; - per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i]; - per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i]; - req_select_table_r[core_req_bid[i]][i % NUM_PORTS] = (1 << i); - end - end - end - - always @(*) begin - for (integer i = 0; i < NUM_REQS; ++i) begin - core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] - && core_req_line_match[i] - && req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]; - end - end - - end else begin - - always @(*) begin - per_bank_core_req_valid_r = 0; - per_bank_core_req_pmask_r = 0; - per_bank_core_req_rw_r = 'x; - per_bank_core_req_addr_r = 'x; - per_bank_core_req_wsel_r = 'x; - per_bank_core_req_byteen_r= 'x; - per_bank_core_req_data_r = 'x; - per_bank_core_req_tag_r = 'x; - per_bank_core_req_tid_r = 'x; - - for (integer i = NUM_REQS-1; i >= 0; --i) begin - if (core_req_valid[i]) begin - per_bank_core_req_valid_r[core_req_bid[i]] = 1; - per_bank_core_req_pmask_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i]; - per_bank_core_req_wsel_r[core_req_bid[i]][i % NUM_PORTS] = core_req_wsel[i]; - per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i]; - per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i]; - per_bank_core_req_tid_r[core_req_bid[i]][i % NUM_PORTS] = `REQS_BITS'(i); - per_bank_core_req_tag_r[core_req_bid[i]][i % NUM_PORTS] = core_req_tag[i]; - per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i]; - per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i]; - end - end - end - - always @(*) begin - for (integer i = 0; i < NUM_REQS; ++i) begin - core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] - && core_req_line_match[i]; - end - end - end - - end else begin - - always @(*) begin - per_bank_core_req_valid_r = 0; - per_bank_core_req_rw_r = 'x; - per_bank_core_req_addr_r = 'x; - per_bank_core_req_wsel_r = 'x; - per_bank_core_req_byteen_r= 'x; - per_bank_core_req_data_r = 'x; - per_bank_core_req_tag_r = 'x; - per_bank_core_req_tid_r = 'x; - - for (integer i = NUM_REQS-1; i >= 0; --i) begin - if (core_req_valid[i]) begin - per_bank_core_req_valid_r[core_req_bid[i]] = 1; - per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i]; - per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i]; - per_bank_core_req_wsel_r[core_req_bid[i]] = core_req_wsel[i]; - per_bank_core_req_byteen_r[core_req_bid[i]]= core_req_byteen[i]; - per_bank_core_req_data_r[core_req_bid[i]] = core_req_data[i]; - per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i]; - per_bank_core_req_tid_r[core_req_bid[i]] = `REQS_BITS'(i); - end - end - - per_bank_core_req_pmask_r = per_bank_core_req_valid_r; - end - - if (NUM_BANKS > 1) begin - always @(*) begin - core_req_ready_r = 0; - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_req_valid_r[i]) begin - core_req_ready_r[per_bank_core_req_tid_r[i]] = per_bank_core_req_ready[i]; - end - end - end - end else begin - always @(*) begin - core_req_ready_r = 0; - core_req_ready_r[per_bank_core_req_tid_r[0]] = per_bank_core_req_ready; - end - end - end - - end else begin - - if (NUM_BANKS > 1) begin - always @(*) begin - per_bank_core_req_valid_r = 0; - per_bank_core_req_rw_r = 'x; - per_bank_core_req_addr_r = 'x; - per_bank_core_req_wsel_r = 'x; - per_bank_core_req_byteen_r= 'x; - per_bank_core_req_data_r = 'x; - per_bank_core_req_tag_r = 'x; - per_bank_core_req_tid_r = 'x; - per_bank_core_req_valid_r[core_req_bid[0]] = core_req_valid; - per_bank_core_req_rw_r[core_req_bid[0]] = core_req_rw; - per_bank_core_req_addr_r[core_req_bid[0]] = core_req_line_addr; - per_bank_core_req_wsel_r[core_req_bid[0]] = core_req_wsel; - per_bank_core_req_byteen_r[core_req_bid[0]] = core_req_byteen; - per_bank_core_req_data_r[core_req_bid[0]] = core_req_data; - per_bank_core_req_tag_r[core_req_bid[0]] = core_req_tag; - per_bank_core_req_tid_r[core_req_bid[0]] = 0; - core_req_ready_r = per_bank_core_req_ready[core_req_bid[0]]; - - per_bank_core_req_pmask_r = per_bank_core_req_valid_r; - end - end else begin - `UNUSED_VAR (core_req_bid) - always @(*) begin - per_bank_core_req_valid_r = core_req_valid; - per_bank_core_req_rw_r = core_req_rw; - per_bank_core_req_addr_r = core_req_line_addr; - per_bank_core_req_wsel_r = core_req_wsel; - per_bank_core_req_byteen_r = core_req_byteen; - per_bank_core_req_data_r = core_req_data; - per_bank_core_req_tag_r = core_req_tag; - per_bank_core_req_tid_r = 0; - core_req_ready_r = per_bank_core_req_ready; - - per_bank_core_req_pmask_r = per_bank_core_req_valid_r; - end - end - - end - - assign per_bank_core_req_valid = per_bank_core_req_valid_r; - assign per_bank_core_req_pmask = per_bank_core_req_pmask_r; - assign per_bank_core_req_rw = per_bank_core_req_rw_r; - assign per_bank_core_req_addr = per_bank_core_req_addr_r; - assign per_bank_core_req_wsel = per_bank_core_req_wsel_r; - assign per_bank_core_req_byteen = per_bank_core_req_byteen_r; - assign per_bank_core_req_data = per_bank_core_req_data_r; - assign per_bank_core_req_tag = per_bank_core_req_tag_r; - assign per_bank_core_req_tid = per_bank_core_req_tid_r; - assign core_req_ready = core_req_ready_r; - -`ifdef PERF_ENABLE - reg [NUM_REQS-1:0] core_req_sel_r; - - always @(*) begin - core_req_sel_r = 0; - for (integer i = 0; i < NUM_REQS; ++i) begin - if (core_req_valid[i]) begin - core_req_sel_r[i] = per_bank_core_req_ready[core_req_bid[i]]; - end - end - end - - reg [`PERF_CTR_BITS-1:0] bank_stalls_r; - wire [$clog2(NUM_REQS+1)-1:0] bank_stall_cnt; - - wire [NUM_REQS-1:0] bank_stall_mask = core_req_sel_r & ~core_req_ready; - `POP_COUNT(bank_stall_cnt, bank_stall_mask); - - always @(posedge clk) begin - if (reset) begin - bank_stalls_r <= 0; - end else begin - bank_stalls_r <= bank_stalls_r + `PERF_CTR_BITS'(bank_stall_cnt); - end - end - - assign bank_stalls = bank_stalls_r; -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_core_rsp_merge.sv b/hw/rtl/cache/VX_core_rsp_merge.sv deleted file mode 100644 index b21f6085..00000000 --- a/hw/rtl/cache/VX_core_rsp_merge.sv +++ /dev/null @@ -1,350 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_core_rsp_merge #( - parameter CACHE_ID = 0, - - // Number of Word requests per cycle - parameter NUM_REQS = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // core request tag size - parameter CORE_TAG_WIDTH = 1, - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 0, - // output register - parameter OUT_REG = 0 -) ( - input wire clk, - input wire reset, - - // Per Bank WB - input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid, - input wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_pmask, - input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data, - input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid, - input wire [NUM_BANKS-1:0][NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag, - output wire [NUM_BANKS-1:0] per_bank_core_rsp_ready, - - // Core Response - output wire [`CORE_RSP_TAGS-1:0] core_rsp_valid, - output wire [NUM_REQS-1:0] core_rsp_tmask, - output wire [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, - output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data, - input wire [`CORE_RSP_TAGS-1:0] core_rsp_ready -); - `UNUSED_PARAM (CACHE_ID) - - if (NUM_BANKS > 1) begin - - reg [NUM_REQS-1:0] core_rsp_valid_unqual; - reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; - reg [NUM_BANKS-1:0] per_bank_core_rsp_ready_r; - - if (CORE_TAG_ID_BITS != 0) begin - - // The core response bus handles a single tag at the time - // We first need to select the current tag to process, - // then send all bank responses for that tag as a batch - - wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; - wire core_rsp_ready_unqual; - - if (NUM_PORTS > 1) begin - - reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_r, per_bank_core_rsp_sent; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_n; - - for (genvar i = 0; i < NUM_BANKS; ++i) begin - assign per_bank_core_rsp_sent_n[i] = per_bank_core_rsp_sent_r[i] | per_bank_core_rsp_sent[i]; - end - - always @(posedge clk) begin - if (reset) begin - per_bank_core_rsp_sent_r <= '0; - end else begin - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]) begin - per_bank_core_rsp_sent_r[i] <= '0; - end else begin - per_bank_core_rsp_sent_r[i] <= per_bank_core_rsp_sent_n[i]; - end - end - end - end - - wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_valid_p; - for (genvar i = 0; i < NUM_BANKS; ++i) begin - for (genvar p = 0; p < NUM_PORTS; ++p) begin - assign per_bank_core_rsp_valid_p[i][p] = per_bank_core_rsp_valid[i] - && per_bank_core_rsp_pmask[i][p] - && !per_bank_core_rsp_sent_r[i][p]; - end - end - - VX_find_first #( - .N (NUM_BANKS * NUM_PORTS), - .DATAW (CORE_TAG_WIDTH) - ) find_first ( - .valid_i (per_bank_core_rsp_valid_p), - .data_i (per_bank_core_rsp_tag), - .data_o (core_rsp_tag_unqual), - `UNUSED_PIN (valid_o) - ); - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_data_unqual = 'x; - per_bank_core_rsp_sent = 0; - - for (integer i = 0; i < NUM_BANKS; ++i) begin - for (integer p = 0; p < NUM_PORTS; ++p) begin - if (per_bank_core_rsp_valid[i] - && per_bank_core_rsp_pmask[i][p] - && !per_bank_core_rsp_sent_r[i][p] - && (per_bank_core_rsp_tag[i][p][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin - core_rsp_valid_unqual[per_bank_core_rsp_tid[i][p]] = 1; - core_rsp_data_unqual[per_bank_core_rsp_tid[i][p]] = per_bank_core_rsp_data[i][p]; - per_bank_core_rsp_sent[i][p] = core_rsp_ready_unqual; - end - end - end - end - - always @(*) begin - for (integer i = 0; i < NUM_BANKS; ++i) begin - per_bank_core_rsp_ready_r[i] = (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]); - end - end - - end else begin - - `UNUSED_VAR (per_bank_core_rsp_pmask) - - VX_find_first #( - .N (NUM_BANKS), - .DATAW (CORE_TAG_WIDTH) - ) find_first ( - .valid_i (per_bank_core_rsp_valid), - .data_i (per_bank_core_rsp_tag), - .data_o (core_rsp_tag_unqual), - `UNUSED_PIN (valid_o) - ); - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_data_unqual = 'x; - per_bank_core_rsp_ready_r = 0; - - for (integer i = 0; i < NUM_BANKS; i++) begin - if (per_bank_core_rsp_valid[i] - && (per_bank_core_rsp_tag[i][0][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin - core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; - core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; - per_bank_core_rsp_ready_r[i] = core_rsp_ready_unqual; - end - end - end - end - - wire core_rsp_valid_any = (| per_bank_core_rsp_valid); - - VX_skid_buffer #( - .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)), - .PASSTHRU (0 == OUT_REG) - ) out_sbuf ( - .clk (clk), - .reset (reset), - .valid_in (core_rsp_valid_any), - .data_in ({core_rsp_valid_unqual, core_rsp_tag_unqual, core_rsp_data_unqual}), - .ready_in (core_rsp_ready_unqual), - .valid_out (core_rsp_valid), - .data_out ({core_rsp_tmask, core_rsp_tag, core_rsp_data}), - .ready_out (core_rsp_ready) - ); - - end else begin - - reg [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; - wire [NUM_REQS-1:0] core_rsp_ready_unqual; - - if (NUM_PORTS > 1) begin - - reg [NUM_REQS-1:0][(`PORTS_BITS + `BANK_SELECT_BITS)-1:0] bank_select_table; - - reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_r, per_bank_core_rsp_sent; - wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_sent_n; - - for (genvar i = 0; i < NUM_BANKS; ++i) begin - assign per_bank_core_rsp_sent_n[i] = per_bank_core_rsp_sent_r[i] | per_bank_core_rsp_sent[i]; - end - - always @(posedge clk) begin - if (reset) begin - per_bank_core_rsp_sent_r <= '0; - end else begin - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]) begin - per_bank_core_rsp_sent_r[i] <= '0; - end else begin - per_bank_core_rsp_sent_r[i] <= per_bank_core_rsp_sent_n[i]; - end - end - end - end - - always @(*) begin - core_rsp_valid_unqual = '0; - core_rsp_tag_unqual = 'x; - core_rsp_data_unqual = 'x; - bank_select_table = 'x; - - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - for (integer p = 0; p < NUM_PORTS; ++p) begin - if (per_bank_core_rsp_valid[i] - && per_bank_core_rsp_pmask[i][p] - && !per_bank_core_rsp_sent_r[i][p]) begin - core_rsp_valid_unqual[per_bank_core_rsp_tid[i][p]] = 1; - core_rsp_tag_unqual[per_bank_core_rsp_tid[i][p]] = per_bank_core_rsp_tag[i][p]; - core_rsp_data_unqual[per_bank_core_rsp_tid[i][p]] = per_bank_core_rsp_data[i][p]; - bank_select_table[per_bank_core_rsp_tid[i][p]] = {`PORTS_BITS'(p), `BANK_SELECT_BITS'(i)}; - end - end - end - end - - always @(*) begin - per_bank_core_rsp_sent = '0; - for (integer i = 0; i < NUM_REQS; i++) begin - if (core_rsp_valid_unqual[i]) begin - per_bank_core_rsp_sent[bank_select_table[i][0 +: `BANK_SELECT_BITS]][bank_select_table[i][`BANK_SELECT_BITS +: `PORTS_BITS]] = core_rsp_ready_unqual[i]; - end - end - end - - always @(*) begin - for (integer i = 0; i < NUM_BANKS; i++) begin - per_bank_core_rsp_ready_r[i] = (per_bank_core_rsp_sent_n[i] == per_bank_core_rsp_pmask[i]); - end - end - - end else begin - - `UNUSED_VAR (per_bank_core_rsp_pmask) - reg [NUM_REQS-1:0][NUM_BANKS-1:0] bank_select_table; - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_tag_unqual = 'x; - core_rsp_data_unqual = 'x; - bank_select_table = 'x; - - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_core_rsp_valid[i]) begin - core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; - core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i]; - core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; - bank_select_table[per_bank_core_rsp_tid[i]] = (1 << i); - end - end - end - - always @(*) begin - for (integer i = 0; i < NUM_BANKS; ++i) begin - per_bank_core_rsp_ready_r[i] = core_rsp_ready_unqual[per_bank_core_rsp_tid[i]] - && bank_select_table[per_bank_core_rsp_tid[i]][i]; - end - end - end - - for (genvar i = 0; i < NUM_REQS; i++) begin - VX_skid_buffer #( - .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH), - .PASSTHRU (0 == OUT_REG) - ) out_sbuf ( - .clk (clk), - .reset (reset), - .valid_in (core_rsp_valid_unqual[i]), - .data_in ({core_rsp_tag_unqual[i], core_rsp_data_unqual[i]}), - .ready_in (core_rsp_ready_unqual[i]), - .valid_out (core_rsp_valid[i]), - .data_out ({core_rsp_tag[i],core_rsp_data[i]}), - .ready_out (core_rsp_ready[i]) - ); - end - - assign core_rsp_tmask = core_rsp_valid; - - end - - assign per_bank_core_rsp_ready = per_bank_core_rsp_ready_r; - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - `UNUSED_VAR (per_bank_core_rsp_pmask) - - if (NUM_REQS > 1) begin - - reg [`CORE_RSP_TAGS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; - reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; - - if (CORE_TAG_ID_BITS != 0) begin - - reg [NUM_REQS-1:0] core_rsp_tmask_unqual; - - always @(*) begin - core_rsp_tmask_unqual = 0; - core_rsp_tmask_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_valid; - - core_rsp_tag_unqual = per_bank_core_rsp_tag; - - core_rsp_data_unqual = 'x; - core_rsp_data_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_data; - end - - assign core_rsp_valid = per_bank_core_rsp_valid; - assign core_rsp_tmask = core_rsp_tmask_unqual; - assign per_bank_core_rsp_ready = core_rsp_ready; - - end else begin - - reg [`CORE_RSP_TAGS-1:0] core_rsp_valid_unqual; - - always @(*) begin - core_rsp_valid_unqual = 0; - core_rsp_valid_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_valid; - - core_rsp_tag_unqual = 'x; - core_rsp_tag_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_tag; - - core_rsp_data_unqual = 'x; - core_rsp_data_unqual[per_bank_core_rsp_tid] = per_bank_core_rsp_data; - end - - assign core_rsp_valid = core_rsp_valid_unqual; - assign core_rsp_tmask = core_rsp_valid_unqual; - assign per_bank_core_rsp_ready = core_rsp_ready[per_bank_core_rsp_tid]; - - end - - assign core_rsp_tag = core_rsp_tag_unqual; - assign core_rsp_data = core_rsp_data_unqual; - - end else begin - - `UNUSED_VAR(per_bank_core_rsp_tid) - assign core_rsp_valid = per_bank_core_rsp_valid; - assign core_rsp_tmask = per_bank_core_rsp_valid; - assign core_rsp_tag = per_bank_core_rsp_tag; - assign core_rsp_data = per_bank_core_rsp_data; - assign per_bank_core_rsp_ready = core_rsp_ready; - - end - end - -endmodule diff --git a/hw/rtl/cache/VX_data_access.sv b/hw/rtl/cache/VX_data_access.sv deleted file mode 100644 index f5809644..00000000 --- a/hw/rtl/cache/VX_data_access.sv +++ /dev/null @@ -1,133 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_data_access #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // Enable cache writeable - parameter WRITE_ENABLE = 1, - - parameter WORD_SELECT_BITS = `UP(`WORD_SELECT_BITS) -) ( - input wire clk, - input wire reset, - -`IGNORE_UNUSED_BEGIN - input wire[`DBG_CACHE_REQ_IDW-1:0] req_id, -`IGNORE_UNUSED_END - - input wire stall, - - input wire read, - input wire fill, - input wire write, - input wire[`LINE_ADDR_WIDTH-1:0] addr, - input wire [NUM_PORTS-1:0][WORD_SELECT_BITS-1:0] wsel, - input wire [NUM_PORTS-1:0] pmask, - input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen, - input wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] fill_data, - input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] write_data, - output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data -); - `UNUSED_PARAM (CACHE_ID) - `UNUSED_PARAM (BANK_ID) - `UNUSED_PARAM (WORD_SIZE) - `UNUSED_VAR (reset) - `UNUSED_VAR (addr) - `UNUSED_VAR (read) - - localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1; - - wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] rdata; - wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata; - wire [BYTEENW-1:0] wren; - - wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0]; - - if (WRITE_ENABLE) begin - if (`WORDS_PER_LINE > 1) begin - reg [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] wdata_r; - reg [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wren_r; - if (NUM_PORTS > 1) begin - always @(*) begin - wdata_r = 'x; - wren_r = 0; - for (integer i = 0; i < NUM_PORTS; ++i) begin - if (pmask[i]) begin - wdata_r[wsel[i]] = write_data[i]; - wren_r[wsel[i]] = byteen[i]; - end - end - end - end else begin - `UNUSED_VAR (pmask) - always @(*) begin - wdata_r = {`WORDS_PER_LINE{write_data}}; - wren_r = 0; - wren_r[wsel] = byteen; - end - end - assign wdata = write ? wdata_r : fill_data; - assign wren = write ? wren_r : {BYTEENW{fill}}; - end else begin - `UNUSED_VAR (wsel) - `UNUSED_VAR (pmask) - assign wdata = write ? write_data : fill_data; - assign wren = write ? byteen : {BYTEENW{fill}}; - end - end else begin - `UNUSED_VAR (write) - `UNUSED_VAR (byteen) - `UNUSED_VAR (pmask) - `UNUSED_VAR (write_data) - assign wdata = fill_data; - assign wren = fill; - end - - VX_sp_ram #( - .DATAW (`CACHE_LINE_WIDTH), - .SIZE (`LINES_PER_BANK), - .BYTEENW (BYTEENW), - .NO_RWCHECK (1) - ) data_store ( - .clk (clk), - .addr (line_addr), - .wren (wren), - .wdata (wdata), - .rdata (rdata) - ); - - if (`WORDS_PER_LINE > 1) begin - for (genvar i = 0; i < NUM_PORTS; ++i) begin - assign read_data[i] = rdata[wsel[i]]; - end - end else begin - assign read_data = rdata; - end - - `UNUSED_VAR (stall) - -`ifdef DBG_TRACE_CACHE_DATA - always @(posedge clk) begin - if (fill && ~stall) begin - dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data); - end - if (read && ~stall) begin - dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, blk_addr=%0d, data=%0h (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, read_data, req_id); - end - if (write && ~stall) begin - dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, byteen=%b, blk_addr=%0d, data=%0h (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), byteen, line_addr, write_data, req_id); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_flush_ctrl.sv b/hw/rtl/cache/VX_flush_ctrl.sv deleted file mode 100644 index 356781d1..00000000 --- a/hw/rtl/cache/VX_flush_ctrl.sv +++ /dev/null @@ -1,36 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_flush_ctrl #( - // Size of cache in bytes - parameter CACHE_SIZE = 16384, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1 -) ( - input wire clk, - input wire reset, - output wire [`LINE_SELECT_BITS-1:0] addr_out, - output wire valid_out -); - reg flush_enable; - reg [`LINE_SELECT_BITS-1:0] flush_ctr; - - always @(posedge clk) begin - if (reset) begin - flush_enable <= 1; - flush_ctr <= 0; - end else begin - if (flush_enable) begin - if (flush_ctr == ((2 ** `LINE_SELECT_BITS)-1)) begin - flush_enable <= 0; - end - flush_ctr <= flush_ctr + 1; - end - end - end - - assign addr_out = flush_ctr; - assign valid_out = flush_enable; - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_miss_resrv.sv b/hw/rtl/cache/VX_miss_resrv.sv deleted file mode 100644 index b9081fdd..00000000 --- a/hw/rtl/cache/VX_miss_resrv.sv +++ /dev/null @@ -1,234 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_miss_resrv #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - - // Number of Word requests per cycle - parameter NUM_REQS = 1, - - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Number of ports per banks - parameter NUM_PORTS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // Miss Reserv Queue Knob - parameter MSHR_SIZE = 1, - // core request tag size - parameter CORE_TAG_WIDTH = 1, - - parameter MSHR_ADDR_WIDTH = $clog2(MSHR_SIZE) -) ( - input wire clk, - input wire reset, - -`IGNORE_UNUSED_BEGIN - input wire[`DBG_CACHE_REQ_IDW-1:0] deq_req_id, - input wire[`DBG_CACHE_REQ_IDW-1:0] lkp_req_id, - input wire[`DBG_CACHE_REQ_IDW-1:0] rel_req_id, -`IGNORE_UNUSED_END - - // allocate - input wire allocate_valid, - input wire [`LINE_ADDR_WIDTH-1:0] allocate_addr, - input wire [`MSHR_DATA_WIDTH-1:0] allocate_data, - output wire [MSHR_ADDR_WIDTH-1:0] allocate_id, - output wire allocate_ready, - - // fill - input wire fill_valid, - input wire [MSHR_ADDR_WIDTH-1:0] fill_id, - output wire [`LINE_ADDR_WIDTH-1:0] fill_addr, - - // lookup - input wire lookup_valid, - input wire lookup_replay, - input wire [MSHR_ADDR_WIDTH-1:0] lookup_id, - input wire [`LINE_ADDR_WIDTH-1:0] lookup_addr, - output wire lookup_match, - - // dequeue - output wire dequeue_valid, - output wire [MSHR_ADDR_WIDTH-1:0] dequeue_id, - output wire [`LINE_ADDR_WIDTH-1:0] dequeue_addr, - output wire [`MSHR_DATA_WIDTH-1:0] dequeue_data, - input wire dequeue_ready, - - // release - input wire release_valid, - input wire [MSHR_ADDR_WIDTH-1:0] release_id -); - `UNUSED_PARAM (CACHE_ID) - `UNUSED_PARAM (BANK_ID) - - reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table, addr_table_n; - reg [MSHR_SIZE-1:0] valid_table, valid_table_n; - reg [MSHR_SIZE-1:0] ready_table, ready_table_n; - - reg allocate_rdy_r, allocate_rdy_n; - reg [MSHR_ADDR_WIDTH-1:0] allocate_id_r, allocate_id_n; - - reg dequeue_val_r, dequeue_val_n, dequeue_val_x; - reg [MSHR_ADDR_WIDTH-1:0] dequeue_id_r, dequeue_id_n, dequeue_id_x; - - reg [MSHR_SIZE-1:0] valid_table_x; - reg [MSHR_SIZE-1:0] ready_table_x; - - wire [MSHR_SIZE-1:0] addr_matches; - - wire allocate_fire = allocate_valid && allocate_ready; - - wire dequeue_fire = dequeue_valid && dequeue_ready; - - for (genvar i = 0; i < MSHR_SIZE; ++i) begin - assign addr_matches[i] = (addr_table[i] == lookup_addr); - end - - always @(*) begin - valid_table_x = valid_table; - ready_table_x = ready_table; - if (dequeue_fire) begin - valid_table_x[dequeue_id] = 0; - end - if (lookup_replay) begin - ready_table_x |= addr_matches; - end - end - - VX_lzc #( - .N (MSHR_SIZE) - ) dequeue_sel ( - .in_i (valid_table_x & ready_table_x), - .cnt_o (dequeue_id_x), - .valid_o (dequeue_val_x) - ); - - VX_lzc #( - .N (MSHR_SIZE) - ) allocate_sel ( - .in_i (~valid_table_n), - .cnt_o (allocate_id_n), - .valid_o (allocate_rdy_n) - ); - - always @(*) begin - valid_table_n = valid_table_x; - ready_table_n = ready_table_x; - addr_table_n = addr_table; - dequeue_val_n = dequeue_val_r; - dequeue_id_n = dequeue_id_r; - - if (dequeue_fire) begin - dequeue_val_n = dequeue_val_x; - dequeue_id_n = dequeue_id_x; - end - - if (allocate_fire) begin - valid_table_n[allocate_id] = 1; - ready_table_n[allocate_id] = 0; - addr_table_n[allocate_id] = allocate_addr; - end - - if (fill_valid) begin - dequeue_val_n = 1; - dequeue_id_n = fill_id; - end - - if (release_valid) begin - valid_table_n[release_id] = 0; - end - end - - always @(posedge clk) begin - if (reset) begin - valid_table <= 0; - allocate_rdy_r <= 0; - dequeue_val_r <= 0; - end else begin - valid_table <= valid_table_n; - allocate_rdy_r <= allocate_rdy_n; - dequeue_val_r <= dequeue_val_n; - end - ready_table <= ready_table_n; - addr_table <= addr_table_n; - dequeue_id_r <= dequeue_id_n; - allocate_id_r <= allocate_id_n; - - `ASSERT(!allocate_fire || !valid_table[allocate_id_r], ("runtime error")); - `ASSERT(!release_valid || valid_table[release_id], ("runtime error")); - end - - `RUNTIME_ASSERT((!allocate_fire || ~valid_table[allocate_id]), ("%t: *** cache%0d:%0d in-use allocation: addr=%0h, id=%0d", $time, CACHE_ID, BANK_ID, - `LINE_TO_BYTE_ADDR(allocate_addr, BANK_ID), allocate_id)) - - `RUNTIME_ASSERT((!fill_valid || valid_table[fill_id]), ("%t: *** cache%0d:%0d invalid fill: addr=%0h, id=%0d", $time, CACHE_ID, BANK_ID, - `LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id)) - - VX_dp_ram #( - .DATAW (`MSHR_DATA_WIDTH), - .SIZE (MSHR_SIZE), - .LUTRAM (1) - ) entries ( - .clk (clk), - .waddr (allocate_id_r), - .raddr (dequeue_id_r), - .wren (allocate_valid), - .wdata (allocate_data), - .rdata (dequeue_data) - ); - - assign fill_addr = addr_table[fill_id]; - - assign allocate_ready = allocate_rdy_r; - assign allocate_id = allocate_id_r; - - assign dequeue_valid = dequeue_val_r; - assign dequeue_id = dequeue_id_r; - assign dequeue_addr = addr_table[dequeue_id_r]; - - wire [MSHR_SIZE-1:0] lookup_entries; - for (genvar i = 0; i < MSHR_SIZE; ++i) begin - assign lookup_entries[i] = (i != lookup_id); - end - assign lookup_match = |(lookup_entries & valid_table & addr_matches); - - `UNUSED_VAR (lookup_valid) - -`ifdef DBG_TRACE_CACHE_MSHR - always @(posedge clk) begin - if (allocate_fire || fill_valid || dequeue_fire || lookup_replay || lookup_valid || release_valid) begin - if (allocate_fire) - dpi_trace("%d: cache%0d:%0d mshr-allocate: addr=%0h, id=%0d (#%0d)\n", $time, CACHE_ID, BANK_ID, - `LINE_TO_BYTE_ADDR(allocate_addr, BANK_ID), allocate_id, deq_req_id); - if (fill_valid) - dpi_trace("%d: cache%0d:%0d mshr-fill: addr=%0h, id=%0d, addr=%0h\n", $time, CACHE_ID, BANK_ID, - `LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id, `LINE_TO_BYTE_ADDR(fill_addr, BANK_ID)); - if (dequeue_fire) - dpi_trace("%d: cache%0d:%0d mshr-dequeue: addr=%0h, id=%0d (#%0d)\n", $time, CACHE_ID, BANK_ID, - `LINE_TO_BYTE_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_id); - if (lookup_replay) - dpi_trace("%d: cache%0d:%0d mshr-replay: addr=%0h, id=%0d (#%0d)\n", $time, CACHE_ID, BANK_ID, - `LINE_TO_BYTE_ADDR(lookup_addr, BANK_ID), lookup_id, lkp_req_id); - if (lookup_valid) - dpi_trace("%d: cache%0d:%0d mshr-lookup: addr=%0h, id=%0d, match=%b (#%0d)\n", $time, CACHE_ID, BANK_ID, - `LINE_TO_BYTE_ADDR(lookup_addr, BANK_ID), lookup_id, lookup_match, lkp_req_id); - if (release_valid) - dpi_trace("%d: cache%0d:%0d mshr-release id=%0d (#%0d)\n", $time, CACHE_ID, BANK_ID, release_id, rel_req_id); - dpi_trace("%d: cache%0d:%0d mshr-table", $time, CACHE_ID, BANK_ID); - for (integer i = 0; i < MSHR_SIZE; ++i) begin - if (valid_table[i]) begin - dpi_trace(" "); - if (ready_table[i]) - dpi_trace("*"); - dpi_trace("%0d=%0h", i, `LINE_TO_BYTE_ADDR(addr_table[i], BANK_ID)); - end - end - dpi_trace("\n"); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_nc_bypass.sv b/hw/rtl/cache/VX_nc_bypass.sv deleted file mode 100644 index 19cd3921..00000000 --- a/hw/rtl/cache/VX_nc_bypass.sv +++ /dev/null @@ -1,323 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_nc_bypass #( - parameter NUM_PORTS = 1, - parameter NUM_REQS = 1, - parameter NUM_RSP_TAGS = 0, - parameter NC_TAG_BIT = 0, - - parameter CORE_ADDR_WIDTH = 1, - parameter CORE_DATA_SIZE = 1, - parameter CORE_TAG_IN_WIDTH = 1, - - parameter MEM_ADDR_WIDTH = 1, - parameter MEM_DATA_SIZE = 1, - parameter MEM_TAG_IN_WIDTH = 1, - parameter MEM_TAG_OUT_WIDTH = 1, - - parameter CORE_DATA_WIDTH = CORE_DATA_SIZE * 8, - parameter MEM_DATA_WIDTH = MEM_DATA_SIZE * 8, - parameter CORE_TAG_OUT_WIDTH = CORE_TAG_IN_WIDTH - 1, - parameter MEM_SELECT_BITS = `UP(`CLOG2(MEM_DATA_SIZE / CORE_DATA_SIZE)) - ) ( - input wire clk, - input wire reset, - - // Core request in - input wire [NUM_REQS-1:0] core_req_valid_in, - input wire [NUM_REQS-1:0] core_req_rw_in, - input wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_in, - input wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_in, - input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_in, - input wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_req_tag_in, - output wire [NUM_REQS-1:0] core_req_ready_in, - - // Core request out - output wire [NUM_REQS-1:0] core_req_valid_out, - output wire [NUM_REQS-1:0] core_req_rw_out, - output wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_out, - output wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_out, - output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_out, - output wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_req_tag_out, - input wire [NUM_REQS-1:0] core_req_ready_out, - - // Core response in - input wire [NUM_RSP_TAGS-1:0] core_rsp_valid_in, - input wire [NUM_REQS-1:0] core_rsp_tmask_in, - input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_in, - input wire [NUM_RSP_TAGS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_rsp_tag_in, - output wire [NUM_RSP_TAGS-1:0] core_rsp_ready_in, - - // Core response out - output wire [NUM_RSP_TAGS-1:0] core_rsp_valid_out, - output wire [NUM_REQS-1:0] core_rsp_tmask_out, - output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_out, - output wire [NUM_RSP_TAGS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out, - input wire [NUM_RSP_TAGS-1:0] core_rsp_ready_out, - - // Memory request in - input wire mem_req_valid_in, - input wire mem_req_rw_in, - input wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_in, - input wire [NUM_PORTS-1:0] mem_req_pmask_in, - input wire [NUM_PORTS-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_in, - input wire [NUM_PORTS-1:0][MEM_SELECT_BITS-1:0] mem_req_wsel_in, - input wire [NUM_PORTS-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in, - input wire [MEM_TAG_IN_WIDTH-1:0] mem_req_tag_in, - output wire mem_req_ready_in, - - // Memory request out - output wire mem_req_valid_out, - output wire mem_req_rw_out, - output wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_out, - output wire [NUM_PORTS-1:0] mem_req_pmask_out, - output wire [NUM_PORTS-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_out, - output wire [NUM_PORTS-1:0][MEM_SELECT_BITS-1:0] mem_req_wsel_out, - output wire [NUM_PORTS-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_out, - output wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_out, - input wire mem_req_ready_out, - - // Memory response in - input wire mem_rsp_valid_in, - input wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_in, - input wire [MEM_TAG_OUT_WIDTH-1:0] mem_rsp_tag_in, - output wire mem_rsp_ready_in, - - // Memory response out - output wire mem_rsp_valid_out, - output wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_out, - output wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_out, - input wire mem_rsp_ready_out -); - `STATIC_ASSERT((NUM_RSP_TAGS == 1 || NUM_RSP_TAGS == NUM_REQS), ("invalid paramter")) - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - localparam CORE_REQ_TIDW = $clog2(NUM_REQS); - localparam MUX_DATAW = CORE_TAG_IN_WIDTH + CORE_DATA_WIDTH + CORE_DATA_SIZE + CORE_ADDR_WIDTH + 1; - - localparam CORE_LDATAW = $clog2(CORE_DATA_WIDTH); - localparam MEM_LDATAW = $clog2(MEM_DATA_WIDTH); - localparam D = MEM_LDATAW - CORE_LDATAW; - - // core request handling - - wire [NUM_REQS-1:0] core_req_valid_in_nc; - wire [NUM_REQS-1:0] core_req_nc_tids; - wire [`UP(CORE_REQ_TIDW)-1:0] core_req_nc_tid; - wire [NUM_REQS-1:0] core_req_nc_sel; - wire core_req_nc_valid; - - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_req_nc_tids[i] = core_req_tag_in[i][NC_TAG_BIT]; - end - - assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_tids; - - VX_priority_encoder #( - .N (NUM_REQS) - ) core_req_sel ( - .data_in (core_req_valid_in_nc), - .index (core_req_nc_tid), - .onehot (core_req_nc_sel), - .valid_out (core_req_nc_valid) - ); - - assign core_req_valid_out = core_req_valid_in & ~core_req_nc_tids; - assign core_req_rw_out = core_req_rw_in; - assign core_req_addr_out = core_req_addr_in; - assign core_req_byteen_out = core_req_byteen_in; - assign core_req_data_out = core_req_data_in; - - for (genvar i = 0; i < NUM_REQS; ++i) begin - VX_bits_remove #( - .N (CORE_TAG_IN_WIDTH), - .S (1), - .POS (NC_TAG_BIT) - ) core_req_tag_remove ( - .data_in (core_req_tag_in[i]), - .data_out (core_req_tag_out[i]) - ); - end - - if (NUM_REQS > 1) begin - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_req_ready_in[i] = core_req_valid_in_nc[i] ? - (~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i]) : core_req_ready_out[i]; - end - end else begin - assign core_req_ready_in = core_req_valid_in_nc ? (~mem_req_valid_in && mem_req_ready_out) : core_req_ready_out; - end - - // memory request handling - - assign mem_req_valid_out = mem_req_valid_in || core_req_nc_valid; - assign mem_req_ready_in = mem_req_ready_out; - - wire [(MEM_TAG_IN_WIDTH+1)-1:0] mem_req_tag_in_c; - - VX_bits_insert #( - .N (MEM_TAG_IN_WIDTH), - .S (1), - .POS (NC_TAG_BIT) - ) mem_req_tag_insert ( - .data_in (mem_req_tag_in), - .sel_in ('0), - .data_out (mem_req_tag_in_c) - ); - - wire [CORE_TAG_IN_WIDTH-1:0] core_req_tag_in_sel; - wire [CORE_DATA_WIDTH-1:0] core_req_data_in_sel; - wire [CORE_DATA_SIZE-1:0] core_req_byteen_in_sel; - wire [CORE_ADDR_WIDTH-1:0] core_req_addr_in_sel; - wire core_req_rw_in_sel; - - if (NUM_REQS > 1) begin - wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in; - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_req_nc_mux_in[i] = {core_req_tag_in[i], core_req_data_in[i], core_req_byteen_in[i], core_req_addr_in[i], core_req_rw_in[i]}; - end - - assign {core_req_tag_in_sel, core_req_data_in_sel, core_req_byteen_in_sel, core_req_addr_in_sel, core_req_rw_in_sel} = core_req_nc_mux_in[core_req_nc_tid]; - end else begin - assign core_req_tag_in_sel = core_req_tag_in; - assign core_req_data_in_sel = core_req_data_in; - assign core_req_byteen_in_sel = core_req_byteen_in; - assign core_req_addr_in_sel = core_req_addr_in; - assign core_req_rw_in_sel = core_req_rw_in; - end - - assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in_sel; - assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in_sel[D +: MEM_ADDR_WIDTH]; - - if (D != 0) begin - reg [NUM_PORTS-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_in_r; - reg [NUM_PORTS-1:0][MEM_SELECT_BITS-1:0] mem_req_wsel_in_r; - reg [NUM_PORTS-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_r; - - wire [D-1:0] req_addr_idx = core_req_addr_in_sel[D-1:0]; - - always @(*) begin - mem_req_byteen_in_r = 0; - mem_req_byteen_in_r[0] = core_req_byteen_in_sel; - - mem_req_wsel_in_r = 'x; - mem_req_wsel_in_r[0] = req_addr_idx; - - mem_req_data_in_r = 'x; - mem_req_data_in_r[0] = core_req_data_in_sel; - end - - assign mem_req_pmask_out = mem_req_valid_in ? mem_req_pmask_in : NUM_PORTS'(1'b1); - assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r; - assign mem_req_wsel_out = mem_req_valid_in ? mem_req_wsel_in : mem_req_wsel_in_r; - assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : mem_req_data_in_r; - assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_c) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, req_addr_idx, core_req_tag_in_sel}); - end else begin - `UNUSED_VAR (mem_req_wsel_in) - `UNUSED_VAR (mem_req_pmask_in) - assign mem_req_pmask_out = 0; - assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in_sel; - assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : core_req_data_in_sel; - assign mem_req_wsel_out = 0; - assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_c) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, core_req_tag_in_sel}); - end - - // core response handling - - wire [NUM_RSP_TAGS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out_c; - - wire is_mem_rsp_nc = mem_rsp_valid_in && mem_rsp_tag_in[NC_TAG_BIT]; - - for (genvar i = 0; i < NUM_RSP_TAGS; ++i) begin - VX_bits_insert #( - .N (CORE_TAG_OUT_WIDTH), - .S (1), - .POS (NC_TAG_BIT) - ) core_rsp_tag_insert ( - .data_in (core_rsp_tag_in[i]), - .sel_in ('0), - .data_out (core_rsp_tag_out_c[i]) - ); - end - - if (NUM_RSP_TAGS > 1) begin - wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_IN_WIDTH + D) +: CORE_REQ_TIDW]; - reg [NUM_REQS-1:0] rsp_nc_valid_r; - always @(*) begin - rsp_nc_valid_r = 0; - rsp_nc_valid_r[rsp_tid] = is_mem_rsp_nc; - end - - assign core_rsp_valid_out = core_rsp_valid_in | rsp_nc_valid_r; - assign core_rsp_tmask_out = core_rsp_tmask_in; - assign core_rsp_ready_in = core_rsp_ready_out; - - if (D != 0) begin - wire [D-1:0] rsp_addr_idx = mem_rsp_tag_in[CORE_TAG_IN_WIDTH +: D]; - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? - core_rsp_data_in[i] : mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH]; - end - end else begin - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? core_rsp_data_in[i] : mem_rsp_data_in; - end - end - - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_out_c[i] : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0]; - end - end else begin - assign core_rsp_valid_out = core_rsp_valid_in || is_mem_rsp_nc; - assign core_rsp_tag_out = core_rsp_valid_in ? core_rsp_tag_out_c : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0]; - assign core_rsp_ready_in = core_rsp_ready_out; - - if (NUM_REQS > 1) begin - wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_IN_WIDTH + D) +: CORE_REQ_TIDW]; - reg [NUM_REQS-1:0] core_rsp_tmask_in_r; - always @(*) begin - core_rsp_tmask_in_r = 0; - core_rsp_tmask_in_r[rsp_tid] = 1; - end - assign core_rsp_tmask_out = core_rsp_valid_in ? core_rsp_tmask_in : core_rsp_tmask_in_r; - end else begin - assign core_rsp_tmask_out = core_rsp_tmask_in || is_mem_rsp_nc; - end - - if (D != 0) begin - wire [D-1:0] rsp_addr_idx = mem_rsp_tag_in[CORE_TAG_IN_WIDTH +: D]; - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_rsp_data_out[i] = core_rsp_valid_in ? - core_rsp_data_in[i] : mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH]; - end - end else begin - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_rsp_data_out[i] = core_rsp_valid_in ? core_rsp_data_in[i] : mem_rsp_data_in; - end - end - end - - // memory response handling - - assign mem_rsp_valid_out = mem_rsp_valid_in && ~mem_rsp_tag_in[NC_TAG_BIT]; - assign mem_rsp_data_out = mem_rsp_data_in; - - VX_bits_remove #( - .N (MEM_TAG_IN_WIDTH+1), - .S (1), - .POS (NC_TAG_BIT) - ) mem_rsp_tag_remove ( - .data_in (mem_rsp_tag_in[(MEM_TAG_IN_WIDTH+1)-1:0]), - .data_out (mem_rsp_tag_out) - ); - - if (NUM_RSP_TAGS > 1) begin - wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_IN_WIDTH + D) +: CORE_REQ_TIDW]; - assign mem_rsp_ready_in = is_mem_rsp_nc ? (~core_rsp_valid_in[rsp_tid] && core_rsp_ready_out[rsp_tid]) : mem_rsp_ready_out; - end else begin - assign mem_rsp_ready_in = is_mem_rsp_nc ? (~core_rsp_valid_in && core_rsp_ready_out) : mem_rsp_ready_out; - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_shared_mem.sv b/hw/rtl/cache/VX_shared_mem.sv deleted file mode 100644 index 7d6eb275..00000000 --- a/hw/rtl/cache/VX_shared_mem.sv +++ /dev/null @@ -1,371 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_shared_mem #( - parameter CACHE_ID = 0, - - // Size of cache in bytes - parameter CACHE_SIZE = (1024*16), - // Number of banks - parameter NUM_BANKS = 2, - // Size of a word in bytes - parameter WORD_SIZE = 4, - // Number of Word requests per cycle - parameter NUM_REQS = 4, - - // Core Request Queue Size - parameter CREQ_SIZE = 2, - // Core Response Queue Size - parameter CRSQ_SIZE = 2, - - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 8, - - // core request tag size - parameter CORE_TAG_WIDTH = (2 + CORE_TAG_ID_BITS), - - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = `CLOG2(256) - ) ( - input wire clk, - input wire reset, - - // PERF -`ifdef PERF_ENABLE - VX_perf_cache_if.master perf_cache_if, -`endif - - // Core request - input wire [NUM_REQS-1:0] core_req_valid, - input wire [NUM_REQS-1:0] core_req_rw, - input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr, - input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen, - input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data, - input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag, - output wire [NUM_REQS-1:0] core_req_ready, - - // Core response - output wire core_rsp_valid, - output wire [NUM_REQS-1:0] core_rsp_tmask, - output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data, - output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag, - input wire core_rsp_ready -); - - `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) - `UNUSED_PARAM (CACHE_ID) - `UNUSED_PARAM (CORE_TAG_ID_BITS) - - localparam CACHE_LINE_SIZE = WORD_SIZE; - - wire [NUM_BANKS-1:0] per_bank_core_req_valid_unqual; - wire [NUM_BANKS-1:0] per_bank_core_req_rw_unqual; - wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_unqual; - wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_unqual; - wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_unqual; - wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_unqual; - wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_unqual; - wire [NUM_BANKS-1:0] per_bank_core_req_ready_unqual; - - VX_core_req_bank_sel #( - .CACHE_ID (CACHE_ID), - .CACHE_LINE_SIZE (WORD_SIZE), - .NUM_BANKS (NUM_BANKS), - .NUM_PORTS (1), - .WORD_SIZE (WORD_SIZE), - .NUM_REQS (NUM_REQS), - .CORE_TAG_WIDTH (CORE_TAG_WIDTH), - .BANK_ADDR_OFFSET(BANK_ADDR_OFFSET) - ) core_req_bank_sel ( - .clk (clk), - .reset (reset), - `ifdef PERF_ENABLE - .bank_stalls(perf_cache_if.bank_stalls), - `endif - .core_req_valid (core_req_valid), - .core_req_rw (core_req_rw), - .core_req_addr (core_req_addr), - .core_req_byteen (core_req_byteen), - .core_req_data (core_req_data), - .core_req_tag (core_req_tag), - .core_req_ready (core_req_ready), - .per_bank_core_req_valid (per_bank_core_req_valid_unqual), - .per_bank_core_req_tid (per_bank_core_req_tid_unqual), - .per_bank_core_req_rw (per_bank_core_req_rw_unqual), - .per_bank_core_req_addr (per_bank_core_req_addr_unqual), - .per_bank_core_req_byteen(per_bank_core_req_byteen_unqual), - .per_bank_core_req_tag (per_bank_core_req_tag_unqual), - .per_bank_core_req_data (per_bank_core_req_data_unqual), - .per_bank_core_req_ready (per_bank_core_req_ready_unqual), - `UNUSED_PIN (per_bank_core_req_pmask), - `UNUSED_PIN (per_bank_core_req_wsel) - ); - - wire [NUM_BANKS-1:0] per_bank_core_req_valid; - wire [NUM_BANKS-1:0] per_bank_core_req_rw; - wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr; - wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen; - wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data; - wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag; - wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid; - - wire creq_out_valid, creq_out_ready; - wire creq_in_valid, creq_in_ready; - - wire creq_in_fire = creq_in_valid && creq_in_ready; - `UNUSED_VAR (creq_in_fire) - - wire creq_out_fire = creq_out_valid && creq_out_ready; - `UNUSED_VAR (creq_out_fire) - - assign creq_in_valid = (| core_req_valid); - assign per_bank_core_req_ready_unqual = {NUM_BANKS{creq_in_ready}}; - - wire [NUM_BANKS-1:0] core_req_read_mask, core_req_read_mask_unqual; - wire core_req_writeonly, core_req_writeonly_unqual; - - assign core_req_read_mask_unqual = per_bank_core_req_valid_unqual & ~per_bank_core_req_rw_unqual; - assign core_req_writeonly_unqual = ~(| core_req_read_mask_unqual); - - VX_elastic_buffer #( - .DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1), - .SIZE (CREQ_SIZE), - .OUT_REG (1) // output should be registered for the data_store addr port - ) core_req_queue ( - .clk (clk), - .reset (reset), - .ready_in (creq_in_ready), - .valid_in (creq_in_valid), - .data_in ({per_bank_core_req_valid_unqual, - per_bank_core_req_rw_unqual, - per_bank_core_req_addr_unqual, - per_bank_core_req_byteen_unqual, - per_bank_core_req_data_unqual, - per_bank_core_req_tag_unqual, - per_bank_core_req_tid_unqual, - core_req_read_mask_unqual, - core_req_writeonly_unqual}), - .data_out ({per_bank_core_req_valid, - per_bank_core_req_rw, - per_bank_core_req_addr, - per_bank_core_req_byteen, - per_bank_core_req_data, - per_bank_core_req_tag, - per_bank_core_req_tid, - core_req_read_mask, - core_req_writeonly}), - .ready_out (creq_out_ready), - .valid_out (creq_out_valid) - ); - - wire crsq_in_valid, crsq_in_ready; - wire crsq_last_read; - - assign creq_out_ready = core_req_writeonly - || (crsq_in_ready && crsq_last_read); - - wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data; - - for (genvar i = 0; i < NUM_BANKS; i++) begin - - wire [WORD_SIZE-1:0] wren = per_bank_core_req_byteen[i] - & {WORD_SIZE{per_bank_core_req_valid[i] - && per_bank_core_req_rw[i]}}; - - wire [`LINE_SELECT_BITS-1:0] addr = per_bank_core_req_addr[i][`LINE_SELECT_BITS-1:0]; - - VX_sp_ram #( - .DATAW (`WORD_WIDTH), - .SIZE (`LINES_PER_BANK), - .BYTEENW (WORD_SIZE), - .NO_RWCHECK (1) - ) data_store ( - .clk (clk), - .addr (addr), - .wren (wren), - .wdata (per_bank_core_req_data[i]), - .rdata (per_bank_core_rsp_data[i]) - ); - end - - // The core response bus handles a single tag at the time - // We first need to select the current tag to process, - // then send all bank responses for that tag as a batch - - reg [NUM_REQS-1:0] core_rsp_valids_in; - reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in; - wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; - reg [NUM_BANKS-1:0] bank_rsp_sel_r, bank_rsp_sel_n; - - wire crsq_in_fire = crsq_in_valid && crsq_in_ready; - - assign crsq_last_read = (bank_rsp_sel_n == core_req_read_mask); - - always @(posedge clk) begin - if (reset) begin - bank_rsp_sel_r <= 0; - end else begin - if (crsq_in_fire) begin - if (crsq_last_read) begin - bank_rsp_sel_r <= 0; - end else begin - bank_rsp_sel_r <= bank_rsp_sel_n; - end - end - end - end - - VX_find_first #( - .N (NUM_BANKS), - .DATAW (CORE_TAG_WIDTH) - ) find_first ( - .valid_i (core_req_read_mask & ~bank_rsp_sel_r), - .data_i (per_bank_core_req_tag), - .data_o (core_rsp_tag_in), - `UNUSED_PIN (valid_o) - ); - - always @(*) begin - core_rsp_valids_in = 0; - core_rsp_data_in = 'x; - bank_rsp_sel_n = bank_rsp_sel_r; - for (integer i = 0; i < NUM_BANKS; i++) begin - if (core_req_read_mask[i] - && (core_rsp_tag_in[CORE_TAG_ID_BITS-1:0] == per_bank_core_req_tag[i][CORE_TAG_ID_BITS-1:0])) begin - core_rsp_valids_in[per_bank_core_req_tid[i]] = 1; - core_rsp_data_in[per_bank_core_req_tid[i]] = per_bank_core_rsp_data[i]; - bank_rsp_sel_n[i] = 1; - end - end - end - - assign crsq_in_valid = creq_out_valid && ~core_req_writeonly; - - VX_elastic_buffer #( - .DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH), - .SIZE (CRSQ_SIZE) - ) core_rsp_req ( - .clk (clk), - .reset (reset), - .valid_in (crsq_in_valid), - .data_in ({core_rsp_valids_in, core_rsp_data_in, core_rsp_tag_in}), - .ready_in (crsq_in_ready), - .valid_out (core_rsp_valid), - .data_out ({core_rsp_tmask, core_rsp_data, core_rsp_tag}), - .ready_out (core_rsp_ready) - ); - -`IGNORE_UNUSED_BEGIN - wire [NUM_BANKS-1:0][`DBG_CACHE_REQ_IDW-1:0] req_id_st0, req_id_st1; -`IGNORE_UNUSED_END - - for (genvar i = 0; i < NUM_BANKS; ++i) begin - if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin - assign req_id_st0[i] = per_bank_core_req_tag_unqual[i][`CACHE_REQ_ID_RNG]; - assign req_id_st1[i] = per_bank_core_req_tag[i][`CACHE_REQ_ID_RNG]; - end else begin - assign req_id_st0[i] = 0; - assign req_id_st1[i] = 0; - end - end - -`ifdef DBG_TRACE_CACHE_BANK - - reg is_multi_tag_req; -`IGNORE_UNUSED_BEGIN - reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel; -`IGNORE_UNUSED_END - - VX_find_first #( - .N (NUM_BANKS), - .DATAW (CORE_TAG_WIDTH) - ) find_first_d ( - .valid_i (per_bank_core_req_valid), - .data_i (per_bank_core_req_tag), - .data_o (core_req_tag_sel), - `UNUSED_PIN (valid_o) - ); - - always @(*) begin - is_multi_tag_req = 0; - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_req_valid[i] - && (core_req_tag_sel[CORE_TAG_ID_BITS-1:0] != per_bank_core_req_tag[i][CORE_TAG_ID_BITS-1:0])) begin - is_multi_tag_req = creq_out_valid; - end - end - end - - always @(posedge clk) begin - if (!crsq_in_ready) begin - dpi_trace("%d: *** cache%0d pipeline-stall\n", $time, CACHE_ID); - end - if (is_multi_tag_req) begin - dpi_trace("%d: *** cache%0d multi-tag request!\n", $time, CACHE_ID); - end - if (creq_in_fire) begin - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_req_valid_unqual[i]) begin - if (per_bank_core_req_rw_unqual[i]) begin - dpi_trace("%d: smem%0d:%0d core-wr-req: addr=%0h, tag=%0h, byteen=%b, data=%0h (#%0d)\n", - $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr_unqual[i], i), per_bank_core_req_tag_unqual[i], per_bank_core_req_byteen_unqual[i], per_bank_core_req_data_unqual[i], req_id_st0[i]); - end else begin - dpi_trace("%d: smem%0d:%0d core-rd-req: addr=%0h, tag=%0h (#%0d)\n", - $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr_unqual[i], i), per_bank_core_req_tag_unqual[i], req_id_st0[i]); - end - end - end - end - if (creq_out_fire) begin - for (integer i = 0; i < NUM_BANKS; ++i) begin - if (per_bank_core_req_valid[i]) begin - if (per_bank_core_req_rw[i]) begin - dpi_trace("%d: smem%0d:%0d core-wr-rsp: addr=%0h, tag=%0h, data=%0h (#%0d)\n", - $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr[i], i), per_bank_core_req_tag[i], per_bank_core_req_data[i], req_id_st1[i]); - end else begin - dpi_trace("%d: smem%0d:%0d core-rd-rsp: addr=%0h, tag=%0h, data=%0h (#%0d)\n", - $time, CACHE_ID, i, `LINE_TO_BYTE_ADDR(per_bank_core_req_addr[i], i), per_bank_core_req_tag[i], per_bank_core_rsp_data[i], req_id_st1[i]); - end - end - end - end - end -`endif - -`ifdef PERF_ENABLE - // per cycle: core_reads, core_writes - wire [$clog2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; - wire [$clog2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; - - wire [NUM_REQS-1:0] perf_core_reads_per_mask = core_req_valid & core_req_ready & ~core_req_rw; - wire [NUM_REQS-1:0] perf_core_writes_per_mask = core_req_valid & core_req_ready & core_req_rw; - - `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_mask); - `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_mask); - wire perf_crsp_stall_per_cycle = core_rsp_valid & ~core_rsp_ready; - - reg [`PERF_CTR_BITS-1:0] perf_core_reads; - reg [`PERF_CTR_BITS-1:0] perf_core_writes; - reg [`PERF_CTR_BITS-1:0] perf_crsp_stalls; - - always @(posedge clk) begin - if (reset) begin - perf_core_reads <= 0; - perf_core_writes <= 0; - perf_crsp_stalls <= 0; - end else begin - perf_core_reads <= perf_core_reads + `PERF_CTR_BITS'(perf_core_reads_per_cycle); - perf_core_writes <= perf_core_writes + `PERF_CTR_BITS'(perf_core_writes_per_cycle); - perf_crsp_stalls <= perf_crsp_stalls + `PERF_CTR_BITS'(perf_crsp_stall_per_cycle); - end - end - - assign perf_cache_if.reads = perf_core_reads; - assign perf_cache_if.writes = perf_core_writes; - assign perf_cache_if.read_misses = '0; - assign perf_cache_if.write_misses = '0; - assign perf_cache_if.mshr_stalls = '0; - assign perf_cache_if.mem_stalls = '0; - assign perf_cache_if.crsp_stalls = perf_crsp_stalls; -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_tag_access.sv b/hw/rtl/cache/VX_tag_access.sv deleted file mode 100644 index d8d2a4db..00000000 --- a/hw/rtl/cache/VX_tag_access.sv +++ /dev/null @@ -1,79 +0,0 @@ -`include "VX_cache_define.vh" - -module VX_tag_access #( - parameter CACHE_ID = 0, - parameter BANK_ID = 0, - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0 -) ( - input wire clk, - input wire reset, - -`IGNORE_UNUSED_BEGIN - input wire[`DBG_CACHE_REQ_IDW-1:0] req_id, -`IGNORE_UNUSED_END - - input wire stall, - - // read/fill - input wire lookup, - input wire[`LINE_ADDR_WIDTH-1:0] addr, - input wire fill, - input wire flush, - output wire tag_match -); - - `UNUSED_PARAM (CACHE_ID) - `UNUSED_PARAM (BANK_ID) - `UNUSED_VAR (reset) - `UNUSED_VAR (lookup) - - wire [`TAG_SELECT_BITS-1:0] read_tag; - wire read_valid; - - wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0]; - wire [`TAG_SELECT_BITS-1:0] line_tag = `LINE_TAG_ADDR(addr); - - VX_sp_ram #( - .DATAW (`TAG_SELECT_BITS + 1), - .SIZE (`LINES_PER_BANK), - .NO_RWCHECK (1) - ) tag_store ( - .clk( clk), - .addr (line_addr), - .wren (fill || flush), - .wdata ({!flush, line_tag}), - .rdata ({read_valid, read_tag}) - ); - - assign tag_match = read_valid && (line_tag == read_tag); - - `UNUSED_VAR (stall) - -`ifdef DBG_TRACE_CACHE_TAG - always @(posedge clk) begin - if (fill && ~stall) begin - dpi_trace("%d: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, line_tag); - end - if (flush) begin - dpi_trace("%d: cache%0d:%0d tag-flush: addr=%0h, blk_addr=%0d\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr); - end - if (lookup && ~stall) begin - if (tag_match) begin - dpi_trace("%d: cache%0d:%0d tag-hit: addr=%0h, blk_addr=%0d, tag_id=%0h (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, line_tag, req_id); - end else begin - dpi_trace("%d: cache%0d:%0d tag-miss: addr=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h (#%0d)\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, line_tag, read_tag, req_id); - end - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/core/VX_alu_unit.sv b/hw/rtl/core/VX_alu_unit.sv new file mode 100644 index 00000000..d2b38cf4 --- /dev/null +++ b/hw/rtl/core/VX_alu_unit.sv @@ -0,0 +1,172 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_alu_unit #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // Outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH], + VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS] +); + + `UNUSED_PARAM (CORE_ID) + localparam BLOCK_SIZE = `NUM_ALU_BLOCKS; + localparam NUM_LANES = `NUM_ALU_LANES; + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam RSP_ARB_DATAW= `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1; + localparam RSP_ARB_SIZE = 1 + `EXT_M_ENABLED; + localparam PARTIAL_BW = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `NUM_THREADS); + + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) execute_if[BLOCK_SIZE](); + + `RESET_RELAY (dispatch_reset, reset); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (PARTIAL_BW ? 1 : 0) + ) dispatch_unit ( + .clk (clk), + .reset (dispatch_reset), + .dispatch_if(dispatch_if), + .execute_if (execute_if) + ); + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) commit_block_if[BLOCK_SIZE](); + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin + + wire is_muldiv_op; + + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) int_execute_if(); + + assign int_execute_if.valid = execute_if[block_idx].valid && ~is_muldiv_op; + assign int_execute_if.data = execute_if[block_idx].data; + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) int_commit_if(); + + `RESET_RELAY (int_reset, reset); + + VX_int_unit #( + .CORE_ID (CORE_ID), + .BLOCK_IDX (block_idx), + .NUM_LANES (NUM_LANES) + ) int_unit ( + .clk (clk), + .reset (int_reset), + .execute_if (int_execute_if), + .branch_ctl_if (branch_ctl_if[block_idx]), + .commit_if (int_commit_if) + ); + + `ifdef EXT_M_ENABLE + + assign is_muldiv_op = `INST_ALU_IS_M(execute_if[block_idx].data.op_mod); + + `RESET_RELAY (mdv_reset, reset); + + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) mdv_execute_if(); + + assign mdv_execute_if.valid = execute_if[block_idx].valid && is_muldiv_op; + assign mdv_execute_if.data = execute_if[block_idx].data; + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) mdv_commit_if(); + + VX_muldiv_unit #( + .CORE_ID (CORE_ID), + .NUM_LANES (NUM_LANES) + ) mdv_unit ( + .clk (clk), + .reset (mdv_reset), + .execute_if (mdv_execute_if), + .commit_if (mdv_commit_if) + ); + + assign execute_if[block_idx].ready = is_muldiv_op ? mdv_execute_if.ready : int_execute_if.ready; + + `else + + assign is_muldiv_op = 0; + assign execute_if[block_idx].ready = int_execute_if.ready; + + `endif + + // send response + + VX_stream_arb #( + .NUM_INPUTS (RSP_ARB_SIZE), + .DATAW (RSP_ARB_DATAW), + .OUT_REG (PARTIAL_BW ? 1 : 3) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in ({ + `ifdef EXT_M_ENABLE + mdv_commit_if.valid, + `endif + int_commit_if.valid + }), + .ready_in ({ + `ifdef EXT_M_ENABLE + mdv_commit_if.ready, + `endif + int_commit_if.ready + }), + .data_in ({ + `ifdef EXT_M_ENABLE + mdv_commit_if.data, + `endif + int_commit_if.data + }), + .data_out (commit_block_if[block_idx].data), + .valid_out (commit_block_if[block_idx].valid), + .ready_out (commit_block_if[block_idx].ready), + `UNUSED_PIN (sel_out) + ); + end + + `RESET_RELAY (commit_reset, reset); + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (PARTIAL_BW ? 3 : 0) + ) gather_unit ( + .clk (clk), + .reset (commit_reset), + .commit_in_if (commit_block_if), + .commit_out_if (commit_if) + ); + +endmodule diff --git a/hw/rtl/core/VX_commit.sv b/hw/rtl/core/VX_commit.sv new file mode 100644 index 00000000..e5dbe97c --- /dev/null +++ b/hw/rtl/core/VX_commit.sv @@ -0,0 +1,226 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_commit import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_commit_if.slave alu_commit_if [`ISSUE_WIDTH], + VX_commit_if.slave lsu_commit_if [`ISSUE_WIDTH], +`ifdef EXT_F_ENABLE + VX_commit_if.slave fpu_commit_if [`ISSUE_WIDTH], +`endif + VX_commit_if.slave sfu_commit_if [`ISSUE_WIDTH], + + // outputs + VX_writeback_if.master writeback_if [`ISSUE_WIDTH], + VX_commit_csr_if.master commit_csr_if, + VX_commit_sched_if.master commit_sched_if, + + // simulation helper signals + output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value +); + `UNUSED_PARAM (CORE_ID) + localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `XLEN + 1 + `NR_BITS + `NUM_THREADS * `XLEN + 1 + 1 + 1; + localparam COMMIT_SIZEW = `CLOG2(`NUM_THREADS + 1); + localparam COMMIT_ALL_SIZEW = COMMIT_SIZEW + `ISSUE_WIDTH - 1; + + // commit arbitration + + VX_commit_if commit_if[`ISSUE_WIDTH](); + + wire [`ISSUE_WIDTH-1:0] commit_fire; + wire [`ISSUE_WIDTH-1:0][`NW_WIDTH-1:0] commit_wid; + wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] commit_tmask; + wire [`ISSUE_WIDTH-1:0] commit_eop; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + + `RESET_RELAY (arb_reset, reset); + + VX_stream_arb #( + .NUM_INPUTS (`NUM_EX_UNITS), + .DATAW (DATAW), + .ARBITER ("R"), + .OUT_REG (1) + ) commit_arb ( + .clk (clk), + .reset (arb_reset), + .valid_in ({ + sfu_commit_if[i].valid, + `ifdef EXT_F_ENABLE + fpu_commit_if[i].valid, + `endif + alu_commit_if[i].valid, + lsu_commit_if[i].valid + }), + .ready_in ({ + sfu_commit_if[i].ready, + `ifdef EXT_F_ENABLE + fpu_commit_if[i].ready, + `endif + alu_commit_if[i].ready, + lsu_commit_if[i].ready + }), + .data_in ({ + sfu_commit_if[i].data, + `ifdef EXT_F_ENABLE + fpu_commit_if[i].data, + `endif + alu_commit_if[i].data, + lsu_commit_if[i].data + }), + .data_out (commit_if[i].data), + .valid_out (commit_if[i].valid), + .ready_out (commit_if[i].ready), + `UNUSED_PIN (sel_out) + ); + + assign commit_fire[i] = commit_if[i].valid && commit_if[i].ready; + assign commit_tmask[i] = {`NUM_THREADS{commit_fire[i]}} & commit_if[i].data.tmask; + assign commit_wid[i] = commit_if[i].data.wid; + assign commit_eop[i] = commit_if[i].data.eop; + end + + // CSRs update + + wire [`ISSUE_WIDTH-1:0][COMMIT_SIZEW-1:0] commit_size, commit_size_r; + wire [COMMIT_ALL_SIZEW-1:0] commit_size_all, commit_size_all_r; + wire commit_fire_any, commit_fire_any_r, commit_fire_any_rr; + + assign commit_fire_any = (| commit_fire); + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + wire [COMMIT_SIZEW-1:0] pop_count; + `POP_COUNT(pop_count, commit_tmask[i]); + assign commit_size[i] = pop_count; + end + + VX_pipe_register #( + .DATAW (1 + `ISSUE_WIDTH * COMMIT_SIZEW), + .RESETW (1) + ) commit_size_reg1 ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({commit_fire_any, commit_size}), + .data_out ({commit_fire_any_r, commit_size_r}) + ); + + VX_reduce #( + .DATAW_IN (COMMIT_SIZEW), + .DATAW_OUT (COMMIT_ALL_SIZEW), + .N (`ISSUE_WIDTH), + .OP ("+") + ) commit_size_reduce ( + .data_in (commit_size_r), + .data_out (commit_size_all) + ); + + VX_pipe_register #( + .DATAW (1 + COMMIT_ALL_SIZEW), + .RESETW (1) + ) commit_size_reg2 ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({commit_fire_any_r, commit_size_all}), + .data_out ({commit_fire_any_rr, commit_size_all_r}) + ); + + reg [`PERF_CTR_BITS-1:0] instret; + + always @(posedge clk) begin + if (reset) begin + instret <= '0; + end else begin + if (commit_fire_any_rr) begin + instret <= instret + `PERF_CTR_BITS'(commit_size_all_r); + end + end + end + + assign commit_csr_if.instret = instret; + + // Committed instructions + + VX_pipe_register #( + .DATAW (`ISSUE_WIDTH * (1 + `NW_WIDTH)), + .RESETW (`ISSUE_WIDTH) + ) committed_pipe_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({(commit_fire & commit_eop), commit_wid}), + .data_out ({commit_sched_if.committed, commit_sched_if.committed_wid}) + ); + + // Writeback + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + assign writeback_if[i].valid = commit_if[i].valid && commit_if[i].data.wb; + assign writeback_if[i].data.uuid = commit_if[i].data.uuid; + assign writeback_if[i].data.wis = wid_to_wis(commit_if[i].data.wid); + assign writeback_if[i].data.PC = commit_if[i].data.PC; + assign writeback_if[i].data.tmask = commit_if[i].data.tmask; + assign writeback_if[i].data.rd = commit_if[i].data.rd; + assign writeback_if[i].data.data = commit_if[i].data.data; + assign writeback_if[i].data.sop = commit_if[i].data.sop; + assign writeback_if[i].data.eop = commit_if[i].data.eop; + assign commit_if[i].ready = 1'b1; + end + + // simulation helper signal to get RISC-V tests Pass/Fail status + reg [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value_r; + always @(posedge clk) begin + if (writeback_if[0].valid) begin + sim_wb_value_r[writeback_if[0].data.rd] <= writeback_if[0].data.data[0]; + end + end + assign sim_wb_value = sim_wb_value_r; + +`ifdef DBG_TRACE_CORE_PIPELINE + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + always @(posedge clk) begin + if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin + `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, alu_commit_if[i].data.wid, alu_commit_if[i].data.PC, alu_commit_if[i].data.tmask, alu_commit_if[i].data.wb, alu_commit_if[i].data.rd, alu_commit_if[i].data.sop, alu_commit_if[i].data.eop)); + `TRACE_ARRAY1D(1, alu_commit_if[i].data.data, `NUM_THREADS); + `TRACE(1, (" (#%0d)\n", alu_commit_if[i].data.uuid)); + end + if (lsu_commit_if[i].valid && lsu_commit_if[i].ready) begin + `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, lsu_commit_if[i].data.wid, lsu_commit_if[i].data.PC, lsu_commit_if[i].data.tmask, lsu_commit_if[i].data.wb, lsu_commit_if[i].data.rd, lsu_commit_if[i].data.sop, lsu_commit_if[i].data.eop)); + `TRACE_ARRAY1D(1, lsu_commit_if[i].data.data, `NUM_THREADS); + `TRACE(1, (" (#%0d)\n", lsu_commit_if[i].data.uuid)); + end + `ifdef EXT_F_ENABLE + if (fpu_commit_if[i].valid && fpu_commit_if[i].ready) begin + `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, fpu_commit_if[i].data.wid, fpu_commit_if[i].data.PC, fpu_commit_if[i].data.tmask, fpu_commit_if[i].data.wb, fpu_commit_if[i].data.rd, fpu_commit_if[i].data.sop, fpu_commit_if[i].data.eop)); + `TRACE_ARRAY1D(1, fpu_commit_if[i].data.data, `NUM_THREADS); + `TRACE(1, (" (#%0d)\n", fpu_commit_if[i].data.uuid)); + end + `endif + if (sfu_commit_if[i].valid && sfu_commit_if[i].ready) begin + `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=SFU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, sfu_commit_if[i].data.wid, sfu_commit_if[i].data.PC, sfu_commit_if[i].data.tmask, sfu_commit_if[i].data.wb, sfu_commit_if[i].data.rd, sfu_commit_if[i].data.sop, sfu_commit_if[i].data.eop)); + `TRACE_ARRAY1D(1, sfu_commit_if[i].data.data, `NUM_THREADS); + `TRACE(1, (" (#%0d)\n", sfu_commit_if[i].data.uuid)); + end + end + end +`endif + +endmodule diff --git a/hw/rtl/core/VX_core.sv b/hw/rtl/core/VX_core.sv new file mode 100644 index 00000000..01795634 --- /dev/null +++ b/hw/rtl/core/VX_core.sv @@ -0,0 +1,469 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`ifdef EXT_F_ENABLE +`include "VX_fpu_define.vh" +`endif + +module VX_core import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + `SCOPE_IO_DECL + + // Clock + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + VX_mem_perf_if.slave mem_perf_if, +`endif + + VX_dcr_bus_if.slave dcr_bus_if, + + VX_mem_bus_if.master dcache_bus_if [DCACHE_NUM_REQS], + + VX_mem_bus_if.master icache_bus_if, + +`ifdef GBAR_ENABLE + VX_gbar_bus_if.master gbar_bus_if, +`endif + + // simulation helper signals + output wire sim_ebreak, + output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value, + + // Status + output wire busy +); + VX_schedule_if schedule_if(); + VX_fetch_if fetch_if(); + VX_decode_if decode_if(); + VX_sched_csr_if sched_csr_if(); + VX_decode_sched_if decode_sched_if(); + VX_commit_sched_if commit_sched_if(); + VX_commit_csr_if commit_csr_if(); + VX_branch_ctl_if branch_ctl_if[`NUM_ALU_BLOCKS](); + VX_warp_ctl_if warp_ctl_if(); + + VX_dispatch_if alu_dispatch_if[`ISSUE_WIDTH](); + VX_commit_if alu_commit_if[`ISSUE_WIDTH](); + + VX_dispatch_if lsu_dispatch_if[`ISSUE_WIDTH](); + VX_commit_if lsu_commit_if[`ISSUE_WIDTH](); +`ifdef EXT_F_ENABLE + VX_dispatch_if fpu_dispatch_if[`ISSUE_WIDTH](); + VX_commit_if fpu_commit_if[`ISSUE_WIDTH](); +`endif + VX_dispatch_if sfu_dispatch_if[`ISSUE_WIDTH](); + VX_commit_if sfu_commit_if[`ISSUE_WIDTH](); + + VX_writeback_if writeback_if[`ISSUE_WIDTH](); + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH) + ) dcache_bus_tmp_if[DCACHE_NUM_REQS](); + +`ifdef PERF_ENABLE + VX_mem_perf_if mem_perf_tmp_if(); + VX_pipeline_perf_if pipeline_perf_if(); +`endif + + `RESET_RELAY (dcr_data_reset, reset); + `RESET_RELAY (schedule_reset, reset); + `RESET_RELAY (fetch_reset, reset); + `RESET_RELAY (decode_reset, reset); + `RESET_RELAY (issue_reset, reset); + `RESET_RELAY (execute_reset, reset); + `RESET_RELAY (commit_reset, reset); + + base_dcrs_t base_dcrs; + + VX_dcr_data dcr_data ( + .clk (clk), + .reset (dcr_data_reset), + .dcr_bus_if (dcr_bus_if), + .base_dcrs (base_dcrs) + ); + + `SCOPE_IO_SWITCH (3) + + VX_schedule #( + .CORE_ID (CORE_ID) + ) schedule ( + .clk (clk), + .reset (schedule_reset), + + .base_dcrs (base_dcrs), + + .warp_ctl_if (warp_ctl_if), + .branch_ctl_if (branch_ctl_if), + .decode_sched_if(decode_sched_if), + .commit_sched_if(commit_sched_if), + + .schedule_if (schedule_if), + `ifdef GBAR_ENABLE + .gbar_bus_if (gbar_bus_if), + `endif + .sched_csr_if (sched_csr_if), + + .busy (busy) + ); + + VX_fetch #( + .CORE_ID (CORE_ID) + ) fetch ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (fetch_reset), + .icache_bus_if (icache_bus_if), + .schedule_if (schedule_if), + .fetch_if (fetch_if) + ); + + VX_decode #( + .CORE_ID (CORE_ID) + ) decode ( + .clk (clk), + .reset (decode_reset), + .fetch_if (fetch_if), + .decode_if (decode_if), + .decode_sched_if(decode_sched_if) + ); + + VX_issue #( + .CORE_ID (CORE_ID) + ) issue ( + `SCOPE_IO_BIND (1) + + .clk (clk), + .reset (issue_reset), + + `ifdef PERF_ENABLE + .perf_issue_if (pipeline_perf_if.issue), + `endif + + .decode_if (decode_if), + .writeback_if (writeback_if), + + .alu_dispatch_if(alu_dispatch_if), + .lsu_dispatch_if(lsu_dispatch_if), + `ifdef EXT_F_ENABLE + .fpu_dispatch_if(fpu_dispatch_if), + `endif + .sfu_dispatch_if(sfu_dispatch_if) + ); + + VX_execute #( + .CORE_ID (CORE_ID) + ) execute ( + `SCOPE_IO_BIND (2) + + .clk (clk), + .reset (execute_reset), + + .base_dcrs (base_dcrs), + + `ifdef PERF_ENABLE + .mem_perf_if (mem_perf_tmp_if), + .pipeline_perf_if(pipeline_perf_if), + `endif + + .dcache_bus_if (dcache_bus_tmp_if), + + `ifdef EXT_F_ENABLE + .fpu_dispatch_if(fpu_dispatch_if), + .fpu_commit_if (fpu_commit_if), + `endif + + .commit_csr_if (commit_csr_if), + .sched_csr_if (sched_csr_if), + + .alu_dispatch_if(alu_dispatch_if), + .lsu_dispatch_if(lsu_dispatch_if), + .sfu_dispatch_if(sfu_dispatch_if), + + .warp_ctl_if (warp_ctl_if), + .branch_ctl_if (branch_ctl_if), + + .alu_commit_if (alu_commit_if), + .lsu_commit_if (lsu_commit_if), + .sfu_commit_if (sfu_commit_if), + + .sim_ebreak (sim_ebreak) + ); + + VX_commit #( + .CORE_ID (CORE_ID) + ) commit ( + .clk (clk), + .reset (commit_reset), + + .alu_commit_if (alu_commit_if), + .lsu_commit_if (lsu_commit_if), + `ifdef EXT_F_ENABLE + .fpu_commit_if (fpu_commit_if), + `endif + .sfu_commit_if (sfu_commit_if), + + .writeback_if (writeback_if), + + .commit_csr_if (commit_csr_if), + .commit_sched_if(commit_sched_if), + + .sim_wb_value (sim_wb_value) + ); + + VX_smem_unit #( + .CORE_ID (CORE_ID) + ) smem_unit ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .mem_perf_in_if (mem_perf_if), + .mem_perf_out_if (mem_perf_tmp_if), + `endif + .dcache_bus_in_if (dcache_bus_tmp_if), + .dcache_bus_out_if (dcache_bus_if) + ); + +`ifdef PERF_ENABLE + + wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rd_req_per_cycle; + wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_wr_req_per_cycle; + + wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rsp_per_cycle; + + wire perf_icache_pending_read_cycle; + wire [`CLOG2(DCACHE_NUM_REQS+1)+1-1:0] perf_dcache_pending_read_cycle; + + reg [`PERF_CTR_BITS-1:0] perf_icache_pending_reads; + reg [`PERF_CTR_BITS-1:0] perf_dcache_pending_reads; + + reg [`PERF_CTR_BITS-1:0] perf_ifetches; + reg [`PERF_CTR_BITS-1:0] perf_loads; + reg [`PERF_CTR_BITS-1:0] perf_stores; + + wire perf_icache_req_fire = icache_bus_if.req_valid & icache_bus_if.req_ready; + wire perf_icache_rsp_fire = icache_bus_if.rsp_valid & icache_bus_if.rsp_ready; + + wire [DCACHE_NUM_REQS-1:0] perf_dcache_rd_req_fire, perf_dcache_wr_req_fire, perf_dcache_rsp_fire; + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + assign perf_dcache_rd_req_fire[i] = dcache_bus_if[i].req_valid && ~dcache_bus_if[i].req_data.rw && dcache_bus_if[i].req_ready; + assign perf_dcache_wr_req_fire[i] = dcache_bus_if[i].req_valid && dcache_bus_if[i].req_data.rw && dcache_bus_if[i].req_ready; + assign perf_dcache_rsp_fire[i] = dcache_bus_if[i].rsp_valid && dcache_bus_if[i].rsp_ready; + end + + `POP_COUNT(perf_dcache_rd_req_per_cycle, perf_dcache_rd_req_fire); + `POP_COUNT(perf_dcache_wr_req_per_cycle, perf_dcache_wr_req_fire); + `POP_COUNT(perf_dcache_rsp_per_cycle, perf_dcache_rsp_fire); + + assign perf_icache_pending_read_cycle = perf_icache_req_fire - perf_icache_rsp_fire; + assign perf_dcache_pending_read_cycle = perf_dcache_rd_req_per_cycle - perf_dcache_rsp_per_cycle; + + always @(posedge clk) begin + if (reset) begin + perf_icache_pending_reads <= '0; + perf_dcache_pending_reads <= '0; + end else begin + perf_icache_pending_reads <= $signed(perf_icache_pending_reads) + `PERF_CTR_BITS'($signed(perf_icache_pending_read_cycle)); + perf_dcache_pending_reads <= $signed(perf_dcache_pending_reads) + `PERF_CTR_BITS'($signed(perf_dcache_pending_read_cycle)); + end + end + + reg [`PERF_CTR_BITS-1:0] perf_icache_lat; + reg [`PERF_CTR_BITS-1:0] perf_dcache_lat; + + always @(posedge clk) begin + if (reset) begin + perf_ifetches <= '0; + perf_loads <= '0; + perf_stores <= '0; + perf_icache_lat <= '0; + perf_dcache_lat <= '0; + end else begin + perf_ifetches <= perf_ifetches + `PERF_CTR_BITS'(perf_icache_req_fire); + perf_loads <= perf_loads + `PERF_CTR_BITS'(perf_dcache_rd_req_per_cycle); + perf_stores <= perf_stores + `PERF_CTR_BITS'(perf_dcache_wr_req_per_cycle); + perf_icache_lat <= perf_icache_lat + perf_icache_pending_reads; + perf_dcache_lat <= perf_dcache_lat + perf_dcache_pending_reads; + end + end + + assign pipeline_perf_if.ifetches = perf_ifetches; + assign pipeline_perf_if.loads = perf_loads; + assign pipeline_perf_if.stores = perf_stores; + assign pipeline_perf_if.load_latency = perf_dcache_lat; + assign pipeline_perf_if.ifetch_latency = perf_icache_lat; + assign pipeline_perf_if.load_latency = perf_dcache_lat; + +`endif + +endmodule + +/////////////////////////////////////////////////////////////////////////////// + +module VX_core_top +import VX_gpu_pkg::*; +#( + parameter CORE_ID = 0 +) ( + // Clock + input wire clk, + input wire reset, + + input wire dcr_write_valid, + input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_write_addr, + input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_write_data, + + output wire [DCACHE_NUM_REQS-1:0] dcache_req_valid, + output wire [DCACHE_NUM_REQS-1:0] dcache_req_rw, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] dcache_req_byteen, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] dcache_req_addr, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_req_data, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_req_tag, + input wire [DCACHE_NUM_REQS-1:0] dcache_req_ready, + + input wire [DCACHE_NUM_REQS-1:0] dcache_rsp_valid, + input wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_rsp_data, + input wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_rsp_tag, + output wire [DCACHE_NUM_REQS-1:0] dcache_rsp_ready, + + output wire icache_req_valid, + output wire icache_req_rw, + output wire [ICACHE_WORD_SIZE-1:0] icache_req_byteen, + output wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr, + output wire [ICACHE_WORD_SIZE*8-1:0] icache_req_data, + output wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag, + input wire icache_req_ready, + + input wire icache_rsp_valid, + input wire [ICACHE_WORD_SIZE*8-1:0] icache_rsp_data, + input wire [ICACHE_TAG_WIDTH-1:0] icache_rsp_tag, + output wire icache_rsp_ready, + +`ifdef GBAR_ENABLE + output wire gbar_req_valid, + output wire [`NB_WIDTH-1:0] gbar_req_id, + output wire [`NC_WIDTH-1:0] gbar_req_size_m1, + output wire [`NC_WIDTH-1:0] gbar_req_core_id, + input wire gbar_req_ready, + input wire gbar_rsp_valid, + input wire [`NB_WIDTH-1:0] gbar_rsp_id, +`endif + + // simulation helper signals + output wire sim_ebreak, + output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value, + + // Status + output wire busy +); + +`ifdef GBAR_ENABLE + VX_gbar_bus_if gbar_bus_if(); + + assign gbar_req_valid = gbar_bus_if.req_valid; + assign gbar_req_id = gbar_bus_if.req_id; + assign gbar_req_size_m1 = gbar_bus_if.req_size_m1; + assign gbar_req_core_id = gbar_bus_if.req_core_id; + assign gbar_bus_if.req_ready = gbar_req_ready; + assign gbar_bus_if.rsp_valid = gbar_rsp_valid; + assign gbar_bus_if.rsp_id = gbar_rsp_id; +`endif + + VX_dcr_bus_if dcr_bus_if(); + + assign dcr_bus_if.write_valid = dcr_write_valid; + assign dcr_bus_if.write_addr = dcr_write_addr; + assign dcr_bus_if.write_data = dcr_write_data; + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH) + ) dcache_bus_if[DCACHE_NUM_REQS](); + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + assign dcache_req_valid[i] = dcache_bus_if[i].req_valid; + assign dcache_req_rw[i] = dcache_bus_if[i].req_data.rw; + assign dcache_req_byteen[i] = dcache_bus_if[i].req_data.byteen; + assign dcache_req_addr[i] = dcache_bus_if[i].req_data.addr; + assign dcache_req_data[i] = dcache_bus_if[i].req_data.data; + assign dcache_req_tag[i] = dcache_bus_if[i].req_data.tag; + assign dcache_bus_if[i].req_ready = dcache_req_ready[i]; + + assign dcache_bus_if[i].rsp_valid = dcache_rsp_valid[i]; + assign dcache_bus_if[i].rsp_data.tag = dcache_rsp_tag[i]; + assign dcache_bus_if[i].rsp_data.data = dcache_rsp_data[i]; + assign dcache_rsp_ready[i] = dcache_bus_if[i].rsp_ready; + end + + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_WORD_SIZE), + .TAG_WIDTH (ICACHE_TAG_WIDTH) + ) icache_bus_if(); + + assign icache_req_valid = icache_bus_if.req_valid; + assign icache_req_rw = icache_bus_if.req_data.rw; + assign icache_req_byteen = icache_bus_if.req_data.byteen; + assign icache_req_addr = icache_bus_if.req_data.addr; + assign icache_req_data = icache_bus_if.req_data.data; + assign icache_req_tag = icache_bus_if.req_data.tag; + assign icache_bus_if.req_ready = icache_req_ready; + + assign icache_bus_if.rsp_valid = icache_rsp_valid; + assign icache_bus_if.rsp_data.tag = icache_rsp_tag; + assign icache_bus_if.rsp_data.data = icache_rsp_data; + assign icache_rsp_ready = icache_bus_if.rsp_ready; + +`ifdef PERF_ENABLE + VX_mem_perf_if mem_perf_if(); +`endif + +`ifdef SCOPE + wire [0:0] scope_reset_w = 1'b0; + wire [0:0] scope_bus_in_w = 1'b0; + wire [0:0] scope_bus_out_w; + `UNUSED_VAR (scope_bus_out_w) +`endif + + VX_core #( + .CORE_ID (0) + ) core ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .mem_perf_if (mem_perf_if), + `endif + + .dcr_bus_if (dcr_bus_if), + + .dcache_bus_if (dcache_bus_if), + + .icache_bus_if (icache_bus_if), + + `ifdef GBAR_ENABLE + .gbar_bus_if (gbar_bus_if), + `endif + + .sim_ebreak (sim_ebreak), + .sim_wb_value (sim_wb_value), + .busy (busy) + ); + +endmodule diff --git a/hw/rtl/core/VX_csr_data.sv b/hw/rtl/core/VX_csr_data.sv new file mode 100644 index 00000000..0b492ba4 --- /dev/null +++ b/hw/rtl/core/VX_csr_data.sv @@ -0,0 +1,304 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`ifdef EXT_F_ENABLE +`include "VX_fpu_define.vh" +`endif + +module VX_csr_data +import VX_gpu_pkg::*; +`ifdef EXT_F_ENABLE +import VX_fpu_pkg::*; +`endif +#( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + input base_dcrs_t base_dcrs, + +`ifdef PERF_ENABLE + VX_mem_perf_if.slave mem_perf_if, + VX_pipeline_perf_if.slave pipeline_perf_if, + VX_sfu_perf_if.slave sfu_perf_if, +`endif + + VX_commit_csr_if.slave commit_csr_if, + +`ifdef EXT_F_ENABLE + VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS], +`endif + + input wire [`PERF_CTR_BITS-1:0] cycles, + input wire [`NUM_WARPS-1:0] active_warps, + input wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks, + + input wire read_enable, + input wire [`UUID_WIDTH-1:0] read_uuid, + input wire [`NW_WIDTH-1:0] read_wid, + input wire [`VX_CSR_ADDR_BITS-1:0] read_addr, + output wire [31:0] read_data_ro, + output wire [31:0] read_data_rw, + + input wire write_enable, + input wire [`UUID_WIDTH-1:0] write_uuid, + input wire [`NW_WIDTH-1:0] write_wid, + input wire [`VX_CSR_ADDR_BITS-1:0] write_addr, + input wire [31:0] write_data +); + + `UNUSED_VAR (reset) + `UNUSED_VAR (write_wid) + `UNUSED_VAR (write_data) + + // CSRs Write ///////////////////////////////////////////////////////////// + +`ifdef EXT_F_ENABLE + reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FP_FLAGS_BITS-1:0] fcsr, fcsr_n; + wire [`NUM_FPU_BLOCKS-1:0] fpu_write_enable; + wire [`NUM_FPU_BLOCKS-1:0][`NW_WIDTH-1:0] fpu_write_wid; + fflags_t [`NUM_FPU_BLOCKS-1:0] fpu_write_fflags; + for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin + assign fpu_write_enable[i] = fpu_to_csr_if[i].write_enable; + assign fpu_write_wid[i] = fpu_to_csr_if[i].write_wid; + assign fpu_write_fflags[i] = fpu_to_csr_if[i].write_fflags; + end + always @(*) begin + fcsr_n = fcsr; + for (integer i = 0; i < `NUM_FPU_BLOCKS; ++i) begin + if (fpu_write_enable[i]) begin + fcsr_n[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0] = fcsr[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0] + | fpu_write_fflags[i]; + end + end + if (write_enable) begin + case (write_addr) + `VX_CSR_FFLAGS: fcsr_n[write_wid][`FP_FLAGS_BITS-1:0] = write_data[`FP_FLAGS_BITS-1:0]; + `VX_CSR_FRM: fcsr_n[write_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS] = write_data[`INST_FRM_BITS-1:0]; + `VX_CSR_FCSR: fcsr_n[write_wid] = write_data[`FP_FLAGS_BITS+`INST_FRM_BITS-1:0]; + default:; + endcase + end + end + + for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin + assign fpu_to_csr_if[i].read_frm = fcsr[fpu_to_csr_if[i].read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]; + end + + always @(posedge clk) begin + if (reset) begin + fcsr <= '0; + end else begin + fcsr <= fcsr_n; + end + end +`endif + + always @(posedge clk) begin + if (write_enable) begin + case (write_addr) + `ifdef EXT_F_ENABLE + `VX_CSR_FFLAGS, + `VX_CSR_FRM, + `VX_CSR_FCSR, + `endif + `VX_CSR_SATP, + `VX_CSR_MSTATUS, + `VX_CSR_MNSTATUS, + `VX_CSR_MEDELEG, + `VX_CSR_MIDELEG, + `VX_CSR_MIE, + `VX_CSR_MTVEC, + `VX_CSR_MEPC, + `VX_CSR_PMPCFG0, + `VX_CSR_PMPADDR0: /* do nothing!*/; + default: begin + `ASSERT(0, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid)); + end + endcase + end + end + + // CSRs read ////////////////////////////////////////////////////////////// + + reg [31:0] read_data_ro_r; + reg [31:0] read_data_rw_r; + reg read_addr_valid_r; + + always @(*) begin + read_data_ro_r = '0; + read_data_rw_r = '0; + read_addr_valid_r = 1; + case (read_addr) + `VX_CSR_MVENDORID : read_data_ro_r = 32'(`VENDOR_ID); + `VX_CSR_MARCHID : read_data_ro_r = 32'(`ARCHITECTURE_ID); + `VX_CSR_MIMPID : read_data_ro_r = 32'(`IMPLEMENTATION_ID); + `VX_CSR_MISA : read_data_ro_r = (((`CLOG2(`XLEN)-4) << (`XLEN-2)) | `MISA_STD); + `ifdef EXT_F_ENABLE + `VX_CSR_FFLAGS : read_data_rw_r = 32'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]); + `VX_CSR_FRM : read_data_rw_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]); + `VX_CSR_FCSR : read_data_rw_r = 32'(fcsr[read_wid]); + `endif + `VX_CSR_WARP_ID : read_data_ro_r = 32'(read_wid); + `VX_CSR_CORE_ID : read_data_ro_r = 32'(CORE_ID); + `VX_CSR_THREAD_MASK: read_data_ro_r = 32'(thread_masks[read_wid]); + `VX_CSR_WARP_MASK : read_data_ro_r = 32'(active_warps); + `VX_CSR_NUM_THREADS: read_data_ro_r = 32'(`NUM_THREADS); + `VX_CSR_NUM_WARPS : read_data_ro_r = 32'(`NUM_WARPS); + `VX_CSR_NUM_CORES : read_data_ro_r = 32'(`NUM_CORES * `NUM_CLUSTERS); + `VX_CSR_MCYCLE : read_data_ro_r = 32'(cycles[31:0]); + `VX_CSR_MCYCLE_H : read_data_ro_r = 32'(cycles[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_RESERVED : read_data_ro_r = 'x; + `VX_CSR_MPM_RESERVED_H : read_data_ro_r = 'x; + `VX_CSR_MINSTRET : read_data_ro_r = 32'(commit_csr_if.instret[31:0]); + `VX_CSR_MINSTRET_H : read_data_ro_r = 32'(commit_csr_if.instret[`PERF_CTR_BITS-1:32]); + + `VX_CSR_SATP, + `VX_CSR_MSTATUS, + `VX_CSR_MNSTATUS, + `VX_CSR_MEDELEG, + `VX_CSR_MIDELEG, + `VX_CSR_MIE, + `VX_CSR_MTVEC, + `VX_CSR_MEPC, + `VX_CSR_PMPCFG0, + `VX_CSR_PMPADDR0 : read_data_ro_r = 32'(0); + + default: begin + read_addr_valid_r = 0; + if ((read_addr >= `VX_CSR_MPM_BASE && read_addr < (`VX_CSR_MPM_BASE + 32)) + || (read_addr >= `VX_CSR_MPM_BASE_H && read_addr < (`VX_CSR_MPM_BASE_H + 32))) begin + read_addr_valid_r = 1; + `ifdef PERF_ENABLE + case (base_dcrs.mpm_class) + `VX_DCR_MPM_CLASS_CORE: begin + case (read_addr) + // PERF: pipeline + `VX_CSR_MPM_IBUF_ST : read_data_ro_r = pipeline_perf_if.ibf_stalls[31:0]; + `VX_CSR_MPM_IBUF_ST_H : read_data_ro_r = 32'(pipeline_perf_if.ibf_stalls[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_SCRB_ST : read_data_ro_r = pipeline_perf_if.scb_stalls[31:0]; + `VX_CSR_MPM_SCRB_ST_H : read_data_ro_r = 32'(pipeline_perf_if.scb_stalls[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_ALU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_ALU][31:0]; + `VX_CSR_MPM_ALU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_ALU][`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_LSU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_LSU][31:0]; + `VX_CSR_MPM_LSU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_LSU][`PERF_CTR_BITS-1:32]); + `ifdef EXT_F_ENABLE + `VX_CSR_MPM_FPU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_FPU][31:0]; + `VX_CSR_MPM_FPU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_FPU][`PERF_CTR_BITS-1:32]); + `else + `VX_CSR_MPM_FPU_ST : read_data_ro_r = '0; + `VX_CSR_MPM_FPU_ST_H : read_data_ro_r = '0; + `endif + `VX_CSR_MPM_SFU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_SFU][31:0]; + `VX_CSR_MPM_SFU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_SFU][`PERF_CTR_BITS-1:32]); + // PERF: memory + `VX_CSR_MPM_IFETCHES : read_data_ro_r = pipeline_perf_if.ifetches[31:0]; + `VX_CSR_MPM_IFETCHES_H : read_data_ro_r = 32'(pipeline_perf_if.ifetches[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_LOADS : read_data_ro_r = pipeline_perf_if.loads[31:0]; + `VX_CSR_MPM_LOADS_H : read_data_ro_r = 32'(pipeline_perf_if.loads[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_STORES : read_data_ro_r = pipeline_perf_if.stores[31:0]; + `VX_CSR_MPM_STORES_H : read_data_ro_r = 32'(pipeline_perf_if.stores[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_IFETCH_LAT : read_data_ro_r = pipeline_perf_if.ifetch_latency[31:0]; + `VX_CSR_MPM_IFETCH_LAT_H : read_data_ro_r = 32'(pipeline_perf_if.ifetch_latency[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_LOAD_LAT : read_data_ro_r = pipeline_perf_if.load_latency[31:0]; + `VX_CSR_MPM_LOAD_LAT_H : read_data_ro_r = 32'(pipeline_perf_if.load_latency[`PERF_CTR_BITS-1:32]); + default:; + endcase + end + `VX_DCR_MPM_CLASS_MEM: begin + case (read_addr) + // PERF: icache + `VX_CSR_MPM_ICACHE_READS : read_data_ro_r = mem_perf_if.icache_reads[31:0]; + `VX_CSR_MPM_ICACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.icache_reads[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_ICACHE_MISS_R : read_data_ro_r = mem_perf_if.icache_read_misses[31:0]; + `VX_CSR_MPM_ICACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.icache_read_misses[`PERF_CTR_BITS-1:32]); + // PERF: dcache + `VX_CSR_MPM_DCACHE_READS : read_data_ro_r = mem_perf_if.dcache_reads[31:0]; + `VX_CSR_MPM_DCACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.dcache_reads[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_DCACHE_WRITES : read_data_ro_r = mem_perf_if.dcache_writes[31:0]; + `VX_CSR_MPM_DCACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.dcache_writes[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_DCACHE_MISS_R : read_data_ro_r = mem_perf_if.dcache_read_misses[31:0]; + `VX_CSR_MPM_DCACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.dcache_read_misses[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_DCACHE_MISS_W : read_data_ro_r = mem_perf_if.dcache_write_misses[31:0]; + `VX_CSR_MPM_DCACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.dcache_write_misses[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_DCACHE_BANK_ST : read_data_ro_r = mem_perf_if.dcache_bank_stalls[31:0]; + `VX_CSR_MPM_DCACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.dcache_bank_stalls[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_DCACHE_MSHR_ST : read_data_ro_r = mem_perf_if.dcache_mshr_stalls[31:0]; + `VX_CSR_MPM_DCACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.dcache_mshr_stalls[`PERF_CTR_BITS-1:32]); + // PERF: smem + `VX_CSR_MPM_SMEM_READS : read_data_ro_r = mem_perf_if.smem_reads[31:0]; + `VX_CSR_MPM_SMEM_READS_H : read_data_ro_r = 32'(mem_perf_if.smem_reads[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_SMEM_WRITES : read_data_ro_r = mem_perf_if.smem_writes[31:0]; + `VX_CSR_MPM_SMEM_WRITES_H : read_data_ro_r = 32'(mem_perf_if.smem_writes[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_SMEM_BANK_ST : read_data_ro_r = mem_perf_if.smem_bank_stalls[31:0]; + `VX_CSR_MPM_SMEM_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.smem_bank_stalls[`PERF_CTR_BITS-1:32]); + // PERF: l2cache + `VX_CSR_MPM_L2CACHE_READS : read_data_ro_r = mem_perf_if.l2cache_reads[31:0]; + `VX_CSR_MPM_L2CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l2cache_reads[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L2CACHE_WRITES : read_data_ro_r = mem_perf_if.l2cache_writes[31:0]; + `VX_CSR_MPM_L2CACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.l2cache_writes[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L2CACHE_MISS_R : read_data_ro_r = mem_perf_if.l2cache_read_misses[31:0]; + `VX_CSR_MPM_L2CACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.l2cache_read_misses[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L2CACHE_MISS_W : read_data_ro_r = mem_perf_if.l2cache_write_misses[31:0]; + `VX_CSR_MPM_L2CACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.l2cache_write_misses[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L2CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l2cache_bank_stalls[31:0]; + `VX_CSR_MPM_L2CACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.l2cache_bank_stalls[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L2CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l2cache_mshr_stalls[31:0]; + `VX_CSR_MPM_L2CACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.l2cache_mshr_stalls[`PERF_CTR_BITS-1:32]); + // PERF: l3cache + `VX_CSR_MPM_L3CACHE_READS : read_data_ro_r = mem_perf_if.l3cache_reads[31:0]; + `VX_CSR_MPM_L3CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l3cache_reads[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L3CACHE_WRITES : read_data_ro_r = mem_perf_if.l3cache_writes[31:0]; + `VX_CSR_MPM_L3CACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.l3cache_writes[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L3CACHE_MISS_R : read_data_ro_r = mem_perf_if.l3cache_read_misses[31:0]; + `VX_CSR_MPM_L3CACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.l3cache_read_misses[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L3CACHE_MISS_W : read_data_ro_r = mem_perf_if.l3cache_write_misses[31:0]; + `VX_CSR_MPM_L3CACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.l3cache_write_misses[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L3CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l3cache_bank_stalls[31:0]; + `VX_CSR_MPM_L3CACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.l3cache_bank_stalls[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_L3CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l3cache_mshr_stalls[31:0]; + `VX_CSR_MPM_L3CACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.l3cache_mshr_stalls[`PERF_CTR_BITS-1:32]); + // PERF: memory + `VX_CSR_MPM_MEM_READS : read_data_ro_r = mem_perf_if.mem_reads[31:0]; + `VX_CSR_MPM_MEM_READS_H : read_data_ro_r = 32'(mem_perf_if.mem_reads[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_MEM_WRITES : read_data_ro_r = mem_perf_if.mem_writes[31:0]; + `VX_CSR_MPM_MEM_WRITES_H : read_data_ro_r = 32'(mem_perf_if.mem_writes[`PERF_CTR_BITS-1:32]); + `VX_CSR_MPM_MEM_LAT : read_data_ro_r = mem_perf_if.mem_latency[31:0]; + `VX_CSR_MPM_MEM_LAT_H : read_data_ro_r = 32'(mem_perf_if.mem_latency[`PERF_CTR_BITS-1:32]); + default:; + endcase + end + default:; + endcase + `endif + end + end + endcase + end + + assign read_data_ro = read_data_ro_r; + assign read_data_rw = read_data_rw_r; + + `UNUSED_VAR (base_dcrs) + + `RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("%t: *** invalid CSR read address: 0x%0h (#%0d)", $time, read_addr, read_uuid)) + +`ifdef PERF_ENABLE + wire [`PERF_CTR_BITS-1:0] perf_wctl_stalls = sfu_perf_if.wctl_stalls; + `UNUSED_VAR (perf_wctl_stalls); +`endif + +endmodule diff --git a/hw/rtl/core/VX_csr_unit.sv b/hw/rtl/core/VX_csr_unit.sv new file mode 100644 index 00000000..14b633fa --- /dev/null +++ b/hw/rtl/core/VX_csr_unit.sv @@ -0,0 +1,181 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_csr_unit import VX_gpu_pkg::*; #( + parameter CORE_ID = 0, + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + input base_dcrs_t base_dcrs, + +`ifdef PERF_ENABLE + VX_mem_perf_if.slave mem_perf_if, + VX_pipeline_perf_if.slave pipeline_perf_if, + VX_sfu_perf_if.slave sfu_perf_if, +`endif + +`ifdef EXT_F_ENABLE + VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS], +`endif + + VX_commit_csr_if.slave commit_csr_if, + VX_sched_csr_if.slave sched_csr_if, + VX_execute_if.slave execute_if, + VX_commit_if.master commit_if +); + `UNUSED_PARAM (CORE_ID) + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * 32 + PID_WIDTH + 1 + 1; + + `UNUSED_VAR (execute_if.data.rs3_data) + + reg [NUM_LANES-1:0][31:0] csr_read_data; + reg [31:0] csr_write_data; + wire [31:0] csr_read_data_ro, csr_read_data_rw; + wire [31:0] csr_req_data; + reg csr_rd_enable; + wire csr_wr_enable; + wire csr_req_ready; + + // wait for all pending instructions to complete + assign sched_csr_if.alm_empty_wid = execute_if.data.wid; + wire no_pending_instr = sched_csr_if.alm_empty; + + wire csr_req_valid = execute_if.valid && no_pending_instr; + assign execute_if.ready = csr_req_ready && no_pending_instr; + + wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.imm[`VX_CSR_ADDR_BITS-1:0]; + wire [`NRI_BITS-1:0] csr_imm = execute_if.data.imm[`VX_CSR_ADDR_BITS +: `NRI_BITS]; + + wire [NUM_LANES-1:0][31:0] rs1_data; + `UNUSED_VAR (rs1_data) + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign rs1_data[i] = execute_if.data.rs1_data[i][31:0]; + end + + wire csr_write_enable = (execute_if.data.op_type == `INST_SFU_CSRRW); + + VX_csr_data #( + .CORE_ID (CORE_ID) + ) csr_data ( + .clk (clk), + .reset (reset), + + .base_dcrs (base_dcrs), + + `ifdef PERF_ENABLE + .mem_perf_if (mem_perf_if), + .pipeline_perf_if(pipeline_perf_if), + .sfu_perf_if (sfu_perf_if), + `endif + + .commit_csr_if (commit_csr_if), + .cycles (sched_csr_if.cycles), + .active_warps (sched_csr_if.active_warps), + .thread_masks (sched_csr_if.thread_masks), + + `ifdef EXT_F_ENABLE + .fpu_to_csr_if (fpu_to_csr_if), + `endif + + .read_enable (csr_req_valid && csr_rd_enable), + .read_uuid (execute_if.data.uuid), + .read_wid (execute_if.data.wid), + .read_addr (csr_addr), + .read_data_ro (csr_read_data_ro), + .read_data_rw (csr_read_data_rw), + + .write_enable (csr_req_valid && csr_wr_enable), + .write_uuid (execute_if.data.uuid), + .write_wid (execute_if.data.wid), + .write_addr (csr_addr), + .write_data (csr_write_data) + ); + + // CSR read + + wire [NUM_LANES-1:0][31:0] wtid, gtid; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + if (PID_BITS != 0) begin + assign wtid[i] = 32'(execute_if.data.pid * NUM_LANES + i); + end else begin + assign wtid[i] = 32'(i); + end + assign gtid[i] = (32'(CORE_ID) << (`NW_BITS + `NT_BITS)) + (32'(execute_if.data.wid) << `NT_BITS) + wtid[i]; + end + + always @(*) begin + csr_rd_enable = 0; + case (csr_addr) + `VX_CSR_THREAD_ID : csr_read_data = wtid; + `VX_CSR_MHARTID : csr_read_data = gtid; + default : begin + csr_read_data = {NUM_LANES{csr_read_data_ro | csr_read_data_rw}}; + csr_rd_enable = 1; + end + endcase + end + + // CSR write + + assign csr_req_data = execute_if.data.use_imm ? 32'(csr_imm) : rs1_data[0]; + + assign csr_wr_enable = (csr_write_enable || (| csr_req_data)); + + always @(*) begin + case (execute_if.data.op_type) + `INST_SFU_CSRRW: begin + csr_write_data = csr_req_data; + end + `INST_SFU_CSRRS: begin + csr_write_data = csr_read_data_rw | csr_req_data; + end + //`INST_SFU_CSRRC + default: begin + csr_write_data = csr_read_data_rw & ~csr_req_data; + end + endcase + end + + // unlock the warp + assign sched_csr_if.unlock_warp = csr_req_valid && csr_req_ready && execute_if.data.eop; + assign sched_csr_if.unlock_wid = execute_if.data.wid; + + // send response + wire [NUM_LANES-1:0][31:0] csr_commit_data; + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (csr_req_valid), + .ready_in (csr_req_ready), + .data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, csr_read_data, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}), + .data_out ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.PC, commit_if.data.rd, commit_if.data.wb, csr_commit_data, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop}), + .valid_out (commit_if.valid), + .ready_out (commit_if.ready) + ); + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign commit_if.data.data[i] = `XLEN'(csr_commit_data[i]); + end + +endmodule diff --git a/hw/rtl/core/VX_dcr_data.sv b/hw/rtl/core/VX_dcr_data.sv new file mode 100644 index 00000000..8626f776 --- /dev/null +++ b/hw/rtl/core/VX_dcr_data.sv @@ -0,0 +1,57 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" +`include "VX_trace.vh" + +module VX_dcr_data import VX_gpu_pkg::*; ( + input wire clk, + input wire reset, + + // Inputs + VX_dcr_bus_if.slave dcr_bus_if, + + // Outputs + output base_dcrs_t base_dcrs +); + + `UNUSED_VAR (reset) + + base_dcrs_t dcrs; + + always @(posedge clk) begin + if (dcr_bus_if.write_valid) begin + case (dcr_bus_if.write_addr) + `VX_DCR_BASE_STARTUP_ADDR0 : dcrs.startup_addr[31:0] <= dcr_bus_if.write_data; + `ifdef XLEN_64 + `VX_DCR_BASE_STARTUP_ADDR1 : dcrs.startup_addr[63:32] <= dcr_bus_if.write_data; + `endif + `VX_DCR_BASE_MPM_CLASS : dcrs.mpm_class <= dcr_bus_if.write_data[7:0]; + default:; + endcase + end + end + + assign base_dcrs = dcrs; + +`ifdef DBG_TRACE_CORE_PIPELINE + always @(posedge clk) begin + if (dcr_bus_if.write_valid) begin + `TRACE(1, ("%d: base-dcr: state=", $time)); + trace_base_dcr(1, dcr_bus_if.write_addr); + `TRACE(1, (", data=0x%0h\n", dcr_bus_if.write_data)); + end + end +`endif + +endmodule diff --git a/hw/rtl/core/VX_decode.sv b/hw/rtl/core/VX_decode.sv new file mode 100644 index 00000000..0032fe7b --- /dev/null +++ b/hw/rtl/core/VX_decode.sv @@ -0,0 +1,552 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" +`include "VX_trace.vh" + +`ifdef EXT_F_ENABLE + `define USED_IREG(x) \ + x``_r = {1'b0, ``x}; \ + use_``x = 1 + + `define USED_FREG(x) \ + x``_r = {1'b1, ``x}; \ + use_``x = 1 +`else + `define USED_IREG(x) \ + x``_r = ``x; \ + use_``x = 1 +`endif + +module VX_decode #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_fetch_if.slave fetch_if, + + // outputs + VX_decode_if.master decode_if, + VX_decode_sched_if.master decode_sched_if +); + + localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + (`NR_BITS * 4) + `XLEN + 1 + 1; + + `UNUSED_PARAM (CORE_ID) + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + reg [`EX_BITS-1:0] ex_type; + reg [`INST_OP_BITS-1:0] op_type; + reg [`INST_MOD_BITS-1:0] op_mod; + reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r; + reg [`XLEN-1:0] imm; + reg use_rd, use_rs1, use_rs2, use_rs3, use_PC, use_imm; + reg is_wstall; + + wire [31:0] instr = fetch_if.data.instr; + wire [6:0] opcode = instr[6:0]; + wire [1:0] func2 = instr[26:25]; + wire [2:0] func3 = instr[14:12]; + wire [4:0] func5 = instr[31:27]; + wire [6:0] func7 = instr[31:25]; + wire [11:0] u_12 = instr[31:20]; + + wire [4:0] rd = instr[11:7]; + wire [4:0] rs1 = instr[19:15]; + wire [4:0] rs2 = instr[24:20]; + wire [4:0] rs3 = instr[31:27]; + + `UNUSED_VAR (func2) + `UNUSED_VAR (func5) + `UNUSED_VAR (rs3) + `UNUSED_VAR (use_rd) + `UNUSED_VAR (use_rs1) + `UNUSED_VAR (use_rs2) + `UNUSED_VAR (use_rs3) + + wire is_itype_sh = func3[0] && ~func3[1]; + + wire [19:0] ui_imm = instr[31:12]; +`ifdef XLEN_64 + wire [11:0] i_imm = is_itype_sh ? {6'b0, instr[25:20]} : u_12; + wire [11:0] iw_imm = is_itype_sh ? {7'b0, instr[24:20]} : u_12; +`else + wire [11:0] i_imm = is_itype_sh ? {7'b0, instr[24:20]} : u_12; +`endif + wire [11:0] s_imm = {func7, rd}; + wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; + wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; + + reg [`INST_ALU_BITS-1:0] r_type; + always @(*) begin + case (func3) + 3'h0: r_type = (opcode[5] && func7[5]) ? `INST_ALU_SUB : `INST_ALU_ADD; + 3'h1: r_type = `INST_ALU_SLL; + 3'h2: r_type = `INST_ALU_SLT; + 3'h3: r_type = `INST_ALU_SLTU; + 3'h4: r_type = `INST_ALU_XOR; + 3'h5: r_type = func7[5] ? `INST_ALU_SRA : `INST_ALU_SRL; + 3'h6: r_type = `INST_ALU_OR; + 3'h7: r_type = `INST_ALU_AND; + endcase + end + + reg [`INST_BR_BITS-1:0] b_type; + always @(*) begin + case (func3) + 3'h0: b_type = `INST_BR_EQ; + 3'h1: b_type = `INST_BR_NE; + 3'h4: b_type = `INST_BR_LT; + 3'h5: b_type = `INST_BR_GE; + 3'h6: b_type = `INST_BR_LTU; + 3'h7: b_type = `INST_BR_GEU; + default: b_type = 'x; + endcase + end + + reg [`INST_BR_BITS-1:0] s_type; + always @(*) begin + case (u_12) + 12'h000: s_type = `INST_OP_BITS'(`INST_BR_ECALL); + 12'h001: s_type = `INST_OP_BITS'(`INST_BR_EBREAK); + 12'h002: s_type = `INST_OP_BITS'(`INST_BR_URET); + 12'h102: s_type = `INST_OP_BITS'(`INST_BR_SRET); + 12'h302: s_type = `INST_OP_BITS'(`INST_BR_MRET); + default: s_type = 'x; + endcase + end + +`ifdef EXT_M_ENABLE + reg [`INST_M_BITS-1:0] m_type; + always @(*) begin + case (func3) + 3'h0: m_type = `INST_M_MUL; + 3'h1: m_type = `INST_M_MULH; + 3'h2: m_type = `INST_M_MULHSU; + 3'h3: m_type = `INST_M_MULHU; + 3'h4: m_type = `INST_M_DIV; + 3'h5: m_type = `INST_M_DIVU; + 3'h6: m_type = `INST_M_REM; + 3'h7: m_type = `INST_M_REMU; + endcase + end +`endif + + always @(*) begin + + ex_type = '0; + op_type = 'x; + op_mod = '0; + rd_r = '0; + rs1_r = '0; + rs2_r = '0; + rs3_r = '0; + imm = 'x; + use_imm = 0; + use_PC = 0; + use_rd = 0; + use_rs1 = 0; + use_rs2 = 0; + use_rs3 = 0; + is_wstall = 0; + + case (opcode) + `INST_I: begin + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(r_type); + use_rd = 1; + use_imm = 1; + imm = {{(`XLEN-12){i_imm[11]}}, i_imm}; + `USED_IREG (rd); + `USED_IREG (rs1); + end + `INST_R: begin + ex_type = `EX_ALU; + `ifdef EXT_M_ENABLE + if (func7[0]) begin + op_type = `INST_OP_BITS'(m_type); + op_mod[1] = 1; + end else + `endif + begin + op_type = `INST_OP_BITS'(r_type); + end + use_rd = 1; + `USED_IREG (rd); + `USED_IREG (rs1); + `USED_IREG (rs2); + end + `ifdef XLEN_64 + `INST_I_W: begin + // ADDIW, SLLIW, SRLIW, SRAIW + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(r_type); + op_mod[2] = 1; + use_rd = 1; + use_imm = 1; + imm = {{(`XLEN-12){iw_imm[11]}}, iw_imm}; + `USED_IREG (rd); + `USED_IREG (rs1); + end + `INST_R_W: begin + ex_type = `EX_ALU; + `ifdef EXT_M_ENABLE + if (func7[0]) begin + // MULW, DIVW, DIVUW, REMW, REMUW + op_type = `INST_OP_BITS'(m_type); + op_mod[1] = 1; + end else + `endif + begin + // ADDW, SUBW, SLLW, SRLW, SRAW + op_type = `INST_OP_BITS'(r_type); + end + op_mod[2] = 1; + use_rd = 1; + `USED_IREG (rd); + `USED_IREG (rs1); + `USED_IREG (rs2); + end + `endif + `INST_LUI: begin + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(`INST_ALU_LUI); + use_rd = 1; + use_imm = 1; + imm = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)}; + `USED_IREG (rd); + end + `INST_AUIPC: begin + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(`INST_ALU_AUIPC); + use_rd = 1; + use_imm = 1; + use_PC = 1; + imm = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)}; + `USED_IREG (rd); + end + `INST_JAL: begin + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(`INST_BR_JAL); + op_mod[0] = 1; + use_rd = 1; + use_imm = 1; + use_PC = 1; + is_wstall = 1; + imm = {{(`XLEN-21){jal_imm[20]}}, jal_imm}; + `USED_IREG (rd); + end + `INST_JALR: begin + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(`INST_BR_JALR); + op_mod[0] = 1; + use_rd = 1; + use_imm = 1; + is_wstall = 1; + imm = {{(`XLEN-12){u_12[11]}}, u_12}; + `USED_IREG (rd); + `USED_IREG (rs1); + end + `INST_B: begin + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(b_type); + op_mod[0] = 1; + use_imm = 1; + use_PC = 1; + is_wstall = 1; + imm = {{(`XLEN-13){b_imm[12]}}, b_imm}; + `USED_IREG (rs1); + `USED_IREG (rs2); + end + `INST_FENCE: begin + ex_type = `EX_LSU; + op_type = `INST_LSU_FENCE; + end + `INST_SYS : begin + if (func3[1:0] != 0) begin + ex_type = `EX_SFU; + op_type = `INST_OP_BITS'(`INST_SFU_CSR(func3[1:0])); + use_rd = 1; + is_wstall = 1; + use_imm = func3[2]; + imm[`VX_CSR_ADDR_BITS-1:0] = u_12; // addr + `USED_IREG (rd); + if (func3[2]) begin + imm[`VX_CSR_ADDR_BITS +: `NRI_BITS] = rs1; // imm + end else begin + `USED_IREG (rs1); + end + end else begin + ex_type = `EX_ALU; + op_type = `INST_OP_BITS'(s_type); + op_mod[0] = 1; + use_rd = 1; + use_imm = 1; + use_PC = 1; + is_wstall = 1; + imm = `XLEN'd4; + `USED_IREG (rd); + end + end + `ifdef EXT_F_ENABLE + `INST_FL, + `endif + `INST_L: begin + ex_type = `EX_LSU; + op_type = `INST_OP_BITS'({1'b0, func3}); + use_rd = 1; + imm = {{(`XLEN-12){u_12[11]}}, u_12}; + use_imm = 1; + `ifdef EXT_F_ENABLE + if (opcode[2]) begin + `USED_FREG (rd); + end else + `endif + `USED_IREG (rd); + `USED_IREG (rs1); + end + `ifdef EXT_F_ENABLE + `INST_FS, + `endif + `INST_S: begin + ex_type = `EX_LSU; + op_type = `INST_OP_BITS'({1'b1, func3}); + imm = {{(`XLEN-12){s_imm[11]}}, s_imm}; + use_imm = 1; + `USED_IREG (rs1); + `ifdef EXT_F_ENABLE + if (opcode[2]) begin + `USED_FREG (rs2); + end else + `endif + `USED_IREG (rs2); + end + `ifdef EXT_F_ENABLE + `INST_FMADD, + `INST_FMSUB, + `INST_FNMSUB, + `INST_FNMADD: begin + ex_type = `EX_FPU; + op_type = `INST_OP_BITS'({2'b11, opcode[3:2]}); + op_mod = `INST_MOD_BITS'(func3); + imm[0] = func2[0]; // destination is double? + use_rd = 1; + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + `USED_FREG (rs3); + end + `INST_FCI: begin + ex_type = `EX_FPU; + op_mod = `INST_MOD_BITS'(func3); + `ifdef FLEN_64 + imm[0] = func2[0]; // destination is double? + `endif + use_rd = 1; + case (func5) + 5'b00000, // FADD + 5'b00001, // FSUB + 5'b00010, // FMUL + 5'b00011: begin // FDIV + op_type = `INST_OP_BITS'(func5[1:0]); + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + 5'b00100: begin + // NCP: FSGNJ=0, FSGNJN=1, FSGNJX=2 + op_type = `INST_OP_BITS'(`INST_FPU_MISC); + op_mod = `INST_MOD_BITS'(func3[1:0]); + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + 5'b00101: begin + // NCP: FMIN=6, FMAX=7 + op_type = `INST_OP_BITS'(`INST_FPU_MISC); + op_mod = func3[0] ? 7 : 6; + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + `ifdef FLEN_64 + 5'b01000: begin + // CVT.S.D, CVT.D.S + op_type = `INST_OP_BITS'(`INST_FPU_F2F); + `USED_FREG (rd); + `USED_FREG (rs1); + end + `endif + 5'b01011: begin + // SQRT + op_type = `INST_OP_BITS'(`INST_FPU_SQRT); + `USED_FREG (rd); + `USED_FREG (rs1); + end + 5'b10100: begin + // CMP + op_type = `INST_OP_BITS'(`INST_FPU_CMP); + `USED_IREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + 5'b11000: begin + // CVT.W.X, CVT.WU.X + op_type = (rs2[0]) ? `INST_OP_BITS'(`INST_FPU_F2U) : `INST_OP_BITS'(`INST_FPU_F2I); + `ifdef XLEN_64 + imm[1] = rs2[1]; // is 64-bit integer + `endif + `USED_IREG (rd); + `USED_FREG (rs1); + end + 5'b11010: begin + // CVT.X.W, CVT.X.WU + op_type = (rs2[0]) ? `INST_OP_BITS'(`INST_FPU_U2F) : `INST_OP_BITS'(`INST_FPU_I2F); + `ifdef XLEN_64 + imm[1] = rs2[1]; // is 64-bit integer + `endif + `USED_FREG (rd); + `USED_IREG (rs1); + end + 5'b11100: begin + if (func3[0]) begin + // NCP: FCLASS=3 + op_type = `INST_OP_BITS'(`INST_FPU_MISC); + op_mod = 3; + end else begin + // NCP: FMV.X.W=4 + op_type = `INST_OP_BITS'(`INST_FPU_MISC); + op_mod = 4; + end + `USED_IREG (rd); + `USED_FREG (rs1); + end + 5'b11110: begin + // NCP: FMV.W.X=5 + op_type = `INST_OP_BITS'(`INST_FPU_MISC); + op_mod = 5; + `USED_FREG (rd); + `USED_IREG (rs1); + end + default:; + endcase + end + `endif + `INST_EXT1: begin + case (func7) + 7'h00: begin + ex_type = `EX_SFU; + is_wstall = 1; + case (func3) + 3'h0: begin // TMC + op_type = `INST_OP_BITS'(`INST_SFU_TMC); + `USED_IREG (rs1); + end + 3'h1: begin // WSPAWN + op_type = `INST_OP_BITS'(`INST_SFU_WSPAWN); + `USED_IREG (rs1); + `USED_IREG (rs2); + end + 3'h2: begin // SPLIT + op_type = `INST_OP_BITS'(`INST_SFU_SPLIT); + use_rd = 1; + `USED_IREG (rs1); + `USED_IREG (rd); + end + 3'h3: begin // JOIN + op_type = `INST_OP_BITS'(`INST_SFU_JOIN); + `USED_IREG (rs1); + end + 3'h4: begin // BAR + op_type = `INST_OP_BITS'(`INST_SFU_BAR); + `USED_IREG (rs1); + `USED_IREG (rs2); + end + 3'h5: begin // PRED + op_type = `INST_OP_BITS'(`INST_SFU_PRED); + `USED_IREG (rs1); + `USED_IREG (rs2); + end + default:; + endcase + end + default:; + endcase + end + `INST_EXT2: begin + case (func3) + 3'h1: begin + case (func2) + 2'h0: begin // CMOV + ex_type = `EX_SFU; + op_type = `INST_OP_BITS'(`INST_SFU_CMOV); + use_rd = 1; + `USED_IREG (rd); + `USED_IREG (rs1); + `USED_IREG (rs2); + `USED_IREG (rs3); + end + default:; + endcase + end + default:; + endcase + end + default:; + endcase + end + + // disable write to integer register r0 + wire wb = use_rd && (rd_r != 0); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (0) + ) req_buf ( + .clk (clk), + .reset (reset), + .valid_in (fetch_if.valid), + .ready_in (fetch_if.ready), + .data_in ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_mod, use_PC, imm, use_imm, wb, rd_r, rs1_r, rs2_r, rs3_r}), + .data_out ({decode_if.data.uuid, decode_if.data.wid, decode_if.data.tmask, decode_if.data.PC, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.use_PC, decode_if.data.imm, decode_if.data.use_imm, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3}), + .valid_out (decode_if.valid), + .ready_out (decode_if.ready) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire fetch_fire = fetch_if.valid && fetch_if.ready; + + assign decode_sched_if.valid = fetch_fire; + assign decode_sched_if.wid = fetch_if.data.wid; + assign decode_sched_if.is_wstall = is_wstall; + + assign fetch_if.ibuf_pop = decode_if.ibuf_pop; + +`ifdef DBG_TRACE_CORE_PIPELINE + always @(posedge clk) begin + if (decode_if.valid && decode_if.ready) begin + `TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr)); + trace_ex_type(1, decode_if.data.ex_type); + `TRACE(1, (", op=")); + trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.rd, decode_if.data.rs2, decode_if.data.use_imm, decode_if.data.imm); + `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=0x%0h, opds=%b%b%b%b, use_pc=%b, use_imm=%b (#%0d)\n", + decode_if.data.op_mod, decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, decode_if.data.imm, use_rd, use_rs1, use_rs2, use_rs3, decode_if.data.use_PC, decode_if.data.use_imm, decode_if.data.uuid)); + end + end +`endif + +endmodule diff --git a/hw/rtl/core/VX_dispatch.sv b/hw/rtl/core/VX_dispatch.sv new file mode 100644 index 00000000..efd719be --- /dev/null +++ b/hw/rtl/core/VX_dispatch.sv @@ -0,0 +1,227 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_dispatch import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire [`PERF_CTR_BITS-1:0] perf_stalls [`NUM_EX_UNITS], +`endif + // inputs + VX_operands_if.slave operands_if [`ISSUE_WIDTH], + + // outputs + VX_dispatch_if.master alu_dispatch_if [`ISSUE_WIDTH], + VX_dispatch_if.master lsu_dispatch_if [`ISSUE_WIDTH], +`ifdef EXT_F_ENABLE + VX_dispatch_if.master fpu_dispatch_if [`ISSUE_WIDTH], +`endif + VX_dispatch_if.master sfu_dispatch_if [`ISSUE_WIDTH] +); + `UNUSED_PARAM (CORE_ID) + + localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + (3 * `NUM_THREADS * `XLEN) + `NT_WIDTH; + + wire [`ISSUE_WIDTH-1:0][`NT_WIDTH-1:0] last_active_tid; + + wire [`NUM_THREADS-1:0][`NT_WIDTH-1:0] tids; + for (genvar i = 0; i < `NUM_THREADS; ++i) begin + assign tids[i] = `NT_WIDTH'(i); + end + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + VX_find_first #( + .N (`NUM_THREADS), + .DATAW (`NT_WIDTH), + .REVERSE (1) + ) last_tid_select ( + .valid_in (operands_if[i].data.tmask), + .data_in (tids), + .data_out (last_active_tid[i]), + `UNUSED_PIN (valid_out) + ); + end + + // ALU dispatch + + VX_operands_if alu_operands_if[`ISSUE_WIDTH](); + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + assign alu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_ALU); + assign alu_operands_if[i].data = operands_if[i].data; + + `RESET_RELAY (alu_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2), + .OUT_REG (2) + ) alu_buffer ( + .clk (clk), + .reset (alu_reset), + .valid_in (alu_operands_if[i].valid), + .ready_in (alu_operands_if[i].ready), + .data_in (`TO_DISPATCH_DATA(alu_operands_if[i].data, last_active_tid[i])), + .data_out (alu_dispatch_if[i].data), + .valid_out (alu_dispatch_if[i].valid), + .ready_out (alu_dispatch_if[i].ready) + ); + end + + // LSU dispatch + + VX_operands_if lsu_operands_if[`ISSUE_WIDTH](); + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + assign lsu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_LSU); + assign lsu_operands_if[i].data = operands_if[i].data; + + `RESET_RELAY (lsu_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2), + .OUT_REG (2) + ) lsu_buffer ( + .clk (clk), + .reset (lsu_reset), + .valid_in (lsu_operands_if[i].valid), + .ready_in (lsu_operands_if[i].ready), + .data_in (`TO_DISPATCH_DATA(lsu_operands_if[i].data, last_active_tid[i])), + .data_out (lsu_dispatch_if[i].data), + .valid_out (lsu_dispatch_if[i].valid), + .ready_out (lsu_dispatch_if[i].ready) + ); + end + + // FPU dispatch + +`ifdef EXT_F_ENABLE + + VX_operands_if fpu_operands_if[`ISSUE_WIDTH](); + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + assign fpu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_FPU); + assign fpu_operands_if[i].data = operands_if[i].data; + + `RESET_RELAY (fpu_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2), + .OUT_REG (2) + ) fpu_buffer ( + .clk (clk), + .reset (fpu_reset), + .valid_in (fpu_operands_if[i].valid), + .ready_in (fpu_operands_if[i].ready), + .data_in (`TO_DISPATCH_DATA(fpu_operands_if[i].data, last_active_tid[i])), + .data_out (fpu_dispatch_if[i].data), + .valid_out (fpu_dispatch_if[i].valid), + .ready_out (fpu_dispatch_if[i].ready) + ); + end +`endif + + // SFU dispatch + + VX_operands_if sfu_operands_if[`ISSUE_WIDTH](); + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + assign sfu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_SFU); + assign sfu_operands_if[i].data = operands_if[i].data; + + `RESET_RELAY (sfu_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2), + .OUT_REG (2) + ) sfu_buffer ( + .clk (clk), + .reset (sfu_reset), + .valid_in (sfu_operands_if[i].valid), + .ready_in (sfu_operands_if[i].ready), + .data_in (`TO_DISPATCH_DATA(sfu_operands_if[i].data, last_active_tid[i])), + .data_out (sfu_dispatch_if[i].data), + .valid_out (sfu_dispatch_if[i].valid), + .ready_out (sfu_dispatch_if[i].ready) + ); + end + + // can take next request? + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + assign operands_if[i].ready = (alu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_ALU)) + || (lsu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_LSU)) + `ifdef EXT_F_ENABLE + || (fpu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_FPU)) + `endif + || (sfu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_SFU)); + end + +`ifdef PERF_ENABLE + reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_stalls_n, perf_stalls_r; + wire [`ISSUE_WIDTH-1:0] operands_stall; + wire [`ISSUE_WIDTH-1:0][`EX_BITS-1:0] operands_ex_type; + + for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin + assign operands_stall[i] = operands_if[i].valid && ~operands_if[i].ready; + assign operands_ex_type[i] = operands_if[i].data.ex_type; + end + + always @(*) begin + perf_stalls_n = perf_stalls_r; + for (integer i=0; i < `ISSUE_WIDTH; ++i) begin + if (operands_stall[i]) begin + perf_stalls_n[operands_ex_type[i]] += `PERF_CTR_BITS'(1); + end + end + end + + always @(posedge clk) begin + if (reset) begin + perf_stalls_r <= '0; + end else begin + perf_stalls_r <= perf_stalls_n; + end + end + + for (genvar i=0; i < `NUM_EX_UNITS; ++i) begin + assign perf_stalls[i] = perf_stalls_r[i]; + end +`endif + +`ifdef DBG_TRACE_CORE_PIPELINE + for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin + always @(posedge clk) begin + if (operands_if[i].valid && operands_if[i].ready) begin + `TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), operands_if[i].data.PC)); + trace_ex_type(1, operands_if[i].data.ex_type); + `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if[i].data.op_mod, operands_if[i].data.tmask, operands_if[i].data.wb, operands_if[i].data.rd)); + `TRACE_ARRAY1D(1, operands_if[i].data.rs1_data, `NUM_THREADS); + `TRACE(1, (", rs2_data=")); + `TRACE_ARRAY1D(1, operands_if[i].data.rs2_data, `NUM_THREADS); + `TRACE(1, (", rs3_data=")); + `TRACE_ARRAY1D(1, operands_if[i].data.rs3_data, `NUM_THREADS); + `TRACE(1, (" (#%0d)\n", operands_if[i].data.uuid)); + end + end + end +`endif + +endmodule diff --git a/hw/rtl/core/VX_dispatch_unit.sv b/hw/rtl/core/VX_dispatch_unit.sv new file mode 100644 index 00000000..86564187 --- /dev/null +++ b/hw/rtl/core/VX_dispatch_unit.sv @@ -0,0 +1,256 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_dispatch_unit import VX_gpu_pkg::*; #( + parameter BLOCK_SIZE = 1, + parameter NUM_LANES = 1, + parameter OUT_REG = 0, + parameter MAX_FANOUT = `MAX_FANOUT +) ( + input wire clk, + input wire reset, + + // inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // outputs + VX_execute_if.master execute_if [BLOCK_SIZE] + +); + `STATIC_ASSERT ((`NUM_THREADS == NUM_LANES * (`NUM_THREADS / NUM_LANES)), ("invalid parameter")) + localparam BLOCK_SIZE_W = `LOG2UP(BLOCK_SIZE); + localparam NUM_PACKETS = `NUM_THREADS / NUM_LANES; + localparam PID_BITS = `CLOG2(NUM_PACKETS); + localparam PID_WIDTH = `UP(PID_BITS); + localparam BATCH_COUNT = `ISSUE_WIDTH / BLOCK_SIZE; + localparam BATCH_COUNT_W= `LOG2UP(BATCH_COUNT); + localparam ISSUE_W = `LOG2UP(`ISSUE_WIDTH); + localparam IN_DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + `NT_WIDTH + (3 * `NUM_THREADS * `XLEN); + localparam OUT_DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + `NT_WIDTH + (3 * NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1; + localparam FANOUT_ENABLE= (`NUM_THREADS > (MAX_FANOUT + MAX_FANOUT/2)); + + localparam DATA_TMASK_OFF = IN_DATAW - (`UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS); + localparam DATA_REGS_OFF = 0; + + wire [`ISSUE_WIDTH-1:0] dispatch_valid; + wire [`ISSUE_WIDTH-1:0][IN_DATAW-1:0] dispatch_data; + wire [`ISSUE_WIDTH-1:0] dispatch_ready; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + assign dispatch_valid[i] = dispatch_if[i].valid; + assign dispatch_data[i] = dispatch_if[i].data; + assign dispatch_if[i].ready = dispatch_ready[i]; + end + + wire [BLOCK_SIZE-1:0][ISSUE_W-1:0] issue_indices; + wire [BLOCK_SIZE-1:0] block_ready; + wire [BLOCK_SIZE-1:0][NUM_LANES-1:0] block_tmask; + wire [BLOCK_SIZE-1:0][2:0][NUM_LANES-1:0][`XLEN-1:0] block_regs; + wire [BLOCK_SIZE-1:0][PID_WIDTH-1:0] block_pid; + wire [BLOCK_SIZE-1:0] block_sop; + wire [BLOCK_SIZE-1:0] block_eop; + wire [BLOCK_SIZE-1:0] block_done; + + wire batch_done = (& block_done); + + logic [BATCH_COUNT_W-1:0] batch_idx; + if (BATCH_COUNT != 1) begin + always @(posedge clk) begin + if (reset) begin + batch_idx <= '0; + end else if (batch_done) begin + batch_idx <= batch_idx + BATCH_COUNT_W'(1); + end + end + end else begin + assign batch_idx = 0; + `UNUSED_VAR (batch_done) + end + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin + + wire [ISSUE_W-1:0] issue_idx = ISSUE_W'(batch_idx * BLOCK_SIZE) + ISSUE_W'(block_idx); + assign issue_indices[block_idx] = issue_idx; + + wire valid_p, ready_p; + + if (`NUM_THREADS != NUM_LANES) begin + reg [NUM_PACKETS-1:0] sent_mask_p; + wire [PID_WIDTH-1:0] start_p_n, start_p, end_p; + wire dispatch_valid_r; + reg is_first_p; + + wire fire_p = valid_p && ready_p; + + wire is_last_p = (start_p == end_p); + + wire fire_eop = fire_p && is_last_p; + + always @(posedge clk) begin + if (reset) begin + sent_mask_p <= '0; + is_first_p <= 1; + end else begin + if ((BATCH_COUNT != 1) ? batch_done : fire_eop) begin + sent_mask_p <= '0; + is_first_p <= 1; + end else if (fire_p) begin + sent_mask_p[start_p] <= 1; + is_first_p <= 0; + end + end + end + + wire [NUM_PACKETS-1:0][NUM_LANES-1:0] per_packet_tmask; + wire [NUM_PACKETS-1:0][2:0][NUM_LANES-1:0][`XLEN-1:0] per_packet_regs; + + wire [`NUM_THREADS-1:0] dispatch_tmask = dispatch_data[issue_idx][DATA_TMASK_OFF +: `NUM_THREADS]; + wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs1_data = dispatch_data[issue_idx][DATA_REGS_OFF + 2 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN]; + wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs2_data = dispatch_data[issue_idx][DATA_REGS_OFF + 1 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN]; + wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs3_data = dispatch_data[issue_idx][DATA_REGS_OFF + 0 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN]; + + for (genvar i = 0; i < NUM_PACKETS; ++i) begin + for (genvar j = 0; j < NUM_LANES; ++j) begin + localparam k = i * NUM_LANES + j; + assign per_packet_tmask[i][j] = dispatch_tmask[k]; + assign per_packet_regs[i][0][j] = dispatch_rs1_data[k]; + assign per_packet_regs[i][1][j] = dispatch_rs2_data[k]; + assign per_packet_regs[i][2][j] = dispatch_rs3_data[k]; + end + end + + wire [NUM_PACKETS-1:0] packet_valids; + wire [NUM_PACKETS-1:0][PID_WIDTH-1:0] packet_ids; + + for (genvar i = 0; i < NUM_PACKETS; ++i) begin + assign packet_valids[i] = (| per_packet_tmask[i]); + assign packet_ids[i] = PID_WIDTH'(i); + end + + VX_find_first #( + .N (NUM_PACKETS), + .DATAW (PID_WIDTH), + .REVERSE (0) + ) find_first ( + .valid_in (packet_valids & ~sent_mask_p), + .data_in (packet_ids), + .data_out (start_p_n), + `UNUSED_PIN (valid_out) + ); + + VX_find_first #( + .N (NUM_PACKETS), + .DATAW (PID_WIDTH), + .REVERSE (1) + ) find_last ( + .valid_in (packet_valids), + .data_in (packet_ids), + .data_out (end_p), + `UNUSED_PIN (valid_out) + ); + + VX_pipe_register #( + .DATAW (1 + PID_WIDTH), + .RESETW (1), + .DEPTH (FANOUT_ENABLE ? 1 : 0) + ) pipe_reg ( + .clk (clk), + .reset (reset || fire_p), // should flush on fire + .enable (1'b1), + .data_in ({dispatch_valid[issue_idx], start_p_n}), + .data_out ({dispatch_valid_r, start_p}) + ); + + wire [NUM_LANES-1:0] tmask_p = per_packet_tmask[start_p]; + wire [2:0][NUM_LANES-1:0][`XLEN-1:0] regs_p = per_packet_regs[start_p]; + + wire block_enable = (BATCH_COUNT == 1 || ~(& sent_mask_p)); + + assign valid_p = dispatch_valid_r && block_enable; + assign block_tmask[block_idx] = tmask_p; + assign block_regs[block_idx] = regs_p; + assign block_pid[block_idx] = start_p; + assign block_sop[block_idx] = is_first_p; + assign block_eop[block_idx] = is_last_p; + if (FANOUT_ENABLE) begin + assign block_ready[block_idx] = dispatch_valid_r && ready_p && block_enable; + end else begin + assign block_ready[block_idx] = ready_p && block_enable; + end + assign block_done[block_idx] = ~dispatch_valid[issue_idx] || fire_eop; + end else begin + assign valid_p = dispatch_valid[issue_idx]; + assign block_tmask[block_idx] = dispatch_data[issue_idx][DATA_TMASK_OFF +: `NUM_THREADS]; + assign block_regs[block_idx][0] = dispatch_data[issue_idx][DATA_REGS_OFF + 2 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN]; + assign block_regs[block_idx][1] = dispatch_data[issue_idx][DATA_REGS_OFF + 1 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN]; + assign block_regs[block_idx][2] = dispatch_data[issue_idx][DATA_REGS_OFF + 0 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN]; + assign block_pid[block_idx] = '0; + assign block_sop[block_idx] = 1'b1; + assign block_eop[block_idx] = 1'b1; + assign block_ready[block_idx] = ready_p; + assign block_done[block_idx] = ~valid_p || ready_p; + end + + wire [ISSUE_IDX_W-1:0] wsi; + if (BATCH_COUNT != 1) begin + if (BLOCK_SIZE != 1) begin + assign wsi = {batch_idx, BLOCK_SIZE_W'(block_idx)}; + end else begin + assign wsi = batch_idx; + end + end else begin + assign wsi = block_idx; + end + + `RESET_RELAY(buf_out_reset, reset); + + wire [`NW_WIDTH-1:0] block_wid = wis_to_wid(dispatch_data[issue_idx][DATA_TMASK_OFF+`NUM_THREADS +: ISSUE_WIS_W], wsi); + + VX_elastic_buffer #( + .DATAW (OUT_DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) buf_out ( + .clk (clk), + .reset (buf_out_reset), + .valid_in (valid_p), + .ready_in (ready_p), + .data_in ({ + dispatch_data[issue_idx][IN_DATAW-1 : DATA_TMASK_OFF+`NUM_THREADS+ISSUE_WIS_W], + block_wid, + block_tmask[block_idx], + dispatch_data[issue_idx][DATA_TMASK_OFF-1 : DATA_REGS_OFF + 3 * `NUM_THREADS * `XLEN], + block_regs[block_idx][0], + block_regs[block_idx][1], + block_regs[block_idx][2], + block_pid[block_idx], + block_sop[block_idx], + block_eop[block_idx]}), + .data_out (execute_if[block_idx].data), + .valid_out (execute_if[block_idx].valid), + .ready_out (execute_if[block_idx].ready) + ); + end + + reg [`ISSUE_WIDTH-1:0] ready_in; + always @(*) begin + ready_in = 0; + for (integer i = 0; i < BLOCK_SIZE; ++i) begin + ready_in[issue_indices[i]] = block_ready[i] && block_eop[i]; + end + end + assign dispatch_ready = ready_in; + +endmodule diff --git a/hw/rtl/core/VX_execute.sv b/hw/rtl/core/VX_execute.sv new file mode 100644 index 00000000..f1ea2675 --- /dev/null +++ b/hw/rtl/core/VX_execute.sv @@ -0,0 +1,137 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_execute import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + input base_dcrs_t base_dcrs, + + // Dcache interface + VX_mem_bus_if.master dcache_bus_if [DCACHE_NUM_REQS], + + // commit interface + VX_commit_csr_if.slave commit_csr_if, + + // fetch interface + VX_sched_csr_if.slave sched_csr_if, + +`ifdef PERF_ENABLE + VX_mem_perf_if.slave mem_perf_if, + VX_pipeline_perf_if.slave pipeline_perf_if, +`endif + +`ifdef EXT_F_ENABLE + VX_dispatch_if.slave fpu_dispatch_if [`ISSUE_WIDTH], + VX_commit_if.master fpu_commit_if [`ISSUE_WIDTH], +`endif + + VX_dispatch_if.slave alu_dispatch_if [`ISSUE_WIDTH], + VX_commit_if.master alu_commit_if [`ISSUE_WIDTH], + VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS], + + VX_dispatch_if.slave lsu_dispatch_if [`ISSUE_WIDTH], + VX_commit_if.master lsu_commit_if [`ISSUE_WIDTH], + + VX_dispatch_if.slave sfu_dispatch_if [`ISSUE_WIDTH], + VX_commit_if.master sfu_commit_if [`ISSUE_WIDTH], + VX_warp_ctl_if.master warp_ctl_if, + + // simulation helper signals + output wire sim_ebreak +); + +`ifdef EXT_F_ENABLE + VX_fpu_to_csr_if fpu_to_csr_if[`NUM_FPU_BLOCKS](); +`endif + + `RESET_RELAY (alu_reset, reset); + `RESET_RELAY (lsu_reset, reset); + `RESET_RELAY (sfu_reset, reset); + + VX_alu_unit #( + .CORE_ID (CORE_ID) + ) alu_unit ( + .clk (clk), + .reset (alu_reset), + .dispatch_if (alu_dispatch_if), + .branch_ctl_if (branch_ctl_if), + .commit_if (alu_commit_if) + ); + + `SCOPE_IO_SWITCH (1) + + VX_lsu_unit #( + .CORE_ID (CORE_ID) + ) lsu_unit ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (lsu_reset), + .cache_bus_if (dcache_bus_if), + .dispatch_if (lsu_dispatch_if), + .commit_if (lsu_commit_if) + ); + +`ifdef EXT_F_ENABLE + `RESET_RELAY (fpu_reset, reset); + + VX_fpu_unit #( + .CORE_ID (CORE_ID) + ) fpu_unit ( + .clk (clk), + .reset (fpu_reset), + .dispatch_if (fpu_dispatch_if), + .fpu_to_csr_if (fpu_to_csr_if), + .commit_if (fpu_commit_if) + ); +`endif + + VX_sfu_unit #( + .CORE_ID (CORE_ID) + ) sfu_unit ( + .clk (clk), + .reset (sfu_reset), + + `ifdef PERF_ENABLE + .mem_perf_if (mem_perf_if), + .pipeline_perf_if (pipeline_perf_if), + `endif + + .base_dcrs (base_dcrs), + + .dispatch_if (sfu_dispatch_if), + + `ifdef EXT_F_ENABLE + .fpu_to_csr_if (fpu_to_csr_if), + `endif + + .commit_csr_if (commit_csr_if), + .sched_csr_if (sched_csr_if), + .warp_ctl_if (warp_ctl_if), + .commit_if (sfu_commit_if) + ); + + // simulation helper signal to get RISC-V tests Pass/Fail status + assign sim_ebreak = alu_dispatch_if[0].valid && alu_dispatch_if[0].ready + && alu_dispatch_if[0].data.wis == 0 + && `INST_ALU_IS_BR(alu_dispatch_if[0].data.op_mod) + && (`INST_BR_BITS'(alu_dispatch_if[0].data.op_type) == `INST_BR_EBREAK + || `INST_BR_BITS'(alu_dispatch_if[0].data.op_type) == `INST_BR_ECALL); + +endmodule diff --git a/hw/rtl/core/VX_fetch.sv b/hw/rtl/core/VX_fetch.sv new file mode 100644 index 00000000..ef52ef65 --- /dev/null +++ b/hw/rtl/core/VX_fetch.sv @@ -0,0 +1,184 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_fetch import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Icache interface + VX_mem_bus_if.master icache_bus_if, + + // inputs + VX_schedule_if.slave schedule_if, + + // outputs + VX_fetch_if.master fetch_if +); + `UNUSED_PARAM (CORE_ID) + `UNUSED_VAR (reset) + localparam ISW_WIDTH = `LOG2UP(`ISSUE_WIDTH); + + wire icache_req_valid; + wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr; + wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag; + wire icache_req_ready; + + wire [`UUID_WIDTH-1:0] rsp_uuid; + wire [`NW_WIDTH-1:0] req_tag, rsp_tag; + + wire icache_req_fire = icache_req_valid && icache_req_ready; + + wire [ISW_WIDTH-1:0] schedule_isw = wid_to_isw(schedule_if.data.wid); + + assign req_tag = schedule_if.data.wid; + + assign {rsp_uuid, rsp_tag} = icache_bus_if.rsp_data.tag; + + wire [`XLEN-1:0] rsp_PC; + wire [`NUM_THREADS-1:0] rsp_tmask; + + VX_dp_ram #( + .DATAW (`XLEN + `NUM_THREADS), + .SIZE (`NUM_WARPS), + .LUTRAM (1) + ) tag_store ( + .clk (clk), + .read (1'b1), + .write (icache_req_fire), + `UNUSED_PIN (wren), + .waddr (req_tag), + .wdata ({schedule_if.data.PC, schedule_if.data.tmask}), + .raddr (rsp_tag), + .rdata ({rsp_PC, rsp_tmask}) + ); + + // Ensure that the ibuffer doesn't fill up. + // This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache request. + // This issue is particularly prevalent when the icache and dcache is disabled and both requests share the same bus. + wire [`ISSUE_WIDTH-1:0] pending_ibuf_full; + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + VX_pending_size #( + .SIZE (`IBUF_SIZE) + ) pending_reads ( + .clk (clk), + .reset (reset), + .incr (icache_req_fire && schedule_isw == i), + .decr (fetch_if.ibuf_pop[i]), + .full (pending_ibuf_full[i]), + `UNUSED_PIN (size), + `UNUSED_PIN (empty) + ); + end + + `RUNTIME_ASSERT((!schedule_if.valid || schedule_if.data.PC != 0), + ("%t: *** invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, schedule_if.data.PC, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid)) + + // Icache Request + + wire ibuf_ready = ~pending_ibuf_full[schedule_isw]; + assign icache_req_valid = schedule_if.valid && ibuf_ready; + assign icache_req_addr = schedule_if.data.PC[`MEM_ADDR_WIDTH-1:2]; + assign icache_req_tag = {schedule_if.data.uuid, req_tag}; + assign schedule_if.ready = icache_req_ready && ibuf_ready; + + VX_elastic_buffer #( + .DATAW (ICACHE_ADDR_WIDTH + ICACHE_TAG_WIDTH), + .SIZE (2), + .OUT_REG (1) // external bus should be registered + ) req_buf ( + .clk (clk), + .reset (reset), + .valid_in (icache_req_valid), + .ready_in (icache_req_ready), + .data_in ({icache_req_addr, icache_req_tag}), + .data_out ({icache_bus_if.req_data.addr, icache_bus_if.req_data.tag}), + .valid_out (icache_bus_if.req_valid), + .ready_out (icache_bus_if.req_ready) + ); + + assign icache_bus_if.req_data.rw = 0; + assign icache_bus_if.req_data.byteen = 4'b1111; + assign icache_bus_if.req_data.data = '0; + + // Icache Response + + assign fetch_if.valid = icache_bus_if.rsp_valid; + assign fetch_if.data.tmask = rsp_tmask; + assign fetch_if.data.wid = rsp_tag; + assign fetch_if.data.PC = rsp_PC; + assign fetch_if.data.instr = icache_bus_if.rsp_data.data; + assign fetch_if.data.uuid = rsp_uuid; + assign icache_bus_if.rsp_ready = fetch_if.ready; + +`ifdef DBG_SCOPE_FETCH + if (CORE_ID == 0) begin + `ifdef SCOPE + wire schedule_fire = schedule_if.valid && schedule_if.ready; + wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready; + VX_scope_tap #( + .SCOPE_ID (1), + .TRIGGERW (4), + .PROBEW (3*`UUID_WIDTH + 108) + ) scope_tap ( + .clk(clk), + .reset(scope_reset), + .start(1'b0), + .stop(1'b0), + .triggers({ + reset, + schedule_fire, + icache_req_fire, + icache_rsp_fire + }), + .probes({ + schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC, + icache_bus_if.req_data.tag, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr, + icache_bus_if.rsp_data.data, icache_bus_if.rsp_data.tag + }), + .bus_in(scope_bus_in), + .bus_out(scope_bus_out) + ); + `endif + `ifdef CHIPSCOPE + ila_fetch ila_fetch_inst ( + .clk (clk), + .probe0 ({reset, schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC, schedule_if.ready, schedule_if.valid}), + .probe1 ({icache_bus_if.req_data.tag, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr, icache_bus_if.req_ready, icache_bus_if.req_valid}), + .probe2 ({icache_bus_if.rsp_data.data, icache_bus_if.rsp_data.tag, icache_bus_if.rsp_ready, icache_bus_if.rsp_valid}) + ); + `endif + end +`else + `SCOPE_IO_UNUSED() +`endif + +`ifdef DBG_TRACE_CORE_ICACHE + wire schedule_fire = schedule_if.valid && schedule_if.ready; + wire fetch_fire = fetch_if.valid && fetch_if.ready; + always @(posedge clk) begin + if (schedule_fire) begin + `TRACE(1, ("%d: I$%0d req: wid=%0d, PC=0x%0h, tmask=%b (#%0d)\n", $time, CORE_ID, schedule_if.data.wid, schedule_if.data.PC, schedule_if.data.tmask, schedule_if.data.uuid)); + end + if (fetch_fire) begin + `TRACE(1, ("%d: I$%0d rsp: wid=%0d, PC=0x%0h, tmask=%b, instr=0x%0h (#%0d)\n", $time, CORE_ID, fetch_if.data.wid, fetch_if.data.PC, fetch_if.data.tmask, fetch_if.data.instr, fetch_if.data.uuid)); + end + end +`endif + +endmodule diff --git a/hw/rtl/core/VX_gather_unit.sv b/hw/rtl/core/VX_gather_unit.sv new file mode 100644 index 00000000..e3dc935d --- /dev/null +++ b/hw/rtl/core/VX_gather_unit.sv @@ -0,0 +1,129 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_gather_unit import VX_gpu_pkg::*; #( + parameter BLOCK_SIZE = 1, + parameter NUM_LANES = 1, + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_commit_if.slave commit_in_if [BLOCK_SIZE], + + // outputs + VX_commit_if.master commit_out_if [`ISSUE_WIDTH] + +); + localparam BLOCK_SIZE_W = `LOG2UP(BLOCK_SIZE); + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + 1 + `NR_BITS + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1; + localparam DATA_WIS_OFF = DATAW - (`UUID_WIDTH + `NW_WIDTH); + + wire [BLOCK_SIZE-1:0] commit_in_valid; + wire [BLOCK_SIZE-1:0][DATAW-1:0] commit_in_data; + wire [BLOCK_SIZE-1:0] commit_in_ready; + wire [BLOCK_SIZE-1:0][ISSUE_IDX_W-1:0] commit_in_wsi; + + for (genvar i = 0; i < BLOCK_SIZE; ++i) begin + assign commit_in_valid[i] = commit_in_if[i].valid; + assign commit_in_data[i] = commit_in_if[i].data; + assign commit_in_if[i].ready = commit_in_ready[i]; + if (BLOCK_SIZE != `ISSUE_WIDTH) begin + if (BLOCK_SIZE != 1) begin + assign commit_in_wsi[i] = {commit_in_data[i][DATA_WIS_OFF+BLOCK_SIZE_W +: (ISSUE_IDX_W-BLOCK_SIZE_W)], BLOCK_SIZE_W'(i)}; + end else begin + assign commit_in_wsi[i] = commit_in_data[i][DATA_WIS_OFF +: ISSUE_IDX_W]; + end + end else begin + assign commit_in_wsi[i] = BLOCK_SIZE_W'(i); + end + end + + reg [`ISSUE_WIDTH-1:0] commit_out_valid; + reg [`ISSUE_WIDTH-1:0][DATAW-1:0] commit_out_data; + wire [`ISSUE_WIDTH-1:0] commit_out_ready; + + always @(*) begin + commit_out_valid = '0; + for (integer i = 0; i < `ISSUE_WIDTH; ++i) begin + commit_out_data[i] = 'x; + end + for (integer i = 0; i < BLOCK_SIZE; ++i) begin + commit_out_valid[commit_in_wsi[i]] = commit_in_valid[i]; + commit_out_data[commit_in_wsi[i]] = commit_in_data[i]; + end + end + for (genvar i = 0; i < BLOCK_SIZE; ++i) begin + assign commit_in_ready[i] = commit_out_ready[commit_in_wsi[i]]; + end + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) commit_tmp_if(); + + `RESET_RELAY(commit_out_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (commit_out_reset), + .valid_in (commit_out_valid[i]), + .ready_in (commit_out_ready[i]), + .data_in (commit_out_data[i]), + .data_out (commit_tmp_if.data), + .valid_out (commit_tmp_if.valid), + .ready_out (commit_tmp_if.ready) + ); + + logic [`NUM_THREADS-1:0] commit_tmask_r; + logic [`NUM_THREADS-1:0][`XLEN-1:0] commit_data_r; + if (PID_BITS != 0) begin + always @(*) begin + commit_tmask_r = '0; + commit_data_r = 'x; + for (integer j = 0; j < NUM_LANES; ++j) begin + commit_tmask_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.tmask[j]; + commit_data_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.data[j]; + end + end + end else begin + assign commit_tmask_r = commit_tmp_if.data.tmask; + assign commit_data_r = commit_tmp_if.data.data; + end + + assign commit_out_if[i].valid = commit_tmp_if.valid; + assign commit_out_if[i].data = { + commit_tmp_if.data.uuid, + commit_tmp_if.data.wid, + commit_tmask_r, + commit_tmp_if.data.PC, + commit_tmp_if.data.wb, + commit_tmp_if.data.rd, + commit_data_r, + 1'b0, // PID + commit_tmp_if.data.sop, + commit_tmp_if.data.eop + }; + assign commit_tmp_if.ready = commit_out_if[i].ready; + end + +endmodule diff --git a/hw/rtl/core/VX_ibuffer.sv b/hw/rtl/core/VX_ibuffer.sv new file mode 100644 index 00000000..b6847edc --- /dev/null +++ b/hw/rtl/core/VX_ibuffer.sv @@ -0,0 +1,73 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_ibuffer import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_decode_if.slave decode_if, + + // outputs + VX_ibuffer_if.master ibuffer_if [`ISSUE_WIDTH] +); + `UNUSED_PARAM (CORE_ID) + localparam ISW_WIDTH = `LOG2UP(`ISSUE_WIDTH); + localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4); + + wire [`ISSUE_WIDTH-1:0] ibuf_ready_in; + + wire [ISW_WIDTH-1:0] decode_isw = wid_to_isw(decode_if.data.wid); + wire [ISSUE_WIS_W-1:0] decode_wis = wid_to_wis(decode_if.data.wid); + + assign decode_if.ready = ibuf_ready_in[decode_isw]; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`IBUF_SIZE), + .OUT_REG (1) + ) instr_buf ( + .clk (clk), + .reset (reset), + .valid_in (decode_if.valid && decode_isw == i), + .ready_in (ibuf_ready_in[i]), + .data_in ({ + decode_if.data.uuid, + decode_wis, + decode_if.data.tmask, + decode_if.data.ex_type, + decode_if.data.op_type, + decode_if.data.op_mod, + decode_if.data.wb, + decode_if.data.use_PC, + decode_if.data.use_imm, + decode_if.data.PC, + decode_if.data.imm, + decode_if.data.rd, + decode_if.data.rs1, + decode_if.data.rs2, + decode_if.data.rs3}), + .data_out(ibuffer_if[i].data), + .valid_out (ibuffer_if[i].valid), + .ready_out(ibuffer_if[i].ready) + ); + + assign decode_if.ibuf_pop[i] = ibuffer_if[i].valid && ibuffer_if[i].ready; + end + +endmodule diff --git a/hw/rtl/core/VX_int_unit.sv b/hw/rtl/core/VX_int_unit.sv new file mode 100644 index 00000000..a5e4f394 --- /dev/null +++ b/hw/rtl/core/VX_int_unit.sv @@ -0,0 +1,191 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_int_unit #( + parameter CORE_ID = 0, + parameter BLOCK_IDX = 0, + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_commit_if.master commit_if, + VX_branch_ctl_if.master branch_ctl_if +); + + `UNUSED_PARAM (CORE_ID) + localparam LANE_BITS = `CLOG2(NUM_LANES); + localparam LANE_WIDTH = `UP(LANE_BITS); + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam SHIFT_IMM_BITS = `CLOG2(`XLEN); + + `UNUSED_VAR (execute_if.data.rs3_data) + + wire [NUM_LANES-1:0][`XLEN-1:0] add_result; + wire [NUM_LANES-1:0][`XLEN:0] sub_result; // +1 bit for branch compare + wire [NUM_LANES-1:0][`XLEN-1:0] shr_result; + reg [NUM_LANES-1:0][`XLEN-1:0] msc_result; + + wire [NUM_LANES-1:0][`XLEN-1:0] add_result_w; + wire [NUM_LANES-1:0][`XLEN-1:0] sub_result_w; + wire [NUM_LANES-1:0][`XLEN-1:0] shr_result_w; + reg [NUM_LANES-1:0][`XLEN-1:0] msc_result_w; + + reg [NUM_LANES-1:0][`XLEN-1:0] alu_result; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_result_r; + +`ifdef XLEN_64 + wire is_alu_w = `INST_ALU_IS_W(execute_if.data.op_mod); +`else + wire is_alu_w = 0; +`endif + + `UNUSED_VAR (execute_if.data.op_mod) + + wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_BITS'(execute_if.data.op_type); + wire [`INST_BR_BITS-1:0] br_op = `INST_BR_BITS'(execute_if.data.op_type); + wire is_br_op = `INST_ALU_IS_BR(execute_if.data.op_mod); + wire is_sub_op = `INST_ALU_IS_SUB(alu_op); + wire is_signed = `INST_ALU_SIGNED(alu_op); + wire [1:0] op_class = is_br_op ? `INST_BR_CLASS(alu_op) : `INST_ALU_CLASS(alu_op); + + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1 = execute_if.data.rs1_data; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2 = execute_if.data.rs2_data; + + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1_PC = execute_if.data.use_PC ? {NUM_LANES{execute_if.data.PC}} : alu_in1; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_imm = execute_if.data.use_imm ? {NUM_LANES{execute_if.data.imm}} : alu_in2; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_br = (execute_if.data.use_imm && ~is_br_op) ? {NUM_LANES{execute_if.data.imm}} : alu_in2; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i]; + assign add_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] + alu_in2_imm[i][31:0])); + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [`XLEN:0] sub_in1 = {is_signed & alu_in1[i][`XLEN-1], alu_in1[i]}; + wire [`XLEN:0] sub_in2 = {is_signed & alu_in2_br[i][`XLEN-1], alu_in2_br[i]}; + assign sub_result[i] = sub_in1 - sub_in2; + assign sub_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] - alu_in2_imm[i][31:0])); + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [`XLEN:0] shr_in1 = {is_signed && alu_in1[i][`XLEN-1], alu_in1[i]}; + assign shr_result[i] = `XLEN'($signed(shr_in1) >>> alu_in2_imm[i][SHIFT_IMM_BITS-1:0]); + wire [32:0] shr_in1_w = {is_signed && alu_in1[i][31], alu_in1[i][31:0]}; + wire [31:0] shr_res_w = 32'($signed(shr_in1_w) >>> alu_in2_imm[i][4:0]); + assign shr_result_w[i] = `XLEN'($signed(shr_res_w)); + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + case (alu_op[1:0]) + 2'b00: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; // AND + 2'b01: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; // OR + 2'b10: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; // XOR + 2'b11: msc_result[i] = alu_in1[i] << alu_in2_imm[i][SHIFT_IMM_BITS-1:0]; // SLL + endcase + end + assign msc_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] << alu_in2_imm[i][4:0])); + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [`XLEN-1:0] slt_br_result = `XLEN'({is_br_op && ~(| sub_result[i][`XLEN-1:0]), sub_result[i][`XLEN]}); + wire [`XLEN-1:0] sub_slt_br_result = (is_sub_op && ~is_br_op) ? sub_result[i][`XLEN-1:0] : slt_br_result; + always @(*) begin + case ({is_alu_w, op_class}) + 3'b000: alu_result[i] = add_result[i]; // ADD, LUI, AUIPC + 3'b001: alu_result[i] = sub_slt_br_result; // SUB, SLTU, SLTI, BR* + 3'b010: alu_result[i] = shr_result[i]; // SRL, SRA, SRLI, SRAI + 3'b011: alu_result[i] = msc_result[i]; // AND, OR, XOR, SLL, SLLI + 3'b100: alu_result[i] = add_result_w[i]; // ADDIW, ADDW + 3'b101: alu_result[i] = sub_result_w[i]; // SUBW + 3'b110: alu_result[i] = shr_result_w[i]; // SRLW, SRAW, SRLIW, SRAIW + 3'b111: alu_result[i] = msc_result_w[i]; // SLLW + endcase + end + end + + // branch + + wire [`XLEN-1:0] PC_r, imm_r; + wire [`INST_BR_BITS-1:0] br_op_r; + wire [LANE_WIDTH-1:0] tid, tid_r; + wire is_br_op_r; + + if (LANE_BITS != 0) begin + assign tid = execute_if.data.tid[0 +: LANE_BITS]; + end else begin + assign tid = 0; + end + + VX_elastic_buffer #( + .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `NR_BITS + 1 + PID_WIDTH + 1 + 1 + (NUM_LANES * `XLEN) + `XLEN + `XLEN + 1 + `INST_BR_BITS + LANE_WIDTH) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (execute_if.valid), + .ready_in (execute_if.ready), + .data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, alu_result, execute_if.data.PC, execute_if.data.imm, is_br_op, br_op, tid}), + .data_out ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.rd, commit_if.data.wb, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop, alu_result_r, PC_r, imm_r, is_br_op_r, br_op_r, tid_r}), + .valid_out (commit_if.valid), + .ready_out (commit_if.ready) + ); + + `UNUSED_VAR (br_op_r) + wire is_br_neg = `INST_BR_IS_NEG(br_op_r); + wire is_br_less = `INST_BR_IS_LESS(br_op_r); + wire is_br_static = `INST_BR_IS_STATIC(br_op_r); + wire [`XLEN-1:0] br_result = alu_result_r[tid_r]; + + wire is_less = br_result[0]; + wire is_equal = br_result[1]; + + wire br_enable = is_br_op_r && commit_if.valid && commit_if.ready && commit_if.data.eop; + wire br_taken = ((is_br_less ? is_less : is_equal) ^ is_br_neg) | is_br_static; + wire [`XLEN-1:0] br_dest = is_br_static ? br_result : (PC_r + imm_r); + wire [`NW_WIDTH-1:0] br_wid; + `ASSIGN_BLOCKED_WID (br_wid, commit_if.data.wid, BLOCK_IDX, `NUM_ALU_BLOCKS) + + VX_pipe_register #( + .DATAW (1 + `NW_WIDTH + 1 + `XLEN) + ) branch_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({br_enable, br_wid, br_taken, br_dest}), + .data_out ({branch_ctl_if.valid, branch_ctl_if.wid, branch_ctl_if.taken, branch_ctl_if.dest}) + ); + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign commit_if.data.data[i] = (is_br_op_r && is_br_static) ? (PC_r + 4) : alu_result_r[i]; + end + + assign commit_if.data.PC = PC_r; + +`ifdef DBG_TRACE_CORE_PIPELINE + always @(posedge clk) begin + if (branch_ctl_if.valid) begin + `TRACE(1, ("%d: core%0d-branch: wid=%0d, PC=0x%0h, taken=%b, dest=0x%0h (#%0d)\n", + $time, CORE_ID, branch_ctl_if.wid, commit_if.data.PC, branch_ctl_if.taken, branch_ctl_if.dest, commit_if.data.uuid)); + end + end +`endif + +endmodule diff --git a/hw/rtl/core/VX_ipdom_stack.sv b/hw/rtl/core/VX_ipdom_stack.sv new file mode 100644 index 00000000..a6524b2d --- /dev/null +++ b/hw/rtl/core/VX_ipdom_stack.sv @@ -0,0 +1,108 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +module VX_ipdom_stack #( + parameter WIDTH = 1, + parameter DEPTH = 1, + parameter OUT_REG = 0, + parameter ADDRW = `LOG2UP(DEPTH) +) ( + input wire clk, + input wire reset, + input wire [WIDTH-1:0] q0, + input wire [WIDTH-1:0] q1, + output wire [WIDTH-1:0] d, + output wire d_set, + input wire push, + input wire pop, + output wire empty, + output wire full +); + reg slot_set [DEPTH-1:0]; + + reg [ADDRW-1:0] rd_ptr, wr_ptr; + + reg empty_r, full_r; + + wire [WIDTH-1:0] d0, d1; + + wire d_set_n = slot_set[rd_ptr]; + + always @(posedge clk) begin + if (reset) begin + rd_ptr <= '0; + wr_ptr <= '0; + empty_r <= 1; + full_r <= 0; + end else begin + `ASSERT(~push || ~full, ("runtime error: writing to a full stack!")); + `ASSERT(~pop || ~empty, ("runtime error: reading an empty stack!")); + `ASSERT(~push || ~pop, ("runtime error: push and pop in same cycle not supported!")); + if (push) begin + rd_ptr <= wr_ptr; + wr_ptr <= wr_ptr + ADDRW'(1); + empty_r <= 0; + full_r <= (ADDRW'(DEPTH-1) == wr_ptr); + end else if (pop) begin + wr_ptr <= wr_ptr - ADDRW'(d_set_n); + rd_ptr <= rd_ptr - ADDRW'(d_set_n); + empty_r <= (rd_ptr == 0) && (d_set_n == 1); + full_r <= 0; + end + end + end + + VX_dp_ram #( + .DATAW (WIDTH * 2), + .SIZE (DEPTH), + .OUT_REG (OUT_REG ? 1 : 0), + .LUTRAM (OUT_REG ? 0 : 1) + ) store ( + .clk (clk), + .read (1'b1), + .write (push), + `UNUSED_PIN (wren), + .waddr (wr_ptr), + .wdata ({q1, q0}), + .raddr (rd_ptr), + .rdata ({d1, d0}) + ); + + always @(posedge clk) begin + if (push) begin + slot_set[wr_ptr] <= 0; + end else if (pop) begin + slot_set[rd_ptr] <= 1; + end + end + + wire d_set_r; + VX_pipe_register #( + .DATAW (1), + .DEPTH (OUT_REG) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in (d_set_n), + .data_out (d_set_r) + ); + + assign d = d_set_r ? d0 : d1; + assign d_set = ~d_set_r; + assign empty = empty_r; + assign full = full_r; + +endmodule diff --git a/hw/rtl/core/VX_issue.sv b/hw/rtl/core/VX_issue.sv new file mode 100644 index 00000000..af00014e --- /dev/null +++ b/hw/rtl/core/VX_issue.sv @@ -0,0 +1,180 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" +`include "VX_trace.vh" + +module VX_issue #( + parameter CORE_ID = 0 +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + VX_pipeline_perf_if.issue perf_issue_if, +`endif + + VX_decode_if.slave decode_if, + VX_writeback_if.slave writeback_if [`ISSUE_WIDTH], + + VX_dispatch_if.master alu_dispatch_if [`ISSUE_WIDTH], + VX_dispatch_if.master lsu_dispatch_if [`ISSUE_WIDTH], +`ifdef EXT_F_ENABLE + VX_dispatch_if.master fpu_dispatch_if [`ISSUE_WIDTH], +`endif + VX_dispatch_if.master sfu_dispatch_if [`ISSUE_WIDTH] +); + VX_ibuffer_if ibuffer_if [`ISSUE_WIDTH](); + VX_ibuffer_if scoreboard_if [`ISSUE_WIDTH](); + VX_operands_if operands_if [`ISSUE_WIDTH](); + + `RESET_RELAY (ibuf_reset, reset); + `RESET_RELAY (scoreboard_reset, reset); + `RESET_RELAY (operands_reset, reset); + `RESET_RELAY (dispatch_reset, reset); + + VX_ibuffer #( + .CORE_ID (CORE_ID) + ) ibuffer ( + .clk (clk), + .reset (ibuf_reset), + .decode_if (decode_if), + .ibuffer_if (ibuffer_if) + ); + + VX_scoreboard #( + .CORE_ID (CORE_ID) + ) scoreboard ( + .clk (clk), + .reset (scoreboard_reset), + .writeback_if (writeback_if), + .ibuffer_if (ibuffer_if), + .scoreboard_if (scoreboard_if) + ); + + VX_operands #( + .CORE_ID (CORE_ID) + ) operands ( + .clk (clk), + .reset (operands_reset), + .writeback_if (writeback_if), + .scoreboard_if (scoreboard_if), + .operands_if (operands_if) + ); + + VX_dispatch #( + .CORE_ID (CORE_ID) + ) dispatch ( + .clk (clk), + .reset (dispatch_reset), + `ifdef PERF_ENABLE + .perf_stalls (perf_issue_if.dsp_stalls), + `endif + .operands_if (operands_if), + .alu_dispatch_if(alu_dispatch_if), + .lsu_dispatch_if(lsu_dispatch_if), + `ifdef EXT_F_ENABLE + .fpu_dispatch_if(fpu_dispatch_if), + `endif + .sfu_dispatch_if(sfu_dispatch_if) + ); + +`ifdef DBG_SCOPE_ISSUE + if (CORE_ID == 0) begin + `ifdef SCOPE + wire operands_if_fire = operands_if[0].valid && operands_if[0].ready; + wire operands_if_not_ready = ~operands_if[0].ready; + wire writeback_if_valid = writeback_if[0].valid; + VX_scope_tap #( + .SCOPE_ID (2), + .TRIGGERW (4), + .PROBEW (`UUID_WIDTH + `NUM_THREADS + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + + 1 + `NR_BITS + `XLEN + 1 + 1 + (`NUM_THREADS * 3 * `XLEN) + + `UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1) + ) scope_tap ( + .clk(clk), + .reset(scope_reset), + .start(1'b0), + .stop(1'b0), + .triggers({ + reset, + operands_if_fire, + operands_if_not_ready, + writeback_if_valid + }), + .probes({ + operands_if[0].data.uuid, + operands_if[0].data.tmask, + operands_if[0].data.ex_type, + operands_if[0].data.op_type, + operands_if[0].data.op_mod, + operands_if[0].data.wb, + operands_if[0].data.rd, + operands_if[0].data.imm, + operands_if[0].data.use_PC, + operands_if[0].data.use_imm, + operands_if[0].data.rs1_data, + operands_if[0].data.rs2_data, + operands_if[0].data.rs3_data, + writeback_if[0].data.uuid, + writeback_if[0].data.tmask, + writeback_if[0].data.rd, + writeback_if[0].data.data, + writeback_if[0].data.eop + }), + .bus_in(scope_bus_in), + .bus_out(scope_bus_out) + ); + `endif + `ifdef CHIPSCOPE + ila_issue ila_issue_inst ( + .clk (clk), + .probe0 ({operands_if.uuid, ibuffer.rs3, ibuffer.rs2, ibuffer.rs1, operands_if.PC, operands_if.tmask, operands_if.wid, operands_if.ex_type, operands_if.op_type, operands_if.ready, operands_if.valid}), + .probe1 ({writeback_if.uuid, writeback_if.data[0], writeback_if.PC, writeback_if.tmask, writeback_if.wid, writeback_if.eop, writeback_if.valid}) + ); + `endif + end +`else + `SCOPE_IO_UNUSED() +`endif + +`ifdef PERF_ENABLE + reg [`PERF_CTR_BITS-1:0] perf_ibf_stalls; + reg [`PERF_CTR_BITS-1:0] perf_scb_stalls; + + wire [`CLOG2(`ISSUE_WIDTH+1)-1:0] scoreboard_stalls_per_cycle; + reg [`ISSUE_WIDTH-1:0] scoreboard_stalls; + for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin + assign scoreboard_stalls[i] = ibuffer_if[i].valid && ~ibuffer_if[i].ready; + end + `POP_COUNT(scoreboard_stalls_per_cycle, scoreboard_stalls); + + always @(posedge clk) begin + if (reset) begin + perf_ibf_stalls <= '0; + perf_scb_stalls <= '0; + end else begin + if (decode_if.valid && ~decode_if.ready) begin + perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'(1); + end + perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'(scoreboard_stalls_per_cycle); + end + end + + assign perf_issue_if.ibf_stalls = perf_ibf_stalls; + assign perf_issue_if.scb_stalls = perf_scb_stalls; +`endif + +endmodule diff --git a/hw/rtl/core/VX_lsu_unit.sv b/hw/rtl/core/VX_lsu_unit.sv new file mode 100644 index 00000000..b939b081 --- /dev/null +++ b/hw/rtl/core/VX_lsu_unit.sv @@ -0,0 +1,647 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_lsu_unit import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Dcache interface + VX_mem_bus_if.master cache_bus_if [DCACHE_NUM_REQS], + + // inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH] +); + localparam BLOCK_SIZE = 1; + localparam NUM_LANES = `NUM_LSU_LANES; + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam RSP_ARB_DATAW= `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1; + localparam LSUQ_SIZEW = `LOG2UP(`LSUQ_SIZE); + localparam MEM_ASHIFT = `CLOG2(`MEM_BLOCK_SIZE); + localparam MEM_ADDRW = `XLEN - MEM_ASHIFT; + localparam REQ_ASHIFT = `CLOG2(DCACHE_WORD_SIZE); + localparam CACHE_TAG_WIDTH = `UUID_WIDTH + (NUM_LANES * `CACHE_ADDR_TYPE_BITS) + LSUQ_TAG_BITS; + + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) execute_if[BLOCK_SIZE](); + + `RESET_RELAY (dispatch_reset, reset); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (1) + ) dispatch_unit ( + .clk (clk), + .reset (dispatch_reset), + .dispatch_if(dispatch_if), + .execute_if (execute_if) + ); + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) commit_st_if(); + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) commit_ld_if(); + + `UNUSED_VAR (execute_if[0].data.op_mod) + `UNUSED_VAR (execute_if[0].data.use_PC) + `UNUSED_VAR (execute_if[0].data.use_imm) + `UNUSED_VAR (execute_if[0].data.rs3_data) + `UNUSED_VAR (execute_if[0].data.tid) + +`ifdef SM_ENABLE + `STATIC_ASSERT((1 << `SMEM_LOG_SIZE) == `MEM_BLOCK_SIZE * ((1 << `SMEM_LOG_SIZE) / `MEM_BLOCK_SIZE), ("invalid parameter")) + `STATIC_ASSERT(0 == (`SMEM_BASE_ADDR % (1 << `SMEM_LOG_SIZE)), ("invalid parameter")) + localparam SMEM_START_B = MEM_ADDRW'(`XLEN'(`SMEM_BASE_ADDR) >> MEM_ASHIFT); + localparam SMEM_END_B = MEM_ADDRW'((`XLEN'(`SMEM_BASE_ADDR) + (1 << `SMEM_LOG_SIZE)) >> MEM_ASHIFT); +`endif + + // tag = uuid + addr_type + wid + PC + tmask + rd + op_type + align + is_dup + pid + pkt_addr + localparam TAG_WIDTH = `UUID_WIDTH + (NUM_LANES * `CACHE_ADDR_TYPE_BITS) + `NW_WIDTH + `XLEN + NUM_LANES + `NR_BITS + `INST_LSU_BITS + (NUM_LANES * (REQ_ASHIFT)) + `LSU_DUP_ENABLED + PID_WIDTH + LSUQ_SIZEW; + + `STATIC_ASSERT(0 == (`IO_BASE_ADDR % `MEM_BLOCK_SIZE), ("invalid parameter")) + + wire [NUM_LANES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] lsu_addr_type; + + // full address calculation + + wire [NUM_LANES-1:0][`XLEN-1:0] full_addr; + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign full_addr[i] = execute_if[0].data.rs1_data[i][`XLEN-1:0] + execute_if[0].data.imm; + end + + // detect duplicate addresses + + wire lsu_is_dup; +`ifdef LSU_DUP + if (NUM_LANES > 1) begin + wire [NUM_LANES-2:0] addr_matches; + for (genvar i = 0; i < (NUM_LANES-1); ++i) begin + assign addr_matches[i] = (execute_if[0].data.rs1_data[i+1] == execute_if[0].data.rs1_data[0]) || ~execute_if[0].data.tmask[i+1]; + end + assign lsu_is_dup = execute_if[0].data.tmask[0] && (& addr_matches); + end else begin + assign lsu_is_dup = 0; + end +`else + assign lsu_is_dup = 0; +`endif + + // detect address type + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [MEM_ADDRW-1:0] full_addr_b = full_addr[i][MEM_ASHIFT +: MEM_ADDRW]; + // is non-cacheable I/O address + wire is_addr_io = (full_addr_b >= MEM_ADDRW'(`XLEN'(`IO_BASE_ADDR) >> MEM_ASHIFT)); + `ifdef SM_ENABLE + // is shared memory address + wire is_addr_sm = (full_addr_b >= SMEM_START_B) && (full_addr_b < SMEM_END_B); + assign lsu_addr_type[i] = {is_addr_io, is_addr_sm}; + `else + assign lsu_addr_type[i] = is_addr_io; + `endif + end + + wire mem_req_empty; + wire st_rsp_ready; + wire lsu_valid, lsu_ready; + + // fence: stall the pipeline until all pending requests are sent + wire is_fence = `INST_LSU_IS_FENCE(execute_if[0].data.op_type); + wire fence_wait = is_fence && ~mem_req_empty; + + assign lsu_valid = execute_if[0].valid && ~fence_wait; + assign execute_if[0].ready = lsu_ready && ~fence_wait; + + // schedule memory request + + wire mem_req_valid; + wire [NUM_LANES-1:0] mem_req_mask; + wire mem_req_rw; + wire [NUM_LANES-1:0][`MEM_ADDR_WIDTH-REQ_ASHIFT-1:0] mem_req_addr; + reg [NUM_LANES-1:0][DCACHE_WORD_SIZE-1:0] mem_req_byteen; + reg [NUM_LANES-1:0][`XLEN-1:0] mem_req_data; + wire [TAG_WIDTH-1:0] mem_req_tag; + wire mem_req_ready; + + wire mem_rsp_valid; + wire [NUM_LANES-1:0] mem_rsp_mask; + wire [NUM_LANES-1:0][`XLEN-1:0] mem_rsp_data; + wire [TAG_WIDTH-1:0] mem_rsp_tag; + wire mem_rsp_sop; + wire mem_rsp_eop; + wire mem_rsp_ready; + + assign mem_req_valid = lsu_valid; + assign lsu_ready = mem_req_ready + && (~mem_req_rw || st_rsp_ready); // writes commit directly + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign mem_req_mask[i] = execute_if[0].data.tmask[i] && (~lsu_is_dup || (i == 0)); + end + + assign mem_req_rw = ~execute_if[0].data.wb; + + wire mem_req_fire = mem_req_valid && mem_req_ready; + wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; + `UNUSED_VAR (mem_req_fire) + `UNUSED_VAR (mem_rsp_fire) + + // address formatting + + wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] req_align; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign req_align[i] = full_addr[i][REQ_ASHIFT-1:0]; + assign mem_req_addr[i] = full_addr[i][`MEM_ADDR_WIDTH-1:REQ_ASHIFT]; + end + + // byte enable formatting + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + mem_req_byteen[i] = '0; + case (`INST_LSU_WSIZE(execute_if[0].data.op_type)) + 0: begin // 8-bit + mem_req_byteen[i][req_align[i]] = 1'b1; + end + 1: begin // 16 bit + mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:1], 1'b0}] = 1'b1; + mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:1], 1'b1}] = 1'b1; + end + `ifdef XLEN_64 + 2: begin // 32 bit + mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b00}] = 1'b1; + mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b01}] = 1'b1; + mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b10}] = 1'b1; + mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b11}] = 1'b1; + end + `endif + default : mem_req_byteen[i] = {DCACHE_WORD_SIZE{1'b1}}; + endcase + end + end + + // memory misalignment not supported! + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire lsu_req_fire = execute_if[0].valid && execute_if[0].ready; + `RUNTIME_ASSERT((~lsu_req_fire || ~execute_if[0].data.tmask[i] || is_fence || (full_addr[i] % (1 << `INST_LSU_WSIZE(execute_if[0].data.op_type))) == 0), + ("misaligned memory access, wid=%0d, PC=0x%0h, addr=0x%0h, wsize=%0d! (#%0d)", + execute_if[0].data.wid, execute_if[0].data.PC, full_addr[i], `INST_LSU_WSIZE(execute_if[0].data.op_type), execute_if[0].data.uuid)); + end + + // store data formatting + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + mem_req_data[i] = execute_if[0].data.rs2_data[i]; + case (req_align[i]) + 1: mem_req_data[i][`XLEN-1:8] = execute_if[0].data.rs2_data[i][`XLEN-9:0]; + 2: mem_req_data[i][`XLEN-1:16] = execute_if[0].data.rs2_data[i][`XLEN-17:0]; + 3: mem_req_data[i][`XLEN-1:24] = execute_if[0].data.rs2_data[i][`XLEN-25:0]; + `ifdef XLEN_64 + 4: mem_req_data[i][`XLEN-1:32] = execute_if[0].data.rs2_data[i][`XLEN-33:0]; + 5: mem_req_data[i][`XLEN-1:40] = execute_if[0].data.rs2_data[i][`XLEN-41:0]; + 6: mem_req_data[i][`XLEN-1:48] = execute_if[0].data.rs2_data[i][`XLEN-49:0]; + 7: mem_req_data[i][`XLEN-1:56] = execute_if[0].data.rs2_data[i][`XLEN-57:0]; + `endif + default:; + endcase + end + end + + // track SOP/EOP for out-of-order memory responses + + wire [LSUQ_SIZEW-1:0] pkt_waddr, pkt_raddr; + wire mem_rsp_sop_pkt, mem_rsp_eop_pkt; + + if (PID_BITS != 0) begin + reg [`LSUQ_SIZE-1:0][PID_BITS:0] pkt_ctr; + reg [`LSUQ_SIZE-1:0] pkt_sop, pkt_eop; + + wire mem_req_rd_fire = mem_req_fire && execute_if[0].data.wb; + wire mem_req_rd_sop_fire = mem_req_rd_fire && execute_if[0].data.sop; + wire mem_req_rd_eop_fire = mem_req_rd_fire && execute_if[0].data.eop; + wire mem_rsp_eop_fire = mem_rsp_fire && mem_rsp_eop; + wire full; + + VX_allocator #( + .SIZE (`LSUQ_SIZE) + ) pkt_allocator ( + .clk (clk), + .reset (reset), + .acquire_en (mem_req_rd_eop_fire), + .acquire_addr(pkt_waddr), + .release_en (mem_rsp_eop_pkt), + .release_addr(pkt_raddr), + `UNUSED_PIN (empty), + .full (full) + ); + + wire rd_during_wr = mem_req_rd_fire && mem_rsp_eop_fire && (pkt_raddr == pkt_waddr); + + always @(posedge clk) begin + if (reset) begin + pkt_ctr <= '0; + pkt_sop <= '0; + pkt_eop <= '0; + end else begin + if (mem_req_rd_sop_fire) begin + pkt_sop[pkt_waddr] <= 1; + end + if (mem_req_rd_eop_fire) begin + pkt_eop[pkt_waddr] <= 1; + end + if (mem_rsp_fire) begin + pkt_sop[pkt_raddr] <= 0; + end + if (mem_rsp_eop_pkt) begin + pkt_eop[pkt_raddr] <= 0; + end + if (~rd_during_wr) begin + if (mem_req_rd_fire) begin + pkt_ctr[pkt_waddr] <= pkt_ctr[pkt_waddr] + PID_BITS'(1); + end + if (mem_rsp_eop_fire) begin + pkt_ctr[pkt_raddr] <= pkt_ctr[pkt_raddr] - PID_BITS'(1); + end + end + end + end + + assign mem_rsp_sop_pkt = pkt_sop[pkt_raddr]; + assign mem_rsp_eop_pkt = mem_rsp_eop_fire && pkt_eop[pkt_raddr] && (pkt_ctr[pkt_raddr] == 1); + `RUNTIME_ASSERT(~(mem_req_rd_fire && full), ("allocator full!")) + `RUNTIME_ASSERT(~mem_req_rd_sop_fire || 0 == pkt_ctr[pkt_waddr], ("Oops!")) + `UNUSED_VAR (mem_rsp_sop) + end else begin + assign pkt_waddr = 0; + assign mem_rsp_sop_pkt = mem_rsp_sop; + assign mem_rsp_eop_pkt = mem_rsp_eop; + `UNUSED_VAR (pkt_raddr) + end + + assign mem_req_tag = { + execute_if[0].data.uuid, lsu_addr_type, execute_if[0].data.wid, execute_if[0].data.tmask, execute_if[0].data.PC, execute_if[0].data.rd, execute_if[0].data.op_type, req_align, execute_if[0].data.pid, pkt_waddr + `ifdef LSU_DUP + , lsu_is_dup + `endif + }; + + wire [DCACHE_NUM_REQS-1:0] cache_req_valid; + wire [DCACHE_NUM_REQS-1:0] cache_req_rw; + wire [DCACHE_NUM_REQS-1:0][(`XLEN/8)-1:0] cache_req_byteen; + wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] cache_req_addr; + wire [DCACHE_NUM_REQS-1:0][`XLEN-1:0] cache_req_data; + wire [DCACHE_NUM_REQS-1:0][CACHE_TAG_WIDTH-1:0] cache_req_tag; + wire [DCACHE_NUM_REQS-1:0] cache_req_ready; + wire [DCACHE_NUM_REQS-1:0] cache_rsp_valid; + wire [DCACHE_NUM_REQS-1:0][`XLEN-1:0] cache_rsp_data; + wire [DCACHE_NUM_REQS-1:0][CACHE_TAG_WIDTH-1:0] cache_rsp_tag; + wire [DCACHE_NUM_REQS-1:0] cache_rsp_ready; + + `RESET_RELAY (mem_scheduler_reset, reset); + + VX_mem_scheduler #( + .INSTANCE_ID ($sformatf("core%0d-lsu-memsched", CORE_ID)), + .NUM_REQS (LSU_MEM_REQS), + .NUM_BANKS (DCACHE_NUM_REQS), + .ADDR_WIDTH (DCACHE_ADDR_WIDTH), + .DATA_WIDTH (`XLEN), + .QUEUE_SIZE (`LSUQ_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .MEM_TAG_ID (`UUID_WIDTH + (NUM_LANES * `CACHE_ADDR_TYPE_BITS)), + .UUID_WIDTH (`UUID_WIDTH), + .RSP_PARTIAL (1), + .MEM_OUT_REG (2) + ) mem_scheduler ( + .clk (clk), + .reset (mem_scheduler_reset), + + // Input request + .req_valid (mem_req_valid), + .req_rw (mem_req_rw), + .req_mask (mem_req_mask), + .req_byteen (mem_req_byteen), + .req_addr (mem_req_addr), + .req_data (mem_req_data), + .req_tag (mem_req_tag), + .req_empty (mem_req_empty), + .req_ready (mem_req_ready), + `UNUSED_PIN (write_notify), + + // Output response + .rsp_valid (mem_rsp_valid), + .rsp_mask (mem_rsp_mask), + .rsp_data (mem_rsp_data), + .rsp_tag (mem_rsp_tag), + .rsp_sop (mem_rsp_sop), + .rsp_eop (mem_rsp_eop), + .rsp_ready (mem_rsp_ready), + + // Memory request + .mem_req_valid (cache_req_valid), + .mem_req_rw (cache_req_rw), + .mem_req_byteen (cache_req_byteen), + .mem_req_addr (cache_req_addr), + .mem_req_data (cache_req_data), + .mem_req_tag (cache_req_tag), + .mem_req_ready (cache_req_ready), + + // Memory response + .mem_rsp_valid (cache_rsp_valid), + .mem_rsp_data (cache_rsp_data), + .mem_rsp_tag (cache_rsp_tag), + .mem_rsp_ready (cache_rsp_ready) + ); + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + assign cache_bus_if[i].req_valid = cache_req_valid[i]; + assign cache_bus_if[i].req_data.rw = cache_req_rw[i]; + assign cache_bus_if[i].req_data.byteen = cache_req_byteen[i]; + assign cache_bus_if[i].req_data.addr = cache_req_addr[i]; + assign cache_bus_if[i].req_data.data = cache_req_data[i]; + assign cache_req_ready[i] = cache_bus_if[i].req_ready; + + assign cache_rsp_valid[i] = cache_bus_if[i].rsp_valid; + assign cache_rsp_data[i] = cache_bus_if[i].rsp_data.data; + assign cache_bus_if[i].rsp_ready = cache_rsp_ready[i]; + end + + // cache tag formatting: + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + wire [`UUID_WIDTH-1:0] cache_req_uuid, cache_rsp_uuid; + wire [NUM_LANES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] cache_req_type, cache_rsp_type; + wire [`CLOG2(`LSUQ_SIZE)-1:0] cache_req_tag_x, cache_rsp_tag_x; + if (DCACHE_NUM_BATCHES > 1) begin + + wire [DCACHE_NUM_BATCHES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] cache_req_type_b, cache_rsp_type_b; + wire [`CACHE_ADDR_TYPE_BITS-1:0] cache_req_type_bi, cache_rsp_type_bi; + wire [DCACHE_BATCH_SEL_BITS-1:0] cache_req_bid, cache_rsp_bid; + + assign {cache_req_uuid, cache_req_type, cache_req_bid, cache_req_tag_x} = cache_req_tag[i]; + assign cache_req_type_bi = cache_req_type_b[cache_req_bid]; + assign cache_bus_if[i].req_data.tag = {cache_req_uuid, cache_req_bid, cache_req_tag_x, cache_req_type_bi}; + + assign {cache_rsp_uuid, cache_rsp_bid, cache_rsp_tag_x, cache_rsp_type_bi} = cache_bus_if[i].rsp_data.tag; + assign cache_rsp_type_b = {DCACHE_NUM_BATCHES{cache_rsp_type_bi}}; + assign cache_rsp_tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_bid, cache_rsp_tag_x}; + + for (genvar j = 0; j < DCACHE_NUM_BATCHES; ++j) begin + localparam k = j * DCACHE_NUM_REQS + i; + if (k < NUM_LANES) begin + assign cache_req_type_b[j] = cache_req_type[k]; + assign cache_rsp_type[k] = cache_rsp_type_b[j]; + end else begin + assign cache_req_type_b[j] = '0; + `UNUSED_VAR (cache_rsp_type_b[j]) + end + end + + end else begin + + assign {cache_req_uuid, cache_req_type, cache_req_tag_x} = cache_req_tag[i]; + assign cache_bus_if[i].req_data.tag = {cache_req_uuid, cache_req_tag_x, cache_req_type[i]}; + + assign {cache_rsp_uuid, cache_rsp_tag_x, cache_rsp_type[i]} = cache_bus_if[i].rsp_data.tag; + assign cache_rsp_tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_tag_x}; + + for (genvar j = 0; j < DCACHE_NUM_REQS; ++j) begin + if (i != j) begin + `UNUSED_VAR (cache_req_type[j]) + assign cache_rsp_type[j] = '0; + end + end + end + end + + wire [`UUID_WIDTH-1:0] rsp_uuid; + wire [NUM_LANES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] rsp_addr_type; + wire [`NW_WIDTH-1:0] rsp_wid; + wire [NUM_LANES-1:0] rsp_tmask_uq; + wire [`XLEN-1:0] rsp_pc; + wire [`NR_BITS-1:0] rsp_rd; + wire [`INST_LSU_BITS-1:0] rsp_op_type; + wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] rsp_align; + wire [PID_WIDTH-1:0] rsp_pid; + wire rsp_is_dup; + +`ifndef LSU_DUP + assign rsp_is_dup = 0; +`endif + + assign { + rsp_uuid, rsp_addr_type, rsp_wid, rsp_tmask_uq, rsp_pc, rsp_rd, rsp_op_type, rsp_align, rsp_pid, pkt_raddr + `ifdef LSU_DUP + , rsp_is_dup + `endif + } = mem_rsp_tag; + `UNUSED_VAR (rsp_addr_type) + `UNUSED_VAR (rsp_op_type) + + // load response formatting + + reg [NUM_LANES-1:0][`XLEN-1:0] rsp_data; + wire [NUM_LANES-1:0] rsp_tmask; + +`ifdef XLEN_64 +`ifdef EXT_F_ENABLE + // apply nan-boxing to flw outputs + wire rsp_is_float = rsp_rd[5]; +`else + wire rsp_is_float = 0; +`endif +`endif + + for (genvar i = 0; i < NUM_LANES; i++) begin + `ifdef XLEN_64 + wire [63:0] rsp_data64 = (i == 0 || rsp_is_dup) ? mem_rsp_data[0] : mem_rsp_data[i]; + wire [31:0] rsp_data32 = (i == 0 || rsp_is_dup) ? (rsp_align[0][2] ? mem_rsp_data[0][63:32] : mem_rsp_data[0][31:0]) : + (rsp_align[i][2] ? mem_rsp_data[i][63:32] : mem_rsp_data[i][31:0]); + `else + wire [31:0] rsp_data32 = (i == 0 || rsp_is_dup) ? mem_rsp_data[0] : mem_rsp_data[i]; + `endif + wire [15:0] rsp_data16 = rsp_align[i][1] ? rsp_data32[31:16] : rsp_data32[15:0]; + wire [7:0] rsp_data8 = rsp_align[i][0] ? rsp_data16[15:8] : rsp_data16[7:0]; + + always @(*) begin + case (`INST_LSU_FMT(rsp_op_type)) + `INST_FMT_B: rsp_data[i] = `XLEN'(signed'(rsp_data8)); + `INST_FMT_H: rsp_data[i] = `XLEN'(signed'(rsp_data16)); + `INST_FMT_BU: rsp_data[i] = `XLEN'(unsigned'(rsp_data8)); + `INST_FMT_HU: rsp_data[i] = `XLEN'(unsigned'(rsp_data16)); + `ifdef XLEN_64 + `INST_FMT_W: rsp_data[i] = rsp_is_float ? (`XLEN'(rsp_data32) | 64'hffffffff00000000) : `XLEN'(signed'(rsp_data32)); + `INST_FMT_WU: rsp_data[i] = `XLEN'(unsigned'(rsp_data32)); + `INST_FMT_D: rsp_data[i] = `XLEN'(signed'(rsp_data64)); + `else + `INST_FMT_W: rsp_data[i] = `XLEN'(signed'(rsp_data32)); + `endif + default: rsp_data[i] = 'x; + endcase + end + end + + assign rsp_tmask = rsp_is_dup ? rsp_tmask_uq : mem_rsp_mask; + + // load commit + + VX_elastic_buffer #( + .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + (NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1), + .SIZE (2) + ) ld_rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_rsp_valid), + .ready_in (mem_rsp_ready), + .data_in ({rsp_uuid, rsp_wid, rsp_tmask, rsp_pc, rsp_rd, rsp_data, rsp_pid, mem_rsp_sop_pkt, mem_rsp_eop_pkt}), + .data_out ({commit_ld_if.data.uuid, commit_ld_if.data.wid, commit_ld_if.data.tmask, commit_ld_if.data.PC, commit_ld_if.data.rd, commit_ld_if.data.data, commit_ld_if.data.pid, commit_ld_if.data.sop, commit_ld_if.data.eop}), + .valid_out (commit_ld_if.valid), + .ready_out (commit_ld_if.ready) + ); + + assign commit_ld_if.data.wb = 1'b1; + + // store commit + + VX_elastic_buffer #( + .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + PID_WIDTH + 1 + 1), + .SIZE (2) + ) st_rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_fire && mem_req_rw), + .ready_in (st_rsp_ready), + .data_in ({execute_if[0].data.uuid, execute_if[0].data.wid, execute_if[0].data.tmask, execute_if[0].data.PC, execute_if[0].data.pid, execute_if[0].data.sop, execute_if[0].data.eop}), + .data_out ({commit_st_if.data.uuid, commit_st_if.data.wid, commit_st_if.data.tmask, commit_st_if.data.PC, commit_st_if.data.pid, commit_st_if.data.sop, commit_st_if.data.eop}), + .valid_out (commit_st_if.valid), + .ready_out (commit_st_if.ready) + ); + assign commit_st_if.data.rd = '0; + assign commit_st_if.data.wb = 1'b0; + assign commit_st_if.data.data = commit_ld_if.data.data; // force arbiter passthru + + // lsu commit + + `RESET_RELAY (commit_reset, reset); + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) commit_arb_if[1](); + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (RSP_ARB_DATAW), + .OUT_REG (1) + ) rsp_arb ( + .clk (clk), + .reset (commit_reset), + .valid_in ({commit_st_if.valid, commit_ld_if.valid}), + .ready_in ({commit_st_if.ready, commit_ld_if.ready}), + .data_in ({commit_st_if.data, commit_ld_if.data}), + .data_out (commit_arb_if[0].data), + .valid_out (commit_arb_if[0].valid), + .ready_out (commit_arb_if[0].ready), + `UNUSED_PIN (sel_out) + ); + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (3) + ) gather_unit ( + .clk (clk), + .reset (commit_reset), + .commit_in_if (commit_arb_if), + .commit_out_if (commit_if) + ); + +`ifdef DBG_SCOPE_LSU + if (CORE_ID == 0) begin + `ifdef SCOPE + VX_scope_tap #( + .SCOPE_ID (3), + .TRIGGERW (3), + .PROBEW (`UUID_WIDTH+NUM_LANES*(`XLEN+4+`XLEN)+1+`UUID_WIDTH+NUM_LANES*`XLEN) + ) scope_tap ( + .clk(clk), + .reset(scope_reset), + .start(1'b0), + .stop(1'b0), + .triggers({reset, mem_req_fire, mem_rsp_fire}), + .probes({execute_if[0].data.uuid, full_addr, mem_req_rw, mem_req_byteen, mem_req_data, rsp_uuid, rsp_data}), + .bus_in(scope_bus_in), + .bus_out(scope_bus_out) + ); + `endif + `ifdef CHIPSCOPE + wire [31:0] full_addr_0 = full_addr[0]; + wire [31:0] mem_req_data_0 = mem_req_data[0]; + wire [31:0] rsp_data_0 = rsp_data[0]; + ila_lsu ila_lsu_inst ( + .clk (clk), + .probe0 ({mem_req_data_0, execute_if[0].data.uuid, execute_if[0].data.wid, execute_if[0].data.PC, mem_req_mask, full_addr_0, mem_req_byteen, mem_req_rw, mem_req_ready, mem_req_valid}), + .probe1 ({rsp_data_0, rsp_uuid, mem_rsp_eop, rsp_pc, rsp_rd, rsp_tmask, rsp_wid, mem_rsp_ready, mem_rsp_valid}), + .probe2 ({cache_bus_if.req_data.data, cache_bus_if.req_data.tag, cache_bus_if.req_data.byteen, cache_bus_if.req_data.addr, cache_bus_if.req_data.rw, cache_bus_if.req_ready, cache_bus_if.req_valid}), + .probe3 ({cache_bus_if.rsp_data.data, cache_bus_if.rsp_data.tag, cache_bus_if.rsp_ready, cache_bus_if.rsp_valid}) + ); + `endif + end +`else + `SCOPE_IO_UNUSED() +`endif + +`ifdef DBG_TRACE_CORE_DCACHE + always @(posedge clk) begin + if (execute_if[0].valid && fence_wait) begin + `TRACE(1, ("%d: *** D$%0d fence wait\n", $time, CORE_ID)); + end + if (mem_req_fire) begin + if (mem_req_rw) begin + `TRACE(1, ("%d: D$%0d Wr Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, execute_if[0].data.wid, execute_if[0].data.PC, mem_req_mask)); + `TRACE_ARRAY1D(1, full_addr, NUM_LANES); + `TRACE(1, (", tag=0x%0h, byteen=0x%0h, type=", mem_req_tag, mem_req_byteen)); + `TRACE_ARRAY1D(1, lsu_addr_type, NUM_LANES); + `TRACE(1, (", data=")); + `TRACE_ARRAY1D(1, mem_req_data, NUM_LANES); + `TRACE(1, (", is_dup=%b (#%0d)\n", lsu_is_dup, execute_if[0].data.uuid)); + end else begin + `TRACE(1, ("%d: D$%0d Rd Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, execute_if[0].data.wid, execute_if[0].data.PC, mem_req_mask)); + `TRACE_ARRAY1D(1, full_addr, NUM_LANES); + `TRACE(1, (", tag=0x%0h, byteen=0x%0h, type=", mem_req_tag, mem_req_byteen)); + `TRACE_ARRAY1D(1, lsu_addr_type, NUM_LANES); + `TRACE(1, (", rd=%0d, is_dup=%b (#%0d)\n", execute_if[0].data.rd, lsu_is_dup, execute_if[0].data.uuid)); + end + end + if (mem_rsp_fire) begin + `TRACE(1, ("%d: D$%0d Rsp: wid=%0d, PC=0x%0h, tmask=%b, tag=0x%0h, rd=%0d, sop=%b, eop=%b, data=", + $time, CORE_ID, rsp_wid, rsp_pc, mem_rsp_mask, mem_rsp_tag, rsp_rd, mem_rsp_sop, mem_rsp_eop)); + `TRACE_ARRAY1D(1, mem_rsp_data, NUM_LANES); + `TRACE(1, (", is_dup=%b (#%0d)\n", rsp_is_dup, rsp_uuid)); + end + end +`endif + +endmodule diff --git a/hw/rtl/core/VX_muldiv_unit.sv b/hw/rtl/core/VX_muldiv_unit.sv new file mode 100644 index 00000000..f3c730d4 --- /dev/null +++ b/hw/rtl/core/VX_muldiv_unit.sv @@ -0,0 +1,336 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_muldiv_unit #( + parameter CORE_ID = 0, + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_commit_if.master commit_if +); + `UNUSED_PARAM (CORE_ID) + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam TAGW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + PID_WIDTH + 1 + 1; + + `UNUSED_VAR (execute_if.data.rs3_data) + + wire [`INST_M_BITS-1:0] muldiv_op = `INST_M_BITS'(execute_if.data.op_type); + + wire is_mulx_op = `INST_M_IS_MULX(muldiv_op); + wire is_signed_op = `INST_M_SIGNED(muldiv_op); +`ifdef XLEN_64 + wire is_alu_w = `INST_ALU_IS_W(execute_if.data.op_mod); +`else + wire is_alu_w = 0; +`endif + + wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_out; + wire [`UUID_WIDTH-1:0] mul_uuid_out; + wire [`NW_WIDTH-1:0] mul_wid_out; + wire [NUM_LANES-1:0] mul_tmask_out; + wire [`XLEN-1:0] mul_PC_out; + wire [`NR_BITS-1:0] mul_rd_out; + wire mul_wb_out; + wire [PID_WIDTH-1:0] mul_pid_out; + wire mul_sop_out, mul_eop_out; + + wire mul_valid_in = execute_if.valid && is_mulx_op; + wire mul_ready_in; + wire mul_valid_out; + wire mul_ready_out; + + wire is_mulh_in = `INST_M_IS_MULH(muldiv_op); + wire is_signed_mul_a = `INST_M_SIGNED_A(muldiv_op); + wire is_signed_mul_b = is_signed_op; + +`ifdef IMUL_DPI + + wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_tmp; + + wire mul_fire_in = mul_valid_in && mul_ready_in; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [`XLEN-1:0] mul_resultl, mul_resulth; + wire [`XLEN-1:0] mul_in1 = is_alu_w ? (execute_if.data.rs1_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs1_data[i]; + wire [`XLEN-1:0] mul_in2 = is_alu_w ? (execute_if.data.rs2_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs2_data[i]; + always @(*) begin + dpi_imul (mul_fire_in, is_signed_mul_a, is_signed_mul_b, mul_in1, mul_in2, mul_resultl, mul_resulth); + end + assign mul_result_tmp[i] = is_mulh_in ? mul_resulth : (is_alu_w ? `XLEN'($signed(mul_resultl[31:0])) : mul_resultl); + end + + VX_shift_register #( + .DATAW (1 + TAGW + (NUM_LANES * `XLEN)), + .DEPTH (`LATENCY_IMUL), + .RESETW (1) + ) mul_shift_reg ( + .clk(clk), + .reset (reset), + .enable (mul_ready_in), + .data_in ({mul_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, mul_result_tmp}), + .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, mul_result_out}) + ); + + assign mul_ready_in = mul_ready_out || ~mul_valid_out; + +`else + + wire [NUM_LANES-1:0][2*(`XLEN+1)-1:0] mul_result_tmp; + wire is_mulh_out; + wire is_mul_w_out; + +`ifdef XLEN_64 + + wire [NUM_LANES-1:0][`XLEN:0] mul_in1; + wire [NUM_LANES-1:0][`XLEN:0] mul_in2; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign mul_in1[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]} : {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]}; + assign mul_in2[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]} : {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]}; + end + + wire mul_strode; + wire mul_busy; + + VX_elastic_adapter mul_elastic_adapter ( + .clk (clk), + .reset (reset), + .valid_in (mul_valid_in), + .ready_in (mul_ready_in), + .valid_out (mul_valid_out), + .ready_out (mul_ready_out), + .strobe (mul_strode), + .busy (mul_busy) + ); + + VX_serial_mul #( + .A_WIDTH (`XLEN+1), + .LANES (NUM_LANES), + .SIGNED (1) + ) serial_mul ( + .clk (clk), + .reset (reset), + + .strobe (mul_strode), + .busy (mul_busy), + + .dataa (mul_in1), + .datab (mul_in2), + .result (mul_result_tmp) + ); + + reg [TAGW+2-1:0] mul_tag_r; + always @(posedge clk) begin + if (mul_valid_in && mul_ready_in) begin + mul_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_mulh_in, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}; + end + end + + assign {mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out, is_mul_w_out, mul_pid_out, mul_sop_out, mul_eop_out} = mul_tag_r; + +`else + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [`XLEN:0] mul_in1 = {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]}; + wire [`XLEN:0] mul_in2 = {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]}; + + VX_multiplier #( + .A_WIDTH (`XLEN+1), + .B_WIDTH (`XLEN+1), + .R_WIDTH (2*(`XLEN+1)), + .SIGNED (1), + .LATENCY (`LATENCY_IMUL) + ) multiplier ( + .clk (clk), + .enable (mul_ready_in), + .dataa (mul_in1), + .datab (mul_in2), + .result (mul_result_tmp[i]) + ); + end + + VX_shift_register #( + .DATAW (1 + TAGW + 1 + 1), + .DEPTH (`LATENCY_IMUL), + .RESETW (1) + ) mul_shift_reg ( + .clk(clk), + .reset (reset), + .enable (mul_ready_in), + .data_in ({mul_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, is_mulh_in, is_alu_w}), + .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, is_mulh_out, is_mul_w_out}) + ); + + assign mul_ready_in = mul_ready_out || ~mul_valid_out; + +`endif + + for (genvar i = 0; i < NUM_LANES; ++i) begin + `ifdef XLEN_64 + assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] : + (is_mul_w_out ? `XLEN'($signed(mul_result_tmp[i][31:0])) : + mul_result_tmp[i][`XLEN-1:0]); + `else + assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] : mul_result_tmp[i][`XLEN-1:0]; + `UNUSED_VAR (is_mul_w_out) + `endif + end + +`endif + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_LANES-1:0][`XLEN-1:0] div_result_out; + wire [`UUID_WIDTH-1:0] div_uuid_out; + wire [`NW_WIDTH-1:0] div_wid_out; + wire [NUM_LANES-1:0] div_tmask_out; + wire [`XLEN-1:0] div_PC_out; + wire [`NR_BITS-1:0] div_rd_out; + wire div_wb_out; + wire [PID_WIDTH-1:0] div_pid_out; + wire div_sop_out, div_eop_out; + + wire is_rem_op = `INST_M_IS_REM(muldiv_op); + + wire div_valid_in = execute_if.valid && ~is_mulx_op; + wire div_ready_in; + wire div_valid_out; + wire div_ready_out; + + wire [NUM_LANES-1:0][`XLEN-1:0] div_in1; + wire [NUM_LANES-1:0][`XLEN-1:0] div_in2; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign div_in1[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]}: execute_if.data.rs1_data[i]; + assign div_in2[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]}: execute_if.data.rs2_data[i]; + end + +`ifdef IDIV_DPI + + wire [NUM_LANES-1:0][`XLEN-1:0] div_result_in; + wire div_fire_in = div_valid_in && div_ready_in; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [`XLEN-1:0] div_quotient, div_remainder; + always @(*) begin + dpi_idiv (div_fire_in, is_signed_op, div_in1[i], div_in2[i], div_quotient, div_remainder); + end + assign div_result_in[i] = is_rem_op ? (is_alu_w ? `XLEN'($signed(div_remainder[31:0])) : div_remainder) : + (is_alu_w ? `XLEN'($signed(div_quotient[31:0])) : div_quotient); + end + + VX_shift_register #( + .DATAW (1 + TAGW + (NUM_LANES * `XLEN)), + .DEPTH (`LATENCY_IMUL), + .RESETW (1) + ) div_shift_reg ( + .clk(clk), + .reset (reset), + .enable (div_ready_in), + .data_in ({div_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, div_result_in}), + .data_out ({div_valid_out, div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, div_pid_out, div_sop_out, div_eop_out, div_result_out}) + ); + + assign div_ready_in = div_ready_out || ~div_valid_out; + +`else + + wire [NUM_LANES-1:0][`XLEN-1:0] div_quotient, div_remainder; + wire is_rem_op_out; + wire is_div_w_out; + wire div_strode; + wire div_busy; + + VX_elastic_adapter div_elastic_adapter ( + .clk (clk), + .reset (reset), + .valid_in (div_valid_in), + .ready_in (div_ready_in), + .valid_out (div_valid_out), + .ready_out (div_ready_out), + .strobe (div_strode), + .busy (div_busy) + ); + + VX_serial_div #( + .WIDTHN (`XLEN), + .WIDTHD (`XLEN), + .WIDTHQ (`XLEN), + .WIDTHR (`XLEN), + .LANES (NUM_LANES) + ) serial_div ( + .clk (clk), + .reset (reset), + + .strobe (div_strode), + .busy (div_busy), + + .is_signed (is_signed_op), + .numer (div_in1), + .denom (div_in2), + + .quotient (div_quotient), + .remainder (div_remainder) + ); + + reg [TAGW+2-1:0] div_tag_r; + always @(posedge clk) begin + if (div_valid_in && div_ready_in) begin + div_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_rem_op, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}; + end + end + + assign {div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out, is_div_w_out, div_pid_out, div_sop_out, div_eop_out} = div_tag_r; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + `ifdef XLEN_64 + assign div_result_out[i] = is_rem_op_out ? (is_div_w_out ? `XLEN'($signed(div_remainder[i][31:0])) : div_remainder[i]) : + (is_div_w_out ? `XLEN'($signed(div_quotient[i][31:0])) : div_quotient[i]); + `else + assign div_result_out[i] = is_rem_op_out ? div_remainder[i] : div_quotient[i]; + `UNUSED_VAR (is_div_w_out) + `endif + end + +`endif + + // can accept new request? + assign execute_if.ready = is_mulx_op ? mul_ready_in : div_ready_in; + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (TAGW + (NUM_LANES * `XLEN)), + .OUT_REG (1) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in ({div_valid_out, mul_valid_out}), + .ready_in ({div_ready_out, mul_ready_out}), + .data_in ({{div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, div_pid_out, div_sop_out, div_eop_out, div_result_out}, + {mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, mul_result_out}}), + .data_out ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.PC, commit_if.data.rd, commit_if.data.wb, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop, commit_if.data.data}), + .valid_out (commit_if.valid), + .ready_out (commit_if.ready), + `UNUSED_PIN (sel_out) + ); + +endmodule diff --git a/hw/rtl/core/VX_operands.sv b/hw/rtl/core/VX_operands.sv new file mode 100644 index 00000000..3d2c570c --- /dev/null +++ b/hw/rtl/core/VX_operands.sv @@ -0,0 +1,302 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_operands import VX_gpu_pkg::*; #( + parameter CORE_ID = 0, + parameter CACHE_ENABLE = 0 +) ( + input wire clk, + input wire reset, + + VX_writeback_if.slave writeback_if [`ISSUE_WIDTH], + VX_ibuffer_if.slave scoreboard_if [`ISSUE_WIDTH], + VX_operands_if.master operands_if [`ISSUE_WIDTH] +); + `UNUSED_PARAM (CORE_ID) + localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + `NR_BITS; + + localparam STATE_IDLE = 2'd0; + localparam STATE_FETCH1 = 2'd1; + localparam STATE_FETCH2 = 2'd2; + localparam STATE_FETCH3 = 2'd3; + localparam STATE_BITS = 2; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + wire [`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data; + reg [`NR_BITS-1:0] gpr_rd_rid, gpr_rd_rid_n; + reg [ISSUE_WIS_W-1:0] gpr_rd_wis, gpr_rd_wis_n; + + reg [ISSUE_RATIO-1:0][`NUM_THREADS-1:0][`XLEN-1:0] cache_data, cache_data_n; + reg [ISSUE_RATIO-1:0][`NR_BITS-1:0] cache_reg, cache_reg_n; + reg [ISSUE_RATIO-1:0][`NUM_THREADS-1:0] cache_tmask, cache_tmask_n; + reg [ISSUE_RATIO-1:0] cache_eop, cache_eop_n; + + reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n; + reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n; + reg [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data, rs3_data_n; + + reg [STATE_BITS-1:0] state, state_n; + reg [`NR_BITS-1:0] rs2, rs2_n; + reg [`NR_BITS-1:0] rs3, rs3_n; + reg rs2_ready, rs2_ready_n; + reg rs3_ready, rs3_ready_n; + reg data_ready, data_ready_n; + + wire is_rs1_zero = (scoreboard_if[i].data.rs1 == 0); + wire is_rs2_zero = (scoreboard_if[i].data.rs2 == 0); + wire is_rs3_zero = (scoreboard_if[i].data.rs3 == 0); + + VX_operands_if staging_if(); + + always @(*) begin + state_n = state; + rs2_n = rs2; + rs3_n = rs3; + rs2_ready_n = rs2_ready; + rs3_ready_n = rs3_ready; + rs1_data_n = rs1_data; + rs2_data_n = rs2_data; + rs3_data_n = rs3_data; + cache_data_n = cache_data; + cache_reg_n = cache_reg; + cache_tmask_n= cache_tmask; + cache_eop_n = cache_eop; + gpr_rd_rid_n = gpr_rd_rid; + gpr_rd_wis_n = gpr_rd_wis; + data_ready_n = data_ready; + + case (state) + STATE_IDLE: begin + if (staging_if.valid && staging_if.ready) begin + data_ready_n = 0; + end + if (scoreboard_if[i].valid && data_ready_n == 0) begin + data_ready_n = 1; + if (is_rs3_zero || (CACHE_ENABLE != 0 && + scoreboard_if[i].data.rs3 == cache_reg[scoreboard_if[i].data.wis] && + (scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin + rs3_data_n = (is_rs3_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis]; + rs3_ready_n = 1; + end else begin + rs3_ready_n = 0; + gpr_rd_rid_n = scoreboard_if[i].data.rs3; + data_ready_n = 0; + state_n = STATE_FETCH3; + end + if (is_rs2_zero || (CACHE_ENABLE != 0 && + scoreboard_if[i].data.rs2 == cache_reg[scoreboard_if[i].data.wis] && + (scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin + rs2_data_n = (is_rs2_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis]; + rs2_ready_n = 1; + end else begin + rs2_ready_n = 0; + gpr_rd_rid_n = scoreboard_if[i].data.rs2; + data_ready_n = 0; + state_n = STATE_FETCH2; + end + if (is_rs1_zero || (CACHE_ENABLE != 0 && + scoreboard_if[i].data.rs1 == cache_reg[scoreboard_if[i].data.wis] && + (scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin + rs1_data_n = (is_rs1_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis]; + end else begin + gpr_rd_rid_n = scoreboard_if[i].data.rs1; + data_ready_n = 0; + state_n = STATE_FETCH1; + end + end + gpr_rd_wis_n = scoreboard_if[i].data.wis; + rs2_n = scoreboard_if[i].data.rs2; + rs3_n = scoreboard_if[i].data.rs3; + end + STATE_FETCH1: begin + rs1_data_n = gpr_rd_data; + if (~rs2_ready) begin + gpr_rd_rid_n = rs2; + state_n = STATE_FETCH2; + end else if (~rs3_ready) begin + gpr_rd_rid_n = rs3; + state_n = STATE_FETCH3; + end else begin + data_ready_n = 1; + state_n = STATE_IDLE; + end + end + STATE_FETCH2: begin + rs2_data_n = gpr_rd_data; + if (~rs3_ready) begin + gpr_rd_rid_n = rs3; + state_n = STATE_FETCH3; + end else begin + data_ready_n = 1; + state_n = STATE_IDLE; + end + end + STATE_FETCH3: begin + rs3_data_n = gpr_rd_data; + data_ready_n = 1; + state_n = STATE_IDLE; + end + endcase + + if (CACHE_ENABLE != 0 && writeback_if[i].valid) begin + if ((cache_reg[writeback_if[i].data.wis] == writeback_if[i].data.rd) + || (cache_eop[writeback_if[i].data.wis] && writeback_if[i].data.sop)) begin + for (integer j = 0; j < `NUM_THREADS; ++j) begin + if (writeback_if[i].data.tmask[j]) begin + cache_data_n[writeback_if[i].data.wis][j] = writeback_if[i].data.data[j]; + end + end + cache_reg_n[writeback_if[i].data.wis] = writeback_if[i].data.rd; + cache_eop_n[writeback_if[i].data.wis] = writeback_if[i].data.eop; + if (writeback_if[i].data.sop) begin + cache_tmask_n[writeback_if[i].data.wis] = writeback_if[i].data.tmask; + end else begin + cache_tmask_n[writeback_if[i].data.wis] |= writeback_if[i].data.tmask; + end + end + end + end + + always @(posedge clk) begin + if (reset) begin + state <= STATE_IDLE; + gpr_rd_rid <= '0; + gpr_rd_wis <= '0; + cache_eop <= {ISSUE_RATIO{1'b1}}; + cache_reg <= '0; + data_ready <= 0; + end else begin + state <= state_n; + rs2 <= rs2_n; + rs3 <= rs3_n; + rs2_ready <= rs2_ready_n; + rs3_ready <= rs3_ready_n; + rs1_data <= rs1_data_n; + rs2_data <= rs2_data_n; + rs3_data <= rs3_data_n; + gpr_rd_rid <= gpr_rd_rid_n; + gpr_rd_wis <= gpr_rd_wis_n; + cache_data <= cache_data_n; + cache_reg <= cache_reg_n; + cache_tmask <= cache_tmask_n; + cache_eop <= cache_eop_n; + data_ready <= data_ready_n; + end + end + + // GPR banks + + `ifdef GPR_RESET + reg wr_enabled = 0; + always @(posedge clk) begin + if (reset) begin + wr_enabled <= 1; + end + end + `else + wire wr_enabled = 1; + `endif + + for (genvar j = 0; j < `NUM_THREADS; ++j) begin + VX_dp_ram #( + .DATAW (`XLEN), + .SIZE (`NUM_REGS * ISSUE_RATIO), + `ifdef GPR_RESET + .INIT_ENABLE (1), + .INIT_VALUE (0), + `endif + .NO_RWCHECK (1) + ) gpr_ram ( + .clk (clk), + .read (1'b1), + `UNUSED_PIN (wren), + .write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]), + .waddr (wis_to_addr(writeback_if[i].data.rd, writeback_if[i].data.wis)), + .wdata (writeback_if[i].data.data[j]), + .raddr (wis_to_addr(gpr_rd_rid, gpr_rd_wis)), + .rdata (gpr_rd_data[j]) + ); + end + + // staging buffer + + `RESET_RELAY (stg_buf_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW) + ) stg_buf ( + .clk (clk), + .reset (stg_buf_reset), + .valid_in (scoreboard_if[i].valid), + .ready_in (scoreboard_if[i].ready), + .data_in ({ + scoreboard_if[i].data.uuid, + scoreboard_if[i].data.wis, + scoreboard_if[i].data.tmask, + scoreboard_if[i].data.PC, + scoreboard_if[i].data.wb, + scoreboard_if[i].data.ex_type, + scoreboard_if[i].data.op_type, + scoreboard_if[i].data.op_mod, + scoreboard_if[i].data.use_PC, + scoreboard_if[i].data.use_imm, + scoreboard_if[i].data.imm, + scoreboard_if[i].data.rd}), + .data_out ({ + staging_if.data.uuid, + staging_if.data.wis, + staging_if.data.tmask, + staging_if.data.PC, + staging_if.data.wb, + staging_if.data.ex_type, + staging_if.data.op_type, + staging_if.data.op_mod, + staging_if.data.use_PC, + staging_if.data.use_imm, + staging_if.data.imm, + staging_if.data.rd}), + .valid_out (staging_if.valid), + .ready_out (staging_if.ready) + ); + + assign staging_if.data.rs1_data = rs1_data; + assign staging_if.data.rs2_data = rs2_data; + assign staging_if.data.rs3_data = rs3_data; + + // output buffer + + wire valid_stg, ready_stg; + assign valid_stg = staging_if.valid && data_ready; + assign staging_if.ready = ready_stg && data_ready; + + `RESET_RELAY (out_buf_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW + (3 * `NUM_THREADS * `XLEN)), + .SIZE (2), + .OUT_REG (2) + ) out_buf ( + .clk (clk), + .reset (out_buf_reset), + .valid_in (valid_stg), + .ready_in (ready_stg), + .data_in (staging_if.data), + .data_out (operands_if[i].data), + .valid_out (operands_if[i].valid), + .ready_out (operands_if[i].ready) + ); + end + +endmodule diff --git a/hw/rtl/core/VX_pending_instr.sv b/hw/rtl/core/VX_pending_instr.sv new file mode 100644 index 00000000..af87b53e --- /dev/null +++ b/hw/rtl/core/VX_pending_instr.sv @@ -0,0 +1,79 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_pending_instr #( + parameter CTR_WIDTH = 12, + parameter ALM_EMPTY = 1, + parameter DECR_COUNT = 1 +) ( + input wire clk, + input wire reset, + input wire incr, + input wire [`NW_WIDTH-1:0] incr_wid, + input wire [DECR_COUNT-1:0] decr, + input wire [DECR_COUNT-1:0][`NW_WIDTH-1:0] decr_wid, + input wire [`NW_WIDTH-1:0] alm_empty_wid, + output wire empty, + output wire alm_empty +); + localparam COUNTW = `CLOG2(DECR_COUNT+1); + + reg [`NUM_WARPS-1:0][CTR_WIDTH-1:0] pending_instrs; + reg [`NUM_WARPS-1:0][COUNTW-1:0] decr_cnt; + reg [`NUM_WARPS-1:0][DECR_COUNT-1:0] decr_mask; + reg [`NUM_WARPS-1:0] incr_cnt, incr_cnt_n; + reg [`NUM_WARPS-1:0] alm_empty_r, empty_r; + + always @(*) begin + incr_cnt_n = 0; + decr_mask = 0; + if (incr) begin + incr_cnt_n[incr_wid] = 1; + end + for (integer i = 0; i < DECR_COUNT; ++i) begin + if (decr[i]) begin + decr_mask[decr_wid[i]][i] = 1; + end + end + end + + for (genvar i = 0; i < `NUM_WARPS; ++i) begin + + wire [COUNTW-1:0] decr_cnt_n; + `POP_COUNT(decr_cnt_n, decr_mask[i]); + + wire [CTR_WIDTH-1:0] pending_instrs_n = pending_instrs[i] + CTR_WIDTH'(incr_cnt[i]) - CTR_WIDTH'(decr_cnt[i]); + + always @(posedge clk) begin + if (reset) begin + incr_cnt[i] <= '0; + decr_cnt[i] <= '0; + pending_instrs[i] <= '0; + alm_empty_r[i] <= 0; + empty_r[i] <= 1; + end else begin + incr_cnt[i] <= incr_cnt_n[i]; + decr_cnt[i] <= decr_cnt_n; + pending_instrs[i] <= pending_instrs_n; + alm_empty_r[i] <= (pending_instrs_n == ALM_EMPTY); + empty_r[i] <= (pending_instrs_n == 0); + end + end + end + + assign alm_empty = alm_empty_r[alm_empty_wid]; + assign empty = (& empty_r); + +endmodule diff --git a/hw/rtl/core/VX_schedule.sv b/hw/rtl/core/VX_schedule.sv new file mode 100644 index 00000000..ea96178e --- /dev/null +++ b/hw/rtl/core/VX_schedule.sv @@ -0,0 +1,379 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_schedule import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // configuration + input base_dcrs_t base_dcrs, + + // inputsdecode_if + VX_warp_ctl_if.slave warp_ctl_if, + VX_branch_ctl_if.slave branch_ctl_if [`NUM_ALU_BLOCKS], + VX_decode_sched_if.slave decode_sched_if, + VX_commit_sched_if.slave commit_sched_if, + + // outputs + VX_schedule_if.master schedule_if, +`ifdef GBAR_ENABLE + VX_gbar_bus_if.master gbar_bus_if, +`endif + VX_sched_csr_if.master sched_csr_if, + + // status + output wire busy +); + `UNUSED_PARAM (CORE_ID) + + reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // updated when a warp is activated or disabled + reg [`NUM_WARPS-1:0] stalled_warps, stalled_warps_n; // set when branch/gpgpu instructions are issued + + reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks, thread_masks_n; + reg [`NUM_WARPS-1:0][`XLEN-1:0] warp_pcs, warp_pcs_n; + + wire [`NW_WIDTH-1:0] schedule_wid; + wire [`NUM_THREADS-1:0] schedule_tmask; + wire [`XLEN-1:0] schedule_pc; + wire schedule_valid; + wire schedule_ready; + + // split/join + wire join_valid; + wire join_is_dvg; + wire join_is_else; + wire [`NW_WIDTH-1:0] join_wid; + wire [`NUM_THREADS-1:0] join_tmask; + wire [`XLEN-1:0] join_pc; + + reg [`PERF_CTR_BITS-1:0] cycles; + + reg [`NUM_WARPS-1:0][`UUID_WIDTH-1:0] issued_instrs; + + wire schedule_fire = schedule_valid && schedule_ready; + wire schedule_if_fire = schedule_if.valid && schedule_if.ready; + + // branch + wire [`NUM_ALU_BLOCKS-1:0] branch_valid; + wire [`NUM_ALU_BLOCKS-1:0][`NW_WIDTH-1:0] branch_wid; + wire [`NUM_ALU_BLOCKS-1:0] branch_taken; + wire [`NUM_ALU_BLOCKS-1:0][`XLEN-1:0] branch_dest; + for (genvar i = 0; i < `NUM_ALU_BLOCKS; ++i) begin + assign branch_valid[i] = branch_ctl_if[i].valid; + assign branch_wid[i] = branch_ctl_if[i].wid; + assign branch_taken[i] = branch_ctl_if[i].taken; + assign branch_dest[i] = branch_ctl_if[i].dest; + end + + // barriers + reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks, barrier_masks_n; + reg [`NUM_WARPS-1:0] barrier_stalls, barrier_stalls_n; + wire [`CLOG2(`NUM_WARPS+1)-1:0] active_barrier_count; + wire [`NUM_WARPS-1:0] curr_barrier_mask; +`ifdef GBAR_ENABLE + reg [`NUM_WARPS-1:0] curr_barrier_mask_n; + reg gbar_req_valid; + reg [`NB_WIDTH-1:0] gbar_req_id; + reg [`NC_WIDTH-1:0] gbar_req_size_m1; +`endif + + assign curr_barrier_mask = barrier_masks[warp_ctl_if.barrier.id]; + `POP_COUNT(active_barrier_count, curr_barrier_mask); + `UNUSED_VAR (active_barrier_count) + + always @(*) begin + active_warps_n = active_warps; + stalled_warps_n = stalled_warps; + thread_masks_n = thread_masks; + barrier_masks_n = barrier_masks; + barrier_stalls_n= barrier_stalls; + warp_pcs_n = warp_pcs; + + // wspawn handling + if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin + active_warps_n |= warp_ctl_if.wspawn.wmask; + for (integer i = 0; i < `NUM_WARPS; ++i) begin + if (warp_ctl_if.wspawn.wmask[i]) begin + thread_masks_n[i][0] = 1; + warp_pcs_n[i] = warp_ctl_if.wspawn.pc; + end + end + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end + + // TMC handling + if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin + active_warps_n[warp_ctl_if.wid] = (warp_ctl_if.tmc.tmask != 0); + thread_masks_n[warp_ctl_if.wid] = warp_ctl_if.tmc.tmask; + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end + + // split handling + if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin + if (warp_ctl_if.split.is_dvg) begin + thread_masks_n[warp_ctl_if.wid] = warp_ctl_if.split.then_tmask; + end + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end + + // join handling + if (join_valid) begin + if (join_is_dvg) begin + if (join_is_else) begin + warp_pcs_n[join_wid] = join_pc; + end + thread_masks_n[join_wid] = join_tmask; + end + stalled_warps_n[join_wid] = 0; // unlock warp + end + + // barrier handling + `ifdef GBAR_ENABLE + curr_barrier_mask_n = curr_barrier_mask; + curr_barrier_mask_n[warp_ctl_if.wid] = 1; + `endif + if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin + if (~warp_ctl_if.barrier.is_global + && (active_barrier_count[`NW_WIDTH-1:0] == warp_ctl_if.barrier.size_m1[`NW_WIDTH-1:0])) begin + barrier_masks_n[warp_ctl_if.barrier.id] = '0; + barrier_stalls_n &= ~barrier_masks[warp_ctl_if.barrier.id]; + end else begin + barrier_masks_n[warp_ctl_if.barrier.id][warp_ctl_if.wid] = 1; + barrier_stalls_n[warp_ctl_if.wid] = 1; + end + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end + `ifdef GBAR_ENABLE + if (gbar_bus_if.rsp_valid && (gbar_req_id == gbar_bus_if.rsp_id)) begin + barrier_masks_n[gbar_bus_if.rsp_id] = '0; + barrier_stalls_n = '0; // unlock all warps + end + `endif + + // Branch handling + for (integer i = 0; i < `NUM_ALU_BLOCKS; ++i) begin + if (branch_valid[i]) begin + if (branch_taken[i]) begin + warp_pcs_n[branch_wid[i]] = branch_dest[i]; + end + stalled_warps_n[branch_wid[i]] = 0; // unlock warp + end + end + + // decode unlock + if (decode_sched_if.valid && ~decode_sched_if.is_wstall) begin + stalled_warps_n[decode_sched_if.wid] = 0; + end + + // CSR unlock + if (sched_csr_if.unlock_warp) begin + stalled_warps_n[sched_csr_if.unlock_wid] = 0; + end + + // stall the warp until decode stage + if (schedule_fire) begin + stalled_warps_n[schedule_wid] = 1; + end + + // advance PC + if (schedule_if_fire) begin + warp_pcs_n[schedule_if.data.wid] = schedule_if.data.PC + 4; + end + end + + `UNUSED_VAR (base_dcrs) + + always @(posedge clk) begin + if (reset) begin + barrier_masks <= '0; + `ifdef GBAR_ENABLE + gbar_req_valid <= 0; + `endif + stalled_warps <= '0; + warp_pcs <= '0; + active_warps <= '0; + thread_masks <= '0; + barrier_stalls <= '0; + issued_instrs <= '0; + cycles <= '0; + + // activate first warp + warp_pcs[0] <= base_dcrs.startup_addr; + active_warps[0] <= 1; + thread_masks[0][0] <= 1; + end else begin + active_warps <= active_warps_n; + stalled_warps <= stalled_warps_n; + thread_masks <= thread_masks_n; + warp_pcs <= warp_pcs_n; + barrier_masks <= barrier_masks_n; + barrier_stalls <= barrier_stalls_n; + + // global barrier scheduling + `ifdef GBAR_ENABLE + if (warp_ctl_if.valid && warp_ctl_if.barrier.valid + && warp_ctl_if.barrier.is_global + && (curr_barrier_mask_n == active_warps)) begin + gbar_req_valid <= 1; + gbar_req_id <= warp_ctl_if.barrier.id; + gbar_req_size_m1 <= warp_ctl_if.barrier.size_m1[`NC_WIDTH-1:0]; + end + if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin + gbar_req_valid <= 0; + end + `endif + + if (schedule_if_fire) begin + issued_instrs[schedule_if.data.wid] <= issued_instrs[schedule_if.data.wid] + `UUID_WIDTH'(1); + end + + if (busy) begin + cycles <= cycles + 1; + end + end + end + + // barrier handling + +`ifdef GBAR_ENABLE + assign gbar_bus_if.req_valid = gbar_req_valid; + assign gbar_bus_if.req_id = gbar_req_id; + assign gbar_bus_if.req_size_m1 = gbar_req_size_m1; + assign gbar_bus_if.req_core_id = `NC_WIDTH'(CORE_ID % `NUM_CORES); +`endif + + // split/join handling + + `RESET_RELAY (split_join_reset, reset); + + VX_split_join #( + .CORE_ID (CORE_ID) + ) split_join ( + .clk (clk), + .reset (split_join_reset), + .valid (warp_ctl_if.valid), + .wid (warp_ctl_if.wid), + .split (warp_ctl_if.split), + .sjoin (warp_ctl_if.sjoin), + .join_valid (join_valid), + .join_is_dvg (join_is_dvg), + .join_is_else (join_is_else), + .join_wid (join_wid), + .join_tmask (join_tmask), + .join_pc (join_pc) + ); + + // schedule the next ready warp + + wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls); + + VX_lzc #( + .N (`NUM_WARPS), + .REVERSE (1) + ) wid_select ( + .data_in (ready_warps), + .data_out (schedule_wid), + .valid_out (schedule_valid) + ); + + wire [`NUM_WARPS-1:0][(`NUM_THREADS + `XLEN)-1:0] schedule_data; + for (genvar i = 0; i < `NUM_WARPS; ++i) begin + assign schedule_data[i] = {thread_masks[i], warp_pcs[i]}; + end + + assign {schedule_tmask, schedule_pc} = { + schedule_data[schedule_wid][(`NUM_THREADS + `XLEN)-1:(`NUM_THREADS + `XLEN)-4], + schedule_data[schedule_wid][(`NUM_THREADS + `XLEN)-5:0] + }; + +`ifndef NDEBUG + localparam GNW_WIDTH = `LOG2UP(`NUM_CLUSTERS * `NUM_CORES * `NUM_WARPS); + reg [`UUID_WIDTH-1:0] instr_uuid; + wire [GNW_WIDTH-1:0] g_wid = (GNW_WIDTH'(CORE_ID) << `NW_BITS) + GNW_WIDTH'(schedule_wid); + always @(posedge clk) begin + if (reset) begin + instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(1, 0, 0)); + end else if (schedule_fire) begin + instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(0, 32'(g_wid), 64'(schedule_pc))); + end + end +`else + wire [`UUID_WIDTH-1:0] instr_uuid = '0; +`endif + + VX_elastic_buffer #( + .DATAW (`NUM_THREADS + `XLEN + `NW_WIDTH) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (schedule_valid), + .ready_in (schedule_ready), + .data_in ({schedule_tmask, schedule_pc, schedule_wid}), + .data_out ({schedule_if.data.tmask, schedule_if.data.PC, schedule_if.data.wid}), + .valid_out (schedule_if.valid), + .ready_out (schedule_if.ready) + ); + + assign schedule_if.data.uuid = instr_uuid; + + `RESET_RELAY (pending_instr_reset, reset); + + wire no_pending_instr; + VX_pending_instr #( + .CTR_WIDTH (12), + .DECR_COUNT (`ISSUE_WIDTH), + .ALM_EMPTY (1) + ) pending_instr( + .clk (clk), + .reset (pending_instr_reset), + .incr (schedule_if_fire), + .incr_wid (schedule_if.data.wid), + .decr (commit_sched_if.committed), + .decr_wid (commit_sched_if.committed_wid), + .alm_empty_wid (sched_csr_if.alm_empty_wid), + .alm_empty (sched_csr_if.alm_empty), + .empty (no_pending_instr) + ); + + `BUFFER_BUSY (busy, (active_warps != 0 || ~no_pending_instr), 1); + + // export CSRs + assign sched_csr_if.cycles = cycles; + assign sched_csr_if.active_warps = active_warps; + assign sched_csr_if.thread_masks = thread_masks; + + // timeout handling + reg [31:0] timeout_ctr; + reg timeout_enable; + always @(posedge clk) begin + if (reset) begin + timeout_ctr <= '0; + timeout_enable <= 0; + end else begin + if (decode_sched_if.valid && ~decode_sched_if.is_wstall) begin + timeout_enable <= 1; + end + if (timeout_enable && active_warps !=0 && active_warps == stalled_warps) begin + timeout_ctr <= timeout_ctr + 1; + end else if (active_warps == 0 || active_warps != stalled_warps) begin + timeout_ctr <= '0; + end + end + end + `RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** core%0d-scheduler-timeout: stalled_warps=%b", $time, CORE_ID, stalled_warps)); + +endmodule diff --git a/hw/rtl/core/VX_scoreboard.sv b/hw/rtl/core/VX_scoreboard.sv new file mode 100644 index 00000000..ee5ae2ec --- /dev/null +++ b/hw/rtl/core/VX_scoreboard.sv @@ -0,0 +1,139 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_scoreboard import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + VX_writeback_if.slave writeback_if [`ISSUE_WIDTH], + VX_ibuffer_if.slave ibuffer_if [`ISSUE_WIDTH], + VX_ibuffer_if.master scoreboard_if [`ISSUE_WIDTH] +); + `UNUSED_PARAM (CORE_ID) + localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4) + 1; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin + reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; + reg [3:0] ready_masks, ready_masks_n; + VX_ibuffer_if staging_if(); + + wire writeback_fire = writeback_if[i].valid && writeback_if[i].data.eop; + + always @(*) begin + inuse_regs_n = inuse_regs; + ready_masks_n = ready_masks; + if (writeback_fire) begin + inuse_regs_n[writeback_if[i].data.wis][writeback_if[i].data.rd] = 0; + ready_masks_n |= {4{(ISSUE_RATIO == 0) || writeback_if[i].data.wis == staging_if.data.wis}} + & {(writeback_if[i].data.rd == staging_if.data.rd), + (writeback_if[i].data.rd == staging_if.data.rs1), + (writeback_if[i].data.rd == staging_if.data.rs2), + (writeback_if[i].data.rd == staging_if.data.rs3)}; + end + if (staging_if.valid && staging_if.ready && staging_if.data.wb) begin + inuse_regs_n[staging_if.data.wis][staging_if.data.rd] = 1; + ready_masks_n = '0; + end + if (ibuffer_if[i].valid && ibuffer_if[i].ready) begin + ready_masks_n = ~{inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd], + inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1], + inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2], + inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3]}; + end + end + + always @(posedge clk) begin + if (reset) begin + inuse_regs <= '0; + ready_masks <= '0; + end else begin + inuse_regs <= inuse_regs_n; + ready_masks <= ready_masks_n; + end + end + + // staging buffer + + `RESET_RELAY (stg_buf_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW) + ) stg_buf ( + .clk (clk), + .reset (stg_buf_reset), + .valid_in (ibuffer_if[i].valid), + .ready_in (ibuffer_if[i].ready), + .data_in (ibuffer_if[i].data), + .data_out (staging_if.data), + .valid_out (staging_if.valid), + .ready_out (staging_if.ready) + ); + + // output buffer + + wire valid_stg, ready_stg; + wire regs_ready = (& ready_masks); + assign valid_stg = staging_if.valid && regs_ready; + assign staging_if.ready = ready_stg && regs_ready; + + `RESET_RELAY (out_buf_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2), + .OUT_REG (2) + ) out_buf ( + .clk (clk), + .reset (out_buf_reset), + .valid_in (valid_stg), + .ready_in (ready_stg), + .data_in (staging_if.data), + .data_out (scoreboard_if[i].data), + .valid_out (scoreboard_if[i].valid), + .ready_out (scoreboard_if[i].ready) + ); + + reg [31:0] timeout_ctr; + + always @(posedge clk) begin + if (reset) begin + timeout_ctr <= '0; + end else begin + if (staging_if.valid && ~regs_ready) begin + `ifdef DBG_TRACE_CORE_PIPELINE + `TRACE(3, ("%d: *** core%0d-scoreboard-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n", + $time, CORE_ID, wis_to_wid(staging_if.data.wis, i), staging_if.data.PC, staging_if.data.tmask, timeout_ctr, + ~ready_masks, staging_if.data.uuid)); + `endif + timeout_ctr <= timeout_ctr + 1; + end else if (staging_if.valid && staging_if.ready) begin + timeout_ctr <= '0; + end + end + end + + `RUNTIME_ASSERT((timeout_ctr < `STALL_TIMEOUT), + ("%t: *** core%0d-scoreboard-timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)", + $time, CORE_ID, wis_to_wid(staging_if.data.wis, i), staging_if.data.PC, staging_if.data.tmask, timeout_ctr, + ~ready_masks, staging_if.data.uuid)); + + `RUNTIME_ASSERT(~writeback_fire || inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] != 0, + ("%t: *** core%0d: invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)", + $time, CORE_ID, wis_to_wid(writeback_if[i].data.wis, i), writeback_if[i].data.PC, writeback_if[i].data.tmask, writeback_if[i].data.rd, writeback_if[i].data.uuid)); + end + +endmodule diff --git a/hw/rtl/core/VX_sfu_unit.sv b/hw/rtl/core/VX_sfu_unit.sv new file mode 100644 index 00000000..e94f86fd --- /dev/null +++ b/hw/rtl/core/VX_sfu_unit.sv @@ -0,0 +1,209 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_sfu_unit import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + VX_mem_perf_if.slave mem_perf_if, + VX_pipeline_perf_if.slave pipeline_perf_if, +`endif + + input base_dcrs_t base_dcrs, + + // Inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + +`ifdef EXT_F_ENABLE + VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS], +`endif + + // Outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH], + VX_commit_csr_if.slave commit_csr_if, + VX_sched_csr_if.slave sched_csr_if, + VX_warp_ctl_if.master warp_ctl_if +); + `UNUSED_PARAM (CORE_ID) + localparam BLOCK_SIZE = 1; + localparam NUM_LANES = `NUM_SFU_LANES; + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + + localparam RSP_ARB_DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + (NUM_LANES * `XLEN) + `NR_BITS + 1 + `XLEN + PID_WIDTH + 1 + 1; + localparam RSP_ARB_SIZE = 1 + 1; + localparam RSP_ARB_IDX_WCTL = 0; + localparam RSP_ARB_IDX_CSR = 1; + + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) execute_if[BLOCK_SIZE](); + + `RESET_RELAY (dispatch_reset, reset); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (1) + ) dispatch_unit ( + .clk (clk), + .reset (dispatch_reset), + .dispatch_if(dispatch_if), + .execute_if (execute_if) + ); + + wire [RSP_ARB_SIZE-1:0] rsp_arb_valid_in; + wire [RSP_ARB_SIZE-1:0] rsp_arb_ready_in; + wire [RSP_ARB_SIZE-1:0][RSP_ARB_DATAW-1:0] rsp_arb_data_in; + +`ifdef PERF_ENABLE + VX_sfu_perf_if sfu_perf_if(); +`endif + + // Warp control block + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) wctl_execute_if(); + VX_commit_if#( + .NUM_LANES (NUM_LANES) + ) wctl_commit_if(); + + assign wctl_execute_if.valid = execute_if[0].valid && `INST_SFU_IS_WCTL(execute_if[0].data.op_type); + assign wctl_execute_if.data = execute_if[0].data; + + `RESET_RELAY (wctl_reset, reset); + + VX_wctl_unit #( + .CORE_ID (CORE_ID), + .NUM_LANES (NUM_LANES) + ) wctl_unit ( + .clk (clk), + .reset (wctl_reset), + .execute_if (wctl_execute_if), + .warp_ctl_if(warp_ctl_if), + .commit_if (wctl_commit_if) + ); + + assign rsp_arb_valid_in[RSP_ARB_IDX_WCTL] = wctl_commit_if.valid; + assign rsp_arb_data_in[RSP_ARB_IDX_WCTL] = wctl_commit_if.data; + assign wctl_commit_if.ready = rsp_arb_ready_in[RSP_ARB_IDX_WCTL]; + + // CSR unit + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) csr_execute_if(); + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) csr_commit_if(); + + assign csr_execute_if.valid = execute_if[0].valid && `INST_SFU_IS_CSR(execute_if[0].data.op_type); + assign csr_execute_if.data = execute_if[0].data; + + `RESET_RELAY (csr_reset, reset); + + VX_csr_unit #( + .CORE_ID (CORE_ID), + .NUM_LANES (NUM_LANES) + ) csr_unit ( + .clk (clk), + .reset (csr_reset), + + .base_dcrs (base_dcrs), + .execute_if (csr_execute_if), + + `ifdef PERF_ENABLE + .mem_perf_if (mem_perf_if), + .pipeline_perf_if(pipeline_perf_if), + .sfu_perf_if (sfu_perf_if), + `endif + + `ifdef EXT_F_ENABLE + .fpu_to_csr_if (fpu_to_csr_if), + `endif + + .sched_csr_if (sched_csr_if), + .commit_csr_if (commit_csr_if), + .commit_if (csr_commit_if) + ); + + assign rsp_arb_valid_in[RSP_ARB_IDX_CSR] = csr_commit_if.valid; + assign rsp_arb_data_in[RSP_ARB_IDX_CSR] = csr_commit_if.data; + assign csr_commit_if.ready = rsp_arb_ready_in[RSP_ARB_IDX_CSR]; + + // can accept new request? + + reg sfu_req_ready; + always @(*) begin + case (execute_if[0].data.op_type) + `INST_SFU_CSRRW, + `INST_SFU_CSRRS, + `INST_SFU_CSRRC: sfu_req_ready = csr_execute_if.ready; + default: sfu_req_ready = wctl_execute_if.ready; + endcase + end + assign execute_if[0].ready = sfu_req_ready; + + // response arbitration + + `RESET_RELAY (commit_reset, reset); + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) arb_commit_if[BLOCK_SIZE](); + + VX_stream_arb #( + .NUM_INPUTS (RSP_ARB_SIZE), + .DATAW (RSP_ARB_DATAW), + .ARBITER ("R"), + .OUT_REG (1) + ) rsp_arb ( + .clk (clk), + .reset (commit_reset), + .valid_in (rsp_arb_valid_in), + .ready_in (rsp_arb_ready_in), + .data_in (rsp_arb_data_in), + .data_out (arb_commit_if[0].data), + .valid_out (arb_commit_if[0].valid), + .ready_out (arb_commit_if[0].ready), + `UNUSED_PIN (sel_out) + ); + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (3) + ) gather_unit ( + .clk (clk), + .reset (commit_reset), + .commit_in_if (arb_commit_if), + .commit_out_if (commit_if) + ); + +`ifdef PERF_ENABLE + reg [`PERF_CTR_BITS-1:0] perf_wctl_stalls; + always @(posedge clk) begin + if (reset) begin + perf_wctl_stalls <= '0; + end else begin + perf_wctl_stalls <= perf_wctl_stalls + `PERF_CTR_BITS'(wctl_execute_if.valid && ~wctl_execute_if.ready); + end + end + assign sfu_perf_if.wctl_stalls = perf_wctl_stalls; +`endif + +endmodule diff --git a/hw/rtl/core/VX_smem_unit.sv b/hw/rtl/core/VX_smem_unit.sv new file mode 100644 index 00000000..82eb126a --- /dev/null +++ b/hw/rtl/core/VX_smem_unit.sv @@ -0,0 +1,185 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_smem_unit import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + VX_mem_perf_if.slave mem_perf_in_if, + VX_mem_perf_if.master mem_perf_out_if, +`endif + + VX_mem_bus_if.slave dcache_bus_in_if [DCACHE_NUM_REQS], + VX_mem_bus_if.master dcache_bus_out_if [DCACHE_NUM_REQS] +); + `UNUSED_PARAM (CORE_ID) + +`ifdef SM_ENABLE + localparam SMEM_ADDR_WIDTH = `SMEM_LOG_SIZE - `CLOG2(DCACHE_WORD_SIZE); + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH) + ) switch_out_bus_if[2 * DCACHE_NUM_REQS](); + +`ifdef PERF_ENABLE + VX_cache_perf_if perf_smem_if(); +`endif + + `RESET_RELAY (switch_reset, reset); + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + VX_smem_switch #( + .NUM_REQS (2), + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH), + .TAG_SEL_IDX (0), + .ARBITER ("P"), + .OUT_REG_REQ (2), + .OUT_REG_RSP (2) + ) smem_switch ( + .clk (clk), + .reset (switch_reset), + .bus_in_if (dcache_bus_in_if[i]), + .bus_out_if (switch_out_bus_if[i * 2 +: 2]) + ); + end + + // this bus goes to the dcache + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + `ASSIGN_VX_MEM_BUS_IF (dcache_bus_out_if[i], switch_out_bus_if[i * 2]); + end + + wire [DCACHE_NUM_REQS-1:0] smem_req_valid; + wire [DCACHE_NUM_REQS-1:0] smem_req_rw; + wire [DCACHE_NUM_REQS-1:0][SMEM_ADDR_WIDTH-1:0] smem_req_addr; + wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] smem_req_byteen; + wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] smem_req_data; + wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] smem_req_tag; + wire [DCACHE_NUM_REQS-1:0] smem_req_ready; + wire [DCACHE_NUM_REQS-1:0] smem_rsp_valid; + wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] smem_rsp_data; + wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] smem_rsp_tag; + wire [DCACHE_NUM_REQS-1:0] smem_rsp_ready; + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + + assign smem_req_valid[i] = switch_out_bus_if[i * 2 + 1].req_valid; + assign smem_req_rw[i] = switch_out_bus_if[i * 2 + 1].req_data.rw; + assign smem_req_byteen[i] = switch_out_bus_if[i * 2 + 1].req_data.byteen; + assign smem_req_data[i] = switch_out_bus_if[i * 2 + 1].req_data.data; + assign smem_req_tag[i] = switch_out_bus_if[i * 2 + 1].req_data.tag; + assign switch_out_bus_if[i * 2 + 1].req_ready = smem_req_ready[i]; + + assign switch_out_bus_if[i * 2 + 1].rsp_valid = smem_rsp_valid[i]; + assign switch_out_bus_if[i * 2 + 1].rsp_data.data = smem_rsp_data[i]; + assign switch_out_bus_if[i * 2 + 1].rsp_data.tag = smem_rsp_tag[i]; + assign smem_rsp_ready[i] = switch_out_bus_if[i * 2 + 1].rsp_ready; + + assign smem_req_addr[i] = switch_out_bus_if[i * 2 + 1].req_data.addr[SMEM_ADDR_WIDTH-1:0]; + end + + `RESET_RELAY (smem_reset, reset); + + VX_shared_mem #( + .INSTANCE_ID($sformatf("core%0d-smem", CORE_ID)), + .SIZE (1 << `SMEM_LOG_SIZE), + .NUM_REQS (DCACHE_NUM_REQS), + .NUM_BANKS (`SMEM_NUM_BANKS), + .WORD_SIZE (DCACHE_WORD_SIZE), + .ADDR_WIDTH (SMEM_ADDR_WIDTH), + .UUID_WIDTH (`UUID_WIDTH), + .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH) + ) shared_mem ( + .clk (clk), + .reset (smem_reset), + + `ifdef PERF_ENABLE + .cache_perf_if(perf_smem_if), + `endif + + // Core request + .req_valid (smem_req_valid), + .req_rw (smem_req_rw), + .req_byteen (smem_req_byteen), + .req_addr (smem_req_addr), + .req_data (smem_req_data), + .req_tag (smem_req_tag), + .req_ready (smem_req_ready), + + // Core response + .rsp_valid (smem_rsp_valid), + .rsp_data (smem_rsp_data), + .rsp_tag (smem_rsp_tag), + .rsp_ready (smem_rsp_ready) + ); + +`else + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + `ASSIGN_VX_MEM_BUS_IF (dcache_bus_out_if[i], dcache_bus_in_if[i]); + end + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + +`endif + +`ifdef PERF_ENABLE + + assign mem_perf_out_if.icache_reads = mem_perf_in_if.icache_reads; + assign mem_perf_out_if.icache_read_misses = mem_perf_in_if.icache_read_misses; + + assign mem_perf_out_if.dcache_reads = mem_perf_in_if.dcache_reads; + assign mem_perf_out_if.dcache_writes = mem_perf_in_if.dcache_writes; + assign mem_perf_out_if.dcache_read_misses = mem_perf_in_if.dcache_read_misses; + assign mem_perf_out_if.dcache_write_misses = mem_perf_in_if.dcache_write_misses; + assign mem_perf_out_if.dcache_bank_stalls = mem_perf_in_if.dcache_bank_stalls; + assign mem_perf_out_if.dcache_mshr_stalls = mem_perf_in_if.dcache_mshr_stalls; + + assign mem_perf_out_if.l2cache_reads = mem_perf_in_if.l2cache_reads; + assign mem_perf_out_if.l2cache_writes = mem_perf_in_if.l2cache_writes; + assign mem_perf_out_if.l2cache_read_misses = mem_perf_in_if.l2cache_read_misses; + assign mem_perf_out_if.l2cache_write_misses = mem_perf_in_if.l2cache_write_misses; + assign mem_perf_out_if.l2cache_bank_stalls = mem_perf_in_if.l2cache_bank_stalls; + assign mem_perf_out_if.l2cache_mshr_stalls = mem_perf_in_if.l2cache_mshr_stalls; + + assign mem_perf_out_if.l3cache_reads = mem_perf_in_if.l3cache_reads; + assign mem_perf_out_if.l3cache_writes = mem_perf_in_if.l3cache_writes; + assign mem_perf_out_if.l3cache_read_misses = mem_perf_in_if.l3cache_read_misses; + assign mem_perf_out_if.l3cache_write_misses = mem_perf_in_if.l3cache_write_misses; + assign mem_perf_out_if.l3cache_bank_stalls = mem_perf_in_if.l3cache_bank_stalls; + assign mem_perf_out_if.l3cache_mshr_stalls = mem_perf_in_if.l3cache_mshr_stalls; + + assign mem_perf_out_if.mem_reads = mem_perf_in_if.mem_reads; + assign mem_perf_out_if.mem_writes = mem_perf_in_if.mem_writes; + assign mem_perf_out_if.mem_latency = mem_perf_in_if.mem_latency; + +`ifdef SM_ENABLE + assign mem_perf_out_if.smem_reads = perf_smem_if.reads; + assign mem_perf_out_if.smem_writes = perf_smem_if.writes; + assign mem_perf_out_if.smem_bank_stalls = perf_smem_if.bank_stalls; +`else + assign mem_perf_out_if.smem_reads = '0; + assign mem_perf_out_if.smem_writes = '0; + assign mem_perf_out_if.smem_bank_stalls = '0; +`endif + +`endif + +endmodule diff --git a/hw/rtl/core/VX_split_join.sv b/hw/rtl/core/VX_split_join.sv new file mode 100644 index 00000000..e4f3fd43 --- /dev/null +++ b/hw/rtl/core/VX_split_join.sv @@ -0,0 +1,76 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_split_join import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [`NW_WIDTH-1:0] wid, + input split_t split, + input join_t sjoin, + output wire join_valid, + output wire join_is_dvg, + output wire join_is_else, + output wire [`NW_WIDTH-1:0] join_wid, + output wire [`NUM_THREADS-1:0] join_tmask, + output wire [`XLEN-1:0] join_pc +); + `UNUSED_PARAM (CORE_ID) + + wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_data [`NUM_WARPS-1:0]; + wire ipdom_set [`NUM_WARPS-1:0]; + + wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_q0 = {split.then_tmask | split.else_tmask, `XLEN'(0)}; + wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_q1 = {split.else_tmask, split.next_pc}; + + wire ipdom_push = valid && split.valid && split.is_dvg; + wire ipdom_pop = valid && sjoin.valid && sjoin.is_dvg; + + for (genvar i = 0; i < `NUM_WARPS; ++i) begin + + `RESET_RELAY (ipdom_reset, reset); + + VX_ipdom_stack #( + .WIDTH (`XLEN+`NUM_THREADS), + .DEPTH (`UP(`NUM_THREADS-1)) + ) ipdom_stack ( + .clk (clk), + .reset (ipdom_reset), + .push (ipdom_push && (i == wid)), + .pop (ipdom_pop && (i == wid)), + .q0 (ipdom_q0), + .q1 (ipdom_q1), + .d (ipdom_data[i]), + .d_set (ipdom_set[i]), + `UNUSED_PIN (empty), + `UNUSED_PIN (full) + ); + end + + VX_pipe_register #( + .DATAW (1 + 1 + `NW_WIDTH + 1 + `XLEN + `NUM_THREADS), + .DEPTH (1), + .RESETW (1) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({valid && sjoin.valid, sjoin.is_dvg, ipdom_set[wid], wid, ipdom_data[wid]}), + .data_out ({join_valid, join_is_dvg, join_is_else, join_wid, join_tmask, join_pc}) + ); + +endmodule diff --git a/hw/rtl/core/VX_trace.vh b/hw/rtl/core/VX_trace.vh new file mode 100644 index 00000000..bf0f8012 --- /dev/null +++ b/hw/rtl/core/VX_trace.vh @@ -0,0 +1,378 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_TRACE_VH +`define VX_TRACE_VH + +`include "VX_define.vh" + +task trace_ex_type(input int level, input [`EX_BITS-1:0] ex_type); + case (ex_type) + `EX_ALU: `TRACE(level, ("ALU")); + `EX_LSU: `TRACE(level, ("LSU")); + `EX_FPU: `TRACE(level, ("FPU")); + `EX_SFU: `TRACE(level, ("SFU")); + default: `TRACE(level, ("?")); + endcase +endtask + +task trace_ex_op(input int level, + input [`EX_BITS-1:0] ex_type, + input [`INST_OP_BITS-1:0] op_type, + input [`INST_MOD_BITS-1:0] op_mod, + `UNUSED_ARG(input [`NR_BITS-1:0] rd), + `UNUSED_ARG(input [`NR_BITS-1:0] rs2), + input use_imm, + `UNUSED_ARG(input [`XLEN-1:0] imm) +); + +`ifdef FLEN_64 + logic fdst_d = imm[0]; +`else + logic fdst_d = 0; +`endif + +`ifdef XLEN_64 + logic fcvt_l = imm[1]; +`else + logic fcvt_l = 0; +`endif + +`ifdef EXT_F_ENABLE + logic rd_float = 1'(rd >> 5) || 1'(rs2 >> 5); +`else + logic rd_float = 0; +`endif + + case (ex_type) + `EX_ALU: begin + if (`INST_ALU_IS_BR(op_mod)) begin + case (`INST_BR_BITS'(op_type)) + `INST_BR_EQ: `TRACE(level, ("BEQ")); + `INST_BR_NE: `TRACE(level, ("BNE")); + `INST_BR_LT: `TRACE(level, ("BLT")); + `INST_BR_GE: `TRACE(level, ("BGE")); + `INST_BR_LTU: `TRACE(level, ("BLTU")); + `INST_BR_GEU: `TRACE(level, ("BGEU")); + `INST_BR_JAL: `TRACE(level, ("JAL")); + `INST_BR_JALR: `TRACE(level, ("JALR")); + `INST_BR_ECALL: `TRACE(level, ("ECALL")); + `INST_BR_EBREAK:`TRACE(level, ("EBREAK")); + `INST_BR_URET: `TRACE(level, ("URET")); + `INST_BR_SRET: `TRACE(level, ("SRET")); + `INST_BR_MRET: `TRACE(level, ("MRET")); + default: `TRACE(level, ("?")); + endcase + end else if (`INST_ALU_IS_M(op_mod)) begin + if (`INST_ALU_IS_W(op_mod)) begin + case (`INST_M_BITS'(op_type)) + `INST_M_MUL: `TRACE(level, ("MULW")); + `INST_M_DIV: `TRACE(level, ("DIVW")); + `INST_M_DIVU: `TRACE(level, ("DIVUW")); + `INST_M_REM: `TRACE(level, ("REMW")); + `INST_M_REMU: `TRACE(level, ("REMUW")); + default: `TRACE(level, ("?")); + endcase + end else begin + case (`INST_M_BITS'(op_type)) + `INST_M_MUL: `TRACE(level, ("MUL")); + `INST_M_MULH: `TRACE(level, ("MULH")); + `INST_M_MULHSU:`TRACE(level, ("MULHSU")); + `INST_M_MULHU: `TRACE(level, ("MULHU")); + `INST_M_DIV: `TRACE(level, ("DIV")); + `INST_M_DIVU: `TRACE(level, ("DIVU")); + `INST_M_REM: `TRACE(level, ("REM")); + `INST_M_REMU: `TRACE(level, ("REMU")); + default: `TRACE(level, ("?")); + endcase + end + end else begin + if (`INST_ALU_IS_W(op_mod)) begin + if (use_imm) begin + case (`INST_ALU_BITS'(op_type)) + `INST_ALU_ADD: `TRACE(level, ("ADDIW")); + `INST_ALU_SLL: `TRACE(level, ("SLLIW")); + `INST_ALU_SRL: `TRACE(level, ("SRLIW")); + `INST_ALU_SRA: `TRACE(level, ("SRAIW")); + default: `TRACE(level, ("?")); + endcase + end else begin + case (`INST_ALU_BITS'(op_type)) + `INST_ALU_ADD: `TRACE(level, ("ADDW")); + `INST_ALU_SUB: `TRACE(level, ("SUBW")); + `INST_ALU_SLL: `TRACE(level, ("SLLW")); + `INST_ALU_SRL: `TRACE(level, ("SRLW")); + `INST_ALU_SRA: `TRACE(level, ("SRAW")); + default: `TRACE(level, ("?")); + endcase + end + end else begin + if (use_imm) begin + case (`INST_ALU_BITS'(op_type)) + `INST_ALU_ADD: `TRACE(level, ("ADDI")); + `INST_ALU_SLL: `TRACE(level, ("SLLI")); + `INST_ALU_SRL: `TRACE(level, ("SRLI")); + `INST_ALU_SRA: `TRACE(level, ("SRAI")); + `INST_ALU_SLT: `TRACE(level, ("SLTI")); + `INST_ALU_SLTU: `TRACE(level, ("SLTIU")); + `INST_ALU_XOR: `TRACE(level, ("XORI")); + `INST_ALU_OR: `TRACE(level, ("ORI")); + `INST_ALU_AND: `TRACE(level, ("ANDI")); + `INST_ALU_LUI: `TRACE(level, ("LUI")); + `INST_ALU_AUIPC: `TRACE(level, ("AUIPC")); + default: `TRACE(level, ("?")); + endcase + end else begin + case (`INST_ALU_BITS'(op_type)) + `INST_ALU_ADD: `TRACE(level, ("ADD")); + `INST_ALU_SUB: `TRACE(level, ("SUB")); + `INST_ALU_SLL: `TRACE(level, ("SLL")); + `INST_ALU_SRL: `TRACE(level, ("SRL")); + `INST_ALU_SRA: `TRACE(level, ("SRA")); + `INST_ALU_SLT: `TRACE(level, ("SLT")); + `INST_ALU_SLTU: `TRACE(level, ("SLTU")); + `INST_ALU_XOR: `TRACE(level, ("XOR")); + `INST_ALU_OR: `TRACE(level, ("OR")); + `INST_ALU_AND: `TRACE(level, ("AND")); + default: `TRACE(level, ("?")); + endcase + end + end + end + end + `EX_LSU: begin + if (rd_float) begin + case (`INST_LSU_BITS'(op_type)) + `INST_LSU_LW: `TRACE(level, ("FLW")); + `INST_LSU_LD: `TRACE(level, ("FLD")); + `INST_LSU_SW: `TRACE(level, ("FSW")); + `INST_LSU_SD: `TRACE(level, ("FSD")); + default: `TRACE(level, ("?")); + endcase + end else begin + case (`INST_LSU_BITS'(op_type)) + `INST_LSU_LB: `TRACE(level, ("LB")); + `INST_LSU_LH: `TRACE(level, ("LH")); + `INST_LSU_LW: `TRACE(level, ("LW")); + `INST_LSU_LD: `TRACE(level, ("LD")); + `INST_LSU_LBU:`TRACE(level, ("LBU")); + `INST_LSU_LHU:`TRACE(level, ("LHU")); + `INST_LSU_LWU:`TRACE(level, ("LWU")); + `INST_LSU_SB: `TRACE(level, ("SB")); + `INST_LSU_SH: `TRACE(level, ("SH")); + `INST_LSU_SW: `TRACE(level, ("SW")); + `INST_LSU_SD: `TRACE(level, ("SD")); + `INST_LSU_FENCE:`TRACE(level,("FENCE")); + default: `TRACE(level, ("?")); + endcase + end + end + `EX_FPU: begin + case (`INST_FPU_BITS'(op_type)) + `INST_FPU_ADD: begin + if (fdst_d) + `TRACE(level, ("FADD.D")); + else + `TRACE(level, ("FADD.S")); + end + `INST_FPU_SUB: begin + if (fdst_d) + `TRACE(level, ("FSUB.D")); + else + `TRACE(level, ("FSUB.S")); + end + `INST_FPU_MUL: begin + if (fdst_d) + `TRACE(level, ("FMUL.D")); + else + `TRACE(level, ("FMUL.S")); + end + `INST_FPU_DIV: begin + if (fdst_d) + `TRACE(level, ("FDIV.D")); + else + `TRACE(level, ("FDIV.S")); + end + `INST_FPU_SQRT: begin + if (fdst_d) + `TRACE(level, ("FSQRT.D")); + else + `TRACE(level, ("FSQRT.S")); + end + `INST_FPU_MADD: begin + if (fdst_d) + `TRACE(level, ("FMADD.D")); + else + `TRACE(level, ("FMADD.S")); + end + `INST_FPU_MSUB: begin + if (fdst_d) + `TRACE(level, ("FMSUB.D")); + else + `TRACE(level, ("FMSUB.S")); + end + `INST_FPU_NMADD: begin + if (fdst_d) + `TRACE(level, ("FNMADD.D")); + else + `TRACE(level, ("FNMADD.S")); + end + `INST_FPU_NMSUB: begin + if (fdst_d) + `TRACE(level, ("FNMSUB.D")); + else + `TRACE(level, ("FNMSUB.S")); + end + `INST_FPU_CMP: begin + if (fdst_d) begin + case (op_mod[1:0]) + 0: `TRACE(level, ("FLE.D")); + 1: `TRACE(level, ("FLT.D")); + 2: `TRACE(level, ("FEQ.D")); + default: `TRACE(level, ("?")); + endcase + end else begin + case (op_mod[1:0]) + 0: `TRACE(level, ("FLE.S")); + 1: `TRACE(level, ("FLT.S")); + 2: `TRACE(level, ("FEQ.S")); + default: `TRACE(level, ("?")); + endcase + end + end + `INST_FPU_F2F: begin + if (fdst_d) begin + `TRACE(level, ("FCVT.D.S")); + end else begin + `TRACE(level, ("FCVT.S.D")); + end + end + `INST_FPU_F2I: begin + if (fdst_d) begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.L.D")); + end else begin + `TRACE(level, ("FCVT.W.D")); + end + end else begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.L.S")); + end else begin + `TRACE(level, ("FCVT.W.S")); + end + end + end + `INST_FPU_F2U: begin + if (fdst_d) begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.LU.D")); + end else begin + `TRACE(level, ("FCVT.WU.D")); + end + end else begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.LU.S")); + end else begin + `TRACE(level, ("FCVT.WU.S")); + end + end + end + `INST_FPU_I2F: begin + if (fdst_d) begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.D.L")); + end else begin + `TRACE(level, ("FCVT.D.W")); + end + end else begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.S.L")); + end else begin + `TRACE(level, ("FCVT.S.W")); + end + end + end + `INST_FPU_U2F: begin + if (fdst_d) begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.D.LU")); + end else begin + `TRACE(level, ("FCVT.D.WU")); + end + end else begin + if (fcvt_l) begin + `TRACE(level, ("FCVT.S.LU")); + end else begin + `TRACE(level, ("FCVT.S.WU")); + end + end + end + `INST_FPU_MISC: begin + if (fdst_d) begin + case (op_mod) + 0: `TRACE(level, ("FSGNJ.D")); + 1: `TRACE(level, ("FSGNJN.D")); + 2: `TRACE(level, ("FSGNJX.D")); + 3: `TRACE(level, ("FCLASS.D")); + 4: `TRACE(level, ("FMV.X.D")); + 5: `TRACE(level, ("FMV.D.X")); + 6: `TRACE(level, ("FMIN.D")); + 7: `TRACE(level, ("FMAX.D")); + endcase + end else begin + case (op_mod) + 0: `TRACE(level, ("FSGNJ.S")); + 1: `TRACE(level, ("FSGNJN.S")); + 2: `TRACE(level, ("FSGNJX.S")); + 3: `TRACE(level, ("FCLASS.S")); + 4: `TRACE(level, ("FMV.X.S")); + 5: `TRACE(level, ("FMV.S.X")); + 6: `TRACE(level, ("FMIN.S")); + 7: `TRACE(level, ("FMAX.S")); + endcase + end + end + default: `TRACE(level, ("?")); + endcase + end + `EX_SFU: begin + case (`INST_SFU_BITS'(op_type)) + `INST_SFU_TMC: `TRACE(level, ("TMC")); + `INST_SFU_WSPAWN:`TRACE(level, ("WSPAWN")); + `INST_SFU_SPLIT: `TRACE(level, ("SPLIT")); + `INST_SFU_JOIN: `TRACE(level, ("JOIN")); + `INST_SFU_BAR: `TRACE(level, ("BAR")); + `INST_SFU_PRED: `TRACE(level, ("PRED")); + `INST_SFU_CSRRW: begin if (use_imm) `TRACE(level, ("CSRRWI")); else `TRACE(level, ("CSRRW")); end + `INST_SFU_CSRRS: begin if (use_imm) `TRACE(level, ("CSRRSI")); else `TRACE(level, ("CSRRS")); end + `INST_SFU_CSRRC: begin if (use_imm) `TRACE(level, ("CSRRCI")); else `TRACE(level, ("CSRRC")); end + `INST_SFU_TEX: `TRACE(level, ("TEX")); + `INST_SFU_RASTER:`TRACE(level, ("RASTER")); + `INST_SFU_ROP: `TRACE(level, ("ROP")); + default: `TRACE(level, ("?")); + endcase + end + default: `TRACE(level, ("?")); + endcase +endtask + +task trace_base_dcr(input int level, input [`VX_DCR_ADDR_WIDTH-1:0] addr); + case (addr) + `VX_DCR_BASE_STARTUP_ADDR0: `TRACE(level, ("STARTUP_ADDR0")); + `VX_DCR_BASE_STARTUP_ADDR1: `TRACE(level, ("STARTUP_ADDR1")); + `VX_DCR_BASE_MPM_CLASS: `TRACE(level, ("MPM_CLASS")); + default: `TRACE(level, ("?")); + endcase +endtask + +`endif // VX_TRACE_VH diff --git a/hw/rtl/core/VX_wctl_unit.sv b/hw/rtl/core/VX_wctl_unit.sv new file mode 100644 index 00000000..d628e16c --- /dev/null +++ b/hw/rtl/core/VX_wctl_unit.sv @@ -0,0 +1,157 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_wctl_unit import VX_gpu_pkg::*; #( + parameter CORE_ID = 0, + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_warp_ctl_if.master warp_ctl_if, + VX_commit_if.master commit_if +); + `UNUSED_PARAM (CORE_ID) + localparam LANE_BITS = `CLOG2(NUM_LANES); + localparam LANE_WIDTH = `UP(LANE_BITS); + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam WCTL_WIDTH = $bits(tmc_t) + $bits(wspawn_t) + $bits(split_t) + $bits(join_t) + $bits(barrier_t); + localparam DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + WCTL_WIDTH + PID_WIDTH + 1 + 1; + + `UNUSED_VAR (execute_if.data.rs3_data) + + tmc_t tmc, tmc_r; + wspawn_t wspawn, wspawn_r; + split_t split, split_r; + join_t sjoin, sjoin_r; + barrier_t barrier, barrier_r; + + wire is_wspawn = (execute_if.data.op_type == `INST_SFU_WSPAWN); + wire is_tmc = (execute_if.data.op_type == `INST_SFU_TMC); + wire is_pred = (execute_if.data.op_type == `INST_SFU_PRED); + wire is_split = (execute_if.data.op_type == `INST_SFU_SPLIT); + wire is_join = (execute_if.data.op_type == `INST_SFU_JOIN); + wire is_bar = (execute_if.data.op_type == `INST_SFU_BAR); + + wire [LANE_WIDTH-1:0] tid; + if (LANE_BITS != 0) begin + assign tid = execute_if.data.tid[0 +: LANE_BITS]; + end else begin + assign tid = 0; + end + + wire [`XLEN-1:0] rs1_data = execute_if.data.rs1_data[tid]; + wire [`XLEN-1:0] rs2_data = execute_if.data.rs2_data[tid]; + `UNUSED_VAR (rs1_data) + + wire [NUM_LANES-1:0] taken; + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign taken[i] = execute_if.data.rs1_data[i][0]; + end + + reg [`NUM_THREADS-1:0] then_tmask_r, then_tmask_n; + reg [`NUM_THREADS-1:0] else_tmask_r, else_tmask_n; + always @(*) begin + then_tmask_n = then_tmask_r; + else_tmask_n = else_tmask_r; + if (execute_if.data.sop) begin + then_tmask_n = '0; + else_tmask_n = '0; + end + then_tmask_n[execute_if.data.pid * NUM_LANES +: NUM_LANES] = taken & execute_if.data.tmask; + else_tmask_n[execute_if.data.pid * NUM_LANES +: NUM_LANES] = ~taken & execute_if.data.tmask; + end + always @(posedge clk) begin + if (execute_if.valid) begin + then_tmask_r <= then_tmask_n; + else_tmask_r <= else_tmask_n; + end + end + wire has_then = (then_tmask_n != 0); + wire has_else = (else_tmask_n != 0); + + // tmc / pred + + wire [`NUM_THREADS-1:0] pred_mask = has_then ? then_tmask_n : rs2_data[`NUM_THREADS-1:0]; + assign tmc.valid = (is_tmc || is_pred); + assign tmc.tmask = is_pred ? pred_mask : rs1_data[`NUM_THREADS-1:0]; + + // split + + assign split.valid = is_split; + assign split.is_dvg = has_then && has_else; + assign split.then_tmask = then_tmask_n; + assign split.else_tmask = else_tmask_n; + assign split.next_pc = execute_if.data.PC + 4; + + // join + + assign sjoin.valid = is_join; + assign sjoin.is_dvg = rs1_data[0]; + + // barrier + assign barrier.valid = is_bar; + assign barrier.id = rs1_data[`NB_WIDTH-1:0]; +`ifdef GBAR_ENABLE + assign barrier.is_global = rs1_data[31]; +`else + assign barrier.is_global = 1'b0; +`endif + assign barrier.size_m1 = rs2_data[$bits(barrier.size_m1)-1:0] - $bits(barrier.size_m1)'(1); + + // wspawn + + wire [`NUM_WARPS-1:0] wspawn_wmask; + for (genvar i = 0; i < `NUM_WARPS; ++i) begin + assign wspawn_wmask[i] = (i < rs1_data[`NW_BITS:0]) && (i != execute_if.data.wid); + end + assign wspawn.valid = is_wspawn; + assign wspawn.wmask = wspawn_wmask; + assign wspawn.pc = rs2_data; + + // response + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (execute_if.valid), + .ready_in (execute_if.ready), + .data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, {tmc, wspawn, split, sjoin, barrier}}), + .data_out ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.PC, commit_if.data.rd, commit_if.data.wb, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop, {tmc_r, wspawn_r, split_r, sjoin_r, barrier_r}}), + .valid_out (commit_if.valid), + .ready_out (commit_if.ready) + ); + + assign warp_ctl_if.valid = commit_if.valid && commit_if.ready && commit_if.data.eop; + assign warp_ctl_if.wid = commit_if.data.wid; + assign warp_ctl_if.tmc = tmc_r; + assign warp_ctl_if.wspawn = wspawn_r; + assign warp_ctl_if.split = split_r; + assign warp_ctl_if.sjoin = sjoin_r; + assign warp_ctl_if.barrier = barrier_r; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign commit_if.data.data[i] = `XLEN'(split_r.is_dvg); + end + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_cvt.sv b/hw/rtl/fp_cores/VX_fp_cvt.sv deleted file mode 100644 index 733713c1..00000000 --- a/hw/rtl/fp_cores/VX_fp_cvt.sv +++ /dev/null @@ -1,445 +0,0 @@ -`include "VX_fpu_define.vh" - -/// Modified port of cast module from fpnew Libray -/// reference: https://github.com/pulp-platform/fpnew - -module VX_fp_cvt #( - parameter TAGW = 1, - parameter LANES = 1 -) ( - input wire clk, - input wire reset, - - output wire ready_in, - input wire valid_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FRM_BITS-1:0] frm, - - input wire is_itof, - input wire is_signed, - - input wire [LANES-1:0][31:0] dataa, - output wire [LANES-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [LANES-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - // Constants - - localparam MAN_BITS = 23; - localparam EXP_BITS = 8; - localparam EXP_BIAS = 2**(EXP_BITS-1)-1; - - // Use 32-bit integer - localparam MAX_INT_WIDTH = 32; - - // The internal mantissa includes normal bit or an entire integer - localparam INT_MAN_WIDTH = `MAX(MAN_BITS + 1, MAX_INT_WIDTH); - - // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection - localparam LZC_RESULT_WIDTH = $clog2(INT_MAN_WIDTH); - - // The internal exponent must be able to represent the smallest denormal input value as signed - // or the number of bits in an integer - localparam INT_EXP_WIDTH = `MAX($clog2(MAX_INT_WIDTH), `MAX(EXP_BITS, $clog2(EXP_BIAS + MAN_BITS))) + 1; - - // shift amount for denormalization - localparam SHAMT_BITS = $clog2(INT_MAN_WIDTH+1); - - localparam FMT_SHIFT_COMPENSATION = INT_MAN_WIDTH - 1 - MAN_BITS; - localparam NUM_FP_STICKY = 2 * INT_MAN_WIDTH - MAN_BITS - 1; // removed mantissa, 1. and R - localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - MAX_INT_WIDTH; // removed int and R - - // Input processing - - fp_class_t [LANES-1:0] fp_clss; - - for (genvar i = 0; i < LANES; ++i) begin - VX_fp_class #( - .EXP_BITS (EXP_BITS), - .MAN_BITS (MAN_BITS) - ) fp_class ( - .exp_i (dataa[i][30:23]), - .man_i (dataa[i][22:0]), - .clss_o (fp_clss[i]) - ); - end - - wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant; // input mantissa with implicit bit - wire [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent; - wire [LANES-1:0] input_sign; - - for (genvar i = 0; i < LANES; ++i) begin - `IGNORE_WARNINGS_BEGIN - wire [INT_MAN_WIDTH-1:0] int_mantissa; - wire [INT_MAN_WIDTH-1:0] fmt_mantissa; - wire fmt_sign = dataa[i][31]; - wire int_sign = dataa[i][31] & is_signed; - assign int_mantissa = int_sign ? (-dataa[i]) : dataa[i]; - assign fmt_mantissa = INT_MAN_WIDTH'({fp_clss[i].is_normal, dataa[i][MAN_BITS-1:0]}); - assign fmt_exponent[i] = {1'b0, dataa[i][MAN_BITS +: EXP_BITS]} + - {1'b0, fp_clss[i].is_subnormal}; - assign encoded_mant[i] = is_itof ? int_mantissa : fmt_mantissa; - assign input_sign[i] = is_itof ? int_sign : fmt_sign; - `IGNORE_WARNINGS_END - end - - // Pipeline stage0 - - wire valid_in_s0; - wire [TAGW-1:0] tag_in_s0; - wire is_itof_s0; - wire unsigned_s0; - wire [2:0] rnd_mode_s0; - fp_class_t [LANES-1:0] fp_clss_s0; - wire [LANES-1:0] input_sign_s0; - wire [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0; - wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0; - - wire stall; - - VX_pipe_register #( - .DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_class_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)), - .RESETW (1) - ) pipe_reg0 ( - .clk (clk), - .reset (reset), - .enable (~stall), - .data_in ({valid_in, tag_in, is_itof, !is_signed, frm, fp_clss, input_sign, fmt_exponent, encoded_mant}), - .data_out ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fp_clss_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0}) - ); - - // Normalization - - wire [LANES-1:0][LZC_RESULT_WIDTH-1:0] renorm_shamt_s0; // renormalization shift amount - wire [LANES-1:0] mant_is_zero_s0; // for integer zeroes - - for (genvar i = 0; i < LANES; ++i) begin - wire mant_is_nonzero; - VX_lzc #( - .N (INT_MAN_WIDTH), - .MODE (1) - ) lzc ( - .in_i (encoded_mant_s0[i]), - .cnt_o (renorm_shamt_s0[i]), - .valid_o (mant_is_nonzero) - ); - assign mant_is_zero_s0[i] = ~mant_is_nonzero; - end - - wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s0; // normalized input mantissa - wire [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s0; // unbiased true exponent - - for (genvar i = 0; i < LANES; ++i) begin - `IGNORE_WARNINGS_BEGIN - // Realign input mantissa, append zeroes if destination is wider - assign input_mant_s0[i] = encoded_mant_s0[i] << renorm_shamt_s0[i]; - - // Unbias exponent and compensate for shift - wire [INT_EXP_WIDTH-1:0] fp_input_exp = fmt_exponent_s0[i] + (FMT_SHIFT_COMPENSATION - EXP_BIAS) - {1'b0, renorm_shamt_s0[i]}; - wire [INT_EXP_WIDTH-1:0] int_input_exp = (INT_MAN_WIDTH-1) - {1'b0, renorm_shamt_s0[i]}; - - assign input_exp_s0[i] = is_itof_s0 ? int_input_exp : fp_input_exp; - `IGNORE_WARNINGS_END - end - - // Pipeline stage1 - - wire valid_in_s1; - wire [TAGW-1:0] tag_in_s1; - wire is_itof_s1; - wire unsigned_s1; - wire [2:0] rnd_mode_s1; - fp_class_t [LANES-1:0] fp_clss_s1; - wire [LANES-1:0] input_sign_s1; - wire [LANES-1:0] mant_is_zero_s1; - wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1; - wire [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1; - - VX_pipe_register #( - .DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + LANES * ($bits(fp_class_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)), - .RESETW (1) - ) pipe_reg1 ( - .clk (clk), - .reset (reset), - .enable (~stall), - .data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fp_clss_s0, input_sign_s0, mant_is_zero_s0, input_mant_s0, input_exp_s0}), - .data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fp_clss_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1}) - ); - - // Perform adjustments to mantissa and exponent - - wire [LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s1; - wire [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s1; - wire [LANES-1:0] of_before_round_s1; - - for (genvar i = 0; i < LANES; ++i) begin - reg [2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift - reg [SHAMT_BITS-1:0] denorm_shamt; // shift amount for denormalization - reg [INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments - reg of_before_round; - - always @(*) begin - `IGNORE_WARNINGS_BEGIN - // Default assignment - final_exp = input_exp_s1[i] + EXP_BIAS; // take exponent as is, only look at lower bits - preshift_mant = {input_mant_s1[i], 33'b0}; // Place mantissa to the left of the shifter - denorm_shamt = 0; // right of mantissa - of_before_round = 1'b0; - - // Handle INT casts - if (is_itof_s1) begin - if ($signed(input_exp_s1[i]) >= $signed(2**EXP_BITS-1-EXP_BIAS)) begin - // Overflow or infinities (for proper rounding) - final_exp = (2**EXP_BITS-2); // largest normal value - preshift_mant = ~0; // largest normal value and RS bits set - of_before_round = 1'b1; - end else if ($signed(input_exp_s1[i]) < $signed(-MAN_BITS-EXP_BIAS)) begin - // Limit the shift to retain sticky bits - final_exp = 0; // denormal result - denorm_shamt = (2 + MAN_BITS); // to sticky - end else if ($signed(input_exp_s1[i]) < $signed(1-EXP_BIAS)) begin - // Denormalize underflowing values - final_exp = 0; // denormal result - denorm_shamt = (1-EXP_BIAS) - input_exp_s1[i]; // adjust right shifting - end - end else begin - if ($signed(input_exp_s1[i]) >= $signed((MAX_INT_WIDTH-1) + unsigned_s1)) begin - // overflow: when converting to unsigned the range is larger by one - denorm_shamt = SHAMT_BITS'(0); // prevent shifting - of_before_round = 1'b1; - end else if ($signed(input_exp_s1[i]) < $signed(-1)) begin - // underflow - denorm_shamt = MAX_INT_WIDTH+1; // all bits go to the sticky - end else begin - // By default right shift mantissa to be an integer - denorm_shamt = (MAX_INT_WIDTH-1) - input_exp_s1[i]; - end - end - `IGNORE_WARNINGS_END - end - - assign destination_mant_s1[i] = preshift_mant >> denorm_shamt; - assign final_exp_s1[i] = final_exp; - assign of_before_round_s1[i] = of_before_round; - end - - // Pipeline stage2 - - wire valid_in_s2; - wire [TAGW-1:0] tag_in_s2; - wire is_itof_s2; - wire unsigned_s2; - wire [2:0] rnd_mode_s2; - fp_class_t [LANES-1:0] fp_clss_s2; - wire [LANES-1:0] mant_is_zero_s2; - wire [LANES-1:0] input_sign_s2; - wire [LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s2; - wire [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s2; - wire [LANES-1:0] of_before_round_s2; - - VX_pipe_register #( - .DATAW (1 + TAGW + 1 + 1 + `INST_FRM_BITS + LANES * ($bits(fp_class_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)), - .RESETW (1) - ) pipe_reg2 ( - .clk (clk), - .reset (reset), - .enable (~stall), - .data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fp_clss_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}), - .data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, rnd_mode_s2, fp_clss_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2}) - ); - - wire [LANES-1:0] rounded_sign; - wire [LANES-1:0][31:0] rounded_abs; // absolute value of result after rounding - wire [LANES-1:0][1:0] fp_round_sticky_bits, int_round_sticky_bits; - - // Rouding and classification - - for (genvar i = 0; i < LANES; ++i) begin - wire [MAN_BITS-1:0] final_mant; // mantissa after adjustments - wire [MAX_INT_WIDTH-1:0] final_int; // integer shifted in position - wire [1:0] round_sticky_bits; - wire [31:0] fmt_pre_round_abs; - wire [31:0] pre_round_abs; - - // Extract final mantissa and round bit, discard the normal bit (for FP) - assign {final_mant, fp_round_sticky_bits[i][1]} = destination_mant_s2[i][2*INT_MAN_WIDTH-1 : 2*INT_MAN_WIDTH-1 - (MAN_BITS+1) + 1]; - assign {final_int, int_round_sticky_bits[i][1]} = destination_mant_s2[i][2*INT_MAN_WIDTH : 2*INT_MAN_WIDTH - (MAX_INT_WIDTH+1) + 1]; - - // Collapse sticky bits - assign fp_round_sticky_bits[i][0] = (| destination_mant_s2[i][NUM_FP_STICKY-1:0]); - assign int_round_sticky_bits[i][0] = (| destination_mant_s2[i][NUM_INT_STICKY-1:0]); - - // select RS bits for destination operation - assign round_sticky_bits = is_itof_s2 ? fp_round_sticky_bits[i] : int_round_sticky_bits[i]; - - // Pack exponent and mantissa into proper rounding form - assign fmt_pre_round_abs = {1'b0, final_exp_s2[i][EXP_BITS-1:0], final_mant[MAN_BITS-1:0]}; - - // Select output with destination format and operation - assign pre_round_abs = is_itof_s2 ? fmt_pre_round_abs : final_int; - - // Perform the rounding - VX_fp_rounding #( - .DAT_WIDTH (32) - ) fp_rounding ( - .abs_value_i (pre_round_abs), - .sign_i (input_sign_s2[i]), - .round_sticky_bits_i(round_sticky_bits), - .rnd_mode_i (rnd_mode_s2), - .effective_subtraction_i(1'b0), - .abs_rounded_o (rounded_abs[i]), - .sign_o (rounded_sign[i]), - `UNUSED_PIN (exact_zero_o) - ); - end - - // Pipeline stage3 - - wire valid_in_s3; - wire [TAGW-1:0] tag_in_s3; - wire is_itof_s3; - wire unsigned_s3; - fp_class_t [LANES-1:0] fp_clss_s3; - wire [LANES-1:0] mant_is_zero_s3; - wire [LANES-1:0] input_sign_s3; - wire [LANES-1:0] rounded_sign_s3; - wire [LANES-1:0][31:0] rounded_abs_s3; - wire [LANES-1:0] of_before_round_s3; - - VX_pipe_register #( - .DATAW (1 + TAGW + 1 + 1 + LANES * ($bits(fp_class_t) + 1 + 1 + 32 + 1 + 1)), - .RESETW (1) - ) pipe_reg3 ( - .clk (clk), - .reset (reset), - .enable (~stall), - .data_in ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, fp_clss_s2, mant_is_zero_s2, input_sign_s2, rounded_abs, rounded_sign, of_before_round_s2}), - .data_out ({valid_in_s3, tag_in_s3, is_itof_s3, unsigned_s3, fp_clss_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3}) - ); - - wire [LANES-1:0] of_after_round; - wire [LANES-1:0] uf_after_round; - wire [LANES-1:0][31:0] fmt_result; - wire [LANES-1:0][31:0] rounded_int_res; // after possible inversion - wire [LANES-1:0] rounded_int_res_zero; // after rounding - - for (genvar i = 0; i < LANES; ++i) begin - // Assemble regular result, nan box short ones. Int zeroes need to be detected - assign fmt_result[i] = (is_itof_s3 & mant_is_zero_s3[i]) ? 0 : {rounded_sign_s3[i], rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:0]}; - - // Classification after rounding select by destination format - assign uf_after_round[i] = (rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == 0); // denormal - assign of_after_round[i] = (rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == ~0); // inf exp. - - // Negative integer result needs to be brought into two's complement - assign rounded_int_res[i] = rounded_sign_s3[i] ? (-rounded_abs_s3[i]) : rounded_abs_s3[i]; - assign rounded_int_res_zero[i] = (rounded_int_res[i] == 0); - end - - // FP Special case handling - - wire [LANES-1:0][31:0] fp_special_result; - fflags_t [LANES-1:0] fp_special_status; - wire [LANES-1:0] fp_result_is_special; - - localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = 2**EXP_BITS-1; - localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1); - - for (genvar i = 0; i < LANES; ++i) begin - // Detect special case from source format, I2F casts don't produce a special result - assign fp_result_is_special[i] = ~is_itof_s3 & (fp_clss_s3[i].is_zero | fp_clss_s3[i].is_nan); - - // Signalling input NaNs raise invalid flag, otherwise no flags set - assign fp_special_status[i] = fp_clss_s3[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation - - // Assemble result according to destination format - assign fp_special_result[i] = fp_clss_s3[i].is_zero ? (32'(input_sign_s3) << 31) // signed zero - : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN - end - - // INT Special case handling - - reg [LANES-1:0][31:0] int_special_result; - fflags_t [LANES-1:0] int_special_status; - wire [LANES-1:0] int_result_is_special; - - for (genvar i = 0; i < LANES; ++i) begin - // Assemble result according to destination format - always @(*) begin - if (input_sign_s3[i] && !fp_clss_s3[i].is_nan) begin - int_special_result[i][30:0] = 0; // alone yields 2**(31)-1 - int_special_result[i][31] = ~unsigned_s3; // for unsigned casts yields 2**31 - end else begin - int_special_result[i][30:0] = 2**(31) - 1; // alone yields 2**(31)-1 - int_special_result[i][31] = unsigned_s3; // for unsigned casts yields 2**31 - end - end - - // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned) - assign int_result_is_special[i] = fp_clss_s3[i].is_nan - | fp_clss_s3[i].is_inf - | of_before_round_s3[i] - | (input_sign_s3[i] & unsigned_s3 & ~rounded_int_res_zero[i]); - - // All integer special cases are invalid - assign int_special_status[i] = {1'b1, 4'h0}; - end - - // Result selection and Output handshake - - fflags_t [LANES-1:0] tmp_fflags; - wire [LANES-1:0][31:0] tmp_result; - - for (genvar i = 0; i < LANES; ++i) begin - fflags_t fp_regular_status, int_regular_status; - fflags_t fp_status, int_status; - wire [31:0] fp_result, int_result; - - wire inexact = is_itof_s3 ? (| fp_round_sticky_bits[i]) // overflow is invalid in i2f; - : (| fp_round_sticky_bits[i]) | (~fp_clss_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); - - assign fp_regular_status.NV = is_itof_s3 & (of_before_round_s3[i] | of_after_round[i]); // overflow is invalid for I2F casts - assign fp_regular_status.DZ = 1'b0; // no divisions - assign fp_regular_status.OF = ~is_itof_s3 & (~fp_clss_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); // inf casts no OF - assign fp_regular_status.UF = uf_after_round[i] & inexact; - assign fp_regular_status.NX = inexact; - - assign int_regular_status = (| int_round_sticky_bits[i]) ? {4'h0, 1'b1} : 5'h0; - - assign fp_result = fp_result_is_special[i] ? fp_special_result[i] : fmt_result[i]; - assign int_result = int_result_is_special[i] ? int_special_result[i] : rounded_int_res[i]; - - assign fp_status = fp_result_is_special[i] ? fp_special_status[i] : fp_regular_status; - assign int_status = int_result_is_special[i] ? int_special_status[i] : int_regular_status; - - // Select output depending on special case detection - assign tmp_result[i] = is_itof_s3 ? fp_result : int_result; - assign tmp_fflags[i] = is_itof_s3 ? fp_status : int_status; - end - - assign stall = ~ready_out && valid_out; - - VX_pipe_register #( - .DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFLAGS_BITS)), - .RESETW (1) - ) pipe_reg4 ( - .clk (clk), - .reset (reset), - .enable (!stall), - .data_in ({valid_in_s3, tag_in_s3, tmp_result, tmp_fflags}), - .data_out ({valid_out, tag_out, result, fflags}) - ); - - assign ready_in = ~stall; - - assign has_fflags = 1'b1; - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_div.sv b/hw/rtl/fp_cores/VX_fp_div.sv deleted file mode 100644 index 48e9d9b8..00000000 --- a/hw/rtl/fp_cores/VX_fp_div.sv +++ /dev/null @@ -1,85 +0,0 @@ -`include "VX_fpu_define.vh" - -module VX_fp_div #( - parameter TAGW = 1, - parameter LANES = 1 -) ( - input wire clk, - input wire reset, - - output wire ready_in, - input wire valid_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FRM_BITS-1:0] frm, - - input wire [LANES-1:0][31:0] dataa, - input wire [LANES-1:0][31:0] datab, - output wire [LANES-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [LANES-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - wire stall = ~ready_out && valid_out; - wire enable = ~stall; - - for (genvar i = 0; i < LANES; i++) begin - `ifdef VERILATOR - reg [31:0] r; - fflags_t f; - - always @(*) begin - dpi_fdiv (enable && valid_in, dataa[i], datab[i], frm, r, f); - end - `UNUSED_VAR (f) - - VX_shift_register #( - .DATAW (32), - .DEPTH (`LATENCY_FDIV), - .RESETW (1) - ) shift_req_dpi ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in (r), - .data_out (result[i]) - ); - `else - `RESET_RELAY (fdiv_reset); - - acl_fdiv fdiv ( - .clk (clk), - .areset (fdiv_reset), - .en (enable), - .a (dataa[i]), - .b (datab[i]), - .q (result[i]) - ); - `endif - end - - VX_shift_register #( - .DATAW (1 + TAGW), - .DEPTH (`LATENCY_FDIV), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in ({valid_in, tag_in}), - .data_out ({valid_out, tag_out}) - ); - - assign ready_in = enable; - - `UNUSED_VAR (frm) - assign has_fflags = 0; - assign fflags = 0; - -endmodule diff --git a/hw/rtl/fp_cores/VX_fp_fma.sv b/hw/rtl/fp_cores/VX_fp_fma.sv deleted file mode 100644 index 8f826b5f..00000000 --- a/hw/rtl/fp_cores/VX_fp_fma.sv +++ /dev/null @@ -1,115 +0,0 @@ -`include "VX_fpu_define.vh" - -module VX_fp_fma #( - parameter TAGW = 1, - parameter LANES = 1 -) ( - input wire clk, - input wire reset, - - output wire ready_in, - input wire valid_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FRM_BITS-1:0] frm, - - input wire do_madd, - input wire do_sub, - input wire do_neg, - - input wire [LANES-1:0][31:0] dataa, - input wire [LANES-1:0][31:0] datab, - input wire [LANES-1:0][31:0] datac, - output wire [LANES-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [LANES-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - - wire stall = ~ready_out && valid_out; - wire enable = ~stall; - - for (genvar i = 0; i < LANES; i++) begin - reg [31:0] a, b, c; - - always @(*) begin - if (do_madd) begin - // MADD/MSUB/NMADD/NMSUB - a = do_neg ? {~dataa[i][31], dataa[i][30:0]} : dataa[i]; - b = datab[i]; - c = (do_neg ^ do_sub) ? {~datac[i][31], datac[i][30:0]} : datac[i]; - end else begin - if (do_neg) begin - // MUL - a = dataa[i]; - b = datab[i]; - c = 0; - end else begin - // ADD/SUB - a = 32'h3f800000; // 1.0f - b = dataa[i]; - c = do_sub ? {~datab[i][31], datab[i][30:0]} : datab[i]; - end - end - end - - `ifdef VERILATOR - reg [31:0] r; - fflags_t f; - - always @(*) begin - dpi_fmadd (enable && valid_in, a, b, c, frm, r, f); - end - `UNUSED_VAR (f) - - VX_shift_register #( - .DATAW (32), - .DEPTH (`LATENCY_FMA), - .RESETW (1) - ) shift_req_dpi ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in (r), - .data_out (result[i]) - ); - `else - `RESET_RELAY (fma_reset); - - acl_fmadd fmadd ( - .clk (clk), - .areset (fma_reset), - .en (enable), - .a (a), - .b (b), - .c (c), - .q (result[i]) - ); - `endif - end - - VX_shift_register #( - .DATAW (1 + TAGW), - .DEPTH (`LATENCY_FMA), - .RESETW (1) - ) shift_reg ( - .clk(clk), - .reset (reset), - .enable (enable), - .data_in ({valid_in, tag_in}), - .data_out ({valid_out, tag_out}) - ); - - assign ready_in = enable; - - `UNUSED_VAR (frm) - assign has_fflags = 0; - assign fflags = 0; - -endmodule diff --git a/hw/rtl/fp_cores/VX_fp_ncomp.sv b/hw/rtl/fp_cores/VX_fp_ncomp.sv deleted file mode 100644 index 17d42102..00000000 --- a/hw/rtl/fp_cores/VX_fp_ncomp.sv +++ /dev/null @@ -1,270 +0,0 @@ -`include "VX_fpu_define.vh" - -/// Modified port of noncomp module from fpnew Libray -/// reference: https://github.com/pulp-platform/fpnew - -module VX_fp_ncomp #( - parameter TAGW = 1, - parameter LANES = 1 -) ( - input wire clk, - input wire reset, - - output wire ready_in, - input wire valid_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FPU_BITS-1:0] op_type, - input wire [`INST_FRM_BITS-1:0] frm, - - input wire [LANES-1:0][31:0] dataa, - input wire [LANES-1:0][31:0] datab, - output wire [LANES-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [LANES-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - localparam EXP_BITS = 8; - localparam MAN_BITS = 23; - - localparam NEG_INF = 32'h00000001, - NEG_NORM = 32'h00000002, - NEG_SUBNORM = 32'h00000004, - NEG_ZERO = 32'h00000008, - POS_ZERO = 32'h00000010, - POS_SUBNORM = 32'h00000020, - POS_NORM = 32'h00000040, - POS_INF = 32'h00000080, - //SIG_NAN = 32'h00000100, - QUT_NAN = 32'h00000200; - - wire [LANES-1:0] a_sign, b_sign; - wire [LANES-1:0][7:0] a_exponent, b_exponent; - wire [LANES-1:0][22:0] a_mantissa, b_mantissa; - fp_class_t [LANES-1:0] a_clss, b_clss; - wire [LANES-1:0] a_smaller, ab_equal; - - // Setup - for (genvar i = 0; i < LANES; i++) begin - assign a_sign[i] = dataa[i][31]; - assign a_exponent[i] = dataa[i][30:23]; - assign a_mantissa[i] = dataa[i][22:0]; - - assign b_sign[i] = datab[i][31]; - assign b_exponent[i] = datab[i][30:23]; - assign b_mantissa[i] = datab[i][22:0]; - - VX_fp_class #( - .EXP_BITS (EXP_BITS), - .MAN_BITS (MAN_BITS) - ) fp_class_a ( - .exp_i (a_exponent[i]), - .man_i (a_mantissa[i]), - .clss_o (a_clss[i]) - ); - - VX_fp_class #( - .EXP_BITS (EXP_BITS), - .MAN_BITS (MAN_BITS) - ) fp_class_b ( - .exp_i (b_exponent[i]), - .man_i (b_mantissa[i]), - .clss_o (b_clss[i]) - ); - - assign a_smaller[i] = $signed(dataa[i]) < $signed(datab[i]); - assign ab_equal[i] = (dataa[i] == datab[i]) | (a_clss[i].is_zero & b_clss[i].is_zero); - end - - // Pipeline stage0 - - wire valid_in_s0; - wire [TAGW-1:0] tag_in_s0; - wire [`INST_FPU_BITS-1:0] op_type_s0; - wire [`INST_FRM_BITS-1:0] frm_s0; - wire [LANES-1:0][31:0] dataa_s0, datab_s0; - wire [LANES-1:0] a_sign_s0, b_sign_s0; - wire [LANES-1:0][7:0] a_exponent_s0; - wire [LANES-1:0][22:0] a_mantissa_s0; - fp_class_t [LANES-1:0] a_clss_s0, b_clss_s0; - wire [LANES-1:0] a_smaller_s0, ab_equal_s0; - - wire stall; - - VX_pipe_register #( - .DATAW (1 + TAGW + `INST_FPU_BITS + `INST_FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_class_t) + 1 + 1)), - .RESETW (1), - .DEPTH (0) - ) pipe_reg0 ( - .clk (clk), - .reset (reset), - .enable (!stall), - .data_in ({valid_in, tag_in, op_type, frm, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_clss, b_clss, a_smaller, ab_equal}), - .data_out ({valid_in_s0, tag_in_s0, op_type_s0, frm_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_clss_s0, b_clss_s0, a_smaller_s0, ab_equal_s0}) - ); - - // FCLASS - reg [LANES-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg - for (genvar i = 0; i < LANES; i++) begin - always @(*) begin - if (a_clss_s0[i].is_normal) begin - fclass_mask[i] = a_sign_s0[i] ? NEG_NORM : POS_NORM; - end - else if (a_clss_s0[i].is_inf) begin - fclass_mask[i] = a_sign_s0[i] ? NEG_INF : POS_INF; - end - else if (a_clss_s0[i].is_zero) begin - fclass_mask[i] = a_sign_s0[i] ? NEG_ZERO : POS_ZERO; - end - else if (a_clss_s0[i].is_subnormal) begin - fclass_mask[i] = a_sign_s0[i] ? NEG_SUBNORM : POS_SUBNORM; - end - else if (a_clss_s0[i].is_nan) begin - fclass_mask[i] = {22'h0, a_clss_s0[i].is_quiet, a_clss_s0[i].is_signaling, 8'h0}; - end - else begin - fclass_mask[i] = QUT_NAN; - end - end - end - - // Min/Max - reg [LANES-1:0][31:0] fminmax_res; // result of fmin/fmax - for (genvar i = 0; i < LANES; i++) begin - always @(*) begin - if (a_clss_s0[i].is_nan && b_clss_s0[i].is_nan) - fminmax_res[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN - else if (a_clss_s0[i].is_nan) - fminmax_res[i] = datab_s0[i]; - else if (b_clss_s0[i].is_nan) - fminmax_res[i] = dataa_s0[i]; - else begin - case (frm_s0) // use LSB to distinguish MIN and MAX - 3: fminmax_res[i] = a_smaller_s0[i] ? dataa_s0[i] : datab_s0[i]; - 4: fminmax_res[i] = a_smaller_s0[i] ? datab_s0[i] : dataa_s0[i]; - default: fminmax_res[i] = 'x; // don't care value - endcase - end - end - end - - // Sign injection - reg [LANES-1:0][31:0] fsgnj_res; // result of sign injection - for (genvar i = 0; i < LANES; i++) begin - always @(*) begin - case (frm_s0) - 0: fsgnj_res[i] = { b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]}; - 1: fsgnj_res[i] = {~b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]}; - 2: fsgnj_res[i] = { a_sign_s0[i] ^ b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]}; - default: fsgnj_res[i] = 'x; // don't care value - endcase - end - end - - // Comparison - reg [LANES-1:0][31:0] fcmp_res; // result of comparison - fflags_t [LANES-1:0] fcmp_fflags; // comparison fflags - for (genvar i = 0; i < LANES; i++) begin - always @(*) begin - case (frm_s0) - `INST_FRM_RNE: begin // LE - fcmp_fflags[i] = 5'h0; - if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin - fcmp_res[i] = 32'h0; - fcmp_fflags[i].NV = 1'b1; - end else begin - fcmp_res[i] = {31'h0, (a_smaller_s0[i] | ab_equal_s0[i])}; - end - end - `INST_FRM_RTZ: begin // LS - fcmp_fflags[i] = 5'h0; - if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin - fcmp_res[i] = 32'h0; - fcmp_fflags[i].NV = 1'b1; - end else begin - fcmp_res[i] = {31'h0, (a_smaller_s0[i] & ~ab_equal_s0[i])}; - end - end - `INST_FRM_RDN: begin // EQ - fcmp_fflags[i] = 5'h0; - if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin - fcmp_res[i] = 32'h0; - fcmp_fflags[i].NV = a_clss_s0[i].is_signaling | b_clss_s0[i].is_signaling; - end else begin - fcmp_res[i] = {31'h0, ab_equal_s0[i]}; - end - end - default: begin - fcmp_res[i] = 'x; - fcmp_fflags[i] = 'x; - end - endcase - end - end - - // outputs - - reg [LANES-1:0][31:0] tmp_result; - fflags_t [LANES-1:0] tmp_fflags; - - for (genvar i = 0; i < LANES; i++) begin - always @(*) begin - case (op_type_s0) - `INST_FPU_CLASS: begin - tmp_result[i] = fclass_mask[i]; - tmp_fflags[i] = 'x; - end - `INST_FPU_CMP: begin - tmp_result[i] = fcmp_res[i]; - tmp_fflags[i] = fcmp_fflags[i]; - end - //`FPU_MISC: - default: begin - case (frm_s0) - 0,1,2: begin - tmp_result[i] = fsgnj_res[i]; - tmp_fflags[i] = 'x; - end - 3,4: begin - tmp_result[i] = fminmax_res[i]; - tmp_fflags[i] = 0; - tmp_fflags[i].NV = a_clss_s0[i].is_signaling | b_clss_s0[i].is_signaling; - end - //5,6,7: MOVE - default: begin - tmp_result[i] = dataa_s0[i]; - tmp_fflags[i] = 'x; - end - endcase - end - endcase - end - end - - wire has_fflags_s0 = ((op_type_s0 == `INST_FPU_MISC) - && (frm_s0 == 3 // MIN - || frm_s0 == 4)) // MAX - || (op_type_s0 == `INST_FPU_CMP); // CMP - - assign stall = ~ready_out && valid_out; - - VX_pipe_register #( - .DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFLAGS_BITS)), - .RESETW (1) - ) pipe_reg1 ( - .clk (clk), - .reset (reset), - .enable (!stall), - .data_in ({valid_in_s0, tag_in_s0, tmp_result, has_fflags_s0, tmp_fflags}), - .data_out ({valid_out, tag_out, result, has_fflags, fflags}) - ); - - assign ready_in = ~stall; - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.sv b/hw/rtl/fp_cores/VX_fp_sqrt.sv deleted file mode 100644 index 441b8d95..00000000 --- a/hw/rtl/fp_cores/VX_fp_sqrt.sv +++ /dev/null @@ -1,83 +0,0 @@ -`include "VX_fpu_define.vh" - -module VX_fp_sqrt #( - parameter TAGW = 1, - parameter LANES = 1 -) ( - input wire clk, - input wire reset, - - output wire ready_in, - input wire valid_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FRM_BITS-1:0] frm, - - input wire [LANES-1:0][31:0] dataa, - output wire [LANES-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [LANES-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - wire stall = ~ready_out && valid_out; - wire enable = ~stall; - - for (genvar i = 0; i < LANES; i++) begin - `ifdef VERILATOR - reg [31:0] r; - fflags_t f; - - always @(*) begin - dpi_fsqrt (enable && valid_in, dataa[i], frm, r, f); - end - `UNUSED_VAR (f) - - VX_shift_register #( - .DATAW (32), - .DEPTH (`LATENCY_FSQRT), - .RESETW (1) - ) shift_req_dpi ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in (r), - .data_out (result[i]) - ); - `else - `RESET_RELAY (fsqrt_reset); - - acl_fsqrt fsqrt ( - .clk (clk), - .areset (fsqrt_reset), - .en (enable), - .a (dataa[i]), - .q (result[i]) - ); - `endif - end - - VX_shift_register #( - .DATAW (1 + TAGW), - .DEPTH (`LATENCY_FSQRT), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in ({valid_in, tag_in}), - .data_out ({valid_out, tag_out}) - ); - - assign ready_in = enable; - - `UNUSED_VAR (frm) - assign has_fflags = 0; - assign fflags = 0; - -endmodule diff --git a/hw/rtl/fp_cores/VX_fpu_define.vh b/hw/rtl/fp_cores/VX_fpu_define.vh deleted file mode 100644 index d764e8e4..00000000 --- a/hw/rtl/fp_cores/VX_fpu_define.vh +++ /dev/null @@ -1,14 +0,0 @@ -`ifndef VX_FPU_DEFINE -`define VX_FPU_DEFINE - -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif - -`IGNORE_WARNINGS_BEGIN -import fpu_types::*; -`IGNORE_WARNINGS_END - -`endif \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_dpi.sv b/hw/rtl/fp_cores/VX_fpu_dpi.sv deleted file mode 100644 index ae9f8306..00000000 --- a/hw/rtl/fp_cores/VX_fpu_dpi.sv +++ /dev/null @@ -1,420 +0,0 @@ -`include "VX_fpu_define.vh" - -module VX_fpu_dpi #( - parameter TAGW = 1 -) ( - input wire clk, - input wire reset, - - input wire valid_in, - output wire ready_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FPU_BITS-1:0] op_type, - input wire [`INST_MOD_BITS-1:0] frm, - - input wire [`NUM_THREADS-1:0][31:0] dataa, - input wire [`NUM_THREADS-1:0][31:0] datab, - input wire [`NUM_THREADS-1:0][31:0] datac, - output wire [`NUM_THREADS-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [`NUM_THREADS-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - localparam FPU_FMA = 0; - localparam FPU_DIV = 1; - localparam FPU_SQRT = 2; - localparam FPU_CVT = 3; - localparam FPU_NCP = 4; - localparam NUM_FPC = 5; - localparam FPC_BITS = `LOG2UP(NUM_FPC); - - wire [NUM_FPC-1:0] per_core_ready_in; - wire [NUM_FPC-1:0][`NUM_THREADS-1:0][31:0] per_core_result; - wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out; - reg [NUM_FPC-1:0] per_core_ready_out; - wire [NUM_FPC-1:0] per_core_valid_out; - - wire [NUM_FPC-1:0] per_core_has_fflags; - fflags_t [NUM_FPC-1:0][`NUM_THREADS-1:0] per_core_fflags; - - reg [FPC_BITS-1:0] core_select; - - reg is_fadd, is_fsub, is_fmul, is_fmadd, is_fmsub, is_fnmadd, is_fnmsub; - reg is_itof, is_utof, is_ftoi, is_ftou; - reg is_fclss, is_flt, is_fle, is_feq, is_fmin, is_fmax, is_fsgnj, is_fsgnjn, is_fsgnjx; - - always @(*) begin - is_fadd = 0; - is_fsub = 0; - is_fmul = 0; - is_fmadd = 0; - is_fmsub = 0; - is_fnmadd = 0; - is_fnmsub = 0; - is_itof = 0; - is_utof = 0; - is_ftoi = 0; - is_ftou = 0; - is_fclss = 0; - is_flt = 0; - is_fle = 0; - is_feq = 0; - is_fmin = 0; - is_fmax = 0; - is_fsgnj = 0; - is_fsgnjn = 0; - is_fsgnjx = 0; - - case (op_type) - `INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end - `INST_FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end - `INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end - `INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end - `INST_FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end - `INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end - `INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end - `INST_FPU_DIV: begin core_select = FPU_DIV; end - `INST_FPU_SQRT: begin core_select = FPU_SQRT; end - `INST_FPU_CVTWS: begin core_select = FPU_CVT; is_ftoi = 1; end - `INST_FPU_CVTWUS:begin core_select = FPU_CVT; is_ftou = 1; end - `INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; end - `INST_FPU_CVTSWU:begin core_select = FPU_CVT; is_utof = 1; end - `INST_FPU_CLASS: begin core_select = FPU_NCP; is_fclss = 1; end - `INST_FPU_CMP: begin core_select = FPU_NCP; - is_fle = (frm == 0); - is_flt = (frm == 1); - is_feq = (frm == 2); - end - default: begin core_select = FPU_NCP; - is_fsgnj = (frm == 0); - is_fsgnjn = (frm == 1); - is_fsgnjx = (frm == 2); - is_fmin = (frm == 3); - is_fmax = (frm == 4); - end - endcase - end - - generate - begin : fma - - wire [`NUM_THREADS-1:0][31:0] result_fma; - wire [`NUM_THREADS-1:0][31:0] result_fadd; - wire [`NUM_THREADS-1:0][31:0] result_fsub; - wire [`NUM_THREADS-1:0][31:0] result_fmul; - wire [`NUM_THREADS-1:0][31:0] result_fmadd; - wire [`NUM_THREADS-1:0][31:0] result_fmsub; - wire [`NUM_THREADS-1:0][31:0] result_fnmadd; - wire [`NUM_THREADS-1:0][31:0] result_fnmsub; - - fflags_t [`NUM_THREADS-1:0] fflags_fma; - fflags_t [`NUM_THREADS-1:0] fflags_fadd; - fflags_t [`NUM_THREADS-1:0] fflags_fsub; - fflags_t [`NUM_THREADS-1:0] fflags_fmul; - fflags_t [`NUM_THREADS-1:0] fflags_fmadd; - fflags_t [`NUM_THREADS-1:0] fflags_fmsub; - fflags_t [`NUM_THREADS-1:0] fflags_fnmadd; - fflags_t [`NUM_THREADS-1:0] fflags_fnmsub; - - wire fma_valid = (valid_in && core_select == FPU_FMA); - wire fma_ready = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA]; - - wire fma_fire = fma_valid && fma_ready; - - always @(*) begin - for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fadd (fma_fire, dataa[i], datab[i], frm, result_fadd[i], fflags_fadd[i]); - dpi_fsub (fma_fire, dataa[i], datab[i], frm, result_fsub[i], fflags_fsub[i]); - dpi_fmul (fma_fire, dataa[i], datab[i], frm, result_fmul[i], fflags_fmul[i]); - dpi_fmadd (fma_fire, dataa[i], datab[i], datac[i], frm, result_fmadd[i], fflags_fmadd[i]); - dpi_fmsub (fma_fire, dataa[i], datab[i], datac[i], frm, result_fmsub[i], fflags_fmsub[i]); - dpi_fnmadd (fma_fire, dataa[i], datab[i], datac[i], frm, result_fnmadd[i], fflags_fnmadd[i]); - dpi_fnmsub (fma_fire, dataa[i], datab[i], datac[i], frm, result_fnmsub[i], fflags_fnmsub[i]); - end - end - - assign result_fma = is_fadd ? result_fadd : - is_fsub ? result_fsub : - is_fmul ? result_fmul : - is_fmadd ? result_fmadd : - is_fmsub ? result_fmsub : - is_fnmadd ? result_fnmadd : - is_fnmsub ? result_fnmsub : - 0; - - assign fflags_fma = is_fadd ? fflags_fadd : - is_fsub ? fflags_fsub : - is_fmul ? fflags_fmul : - is_fmadd ? fflags_fmadd : - is_fmsub ? fflags_fmsub : - is_fnmadd ? fflags_fnmadd : - is_fnmsub ? fflags_fnmsub : - 0; - - VX_shift_register #( - .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), - .DEPTH (`LATENCY_FMA), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (fma_ready), - .data_in ({fma_valid, tag_in, result_fma, fflags_fma}), - .data_out ({per_core_valid_out[FPU_FMA], per_core_tag_out[FPU_FMA], per_core_result[FPU_FMA], per_core_fflags[FPU_FMA]}) - ); - - assign per_core_has_fflags[FPU_FMA] = 1; - assign per_core_ready_in[FPU_FMA] = fma_ready; - - end - endgenerate - - generate - begin : fdiv - - wire [`NUM_THREADS-1:0][31:0] result_fdiv; - fflags_t [`NUM_THREADS-1:0] fflags_fdiv; - - wire fdiv_valid = (valid_in && core_select == FPU_DIV); - wire fdiv_ready = per_core_ready_out[FPU_DIV] || ~per_core_valid_out[FPU_DIV]; - - wire fdiv_fire = fdiv_valid && fdiv_ready; - - always @(*) begin - for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fdiv (fdiv_fire, dataa[i], datab[i], frm, result_fdiv[i], fflags_fdiv[i]); - end - end - - VX_shift_register #( - .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), - .DEPTH (`LATENCY_FDIV), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (fdiv_ready), - .data_in ({fdiv_valid, tag_in, result_fdiv, fflags_fdiv}), - .data_out ({per_core_valid_out[FPU_DIV], per_core_tag_out[FPU_DIV], per_core_result[FPU_DIV], per_core_fflags[FPU_DIV]}) - ); - - assign per_core_has_fflags[FPU_DIV] = 1; - assign per_core_ready_in[FPU_DIV] = fdiv_ready; - - end - endgenerate - - generate - begin : fsqrt - - wire [`NUM_THREADS-1:0][31:0] result_fsqrt; - fflags_t [`NUM_THREADS-1:0] fflags_fsqrt; - - wire fsqrt_valid = (valid_in && core_select == FPU_SQRT); - wire fsqrt_ready = per_core_ready_out[FPU_SQRT] || ~per_core_valid_out[FPU_SQRT]; - - wire fsqrt_fire = fsqrt_valid && fsqrt_ready; - - always @(*) begin - for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fsqrt (fsqrt_fire, dataa[i], frm, result_fsqrt[i], fflags_fsqrt[i]); - end - end - - VX_shift_register #( - .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), - .DEPTH (`LATENCY_FSQRT), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (fsqrt_ready), - .data_in ({fsqrt_valid, tag_in, result_fsqrt, fflags_fsqrt}), - .data_out ({per_core_valid_out[FPU_SQRT], per_core_tag_out[FPU_SQRT], per_core_result[FPU_SQRT], per_core_fflags[FPU_SQRT]}) - ); - - assign per_core_has_fflags[FPU_SQRT] = 1; - assign per_core_ready_in[FPU_SQRT] = fsqrt_ready; - - end - endgenerate - - generate - begin : fcvt - - wire [`NUM_THREADS-1:0][31:0] result_fcvt; - wire [`NUM_THREADS-1:0][31:0] result_itof; - wire [`NUM_THREADS-1:0][31:0] result_utof; - wire [`NUM_THREADS-1:0][31:0] result_ftoi; - wire [`NUM_THREADS-1:0][31:0] result_ftou; - - fflags_t [`NUM_THREADS-1:0] fflags_fcvt; - fflags_t [`NUM_THREADS-1:0] fflags_itof; - fflags_t [`NUM_THREADS-1:0] fflags_utof; - fflags_t [`NUM_THREADS-1:0] fflags_ftoi; - fflags_t [`NUM_THREADS-1:0] fflags_ftou; - - wire fcvt_valid = (valid_in && core_select == FPU_CVT); - wire fcvt_ready = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT]; - - wire fcvt_fire = fcvt_valid && fcvt_ready; - - always @(*) begin - for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_itof (fcvt_fire, dataa[i], frm, result_itof[i], fflags_itof[i]); - dpi_utof (fcvt_fire, dataa[i], frm, result_utof[i], fflags_utof[i]); - dpi_ftoi (fcvt_fire, dataa[i], frm, result_ftoi[i], fflags_ftoi[i]); - dpi_ftou (fcvt_fire, dataa[i], frm, result_ftou[i], fflags_ftou[i]); - end - end - - assign result_fcvt = is_itof ? result_itof : - is_utof ? result_utof : - is_ftoi ? result_ftoi : - is_ftou ? result_ftou : - 0; - - assign fflags_fcvt = is_itof ? fflags_itof : - is_utof ? fflags_utof : - is_ftoi ? fflags_ftoi : - is_ftou ? fflags_ftou : - 0; - - VX_shift_register #( - .DATAW (1 + TAGW + `NUM_THREADS * (32 + $bits(fflags_t))), - .DEPTH (`LATENCY_FCVT), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (fcvt_ready), - .data_in ({fcvt_valid, tag_in, result_fcvt, fflags_fcvt}), - .data_out ({per_core_valid_out[FPU_CVT], per_core_tag_out[FPU_CVT], per_core_result[FPU_CVT], per_core_fflags[FPU_CVT]}) - ); - - assign per_core_has_fflags[FPU_CVT] = 1; - assign per_core_ready_in[FPU_CVT] = fcvt_ready; - - end - endgenerate - - generate - begin : fncp - - wire [`NUM_THREADS-1:0][31:0] result_fncp; - wire [`NUM_THREADS-1:0][31:0] result_fclss; - wire [`NUM_THREADS-1:0][31:0] result_flt; - wire [`NUM_THREADS-1:0][31:0] result_fle; - wire [`NUM_THREADS-1:0][31:0] result_feq; - wire [`NUM_THREADS-1:0][31:0] result_fmin; - wire [`NUM_THREADS-1:0][31:0] result_fmax; - wire [`NUM_THREADS-1:0][31:0] result_fsgnj; - wire [`NUM_THREADS-1:0][31:0] result_fsgnjn; - wire [`NUM_THREADS-1:0][31:0] result_fsgnjx; - reg [`NUM_THREADS-1:0][31:0] result_fmv; - - fflags_t [`NUM_THREADS-1:0] fflags_fncp; - fflags_t [`NUM_THREADS-1:0] fflags_flt; - fflags_t [`NUM_THREADS-1:0] fflags_fle; - fflags_t [`NUM_THREADS-1:0] fflags_feq; - fflags_t [`NUM_THREADS-1:0] fflags_fmin; - fflags_t [`NUM_THREADS-1:0] fflags_fmax; - - wire fncp_valid = (valid_in && core_select == FPU_NCP); - wire fncp_ready = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP]; - - wire fncp_fire = fncp_valid && fncp_ready; - - always @(*) begin - for (integer i = 0; i < `NUM_THREADS; i++) begin - dpi_fclss (fncp_fire, dataa[i], result_fclss[i]); - dpi_flt (fncp_fire, dataa[i], datab[i], result_flt[i], fflags_flt[i]); - dpi_fle (fncp_fire, dataa[i], datab[i], result_fle[i], fflags_fle[i]); - dpi_feq (fncp_fire, dataa[i], datab[i], result_feq[i], fflags_feq[i]); - dpi_fmin (fncp_fire, dataa[i], datab[i], result_fmin[i], fflags_fmin[i]); - dpi_fmax (fncp_fire, dataa[i], datab[i], result_fmax[i], fflags_fmax[i]); - dpi_fsgnj (fncp_fire, dataa[i], datab[i], result_fsgnj[i]); - dpi_fsgnjn (fncp_fire, dataa[i], datab[i], result_fsgnjn[i]); - dpi_fsgnjx (fncp_fire, dataa[i], datab[i], result_fsgnjx[i]); - result_fmv[i] = dataa[i]; - end - end - - assign result_fncp = is_fclss ? result_fclss : - is_flt ? result_flt : - is_fle ? result_fle : - is_feq ? result_feq : - is_fmin ? result_fmin : - is_fmax ? result_fmax : - is_fsgnj ? result_fsgnj : - is_fsgnjn ? result_fsgnjn : - is_fsgnjx ? result_fsgnjx : - result_fmv; - - wire has_fflags_fncp = (is_flt || is_fle || is_feq || is_fmin || is_fmax); - - assign fflags_fncp = is_flt ? fflags_flt : - is_fle ? fflags_fle : - is_feq ? fflags_feq : - is_fmin ? fflags_fmin : - is_fmax ? fflags_fmax : - 0; - - VX_shift_register #( - .DATAW (1 + TAGW + 1 + `NUM_THREADS * (32 + $bits(fflags_t))), - .DEPTH (`LATENCY_FNCP), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (fncp_ready), - .data_in ({fncp_valid, tag_in, has_fflags_fncp, result_fncp, fflags_fncp}), - .data_out ({per_core_valid_out[FPU_NCP], per_core_tag_out[FPU_NCP], per_core_has_fflags[FPU_NCP], per_core_result[FPU_NCP], per_core_fflags[FPU_NCP]}) - ); - - assign per_core_ready_in[FPU_NCP] = fncp_ready; - - end - endgenerate - - /////////////////////////////////////////////////////////////////////////// - - reg has_fflags_n; - fflags_t [`NUM_THREADS-1:0] fflags_n; - reg [`NUM_THREADS-1:0][31:0] result_n; - reg [TAGW-1:0] tag_out_n; - - always @(*) begin - per_core_ready_out = 0; - has_fflags_n = 'x; - fflags_n = 'x; - result_n = 'x; - tag_out_n = 'x; - for (integer i = 0; i < NUM_FPC; i++) begin - if (per_core_valid_out[i]) begin - has_fflags_n = per_core_has_fflags[i]; - fflags_n = per_core_fflags[i]; - result_n = per_core_result[i]; - tag_out_n = per_core_tag_out[i]; - per_core_ready_out[i] = ready_out; - break; - end - end - end - - assign valid_out = (| per_core_valid_out); - assign has_fflags = has_fflags_n; - assign tag_out = tag_out_n; - assign result = result_n; - assign fflags = fflags_n; - - assign ready_in = per_core_ready_in[core_select]; - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_fpga.sv b/hw/rtl/fp_cores/VX_fpu_fpga.sv deleted file mode 100644 index 671f1656..00000000 --- a/hw/rtl/fp_cores/VX_fpu_fpga.sv +++ /dev/null @@ -1,216 +0,0 @@ -`include "VX_fpu_define.vh" - -module VX_fpu_fpga #( - parameter TAGW = 4 -) ( - input wire clk, - input wire reset, - - input wire valid_in, - output wire ready_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FPU_BITS-1:0] op_type, - input wire [`INST_MOD_BITS-1:0] frm, - - input wire [`NUM_THREADS-1:0][31:0] dataa, - input wire [`NUM_THREADS-1:0][31:0] datab, - input wire [`NUM_THREADS-1:0][31:0] datac, - output wire [`NUM_THREADS-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [`NUM_THREADS-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - localparam FPU_FMA = 0; - localparam FPU_DIV = 1; - localparam FPU_SQRT = 2; - localparam FPU_CVT = 3; - localparam FPU_NCP = 4; - localparam NUM_FPC = 5; - localparam FPC_BITS = `LOG2UP(NUM_FPC); - - wire [NUM_FPC-1:0] per_core_ready_in; - wire [NUM_FPC-1:0][`NUM_THREADS-1:0][31:0] per_core_result; - wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out; - reg [NUM_FPC-1:0] per_core_ready_out; - wire [NUM_FPC-1:0] per_core_valid_out; - - wire [NUM_FPC-1:0] per_core_has_fflags; - fflags_t [NUM_FPC-1:0][`NUM_THREADS-1:0] per_core_fflags; - - reg [FPC_BITS-1:0] core_select; - reg do_madd, do_sub, do_neg, is_itof, is_signed; - - always @(*) begin - do_madd = 0; - do_sub = 0; - do_neg = 0; - is_itof = 0; - is_signed = 0; - case (op_type) - `INST_FPU_ADD: begin core_select = FPU_FMA; end - `INST_FPU_SUB: begin core_select = FPU_FMA; do_sub = 1; end - `INST_FPU_MUL: begin core_select = FPU_FMA; do_neg = 1; end - `INST_FPU_MADD: begin core_select = FPU_FMA; do_madd = 1; end - `INST_FPU_MSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; end - `INST_FPU_NMADD: begin core_select = FPU_FMA; do_madd = 1; do_neg = 1; end - `INST_FPU_NMSUB: begin core_select = FPU_FMA; do_madd = 1; do_sub = 1; do_neg = 1; end - `INST_FPU_DIV: begin core_select = FPU_DIV; end - `INST_FPU_SQRT: begin core_select = FPU_SQRT; end - `INST_FPU_CVTWS: begin core_select = FPU_CVT; is_signed = 1; end - `INST_FPU_CVTWUS: begin core_select = FPU_CVT; end - `INST_FPU_CVTSW: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end - `INST_FPU_CVTSWU: begin core_select = FPU_CVT; is_itof = 1; end - default: begin core_select = FPU_NCP; end - endcase - end - - `RESET_RELAY (fma_reset); - `RESET_RELAY (div_reset); - `RESET_RELAY (sqrt_reset); - `RESET_RELAY (cvt_reset); - `RESET_RELAY (ncp_reset); - - VX_fp_fma #( - .TAGW (TAGW), - .LANES(`NUM_THREADS) - ) fp_fma ( - .clk (clk), - .reset (fma_reset), - .valid_in (valid_in && (core_select == FPU_FMA)), - .ready_in (per_core_ready_in[FPU_FMA]), - .tag_in (tag_in), - .frm (frm), - .do_madd (do_madd), - .do_sub (do_sub), - .do_neg (do_neg), - .dataa (dataa), - .datab (datab), - .datac (datac), - .has_fflags (per_core_has_fflags[FPU_FMA]), - .fflags (per_core_fflags[FPU_FMA]), - .result (per_core_result[FPU_FMA]), - .tag_out (per_core_tag_out[FPU_FMA]), - .ready_out (per_core_ready_out[FPU_FMA]), - .valid_out (per_core_valid_out[FPU_FMA]) - ); - - VX_fp_div #( - .TAGW (TAGW), - .LANES(`NUM_THREADS) - ) fp_div ( - .clk (clk), - .reset (div_reset), - .valid_in (valid_in && (core_select == FPU_DIV)), - .ready_in (per_core_ready_in[FPU_DIV]), - .tag_in (tag_in), - .frm (frm), - .dataa (dataa), - .datab (datab), - .has_fflags (per_core_has_fflags[FPU_DIV]), - .fflags (per_core_fflags[FPU_DIV]), - .result (per_core_result[FPU_DIV]), - .tag_out (per_core_tag_out[FPU_DIV]), - .ready_out (per_core_ready_out[FPU_DIV]), - .valid_out (per_core_valid_out[FPU_DIV]) - ); - - VX_fp_sqrt #( - .TAGW (TAGW), - .LANES(`NUM_THREADS) - ) fp_sqrt ( - .clk (clk), - .reset (sqrt_reset), - .valid_in (valid_in && (core_select == FPU_SQRT)), - .ready_in (per_core_ready_in[FPU_SQRT]), - .tag_in (tag_in), - .frm (frm), - .dataa (dataa), - .has_fflags (per_core_has_fflags[FPU_SQRT]), - .fflags (per_core_fflags[FPU_SQRT]), - .result (per_core_result[FPU_SQRT]), - .tag_out (per_core_tag_out[FPU_SQRT]), - .ready_out (per_core_ready_out[FPU_SQRT]), - .valid_out (per_core_valid_out[FPU_SQRT]) - ); - - VX_fp_cvt #( - .TAGW (TAGW), - .LANES(`NUM_THREADS) - ) fp_cvt ( - .clk (clk), - .reset (cvt_reset), - .valid_in (valid_in && (core_select == FPU_CVT)), - .ready_in (per_core_ready_in[FPU_CVT]), - .tag_in (tag_in), - .frm (frm), - .is_itof (is_itof), - .is_signed (is_signed), - .dataa (dataa), - .has_fflags (per_core_has_fflags[FPU_CVT]), - .fflags (per_core_fflags[FPU_CVT]), - .result (per_core_result[FPU_CVT]), - .tag_out (per_core_tag_out[FPU_CVT]), - .ready_out (per_core_ready_out[FPU_CVT]), - .valid_out (per_core_valid_out[FPU_CVT]) - ); - - VX_fp_ncomp #( - .TAGW (TAGW), - .LANES(`NUM_THREADS) - ) fp_ncomp ( - .clk (clk), - .reset (ncp_reset), - .valid_in (valid_in && (core_select == FPU_NCP)), - .ready_in (per_core_ready_in[FPU_NCP]), - .tag_in (tag_in), - .op_type (op_type), - .frm (frm), - .dataa (dataa), - .datab (datab), - .result (per_core_result[FPU_NCP]), - .has_fflags (per_core_has_fflags[FPU_NCP]), - .fflags (per_core_fflags[FPU_NCP]), - .tag_out (per_core_tag_out[FPU_NCP]), - .ready_out (per_core_ready_out[FPU_NCP]), - .valid_out (per_core_valid_out[FPU_NCP]) - ); - - reg has_fflags_n; - fflags_t [`NUM_THREADS-1:0] fflags_n; - reg [`NUM_THREADS-1:0][31:0] result_n; - reg [TAGW-1:0] tag_out_n; - - always @(*) begin - per_core_ready_out = 0; - has_fflags_n = 'x; - fflags_n = 'x; - result_n = 'x; - tag_out_n = 'x; - for (integer i = 0; i < NUM_FPC; i++) begin - if (per_core_valid_out[i]) begin - has_fflags_n = per_core_has_fflags[i]; - fflags_n = per_core_fflags[i]; - result_n = per_core_result[i]; - tag_out_n = per_core_tag_out[i]; - per_core_ready_out[i] = ready_out; - break; - end - end - end - - assign valid_out = (| per_core_valid_out); - assign has_fflags = has_fflags_n; - assign tag_out = tag_out_n; - assign result = result_n; - assign fflags = fflags_n; - - assign ready_in = per_core_ready_in[core_select]; - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_fpnew.sv b/hw/rtl/fp_cores/VX_fpu_fpnew.sv deleted file mode 100644 index deaf62de..00000000 --- a/hw/rtl/fp_cores/VX_fpu_fpnew.sv +++ /dev/null @@ -1,208 +0,0 @@ -`include "VX_fpu_define.vh" -`include "fpnew_pkg.sv" -`include "defs_div_sqrt_mvp.sv" - -`TRACING_OFF -module VX_fpu_fpnew #( - parameter TAGW = 1, - parameter FMULADD = 1, - parameter FDIVSQRT = 1, - parameter FNONCOMP = 1, - parameter FCONV = 1 -) ( - input wire clk, - input wire reset, - - input wire valid_in, - output wire ready_in, - - input wire [TAGW-1:0] tag_in, - - input wire [`INST_FPU_BITS-1:0] op_type, - input wire [`INST_MOD_BITS-1:0] frm, - - input wire [`NUM_THREADS-1:0][31:0] dataa, - input wire [`NUM_THREADS-1:0][31:0] datab, - input wire [`NUM_THREADS-1:0][31:0] datac, - output wire [`NUM_THREADS-1:0][31:0] result, - - output wire has_fflags, - output fflags_t [`NUM_THREADS-1:0] fflags, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - localparam UNIT_FMULADD = FMULADD ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED; - localparam UNIT_FDIVSQRT = FDIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED; - localparam UNIT_FNONCOMP = FNONCOMP ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED; - localparam UNIT_FCONV = FCONV ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED; - - localparam FOP_BITS = fpnew_pkg::OP_BITS; - localparam FMTF_BITS = $clog2(fpnew_pkg::NUM_FP_FORMATS); - localparam FMTI_BITS = $clog2(fpnew_pkg::NUM_INT_FORMATS); - - localparam FPU_DPATHW = 32'd32; - - localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ - Width: FPU_DPATHW, - EnableVectors: 1'b0, - EnableNanBox: 1'b1, - FpFmtMask: 5'b10000, - IntFmtMask: 4'b0010 - }; - - localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ - PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL - '{default: `LATENCY_FDIVSQRT}, // DIVSQRT - '{default: `LATENCY_FNCP}, // NONCOMP - '{default: `LATENCY_FCVT}}, // CONV - UnitTypes:'{'{default: UNIT_FMULADD}, // ADDMUL - '{default: UNIT_FDIVSQRT}, // DIVSQRT - '{default: UNIT_FNONCOMP}, // NONCOMP - '{default: UNIT_FCONV}}, // CONV - PipeConfig: fpnew_pkg::DISTRIBUTED - }; - - wire fpu_ready_in, fpu_valid_in; - wire fpu_ready_out, fpu_valid_out; - - reg [TAGW-1:0] fpu_tag_in, fpu_tag_out; - - reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands; - - wire [FMTF_BITS-1:0] fpu_src_fmt = fpnew_pkg::FP32; - wire [FMTF_BITS-1:0] fpu_dst_fmt = fpnew_pkg::FP32; - wire [FMTI_BITS-1:0] fpu_int_fmt = fpnew_pkg::INT32; - - wire [`NUM_THREADS-1:0][31:0] fpu_result; - fpnew_pkg::status_t [`NUM_THREADS-1:0] fpu_status; - - reg [FOP_BITS-1:0] fpu_op; - reg [`INST_FRM_BITS-1:0] fpu_rnd; - reg fpu_op_mod; - reg fpu_has_fflags, fpu_has_fflags_out; - - always @(*) begin - fpu_op = fpnew_pkg::SGNJ; - fpu_rnd = frm; - fpu_op_mod = 0; - fpu_has_fflags = 1; - fpu_operands[0] = dataa; - fpu_operands[1] = datab; - fpu_operands[2] = datac; - - case (op_type) - `INST_FPU_ADD: begin - fpu_op = fpnew_pkg::ADD; - fpu_operands[1] = dataa; - fpu_operands[2] = datab; - end - `INST_FPU_SUB: begin - fpu_op = fpnew_pkg::ADD; - fpu_operands[1] = dataa; - fpu_operands[2] = datab; - fpu_op_mod = 1; - end - `INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end - `INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end - `INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end - `INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end - `INST_FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end - `INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end - `INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end - `INST_FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end - `INST_FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end - `INST_FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end - `INST_FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end - `INST_FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end - `INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end - `INST_FPU_MISC: begin - case (frm) - 0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RNE; fpu_has_fflags = 0; end - 1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RTZ; fpu_has_fflags = 0; end - 2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RDN; fpu_has_fflags = 0; end - 3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RNE; end - 4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RTZ; end - default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RUP; fpu_has_fflags = 0; end - endcase - end - default:; - endcase - end - - for (genvar i = 0; i < `NUM_THREADS; i++) begin - if (0 == i) begin - fpnew_top #( - .Features (FPU_FEATURES), - .Implementation (FPU_IMPLEMENTATION), - .TagType (logic[TAGW+1+1-1:0]) - ) fpnew_core ( - .clk_i (clk), - .rst_ni (1'b1), - .operands_i ({fpu_operands[2][0], fpu_operands[1][0], fpu_operands[0][0]}), - .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)), - .op_i (fpnew_pkg::operation_e'(fpu_op)), - .op_mod_i (fpu_op_mod), - .src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)), - .dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)), - .int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)), - .vectorial_op_i (1'b0), - .tag_i ({fpu_tag_in, fpu_has_fflags}), - .in_valid_i (fpu_valid_in), - .in_ready_o (fpu_ready_in), - .flush_i (reset), - .result_o (fpu_result[0]), - .status_o (fpu_status[0]), - .tag_o ({fpu_tag_out, fpu_has_fflags_out}), - .out_valid_o (fpu_valid_out), - .out_ready_i (fpu_ready_out), - `UNUSED_PIN (busy_o) - ); - end else begin - fpnew_top #( - .Features (FPU_FEATURES), - .Implementation (FPU_IMPLEMENTATION), - .TagType (logic) - ) fpnew_core ( - .clk_i (clk), - .rst_ni (1'b1), - .operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}), - .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)), - .op_i (fpnew_pkg::operation_e'(fpu_op)), - .op_mod_i (fpu_op_mod), - .src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)), - .dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)), - .int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)), - .vectorial_op_i (1'b0), - .tag_i (1'b0), - .in_valid_i (fpu_valid_in), - `UNUSED_PIN (in_ready_o), - .flush_i (reset), - .result_o (fpu_result[i]), - .status_o (fpu_status[i]), - `UNUSED_PIN (tag_o), - `UNUSED_PIN (out_valid_o), - .out_ready_i (fpu_ready_out), - `UNUSED_PIN (busy_o) - ); - end - end - - assign fpu_valid_in = valid_in; - assign ready_in = fpu_ready_in; - - assign fpu_tag_in = tag_in; - assign tag_out = fpu_tag_out; - - assign result = fpu_result; - - assign has_fflags = fpu_has_fflags_out; - assign fflags = fpu_status; - - assign valid_out = fpu_valid_out; - assign fpu_ready_out = ready_out; - -endmodule -`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpu_types.vh b/hw/rtl/fp_cores/VX_fpu_types.vh deleted file mode 100644 index df8a955f..00000000 --- a/hw/rtl/fp_cores/VX_fpu_types.vh +++ /dev/null @@ -1,32 +0,0 @@ -`ifndef VX_FPU_TYPES -`define VX_FPU_TYPES - -`include "VX_define.vh" - -package fpu_types; - -typedef struct packed { - logic is_normal; - logic is_zero; - logic is_subnormal; - logic is_inf; - logic is_nan; - logic is_quiet; - logic is_signaling; -} fp_class_t; - -`define FP_CLASS_BITS $bits(fpu_types::fp_class_t) - -typedef struct packed { - logic NV; // 4-Invalid - logic DZ; // 3-Divide by zero - logic OF; // 2-Overflow - logic UF; // 1-Underflow - logic NX; // 0-Inexact -} fflags_t; - -`define FFLAGS_BITS $bits(fpu_types::fflags_t) - -endpackage - -`endif \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv b/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv deleted file mode 100644 index b9b44742..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv +++ /dev/null @@ -1,1592 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fdiv -// SystemVerilog created on Mon Jan 18 04:15:46 2021 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fdiv ( - input wire [31:0] a, - input wire [31:0] b, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] cstBiasM1_uid6_fpDivTest_q; - wire [7:0] expX_uid9_fpDivTest_b; - wire [22:0] fracX_uid10_fpDivTest_b; - wire [0:0] signX_uid11_fpDivTest_b; - wire [7:0] expY_uid12_fpDivTest_b; - wire [22:0] fracY_uid13_fpDivTest_b; - wire [0:0] signY_uid14_fpDivTest_b; - wire [22:0] paddingY_uid15_fpDivTest_q; - wire [23:0] updatedY_uid16_fpDivTest_q; - wire [23:0] fracYZero_uid15_fpDivTest_a; - wire [0:0] fracYZero_uid15_fpDivTest_qi; - reg [0:0] fracYZero_uid15_fpDivTest_q; - wire [7:0] cstAllOWE_uid18_fpDivTest_q; - wire [7:0] cstAllZWE_uid20_fpDivTest_q; - wire [0:0] excZ_x_uid23_fpDivTest_qi; - reg [0:0] excZ_x_uid23_fpDivTest_q; - wire [0:0] expXIsMax_uid24_fpDivTest_qi; - reg [0:0] expXIsMax_uid24_fpDivTest_q; - wire [0:0] fracXIsZero_uid25_fpDivTest_qi; - reg [0:0] fracXIsZero_uid25_fpDivTest_q; - wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; - wire [0:0] excI_x_uid27_fpDivTest_q; - wire [0:0] excN_x_uid28_fpDivTest_q; - wire [0:0] invExpXIsMax_uid29_fpDivTest_q; - wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; - wire [0:0] excR_x_uid31_fpDivTest_q; - wire [0:0] excZ_y_uid37_fpDivTest_qi; - reg [0:0] excZ_y_uid37_fpDivTest_q; - wire [0:0] expXIsMax_uid38_fpDivTest_qi; - reg [0:0] expXIsMax_uid38_fpDivTest_q; - wire [0:0] fracXIsZero_uid39_fpDivTest_qi; - reg [0:0] fracXIsZero_uid39_fpDivTest_q; - wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; - wire [0:0] excI_y_uid41_fpDivTest_q; - wire [0:0] excN_y_uid42_fpDivTest_q; - wire [0:0] invExpXIsMax_uid43_fpDivTest_q; - wire [0:0] InvExpXIsZero_uid44_fpDivTest_q; - wire [0:0] excR_y_uid45_fpDivTest_q; - wire [0:0] signR_uid46_fpDivTest_qi; - reg [0:0] signR_uid46_fpDivTest_q; - wire [8:0] expXmY_uid47_fpDivTest_a; - wire [8:0] expXmY_uid47_fpDivTest_b; - logic [8:0] expXmY_uid47_fpDivTest_o; - wire [8:0] expXmY_uid47_fpDivTest_q; - wire [10:0] expR_uid48_fpDivTest_a; - wire [10:0] expR_uid48_fpDivTest_b; - logic [10:0] expR_uid48_fpDivTest_o; - wire [9:0] expR_uid48_fpDivTest_q; - wire [8:0] yAddr_uid51_fpDivTest_b; - wire [13:0] yPE_uid52_fpDivTest_b; - wire [0:0] fracYPostZ_uid56_fpDivTest_qi; - reg [0:0] fracYPostZ_uid56_fpDivTest_q; - wire [23:0] lOAdded_uid58_fpDivTest_q; - wire [1:0] oFracXSE_bottomExtension_uid61_fpDivTest_q; - wire [25:0] oFracXSE_mergedSignalTM_uid63_fpDivTest_q; - wire [0:0] divValPreNormTrunc_uid66_fpDivTest_s; - reg [25:0] divValPreNormTrunc_uid66_fpDivTest_q; - wire [0:0] norm_uid67_fpDivTest_b; - wire [24:0] divValPreNormHigh_uid68_fpDivTest_in; - wire [23:0] divValPreNormHigh_uid68_fpDivTest_b; - wire [23:0] divValPreNormLow_uid69_fpDivTest_in; - wire [23:0] divValPreNormLow_uid69_fpDivTest_b; - wire [0:0] normFracRnd_uid70_fpDivTest_s; - reg [23:0] normFracRnd_uid70_fpDivTest_q; - wire [33:0] expFracRnd_uid71_fpDivTest_q; - wire [24:0] rndOp_uid75_fpDivTest_q; - wire [35:0] expFracPostRnd_uid76_fpDivTest_a; - wire [35:0] expFracPostRnd_uid76_fpDivTest_b; - logic [35:0] expFracPostRnd_uid76_fpDivTest_o; - wire [34:0] expFracPostRnd_uid76_fpDivTest_q; - wire [23:0] fracRPreExc_uid78_fpDivTest_in; - wire [22:0] fracRPreExc_uid78_fpDivTest_b; - wire [31:0] excRPreExc_uid79_fpDivTest_in; - wire [7:0] excRPreExc_uid79_fpDivTest_b; - wire [10:0] expRExt_uid80_fpDivTest_b; - wire [12:0] expUdf_uid81_fpDivTest_a; - wire [12:0] expUdf_uid81_fpDivTest_b; - logic [12:0] expUdf_uid81_fpDivTest_o; - wire [0:0] expUdf_uid81_fpDivTest_n; - wire [12:0] expOvf_uid84_fpDivTest_a; - wire [12:0] expOvf_uid84_fpDivTest_b; - logic [12:0] expOvf_uid84_fpDivTest_o; - wire [0:0] expOvf_uid84_fpDivTest_n; - wire [0:0] zeroOverReg_uid85_fpDivTest_q; - wire [0:0] regOverRegWithUf_uid86_fpDivTest_q; - wire [0:0] xRegOrZero_uid87_fpDivTest_q; - wire [0:0] regOrZeroOverInf_uid88_fpDivTest_q; - wire [0:0] excRZero_uid89_fpDivTest_q; - wire [0:0] excXRYZ_uid90_fpDivTest_q; - wire [0:0] excXRYROvf_uid91_fpDivTest_q; - wire [0:0] excXIYZ_uid92_fpDivTest_q; - wire [0:0] excXIYR_uid93_fpDivTest_q; - wire [0:0] excRInf_uid94_fpDivTest_q; - wire [0:0] excXZYZ_uid95_fpDivTest_q; - wire [0:0] excXIYI_uid96_fpDivTest_q; - wire [0:0] excRNaN_uid97_fpDivTest_q; - wire [2:0] concExc_uid98_fpDivTest_q; - reg [1:0] excREnc_uid99_fpDivTest_q; - wire [22:0] oneFracRPostExc2_uid100_fpDivTest_q; - wire [1:0] fracRPostExc_uid103_fpDivTest_s; - reg [22:0] fracRPostExc_uid103_fpDivTest_q; - wire [1:0] expRPostExc_uid107_fpDivTest_s; - reg [7:0] expRPostExc_uid107_fpDivTest_q; - wire [0:0] invExcRNaN_uid108_fpDivTest_q; - wire [0:0] sRPostExc_uid109_fpDivTest_qi; - reg [0:0] sRPostExc_uid109_fpDivTest_q; - wire [31:0] divR_uid110_fpDivTest_q; - wire [11:0] yT1_uid124_invPolyEval_b; - wire [0:0] lowRangeB_uid126_invPolyEval_in; - wire [0:0] lowRangeB_uid126_invPolyEval_b; - wire [11:0] highBBits_uid127_invPolyEval_b; - wire [21:0] s1sumAHighB_uid128_invPolyEval_a; - wire [21:0] s1sumAHighB_uid128_invPolyEval_b; - logic [21:0] s1sumAHighB_uid128_invPolyEval_o; - wire [21:0] s1sumAHighB_uid128_invPolyEval_q; - wire [22:0] s1_uid129_invPolyEval_q; - wire [1:0] lowRangeB_uid132_invPolyEval_in; - wire [1:0] lowRangeB_uid132_invPolyEval_b; - wire [21:0] highBBits_uid133_invPolyEval_b; - wire [31:0] s2sumAHighB_uid134_invPolyEval_a; - wire [31:0] s2sumAHighB_uid134_invPolyEval_b; - logic [31:0] s2sumAHighB_uid134_invPolyEval_o; - wire [31:0] s2sumAHighB_uid134_invPolyEval_q; - wire [33:0] s2_uid135_invPolyEval_q; - wire [25:0] osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; - wire [12:0] osig_uid141_pT1_uid125_invPolyEval_b; - wire [23:0] osig_uid144_pT2_uid131_invPolyEval_b; - wire memoryC0_uid112_invTables_lutmem_reset0; - wire [30:0] memoryC0_uid112_invTables_lutmem_ia; - wire [8:0] memoryC0_uid112_invTables_lutmem_aa; - wire [8:0] memoryC0_uid112_invTables_lutmem_ab; - wire [30:0] memoryC0_uid112_invTables_lutmem_ir; - wire [30:0] memoryC0_uid112_invTables_lutmem_r; - wire memoryC1_uid115_invTables_lutmem_reset0; - wire [20:0] memoryC1_uid115_invTables_lutmem_ia; - wire [8:0] memoryC1_uid115_invTables_lutmem_aa; - wire [8:0] memoryC1_uid115_invTables_lutmem_ab; - wire [20:0] memoryC1_uid115_invTables_lutmem_ir; - wire [20:0] memoryC1_uid115_invTables_lutmem_r; - wire memoryC2_uid118_invTables_lutmem_reset0; - wire [11:0] memoryC2_uid118_invTables_lutmem_ia; - wire [8:0] memoryC2_uid118_invTables_lutmem_aa; - wire [8:0] memoryC2_uid118_invTables_lutmem_ab; - wire [11:0] memoryC2_uid118_invTables_lutmem_ir; - wire [11:0] memoryC2_uid118_invTables_lutmem_r; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y [0:0]; - reg [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s [0:0]; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq; - wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1; - wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 [0:0]; - wire signed [12:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_l [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_p [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_u [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_w [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_x [0:0]; - wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_y [0:0]; - reg signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_s [0:0]; - wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_qq; - wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_q; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1; - wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 [0:0]; - wire signed [14:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_l [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_p [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_u [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_w [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_x [0:0]; - wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_y [0:0]; - reg signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_s [0:0]; - wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_qq; - wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_q; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1; - wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2; - wire [31:0] invY_uid54_fpDivTest_merged_bit_select_in; - wire [25:0] invY_uid54_fpDivTest_merged_bit_select_b; - wire [0:0] invY_uid54_fpDivTest_merged_bit_select_c; - reg [25:0] redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; - reg [0:0] redist1_lowRangeB_uid126_invPolyEval_b_1_q; - reg [7:0] redist2_excRPreExc_uid79_fpDivTest_b_1_q; - reg [22:0] redist3_fracRPreExc_uid78_fpDivTest_b_1_q; - reg [23:0] redist4_lOAdded_uid58_fpDivTest_q_3_q; - reg [0:0] redist5_fracYPostZ_uid56_fpDivTest_q_4_q; - reg [13:0] redist6_yPE_uid52_fpDivTest_b_2_q; - reg [8:0] redist8_yAddr_uid51_fpDivTest_b_3_q; - reg [8:0] redist9_yAddr_uid51_fpDivTest_b_7_q; - reg [0:0] redist11_signR_uid46_fpDivTest_q_14_q; - reg [0:0] redist12_fracXIsZero_uid39_fpDivTest_q_14_q; - reg [0:0] redist13_expXIsMax_uid38_fpDivTest_q_14_q; - reg [0:0] redist14_excZ_y_uid37_fpDivTest_q_14_q; - reg [0:0] redist15_fracXIsZero_uid25_fpDivTest_q_4_q; - reg [0:0] redist16_expXIsMax_uid24_fpDivTest_q_14_q; - reg [0:0] redist17_excZ_x_uid23_fpDivTest_q_14_q; - reg [0:0] redist18_fracYZero_uid15_fpDivTest_q_9_q; - wire redist7_yPE_uid52_fpDivTest_b_6_mem_reset0; - wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ia; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_aa; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ab; - wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_iq; - wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_q; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; - (* preserve *) reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i; - (* preserve *) reg redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_s; - reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; - reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; - wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_last_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmp_q; - reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_notEnable_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_nor_q; - (* preserve_syn_only *) reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q; - wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q; - reg [8:0] redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q; - wire redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0; - wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ia; - wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_aa; - wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ab; - wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_iq; - wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_q; - wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; - (* preserve *) reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i; - (* preserve *) reg redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s; - reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; - reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; - wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q; - wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_b; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; - reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_nor_q; - (* preserve_syn_only *) reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q; - wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q; - wire redist19_fracX_uid10_fpDivTest_b_10_mem_reset0; - wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ia; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_aa; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ab; - wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_iq; - wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_q; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; - (* preserve *) reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i; - (* preserve *) reg redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_s; - reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; - reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; - wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_last_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmp_q; - reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_notEnable_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_nor_q; - (* preserve_syn_only *) reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q; - wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q; - - - // fracY_uid13_fpDivTest(BITSELECT,12)@0 - assign fracY_uid13_fpDivTest_b = b[22:0]; - - // paddingY_uid15_fpDivTest(CONSTANT,14) - assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1 - assign fracXIsZero_uid39_fpDivTest_qi = paddingY_uid15_fpDivTest_q == fracY_uid13_fpDivTest_b ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid39_fpDivTest_delay ( .xin(fracXIsZero_uid39_fpDivTest_qi), .xout(fracXIsZero_uid39_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist12_fracXIsZero_uid39_fpDivTest_q_14(DELAY,164) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist12_fracXIsZero_uid39_fpDivTest_q_14 ( .xin(fracXIsZero_uid39_fpDivTest_q), .xout(redist12_fracXIsZero_uid39_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid18_fpDivTest(CONSTANT,17) - assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; - - // expY_uid12_fpDivTest(BITSELECT,11)@0 - assign expY_uid12_fpDivTest_b = b[30:23]; - - // expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1 - assign expXIsMax_uid38_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid38_fpDivTest_delay ( .xin(expXIsMax_uid38_fpDivTest_qi), .xout(expXIsMax_uid38_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist13_expXIsMax_uid38_fpDivTest_q_14(DELAY,165) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist13_expXIsMax_uid38_fpDivTest_q_14 ( .xin(expXIsMax_uid38_fpDivTest_q), .xout(redist13_expXIsMax_uid38_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_y_uid41_fpDivTest(LOGICAL,40)@14 - assign excI_y_uid41_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & redist12_fracXIsZero_uid39_fpDivTest_q_14_q; - - // redist19_fracX_uid10_fpDivTest_b_10_notEnable(LOGICAL,202) - assign redist19_fracX_uid10_fpDivTest_b_10_notEnable_q = ~ (en); - - // redist19_fracX_uid10_fpDivTest_b_10_nor(LOGICAL,203) - assign redist19_fracX_uid10_fpDivTest_b_10_nor_q = ~ (redist19_fracX_uid10_fpDivTest_b_10_notEnable_q | redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q); - - // redist19_fracX_uid10_fpDivTest_b_10_mem_last(CONSTANT,199) - assign redist19_fracX_uid10_fpDivTest_b_10_mem_last_q = 4'b0111; - - // redist19_fracX_uid10_fpDivTest_b_10_cmp(LOGICAL,200) - assign redist19_fracX_uid10_fpDivTest_b_10_cmp_q = redist19_fracX_uid10_fpDivTest_b_10_mem_last_q == redist19_fracX_uid10_fpDivTest_b_10_rdmux_q ? 1'b1 : 1'b0; - - // redist19_fracX_uid10_fpDivTest_b_10_cmpReg(REG,201) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= redist19_fracX_uid10_fpDivTest_b_10_cmp_q; - end - end - - // redist19_fracX_uid10_fpDivTest_b_10_sticky_ena(REG,204) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= 1'b0; - end - else if (redist19_fracX_uid10_fpDivTest_b_10_nor_q == 1'b1) - begin - redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; - end - end - - // redist19_fracX_uid10_fpDivTest_b_10_enaAnd(LOGICAL,205) - assign redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q = redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q & en; - - // redist19_fracX_uid10_fpDivTest_b_10_rdcnt(COUNTER,196) - // low=0, high=8, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= 4'd0; - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i == 4'd7) - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b1; - end - else - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; - end - if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq == 1'b1) - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd8); - end - else - begin - redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i[3:0]; - - // redist19_fracX_uid10_fpDivTest_b_10_rdmux(MUX,197) - assign redist19_fracX_uid10_fpDivTest_b_10_rdmux_s = en; - always @(redist19_fracX_uid10_fpDivTest_b_10_rdmux_s or redist19_fracX_uid10_fpDivTest_b_10_wraddr_q or redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q) - begin - unique case (redist19_fracX_uid10_fpDivTest_b_10_rdmux_s) - 1'b0 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; - 1'b1 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; - default : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = 4'b0; - endcase - end - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // fracX_uid10_fpDivTest(BITSELECT,9)@0 - assign fracX_uid10_fpDivTest_b = a[22:0]; - - // redist19_fracX_uid10_fpDivTest_b_10_wraddr(REG,198) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= 4'b1000; - end - else - begin - redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; - end - end - - // redist19_fracX_uid10_fpDivTest_b_10_mem(DUALMEM,195) - assign redist19_fracX_uid10_fpDivTest_b_10_mem_ia = fracX_uid10_fpDivTest_b; - assign redist19_fracX_uid10_fpDivTest_b_10_mem_aa = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; - assign redist19_fracX_uid10_fpDivTest_b_10_mem_ab = redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; - assign redist19_fracX_uid10_fpDivTest_b_10_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(4), - .numwords_a(9), - .width_b(23), - .widthad_b(4), - .numwords_b(9), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist19_fracX_uid10_fpDivTest_b_10_mem_dmem ( - .clocken1(redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist19_fracX_uid10_fpDivTest_b_10_mem_reset0), - .clock1(clk), - .address_a(redist19_fracX_uid10_fpDivTest_b_10_mem_aa), - .data_a(redist19_fracX_uid10_fpDivTest_b_10_mem_ia), - .wren_a(en[0]), - .address_b(redist19_fracX_uid10_fpDivTest_b_10_mem_ab), - .q_b(redist19_fracX_uid10_fpDivTest_b_10_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist19_fracX_uid10_fpDivTest_b_10_mem_q = redist19_fracX_uid10_fpDivTest_b_10_mem_iq[22:0]; - - // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@10 + 1 - assign fracXIsZero_uid25_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist19_fracX_uid10_fpDivTest_b_10_mem_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid25_fpDivTest_delay ( .xin(fracXIsZero_uid25_fpDivTest_qi), .xout(fracXIsZero_uid25_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist15_fracXIsZero_uid25_fpDivTest_q_4(DELAY,167) - dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) - redist15_fracXIsZero_uid25_fpDivTest_q_4 ( .xin(fracXIsZero_uid25_fpDivTest_q), .xout(redist15_fracXIsZero_uid25_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expX_uid9_fpDivTest(BITSELECT,8)@0 - assign expX_uid9_fpDivTest_b = a[30:23]; - - // expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1 - assign expXIsMax_uid24_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid24_fpDivTest_delay ( .xin(expXIsMax_uid24_fpDivTest_qi), .xout(expXIsMax_uid24_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist16_expXIsMax_uid24_fpDivTest_q_14(DELAY,168) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist16_expXIsMax_uid24_fpDivTest_q_14 ( .xin(expXIsMax_uid24_fpDivTest_q), .xout(redist16_expXIsMax_uid24_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid27_fpDivTest(LOGICAL,26)@14 - assign excI_x_uid27_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & redist15_fracXIsZero_uid25_fpDivTest_q_4_q; - - // excXIYI_uid96_fpDivTest(LOGICAL,95)@14 - assign excXIYI_uid96_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; - - // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@14 - assign fracXIsNotZero_uid40_fpDivTest_q = ~ (redist12_fracXIsZero_uid39_fpDivTest_q_14_q); - - // excN_y_uid42_fpDivTest(LOGICAL,41)@14 - assign excN_y_uid42_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & fracXIsNotZero_uid40_fpDivTest_q; - - // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@14 - assign fracXIsNotZero_uid26_fpDivTest_q = ~ (redist15_fracXIsZero_uid25_fpDivTest_q_4_q); - - // excN_x_uid28_fpDivTest(LOGICAL,27)@14 - assign excN_x_uid28_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & fracXIsNotZero_uid26_fpDivTest_q; - - // cstAllZWE_uid20_fpDivTest(CONSTANT,19) - assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; - - // excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1 - assign excZ_y_uid37_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_y_uid37_fpDivTest_delay ( .xin(excZ_y_uid37_fpDivTest_qi), .xout(excZ_y_uid37_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist14_excZ_y_uid37_fpDivTest_q_14(DELAY,166) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist14_excZ_y_uid37_fpDivTest_q_14 ( .xin(excZ_y_uid37_fpDivTest_q), .xout(redist14_excZ_y_uid37_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1 - assign excZ_x_uid23_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_x_uid23_fpDivTest_delay ( .xin(excZ_x_uid23_fpDivTest_qi), .xout(excZ_x_uid23_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist17_excZ_x_uid23_fpDivTest_q_14(DELAY,169) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist17_excZ_x_uid23_fpDivTest_q_14 ( .xin(excZ_x_uid23_fpDivTest_q), .xout(redist17_excZ_x_uid23_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excXZYZ_uid95_fpDivTest(LOGICAL,94)@14 - assign excXZYZ_uid95_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - - // excRNaN_uid97_fpDivTest(LOGICAL,96)@14 - assign excRNaN_uid97_fpDivTest_q = excXZYZ_uid95_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid96_fpDivTest_q; - - // invExcRNaN_uid108_fpDivTest(LOGICAL,107)@14 - assign invExcRNaN_uid108_fpDivTest_q = ~ (excRNaN_uid97_fpDivTest_q); - - // signY_uid14_fpDivTest(BITSELECT,13)@0 - assign signY_uid14_fpDivTest_b = b[31:31]; - - // signX_uid11_fpDivTest(BITSELECT,10)@0 - assign signX_uid11_fpDivTest_b = a[31:31]; - - // signR_uid46_fpDivTest(LOGICAL,45)@0 + 1 - assign signR_uid46_fpDivTest_qi = signX_uid11_fpDivTest_b ^ signY_uid14_fpDivTest_b; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist11_signR_uid46_fpDivTest_q_14(DELAY,163) - dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) - redist11_signR_uid46_fpDivTest_q_14 ( .xin(signR_uid46_fpDivTest_q), .xout(redist11_signR_uid46_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // sRPostExc_uid109_fpDivTest(LOGICAL,108)@14 + 1 - assign sRPostExc_uid109_fpDivTest_qi = redist11_signR_uid46_fpDivTest_q_14_q & invExcRNaN_uid108_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - sRPostExc_uid109_fpDivTest_delay ( .xin(sRPostExc_uid109_fpDivTest_qi), .xout(sRPostExc_uid109_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // lOAdded_uid58_fpDivTest(BITJOIN,57)@10 - assign lOAdded_uid58_fpDivTest_q = {VCC_q, redist19_fracX_uid10_fpDivTest_b_10_mem_q}; - - // redist4_lOAdded_uid58_fpDivTest_q_3(DELAY,156) - dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) - redist4_lOAdded_uid58_fpDivTest_q_3 ( .xin(lOAdded_uid58_fpDivTest_q), .xout(redist4_lOAdded_uid58_fpDivTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60) - assign oFracXSE_bottomExtension_uid61_fpDivTest_q = 2'b00; - - // oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@13 - assign oFracXSE_mergedSignalTM_uid63_fpDivTest_q = {redist4_lOAdded_uid58_fpDivTest_q_3_q, oFracXSE_bottomExtension_uid61_fpDivTest_q}; - - // yAddr_uid51_fpDivTest(BITSELECT,50)@0 - assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; - - // memoryC2_uid118_invTables_lutmem(DUALMEM,147)@0 + 2 - // in j@20000000 - assign memoryC2_uid118_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; - assign memoryC2_uid118_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(12), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC2_uid118_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC2_uid118_invTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC2_uid118_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC2_uid118_invTables_lutmem_aa), - .q_a(memoryC2_uid118_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC2_uid118_invTables_lutmem_r = memoryC2_uid118_invTables_lutmem_ir[11:0]; - - // yPE_uid52_fpDivTest(BITSELECT,51)@0 - assign yPE_uid52_fpDivTest_b = b[13:0]; - - // redist6_yPE_uid52_fpDivTest_b_2(DELAY,158) - dspba_delay_ver #( .width(14), .depth(2), .reset_kind("ASYNC") ) - redist6_yPE_uid52_fpDivTest_b_2 ( .xin(yPE_uid52_fpDivTest_b), .xout(redist6_yPE_uid52_fpDivTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // yT1_uid124_invPolyEval(BITSELECT,123)@2 - assign yT1_uid124_invPolyEval_b = redist6_yPE_uid52_fpDivTest_b_2_q[13:2]; - - // prodXY_uid140_pT1_uid125_invPolyEval_cma(CHAINMULTADD,149)@2 + 3 - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_reset = areset; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid140_pT1_uid125_invPolyEval_cma_a1[0][11:0]}); - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] * prodXY_uid140_pT1_uid125_invPolyEval_cma_c1[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0][24:0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0]; - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a0[0] <= yT1_uid124_invPolyEval_b; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c0[0] <= memoryC2_uid118_invTables_lutmem_r; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_a0; - prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0] <= prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid140_pT1_uid125_invPolyEval_cma_delay ( .xin(prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid140_pT1_uid125_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid140_pT1_uid125_invPolyEval_cma_q = prodXY_uid140_pT1_uid125_invPolyEval_cma_qq[23:0]; - - // osig_uid141_pT1_uid125_invPolyEval(BITSELECT,140)@5 - assign osig_uid141_pT1_uid125_invPolyEval_b = prodXY_uid140_pT1_uid125_invPolyEval_cma_q[23:11]; - - // highBBits_uid127_invPolyEval(BITSELECT,126)@5 - assign highBBits_uid127_invPolyEval_b = osig_uid141_pT1_uid125_invPolyEval_b[12:1]; - - // redist8_yAddr_uid51_fpDivTest_b_3(DELAY,160) - dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) - redist8_yAddr_uid51_fpDivTest_b_3 ( .xin(yAddr_uid51_fpDivTest_b), .xout(redist8_yAddr_uid51_fpDivTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC1_uid115_invTables_lutmem(DUALMEM,146)@3 + 2 - // in j@20000000 - assign memoryC1_uid115_invTables_lutmem_aa = redist8_yAddr_uid51_fpDivTest_b_3_q; - assign memoryC1_uid115_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(21), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC1_uid115_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC1_uid115_invTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC1_uid115_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC1_uid115_invTables_lutmem_aa), - .q_a(memoryC1_uid115_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC1_uid115_invTables_lutmem_r = memoryC1_uid115_invTables_lutmem_ir[20:0]; - - // s1sumAHighB_uid128_invPolyEval(ADD,127)@5 + 1 - assign s1sumAHighB_uid128_invPolyEval_a = {{1{memoryC1_uid115_invTables_lutmem_r[20]}}, memoryC1_uid115_invTables_lutmem_r}; - assign s1sumAHighB_uid128_invPolyEval_b = {{10{highBBits_uid127_invPolyEval_b[11]}}, highBBits_uid127_invPolyEval_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - s1sumAHighB_uid128_invPolyEval_o <= 22'b0; - end - else if (en == 1'b1) - begin - s1sumAHighB_uid128_invPolyEval_o <= $signed(s1sumAHighB_uid128_invPolyEval_a) + $signed(s1sumAHighB_uid128_invPolyEval_b); - end - end - assign s1sumAHighB_uid128_invPolyEval_q = s1sumAHighB_uid128_invPolyEval_o[21:0]; - - // lowRangeB_uid126_invPolyEval(BITSELECT,125)@5 - assign lowRangeB_uid126_invPolyEval_in = osig_uid141_pT1_uid125_invPolyEval_b[0:0]; - assign lowRangeB_uid126_invPolyEval_b = lowRangeB_uid126_invPolyEval_in[0:0]; - - // redist1_lowRangeB_uid126_invPolyEval_b_1(DELAY,153) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist1_lowRangeB_uid126_invPolyEval_b_1 ( .xin(lowRangeB_uid126_invPolyEval_b), .xout(redist1_lowRangeB_uid126_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // s1_uid129_invPolyEval(BITJOIN,128)@6 - assign s1_uid129_invPolyEval_q = {s1sumAHighB_uid128_invPolyEval_q, redist1_lowRangeB_uid126_invPolyEval_b_1_q}; - - // redist7_yPE_uid52_fpDivTest_b_6_notEnable(LOGICAL,179) - assign redist7_yPE_uid52_fpDivTest_b_6_notEnable_q = ~ (en); - - // redist7_yPE_uid52_fpDivTest_b_6_nor(LOGICAL,180) - assign redist7_yPE_uid52_fpDivTest_b_6_nor_q = ~ (redist7_yPE_uid52_fpDivTest_b_6_notEnable_q | redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q); - - // redist7_yPE_uid52_fpDivTest_b_6_mem_last(CONSTANT,176) - assign redist7_yPE_uid52_fpDivTest_b_6_mem_last_q = 2'b01; - - // redist7_yPE_uid52_fpDivTest_b_6_cmp(LOGICAL,177) - assign redist7_yPE_uid52_fpDivTest_b_6_cmp_q = redist7_yPE_uid52_fpDivTest_b_6_mem_last_q == redist7_yPE_uid52_fpDivTest_b_6_rdmux_q ? 1'b1 : 1'b0; - - // redist7_yPE_uid52_fpDivTest_b_6_cmpReg(REG,178) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= redist7_yPE_uid52_fpDivTest_b_6_cmp_q; - end - end - - // redist7_yPE_uid52_fpDivTest_b_6_sticky_ena(REG,181) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= 1'b0; - end - else if (redist7_yPE_uid52_fpDivTest_b_6_nor_q == 1'b1) - begin - redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; - end - end - - // redist7_yPE_uid52_fpDivTest_b_6_enaAnd(LOGICAL,182) - assign redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q = redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q & en; - - // redist7_yPE_uid52_fpDivTest_b_6_rdcnt(COUNTER,173) - // low=0, high=2, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= 2'd0; - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i == 2'd1) - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b1; - end - else - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; - end - if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq == 1'b1) - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd2); - end - else - begin - redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); - end - end - end - assign redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i[1:0]; - - // redist7_yPE_uid52_fpDivTest_b_6_rdmux(MUX,174) - assign redist7_yPE_uid52_fpDivTest_b_6_rdmux_s = en; - always @(redist7_yPE_uid52_fpDivTest_b_6_rdmux_s or redist7_yPE_uid52_fpDivTest_b_6_wraddr_q or redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q) - begin - unique case (redist7_yPE_uid52_fpDivTest_b_6_rdmux_s) - 1'b0 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; - 1'b1 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; - default : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = 2'b0; - endcase - end - - // redist7_yPE_uid52_fpDivTest_b_6_wraddr(REG,175) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= 2'b10; - end - else - begin - redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; - end - end - - // redist7_yPE_uid52_fpDivTest_b_6_mem(DUALMEM,172) - assign redist7_yPE_uid52_fpDivTest_b_6_mem_ia = redist6_yPE_uid52_fpDivTest_b_2_q; - assign redist7_yPE_uid52_fpDivTest_b_6_mem_aa = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; - assign redist7_yPE_uid52_fpDivTest_b_6_mem_ab = redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; - assign redist7_yPE_uid52_fpDivTest_b_6_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(14), - .widthad_a(2), - .numwords_a(3), - .width_b(14), - .widthad_b(2), - .numwords_b(3), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist7_yPE_uid52_fpDivTest_b_6_mem_dmem ( - .clocken1(redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist7_yPE_uid52_fpDivTest_b_6_mem_reset0), - .clock1(clk), - .address_a(redist7_yPE_uid52_fpDivTest_b_6_mem_aa), - .data_a(redist7_yPE_uid52_fpDivTest_b_6_mem_ia), - .wren_a(en[0]), - .address_b(redist7_yPE_uid52_fpDivTest_b_6_mem_ab), - .q_b(redist7_yPE_uid52_fpDivTest_b_6_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist7_yPE_uid52_fpDivTest_b_6_mem_q = redist7_yPE_uid52_fpDivTest_b_6_mem_iq[13:0]; - - // prodXY_uid143_pT2_uid131_invPolyEval_cma(CHAINMULTADD,150)@6 + 3 - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_reset = areset; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid143_pT2_uid131_invPolyEval_cma_a1[0][13:0]}); - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] * prodXY_uid143_pT2_uid131_invPolyEval_cma_c1[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0][37:0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0]; - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a0[0] <= redist7_yPE_uid52_fpDivTest_b_6_mem_q; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c0[0] <= s1_uid129_invPolyEval_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_a0; - prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0] <= prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(37), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid143_pT2_uid131_invPolyEval_cma_delay ( .xin(prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0][36:0]), .xout(prodXY_uid143_pT2_uid131_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid143_pT2_uid131_invPolyEval_cma_q = prodXY_uid143_pT2_uid131_invPolyEval_cma_qq[36:0]; - - // osig_uid144_pT2_uid131_invPolyEval(BITSELECT,143)@9 - assign osig_uid144_pT2_uid131_invPolyEval_b = prodXY_uid143_pT2_uid131_invPolyEval_cma_q[36:13]; - - // highBBits_uid133_invPolyEval(BITSELECT,132)@9 - assign highBBits_uid133_invPolyEval_b = osig_uid144_pT2_uid131_invPolyEval_b[23:2]; - - // redist9_yAddr_uid51_fpDivTest_b_7(DELAY,161) - dspba_delay_ver #( .width(9), .depth(4), .reset_kind("ASYNC") ) - redist9_yAddr_uid51_fpDivTest_b_7 ( .xin(redist8_yAddr_uid51_fpDivTest_b_3_q), .xout(redist9_yAddr_uid51_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC0_uid112_invTables_lutmem(DUALMEM,145)@7 + 2 - // in j@20000000 - assign memoryC0_uid112_invTables_lutmem_aa = redist9_yAddr_uid51_fpDivTest_b_7_q; - assign memoryC0_uid112_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(31), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC0_uid112_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC0_uid112_invTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC0_uid112_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC0_uid112_invTables_lutmem_aa), - .q_a(memoryC0_uid112_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC0_uid112_invTables_lutmem_r = memoryC0_uid112_invTables_lutmem_ir[30:0]; - - // s2sumAHighB_uid134_invPolyEval(ADD,133)@9 - assign s2sumAHighB_uid134_invPolyEval_a = {{1{memoryC0_uid112_invTables_lutmem_r[30]}}, memoryC0_uid112_invTables_lutmem_r}; - assign s2sumAHighB_uid134_invPolyEval_b = {{10{highBBits_uid133_invPolyEval_b[21]}}, highBBits_uid133_invPolyEval_b}; - assign s2sumAHighB_uid134_invPolyEval_o = $signed(s2sumAHighB_uid134_invPolyEval_a) + $signed(s2sumAHighB_uid134_invPolyEval_b); - assign s2sumAHighB_uid134_invPolyEval_q = s2sumAHighB_uid134_invPolyEval_o[31:0]; - - // lowRangeB_uid132_invPolyEval(BITSELECT,131)@9 - assign lowRangeB_uid132_invPolyEval_in = osig_uid144_pT2_uid131_invPolyEval_b[1:0]; - assign lowRangeB_uid132_invPolyEval_b = lowRangeB_uid132_invPolyEval_in[1:0]; - - // s2_uid135_invPolyEval(BITJOIN,134)@9 - assign s2_uid135_invPolyEval_q = {s2sumAHighB_uid134_invPolyEval_q, lowRangeB_uid132_invPolyEval_b}; - - // invY_uid54_fpDivTest_merged_bit_select(BITSELECT,151)@9 - assign invY_uid54_fpDivTest_merged_bit_select_in = s2_uid135_invPolyEval_q[31:0]; - assign invY_uid54_fpDivTest_merged_bit_select_b = invY_uid54_fpDivTest_merged_bit_select_in[30:5]; - assign invY_uid54_fpDivTest_merged_bit_select_c = invY_uid54_fpDivTest_merged_bit_select_in[31:31]; - - // redist0_invY_uid54_fpDivTest_merged_bit_select_b_1(DELAY,152) - dspba_delay_ver #( .width(26), .depth(1), .reset_kind("ASYNC") ) - redist0_invY_uid54_fpDivTest_merged_bit_select_b_1 ( .xin(invY_uid54_fpDivTest_merged_bit_select_b), .xout(redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma(CHAINMULTADD,148)@10 + 3 - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset = areset; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 = en[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1[0] * prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0][49:0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0]; - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 <= '{default: '0}; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 == 1'b1) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0[0] <= redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0[0] <= lOAdded_uid58_fpDivTest_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= '{default: '0}; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 == 1'b1) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0; - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 == 1'b1) - begin - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0] <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(50), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_delay ( .xin(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0][49:0]), .xout(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq[49:0]; - - // osig_uid138_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,137)@13 - assign osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q[49:24]; - - // updatedY_uid16_fpDivTest(BITJOIN,15)@0 - assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; - - // fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1 - assign fracYZero_uid15_fpDivTest_a = {1'b0, fracY_uid13_fpDivTest_b}; - assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist18_fracYZero_uid15_fpDivTest_q_9(DELAY,170) - dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) - redist18_fracYZero_uid15_fpDivTest_q_9 ( .xin(fracYZero_uid15_fpDivTest_q), .xout(redist18_fracYZero_uid15_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracYPostZ_uid56_fpDivTest(LOGICAL,55)@9 + 1 - assign fracYPostZ_uid56_fpDivTest_qi = redist18_fracYZero_uid15_fpDivTest_q_9_q | invY_uid54_fpDivTest_merged_bit_select_c; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracYPostZ_uid56_fpDivTest_delay ( .xin(fracYPostZ_uid56_fpDivTest_qi), .xout(fracYPostZ_uid56_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist5_fracYPostZ_uid56_fpDivTest_q_4(DELAY,157) - dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) - redist5_fracYPostZ_uid56_fpDivTest_q_4 ( .xin(fracYPostZ_uid56_fpDivTest_q), .xout(redist5_fracYPostZ_uid56_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // divValPreNormTrunc_uid66_fpDivTest(MUX,65)@13 - assign divValPreNormTrunc_uid66_fpDivTest_s = redist5_fracYPostZ_uid56_fpDivTest_q_4_q; - always @(divValPreNormTrunc_uid66_fpDivTest_s or en or osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b or oFracXSE_mergedSignalTM_uid63_fpDivTest_q) - begin - unique case (divValPreNormTrunc_uid66_fpDivTest_s) - 1'b0 : divValPreNormTrunc_uid66_fpDivTest_q = osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; - 1'b1 : divValPreNormTrunc_uid66_fpDivTest_q = oFracXSE_mergedSignalTM_uid63_fpDivTest_q; - default : divValPreNormTrunc_uid66_fpDivTest_q = 26'b0; - endcase - end - - // norm_uid67_fpDivTest(BITSELECT,66)@13 - assign norm_uid67_fpDivTest_b = divValPreNormTrunc_uid66_fpDivTest_q[25:25]; - - // rndOp_uid75_fpDivTest(BITJOIN,74)@13 - assign rndOp_uid75_fpDivTest_q = {norm_uid67_fpDivTest_b, paddingY_uid15_fpDivTest_q, VCC_q}; - - // cstBiasM1_uid6_fpDivTest(CONSTANT,5) - assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; - - // redist10_expXmY_uid47_fpDivTest_q_13_notEnable(LOGICAL,191) - assign redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q = ~ (en); - - // redist10_expXmY_uid47_fpDivTest_q_13_nor(LOGICAL,192) - assign redist10_expXmY_uid47_fpDivTest_q_13_nor_q = ~ (redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q | redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q); - - // redist10_expXmY_uid47_fpDivTest_q_13_mem_last(CONSTANT,188) - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q = 5'b01000; - - // redist10_expXmY_uid47_fpDivTest_q_13_cmp(LOGICAL,189) - assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_b = {1'b0, redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q}; - assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q == redist10_expXmY_uid47_fpDivTest_q_13_cmp_b ? 1'b1 : 1'b0; - - // redist10_expXmY_uid47_fpDivTest_q_13_cmpReg(REG,190) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; - end - end - - // redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena(REG,193) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= 1'b0; - end - else if (redist10_expXmY_uid47_fpDivTest_q_13_nor_q == 1'b1) - begin - redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; - end - end - - // redist10_expXmY_uid47_fpDivTest_q_13_enaAnd(LOGICAL,194) - assign redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q = redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q & en; - - // redist10_expXmY_uid47_fpDivTest_q_13_rdcnt(COUNTER,185) - // low=0, high=9, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= 4'd0; - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i == 4'd8) - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b1; - end - else - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; - end - if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq == 1'b1) - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd7); - end - else - begin - redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i[3:0]; - - // redist10_expXmY_uid47_fpDivTest_q_13_rdmux(MUX,186) - assign redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s = en; - always @(redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s or redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q or redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q) - begin - unique case (redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s) - 1'b0 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; - 1'b1 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; - default : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = 4'b0; - endcase - end - - // expXmY_uid47_fpDivTest(SUB,46)@0 + 1 - assign expXmY_uid47_fpDivTest_a = {1'b0, expX_uid9_fpDivTest_b}; - assign expXmY_uid47_fpDivTest_b = {1'b0, expY_uid12_fpDivTest_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - expXmY_uid47_fpDivTest_o <= 9'b0; - end - else if (en == 1'b1) - begin - expXmY_uid47_fpDivTest_o <= $unsigned(expXmY_uid47_fpDivTest_a) - $unsigned(expXmY_uid47_fpDivTest_b); - end - end - assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; - - // redist10_expXmY_uid47_fpDivTest_q_13_wraddr(REG,187) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= 4'b1001; - end - else - begin - redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; - end - end - - // redist10_expXmY_uid47_fpDivTest_q_13_mem(DUALMEM,184) - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ia = expXmY_uid47_fpDivTest_q; - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_aa = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ab = redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(9), - .widthad_a(4), - .numwords_a(10), - .width_b(9), - .widthad_b(4), - .numwords_b(10), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist10_expXmY_uid47_fpDivTest_q_13_mem_dmem ( - .clocken1(redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0), - .clock1(clk), - .address_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_aa), - .data_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_ia), - .wren_a(en[0]), - .address_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_ab), - .q_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist10_expXmY_uid47_fpDivTest_q_13_mem_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_iq[8:0]; - - // redist10_expXmY_uid47_fpDivTest_q_13_outputreg(DELAY,183) - dspba_delay_ver #( .width(9), .depth(1), .reset_kind("ASYNC") ) - redist10_expXmY_uid47_fpDivTest_q_13_outputreg ( .xin(redist10_expXmY_uid47_fpDivTest_q_13_mem_q), .xout(redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expR_uid48_fpDivTest(ADD,47)@13 - assign expR_uid48_fpDivTest_a = {{2{redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q[8]}}, redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q}; - assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; - assign expR_uid48_fpDivTest_o = $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); - assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; - - // divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@13 - assign divValPreNormHigh_uid68_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[24:0]; - assign divValPreNormHigh_uid68_fpDivTest_b = divValPreNormHigh_uid68_fpDivTest_in[24:1]; - - // divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@13 - assign divValPreNormLow_uid69_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[23:0]; - assign divValPreNormLow_uid69_fpDivTest_b = divValPreNormLow_uid69_fpDivTest_in[23:0]; - - // normFracRnd_uid70_fpDivTest(MUX,69)@13 - assign normFracRnd_uid70_fpDivTest_s = norm_uid67_fpDivTest_b; - always @(normFracRnd_uid70_fpDivTest_s or en or divValPreNormLow_uid69_fpDivTest_b or divValPreNormHigh_uid68_fpDivTest_b) - begin - unique case (normFracRnd_uid70_fpDivTest_s) - 1'b0 : normFracRnd_uid70_fpDivTest_q = divValPreNormLow_uid69_fpDivTest_b; - 1'b1 : normFracRnd_uid70_fpDivTest_q = divValPreNormHigh_uid68_fpDivTest_b; - default : normFracRnd_uid70_fpDivTest_q = 24'b0; - endcase - end - - // expFracRnd_uid71_fpDivTest(BITJOIN,70)@13 - assign expFracRnd_uid71_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid70_fpDivTest_q}; - - // expFracPostRnd_uid76_fpDivTest(ADD,75)@13 + 1 - assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid71_fpDivTest_q[33]}}, expFracRnd_uid71_fpDivTest_q}; - assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, rndOp_uid75_fpDivTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - expFracPostRnd_uid76_fpDivTest_o <= 36'b0; - end - else if (en == 1'b1) - begin - expFracPostRnd_uid76_fpDivTest_o <= $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); - end - end - assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[34:0]; - - // excRPreExc_uid79_fpDivTest(BITSELECT,78)@14 - assign excRPreExc_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[31:0]; - assign excRPreExc_uid79_fpDivTest_b = excRPreExc_uid79_fpDivTest_in[31:24]; - - // redist2_excRPreExc_uid79_fpDivTest_b_1(DELAY,154) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist2_excRPreExc_uid79_fpDivTest_b_1 ( .xin(excRPreExc_uid79_fpDivTest_b), .xout(redist2_excRPreExc_uid79_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@14 - assign invExpXIsMax_uid43_fpDivTest_q = ~ (redist13_expXIsMax_uid38_fpDivTest_q_14_q); - - // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@14 - assign InvExpXIsZero_uid44_fpDivTest_q = ~ (redist14_excZ_y_uid37_fpDivTest_q_14_q); - - // excR_y_uid45_fpDivTest(LOGICAL,44)@14 - assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; - - // excXIYR_uid93_fpDivTest(LOGICAL,92)@14 - assign excXIYR_uid93_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; - - // excXIYZ_uid92_fpDivTest(LOGICAL,91)@14 - assign excXIYZ_uid92_fpDivTest_q = excI_x_uid27_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - - // expRExt_uid80_fpDivTest(BITSELECT,79)@14 - assign expRExt_uid80_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[34:24]; - - // expOvf_uid84_fpDivTest(COMPARE,83)@14 - assign expOvf_uid84_fpDivTest_a = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; - assign expOvf_uid84_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; - assign expOvf_uid84_fpDivTest_o = $signed(expOvf_uid84_fpDivTest_a) - $signed(expOvf_uid84_fpDivTest_b); - assign expOvf_uid84_fpDivTest_n[0] = ~ (expOvf_uid84_fpDivTest_o[12]); - - // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@14 - assign invExpXIsMax_uid29_fpDivTest_q = ~ (redist16_expXIsMax_uid24_fpDivTest_q_14_q); - - // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@14 - assign InvExpXIsZero_uid30_fpDivTest_q = ~ (redist17_excZ_x_uid23_fpDivTest_q_14_q); - - // excR_x_uid31_fpDivTest(LOGICAL,30)@14 - assign excR_x_uid31_fpDivTest_q = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; - - // excXRYROvf_uid91_fpDivTest(LOGICAL,90)@14 - assign excXRYROvf_uid91_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid84_fpDivTest_n; - - // excXRYZ_uid90_fpDivTest(LOGICAL,89)@14 - assign excXRYZ_uid90_fpDivTest_q = excR_x_uid31_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; - - // excRInf_uid94_fpDivTest(LOGICAL,93)@14 - assign excRInf_uid94_fpDivTest_q = excXRYZ_uid90_fpDivTest_q | excXRYROvf_uid91_fpDivTest_q | excXIYZ_uid92_fpDivTest_q | excXIYR_uid93_fpDivTest_q; - - // xRegOrZero_uid87_fpDivTest(LOGICAL,86)@14 - assign xRegOrZero_uid87_fpDivTest_q = excR_x_uid31_fpDivTest_q | redist17_excZ_x_uid23_fpDivTest_q_14_q; - - // regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@14 - assign regOrZeroOverInf_uid88_fpDivTest_q = xRegOrZero_uid87_fpDivTest_q & excI_y_uid41_fpDivTest_q; - - // expUdf_uid81_fpDivTest(COMPARE,80)@14 - assign expUdf_uid81_fpDivTest_a = {12'b000000000000, GND_q}; - assign expUdf_uid81_fpDivTest_b = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; - assign expUdf_uid81_fpDivTest_o = $signed(expUdf_uid81_fpDivTest_a) - $signed(expUdf_uid81_fpDivTest_b); - assign expUdf_uid81_fpDivTest_n[0] = ~ (expUdf_uid81_fpDivTest_o[12]); - - // regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@14 - assign regOverRegWithUf_uid86_fpDivTest_q = expUdf_uid81_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; - - // zeroOverReg_uid85_fpDivTest(LOGICAL,84)@14 - assign zeroOverReg_uid85_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & excR_y_uid45_fpDivTest_q; - - // excRZero_uid89_fpDivTest(LOGICAL,88)@14 - assign excRZero_uid89_fpDivTest_q = zeroOverReg_uid85_fpDivTest_q | regOverRegWithUf_uid86_fpDivTest_q | regOrZeroOverInf_uid88_fpDivTest_q; - - // concExc_uid98_fpDivTest(BITJOIN,97)@14 - assign concExc_uid98_fpDivTest_q = {excRNaN_uid97_fpDivTest_q, excRInf_uid94_fpDivTest_q, excRZero_uid89_fpDivTest_q}; - - // excREnc_uid99_fpDivTest(LOOKUP,98)@14 + 1 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - excREnc_uid99_fpDivTest_q <= 2'b01; - end - else if (en == 1'b1) - begin - unique case (concExc_uid98_fpDivTest_q) - 3'b000 : excREnc_uid99_fpDivTest_q <= 2'b01; - 3'b001 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b010 : excREnc_uid99_fpDivTest_q <= 2'b10; - 3'b011 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b100 : excREnc_uid99_fpDivTest_q <= 2'b11; - 3'b101 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b110 : excREnc_uid99_fpDivTest_q <= 2'b00; - 3'b111 : excREnc_uid99_fpDivTest_q <= 2'b00; - default : begin - // unreachable - excREnc_uid99_fpDivTest_q <= 2'bxx; - end - endcase - end - end - - // expRPostExc_uid107_fpDivTest(MUX,106)@15 - assign expRPostExc_uid107_fpDivTest_s = excREnc_uid99_fpDivTest_q; - always @(expRPostExc_uid107_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or redist2_excRPreExc_uid79_fpDivTest_b_1_q or cstAllOWE_uid18_fpDivTest_q) - begin - unique case (expRPostExc_uid107_fpDivTest_s) - 2'b00 : expRPostExc_uid107_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; - 2'b01 : expRPostExc_uid107_fpDivTest_q = redist2_excRPreExc_uid79_fpDivTest_b_1_q; - 2'b10 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - 2'b11 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - default : expRPostExc_uid107_fpDivTest_q = 8'b0; - endcase - end - - // oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99) - assign oneFracRPostExc2_uid100_fpDivTest_q = 23'b00000000000000000000001; - - // fracRPreExc_uid78_fpDivTest(BITSELECT,77)@14 - assign fracRPreExc_uid78_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[23:0]; - assign fracRPreExc_uid78_fpDivTest_b = fracRPreExc_uid78_fpDivTest_in[23:1]; - - // redist3_fracRPreExc_uid78_fpDivTest_b_1(DELAY,155) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist3_fracRPreExc_uid78_fpDivTest_b_1 ( .xin(fracRPreExc_uid78_fpDivTest_b), .xout(redist3_fracRPreExc_uid78_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracRPostExc_uid103_fpDivTest(MUX,102)@15 - assign fracRPostExc_uid103_fpDivTest_s = excREnc_uid99_fpDivTest_q; - always @(fracRPostExc_uid103_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or redist3_fracRPreExc_uid78_fpDivTest_b_1_q or oneFracRPostExc2_uid100_fpDivTest_q) - begin - unique case (fracRPostExc_uid103_fpDivTest_s) - 2'b00 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b01 : fracRPostExc_uid103_fpDivTest_q = redist3_fracRPreExc_uid78_fpDivTest_b_1_q; - 2'b10 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b11 : fracRPostExc_uid103_fpDivTest_q = oneFracRPostExc2_uid100_fpDivTest_q; - default : fracRPostExc_uid103_fpDivTest_q = 23'b0; - endcase - end - - // divR_uid110_fpDivTest(BITJOIN,109)@15 - assign divR_uid110_fpDivTest_q = {sRPostExc_uid109_fpDivTest_q, expRPostExc_uid107_fpDivTest_q, fracRPostExc_uid103_fpDivTest_q}; - - // xOut(GPOUT,4)@15 - assign q = divR_uid110_fpDivTest_q; - -endmodule diff --git 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-:0201DB00011E03 -:0201DC00011C04 -:0201DD00011A05 -:0201DE00011905 -:0201DF00011805 -:0201E000011804 -:0201E100011803 -:0201E200011802 -:0201E300011603 -:0201E400011503 -:0201E500011403 -:0201E600011303 -:0201E700011302 -:0201E800011400 -:0201E9000114FF -:0201EA00011002 -:0201EB00011100 -:0201EC00010F01 -:0201ED00010E01 -:0201EE00010D01 -:0201EF00010C01 -:0201F000010B01 -:0201F100010902 -:0201F200010BFF -:0201F300010801 -:0201F400010800 -:0201F500010601 -:0201F600010600 -:0201F7000107FE -:0201F8000105FF -:0201F900010300 -:0201FA00010200 -:0201FB000102FF -:0201FC000103FD -:0201FD000102FD -:0201FE000100FE -:0201FF000100FD -:00000001ff diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv b/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv deleted file mode 100644 index a30384ef..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv +++ /dev/null @@ -1,74 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fmadd -// SystemVerilog created on Mon Jan 18 04:15:46 2021 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fmadd ( - input wire [31:0] a, - input wire [31:0] b, - input wire [31:0] c, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [31:0] fpMultAddTest_impl_ax0; - wire [31:0] fpMultAddTest_impl_ay0; - wire [31:0] fpMultAddTest_impl_az0; - wire [31:0] fpMultAddTest_impl_q0; - wire fpMultAddTest_impl_reset0; - wire fpMultAddTest_impl_fpMultAddTest_impl_ena0; - - - // fpMultAddTest_impl(FPCOLUMN,5)@0 - // out q0@4 - assign fpMultAddTest_impl_ax0 = c; - assign fpMultAddTest_impl_ay0 = b; - assign fpMultAddTest_impl_az0 = a; - assign fpMultAddTest_impl_reset0 = areset; - assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0]; - twentynm_fp_mac #( - .operation_mode("sp_mult_add"), - .use_chainin("false"), - .ax_clock("0"), - .ay_clock("0"), - .az_clock("0"), - .mult_pipeline_clock("0"), - .adder_input_clock("0"), - .ax_chainin_pl_clock("0"), - .output_clock("0") - ) fpMultAddTest_impl_DSP0 ( - .aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }), - .clk({1'b0,1'b0,clk}), - .ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }), - .ax(fpMultAddTest_impl_ax0), - .ay(fpMultAddTest_impl_ay0), - .az(fpMultAddTest_impl_az0), - .resulta(fpMultAddTest_impl_q0), - .accumulate(), - .chainin(), - .chainout() - ); - - // xOut(GPOUT,4)@4 - assign q = fpMultAddTest_impl_q0; - -endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv deleted file mode 100644 index 80083328..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv +++ /dev/null @@ -1,1128 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fsqrt -// SystemVerilog created on Mon Jan 18 04:15:46 2021 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fsqrt ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] expX_uid6_fpSqrtTest_b; - wire [0:0] signX_uid7_fpSqrtTest_b; - wire [7:0] cstAllOWE_uid8_fpSqrtTest_q; - wire [22:0] cstZeroWF_uid9_fpSqrtTest_q; - wire [7:0] cstAllZWE_uid10_fpSqrtTest_q; - wire [22:0] frac_x_uid12_fpSqrtTest_b; - wire [0:0] excZ_x_uid13_fpSqrtTest_qi; - reg [0:0] excZ_x_uid13_fpSqrtTest_q; - wire [0:0] expXIsMax_uid14_fpSqrtTest_qi; - reg [0:0] expXIsMax_uid14_fpSqrtTest_q; - wire [0:0] fracXIsZero_uid15_fpSqrtTest_qi; - reg [0:0] fracXIsZero_uid15_fpSqrtTest_q; - wire [0:0] fracXIsNotZero_uid16_fpSqrtTest_q; - wire [0:0] excI_x_uid17_fpSqrtTest_q; - wire [0:0] excN_x_uid18_fpSqrtTest_q; - wire [0:0] invExpXIsMax_uid19_fpSqrtTest_q; - wire [0:0] InvExpXIsZero_uid20_fpSqrtTest_q; - wire [0:0] excR_x_uid21_fpSqrtTest_q; - wire [7:0] sBias_uid22_fpSqrtTest_q; - wire [8:0] expEvenSig_uid24_fpSqrtTest_a; - wire [8:0] expEvenSig_uid24_fpSqrtTest_b; - logic [8:0] expEvenSig_uid24_fpSqrtTest_o; - wire [8:0] expEvenSig_uid24_fpSqrtTest_q; - wire [7:0] expREven_uid25_fpSqrtTest_b; - wire [7:0] sBiasM1_uid26_fpSqrtTest_q; - wire [8:0] expOddSig_uid27_fpSqrtTest_a; - wire [8:0] expOddSig_uid27_fpSqrtTest_b; - logic [8:0] expOddSig_uid27_fpSqrtTest_o; - wire [8:0] expOddSig_uid27_fpSqrtTest_q; - wire [7:0] expROdd_uid28_fpSqrtTest_b; - wire [0:0] expX0PS_uid29_fpSqrtTest_in; - wire [0:0] expX0PS_uid29_fpSqrtTest_b; - wire [0:0] expOddSelect_uid30_fpSqrtTest_q; - wire [0:0] expRMux_uid31_fpSqrtTest_s; - reg [7:0] expRMux_uid31_fpSqrtTest_q; - wire [23:0] addrFull_uid33_fpSqrtTest_q; - wire [7:0] yAddr_uid35_fpSqrtTest_b; - wire [15:0] yForPe_uid36_fpSqrtTest_in; - wire [15:0] yForPe_uid36_fpSqrtTest_b; - wire [30:0] expInc_uid38_fpSqrtTest_in; - wire [0:0] expInc_uid38_fpSqrtTest_b; - wire [28:0] fracRPostProcessings_uid39_fpSqrtTest_in; - wire [22:0] fracRPostProcessings_uid39_fpSqrtTest_b; - wire [8:0] expR_uid40_fpSqrtTest_a; - wire [8:0] expR_uid40_fpSqrtTest_b; - logic [8:0] expR_uid40_fpSqrtTest_o; - wire [8:0] expR_uid40_fpSqrtTest_q; - wire [0:0] invSignX_uid41_fpSqrtTest_q; - wire [0:0] inInfAndNotNeg_uid42_fpSqrtTest_q; - wire [0:0] minReg_uid43_fpSqrtTest_q; - wire [0:0] minInf_uid44_fpSqrtTest_q; - wire [0:0] excRNaN_uid45_fpSqrtTest_q; - wire [2:0] excConc_uid46_fpSqrtTest_q; - wire [3:0] fracSelIn_uid47_fpSqrtTest_q; - reg [1:0] fracSel_uid48_fpSqrtTest_q; - wire [7:0] expRR_uid51_fpSqrtTest_in; - wire [7:0] expRR_uid51_fpSqrtTest_b; - wire [1:0] expRPostExc_uid53_fpSqrtTest_s; - reg [7:0] expRPostExc_uid53_fpSqrtTest_q; - wire [22:0] fracNaN_uid54_fpSqrtTest_q; - wire [1:0] fracRPostExc_uid58_fpSqrtTest_s; - reg [22:0] fracRPostExc_uid58_fpSqrtTest_q; - wire [0:0] negZero_uid59_fpSqrtTest_qi; - reg [0:0] negZero_uid59_fpSqrtTest_q; - wire [31:0] RSqrt_uid60_fpSqrtTest_q; - wire [11:0] yT1_uid74_invPolyEval_b; - wire [0:0] lowRangeB_uid76_invPolyEval_in; - wire [0:0] lowRangeB_uid76_invPolyEval_b; - wire [11:0] highBBits_uid77_invPolyEval_b; - wire [21:0] s1sumAHighB_uid78_invPolyEval_a; - wire [21:0] s1sumAHighB_uid78_invPolyEval_b; - logic [21:0] s1sumAHighB_uid78_invPolyEval_o; - wire [21:0] s1sumAHighB_uid78_invPolyEval_q; - wire [22:0] s1_uid79_invPolyEval_q; - wire [1:0] lowRangeB_uid82_invPolyEval_in; - wire [1:0] lowRangeB_uid82_invPolyEval_b; - wire [21:0] highBBits_uid83_invPolyEval_b; - wire [29:0] s2sumAHighB_uid84_invPolyEval_a; - wire [29:0] s2sumAHighB_uid84_invPolyEval_b; - logic [29:0] s2sumAHighB_uid84_invPolyEval_o; - wire [29:0] s2sumAHighB_uid84_invPolyEval_q; - wire [31:0] s2_uid85_invPolyEval_q; - wire [12:0] osig_uid88_pT1_uid75_invPolyEval_b; - wire [23:0] osig_uid91_pT2_uid81_invPolyEval_b; - wire memoryC0_uid62_sqrtTables_lutmem_reset0; - wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ia; - wire [7:0] memoryC0_uid62_sqrtTables_lutmem_aa; - wire [7:0] memoryC0_uid62_sqrtTables_lutmem_ab; - wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ir; - wire [28:0] memoryC0_uid62_sqrtTables_lutmem_r; - wire memoryC1_uid65_sqrtTables_lutmem_reset0; - wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ia; - wire [7:0] memoryC1_uid65_sqrtTables_lutmem_aa; - wire [7:0] memoryC1_uid65_sqrtTables_lutmem_ab; - wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ir; - wire [20:0] memoryC1_uid65_sqrtTables_lutmem_r; - wire memoryC2_uid68_sqrtTables_lutmem_reset0; - wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ia; - wire [7:0] memoryC2_uid68_sqrtTables_lutmem_aa; - wire [7:0] memoryC2_uid68_sqrtTables_lutmem_ab; - wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ir; - wire [11:0] memoryC2_uid68_sqrtTables_lutmem_r; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 [0:0]; - wire signed [12:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_l [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_p [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_u [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_w [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_x [0:0]; - wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_y [0:0]; - reg signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_s [0:0]; - wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_qq; - wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_q; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1; - wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_reset; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 [0:0]; - (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 [0:0]; - wire signed [16:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_l [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_p [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_u [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_w [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_x [0:0]; - wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_y [0:0]; - reg signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_s [0:0]; - wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_qq; - wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_q; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1; - wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2; - reg [0:0] redist0_lowRangeB_uid76_invPolyEval_b_1_q; - reg [0:0] redist1_negZero_uid59_fpSqrtTest_q_9_q; - reg [1:0] redist2_fracSel_uid48_fpSqrtTest_q_9_q; - reg [22:0] redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; - reg [0:0] redist4_expInc_uid38_fpSqrtTest_b_1_q; - reg [15:0] redist5_yForPe_uid36_fpSqrtTest_b_2_q; - reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_3_q; - reg [7:0] redist8_yAddr_uid35_fpSqrtTest_b_7_q; - reg [0:0] redist10_signX_uid7_fpSqrtTest_b_1_q; - wire redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; - (* preserve *) reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i; - (* preserve *) reg redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s; - reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; - reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; - wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; - reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q; - (* preserve_syn_only *) reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q; - reg [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q; - wire redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0; - wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia; - wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa; - wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab; - wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq; - wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q; - wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; - (* preserve *) reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i; - (* preserve *) reg redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s; - reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; - reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; - wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q; - wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; - reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q; - (* preserve_syn_only *) reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q; - wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q; - - - // signX_uid7_fpSqrtTest(BITSELECT,6)@0 - assign signX_uid7_fpSqrtTest_b = a[31:31]; - - // redist10_signX_uid7_fpSqrtTest_b_1(DELAY,107) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist10_signX_uid7_fpSqrtTest_b_1 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist10_signX_uid7_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) - assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; - - // expX_uid6_fpSqrtTest(BITSELECT,5)@0 - assign expX_uid6_fpSqrtTest_b = a[30:23]; - - // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@0 + 1 - assign excZ_x_uid13_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // negZero_uid59_fpSqrtTest(LOGICAL,58)@1 + 1 - assign negZero_uid59_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - negZero_uid59_fpSqrtTest_delay ( .xin(negZero_uid59_fpSqrtTest_qi), .xout(negZero_uid59_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist1_negZero_uid59_fpSqrtTest_q_9(DELAY,98) - dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) - redist1_negZero_uid59_fpSqrtTest_q_9 ( .xin(negZero_uid59_fpSqrtTest_q), .xout(redist1_negZero_uid59_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) - assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; - - // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 - assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; - assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; - - // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 - assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); - - // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 - assign frac_x_uid12_fpSqrtTest_b = a[22:0]; - - // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 - assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; - - // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 - assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; - - // memoryC2_uid68_sqrtTables_lutmem(DUALMEM,94)@0 + 2 - // in j@20000000 - assign memoryC2_uid68_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; - assign memoryC2_uid68_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(12), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC2_uid68_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC2_uid68_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC2_uid68_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC2_uid68_sqrtTables_lutmem_aa), - .q_a(memoryC2_uid68_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC2_uid68_sqrtTables_lutmem_r = memoryC2_uid68_sqrtTables_lutmem_ir[11:0]; - - // yForPe_uid36_fpSqrtTest(BITSELECT,35)@0 - assign yForPe_uid36_fpSqrtTest_in = frac_x_uid12_fpSqrtTest_b[15:0]; - assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; - - // redist5_yForPe_uid36_fpSqrtTest_b_2(DELAY,102) - dspba_delay_ver #( .width(16), .depth(2), .reset_kind("ASYNC") ) - redist5_yForPe_uid36_fpSqrtTest_b_2 ( .xin(yForPe_uid36_fpSqrtTest_b), .xout(redist5_yForPe_uid36_fpSqrtTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // yT1_uid74_invPolyEval(BITSELECT,73)@2 - assign yT1_uid74_invPolyEval_b = redist5_yForPe_uid36_fpSqrtTest_b_2_q[15:4]; - - // prodXY_uid87_pT1_uid75_invPolyEval_cma(CHAINMULTADD,95)@2 + 3 - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_reset = areset; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid87_pT1_uid75_invPolyEval_cma_a1[0][11:0]}); - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] * prodXY_uid87_pT1_uid75_invPolyEval_cma_c1[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0][24:0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0]; - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a0[0] <= yT1_uid74_invPolyEval_b; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c0[0] <= memoryC2_uid68_sqrtTables_lutmem_r; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_a0; - prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0] <= prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid87_pT1_uid75_invPolyEval_cma_delay ( .xin(prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid87_pT1_uid75_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid87_pT1_uid75_invPolyEval_cma_q = prodXY_uid87_pT1_uid75_invPolyEval_cma_qq[23:0]; - - // osig_uid88_pT1_uid75_invPolyEval(BITSELECT,87)@5 - assign osig_uid88_pT1_uid75_invPolyEval_b = prodXY_uid87_pT1_uid75_invPolyEval_cma_q[23:11]; - - // highBBits_uid77_invPolyEval(BITSELECT,76)@5 - assign highBBits_uid77_invPolyEval_b = osig_uid88_pT1_uid75_invPolyEval_b[12:1]; - - // redist7_yAddr_uid35_fpSqrtTest_b_3(DELAY,104) - dspba_delay_ver #( .width(8), .depth(3), .reset_kind("ASYNC") ) - redist7_yAddr_uid35_fpSqrtTest_b_3 ( .xin(yAddr_uid35_fpSqrtTest_b), .xout(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC1_uid65_sqrtTables_lutmem(DUALMEM,93)@3 + 2 - // in j@20000000 - assign memoryC1_uid65_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_3_q; - assign memoryC1_uid65_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(21), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC1_uid65_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC1_uid65_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC1_uid65_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC1_uid65_sqrtTables_lutmem_aa), - .q_a(memoryC1_uid65_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC1_uid65_sqrtTables_lutmem_r = memoryC1_uid65_sqrtTables_lutmem_ir[20:0]; - - // s1sumAHighB_uid78_invPolyEval(ADD,77)@5 + 1 - assign s1sumAHighB_uid78_invPolyEval_a = {{1{memoryC1_uid65_sqrtTables_lutmem_r[20]}}, memoryC1_uid65_sqrtTables_lutmem_r}; - assign s1sumAHighB_uid78_invPolyEval_b = {{10{highBBits_uid77_invPolyEval_b[11]}}, highBBits_uid77_invPolyEval_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - s1sumAHighB_uid78_invPolyEval_o <= 22'b0; - end - else if (en == 1'b1) - begin - s1sumAHighB_uid78_invPolyEval_o <= $signed(s1sumAHighB_uid78_invPolyEval_a) + $signed(s1sumAHighB_uid78_invPolyEval_b); - end - end - assign s1sumAHighB_uid78_invPolyEval_q = s1sumAHighB_uid78_invPolyEval_o[21:0]; - - // lowRangeB_uid76_invPolyEval(BITSELECT,75)@5 - assign lowRangeB_uid76_invPolyEval_in = osig_uid88_pT1_uid75_invPolyEval_b[0:0]; - assign lowRangeB_uid76_invPolyEval_b = lowRangeB_uid76_invPolyEval_in[0:0]; - - // redist0_lowRangeB_uid76_invPolyEval_b_1(DELAY,97) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist0_lowRangeB_uid76_invPolyEval_b_1 ( .xin(lowRangeB_uid76_invPolyEval_b), .xout(redist0_lowRangeB_uid76_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // s1_uid79_invPolyEval(BITJOIN,78)@6 - assign s1_uid79_invPolyEval_q = {s1sumAHighB_uid78_invPolyEval_q, redist0_lowRangeB_uid76_invPolyEval_b_1_q}; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable(LOGICAL,115) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q = ~ (en); - - // redist6_yForPe_uid36_fpSqrtTest_b_6_nor(LOGICAL,116) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q = ~ (redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q | redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q); - - // redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last(CONSTANT,112) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q = 2'b01; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_cmp(LOGICAL,113) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q == redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q ? 1'b1 : 1'b0; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg(REG,114) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena(REG,117) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= 1'b0; - end - else if (redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd(LOGICAL,118) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q = redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q & en; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt(COUNTER,109) - // low=0, high=2, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= 2'd0; - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i == 2'd1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b1; - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; - end - if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd2); - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd1); - end - end - end - assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i[1:0]; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux(MUX,110) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s = en; - always @(redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s or redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q or redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q) - begin - unique case (redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s) - 1'b0 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; - 1'b1 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; - default : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = 2'b0; - endcase - end - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr(REG,111) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= 2'b10; - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_6_mem(DUALMEM,108) - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia = redist5_yForPe_uid36_fpSqrtTest_b_2_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab = redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(16), - .widthad_a(2), - .numwords_a(3), - .width_b(16), - .widthad_b(2), - .numwords_b(3), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist6_yForPe_uid36_fpSqrtTest_b_6_mem_dmem ( - .clocken1(redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0), - .clock1(clk), - .address_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa), - .data_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia), - .wren_a(en[0]), - .address_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab), - .q_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq[15:0]; - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // prodXY_uid90_pT2_uid81_invPolyEval_cma(CHAINMULTADD,96)@6 + 3 - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_reset = areset; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 = en[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid90_pT2_uid81_invPolyEval_cma_a1[0][15:0]}); - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] * prodXY_uid90_pT2_uid81_invPolyEval_cma_c1[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0][39:0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0]; - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0]; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 <= '{default: '0}; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 <= '{default: '0}; - end - else - begin - if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 == 1'b1) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a0[0] <= redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c0[0] <= s1_uid79_invPolyEval_q; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= '{default: '0}; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= '{default: '0}; - end - else - begin - if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 == 1'b1) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_a0; - prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_c0; - end - end - end - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_s <= '{default: '0}; - end - else - begin - if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 == 1'b1) - begin - prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0] <= prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0]; - end - end - end - dspba_delay_ver #( .width(39), .depth(0), .reset_kind("ASYNC") ) - prodXY_uid90_pT2_uid81_invPolyEval_cma_delay ( .xin(prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0][38:0]), .xout(prodXY_uid90_pT2_uid81_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid90_pT2_uid81_invPolyEval_cma_q = prodXY_uid90_pT2_uid81_invPolyEval_cma_qq[38:0]; - - // osig_uid91_pT2_uid81_invPolyEval(BITSELECT,90)@9 - assign osig_uid91_pT2_uid81_invPolyEval_b = prodXY_uid90_pT2_uid81_invPolyEval_cma_q[38:15]; - - // highBBits_uid83_invPolyEval(BITSELECT,82)@9 - assign highBBits_uid83_invPolyEval_b = osig_uid91_pT2_uid81_invPolyEval_b[23:2]; - - // redist8_yAddr_uid35_fpSqrtTest_b_7(DELAY,105) - dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) - redist8_yAddr_uid35_fpSqrtTest_b_7 ( .xin(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .xout(redist8_yAddr_uid35_fpSqrtTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // memoryC0_uid62_sqrtTables_lutmem(DUALMEM,92)@7 + 2 - // in j@20000000 - assign memoryC0_uid62_sqrtTables_lutmem_aa = redist8_yAddr_uid35_fpSqrtTest_b_7_q; - assign memoryC0_uid62_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(29), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_aclr_a("CLEAR0"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Arria 10") - ) memoryC0_uid62_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .aclr0(memoryC0_uid62_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC0_uid62_sqrtTables_lutmem_aa), - .q_a(memoryC0_uid62_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC0_uid62_sqrtTables_lutmem_r = memoryC0_uid62_sqrtTables_lutmem_ir[28:0]; - - // s2sumAHighB_uid84_invPolyEval(ADD,83)@9 - assign s2sumAHighB_uid84_invPolyEval_a = {{1{memoryC0_uid62_sqrtTables_lutmem_r[28]}}, memoryC0_uid62_sqrtTables_lutmem_r}; - assign s2sumAHighB_uid84_invPolyEval_b = {{8{highBBits_uid83_invPolyEval_b[21]}}, highBBits_uid83_invPolyEval_b}; - assign s2sumAHighB_uid84_invPolyEval_o = $signed(s2sumAHighB_uid84_invPolyEval_a) + $signed(s2sumAHighB_uid84_invPolyEval_b); - assign s2sumAHighB_uid84_invPolyEval_q = s2sumAHighB_uid84_invPolyEval_o[29:0]; - - // lowRangeB_uid82_invPolyEval(BITSELECT,81)@9 - assign lowRangeB_uid82_invPolyEval_in = osig_uid91_pT2_uid81_invPolyEval_b[1:0]; - assign lowRangeB_uid82_invPolyEval_b = lowRangeB_uid82_invPolyEval_in[1:0]; - - // s2_uid85_invPolyEval(BITJOIN,84)@9 - assign s2_uid85_invPolyEval_q = {s2sumAHighB_uid84_invPolyEval_q, lowRangeB_uid82_invPolyEval_b}; - - // expInc_uid38_fpSqrtTest(BITSELECT,37)@9 - assign expInc_uid38_fpSqrtTest_in = s2_uid85_invPolyEval_q[30:0]; - assign expInc_uid38_fpSqrtTest_b = expInc_uid38_fpSqrtTest_in[30:30]; - - // redist4_expInc_uid38_fpSqrtTest_b_1(DELAY,101) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist4_expInc_uid38_fpSqrtTest_b_1 ( .xin(expInc_uid38_fpSqrtTest_b), .xout(redist4_expInc_uid38_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable(LOGICAL,127) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q = ~ (en); - - // redist9_expRMux_uid31_fpSqrtTest_q_10_nor(LOGICAL,128) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q = ~ (redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q | redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q); - - // redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last(CONSTANT,124) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q = 4'b0101; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_cmp(LOGICAL,125) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q}; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q == redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b ? 1'b1 : 1'b0; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg(REG,126) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena(REG,129) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= 1'b0; - end - else if (redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q == 1'b1) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd(LOGICAL,130) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q = redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q & en; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt(COUNTER,121) - // low=0, high=6, step=1, init=0 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= 3'd0; - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i == 3'd5) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b1; - end - else - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; - end - if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq == 1'b1) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd2); - end - else - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i[2:0]; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux(MUX,122) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s = en; - always @(redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s or redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q or redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q) - begin - unique case (redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s) - 1'b0 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; - 1'b1 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; - default : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = 3'b0; - endcase - end - - // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) - assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; - - // expOddSig_uid27_fpSqrtTest(ADD,26)@0 - assign expOddSig_uid27_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; - assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; - assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); - assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; - - // expROdd_uid28_fpSqrtTest(BITSELECT,27)@0 - assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; - - // sBias_uid22_fpSqrtTest(CONSTANT,21) - assign sBias_uid22_fpSqrtTest_q = 8'b01111111; - - // expEvenSig_uid24_fpSqrtTest(ADD,23)@0 - assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; - assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; - assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); - assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; - - // expREven_uid25_fpSqrtTest(BITSELECT,24)@0 - assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; - - // expRMux_uid31_fpSqrtTest(MUX,30)@0 + 1 - assign expRMux_uid31_fpSqrtTest_s = expOddSelect_uid30_fpSqrtTest_q; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - expRMux_uid31_fpSqrtTest_q <= 8'b0; - end - else if (en == 1'b1) - begin - unique case (expRMux_uid31_fpSqrtTest_s) - 1'b0 : expRMux_uid31_fpSqrtTest_q <= expREven_uid25_fpSqrtTest_b; - 1'b1 : expRMux_uid31_fpSqrtTest_q <= expROdd_uid28_fpSqrtTest_b; - default : expRMux_uid31_fpSqrtTest_q <= 8'b0; - endcase - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr(REG,123) - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= 3'b110; - end - else - begin - redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_10_mem(DUALMEM,120) - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia = expRMux_uid31_fpSqrtTest_q; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab = redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(3), - .numwords_a(7), - .width_b(8), - .widthad_b(3), - .numwords_b(7), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_aclr_b("CLEAR1"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Arria 10") - ) redist9_expRMux_uid31_fpSqrtTest_q_10_mem_dmem ( - .clocken1(redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q[0]), - .clocken0(VCC_q[0]), - .clock0(clk), - .aclr1(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0), - .clock1(clk), - .address_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa), - .data_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia), - .wren_a(en[0]), - .address_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab), - .q_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .sclr(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq[7:0]; - - // redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg(DELAY,119) - dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) - redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg ( .xin(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q), .xout(redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expR_uid40_fpSqrtTest(ADD,39)@10 - assign expR_uid40_fpSqrtTest_a = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q}; - assign expR_uid40_fpSqrtTest_b = {8'b00000000, redist4_expInc_uid38_fpSqrtTest_b_1_q}; - assign expR_uid40_fpSqrtTest_o = $unsigned(expR_uid40_fpSqrtTest_a) + $unsigned(expR_uid40_fpSqrtTest_b); - assign expR_uid40_fpSqrtTest_q = expR_uid40_fpSqrtTest_o[8:0]; - - // expRR_uid51_fpSqrtTest(BITSELECT,50)@10 - assign expRR_uid51_fpSqrtTest_in = expR_uid40_fpSqrtTest_q[7:0]; - assign expRR_uid51_fpSqrtTest_b = expRR_uid51_fpSqrtTest_in[7:0]; - - // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@0 + 1 - assign expXIsMax_uid14_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@1 - assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); - - // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@1 - assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); - - // excR_x_uid21_fpSqrtTest(LOGICAL,20)@1 - assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; - - // minReg_uid43_fpSqrtTest(LOGICAL,42)@1 - assign minReg_uid43_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; - - // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) - assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@0 + 1 - assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == frac_x_uid12_fpSqrtTest_b ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid17_fpSqrtTest(LOGICAL,16)@1 - assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; - - // minInf_uid44_fpSqrtTest(LOGICAL,43)@1 - assign minInf_uid44_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; - - // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@1 - assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); - - // excN_x_uid18_fpSqrtTest(LOGICAL,17)@1 - assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; - - // excRNaN_uid45_fpSqrtTest(LOGICAL,44)@1 - assign excRNaN_uid45_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid44_fpSqrtTest_q | minReg_uid43_fpSqrtTest_q; - - // invSignX_uid41_fpSqrtTest(LOGICAL,40)@1 - assign invSignX_uid41_fpSqrtTest_q = ~ (redist10_signX_uid7_fpSqrtTest_b_1_q); - - // inInfAndNotNeg_uid42_fpSqrtTest(LOGICAL,41)@1 - assign inInfAndNotNeg_uid42_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid41_fpSqrtTest_q; - - // excConc_uid46_fpSqrtTest(BITJOIN,45)@1 - assign excConc_uid46_fpSqrtTest_q = {excRNaN_uid45_fpSqrtTest_q, inInfAndNotNeg_uid42_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; - - // fracSelIn_uid47_fpSqrtTest(BITJOIN,46)@1 - assign fracSelIn_uid47_fpSqrtTest_q = {redist10_signX_uid7_fpSqrtTest_b_1_q, excConc_uid46_fpSqrtTest_q}; - - // fracSel_uid48_fpSqrtTest(LOOKUP,47)@1 + 1 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - fracSel_uid48_fpSqrtTest_q <= 2'b01; - end - else if (en == 1'b1) - begin - unique case (fracSelIn_uid47_fpSqrtTest_q) - 4'b0000 : fracSel_uid48_fpSqrtTest_q <= 2'b01; - 4'b0001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b0010 : fracSel_uid48_fpSqrtTest_q <= 2'b10; - 4'b0011 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b0100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b0101 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b0110 : fracSel_uid48_fpSqrtTest_q <= 2'b10; - 4'b0111 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b1000 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; - 4'b1010 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1011 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1101 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1110 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - 4'b1111 : fracSel_uid48_fpSqrtTest_q <= 2'b11; - default : begin - // unreachable - fracSel_uid48_fpSqrtTest_q <= 2'bxx; - end - endcase - end - end - - // redist2_fracSel_uid48_fpSqrtTest_q_9(DELAY,99) - dspba_delay_ver #( .width(2), .depth(8), .reset_kind("ASYNC") ) - redist2_fracSel_uid48_fpSqrtTest_q_9 ( .xin(fracSel_uid48_fpSqrtTest_q), .xout(redist2_fracSel_uid48_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expRPostExc_uid53_fpSqrtTest(MUX,52)@10 - assign expRPostExc_uid53_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; - always @(expRPostExc_uid53_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid51_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) - begin - unique case (expRPostExc_uid53_fpSqrtTest_s) - 2'b00 : expRPostExc_uid53_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; - 2'b01 : expRPostExc_uid53_fpSqrtTest_q = expRR_uid51_fpSqrtTest_b; - 2'b10 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - 2'b11 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - default : expRPostExc_uid53_fpSqrtTest_q = 8'b0; - endcase - end - - // fracNaN_uid54_fpSqrtTest(CONSTANT,53) - assign fracNaN_uid54_fpSqrtTest_q = 23'b00000000000000000000001; - - // fracRPostProcessings_uid39_fpSqrtTest(BITSELECT,38)@9 - assign fracRPostProcessings_uid39_fpSqrtTest_in = s2_uid85_invPolyEval_q[28:0]; - assign fracRPostProcessings_uid39_fpSqrtTest_b = fracRPostProcessings_uid39_fpSqrtTest_in[28:6]; - - // redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1(DELAY,100) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1 ( .xin(fracRPostProcessings_uid39_fpSqrtTest_b), .xout(redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracRPostExc_uid58_fpSqrtTest(MUX,57)@10 - assign fracRPostExc_uid58_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; - always @(fracRPostExc_uid58_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q or fracNaN_uid54_fpSqrtTest_q) - begin - unique case (fracRPostExc_uid58_fpSqrtTest_s) - 2'b00 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b01 : fracRPostExc_uid58_fpSqrtTest_q = redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; - 2'b10 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b11 : fracRPostExc_uid58_fpSqrtTest_q = fracNaN_uid54_fpSqrtTest_q; - default : fracRPostExc_uid58_fpSqrtTest_q = 23'b0; - endcase - end - - // RSqrt_uid60_fpSqrtTest(BITJOIN,59)@10 - assign RSqrt_uid60_fpSqrtTest_q = {redist1_negZero_uid59_fpSqrtTest_q_9_q, expRPostExc_uid53_fpSqrtTest_q, fracRPostExc_uid58_fpSqrtTest_q}; - - // xOut(GPOUT,4)@10 - assign q = RSqrt_uid60_fpSqrtTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex b/hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex deleted file mode 100644 index dacc8b55..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex +++ /dev/null @@ -1,258 +0,0 @@ -:020000040000FA -:0400000008000004F0 -:040001000807FC08E8 -:04000200080FF024CF -:040003000817DC6F8F -:04000400081FC0FF12 -:0400050008279DEC3F -:04000600082F734C00 -:040007000837413342 -:04000800083F07B7EF -:040009000846C6EEF1 -:04000A00084E7EEB33 -:04000B0008562FC2A2 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-:0200F1000DD030 -:0200F2000DD22D -:0200F3000DD826 -:0200F4000DDC21 -:0200F5000DDC20 -:0200F6000DDE1D -:0200F7000DE416 -:0200F8000DEC0D -:0200F9000DEC0C -:0200FA000DEE09 -:0200FB000DF600 -:0200FC000DF401 -:0200FD000DF6FE -:0200FE000DF8FB -:0200FF000E02EF -:00000001ff diff --git a/hw/rtl/fp_cores/altera/arria10/acl_gen.log b/hw/rtl/fp_cores/altera/arria10/acl_gen.log deleted file mode 100644 index ca4112b7..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_gen.log +++ /dev/null @@ -1,90 +0,0 @@ -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fmadd - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 4 cycle(s) -@@start -@name FPMultAdd@ -@latency 4@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method multadd@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@inPort 2 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=23 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fdiv - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3 -The pipeline depth of the block is 15 cycle(s) -@@start -@name FPDiv@ -@latency 15@ -@LUT 539@ -@DSP 5@ -@RAMBits 32768@ -@RAMBlockUsage 3@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method polynomial approximation@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Faithful rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fsqrt - Frequency 250MHz - Deployment FPGA Arria10 -Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3 -The pipeline depth of the block is 10 cycle(s) -@@start -@name FPSqrt@ -@latency 10@ -@LUT 271@ -@DSP 3@ -@RAMBits 15872@ -@RAMBlockUsage 3@ -@enable 1@ -@subnormals 0@ -@error 1.00@ -@rounding NA@ -@method polynomial approximation@ -@inPort 0 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end diff --git a/hw/rtl/fp_cores/altera/arria10/acl_gen.sh b/hw/rtl/fp_cores/altera/arria10/acl_gen.sh deleted file mode 100755 index feafed64..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_gen.sh +++ /dev/null @@ -1,33 +0,0 @@ -#!/bin/bash - -FAMILY=Arria10 -PREFIX=acl - -CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 - -OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -faithfulRounding -noChanValid -enable -speedgrade 2" - -export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH - -CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" - -EXP_BITS=8 -MAN_BITS=23 - -FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" - -echo Generating IP cores for $FBITS -{ - #$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 - $CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 - #$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 - #$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS -} > acl_gen.log 2>&1 - -#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/arria10/dspba_delay_ver.sv b/hw/rtl/fp_cores/altera/arria10/dspba_delay_ver.sv deleted file mode 100644 index 526de10a..00000000 --- a/hw/rtl/fp_cores/altera/arria10/dspba_delay_ver.sv +++ /dev/null @@ -1,95 +0,0 @@ -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing device programming or simulation files), and -// any associated documentation or information are expressly subject to the -// terms and conditions of the Intel FPGA Software License Agreement, -// Intel MegaCore Function License Agreement, or other applicable license -// agreement, including, without limitation, that your use is for the sole -// purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - -module dspba_delay_ver -#( - parameter width = 8, - parameter depth = 1, - parameter reset_high = 1'b1, - parameter reset_kind = "ASYNC" -) ( - input clk, - input aclr, - input ena, - input [width-1:0] xin, - output [width-1:0] xout -); - - wire reset; - reg [width-1:0] delays [depth-1:0]; - - assign reset = aclr ^ reset_high; - - generate - if (depth > 0) - begin - genvar i; - for (i = 0; i < depth; ++i) - begin : delay_block - if (reset_kind == "ASYNC") - begin : sync_reset - always @ (posedge clk or negedge reset) - begin: a - if (!reset) begin - delays[i] <= 0; - end else begin - if (ena) begin - if (i > 0) begin - delays[i] <= delays[i - 1]; - end else begin - delays[i] <= xin; - end - end - end - end - end - - if (reset_kind == "SYNC") - begin : async_reset - always @ (posedge clk) - begin: a - if (!reset) begin - delays[i] <= 0; - end else begin - if (ena) begin - if (i > 0) begin - delays[i] <= delays[i - 1]; - end else begin - delays[i] <= xin; - end - end - end - end - end - - if (reset_kind == "NONE") - begin : no_reset - always @ (posedge clk) - begin: a - if (ena) begin - if (i > 0) begin - delays[i] <= delays[i - 1]; - end else begin - delays[i] <= xin; - end - end - end - end - end - - assign xout = delays[depth - 1]; - end else begin - assign xout = xin; - end - endgenerate - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv deleted file mode 100644 index 8ec0f90c..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_fdiv.sv +++ /dev/null @@ -1,4167 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fdiv -// SystemVerilog created on Sun Dec 27 09:48:58 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fdiv ( - input wire [31:0] a, - input wire [31:0] b, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] cstBiasM1_uid6_fpDivTest_q; - wire [7:0] cstBias_uid7_fpDivTest_q; - wire [7:0] expX_uid9_fpDivTest_b; - wire [22:0] fracX_uid10_fpDivTest_b; - wire [0:0] signX_uid11_fpDivTest_b; - wire [7:0] expY_uid12_fpDivTest_b; - wire [22:0] fracY_uid13_fpDivTest_b; - wire [0:0] signY_uid14_fpDivTest_b; - wire [22:0] paddingY_uid15_fpDivTest_q; - wire [23:0] updatedY_uid16_fpDivTest_q; - wire [23:0] fracYZero_uid15_fpDivTest_a; - wire [0:0] fracYZero_uid15_fpDivTest_qi; - reg [0:0] fracYZero_uid15_fpDivTest_q; - wire [7:0] cstAllOWE_uid18_fpDivTest_q; - wire [7:0] cstAllZWE_uid20_fpDivTest_q; - wire [0:0] excZ_x_uid23_fpDivTest_q; - wire [0:0] expXIsMax_uid24_fpDivTest_q; - wire [0:0] fracXIsZero_uid25_fpDivTest_qi; - reg [0:0] fracXIsZero_uid25_fpDivTest_q; - wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; - wire [0:0] excI_x_uid27_fpDivTest_q; - wire [0:0] excN_x_uid28_fpDivTest_q; - wire [0:0] invExpXIsMax_uid29_fpDivTest_q; - wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; - wire [0:0] excR_x_uid31_fpDivTest_qi; - reg [0:0] excR_x_uid31_fpDivTest_q; - wire [0:0] excZ_y_uid37_fpDivTest_qi; - reg [0:0] excZ_y_uid37_fpDivTest_q; - wire [0:0] expXIsMax_uid38_fpDivTest_qi; - reg [0:0] expXIsMax_uid38_fpDivTest_q; - wire [0:0] fracXIsZero_uid39_fpDivTest_qi; - reg [0:0] fracXIsZero_uid39_fpDivTest_q; - wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; - wire [0:0] excI_y_uid41_fpDivTest_q; - wire [0:0] excN_y_uid42_fpDivTest_q; - wire [0:0] invExpXIsMax_uid43_fpDivTest_q; - wire [0:0] InvExpXIsZero_uid44_fpDivTest_q; - wire [0:0] excR_y_uid45_fpDivTest_q; - wire [0:0] signR_uid46_fpDivTest_qi; - reg [0:0] signR_uid46_fpDivTest_q; - wire [8:0] expXmY_uid47_fpDivTest_a; - wire [8:0] expXmY_uid47_fpDivTest_b; - logic [8:0] expXmY_uid47_fpDivTest_o; - wire [8:0] expXmY_uid47_fpDivTest_q; - wire [10:0] expR_uid48_fpDivTest_a; - wire [10:0] expR_uid48_fpDivTest_b; - logic [10:0] expR_uid48_fpDivTest_o; - wire [9:0] expR_uid48_fpDivTest_q; - wire [8:0] yAddr_uid51_fpDivTest_b; - wire [13:0] yPE_uid52_fpDivTest_b; - wire [31:0] invY_uid54_fpDivTest_in; - wire [26:0] invY_uid54_fpDivTest_b; - wire [32:0] invYO_uid55_fpDivTest_in; - wire [0:0] invYO_uid55_fpDivTest_b; - wire [23:0] lOAdded_uid57_fpDivTest_q; - wire [3:0] z4_uid60_fpDivTest_q; - wire [27:0] oFracXZ4_uid61_fpDivTest_q; - wire [0:0] divValPreNormYPow2Exc_uid63_fpDivTest_s; - reg [27:0] divValPreNormYPow2Exc_uid63_fpDivTest_q; - wire [0:0] norm_uid64_fpDivTest_b; - wire [26:0] divValPreNormHigh_uid65_fpDivTest_in; - wire [24:0] divValPreNormHigh_uid65_fpDivTest_b; - wire [25:0] divValPreNormLow_uid66_fpDivTest_in; - wire [24:0] divValPreNormLow_uid66_fpDivTest_b; - wire [0:0] normFracRnd_uid67_fpDivTest_s; - reg [24:0] normFracRnd_uid67_fpDivTest_q; - wire [34:0] expFracRnd_uid68_fpDivTest_q; - wire [23:0] zeroPaddingInAddition_uid74_fpDivTest_q; - wire [25:0] expFracPostRnd_uid75_fpDivTest_q; - wire [36:0] expFracPostRnd_uid76_fpDivTest_a; - wire [36:0] expFracPostRnd_uid76_fpDivTest_b; - logic [36:0] expFracPostRnd_uid76_fpDivTest_o; - wire [35:0] expFracPostRnd_uid76_fpDivTest_q; - wire [23:0] fracXExt_uid77_fpDivTest_q; - wire [24:0] fracPostRndF_uid79_fpDivTest_in; - wire [23:0] fracPostRndF_uid79_fpDivTest_b; - wire [0:0] fracPostRndF_uid80_fpDivTest_s; - reg [23:0] fracPostRndF_uid80_fpDivTest_q; - wire [32:0] expPostRndFR_uid81_fpDivTest_in; - wire [7:0] expPostRndFR_uid81_fpDivTest_b; - wire [0:0] expPostRndF_uid82_fpDivTest_s; - reg [7:0] expPostRndF_uid82_fpDivTest_q; - wire [24:0] lOAdded_uid84_fpDivTest_q; - wire [23:0] lOAdded_uid87_fpDivTest_q; - wire [0:0] qDivProdNorm_uid90_fpDivTest_b; - wire [47:0] qDivProdFracHigh_uid91_fpDivTest_in; - wire [23:0] qDivProdFracHigh_uid91_fpDivTest_b; - wire [46:0] qDivProdFracLow_uid92_fpDivTest_in; - wire [23:0] qDivProdFracLow_uid92_fpDivTest_b; - wire [0:0] qDivProdFrac_uid93_fpDivTest_s; - reg [23:0] qDivProdFrac_uid93_fpDivTest_q; - wire [8:0] qDivProdExp_opA_uid94_fpDivTest_a; - wire [8:0] qDivProdExp_opA_uid94_fpDivTest_b; - logic [8:0] qDivProdExp_opA_uid94_fpDivTest_o; - wire [8:0] qDivProdExp_opA_uid94_fpDivTest_q; - wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_a; - wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_b; - logic [8:0] qDivProdExp_opBs_uid95_fpDivTest_o; - wire [8:0] qDivProdExp_opBs_uid95_fpDivTest_q; - wire [11:0] qDivProdExp_uid96_fpDivTest_a; - wire [11:0] qDivProdExp_uid96_fpDivTest_b; - logic [11:0] qDivProdExp_uid96_fpDivTest_o; - wire [10:0] qDivProdExp_uid96_fpDivTest_q; - wire [22:0] qDivProdFracWF_uid97_fpDivTest_b; - wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_in; - wire [7:0] qDivProdLTX_opA_uid98_fpDivTest_b; - wire [30:0] qDivProdLTX_opA_uid99_fpDivTest_q; - wire [30:0] qDivProdLTX_opB_uid100_fpDivTest_q; - wire [32:0] qDividerProdLTX_uid101_fpDivTest_a; - wire [32:0] qDividerProdLTX_uid101_fpDivTest_b; - logic [32:0] qDividerProdLTX_uid101_fpDivTest_o; - wire [0:0] qDividerProdLTX_uid101_fpDivTest_c; - wire [0:0] betweenFPwF_uid102_fpDivTest_in; - wire [0:0] betweenFPwF_uid102_fpDivTest_b; - wire [0:0] extraUlp_uid103_fpDivTest_qi; - reg [0:0] extraUlp_uid103_fpDivTest_q; - wire [22:0] fracPostRndFT_uid104_fpDivTest_b; - wire [23:0] fracRPreExcExt_uid105_fpDivTest_a; - wire [23:0] fracRPreExcExt_uid105_fpDivTest_b; - logic [23:0] fracRPreExcExt_uid105_fpDivTest_o; - wire [23:0] fracRPreExcExt_uid105_fpDivTest_q; - wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_in; - wire [22:0] fracPostRndFPostUlp_uid106_fpDivTest_b; - wire [0:0] fracRPreExc_uid107_fpDivTest_s; - reg [22:0] fracRPreExc_uid107_fpDivTest_q; - wire [0:0] ovfIncRnd_uid109_fpDivTest_b; - wire [8:0] expFracPostRndInc_uid110_fpDivTest_a; - wire [8:0] expFracPostRndInc_uid110_fpDivTest_b; - logic [8:0] expFracPostRndInc_uid110_fpDivTest_o; - wire [8:0] expFracPostRndInc_uid110_fpDivTest_q; - wire [7:0] expFracPostRndR_uid111_fpDivTest_in; - wire [7:0] expFracPostRndR_uid111_fpDivTest_b; - wire [0:0] expRPreExc_uid112_fpDivTest_s; - reg [7:0] expRPreExc_uid112_fpDivTest_q; - wire [10:0] expRExt_uid114_fpDivTest_b; - wire [12:0] expUdf_uid115_fpDivTest_a; - wire [12:0] expUdf_uid115_fpDivTest_b; - logic [12:0] expUdf_uid115_fpDivTest_o; - wire [0:0] expUdf_uid115_fpDivTest_n; - wire [12:0] expOvf_uid118_fpDivTest_a; - wire [12:0] expOvf_uid118_fpDivTest_b; - logic [12:0] expOvf_uid118_fpDivTest_o; - wire [0:0] expOvf_uid118_fpDivTest_n; - wire [0:0] zeroOverReg_uid119_fpDivTest_q; - wire [0:0] regOverRegWithUf_uid120_fpDivTest_q; - wire [0:0] xRegOrZero_uid121_fpDivTest_q; - wire [0:0] regOrZeroOverInf_uid122_fpDivTest_q; - wire [0:0] excRZero_uid123_fpDivTest_q; - wire [0:0] excXRYZ_uid124_fpDivTest_q; - wire [0:0] excXRYROvf_uid125_fpDivTest_q; - wire [0:0] excXIYZ_uid126_fpDivTest_q; - wire [0:0] excXIYR_uid127_fpDivTest_q; - wire [0:0] excRInf_uid128_fpDivTest_q; - wire [0:0] excXZYZ_uid129_fpDivTest_q; - wire [0:0] excXIYI_uid130_fpDivTest_q; - wire [0:0] excRNaN_uid131_fpDivTest_q; - wire [2:0] concExc_uid132_fpDivTest_q; - reg [1:0] excREnc_uid133_fpDivTest_q; - wire [22:0] oneFracRPostExc2_uid134_fpDivTest_q; - wire [1:0] fracRPostExc_uid137_fpDivTest_s; - reg [22:0] fracRPostExc_uid137_fpDivTest_q; - wire [1:0] expRPostExc_uid141_fpDivTest_s; - reg [7:0] expRPostExc_uid141_fpDivTest_q; - wire [0:0] invExcRNaN_uid142_fpDivTest_q; - wire [0:0] sRPostExc_uid143_fpDivTest_qi; - reg [0:0] sRPostExc_uid143_fpDivTest_q; - wire [31:0] divR_uid144_fpDivTest_q; - wire [12:0] yT1_uid158_invPolyEval_b; - wire [0:0] lowRangeB_uid160_invPolyEval_in; - wire [0:0] lowRangeB_uid160_invPolyEval_b; - wire [12:0] highBBits_uid161_invPolyEval_b; - wire [22:0] s1sumAHighB_uid162_invPolyEval_a; - wire [22:0] s1sumAHighB_uid162_invPolyEval_b; - logic [22:0] s1sumAHighB_uid162_invPolyEval_o; - wire [22:0] s1sumAHighB_uid162_invPolyEval_q; - wire [23:0] s1_uid163_invPolyEval_q; - wire [1:0] lowRangeB_uid166_invPolyEval_in; - wire [1:0] lowRangeB_uid166_invPolyEval_b; - wire [22:0] highBBits_uid167_invPolyEval_b; - wire [32:0] s2sumAHighB_uid168_invPolyEval_a; - wire [32:0] s2sumAHighB_uid168_invPolyEval_b; - logic [32:0] s2sumAHighB_uid168_invPolyEval_o; - wire [32:0] s2sumAHighB_uid168_invPolyEval_q; - wire [34:0] s2_uid169_invPolyEval_q; - wire [27:0] osig_uid172_divValPreNorm_uid59_fpDivTest_b; - wire [13:0] osig_uid175_pT1_uid159_invPolyEval_b; - wire [24:0] osig_uid178_pT2_uid165_invPolyEval_b; - wire memoryC0_uid146_invTables_lutmem_reset0; - wire [31:0] memoryC0_uid146_invTables_lutmem_ia; - wire [8:0] memoryC0_uid146_invTables_lutmem_aa; - wire [8:0] memoryC0_uid146_invTables_lutmem_ab; - wire [31:0] memoryC0_uid146_invTables_lutmem_ir; - wire [31:0] memoryC0_uid146_invTables_lutmem_r; - wire memoryC0_uid146_invTables_lutmem_enaOr_rst; - wire memoryC1_uid149_invTables_lutmem_reset0; - wire [21:0] memoryC1_uid149_invTables_lutmem_ia; - wire [8:0] memoryC1_uid149_invTables_lutmem_aa; - wire [8:0] memoryC1_uid149_invTables_lutmem_ab; - wire [21:0] memoryC1_uid149_invTables_lutmem_ir; - wire [21:0] memoryC1_uid149_invTables_lutmem_r; - wire memoryC1_uid149_invTables_lutmem_enaOr_rst; - wire memoryC2_uid152_invTables_lutmem_reset0; - wire [12:0] memoryC2_uid152_invTables_lutmem_ia; - wire [8:0] memoryC2_uid152_invTables_lutmem_aa; - wire [8:0] memoryC2_uid152_invTables_lutmem_ab; - wire [12:0] memoryC2_uid152_invTables_lutmem_ir; - wire [12:0] memoryC2_uid152_invTables_lutmem_r; - wire memoryC2_uid152_invTables_lutmem_enaOr_rst; - wire qDivProd_uid89_fpDivTest_cma_reset; - (* preserve_syn_only *) reg [24:0] qDivProd_uid89_fpDivTest_cma_ah [0:0]; - (* preserve_syn_only *) reg [23:0] qDivProd_uid89_fpDivTest_cma_ch [0:0]; - wire [24:0] qDivProd_uid89_fpDivTest_cma_a0; - wire [23:0] qDivProd_uid89_fpDivTest_cma_c0; - wire [48:0] qDivProd_uid89_fpDivTest_cma_s0; - wire [48:0] qDivProd_uid89_fpDivTest_cma_qq; - reg [48:0] qDivProd_uid89_fpDivTest_cma_q; - wire qDivProd_uid89_fpDivTest_cma_ena0; - wire qDivProd_uid89_fpDivTest_cma_ena1; - wire qDivProd_uid89_fpDivTest_cma_ena2; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset; - (* preserve_syn_only *) reg [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ah [0:0]; - (* preserve_syn_only *) reg [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ch [0:0]; - wire [26:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0; - wire [23:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s0; - wire [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq; - reg [50:0] prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1; - wire prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_reset; - (* preserve_syn_only *) reg [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_ah [0:0]; - (* preserve_syn_only *) reg signed [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_ch [0:0]; - wire [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_a0; - wire [12:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_c0; - wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_s0; - wire [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_qq; - reg [25:0] prodXY_uid174_pT1_uid159_invPolyEval_cma_q; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1; - wire prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_reset; - (* preserve_syn_only *) reg [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_ah [0:0]; - (* preserve_syn_only *) reg signed [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_ch [0:0]; - wire [13:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_a0; - wire [23:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_c0; - wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_s0; - wire [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_qq; - reg [37:0] prodXY_uid177_pT2_uid165_invPolyEval_cma_q; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1; - wire prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2; - reg [12:0] redist0_memoryC2_uid152_invTables_lutmem_r_1_q; - reg [0:0] redist1_lowRangeB_uid160_invPolyEval_b_1_q; - reg [0:0] redist2_sRPostExc_uid143_fpDivTest_q_9_q; - reg [1:0] redist3_excREnc_uid133_fpDivTest_q_9_q; - reg [0:0] redist5_betweenFPwF_uid102_fpDivTest_b_7_q; - reg [7:0] redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q; - reg [22:0] redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q; - reg [7:0] redist9_expPostRndFR_uid81_fpDivTest_b_9_q; - reg [7:0] redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0; - reg [23:0] redist10_fracPostRndF_uid79_fpDivTest_b_1_q; - reg [0:0] redist11_norm_uid64_fpDivTest_b_1_q; - reg [0:0] redist13_invYO_uid55_fpDivTest_b_9_q; - reg [0:0] redist14_invYO_uid55_fpDivTest_b_15_q; - reg [26:0] redist15_invY_uid54_fpDivTest_b_1_q; - reg [13:0] redist16_yPE_uid52_fpDivTest_b_3_q; - reg [13:0] redist16_yPE_uid52_fpDivTest_b_3_delay_0; - reg [13:0] redist16_yPE_uid52_fpDivTest_b_3_delay_1; - reg [0:0] redist20_signR_uid46_fpDivTest_q_25_q; - reg [0:0] redist21_expXIsMax_uid24_fpDivTest_q_1_q; - reg [0:0] redist22_excZ_x_uid23_fpDivTest_q_1_q; - reg [22:0] redist24_fracY_uid13_fpDivTest_b_24_q; - reg [22:0] redist24_fracY_uid13_fpDivTest_b_24_delay_0; - reg [22:0] redist25_fracY_uid13_fpDivTest_b_25_q; - reg [7:0] redist27_expY_uid12_fpDivTest_b_24_q; - reg [22:0] redist31_fracX_uid10_fpDivTest_b_25_q; - reg [7:0] redist34_expX_uid9_fpDivTest_b_24_q; - reg [7:0] redist36_expX_uid9_fpDivTest_b_32_q; - wire redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0; - wire [22:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ia; - wire [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_aa; - wire [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ab; - wire [22:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_iq; - wire [22:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q; - wire redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_enaOr_rst; - wire [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i; - (* preserve_syn_only *) reg redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq; - wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s; - reg [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q; - reg [2:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q; - wire [3:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last_q; - wire [3:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_b; - wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_q; - reg [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q; - wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable_q; - wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor_q; - (* preserve_syn_only *) reg [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q; - wire [0:0] redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd_q; - reg [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q; - wire redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0; - wire [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ia; - wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_aa; - wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ab; - wire [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_iq; - wire [7:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_q; - wire redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_enaOr_rst; - wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i; - (* preserve_syn_only *) reg redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq; - wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s; - reg [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q; - reg [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q; - wire [2:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last_q; - wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp_q; - reg [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q; - wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable_q; - wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_nor_q; - (* preserve_syn_only *) reg [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q; - wire [0:0] redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd_q; - wire redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0; - wire [23:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_ia; - wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_aa; - wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_ab; - wire [23:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_iq; - wire [23:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_q; - wire redist12_lOAdded_uid57_fpDivTest_q_6_mem_enaOr_rst; - wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i; - (* preserve_syn_only *) reg redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq; - wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s; - reg [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q; - reg [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q; - wire [2:0] redist12_lOAdded_uid57_fpDivTest_q_6_mem_last_q; - wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_cmp_q; - reg [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q; - wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_notEnable_q; - wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_nor_q; - (* preserve_syn_only *) reg [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q; - wire [0:0] redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd_q; - reg [13:0] redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q; - wire redist17_yPE_uid52_fpDivTest_b_10_mem_reset0; - wire [13:0] redist17_yPE_uid52_fpDivTest_b_10_mem_ia; - wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_mem_aa; - wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_mem_ab; - wire [13:0] redist17_yPE_uid52_fpDivTest_b_10_mem_iq; - wire [13:0] redist17_yPE_uid52_fpDivTest_b_10_mem_q; - wire redist17_yPE_uid52_fpDivTest_b_10_mem_enaOr_rst; - wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i; - (* preserve_syn_only *) reg redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq; - wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_rdmux_s; - reg [2:0] redist17_yPE_uid52_fpDivTest_b_10_rdmux_q; - reg [2:0] redist17_yPE_uid52_fpDivTest_b_10_wraddr_q; - wire [2:0] redist17_yPE_uid52_fpDivTest_b_10_mem_last_q; - wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_cmp_q; - reg [0:0] redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q; - wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_notEnable_q; - wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_nor_q; - (* preserve_syn_only *) reg [0:0] redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q; - wire [0:0] redist17_yPE_uid52_fpDivTest_b_10_enaAnd_q; - reg [8:0] redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q; - wire redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0; - wire [8:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_ia; - wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_aa; - wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_ab; - wire [8:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_iq; - wire [8:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_q; - wire redist18_yAddr_uid51_fpDivTest_b_7_mem_enaOr_rst; - wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i; - (* preserve_syn_only *) reg redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq; - wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s; - reg [2:0] redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q; - reg [2:0] redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q; - wire [2:0] redist18_yAddr_uid51_fpDivTest_b_7_mem_last_q; - wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_cmp_q; - reg [0:0] redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q; - wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_notEnable_q; - wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_nor_q; - (* preserve_syn_only *) reg [0:0] redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q; - wire [0:0] redist18_yAddr_uid51_fpDivTest_b_7_enaAnd_q; - reg [8:0] redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q; - wire redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0; - wire [8:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_ia; - wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_aa; - wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_ab; - wire [8:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_iq; - wire [8:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_q; - wire redist19_yAddr_uid51_fpDivTest_b_14_mem_enaOr_rst; - wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i; - (* preserve_syn_only *) reg redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq; - wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s; - reg [2:0] redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q; - reg [2:0] redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q; - wire [2:0] redist19_yAddr_uid51_fpDivTest_b_14_mem_last_q; - wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_cmp_q; - reg [0:0] redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q; - wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_notEnable_q; - wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_nor_q; - (* preserve_syn_only *) reg [0:0] redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q; - wire [0:0] redist19_yAddr_uid51_fpDivTest_b_14_enaAnd_q; - wire redist23_fracY_uid13_fpDivTest_b_22_mem_reset0; - wire [22:0] redist23_fracY_uid13_fpDivTest_b_22_mem_ia; - wire [4:0] redist23_fracY_uid13_fpDivTest_b_22_mem_aa; - wire [4:0] redist23_fracY_uid13_fpDivTest_b_22_mem_ab; - wire [22:0] redist23_fracY_uid13_fpDivTest_b_22_mem_iq; - wire [22:0] redist23_fracY_uid13_fpDivTest_b_22_mem_q; - wire redist23_fracY_uid13_fpDivTest_b_22_mem_enaOr_rst; - wire [4:0] redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q; - (* preserve_syn_only *) reg [4:0] redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i; - (* preserve_syn_only *) reg redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq; - wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_rdmux_s; - reg [4:0] redist23_fracY_uid13_fpDivTest_b_22_rdmux_q; - reg [4:0] redist23_fracY_uid13_fpDivTest_b_22_wraddr_q; - wire [5:0] redist23_fracY_uid13_fpDivTest_b_22_mem_last_q; - wire [5:0] redist23_fracY_uid13_fpDivTest_b_22_cmp_b; - wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_cmp_q; - reg [0:0] redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q; - wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_notEnable_q; - wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_nor_q; - (* preserve_syn_only *) reg [0:0] redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q; - wire [0:0] redist23_fracY_uid13_fpDivTest_b_22_enaAnd_q; - wire redist26_expY_uid12_fpDivTest_b_23_mem_reset0; - wire [7:0] redist26_expY_uid12_fpDivTest_b_23_mem_ia; - wire [4:0] redist26_expY_uid12_fpDivTest_b_23_mem_aa; - wire [4:0] redist26_expY_uid12_fpDivTest_b_23_mem_ab; - wire [7:0] redist26_expY_uid12_fpDivTest_b_23_mem_iq; - wire [7:0] redist26_expY_uid12_fpDivTest_b_23_mem_q; - wire redist26_expY_uid12_fpDivTest_b_23_mem_enaOr_rst; - wire [4:0] redist26_expY_uid12_fpDivTest_b_23_rdcnt_q; - (* preserve_syn_only *) reg [4:0] redist26_expY_uid12_fpDivTest_b_23_rdcnt_i; - (* preserve_syn_only *) reg redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq; - wire [0:0] redist26_expY_uid12_fpDivTest_b_23_rdmux_s; - reg [4:0] redist26_expY_uid12_fpDivTest_b_23_rdmux_q; - reg [4:0] redist26_expY_uid12_fpDivTest_b_23_wraddr_q; - wire [5:0] redist26_expY_uid12_fpDivTest_b_23_mem_last_q; - wire [5:0] redist26_expY_uid12_fpDivTest_b_23_cmp_b; - wire [0:0] redist26_expY_uid12_fpDivTest_b_23_cmp_q; - reg [0:0] redist26_expY_uid12_fpDivTest_b_23_cmpReg_q; - wire [0:0] redist26_expY_uid12_fpDivTest_b_23_notEnable_q; - wire [0:0] redist26_expY_uid12_fpDivTest_b_23_nor_q; - (* preserve_syn_only *) reg [0:0] redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q; - wire [0:0] redist26_expY_uid12_fpDivTest_b_23_enaAnd_q; - reg [7:0] redist28_expY_uid12_fpDivTest_b_31_outputreg0_q; - wire redist28_expY_uid12_fpDivTest_b_31_mem_reset0; - wire [7:0] redist28_expY_uid12_fpDivTest_b_31_mem_ia; - wire [2:0] redist28_expY_uid12_fpDivTest_b_31_mem_aa; - wire [2:0] redist28_expY_uid12_fpDivTest_b_31_mem_ab; - wire [7:0] redist28_expY_uid12_fpDivTest_b_31_mem_iq; - wire [7:0] redist28_expY_uid12_fpDivTest_b_31_mem_q; - wire redist28_expY_uid12_fpDivTest_b_31_mem_enaOr_rst; - wire [2:0] redist28_expY_uid12_fpDivTest_b_31_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist28_expY_uid12_fpDivTest_b_31_rdcnt_i; - (* preserve_syn_only *) reg redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq; - wire [0:0] redist28_expY_uid12_fpDivTest_b_31_rdmux_s; - reg [2:0] redist28_expY_uid12_fpDivTest_b_31_rdmux_q; - reg [2:0] redist28_expY_uid12_fpDivTest_b_31_wraddr_q; - wire [2:0] redist28_expY_uid12_fpDivTest_b_31_mem_last_q; - wire [0:0] redist28_expY_uid12_fpDivTest_b_31_cmp_q; - reg [0:0] redist28_expY_uid12_fpDivTest_b_31_cmpReg_q; - wire [0:0] redist28_expY_uid12_fpDivTest_b_31_notEnable_q; - wire [0:0] redist28_expY_uid12_fpDivTest_b_31_nor_q; - (* preserve_syn_only *) reg [0:0] redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q; - wire [0:0] redist28_expY_uid12_fpDivTest_b_31_enaAnd_q; - reg [22:0] redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q; - wire redist29_fracX_uid10_fpDivTest_b_17_mem_reset0; - wire [22:0] redist29_fracX_uid10_fpDivTest_b_17_mem_ia; - wire [3:0] redist29_fracX_uid10_fpDivTest_b_17_mem_aa; - wire [3:0] redist29_fracX_uid10_fpDivTest_b_17_mem_ab; - wire [22:0] redist29_fracX_uid10_fpDivTest_b_17_mem_iq; - wire [22:0] redist29_fracX_uid10_fpDivTest_b_17_mem_q; - wire redist29_fracX_uid10_fpDivTest_b_17_mem_enaOr_rst; - wire [3:0] redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q; - (* preserve_syn_only *) reg [3:0] redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i; - (* preserve_syn_only *) reg redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq; - wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_rdmux_s; - reg [3:0] redist29_fracX_uid10_fpDivTest_b_17_rdmux_q; - reg [3:0] redist29_fracX_uid10_fpDivTest_b_17_wraddr_q; - wire [4:0] redist29_fracX_uid10_fpDivTest_b_17_mem_last_q; - wire [4:0] redist29_fracX_uid10_fpDivTest_b_17_cmp_b; - wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_cmp_q; - reg [0:0] redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q; - wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_notEnable_q; - wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_nor_q; - (* preserve_syn_only *) reg [0:0] redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q; - wire [0:0] redist29_fracX_uid10_fpDivTest_b_17_enaAnd_q; - wire redist30_fracX_uid10_fpDivTest_b_24_mem_reset0; - wire [22:0] redist30_fracX_uid10_fpDivTest_b_24_mem_ia; - wire [2:0] redist30_fracX_uid10_fpDivTest_b_24_mem_aa; - wire [2:0] redist30_fracX_uid10_fpDivTest_b_24_mem_ab; - wire [22:0] redist30_fracX_uid10_fpDivTest_b_24_mem_iq; - wire [22:0] redist30_fracX_uid10_fpDivTest_b_24_mem_q; - wire redist30_fracX_uid10_fpDivTest_b_24_mem_enaOr_rst; - wire [2:0] redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i; - (* preserve_syn_only *) reg redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq; - wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_rdmux_s; - reg [2:0] redist30_fracX_uid10_fpDivTest_b_24_rdmux_q; - reg [2:0] redist30_fracX_uid10_fpDivTest_b_24_wraddr_q; - wire [3:0] redist30_fracX_uid10_fpDivTest_b_24_mem_last_q; - wire [3:0] redist30_fracX_uid10_fpDivTest_b_24_cmp_b; - wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_cmp_q; - reg [0:0] redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q; - wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_notEnable_q; - wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_nor_q; - (* preserve_syn_only *) reg [0:0] redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q; - wire [0:0] redist30_fracX_uid10_fpDivTest_b_24_enaAnd_q; - wire redist32_fracX_uid10_fpDivTest_b_32_mem_reset0; - wire [22:0] redist32_fracX_uid10_fpDivTest_b_32_mem_ia; - wire [2:0] redist32_fracX_uid10_fpDivTest_b_32_mem_aa; - wire [2:0] redist32_fracX_uid10_fpDivTest_b_32_mem_ab; - wire [22:0] redist32_fracX_uid10_fpDivTest_b_32_mem_iq; - wire [22:0] redist32_fracX_uid10_fpDivTest_b_32_mem_q; - wire redist32_fracX_uid10_fpDivTest_b_32_mem_enaOr_rst; - wire [2:0] redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i; - (* preserve_syn_only *) reg redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq; - wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_rdmux_s; - reg [2:0] redist32_fracX_uid10_fpDivTest_b_32_rdmux_q; - reg [2:0] redist32_fracX_uid10_fpDivTest_b_32_wraddr_q; - wire [3:0] redist32_fracX_uid10_fpDivTest_b_32_mem_last_q; - wire [3:0] redist32_fracX_uid10_fpDivTest_b_32_cmp_b; - wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_cmp_q; - reg [0:0] redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q; - wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_notEnable_q; - wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_nor_q; - (* preserve_syn_only *) reg [0:0] redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q; - wire [0:0] redist32_fracX_uid10_fpDivTest_b_32_enaAnd_q; - wire redist33_expX_uid9_fpDivTest_b_23_mem_reset0; - wire [7:0] redist33_expX_uid9_fpDivTest_b_23_mem_ia; - wire [4:0] redist33_expX_uid9_fpDivTest_b_23_mem_aa; - wire [4:0] redist33_expX_uid9_fpDivTest_b_23_mem_ab; - wire [7:0] redist33_expX_uid9_fpDivTest_b_23_mem_iq; - wire [7:0] redist33_expX_uid9_fpDivTest_b_23_mem_q; - wire redist33_expX_uid9_fpDivTest_b_23_mem_enaOr_rst; - wire [4:0] redist33_expX_uid9_fpDivTest_b_23_rdcnt_q; - (* preserve_syn_only *) reg [4:0] redist33_expX_uid9_fpDivTest_b_23_rdcnt_i; - (* preserve_syn_only *) reg redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq; - wire [0:0] redist33_expX_uid9_fpDivTest_b_23_rdmux_s; - reg [4:0] redist33_expX_uid9_fpDivTest_b_23_rdmux_q; - reg [4:0] redist33_expX_uid9_fpDivTest_b_23_wraddr_q; - wire [5:0] redist33_expX_uid9_fpDivTest_b_23_mem_last_q; - wire [5:0] redist33_expX_uid9_fpDivTest_b_23_cmp_b; - wire [0:0] redist33_expX_uid9_fpDivTest_b_23_cmp_q; - reg [0:0] redist33_expX_uid9_fpDivTest_b_23_cmpReg_q; - wire [0:0] redist33_expX_uid9_fpDivTest_b_23_notEnable_q; - wire [0:0] redist33_expX_uid9_fpDivTest_b_23_nor_q; - (* preserve_syn_only *) reg [0:0] redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q; - wire [0:0] redist33_expX_uid9_fpDivTest_b_23_enaAnd_q; - reg [7:0] redist35_expX_uid9_fpDivTest_b_31_outputreg0_q; - wire redist35_expX_uid9_fpDivTest_b_31_mem_reset0; - wire [7:0] redist35_expX_uid9_fpDivTest_b_31_mem_ia; - wire [2:0] redist35_expX_uid9_fpDivTest_b_31_mem_aa; - wire [2:0] redist35_expX_uid9_fpDivTest_b_31_mem_ab; - wire [7:0] redist35_expX_uid9_fpDivTest_b_31_mem_iq; - wire [7:0] redist35_expX_uid9_fpDivTest_b_31_mem_q; - wire redist35_expX_uid9_fpDivTest_b_31_mem_enaOr_rst; - wire [2:0] redist35_expX_uid9_fpDivTest_b_31_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist35_expX_uid9_fpDivTest_b_31_rdcnt_i; - (* preserve_syn_only *) reg redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq; - wire [0:0] redist35_expX_uid9_fpDivTest_b_31_rdmux_s; - reg [2:0] redist35_expX_uid9_fpDivTest_b_31_rdmux_q; - reg [2:0] redist35_expX_uid9_fpDivTest_b_31_wraddr_q; - wire [2:0] redist35_expX_uid9_fpDivTest_b_31_mem_last_q; - wire [0:0] redist35_expX_uid9_fpDivTest_b_31_cmp_q; - reg [0:0] redist35_expX_uid9_fpDivTest_b_31_cmpReg_q; - wire [0:0] redist35_expX_uid9_fpDivTest_b_31_notEnable_q; - wire [0:0] redist35_expX_uid9_fpDivTest_b_31_nor_q; - (* preserve_syn_only *) reg [0:0] redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q; - wire [0:0] redist35_expX_uid9_fpDivTest_b_31_enaAnd_q; - - - // redist23_fracY_uid13_fpDivTest_b_22_notEnable(LOGICAL,300) - assign redist23_fracY_uid13_fpDivTest_b_22_notEnable_q = ~ (en); - - // redist23_fracY_uid13_fpDivTest_b_22_nor(LOGICAL,301) - assign redist23_fracY_uid13_fpDivTest_b_22_nor_q = ~ (redist23_fracY_uid13_fpDivTest_b_22_notEnable_q | redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q); - - // redist23_fracY_uid13_fpDivTest_b_22_mem_last(CONSTANT,297) - assign redist23_fracY_uid13_fpDivTest_b_22_mem_last_q = 6'b010011; - - // redist23_fracY_uid13_fpDivTest_b_22_cmp(LOGICAL,298) - assign redist23_fracY_uid13_fpDivTest_b_22_cmp_b = {1'b0, redist23_fracY_uid13_fpDivTest_b_22_rdmux_q}; - assign redist23_fracY_uid13_fpDivTest_b_22_cmp_q = redist23_fracY_uid13_fpDivTest_b_22_mem_last_q == redist23_fracY_uid13_fpDivTest_b_22_cmp_b ? 1'b1 : 1'b0; - - // redist23_fracY_uid13_fpDivTest_b_22_cmpReg(REG,299) - always @ (posedge clk) - begin - if (areset) - begin - redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q <= redist23_fracY_uid13_fpDivTest_b_22_cmp_q; - end - end - - // redist23_fracY_uid13_fpDivTest_b_22_sticky_ena(REG,302) - always @ (posedge clk) - begin - if (areset) - begin - redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q <= 1'b0; - end - else if (redist23_fracY_uid13_fpDivTest_b_22_nor_q == 1'b1) - begin - redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q <= redist23_fracY_uid13_fpDivTest_b_22_cmpReg_q; - end - end - - // redist23_fracY_uid13_fpDivTest_b_22_enaAnd(LOGICAL,303) - assign redist23_fracY_uid13_fpDivTest_b_22_enaAnd_q = redist23_fracY_uid13_fpDivTest_b_22_sticky_ena_q & en; - - // redist23_fracY_uid13_fpDivTest_b_22_rdcnt(COUNTER,294) - // low=0, high=20, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i <= 5'd0; - redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i == 5'd19) - begin - redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq <= 1'b1; - end - else - begin - redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq <= 1'b0; - end - if (redist23_fracY_uid13_fpDivTest_b_22_rdcnt_eq == 1'b1) - begin - redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i <= $unsigned(redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i) + $unsigned(5'd12); - end - else - begin - redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i <= $unsigned(redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i) + $unsigned(5'd1); - end - end - end - assign redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q = redist23_fracY_uid13_fpDivTest_b_22_rdcnt_i[4:0]; - - // redist23_fracY_uid13_fpDivTest_b_22_rdmux(MUX,295) - assign redist23_fracY_uid13_fpDivTest_b_22_rdmux_s = en; - always @(redist23_fracY_uid13_fpDivTest_b_22_rdmux_s or redist23_fracY_uid13_fpDivTest_b_22_wraddr_q or redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q) - begin - unique case (redist23_fracY_uid13_fpDivTest_b_22_rdmux_s) - 1'b0 : redist23_fracY_uid13_fpDivTest_b_22_rdmux_q = redist23_fracY_uid13_fpDivTest_b_22_wraddr_q; - 1'b1 : redist23_fracY_uid13_fpDivTest_b_22_rdmux_q = redist23_fracY_uid13_fpDivTest_b_22_rdcnt_q; - default : redist23_fracY_uid13_fpDivTest_b_22_rdmux_q = 5'b0; - endcase - end - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // fracY_uid13_fpDivTest(BITSELECT,12)@0 - assign fracY_uid13_fpDivTest_b = b[22:0]; - - // redist23_fracY_uid13_fpDivTest_b_22_wraddr(REG,296) - always @ (posedge clk) - begin - if (areset) - begin - redist23_fracY_uid13_fpDivTest_b_22_wraddr_q <= 5'b10100; - end - else - begin - redist23_fracY_uid13_fpDivTest_b_22_wraddr_q <= redist23_fracY_uid13_fpDivTest_b_22_rdmux_q; - end - end - - // redist23_fracY_uid13_fpDivTest_b_22_mem(DUALMEM,293) - assign redist23_fracY_uid13_fpDivTest_b_22_mem_ia = fracY_uid13_fpDivTest_b; - assign redist23_fracY_uid13_fpDivTest_b_22_mem_aa = redist23_fracY_uid13_fpDivTest_b_22_wraddr_q; - assign redist23_fracY_uid13_fpDivTest_b_22_mem_ab = redist23_fracY_uid13_fpDivTest_b_22_rdmux_q; - assign redist23_fracY_uid13_fpDivTest_b_22_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(5), - .numwords_a(21), - .width_b(23), - .widthad_b(5), - .numwords_b(21), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist23_fracY_uid13_fpDivTest_b_22_mem_dmem ( - .clocken1(redist23_fracY_uid13_fpDivTest_b_22_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist23_fracY_uid13_fpDivTest_b_22_mem_reset0), - .clock1(clk), - .address_a(redist23_fracY_uid13_fpDivTest_b_22_mem_aa), - .data_a(redist23_fracY_uid13_fpDivTest_b_22_mem_ia), - .wren_a(en[0]), - .address_b(redist23_fracY_uid13_fpDivTest_b_22_mem_ab), - .q_b(redist23_fracY_uid13_fpDivTest_b_22_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist23_fracY_uid13_fpDivTest_b_22_mem_q = redist23_fracY_uid13_fpDivTest_b_22_mem_iq[22:0]; - assign redist23_fracY_uid13_fpDivTest_b_22_mem_enaOr_rst = redist23_fracY_uid13_fpDivTest_b_22_enaAnd_q[0] | redist23_fracY_uid13_fpDivTest_b_22_mem_reset0; - - // redist24_fracY_uid13_fpDivTest_b_24(DELAY,210) - always @ (posedge clk) - begin - if (areset) - begin - redist24_fracY_uid13_fpDivTest_b_24_delay_0 <= '0; - redist24_fracY_uid13_fpDivTest_b_24_q <= '0; - end - else if (en == 1'b1) - begin - redist24_fracY_uid13_fpDivTest_b_24_delay_0 <= redist23_fracY_uid13_fpDivTest_b_22_mem_q; - redist24_fracY_uid13_fpDivTest_b_24_q <= redist24_fracY_uid13_fpDivTest_b_24_delay_0; - end - end - - // paddingY_uid15_fpDivTest(CONSTANT,14) - assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@24 + 1 - assign fracXIsZero_uid39_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist24_fracY_uid13_fpDivTest_b_24_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - fracXIsZero_uid39_fpDivTest_delay ( .xin(fracXIsZero_uid39_fpDivTest_qi), .xout(fracXIsZero_uid39_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid18_fpDivTest(CONSTANT,17) - assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; - - // redist26_expY_uid12_fpDivTest_b_23_notEnable(LOGICAL,311) - assign redist26_expY_uid12_fpDivTest_b_23_notEnable_q = ~ (en); - - // redist26_expY_uid12_fpDivTest_b_23_nor(LOGICAL,312) - assign redist26_expY_uid12_fpDivTest_b_23_nor_q = ~ (redist26_expY_uid12_fpDivTest_b_23_notEnable_q | redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q); - - // redist26_expY_uid12_fpDivTest_b_23_mem_last(CONSTANT,308) - assign redist26_expY_uid12_fpDivTest_b_23_mem_last_q = 6'b010100; - - // redist26_expY_uid12_fpDivTest_b_23_cmp(LOGICAL,309) - assign redist26_expY_uid12_fpDivTest_b_23_cmp_b = {1'b0, redist26_expY_uid12_fpDivTest_b_23_rdmux_q}; - assign redist26_expY_uid12_fpDivTest_b_23_cmp_q = redist26_expY_uid12_fpDivTest_b_23_mem_last_q == redist26_expY_uid12_fpDivTest_b_23_cmp_b ? 1'b1 : 1'b0; - - // redist26_expY_uid12_fpDivTest_b_23_cmpReg(REG,310) - always @ (posedge clk) - begin - if (areset) - begin - redist26_expY_uid12_fpDivTest_b_23_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist26_expY_uid12_fpDivTest_b_23_cmpReg_q <= redist26_expY_uid12_fpDivTest_b_23_cmp_q; - end - end - - // redist26_expY_uid12_fpDivTest_b_23_sticky_ena(REG,313) - always @ (posedge clk) - begin - if (areset) - begin - redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q <= 1'b0; - end - else if (redist26_expY_uid12_fpDivTest_b_23_nor_q == 1'b1) - begin - redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q <= redist26_expY_uid12_fpDivTest_b_23_cmpReg_q; - end - end - - // redist26_expY_uid12_fpDivTest_b_23_enaAnd(LOGICAL,314) - assign redist26_expY_uid12_fpDivTest_b_23_enaAnd_q = redist26_expY_uid12_fpDivTest_b_23_sticky_ena_q & en; - - // redist26_expY_uid12_fpDivTest_b_23_rdcnt(COUNTER,305) - // low=0, high=21, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist26_expY_uid12_fpDivTest_b_23_rdcnt_i <= 5'd0; - redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist26_expY_uid12_fpDivTest_b_23_rdcnt_i == 5'd20) - begin - redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq <= 1'b1; - end - else - begin - redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq <= 1'b0; - end - if (redist26_expY_uid12_fpDivTest_b_23_rdcnt_eq == 1'b1) - begin - redist26_expY_uid12_fpDivTest_b_23_rdcnt_i <= $unsigned(redist26_expY_uid12_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd11); - end - else - begin - redist26_expY_uid12_fpDivTest_b_23_rdcnt_i <= $unsigned(redist26_expY_uid12_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd1); - end - end - end - assign redist26_expY_uid12_fpDivTest_b_23_rdcnt_q = redist26_expY_uid12_fpDivTest_b_23_rdcnt_i[4:0]; - - // redist26_expY_uid12_fpDivTest_b_23_rdmux(MUX,306) - assign redist26_expY_uid12_fpDivTest_b_23_rdmux_s = en; - always @(redist26_expY_uid12_fpDivTest_b_23_rdmux_s or redist26_expY_uid12_fpDivTest_b_23_wraddr_q or redist26_expY_uid12_fpDivTest_b_23_rdcnt_q) - begin - unique case (redist26_expY_uid12_fpDivTest_b_23_rdmux_s) - 1'b0 : redist26_expY_uid12_fpDivTest_b_23_rdmux_q = redist26_expY_uid12_fpDivTest_b_23_wraddr_q; - 1'b1 : redist26_expY_uid12_fpDivTest_b_23_rdmux_q = redist26_expY_uid12_fpDivTest_b_23_rdcnt_q; - default : redist26_expY_uid12_fpDivTest_b_23_rdmux_q = 5'b0; - endcase - end - - // expY_uid12_fpDivTest(BITSELECT,11)@0 - assign expY_uid12_fpDivTest_b = b[30:23]; - - // redist26_expY_uid12_fpDivTest_b_23_wraddr(REG,307) - always @ (posedge clk) - begin - if (areset) - begin - redist26_expY_uid12_fpDivTest_b_23_wraddr_q <= 5'b10101; - end - else - begin - redist26_expY_uid12_fpDivTest_b_23_wraddr_q <= redist26_expY_uid12_fpDivTest_b_23_rdmux_q; - end - end - - // redist26_expY_uid12_fpDivTest_b_23_mem(DUALMEM,304) - assign redist26_expY_uid12_fpDivTest_b_23_mem_ia = expY_uid12_fpDivTest_b; - assign redist26_expY_uid12_fpDivTest_b_23_mem_aa = redist26_expY_uid12_fpDivTest_b_23_wraddr_q; - assign redist26_expY_uid12_fpDivTest_b_23_mem_ab = redist26_expY_uid12_fpDivTest_b_23_rdmux_q; - assign redist26_expY_uid12_fpDivTest_b_23_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(5), - .numwords_a(22), - .width_b(8), - .widthad_b(5), - .numwords_b(22), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist26_expY_uid12_fpDivTest_b_23_mem_dmem ( - .clocken1(redist26_expY_uid12_fpDivTest_b_23_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist26_expY_uid12_fpDivTest_b_23_mem_reset0), - .clock1(clk), - .address_a(redist26_expY_uid12_fpDivTest_b_23_mem_aa), - .data_a(redist26_expY_uid12_fpDivTest_b_23_mem_ia), - .wren_a(en[0]), - .address_b(redist26_expY_uid12_fpDivTest_b_23_mem_ab), - .q_b(redist26_expY_uid12_fpDivTest_b_23_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist26_expY_uid12_fpDivTest_b_23_mem_q = redist26_expY_uid12_fpDivTest_b_23_mem_iq[7:0]; - assign redist26_expY_uid12_fpDivTest_b_23_mem_enaOr_rst = redist26_expY_uid12_fpDivTest_b_23_enaAnd_q[0] | redist26_expY_uid12_fpDivTest_b_23_mem_reset0; - - // redist27_expY_uid12_fpDivTest_b_24(DELAY,213) - always @ (posedge clk) - begin - if (areset) - begin - redist27_expY_uid12_fpDivTest_b_24_q <= '0; - end - else if (en == 1'b1) - begin - redist27_expY_uid12_fpDivTest_b_24_q <= redist26_expY_uid12_fpDivTest_b_23_mem_q; - end - end - - // expXIsMax_uid38_fpDivTest(LOGICAL,37)@24 + 1 - assign expXIsMax_uid38_fpDivTest_qi = redist27_expY_uid12_fpDivTest_b_24_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - expXIsMax_uid38_fpDivTest_delay ( .xin(expXIsMax_uid38_fpDivTest_qi), .xout(expXIsMax_uid38_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_y_uid41_fpDivTest(LOGICAL,40)@25 - assign excI_y_uid41_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsZero_uid39_fpDivTest_q; - - // redist30_fracX_uid10_fpDivTest_b_24_notEnable(LOGICAL,346) - assign redist30_fracX_uid10_fpDivTest_b_24_notEnable_q = ~ (en); - - // redist30_fracX_uid10_fpDivTest_b_24_nor(LOGICAL,347) - assign redist30_fracX_uid10_fpDivTest_b_24_nor_q = ~ (redist30_fracX_uid10_fpDivTest_b_24_notEnable_q | redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q); - - // redist30_fracX_uid10_fpDivTest_b_24_mem_last(CONSTANT,343) - assign redist30_fracX_uid10_fpDivTest_b_24_mem_last_q = 4'b0100; - - // redist30_fracX_uid10_fpDivTest_b_24_cmp(LOGICAL,344) - assign redist30_fracX_uid10_fpDivTest_b_24_cmp_b = {1'b0, redist30_fracX_uid10_fpDivTest_b_24_rdmux_q}; - assign redist30_fracX_uid10_fpDivTest_b_24_cmp_q = redist30_fracX_uid10_fpDivTest_b_24_mem_last_q == redist30_fracX_uid10_fpDivTest_b_24_cmp_b ? 1'b1 : 1'b0; - - // redist30_fracX_uid10_fpDivTest_b_24_cmpReg(REG,345) - always @ (posedge clk) - begin - if (areset) - begin - redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q <= redist30_fracX_uid10_fpDivTest_b_24_cmp_q; - end - end - - // redist30_fracX_uid10_fpDivTest_b_24_sticky_ena(REG,348) - always @ (posedge clk) - begin - if (areset) - begin - redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q <= 1'b0; - end - else if (redist30_fracX_uid10_fpDivTest_b_24_nor_q == 1'b1) - begin - redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q <= redist30_fracX_uid10_fpDivTest_b_24_cmpReg_q; - end - end - - // redist30_fracX_uid10_fpDivTest_b_24_enaAnd(LOGICAL,349) - assign redist30_fracX_uid10_fpDivTest_b_24_enaAnd_q = redist30_fracX_uid10_fpDivTest_b_24_sticky_ena_q & en; - - // redist30_fracX_uid10_fpDivTest_b_24_rdcnt(COUNTER,340) - // low=0, high=5, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i <= 3'd0; - redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i == 3'd4) - begin - redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq <= 1'b1; - end - else - begin - redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq <= 1'b0; - end - if (redist30_fracX_uid10_fpDivTest_b_24_rdcnt_eq == 1'b1) - begin - redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i <= $unsigned(redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i) + $unsigned(3'd3); - end - else - begin - redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i <= $unsigned(redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q = redist30_fracX_uid10_fpDivTest_b_24_rdcnt_i[2:0]; - - // redist30_fracX_uid10_fpDivTest_b_24_rdmux(MUX,341) - assign redist30_fracX_uid10_fpDivTest_b_24_rdmux_s = en; - always @(redist30_fracX_uid10_fpDivTest_b_24_rdmux_s or redist30_fracX_uid10_fpDivTest_b_24_wraddr_q or redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q) - begin - unique case (redist30_fracX_uid10_fpDivTest_b_24_rdmux_s) - 1'b0 : redist30_fracX_uid10_fpDivTest_b_24_rdmux_q = redist30_fracX_uid10_fpDivTest_b_24_wraddr_q; - 1'b1 : redist30_fracX_uid10_fpDivTest_b_24_rdmux_q = redist30_fracX_uid10_fpDivTest_b_24_rdcnt_q; - default : redist30_fracX_uid10_fpDivTest_b_24_rdmux_q = 3'b0; - endcase - end - - // redist29_fracX_uid10_fpDivTest_b_17_notEnable(LOGICAL,335) - assign redist29_fracX_uid10_fpDivTest_b_17_notEnable_q = ~ (en); - - // redist29_fracX_uid10_fpDivTest_b_17_nor(LOGICAL,336) - assign redist29_fracX_uid10_fpDivTest_b_17_nor_q = ~ (redist29_fracX_uid10_fpDivTest_b_17_notEnable_q | redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q); - - // redist29_fracX_uid10_fpDivTest_b_17_mem_last(CONSTANT,332) - assign redist29_fracX_uid10_fpDivTest_b_17_mem_last_q = 5'b01101; - - // redist29_fracX_uid10_fpDivTest_b_17_cmp(LOGICAL,333) - assign redist29_fracX_uid10_fpDivTest_b_17_cmp_b = {1'b0, redist29_fracX_uid10_fpDivTest_b_17_rdmux_q}; - assign redist29_fracX_uid10_fpDivTest_b_17_cmp_q = redist29_fracX_uid10_fpDivTest_b_17_mem_last_q == redist29_fracX_uid10_fpDivTest_b_17_cmp_b ? 1'b1 : 1'b0; - - // redist29_fracX_uid10_fpDivTest_b_17_cmpReg(REG,334) - always @ (posedge clk) - begin - if (areset) - begin - redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q <= redist29_fracX_uid10_fpDivTest_b_17_cmp_q; - end - end - - // redist29_fracX_uid10_fpDivTest_b_17_sticky_ena(REG,337) - always @ (posedge clk) - begin - if (areset) - begin - redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q <= 1'b0; - end - else if (redist29_fracX_uid10_fpDivTest_b_17_nor_q == 1'b1) - begin - redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q <= redist29_fracX_uid10_fpDivTest_b_17_cmpReg_q; - end - end - - // redist29_fracX_uid10_fpDivTest_b_17_enaAnd(LOGICAL,338) - assign redist29_fracX_uid10_fpDivTest_b_17_enaAnd_q = redist29_fracX_uid10_fpDivTest_b_17_sticky_ena_q & en; - - // redist29_fracX_uid10_fpDivTest_b_17_rdcnt(COUNTER,329) - // low=0, high=14, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i <= 4'd0; - redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i == 4'd13) - begin - redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq <= 1'b1; - end - else - begin - redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq <= 1'b0; - end - if (redist29_fracX_uid10_fpDivTest_b_17_rdcnt_eq == 1'b1) - begin - redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i <= $unsigned(redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i) + $unsigned(4'd2); - end - else - begin - redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i <= $unsigned(redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i) + $unsigned(4'd1); - end - end - end - assign redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q = redist29_fracX_uid10_fpDivTest_b_17_rdcnt_i[3:0]; - - // redist29_fracX_uid10_fpDivTest_b_17_rdmux(MUX,330) - assign redist29_fracX_uid10_fpDivTest_b_17_rdmux_s = en; - always @(redist29_fracX_uid10_fpDivTest_b_17_rdmux_s or redist29_fracX_uid10_fpDivTest_b_17_wraddr_q or redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q) - begin - unique case (redist29_fracX_uid10_fpDivTest_b_17_rdmux_s) - 1'b0 : redist29_fracX_uid10_fpDivTest_b_17_rdmux_q = redist29_fracX_uid10_fpDivTest_b_17_wraddr_q; - 1'b1 : redist29_fracX_uid10_fpDivTest_b_17_rdmux_q = redist29_fracX_uid10_fpDivTest_b_17_rdcnt_q; - default : redist29_fracX_uid10_fpDivTest_b_17_rdmux_q = 4'b0; - endcase - end - - // fracX_uid10_fpDivTest(BITSELECT,9)@0 - assign fracX_uid10_fpDivTest_b = a[22:0]; - - // redist29_fracX_uid10_fpDivTest_b_17_wraddr(REG,331) - always @ (posedge clk) - begin - if (areset) - begin - redist29_fracX_uid10_fpDivTest_b_17_wraddr_q <= 4'b1110; - end - else - begin - redist29_fracX_uid10_fpDivTest_b_17_wraddr_q <= redist29_fracX_uid10_fpDivTest_b_17_rdmux_q; - end - end - - // redist29_fracX_uid10_fpDivTest_b_17_mem(DUALMEM,328) - assign redist29_fracX_uid10_fpDivTest_b_17_mem_ia = fracX_uid10_fpDivTest_b; - assign redist29_fracX_uid10_fpDivTest_b_17_mem_aa = redist29_fracX_uid10_fpDivTest_b_17_wraddr_q; - assign redist29_fracX_uid10_fpDivTest_b_17_mem_ab = redist29_fracX_uid10_fpDivTest_b_17_rdmux_q; - assign redist29_fracX_uid10_fpDivTest_b_17_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(4), - .numwords_a(15), - .width_b(23), - .widthad_b(4), - .numwords_b(15), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist29_fracX_uid10_fpDivTest_b_17_mem_dmem ( - .clocken1(redist29_fracX_uid10_fpDivTest_b_17_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist29_fracX_uid10_fpDivTest_b_17_mem_reset0), - .clock1(clk), - .address_a(redist29_fracX_uid10_fpDivTest_b_17_mem_aa), - .data_a(redist29_fracX_uid10_fpDivTest_b_17_mem_ia), - .wren_a(en[0]), - .address_b(redist29_fracX_uid10_fpDivTest_b_17_mem_ab), - .q_b(redist29_fracX_uid10_fpDivTest_b_17_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist29_fracX_uid10_fpDivTest_b_17_mem_q = redist29_fracX_uid10_fpDivTest_b_17_mem_iq[22:0]; - assign redist29_fracX_uid10_fpDivTest_b_17_mem_enaOr_rst = redist29_fracX_uid10_fpDivTest_b_17_enaAnd_q[0] | redist29_fracX_uid10_fpDivTest_b_17_mem_reset0; - - // redist29_fracX_uid10_fpDivTest_b_17_outputreg0(DELAY,327) - always @ (posedge clk) - begin - if (areset) - begin - redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q <= redist29_fracX_uid10_fpDivTest_b_17_mem_q; - end - end - - // redist30_fracX_uid10_fpDivTest_b_24_wraddr(REG,342) - always @ (posedge clk) - begin - if (areset) - begin - redist30_fracX_uid10_fpDivTest_b_24_wraddr_q <= 3'b101; - end - else - begin - redist30_fracX_uid10_fpDivTest_b_24_wraddr_q <= redist30_fracX_uid10_fpDivTest_b_24_rdmux_q; - end - end - - // redist30_fracX_uid10_fpDivTest_b_24_mem(DUALMEM,339) - assign redist30_fracX_uid10_fpDivTest_b_24_mem_ia = redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q; - assign redist30_fracX_uid10_fpDivTest_b_24_mem_aa = redist30_fracX_uid10_fpDivTest_b_24_wraddr_q; - assign redist30_fracX_uid10_fpDivTest_b_24_mem_ab = redist30_fracX_uid10_fpDivTest_b_24_rdmux_q; - assign redist30_fracX_uid10_fpDivTest_b_24_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(3), - .numwords_a(6), - .width_b(23), - .widthad_b(3), - .numwords_b(6), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist30_fracX_uid10_fpDivTest_b_24_mem_dmem ( - .clocken1(redist30_fracX_uid10_fpDivTest_b_24_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist30_fracX_uid10_fpDivTest_b_24_mem_reset0), - .clock1(clk), - .address_a(redist30_fracX_uid10_fpDivTest_b_24_mem_aa), - .data_a(redist30_fracX_uid10_fpDivTest_b_24_mem_ia), - .wren_a(en[0]), - .address_b(redist30_fracX_uid10_fpDivTest_b_24_mem_ab), - .q_b(redist30_fracX_uid10_fpDivTest_b_24_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist30_fracX_uid10_fpDivTest_b_24_mem_q = redist30_fracX_uid10_fpDivTest_b_24_mem_iq[22:0]; - assign redist30_fracX_uid10_fpDivTest_b_24_mem_enaOr_rst = redist30_fracX_uid10_fpDivTest_b_24_enaAnd_q[0] | redist30_fracX_uid10_fpDivTest_b_24_mem_reset0; - - // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@24 + 1 - assign fracXIsZero_uid25_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist30_fracX_uid10_fpDivTest_b_24_mem_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - fracXIsZero_uid25_fpDivTest_delay ( .xin(fracXIsZero_uid25_fpDivTest_qi), .xout(fracXIsZero_uid25_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist33_expX_uid9_fpDivTest_b_23_notEnable(LOGICAL,368) - assign redist33_expX_uid9_fpDivTest_b_23_notEnable_q = ~ (en); - - // redist33_expX_uid9_fpDivTest_b_23_nor(LOGICAL,369) - assign redist33_expX_uid9_fpDivTest_b_23_nor_q = ~ (redist33_expX_uid9_fpDivTest_b_23_notEnable_q | redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q); - - // redist33_expX_uid9_fpDivTest_b_23_mem_last(CONSTANT,365) - assign redist33_expX_uid9_fpDivTest_b_23_mem_last_q = 6'b010100; - - // redist33_expX_uid9_fpDivTest_b_23_cmp(LOGICAL,366) - assign redist33_expX_uid9_fpDivTest_b_23_cmp_b = {1'b0, redist33_expX_uid9_fpDivTest_b_23_rdmux_q}; - assign redist33_expX_uid9_fpDivTest_b_23_cmp_q = redist33_expX_uid9_fpDivTest_b_23_mem_last_q == redist33_expX_uid9_fpDivTest_b_23_cmp_b ? 1'b1 : 1'b0; - - // redist33_expX_uid9_fpDivTest_b_23_cmpReg(REG,367) - always @ (posedge clk) - begin - if (areset) - begin - redist33_expX_uid9_fpDivTest_b_23_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist33_expX_uid9_fpDivTest_b_23_cmpReg_q <= redist33_expX_uid9_fpDivTest_b_23_cmp_q; - end - end - - // redist33_expX_uid9_fpDivTest_b_23_sticky_ena(REG,370) - always @ (posedge clk) - begin - if (areset) - begin - redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q <= 1'b0; - end - else if (redist33_expX_uid9_fpDivTest_b_23_nor_q == 1'b1) - begin - redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q <= redist33_expX_uid9_fpDivTest_b_23_cmpReg_q; - end - end - - // redist33_expX_uid9_fpDivTest_b_23_enaAnd(LOGICAL,371) - assign redist33_expX_uid9_fpDivTest_b_23_enaAnd_q = redist33_expX_uid9_fpDivTest_b_23_sticky_ena_q & en; - - // redist33_expX_uid9_fpDivTest_b_23_rdcnt(COUNTER,362) - // low=0, high=21, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist33_expX_uid9_fpDivTest_b_23_rdcnt_i <= 5'd0; - redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist33_expX_uid9_fpDivTest_b_23_rdcnt_i == 5'd20) - begin - redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq <= 1'b1; - end - else - begin - redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq <= 1'b0; - end - if (redist33_expX_uid9_fpDivTest_b_23_rdcnt_eq == 1'b1) - begin - redist33_expX_uid9_fpDivTest_b_23_rdcnt_i <= $unsigned(redist33_expX_uid9_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd11); - end - else - begin - redist33_expX_uid9_fpDivTest_b_23_rdcnt_i <= $unsigned(redist33_expX_uid9_fpDivTest_b_23_rdcnt_i) + $unsigned(5'd1); - end - end - end - assign redist33_expX_uid9_fpDivTest_b_23_rdcnt_q = redist33_expX_uid9_fpDivTest_b_23_rdcnt_i[4:0]; - - // redist33_expX_uid9_fpDivTest_b_23_rdmux(MUX,363) - assign redist33_expX_uid9_fpDivTest_b_23_rdmux_s = en; - always @(redist33_expX_uid9_fpDivTest_b_23_rdmux_s or redist33_expX_uid9_fpDivTest_b_23_wraddr_q or redist33_expX_uid9_fpDivTest_b_23_rdcnt_q) - begin - unique case (redist33_expX_uid9_fpDivTest_b_23_rdmux_s) - 1'b0 : redist33_expX_uid9_fpDivTest_b_23_rdmux_q = redist33_expX_uid9_fpDivTest_b_23_wraddr_q; - 1'b1 : redist33_expX_uid9_fpDivTest_b_23_rdmux_q = redist33_expX_uid9_fpDivTest_b_23_rdcnt_q; - default : redist33_expX_uid9_fpDivTest_b_23_rdmux_q = 5'b0; - endcase - end - - // expX_uid9_fpDivTest(BITSELECT,8)@0 - assign expX_uid9_fpDivTest_b = a[30:23]; - - // redist33_expX_uid9_fpDivTest_b_23_wraddr(REG,364) - always @ (posedge clk) - begin - if (areset) - begin - redist33_expX_uid9_fpDivTest_b_23_wraddr_q <= 5'b10101; - end - else - begin - redist33_expX_uid9_fpDivTest_b_23_wraddr_q <= redist33_expX_uid9_fpDivTest_b_23_rdmux_q; - end - end - - // redist33_expX_uid9_fpDivTest_b_23_mem(DUALMEM,361) - assign redist33_expX_uid9_fpDivTest_b_23_mem_ia = expX_uid9_fpDivTest_b; - assign redist33_expX_uid9_fpDivTest_b_23_mem_aa = redist33_expX_uid9_fpDivTest_b_23_wraddr_q; - assign redist33_expX_uid9_fpDivTest_b_23_mem_ab = redist33_expX_uid9_fpDivTest_b_23_rdmux_q; - assign redist33_expX_uid9_fpDivTest_b_23_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(5), - .numwords_a(22), - .width_b(8), - .widthad_b(5), - .numwords_b(22), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist33_expX_uid9_fpDivTest_b_23_mem_dmem ( - .clocken1(redist33_expX_uid9_fpDivTest_b_23_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist33_expX_uid9_fpDivTest_b_23_mem_reset0), - .clock1(clk), - .address_a(redist33_expX_uid9_fpDivTest_b_23_mem_aa), - .data_a(redist33_expX_uid9_fpDivTest_b_23_mem_ia), - .wren_a(en[0]), - .address_b(redist33_expX_uid9_fpDivTest_b_23_mem_ab), - .q_b(redist33_expX_uid9_fpDivTest_b_23_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist33_expX_uid9_fpDivTest_b_23_mem_q = redist33_expX_uid9_fpDivTest_b_23_mem_iq[7:0]; - assign redist33_expX_uid9_fpDivTest_b_23_mem_enaOr_rst = redist33_expX_uid9_fpDivTest_b_23_enaAnd_q[0] | redist33_expX_uid9_fpDivTest_b_23_mem_reset0; - - // redist34_expX_uid9_fpDivTest_b_24(DELAY,220) - always @ (posedge clk) - begin - if (areset) - begin - redist34_expX_uid9_fpDivTest_b_24_q <= '0; - end - else if (en == 1'b1) - begin - redist34_expX_uid9_fpDivTest_b_24_q <= redist33_expX_uid9_fpDivTest_b_23_mem_q; - end - end - - // expXIsMax_uid24_fpDivTest(LOGICAL,23)@24 - assign expXIsMax_uid24_fpDivTest_q = redist34_expX_uid9_fpDivTest_b_24_q == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; - - // redist21_expXIsMax_uid24_fpDivTest_q_1(DELAY,207) - always @ (posedge clk) - begin - if (areset) - begin - redist21_expXIsMax_uid24_fpDivTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist21_expXIsMax_uid24_fpDivTest_q_1_q <= expXIsMax_uid24_fpDivTest_q; - end - end - - // excI_x_uid27_fpDivTest(LOGICAL,26)@25 - assign excI_x_uid27_fpDivTest_q = redist21_expXIsMax_uid24_fpDivTest_q_1_q & fracXIsZero_uid25_fpDivTest_q; - - // excXIYI_uid130_fpDivTest(LOGICAL,129)@25 - assign excXIYI_uid130_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; - - // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@25 - assign fracXIsNotZero_uid40_fpDivTest_q = ~ (fracXIsZero_uid39_fpDivTest_q); - - // excN_y_uid42_fpDivTest(LOGICAL,41)@25 - assign excN_y_uid42_fpDivTest_q = expXIsMax_uid38_fpDivTest_q & fracXIsNotZero_uid40_fpDivTest_q; - - // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@25 - assign fracXIsNotZero_uid26_fpDivTest_q = ~ (fracXIsZero_uid25_fpDivTest_q); - - // excN_x_uid28_fpDivTest(LOGICAL,27)@25 - assign excN_x_uid28_fpDivTest_q = redist21_expXIsMax_uid24_fpDivTest_q_1_q & fracXIsNotZero_uid26_fpDivTest_q; - - // cstAllZWE_uid20_fpDivTest(CONSTANT,19) - assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; - - // excZ_y_uid37_fpDivTest(LOGICAL,36)@24 + 1 - assign excZ_y_uid37_fpDivTest_qi = redist27_expY_uid12_fpDivTest_b_24_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - excZ_y_uid37_fpDivTest_delay ( .xin(excZ_y_uid37_fpDivTest_qi), .xout(excZ_y_uid37_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excZ_x_uid23_fpDivTest(LOGICAL,22)@24 - assign excZ_x_uid23_fpDivTest_q = redist34_expX_uid9_fpDivTest_b_24_q == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; - - // redist22_excZ_x_uid23_fpDivTest_q_1(DELAY,208) - always @ (posedge clk) - begin - if (areset) - begin - redist22_excZ_x_uid23_fpDivTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist22_excZ_x_uid23_fpDivTest_q_1_q <= excZ_x_uid23_fpDivTest_q; - end - end - - // excXZYZ_uid129_fpDivTest(LOGICAL,128)@25 - assign excXZYZ_uid129_fpDivTest_q = redist22_excZ_x_uid23_fpDivTest_q_1_q & excZ_y_uid37_fpDivTest_q; - - // excRNaN_uid131_fpDivTest(LOGICAL,130)@25 - assign excRNaN_uid131_fpDivTest_q = excXZYZ_uid129_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid130_fpDivTest_q; - - // invExcRNaN_uid142_fpDivTest(LOGICAL,141)@25 - assign invExcRNaN_uid142_fpDivTest_q = ~ (excRNaN_uid131_fpDivTest_q); - - // signY_uid14_fpDivTest(BITSELECT,13)@0 - assign signY_uid14_fpDivTest_b = b[31:31]; - - // signX_uid11_fpDivTest(BITSELECT,10)@0 - assign signX_uid11_fpDivTest_b = a[31:31]; - - // signR_uid46_fpDivTest(LOGICAL,45)@0 + 1 - assign signR_uid46_fpDivTest_qi = signX_uid11_fpDivTest_b ^ signY_uid14_fpDivTest_b; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist20_signR_uid46_fpDivTest_q_25(DELAY,206) - dspba_delay_ver #( .width(1), .depth(24), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist20_signR_uid46_fpDivTest_q_25 ( .xin(signR_uid46_fpDivTest_q), .xout(redist20_signR_uid46_fpDivTest_q_25_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // sRPostExc_uid143_fpDivTest(LOGICAL,142)@25 + 1 - assign sRPostExc_uid143_fpDivTest_qi = redist20_signR_uid46_fpDivTest_q_25_q & invExcRNaN_uid142_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - sRPostExc_uid143_fpDivTest_delay ( .xin(sRPostExc_uid143_fpDivTest_qi), .xout(sRPostExc_uid143_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist2_sRPostExc_uid143_fpDivTest_q_9(DELAY,188) - dspba_delay_ver #( .width(1), .depth(8), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist2_sRPostExc_uid143_fpDivTest_q_9 ( .xin(sRPostExc_uid143_fpDivTest_q), .xout(redist2_sRPostExc_uid143_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable(LOGICAL,230) - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable_q = ~ (en); - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor(LOGICAL,231) - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor_q = ~ (redist4_fracPostRndFT_uid104_fpDivTest_b_8_notEnable_q | redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q); - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last(CONSTANT,227) - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last_q = 4'b0101; - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp(LOGICAL,228) - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_b = {1'b0, redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q}; - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_last_q == redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_b ? 1'b1 : 1'b0; - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg(REG,229) - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmp_q; - end - end - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena(REG,232) - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q <= 1'b0; - end - else if (redist4_fracPostRndFT_uid104_fpDivTest_b_8_nor_q == 1'b1) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_cmpReg_q; - end - end - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd(LOGICAL,233) - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_sticky_ena_q & en; - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt(COUNTER,224) - // low=0, high=6, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i <= 3'd0; - redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i == 3'd5) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq <= 1'b1; - end - else - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq <= 1'b0; - end - if (redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_eq == 1'b1) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i <= $unsigned(redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i) + $unsigned(3'd2); - end - else - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i <= $unsigned(redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_i[2:0]; - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux(MUX,225) - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s = en; - always @(redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s or redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q or redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q) - begin - unique case (redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_s) - 1'b0 : redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q; - 1'b1 : redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdcnt_q; - default : redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q = 3'b0; - endcase - end - - // redist31_fracX_uid10_fpDivTest_b_25(DELAY,217) - always @ (posedge clk) - begin - if (areset) - begin - redist31_fracX_uid10_fpDivTest_b_25_q <= '0; - end - else if (en == 1'b1) - begin - redist31_fracX_uid10_fpDivTest_b_25_q <= redist30_fracX_uid10_fpDivTest_b_24_mem_q; - end - end - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // fracXExt_uid77_fpDivTest(BITJOIN,76)@25 - assign fracXExt_uid77_fpDivTest_q = {redist31_fracX_uid10_fpDivTest_b_25_q, GND_q}; - - // redist12_lOAdded_uid57_fpDivTest_q_6_notEnable(LOGICAL,253) - assign redist12_lOAdded_uid57_fpDivTest_q_6_notEnable_q = ~ (en); - - // redist12_lOAdded_uid57_fpDivTest_q_6_nor(LOGICAL,254) - assign redist12_lOAdded_uid57_fpDivTest_q_6_nor_q = ~ (redist12_lOAdded_uid57_fpDivTest_q_6_notEnable_q | redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q); - - // redist12_lOAdded_uid57_fpDivTest_q_6_mem_last(CONSTANT,250) - assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_last_q = 3'b011; - - // redist12_lOAdded_uid57_fpDivTest_q_6_cmp(LOGICAL,251) - assign redist12_lOAdded_uid57_fpDivTest_q_6_cmp_q = redist12_lOAdded_uid57_fpDivTest_q_6_mem_last_q == redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q ? 1'b1 : 1'b0; - - // redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg(REG,252) - always @ (posedge clk) - begin - if (areset) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q <= redist12_lOAdded_uid57_fpDivTest_q_6_cmp_q; - end - end - - // redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena(REG,255) - always @ (posedge clk) - begin - if (areset) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q <= 1'b0; - end - else if (redist12_lOAdded_uid57_fpDivTest_q_6_nor_q == 1'b1) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q <= redist12_lOAdded_uid57_fpDivTest_q_6_cmpReg_q; - end - end - - // redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd(LOGICAL,256) - assign redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd_q = redist12_lOAdded_uid57_fpDivTest_q_6_sticky_ena_q & en; - - // redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt(COUNTER,247) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i <= 3'd0; - redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i == 3'd3) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq <= 1'b1; - end - else - begin - redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq <= 1'b0; - end - if (redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_eq == 1'b1) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i <= $unsigned(redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i <= $unsigned(redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q = redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_i[2:0]; - - // redist12_lOAdded_uid57_fpDivTest_q_6_rdmux(MUX,248) - assign redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s = en; - always @(redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s or redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q or redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q) - begin - unique case (redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_s) - 1'b0 : redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q = redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q; - 1'b1 : redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q = redist12_lOAdded_uid57_fpDivTest_q_6_rdcnt_q; - default : redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q = 3'b0; - endcase - end - - // lOAdded_uid57_fpDivTest(BITJOIN,56)@17 - assign lOAdded_uid57_fpDivTest_q = {VCC_q, redist29_fracX_uid10_fpDivTest_b_17_outputreg0_q}; - - // redist12_lOAdded_uid57_fpDivTest_q_6_wraddr(REG,249) - always @ (posedge clk) - begin - if (areset) - begin - redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q <= 3'b100; - end - else - begin - redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q <= redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q; - end - end - - // redist12_lOAdded_uid57_fpDivTest_q_6_mem(DUALMEM,246) - assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_ia = lOAdded_uid57_fpDivTest_q; - assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_aa = redist12_lOAdded_uid57_fpDivTest_q_6_wraddr_q; - assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_ab = redist12_lOAdded_uid57_fpDivTest_q_6_rdmux_q; - assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(24), - .widthad_a(3), - .numwords_a(5), - .width_b(24), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist12_lOAdded_uid57_fpDivTest_q_6_mem_dmem ( - .clocken1(redist12_lOAdded_uid57_fpDivTest_q_6_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0), - .clock1(clk), - .address_a(redist12_lOAdded_uid57_fpDivTest_q_6_mem_aa), - .data_a(redist12_lOAdded_uid57_fpDivTest_q_6_mem_ia), - .wren_a(en[0]), - .address_b(redist12_lOAdded_uid57_fpDivTest_q_6_mem_ab), - .q_b(redist12_lOAdded_uid57_fpDivTest_q_6_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_q = redist12_lOAdded_uid57_fpDivTest_q_6_mem_iq[23:0]; - assign redist12_lOAdded_uid57_fpDivTest_q_6_mem_enaOr_rst = redist12_lOAdded_uid57_fpDivTest_q_6_enaAnd_q[0] | redist12_lOAdded_uid57_fpDivTest_q_6_mem_reset0; - - // z4_uid60_fpDivTest(CONSTANT,59) - assign z4_uid60_fpDivTest_q = 4'b0000; - - // oFracXZ4_uid61_fpDivTest(BITJOIN,60)@23 - assign oFracXZ4_uid61_fpDivTest_q = {redist12_lOAdded_uid57_fpDivTest_q_6_mem_q, z4_uid60_fpDivTest_q}; - - // yAddr_uid51_fpDivTest(BITSELECT,50)@0 - assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; - - // memoryC2_uid152_invTables_lutmem(DUALMEM,181)@0 + 2 - // in j@20000000 - assign memoryC2_uid152_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; - assign memoryC2_uid152_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(13), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_sclr_a("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC2_uid152_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Stratix 10") - ) memoryC2_uid152_invTables_lutmem_dmem ( - .clocken0(en[0]), - .sclr(memoryC2_uid152_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC2_uid152_invTables_lutmem_aa), - .q_a(memoryC2_uid152_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC2_uid152_invTables_lutmem_r = memoryC2_uid152_invTables_lutmem_ir[12:0]; - assign memoryC2_uid152_invTables_lutmem_enaOr_rst = en[0] | memoryC2_uid152_invTables_lutmem_reset0; - - // redist0_memoryC2_uid152_invTables_lutmem_r_1(DELAY,186) - always @ (posedge clk) - begin - if (areset) - begin - redist0_memoryC2_uid152_invTables_lutmem_r_1_q <= '0; - end - else if (en == 1'b1) - begin - redist0_memoryC2_uid152_invTables_lutmem_r_1_q <= memoryC2_uid152_invTables_lutmem_r; - end - end - - // yPE_uid52_fpDivTest(BITSELECT,51)@0 - assign yPE_uid52_fpDivTest_b = b[13:0]; - - // redist16_yPE_uid52_fpDivTest_b_3(DELAY,202) - always @ (posedge clk) - begin - if (areset) - begin - redist16_yPE_uid52_fpDivTest_b_3_delay_0 <= '0; - redist16_yPE_uid52_fpDivTest_b_3_delay_1 <= '0; - redist16_yPE_uid52_fpDivTest_b_3_q <= '0; - end - else if (en == 1'b1) - begin - redist16_yPE_uid52_fpDivTest_b_3_delay_0 <= yPE_uid52_fpDivTest_b; - redist16_yPE_uid52_fpDivTest_b_3_delay_1 <= redist16_yPE_uid52_fpDivTest_b_3_delay_0; - redist16_yPE_uid52_fpDivTest_b_3_q <= redist16_yPE_uid52_fpDivTest_b_3_delay_1; - end - end - - // yT1_uid158_invPolyEval(BITSELECT,157)@3 - assign yT1_uid158_invPolyEval_b = redist16_yPE_uid52_fpDivTest_b_3_q[13:1]; - - // prodXY_uid174_pT1_uid159_invPolyEval_cma(CHAINMULTADD,184)@3 + 5 - // out q@9 - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_reset = areset; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 = en[0] | prodXY_uid174_pT1_uid159_invPolyEval_cma_reset; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0; - always @ (posedge clk) - begin - if (0) - begin - end - else - begin - if (en == 1'b1) - begin - prodXY_uid174_pT1_uid159_invPolyEval_cma_ah[0] <= yT1_uid158_invPolyEval_b; - prodXY_uid174_pT1_uid159_invPolyEval_cma_ch[0] <= redist0_memoryC2_uid152_invTables_lutmem_r_1_q; - end - end - end - - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_a0 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ah[0]; - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_c0 = prodXY_uid174_pT1_uid159_invPolyEval_cma_ch[0]; - fourteennm_mac #( - .operation_mode("m18x18_full"), - .clear_type("sclr"), - .ay_scan_in_clock("0"), - .ay_scan_in_width(13), - .ax_clock("0"), - .ax_width(13), - .signed_may("false"), - .signed_max("true"), - .input_pipeline_clock("2"), - .second_pipeline_clock("2"), - .output_clock("1"), - .result_a_width(26) - ) prodXY_uid174_pT1_uid159_invPolyEval_cma_DSP0 ( - .clk({clk,clk,clk}), - .ena({ prodXY_uid174_pT1_uid159_invPolyEval_cma_ena2, prodXY_uid174_pT1_uid159_invPolyEval_cma_ena1, prodXY_uid174_pT1_uid159_invPolyEval_cma_ena0 }), - .clr({ prodXY_uid174_pT1_uid159_invPolyEval_cma_reset, prodXY_uid174_pT1_uid159_invPolyEval_cma_reset }), - .ay(prodXY_uid174_pT1_uid159_invPolyEval_cma_a0), - .ax(prodXY_uid174_pT1_uid159_invPolyEval_cma_c0), - .resulta(prodXY_uid174_pT1_uid159_invPolyEval_cma_s0), - .accumulate(), - .loadconst(), - .negate(), - .sub(), - .az(), - .coefsela(), - .bx(), - .by(), - .bz(), - .coefselb(), - .scanin(), - .scanout(), - .chainin(), - .chainout(), - .resultb(), - .dfxlfsrena(), - .dfxmisrena(), - .dftout() - ); - dspba_delay_ver #( .width(26), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) - prodXY_uid174_pT1_uid159_invPolyEval_cma_delay ( .xin(prodXY_uid174_pT1_uid159_invPolyEval_cma_s0), .xout(prodXY_uid174_pT1_uid159_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid174_pT1_uid159_invPolyEval_cma_q = prodXY_uid174_pT1_uid159_invPolyEval_cma_qq[25:0]; - - // osig_uid175_pT1_uid159_invPolyEval(BITSELECT,174)@9 - assign osig_uid175_pT1_uid159_invPolyEval_b = prodXY_uid174_pT1_uid159_invPolyEval_cma_q[25:12]; - - // highBBits_uid161_invPolyEval(BITSELECT,160)@9 - assign highBBits_uid161_invPolyEval_b = osig_uid175_pT1_uid159_invPolyEval_b[13:1]; - - // redist18_yAddr_uid51_fpDivTest_b_7_notEnable(LOGICAL,277) - assign redist18_yAddr_uid51_fpDivTest_b_7_notEnable_q = ~ (en); - - // redist18_yAddr_uid51_fpDivTest_b_7_nor(LOGICAL,278) - assign redist18_yAddr_uid51_fpDivTest_b_7_nor_q = ~ (redist18_yAddr_uid51_fpDivTest_b_7_notEnable_q | redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q); - - // redist18_yAddr_uid51_fpDivTest_b_7_mem_last(CONSTANT,274) - assign redist18_yAddr_uid51_fpDivTest_b_7_mem_last_q = 3'b011; - - // redist18_yAddr_uid51_fpDivTest_b_7_cmp(LOGICAL,275) - assign redist18_yAddr_uid51_fpDivTest_b_7_cmp_q = redist18_yAddr_uid51_fpDivTest_b_7_mem_last_q == redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q ? 1'b1 : 1'b0; - - // redist18_yAddr_uid51_fpDivTest_b_7_cmpReg(REG,276) - always @ (posedge clk) - begin - if (areset) - begin - redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q <= redist18_yAddr_uid51_fpDivTest_b_7_cmp_q; - end - end - - // redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena(REG,279) - always @ (posedge clk) - begin - if (areset) - begin - redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q <= 1'b0; - end - else if (redist18_yAddr_uid51_fpDivTest_b_7_nor_q == 1'b1) - begin - redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q <= redist18_yAddr_uid51_fpDivTest_b_7_cmpReg_q; - end - end - - // redist18_yAddr_uid51_fpDivTest_b_7_enaAnd(LOGICAL,280) - assign redist18_yAddr_uid51_fpDivTest_b_7_enaAnd_q = redist18_yAddr_uid51_fpDivTest_b_7_sticky_ena_q & en; - - // redist18_yAddr_uid51_fpDivTest_b_7_rdcnt(COUNTER,271) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i <= 3'd0; - redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i == 3'd3) - begin - redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq <= 1'b1; - end - else - begin - redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq <= 1'b0; - end - if (redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_eq == 1'b1) - begin - redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i <= $unsigned(redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i <= $unsigned(redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q = redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_i[2:0]; - - // redist18_yAddr_uid51_fpDivTest_b_7_rdmux(MUX,272) - assign redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s = en; - always @(redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s or redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q or redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q) - begin - unique case (redist18_yAddr_uid51_fpDivTest_b_7_rdmux_s) - 1'b0 : redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q = redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q; - 1'b1 : redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q = redist18_yAddr_uid51_fpDivTest_b_7_rdcnt_q; - default : redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q = 3'b0; - endcase - end - - // redist18_yAddr_uid51_fpDivTest_b_7_wraddr(REG,273) - always @ (posedge clk) - begin - if (areset) - begin - redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q <= 3'b100; - end - else - begin - redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q <= redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q; - end - end - - // redist18_yAddr_uid51_fpDivTest_b_7_mem(DUALMEM,270) - assign redist18_yAddr_uid51_fpDivTest_b_7_mem_ia = yAddr_uid51_fpDivTest_b; - assign redist18_yAddr_uid51_fpDivTest_b_7_mem_aa = redist18_yAddr_uid51_fpDivTest_b_7_wraddr_q; - assign redist18_yAddr_uid51_fpDivTest_b_7_mem_ab = redist18_yAddr_uid51_fpDivTest_b_7_rdmux_q; - assign redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(9), - .widthad_a(3), - .numwords_a(5), - .width_b(9), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist18_yAddr_uid51_fpDivTest_b_7_mem_dmem ( - .clocken1(redist18_yAddr_uid51_fpDivTest_b_7_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0), - .clock1(clk), - .address_a(redist18_yAddr_uid51_fpDivTest_b_7_mem_aa), - .data_a(redist18_yAddr_uid51_fpDivTest_b_7_mem_ia), - .wren_a(en[0]), - .address_b(redist18_yAddr_uid51_fpDivTest_b_7_mem_ab), - .q_b(redist18_yAddr_uid51_fpDivTest_b_7_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist18_yAddr_uid51_fpDivTest_b_7_mem_q = redist18_yAddr_uid51_fpDivTest_b_7_mem_iq[8:0]; - assign redist18_yAddr_uid51_fpDivTest_b_7_mem_enaOr_rst = redist18_yAddr_uid51_fpDivTest_b_7_enaAnd_q[0] | redist18_yAddr_uid51_fpDivTest_b_7_mem_reset0; - - // redist18_yAddr_uid51_fpDivTest_b_7_outputreg0(DELAY,269) - always @ (posedge clk) - begin - if (areset) - begin - redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q <= redist18_yAddr_uid51_fpDivTest_b_7_mem_q; - end - end - - // memoryC1_uid149_invTables_lutmem(DUALMEM,180)@7 + 2 - // in j@20000000 - assign memoryC1_uid149_invTables_lutmem_aa = redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q; - assign memoryC1_uid149_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(22), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_sclr_a("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC1_uid149_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Stratix 10") - ) memoryC1_uid149_invTables_lutmem_dmem ( - .clocken0(en[0]), - .sclr(memoryC1_uid149_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC1_uid149_invTables_lutmem_aa), - .q_a(memoryC1_uid149_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC1_uid149_invTables_lutmem_r = memoryC1_uid149_invTables_lutmem_ir[21:0]; - assign memoryC1_uid149_invTables_lutmem_enaOr_rst = en[0] | memoryC1_uid149_invTables_lutmem_reset0; - - // s1sumAHighB_uid162_invPolyEval(ADD,161)@9 + 1 - assign s1sumAHighB_uid162_invPolyEval_a = {{1{memoryC1_uid149_invTables_lutmem_r[21]}}, memoryC1_uid149_invTables_lutmem_r}; - assign s1sumAHighB_uid162_invPolyEval_b = {{10{highBBits_uid161_invPolyEval_b[12]}}, highBBits_uid161_invPolyEval_b}; - always @ (posedge clk) - begin - if (areset) - begin - s1sumAHighB_uid162_invPolyEval_o <= 23'b0; - end - else if (en == 1'b1) - begin - s1sumAHighB_uid162_invPolyEval_o <= $signed(s1sumAHighB_uid162_invPolyEval_a) + $signed(s1sumAHighB_uid162_invPolyEval_b); - end - end - assign s1sumAHighB_uid162_invPolyEval_q = s1sumAHighB_uid162_invPolyEval_o[22:0]; - - // lowRangeB_uid160_invPolyEval(BITSELECT,159)@9 - assign lowRangeB_uid160_invPolyEval_in = osig_uid175_pT1_uid159_invPolyEval_b[0:0]; - assign lowRangeB_uid160_invPolyEval_b = lowRangeB_uid160_invPolyEval_in[0:0]; - - // redist1_lowRangeB_uid160_invPolyEval_b_1(DELAY,187) - always @ (posedge clk) - begin - if (areset) - begin - redist1_lowRangeB_uid160_invPolyEval_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist1_lowRangeB_uid160_invPolyEval_b_1_q <= lowRangeB_uid160_invPolyEval_b; - end - end - - // s1_uid163_invPolyEval(BITJOIN,162)@10 - assign s1_uid163_invPolyEval_q = {s1sumAHighB_uid162_invPolyEval_q, redist1_lowRangeB_uid160_invPolyEval_b_1_q}; - - // redist17_yPE_uid52_fpDivTest_b_10_notEnable(LOGICAL,265) - assign redist17_yPE_uid52_fpDivTest_b_10_notEnable_q = ~ (en); - - // redist17_yPE_uid52_fpDivTest_b_10_nor(LOGICAL,266) - assign redist17_yPE_uid52_fpDivTest_b_10_nor_q = ~ (redist17_yPE_uid52_fpDivTest_b_10_notEnable_q | redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q); - - // redist17_yPE_uid52_fpDivTest_b_10_mem_last(CONSTANT,262) - assign redist17_yPE_uid52_fpDivTest_b_10_mem_last_q = 3'b011; - - // redist17_yPE_uid52_fpDivTest_b_10_cmp(LOGICAL,263) - assign redist17_yPE_uid52_fpDivTest_b_10_cmp_q = redist17_yPE_uid52_fpDivTest_b_10_mem_last_q == redist17_yPE_uid52_fpDivTest_b_10_rdmux_q ? 1'b1 : 1'b0; - - // redist17_yPE_uid52_fpDivTest_b_10_cmpReg(REG,264) - always @ (posedge clk) - begin - if (areset) - begin - redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q <= redist17_yPE_uid52_fpDivTest_b_10_cmp_q; - end - end - - // redist17_yPE_uid52_fpDivTest_b_10_sticky_ena(REG,267) - always @ (posedge clk) - begin - if (areset) - begin - redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q <= 1'b0; - end - else if (redist17_yPE_uid52_fpDivTest_b_10_nor_q == 1'b1) - begin - redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q <= redist17_yPE_uid52_fpDivTest_b_10_cmpReg_q; - end - end - - // redist17_yPE_uid52_fpDivTest_b_10_enaAnd(LOGICAL,268) - assign redist17_yPE_uid52_fpDivTest_b_10_enaAnd_q = redist17_yPE_uid52_fpDivTest_b_10_sticky_ena_q & en; - - // redist17_yPE_uid52_fpDivTest_b_10_rdcnt(COUNTER,259) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i <= 3'd0; - redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i == 3'd3) - begin - redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq <= 1'b1; - end - else - begin - redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq <= 1'b0; - end - if (redist17_yPE_uid52_fpDivTest_b_10_rdcnt_eq == 1'b1) - begin - redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i <= $unsigned(redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i <= $unsigned(redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q = redist17_yPE_uid52_fpDivTest_b_10_rdcnt_i[2:0]; - - // redist17_yPE_uid52_fpDivTest_b_10_rdmux(MUX,260) - assign redist17_yPE_uid52_fpDivTest_b_10_rdmux_s = en; - always @(redist17_yPE_uid52_fpDivTest_b_10_rdmux_s or redist17_yPE_uid52_fpDivTest_b_10_wraddr_q or redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q) - begin - unique case (redist17_yPE_uid52_fpDivTest_b_10_rdmux_s) - 1'b0 : redist17_yPE_uid52_fpDivTest_b_10_rdmux_q = redist17_yPE_uid52_fpDivTest_b_10_wraddr_q; - 1'b1 : redist17_yPE_uid52_fpDivTest_b_10_rdmux_q = redist17_yPE_uid52_fpDivTest_b_10_rdcnt_q; - default : redist17_yPE_uid52_fpDivTest_b_10_rdmux_q = 3'b0; - endcase - end - - // redist17_yPE_uid52_fpDivTest_b_10_wraddr(REG,261) - always @ (posedge clk) - begin - if (areset) - begin - redist17_yPE_uid52_fpDivTest_b_10_wraddr_q <= 3'b100; - end - else - begin - redist17_yPE_uid52_fpDivTest_b_10_wraddr_q <= redist17_yPE_uid52_fpDivTest_b_10_rdmux_q; - end - end - - // redist17_yPE_uid52_fpDivTest_b_10_mem(DUALMEM,258) - assign redist17_yPE_uid52_fpDivTest_b_10_mem_ia = redist16_yPE_uid52_fpDivTest_b_3_q; - assign redist17_yPE_uid52_fpDivTest_b_10_mem_aa = redist17_yPE_uid52_fpDivTest_b_10_wraddr_q; - assign redist17_yPE_uid52_fpDivTest_b_10_mem_ab = redist17_yPE_uid52_fpDivTest_b_10_rdmux_q; - assign redist17_yPE_uid52_fpDivTest_b_10_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(14), - .widthad_a(3), - .numwords_a(5), - .width_b(14), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist17_yPE_uid52_fpDivTest_b_10_mem_dmem ( - .clocken1(redist17_yPE_uid52_fpDivTest_b_10_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist17_yPE_uid52_fpDivTest_b_10_mem_reset0), - .clock1(clk), - .address_a(redist17_yPE_uid52_fpDivTest_b_10_mem_aa), - .data_a(redist17_yPE_uid52_fpDivTest_b_10_mem_ia), - .wren_a(en[0]), - .address_b(redist17_yPE_uid52_fpDivTest_b_10_mem_ab), - .q_b(redist17_yPE_uid52_fpDivTest_b_10_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist17_yPE_uid52_fpDivTest_b_10_mem_q = redist17_yPE_uid52_fpDivTest_b_10_mem_iq[13:0]; - assign redist17_yPE_uid52_fpDivTest_b_10_mem_enaOr_rst = redist17_yPE_uid52_fpDivTest_b_10_enaAnd_q[0] | redist17_yPE_uid52_fpDivTest_b_10_mem_reset0; - - // redist17_yPE_uid52_fpDivTest_b_10_outputreg0(DELAY,257) - always @ (posedge clk) - begin - if (areset) - begin - redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q <= redist17_yPE_uid52_fpDivTest_b_10_mem_q; - end - end - - // prodXY_uid177_pT2_uid165_invPolyEval_cma(CHAINMULTADD,185)@10 + 5 - // out q@16 - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_reset = areset; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 = en[0] | prodXY_uid177_pT2_uid165_invPolyEval_cma_reset; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0; - always @ (posedge clk) - begin - if (0) - begin - end - else - begin - if (en == 1'b1) - begin - prodXY_uid177_pT2_uid165_invPolyEval_cma_ah[0] <= redist17_yPE_uid52_fpDivTest_b_10_outputreg0_q; - prodXY_uid177_pT2_uid165_invPolyEval_cma_ch[0] <= s1_uid163_invPolyEval_q; - end - end - end - - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_a0 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ah[0]; - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_c0 = prodXY_uid177_pT2_uid165_invPolyEval_cma_ch[0]; - fourteennm_mac #( - .operation_mode("m27x27"), - .clear_type("sclr"), - .use_chainadder("false"), - .ay_scan_in_clock("0"), - .ay_scan_in_width(14), - .ax_clock("0"), - .ax_width(24), - .signed_may("false"), - .signed_max("true"), - .input_pipeline_clock("2"), - .second_pipeline_clock("2"), - .output_clock("1"), - .result_a_width(38) - ) prodXY_uid177_pT2_uid165_invPolyEval_cma_DSP0 ( - .clk({clk,clk,clk}), - .ena({ prodXY_uid177_pT2_uid165_invPolyEval_cma_ena2, prodXY_uid177_pT2_uid165_invPolyEval_cma_ena1, prodXY_uid177_pT2_uid165_invPolyEval_cma_ena0 }), - .clr({ prodXY_uid177_pT2_uid165_invPolyEval_cma_reset, prodXY_uid177_pT2_uid165_invPolyEval_cma_reset }), - .ay(prodXY_uid177_pT2_uid165_invPolyEval_cma_a0), - .ax(prodXY_uid177_pT2_uid165_invPolyEval_cma_c0), - .resulta(prodXY_uid177_pT2_uid165_invPolyEval_cma_s0), - .accumulate(), - .loadconst(), - .negate(), - .sub(), - .az(), - .coefsela(), - .bx(), - .by(), - .bz(), - .coefselb(), - .scanin(), - .scanout(), - .chainin(), - .chainout(), - .resultb(), - .dfxlfsrena(), - .dfxmisrena(), - .dftout() - ); - dspba_delay_ver #( .width(38), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) - prodXY_uid177_pT2_uid165_invPolyEval_cma_delay ( .xin(prodXY_uid177_pT2_uid165_invPolyEval_cma_s0), .xout(prodXY_uid177_pT2_uid165_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid177_pT2_uid165_invPolyEval_cma_q = prodXY_uid177_pT2_uid165_invPolyEval_cma_qq[37:0]; - - // osig_uid178_pT2_uid165_invPolyEval(BITSELECT,177)@16 - assign osig_uid178_pT2_uid165_invPolyEval_b = prodXY_uid177_pT2_uid165_invPolyEval_cma_q[37:13]; - - // highBBits_uid167_invPolyEval(BITSELECT,166)@16 - assign highBBits_uid167_invPolyEval_b = osig_uid178_pT2_uid165_invPolyEval_b[24:2]; - - // redist19_yAddr_uid51_fpDivTest_b_14_notEnable(LOGICAL,289) - assign redist19_yAddr_uid51_fpDivTest_b_14_notEnable_q = ~ (en); - - // redist19_yAddr_uid51_fpDivTest_b_14_nor(LOGICAL,290) - assign redist19_yAddr_uid51_fpDivTest_b_14_nor_q = ~ (redist19_yAddr_uid51_fpDivTest_b_14_notEnable_q | redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q); - - // redist19_yAddr_uid51_fpDivTest_b_14_mem_last(CONSTANT,286) - assign redist19_yAddr_uid51_fpDivTest_b_14_mem_last_q = 3'b011; - - // redist19_yAddr_uid51_fpDivTest_b_14_cmp(LOGICAL,287) - assign redist19_yAddr_uid51_fpDivTest_b_14_cmp_q = redist19_yAddr_uid51_fpDivTest_b_14_mem_last_q == redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q ? 1'b1 : 1'b0; - - // redist19_yAddr_uid51_fpDivTest_b_14_cmpReg(REG,288) - always @ (posedge clk) - begin - if (areset) - begin - redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q <= redist19_yAddr_uid51_fpDivTest_b_14_cmp_q; - end - end - - // redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena(REG,291) - always @ (posedge clk) - begin - if (areset) - begin - redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q <= 1'b0; - end - else if (redist19_yAddr_uid51_fpDivTest_b_14_nor_q == 1'b1) - begin - redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q <= redist19_yAddr_uid51_fpDivTest_b_14_cmpReg_q; - end - end - - // redist19_yAddr_uid51_fpDivTest_b_14_enaAnd(LOGICAL,292) - assign redist19_yAddr_uid51_fpDivTest_b_14_enaAnd_q = redist19_yAddr_uid51_fpDivTest_b_14_sticky_ena_q & en; - - // redist19_yAddr_uid51_fpDivTest_b_14_rdcnt(COUNTER,283) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i <= 3'd0; - redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i == 3'd3) - begin - redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq <= 1'b1; - end - else - begin - redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq <= 1'b0; - end - if (redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_eq == 1'b1) - begin - redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i <= $unsigned(redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i <= $unsigned(redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q = redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_i[2:0]; - - // redist19_yAddr_uid51_fpDivTest_b_14_rdmux(MUX,284) - assign redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s = en; - always @(redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s or redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q or redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q) - begin - unique case (redist19_yAddr_uid51_fpDivTest_b_14_rdmux_s) - 1'b0 : redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q = redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q; - 1'b1 : redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q = redist19_yAddr_uid51_fpDivTest_b_14_rdcnt_q; - default : redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q = 3'b0; - endcase - end - - // redist19_yAddr_uid51_fpDivTest_b_14_wraddr(REG,285) - always @ (posedge clk) - begin - if (areset) - begin - redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q <= 3'b100; - end - else - begin - redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q <= redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q; - end - end - - // redist19_yAddr_uid51_fpDivTest_b_14_mem(DUALMEM,282) - assign redist19_yAddr_uid51_fpDivTest_b_14_mem_ia = redist18_yAddr_uid51_fpDivTest_b_7_outputreg0_q; - assign redist19_yAddr_uid51_fpDivTest_b_14_mem_aa = redist19_yAddr_uid51_fpDivTest_b_14_wraddr_q; - assign redist19_yAddr_uid51_fpDivTest_b_14_mem_ab = redist19_yAddr_uid51_fpDivTest_b_14_rdmux_q; - assign redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(9), - .widthad_a(3), - .numwords_a(5), - .width_b(9), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist19_yAddr_uid51_fpDivTest_b_14_mem_dmem ( - .clocken1(redist19_yAddr_uid51_fpDivTest_b_14_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0), - .clock1(clk), - .address_a(redist19_yAddr_uid51_fpDivTest_b_14_mem_aa), - .data_a(redist19_yAddr_uid51_fpDivTest_b_14_mem_ia), - .wren_a(en[0]), - .address_b(redist19_yAddr_uid51_fpDivTest_b_14_mem_ab), - .q_b(redist19_yAddr_uid51_fpDivTest_b_14_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist19_yAddr_uid51_fpDivTest_b_14_mem_q = redist19_yAddr_uid51_fpDivTest_b_14_mem_iq[8:0]; - assign redist19_yAddr_uid51_fpDivTest_b_14_mem_enaOr_rst = redist19_yAddr_uid51_fpDivTest_b_14_enaAnd_q[0] | redist19_yAddr_uid51_fpDivTest_b_14_mem_reset0; - - // redist19_yAddr_uid51_fpDivTest_b_14_outputreg0(DELAY,281) - always @ (posedge clk) - begin - if (areset) - begin - redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q <= redist19_yAddr_uid51_fpDivTest_b_14_mem_q; - end - end - - // memoryC0_uid146_invTables_lutmem(DUALMEM,179)@14 + 2 - // in j@20000000 - assign memoryC0_uid146_invTables_lutmem_aa = redist19_yAddr_uid51_fpDivTest_b_14_outputreg0_q; - assign memoryC0_uid146_invTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(32), - .widthad_a(9), - .numwords_a(512), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_sclr_a("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fdiv_memoryC0_uid146_invTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Stratix 10") - ) memoryC0_uid146_invTables_lutmem_dmem ( - .clocken0(en[0]), - .sclr(memoryC0_uid146_invTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC0_uid146_invTables_lutmem_aa), - .q_a(memoryC0_uid146_invTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC0_uid146_invTables_lutmem_r = memoryC0_uid146_invTables_lutmem_ir[31:0]; - assign memoryC0_uid146_invTables_lutmem_enaOr_rst = en[0] | memoryC0_uid146_invTables_lutmem_reset0; - - // s2sumAHighB_uid168_invPolyEval(ADD,167)@16 - assign s2sumAHighB_uid168_invPolyEval_a = {{1{memoryC0_uid146_invTables_lutmem_r[31]}}, memoryC0_uid146_invTables_lutmem_r}; - assign s2sumAHighB_uid168_invPolyEval_b = {{10{highBBits_uid167_invPolyEval_b[22]}}, highBBits_uid167_invPolyEval_b}; - assign s2sumAHighB_uid168_invPolyEval_o = $signed(s2sumAHighB_uid168_invPolyEval_a) + $signed(s2sumAHighB_uid168_invPolyEval_b); - assign s2sumAHighB_uid168_invPolyEval_q = s2sumAHighB_uid168_invPolyEval_o[32:0]; - - // lowRangeB_uid166_invPolyEval(BITSELECT,165)@16 - assign lowRangeB_uid166_invPolyEval_in = osig_uid178_pT2_uid165_invPolyEval_b[1:0]; - assign lowRangeB_uid166_invPolyEval_b = lowRangeB_uid166_invPolyEval_in[1:0]; - - // s2_uid169_invPolyEval(BITJOIN,168)@16 - assign s2_uid169_invPolyEval_q = {s2sumAHighB_uid168_invPolyEval_q, lowRangeB_uid166_invPolyEval_b}; - - // invY_uid54_fpDivTest(BITSELECT,53)@16 - assign invY_uid54_fpDivTest_in = s2_uid169_invPolyEval_q[31:0]; - assign invY_uid54_fpDivTest_b = invY_uid54_fpDivTest_in[31:5]; - - // redist15_invY_uid54_fpDivTest_b_1(DELAY,201) - always @ (posedge clk) - begin - if (areset) - begin - redist15_invY_uid54_fpDivTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist15_invY_uid54_fpDivTest_b_1_q <= invY_uid54_fpDivTest_b; - end - end - - // prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma(CHAINMULTADD,183)@17 + 5 - // out q@23 - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset = areset; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 = en[0] | prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0; - always @ (posedge clk) - begin - if (0) - begin - end - else - begin - if (en == 1'b1) - begin - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ah[0] <= redist15_invY_uid54_fpDivTest_b_1_q; - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ch[0] <= lOAdded_uid57_fpDivTest_q; - end - end - end - - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ah[0]; - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0 = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ch[0]; - fourteennm_mac #( - .operation_mode("m27x27"), - .clear_type("sclr"), - .use_chainadder("false"), - .ay_scan_in_clock("0"), - .ay_scan_in_width(27), - .ax_clock("0"), - .ax_width(24), - .signed_may("false"), - .signed_max("false"), - .input_pipeline_clock("2"), - .second_pipeline_clock("2"), - .output_clock("1"), - .result_a_width(51) - ) prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_DSP0 ( - .clk({clk,clk,clk}), - .ena({ prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena2, prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena1, prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_ena0 }), - .clr({ prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset, prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_reset }), - .ay(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_a0), - .ax(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_c0), - .resulta(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s0), - .accumulate(), - .loadconst(), - .negate(), - .sub(), - .az(), - .coefsela(), - .bx(), - .by(), - .bz(), - .coefselb(), - .scanin(), - .scanout(), - .chainin(), - .chainout(), - .resultb(), - .dfxlfsrena(), - .dfxmisrena(), - .dftout() - ); - dspba_delay_ver #( .width(51), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) - prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_delay ( .xin(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_s0), .xout(prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_qq[50:0]; - - // osig_uid172_divValPreNorm_uid59_fpDivTest(BITSELECT,171)@23 - assign osig_uid172_divValPreNorm_uid59_fpDivTest_b = prodXY_uid171_divValPreNorm_uid59_fpDivTest_cma_q[50:23]; - - // updatedY_uid16_fpDivTest(BITJOIN,15)@22 - assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; - - // fracYZero_uid15_fpDivTest(LOGICAL,16)@22 + 1 - assign fracYZero_uid15_fpDivTest_a = {1'b0, redist23_fracY_uid13_fpDivTest_b_22_mem_q}; - assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // divValPreNormYPow2Exc_uid63_fpDivTest(MUX,62)@23 - assign divValPreNormYPow2Exc_uid63_fpDivTest_s = fracYZero_uid15_fpDivTest_q; - always @(divValPreNormYPow2Exc_uid63_fpDivTest_s or en or osig_uid172_divValPreNorm_uid59_fpDivTest_b or oFracXZ4_uid61_fpDivTest_q) - begin - unique case (divValPreNormYPow2Exc_uid63_fpDivTest_s) - 1'b0 : divValPreNormYPow2Exc_uid63_fpDivTest_q = osig_uid172_divValPreNorm_uid59_fpDivTest_b; - 1'b1 : divValPreNormYPow2Exc_uid63_fpDivTest_q = oFracXZ4_uid61_fpDivTest_q; - default : divValPreNormYPow2Exc_uid63_fpDivTest_q = 28'b0; - endcase - end - - // norm_uid64_fpDivTest(BITSELECT,63)@23 - assign norm_uid64_fpDivTest_b = divValPreNormYPow2Exc_uid63_fpDivTest_q[27:27]; - - // redist11_norm_uid64_fpDivTest_b_1(DELAY,197) - always @ (posedge clk) - begin - if (areset) - begin - redist11_norm_uid64_fpDivTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist11_norm_uid64_fpDivTest_b_1_q <= norm_uid64_fpDivTest_b; - end - end - - // zeroPaddingInAddition_uid74_fpDivTest(CONSTANT,73) - assign zeroPaddingInAddition_uid74_fpDivTest_q = 24'b000000000000000000000000; - - // expFracPostRnd_uid75_fpDivTest(BITJOIN,74)@24 - assign expFracPostRnd_uid75_fpDivTest_q = {redist11_norm_uid64_fpDivTest_b_1_q, zeroPaddingInAddition_uid74_fpDivTest_q, VCC_q}; - - // cstBiasM1_uid6_fpDivTest(CONSTANT,5) - assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; - - // expXmY_uid47_fpDivTest(SUB,46)@23 - assign expXmY_uid47_fpDivTest_a = {1'b0, redist33_expX_uid9_fpDivTest_b_23_mem_q}; - assign expXmY_uid47_fpDivTest_b = {1'b0, redist26_expY_uid12_fpDivTest_b_23_mem_q}; - assign expXmY_uid47_fpDivTest_o = $unsigned(expXmY_uid47_fpDivTest_a) - $unsigned(expXmY_uid47_fpDivTest_b); - assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; - - // expR_uid48_fpDivTest(ADD,47)@23 + 1 - assign expR_uid48_fpDivTest_a = {{2{expXmY_uid47_fpDivTest_q[8]}}, expXmY_uid47_fpDivTest_q}; - assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; - always @ (posedge clk) - begin - if (areset) - begin - expR_uid48_fpDivTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - expR_uid48_fpDivTest_o <= $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); - end - end - assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; - - // divValPreNormHigh_uid65_fpDivTest(BITSELECT,64)@23 - assign divValPreNormHigh_uid65_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[26:0]; - assign divValPreNormHigh_uid65_fpDivTest_b = divValPreNormHigh_uid65_fpDivTest_in[26:2]; - - // divValPreNormLow_uid66_fpDivTest(BITSELECT,65)@23 - assign divValPreNormLow_uid66_fpDivTest_in = divValPreNormYPow2Exc_uid63_fpDivTest_q[25:0]; - assign divValPreNormLow_uid66_fpDivTest_b = divValPreNormLow_uid66_fpDivTest_in[25:1]; - - // normFracRnd_uid67_fpDivTest(MUX,66)@23 + 1 - assign normFracRnd_uid67_fpDivTest_s = norm_uid64_fpDivTest_b; - always @ (posedge clk) - begin - if (areset) - begin - normFracRnd_uid67_fpDivTest_q <= 25'b0; - end - else if (en == 1'b1) - begin - unique case (normFracRnd_uid67_fpDivTest_s) - 1'b0 : normFracRnd_uid67_fpDivTest_q <= divValPreNormLow_uid66_fpDivTest_b; - 1'b1 : normFracRnd_uid67_fpDivTest_q <= divValPreNormHigh_uid65_fpDivTest_b; - default : normFracRnd_uid67_fpDivTest_q <= 25'b0; - endcase - end - end - - // expFracRnd_uid68_fpDivTest(BITJOIN,67)@24 - assign expFracRnd_uid68_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid67_fpDivTest_q}; - - // expFracPostRnd_uid76_fpDivTest(ADD,75)@24 - assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid68_fpDivTest_q[34]}}, expFracRnd_uid68_fpDivTest_q}; - assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, expFracPostRnd_uid75_fpDivTest_q}; - assign expFracPostRnd_uid76_fpDivTest_o = $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); - assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[35:0]; - - // fracPostRndF_uid79_fpDivTest(BITSELECT,78)@24 - assign fracPostRndF_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[24:0]; - assign fracPostRndF_uid79_fpDivTest_b = fracPostRndF_uid79_fpDivTest_in[24:1]; - - // redist10_fracPostRndF_uid79_fpDivTest_b_1(DELAY,196) - always @ (posedge clk) - begin - if (areset) - begin - redist10_fracPostRndF_uid79_fpDivTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist10_fracPostRndF_uid79_fpDivTest_b_1_q <= fracPostRndF_uid79_fpDivTest_b; - end - end - - // invYO_uid55_fpDivTest(BITSELECT,54)@16 - assign invYO_uid55_fpDivTest_in = s2_uid169_invPolyEval_q[32:0]; - assign invYO_uid55_fpDivTest_b = invYO_uid55_fpDivTest_in[32:32]; - - // redist13_invYO_uid55_fpDivTest_b_9(DELAY,199) - dspba_delay_ver #( .width(1), .depth(9), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist13_invYO_uid55_fpDivTest_b_9 ( .xin(invYO_uid55_fpDivTest_b), .xout(redist13_invYO_uid55_fpDivTest_b_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracPostRndF_uid80_fpDivTest(MUX,79)@25 - assign fracPostRndF_uid80_fpDivTest_s = redist13_invYO_uid55_fpDivTest_b_9_q; - always @(fracPostRndF_uid80_fpDivTest_s or en or redist10_fracPostRndF_uid79_fpDivTest_b_1_q or fracXExt_uid77_fpDivTest_q) - begin - unique case (fracPostRndF_uid80_fpDivTest_s) - 1'b0 : fracPostRndF_uid80_fpDivTest_q = redist10_fracPostRndF_uid79_fpDivTest_b_1_q; - 1'b1 : fracPostRndF_uid80_fpDivTest_q = fracXExt_uid77_fpDivTest_q; - default : fracPostRndF_uid80_fpDivTest_q = 24'b0; - endcase - end - - // fracPostRndFT_uid104_fpDivTest(BITSELECT,103)@25 - assign fracPostRndFT_uid104_fpDivTest_b = fracPostRndF_uid80_fpDivTest_q[23:1]; - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr(REG,226) - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q <= 3'b110; - end - else - begin - redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q; - end - end - - // redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem(DUALMEM,223) - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ia = fracPostRndFT_uid104_fpDivTest_b; - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_aa = redist4_fracPostRndFT_uid104_fpDivTest_b_8_wraddr_q; - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ab = redist4_fracPostRndFT_uid104_fpDivTest_b_8_rdmux_q; - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(3), - .numwords_a(7), - .width_b(23), - .widthad_b(3), - .numwords_b(7), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_dmem ( - .clocken1(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0), - .clock1(clk), - .address_a(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_aa), - .data_a(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ia), - .wren_a(en[0]), - .address_b(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_ab), - .q_b(redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q = redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_iq[22:0]; - assign redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_enaOr_rst = redist4_fracPostRndFT_uid104_fpDivTest_b_8_enaAnd_q[0] | redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_reset0; - - // fracRPreExcExt_uid105_fpDivTest(ADD,104)@33 - assign fracRPreExcExt_uid105_fpDivTest_a = {1'b0, redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q}; - assign fracRPreExcExt_uid105_fpDivTest_b = {23'b00000000000000000000000, extraUlp_uid103_fpDivTest_q}; - assign fracRPreExcExt_uid105_fpDivTest_o = $unsigned(fracRPreExcExt_uid105_fpDivTest_a) + $unsigned(fracRPreExcExt_uid105_fpDivTest_b); - assign fracRPreExcExt_uid105_fpDivTest_q = fracRPreExcExt_uid105_fpDivTest_o[23:0]; - - // ovfIncRnd_uid109_fpDivTest(BITSELECT,108)@33 - assign ovfIncRnd_uid109_fpDivTest_b = fracRPreExcExt_uid105_fpDivTest_q[23:23]; - - // expFracPostRndInc_uid110_fpDivTest(ADD,109)@33 - assign expFracPostRndInc_uid110_fpDivTest_a = {1'b0, redist9_expPostRndFR_uid81_fpDivTest_b_9_q}; - assign expFracPostRndInc_uid110_fpDivTest_b = {8'b00000000, ovfIncRnd_uid109_fpDivTest_b}; - assign expFracPostRndInc_uid110_fpDivTest_o = $unsigned(expFracPostRndInc_uid110_fpDivTest_a) + $unsigned(expFracPostRndInc_uid110_fpDivTest_b); - assign expFracPostRndInc_uid110_fpDivTest_q = expFracPostRndInc_uid110_fpDivTest_o[8:0]; - - // expFracPostRndR_uid111_fpDivTest(BITSELECT,110)@33 - assign expFracPostRndR_uid111_fpDivTest_in = expFracPostRndInc_uid110_fpDivTest_q[7:0]; - assign expFracPostRndR_uid111_fpDivTest_b = expFracPostRndR_uid111_fpDivTest_in[7:0]; - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable(LOGICAL,242) - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable_q = ~ (en); - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_nor(LOGICAL,243) - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_nor_q = ~ (redist8_expPostRndFR_uid81_fpDivTest_b_7_notEnable_q | redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q); - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last(CONSTANT,239) - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last_q = 3'b011; - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp(LOGICAL,240) - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_last_q == redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q ? 1'b1 : 1'b0; - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg(REG,241) - always @ (posedge clk) - begin - if (areset) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_cmp_q; - end - end - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena(REG,244) - always @ (posedge clk) - begin - if (areset) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q <= 1'b0; - end - else if (redist8_expPostRndFR_uid81_fpDivTest_b_7_nor_q == 1'b1) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_cmpReg_q; - end - end - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd(LOGICAL,245) - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_sticky_ena_q & en; - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt(COUNTER,236) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i <= 3'd0; - redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i == 3'd3) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq <= 1'b1; - end - else - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq <= 1'b0; - end - if (redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_eq == 1'b1) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i <= $unsigned(redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i <= $unsigned(redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_i[2:0]; - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux(MUX,237) - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s = en; - always @(redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s or redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q or redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q) - begin - unique case (redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_s) - 1'b0 : redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q; - 1'b1 : redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_rdcnt_q; - default : redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q = 3'b0; - endcase - end - - // expPostRndFR_uid81_fpDivTest(BITSELECT,80)@24 - assign expPostRndFR_uid81_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[32:0]; - assign expPostRndFR_uid81_fpDivTest_b = expPostRndFR_uid81_fpDivTest_in[32:25]; - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr(REG,238) - always @ (posedge clk) - begin - if (areset) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q <= 3'b100; - end - else - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q; - end - end - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_mem(DUALMEM,235) - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ia = expPostRndFR_uid81_fpDivTest_b; - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_aa = redist8_expPostRndFR_uid81_fpDivTest_b_7_wraddr_q; - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ab = redist8_expPostRndFR_uid81_fpDivTest_b_7_rdmux_q; - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(3), - .numwords_a(5), - .width_b(8), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_dmem ( - .clocken1(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0), - .clock1(clk), - .address_a(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_aa), - .data_a(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ia), - .wren_a(en[0]), - .address_b(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_ab), - .q_b(redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_iq[7:0]; - assign redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_enaOr_rst = redist8_expPostRndFR_uid81_fpDivTest_b_7_enaAnd_q[0] | redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_reset0; - - // redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0(DELAY,234) - always @ (posedge clk) - begin - if (areset) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q <= redist8_expPostRndFR_uid81_fpDivTest_b_7_mem_q; - end - end - - // redist9_expPostRndFR_uid81_fpDivTest_b_9(DELAY,195) - always @ (posedge clk) - begin - if (areset) - begin - redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0 <= '0; - redist9_expPostRndFR_uid81_fpDivTest_b_9_q <= '0; - end - else if (en == 1'b1) - begin - redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0 <= redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q; - redist9_expPostRndFR_uid81_fpDivTest_b_9_q <= redist9_expPostRndFR_uid81_fpDivTest_b_9_delay_0; - end - end - - // betweenFPwF_uid102_fpDivTest(BITSELECT,101)@25 - assign betweenFPwF_uid102_fpDivTest_in = fracPostRndF_uid80_fpDivTest_q[0:0]; - assign betweenFPwF_uid102_fpDivTest_b = betweenFPwF_uid102_fpDivTest_in[0:0]; - - // redist5_betweenFPwF_uid102_fpDivTest_b_7(DELAY,191) - dspba_delay_ver #( .width(1), .depth(7), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist5_betweenFPwF_uid102_fpDivTest_b_7 ( .xin(betweenFPwF_uid102_fpDivTest_b), .xout(redist5_betweenFPwF_uid102_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist35_expX_uid9_fpDivTest_b_31_notEnable(LOGICAL,380) - assign redist35_expX_uid9_fpDivTest_b_31_notEnable_q = ~ (en); - - // redist35_expX_uid9_fpDivTest_b_31_nor(LOGICAL,381) - assign redist35_expX_uid9_fpDivTest_b_31_nor_q = ~ (redist35_expX_uid9_fpDivTest_b_31_notEnable_q | redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q); - - // redist35_expX_uid9_fpDivTest_b_31_mem_last(CONSTANT,377) - assign redist35_expX_uid9_fpDivTest_b_31_mem_last_q = 3'b011; - - // redist35_expX_uid9_fpDivTest_b_31_cmp(LOGICAL,378) - assign redist35_expX_uid9_fpDivTest_b_31_cmp_q = redist35_expX_uid9_fpDivTest_b_31_mem_last_q == redist35_expX_uid9_fpDivTest_b_31_rdmux_q ? 1'b1 : 1'b0; - - // redist35_expX_uid9_fpDivTest_b_31_cmpReg(REG,379) - always @ (posedge clk) - begin - if (areset) - begin - redist35_expX_uid9_fpDivTest_b_31_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist35_expX_uid9_fpDivTest_b_31_cmpReg_q <= redist35_expX_uid9_fpDivTest_b_31_cmp_q; - end - end - - // redist35_expX_uid9_fpDivTest_b_31_sticky_ena(REG,382) - always @ (posedge clk) - begin - if (areset) - begin - redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q <= 1'b0; - end - else if (redist35_expX_uid9_fpDivTest_b_31_nor_q == 1'b1) - begin - redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q <= redist35_expX_uid9_fpDivTest_b_31_cmpReg_q; - end - end - - // redist35_expX_uid9_fpDivTest_b_31_enaAnd(LOGICAL,383) - assign redist35_expX_uid9_fpDivTest_b_31_enaAnd_q = redist35_expX_uid9_fpDivTest_b_31_sticky_ena_q & en; - - // redist35_expX_uid9_fpDivTest_b_31_rdcnt(COUNTER,374) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist35_expX_uid9_fpDivTest_b_31_rdcnt_i <= 3'd0; - redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist35_expX_uid9_fpDivTest_b_31_rdcnt_i == 3'd3) - begin - redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq <= 1'b1; - end - else - begin - redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq <= 1'b0; - end - if (redist35_expX_uid9_fpDivTest_b_31_rdcnt_eq == 1'b1) - begin - redist35_expX_uid9_fpDivTest_b_31_rdcnt_i <= $unsigned(redist35_expX_uid9_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist35_expX_uid9_fpDivTest_b_31_rdcnt_i <= $unsigned(redist35_expX_uid9_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist35_expX_uid9_fpDivTest_b_31_rdcnt_q = redist35_expX_uid9_fpDivTest_b_31_rdcnt_i[2:0]; - - // redist35_expX_uid9_fpDivTest_b_31_rdmux(MUX,375) - assign redist35_expX_uid9_fpDivTest_b_31_rdmux_s = en; - always @(redist35_expX_uid9_fpDivTest_b_31_rdmux_s or redist35_expX_uid9_fpDivTest_b_31_wraddr_q or redist35_expX_uid9_fpDivTest_b_31_rdcnt_q) - begin - unique case (redist35_expX_uid9_fpDivTest_b_31_rdmux_s) - 1'b0 : redist35_expX_uid9_fpDivTest_b_31_rdmux_q = redist35_expX_uid9_fpDivTest_b_31_wraddr_q; - 1'b1 : redist35_expX_uid9_fpDivTest_b_31_rdmux_q = redist35_expX_uid9_fpDivTest_b_31_rdcnt_q; - default : redist35_expX_uid9_fpDivTest_b_31_rdmux_q = 3'b0; - endcase - end - - // redist35_expX_uid9_fpDivTest_b_31_wraddr(REG,376) - always @ (posedge clk) - begin - if (areset) - begin - redist35_expX_uid9_fpDivTest_b_31_wraddr_q <= 3'b100; - end - else - begin - redist35_expX_uid9_fpDivTest_b_31_wraddr_q <= redist35_expX_uid9_fpDivTest_b_31_rdmux_q; - end - end - - // redist35_expX_uid9_fpDivTest_b_31_mem(DUALMEM,373) - assign redist35_expX_uid9_fpDivTest_b_31_mem_ia = redist34_expX_uid9_fpDivTest_b_24_q; - assign redist35_expX_uid9_fpDivTest_b_31_mem_aa = redist35_expX_uid9_fpDivTest_b_31_wraddr_q; - assign redist35_expX_uid9_fpDivTest_b_31_mem_ab = redist35_expX_uid9_fpDivTest_b_31_rdmux_q; - assign redist35_expX_uid9_fpDivTest_b_31_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(3), - .numwords_a(5), - .width_b(8), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist35_expX_uid9_fpDivTest_b_31_mem_dmem ( - .clocken1(redist35_expX_uid9_fpDivTest_b_31_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist35_expX_uid9_fpDivTest_b_31_mem_reset0), - .clock1(clk), - .address_a(redist35_expX_uid9_fpDivTest_b_31_mem_aa), - .data_a(redist35_expX_uid9_fpDivTest_b_31_mem_ia), - .wren_a(en[0]), - .address_b(redist35_expX_uid9_fpDivTest_b_31_mem_ab), - .q_b(redist35_expX_uid9_fpDivTest_b_31_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist35_expX_uid9_fpDivTest_b_31_mem_q = redist35_expX_uid9_fpDivTest_b_31_mem_iq[7:0]; - assign redist35_expX_uid9_fpDivTest_b_31_mem_enaOr_rst = redist35_expX_uid9_fpDivTest_b_31_enaAnd_q[0] | redist35_expX_uid9_fpDivTest_b_31_mem_reset0; - - // redist35_expX_uid9_fpDivTest_b_31_outputreg0(DELAY,372) - always @ (posedge clk) - begin - if (areset) - begin - redist35_expX_uid9_fpDivTest_b_31_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist35_expX_uid9_fpDivTest_b_31_outputreg0_q <= redist35_expX_uid9_fpDivTest_b_31_mem_q; - end - end - - // redist36_expX_uid9_fpDivTest_b_32(DELAY,222) - always @ (posedge clk) - begin - if (areset) - begin - redist36_expX_uid9_fpDivTest_b_32_q <= '0; - end - else if (en == 1'b1) - begin - redist36_expX_uid9_fpDivTest_b_32_q <= redist35_expX_uid9_fpDivTest_b_31_outputreg0_q; - end - end - - // redist32_fracX_uid10_fpDivTest_b_32_notEnable(LOGICAL,357) - assign redist32_fracX_uid10_fpDivTest_b_32_notEnable_q = ~ (en); - - // redist32_fracX_uid10_fpDivTest_b_32_nor(LOGICAL,358) - assign redist32_fracX_uid10_fpDivTest_b_32_nor_q = ~ (redist32_fracX_uid10_fpDivTest_b_32_notEnable_q | redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q); - - // redist32_fracX_uid10_fpDivTest_b_32_mem_last(CONSTANT,354) - assign redist32_fracX_uid10_fpDivTest_b_32_mem_last_q = 4'b0100; - - // redist32_fracX_uid10_fpDivTest_b_32_cmp(LOGICAL,355) - assign redist32_fracX_uid10_fpDivTest_b_32_cmp_b = {1'b0, redist32_fracX_uid10_fpDivTest_b_32_rdmux_q}; - assign redist32_fracX_uid10_fpDivTest_b_32_cmp_q = redist32_fracX_uid10_fpDivTest_b_32_mem_last_q == redist32_fracX_uid10_fpDivTest_b_32_cmp_b ? 1'b1 : 1'b0; - - // redist32_fracX_uid10_fpDivTest_b_32_cmpReg(REG,356) - always @ (posedge clk) - begin - if (areset) - begin - redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q <= redist32_fracX_uid10_fpDivTest_b_32_cmp_q; - end - end - - // redist32_fracX_uid10_fpDivTest_b_32_sticky_ena(REG,359) - always @ (posedge clk) - begin - if (areset) - begin - redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q <= 1'b0; - end - else if (redist32_fracX_uid10_fpDivTest_b_32_nor_q == 1'b1) - begin - redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q <= redist32_fracX_uid10_fpDivTest_b_32_cmpReg_q; - end - end - - // redist32_fracX_uid10_fpDivTest_b_32_enaAnd(LOGICAL,360) - assign redist32_fracX_uid10_fpDivTest_b_32_enaAnd_q = redist32_fracX_uid10_fpDivTest_b_32_sticky_ena_q & en; - - // redist32_fracX_uid10_fpDivTest_b_32_rdcnt(COUNTER,351) - // low=0, high=5, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i <= 3'd0; - redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i == 3'd4) - begin - redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq <= 1'b1; - end - else - begin - redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq <= 1'b0; - end - if (redist32_fracX_uid10_fpDivTest_b_32_rdcnt_eq == 1'b1) - begin - redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i <= $unsigned(redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i) + $unsigned(3'd3); - end - else - begin - redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i <= $unsigned(redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q = redist32_fracX_uid10_fpDivTest_b_32_rdcnt_i[2:0]; - - // redist32_fracX_uid10_fpDivTest_b_32_rdmux(MUX,352) - assign redist32_fracX_uid10_fpDivTest_b_32_rdmux_s = en; - always @(redist32_fracX_uid10_fpDivTest_b_32_rdmux_s or redist32_fracX_uid10_fpDivTest_b_32_wraddr_q or redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q) - begin - unique case (redist32_fracX_uid10_fpDivTest_b_32_rdmux_s) - 1'b0 : redist32_fracX_uid10_fpDivTest_b_32_rdmux_q = redist32_fracX_uid10_fpDivTest_b_32_wraddr_q; - 1'b1 : redist32_fracX_uid10_fpDivTest_b_32_rdmux_q = redist32_fracX_uid10_fpDivTest_b_32_rdcnt_q; - default : redist32_fracX_uid10_fpDivTest_b_32_rdmux_q = 3'b0; - endcase - end - - // redist32_fracX_uid10_fpDivTest_b_32_wraddr(REG,353) - always @ (posedge clk) - begin - if (areset) - begin - redist32_fracX_uid10_fpDivTest_b_32_wraddr_q <= 3'b101; - end - else - begin - redist32_fracX_uid10_fpDivTest_b_32_wraddr_q <= redist32_fracX_uid10_fpDivTest_b_32_rdmux_q; - end - end - - // redist32_fracX_uid10_fpDivTest_b_32_mem(DUALMEM,350) - assign redist32_fracX_uid10_fpDivTest_b_32_mem_ia = redist31_fracX_uid10_fpDivTest_b_25_q; - assign redist32_fracX_uid10_fpDivTest_b_32_mem_aa = redist32_fracX_uid10_fpDivTest_b_32_wraddr_q; - assign redist32_fracX_uid10_fpDivTest_b_32_mem_ab = redist32_fracX_uid10_fpDivTest_b_32_rdmux_q; - assign redist32_fracX_uid10_fpDivTest_b_32_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(3), - .numwords_a(6), - .width_b(23), - .widthad_b(3), - .numwords_b(6), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist32_fracX_uid10_fpDivTest_b_32_mem_dmem ( - .clocken1(redist32_fracX_uid10_fpDivTest_b_32_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist32_fracX_uid10_fpDivTest_b_32_mem_reset0), - .clock1(clk), - .address_a(redist32_fracX_uid10_fpDivTest_b_32_mem_aa), - .data_a(redist32_fracX_uid10_fpDivTest_b_32_mem_ia), - .wren_a(en[0]), - .address_b(redist32_fracX_uid10_fpDivTest_b_32_mem_ab), - .q_b(redist32_fracX_uid10_fpDivTest_b_32_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist32_fracX_uid10_fpDivTest_b_32_mem_q = redist32_fracX_uid10_fpDivTest_b_32_mem_iq[22:0]; - assign redist32_fracX_uid10_fpDivTest_b_32_mem_enaOr_rst = redist32_fracX_uid10_fpDivTest_b_32_enaAnd_q[0] | redist32_fracX_uid10_fpDivTest_b_32_mem_reset0; - - // qDivProdLTX_opB_uid100_fpDivTest(BITJOIN,99)@32 - assign qDivProdLTX_opB_uid100_fpDivTest_q = {redist36_expX_uid9_fpDivTest_b_32_q, redist32_fracX_uid10_fpDivTest_b_32_mem_q}; - - // redist25_fracY_uid13_fpDivTest_b_25(DELAY,211) - always @ (posedge clk) - begin - if (areset) - begin - redist25_fracY_uid13_fpDivTest_b_25_q <= '0; - end - else if (en == 1'b1) - begin - redist25_fracY_uid13_fpDivTest_b_25_q <= redist24_fracY_uid13_fpDivTest_b_24_q; - end - end - - // lOAdded_uid87_fpDivTest(BITJOIN,86)@25 - assign lOAdded_uid87_fpDivTest_q = {VCC_q, redist25_fracY_uid13_fpDivTest_b_25_q}; - - // lOAdded_uid84_fpDivTest(BITJOIN,83)@25 - assign lOAdded_uid84_fpDivTest_q = {VCC_q, fracPostRndF_uid80_fpDivTest_q}; - - // qDivProd_uid89_fpDivTest_cma(CHAINMULTADD,182)@25 + 5 - // out q@31 - assign qDivProd_uid89_fpDivTest_cma_reset = areset; - assign qDivProd_uid89_fpDivTest_cma_ena0 = en[0] | qDivProd_uid89_fpDivTest_cma_reset; - assign qDivProd_uid89_fpDivTest_cma_ena1 = qDivProd_uid89_fpDivTest_cma_ena0; - assign qDivProd_uid89_fpDivTest_cma_ena2 = qDivProd_uid89_fpDivTest_cma_ena0; - always @ (posedge clk) - begin - if (0) - begin - end - else - begin - if (en == 1'b1) - begin - qDivProd_uid89_fpDivTest_cma_ah[0] <= lOAdded_uid84_fpDivTest_q; - qDivProd_uid89_fpDivTest_cma_ch[0] <= lOAdded_uid87_fpDivTest_q; - end - end - end - - assign qDivProd_uid89_fpDivTest_cma_a0 = qDivProd_uid89_fpDivTest_cma_ah[0]; - assign qDivProd_uid89_fpDivTest_cma_c0 = qDivProd_uid89_fpDivTest_cma_ch[0]; - fourteennm_mac #( - .operation_mode("m27x27"), - .clear_type("sclr"), - .use_chainadder("false"), - .ay_scan_in_clock("0"), - .ay_scan_in_width(25), - .ax_clock("0"), - .ax_width(24), - .signed_may("false"), - .signed_max("false"), - .input_pipeline_clock("2"), - .second_pipeline_clock("2"), - .output_clock("1"), - .result_a_width(49) - ) qDivProd_uid89_fpDivTest_cma_DSP0 ( - .clk({clk,clk,clk}), - .ena({ qDivProd_uid89_fpDivTest_cma_ena2, qDivProd_uid89_fpDivTest_cma_ena1, qDivProd_uid89_fpDivTest_cma_ena0 }), - .clr({ qDivProd_uid89_fpDivTest_cma_reset, qDivProd_uid89_fpDivTest_cma_reset }), - .ay(qDivProd_uid89_fpDivTest_cma_a0), - .ax(qDivProd_uid89_fpDivTest_cma_c0), - .resulta(qDivProd_uid89_fpDivTest_cma_s0), - .accumulate(), - .loadconst(), - .negate(), - .sub(), - .az(), - .coefsela(), - .bx(), - .by(), - .bz(), - .coefselb(), - .scanin(), - .scanout(), - .chainin(), - .chainout(), - .resultb(), - .dfxlfsrena(), - .dfxmisrena(), - .dftout() - ); - dspba_delay_ver #( .width(49), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) - qDivProd_uid89_fpDivTest_cma_delay ( .xin(qDivProd_uid89_fpDivTest_cma_s0), .xout(qDivProd_uid89_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign qDivProd_uid89_fpDivTest_cma_q = qDivProd_uid89_fpDivTest_cma_qq[48:0]; - - // qDivProdNorm_uid90_fpDivTest(BITSELECT,89)@31 - assign qDivProdNorm_uid90_fpDivTest_b = qDivProd_uid89_fpDivTest_cma_q[48:48]; - - // cstBias_uid7_fpDivTest(CONSTANT,6) - assign cstBias_uid7_fpDivTest_q = 8'b01111111; - - // qDivProdExp_opBs_uid95_fpDivTest(SUB,94)@31 - assign qDivProdExp_opBs_uid95_fpDivTest_a = {1'b0, cstBias_uid7_fpDivTest_q}; - assign qDivProdExp_opBs_uid95_fpDivTest_b = {8'b00000000, qDivProdNorm_uid90_fpDivTest_b}; - assign qDivProdExp_opBs_uid95_fpDivTest_o = $unsigned(qDivProdExp_opBs_uid95_fpDivTest_a) - $unsigned(qDivProdExp_opBs_uid95_fpDivTest_b); - assign qDivProdExp_opBs_uid95_fpDivTest_q = qDivProdExp_opBs_uid95_fpDivTest_o[8:0]; - - // redist14_invYO_uid55_fpDivTest_b_15(DELAY,200) - dspba_delay_ver #( .width(1), .depth(6), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist14_invYO_uid55_fpDivTest_b_15 ( .xin(redist13_invYO_uid55_fpDivTest_b_9_q), .xout(redist14_invYO_uid55_fpDivTest_b_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expPostRndF_uid82_fpDivTest(MUX,81)@31 - assign expPostRndF_uid82_fpDivTest_s = redist14_invYO_uid55_fpDivTest_b_15_q; - always @(expPostRndF_uid82_fpDivTest_s or en or redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q or redist35_expX_uid9_fpDivTest_b_31_outputreg0_q) - begin - unique case (expPostRndF_uid82_fpDivTest_s) - 1'b0 : expPostRndF_uid82_fpDivTest_q = redist8_expPostRndFR_uid81_fpDivTest_b_7_outputreg0_q; - 1'b1 : expPostRndF_uid82_fpDivTest_q = redist35_expX_uid9_fpDivTest_b_31_outputreg0_q; - default : expPostRndF_uid82_fpDivTest_q = 8'b0; - endcase - end - - // redist28_expY_uid12_fpDivTest_b_31_notEnable(LOGICAL,323) - assign redist28_expY_uid12_fpDivTest_b_31_notEnable_q = ~ (en); - - // redist28_expY_uid12_fpDivTest_b_31_nor(LOGICAL,324) - assign redist28_expY_uid12_fpDivTest_b_31_nor_q = ~ (redist28_expY_uid12_fpDivTest_b_31_notEnable_q | redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q); - - // redist28_expY_uid12_fpDivTest_b_31_mem_last(CONSTANT,320) - assign redist28_expY_uid12_fpDivTest_b_31_mem_last_q = 3'b011; - - // redist28_expY_uid12_fpDivTest_b_31_cmp(LOGICAL,321) - assign redist28_expY_uid12_fpDivTest_b_31_cmp_q = redist28_expY_uid12_fpDivTest_b_31_mem_last_q == redist28_expY_uid12_fpDivTest_b_31_rdmux_q ? 1'b1 : 1'b0; - - // redist28_expY_uid12_fpDivTest_b_31_cmpReg(REG,322) - always @ (posedge clk) - begin - if (areset) - begin - redist28_expY_uid12_fpDivTest_b_31_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist28_expY_uid12_fpDivTest_b_31_cmpReg_q <= redist28_expY_uid12_fpDivTest_b_31_cmp_q; - end - end - - // redist28_expY_uid12_fpDivTest_b_31_sticky_ena(REG,325) - always @ (posedge clk) - begin - if (areset) - begin - redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q <= 1'b0; - end - else if (redist28_expY_uid12_fpDivTest_b_31_nor_q == 1'b1) - begin - redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q <= redist28_expY_uid12_fpDivTest_b_31_cmpReg_q; - end - end - - // redist28_expY_uid12_fpDivTest_b_31_enaAnd(LOGICAL,326) - assign redist28_expY_uid12_fpDivTest_b_31_enaAnd_q = redist28_expY_uid12_fpDivTest_b_31_sticky_ena_q & en; - - // redist28_expY_uid12_fpDivTest_b_31_rdcnt(COUNTER,317) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist28_expY_uid12_fpDivTest_b_31_rdcnt_i <= 3'd0; - redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist28_expY_uid12_fpDivTest_b_31_rdcnt_i == 3'd3) - begin - redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq <= 1'b1; - end - else - begin - redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq <= 1'b0; - end - if (redist28_expY_uid12_fpDivTest_b_31_rdcnt_eq == 1'b1) - begin - redist28_expY_uid12_fpDivTest_b_31_rdcnt_i <= $unsigned(redist28_expY_uid12_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist28_expY_uid12_fpDivTest_b_31_rdcnt_i <= $unsigned(redist28_expY_uid12_fpDivTest_b_31_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist28_expY_uid12_fpDivTest_b_31_rdcnt_q = redist28_expY_uid12_fpDivTest_b_31_rdcnt_i[2:0]; - - // redist28_expY_uid12_fpDivTest_b_31_rdmux(MUX,318) - assign redist28_expY_uid12_fpDivTest_b_31_rdmux_s = en; - always @(redist28_expY_uid12_fpDivTest_b_31_rdmux_s or redist28_expY_uid12_fpDivTest_b_31_wraddr_q or redist28_expY_uid12_fpDivTest_b_31_rdcnt_q) - begin - unique case (redist28_expY_uid12_fpDivTest_b_31_rdmux_s) - 1'b0 : redist28_expY_uid12_fpDivTest_b_31_rdmux_q = redist28_expY_uid12_fpDivTest_b_31_wraddr_q; - 1'b1 : redist28_expY_uid12_fpDivTest_b_31_rdmux_q = redist28_expY_uid12_fpDivTest_b_31_rdcnt_q; - default : redist28_expY_uid12_fpDivTest_b_31_rdmux_q = 3'b0; - endcase - end - - // redist28_expY_uid12_fpDivTest_b_31_wraddr(REG,319) - always @ (posedge clk) - begin - if (areset) - begin - redist28_expY_uid12_fpDivTest_b_31_wraddr_q <= 3'b100; - end - else - begin - redist28_expY_uid12_fpDivTest_b_31_wraddr_q <= redist28_expY_uid12_fpDivTest_b_31_rdmux_q; - end - end - - // redist28_expY_uid12_fpDivTest_b_31_mem(DUALMEM,316) - assign redist28_expY_uid12_fpDivTest_b_31_mem_ia = redist27_expY_uid12_fpDivTest_b_24_q; - assign redist28_expY_uid12_fpDivTest_b_31_mem_aa = redist28_expY_uid12_fpDivTest_b_31_wraddr_q; - assign redist28_expY_uid12_fpDivTest_b_31_mem_ab = redist28_expY_uid12_fpDivTest_b_31_rdmux_q; - assign redist28_expY_uid12_fpDivTest_b_31_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(3), - .numwords_a(5), - .width_b(8), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist28_expY_uid12_fpDivTest_b_31_mem_dmem ( - .clocken1(redist28_expY_uid12_fpDivTest_b_31_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist28_expY_uid12_fpDivTest_b_31_mem_reset0), - .clock1(clk), - .address_a(redist28_expY_uid12_fpDivTest_b_31_mem_aa), - .data_a(redist28_expY_uid12_fpDivTest_b_31_mem_ia), - .wren_a(en[0]), - .address_b(redist28_expY_uid12_fpDivTest_b_31_mem_ab), - .q_b(redist28_expY_uid12_fpDivTest_b_31_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist28_expY_uid12_fpDivTest_b_31_mem_q = redist28_expY_uid12_fpDivTest_b_31_mem_iq[7:0]; - assign redist28_expY_uid12_fpDivTest_b_31_mem_enaOr_rst = redist28_expY_uid12_fpDivTest_b_31_enaAnd_q[0] | redist28_expY_uid12_fpDivTest_b_31_mem_reset0; - - // redist28_expY_uid12_fpDivTest_b_31_outputreg0(DELAY,315) - always @ (posedge clk) - begin - if (areset) - begin - redist28_expY_uid12_fpDivTest_b_31_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist28_expY_uid12_fpDivTest_b_31_outputreg0_q <= redist28_expY_uid12_fpDivTest_b_31_mem_q; - end - end - - // qDivProdExp_opA_uid94_fpDivTest(ADD,93)@31 - assign qDivProdExp_opA_uid94_fpDivTest_a = {1'b0, redist28_expY_uid12_fpDivTest_b_31_outputreg0_q}; - assign qDivProdExp_opA_uid94_fpDivTest_b = {1'b0, expPostRndF_uid82_fpDivTest_q}; - assign qDivProdExp_opA_uid94_fpDivTest_o = $unsigned(qDivProdExp_opA_uid94_fpDivTest_a) + $unsigned(qDivProdExp_opA_uid94_fpDivTest_b); - assign qDivProdExp_opA_uid94_fpDivTest_q = qDivProdExp_opA_uid94_fpDivTest_o[8:0]; - - // qDivProdExp_uid96_fpDivTest(SUB,95)@31 - assign qDivProdExp_uid96_fpDivTest_a = {3'b000, qDivProdExp_opA_uid94_fpDivTest_q}; - assign qDivProdExp_uid96_fpDivTest_b = {{3{qDivProdExp_opBs_uid95_fpDivTest_q[8]}}, qDivProdExp_opBs_uid95_fpDivTest_q}; - assign qDivProdExp_uid96_fpDivTest_o = $signed(qDivProdExp_uid96_fpDivTest_a) - $signed(qDivProdExp_uid96_fpDivTest_b); - assign qDivProdExp_uid96_fpDivTest_q = qDivProdExp_uid96_fpDivTest_o[10:0]; - - // qDivProdLTX_opA_uid98_fpDivTest(BITSELECT,97)@31 - assign qDivProdLTX_opA_uid98_fpDivTest_in = qDivProdExp_uid96_fpDivTest_q[7:0]; - assign qDivProdLTX_opA_uid98_fpDivTest_b = qDivProdLTX_opA_uid98_fpDivTest_in[7:0]; - - // redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1(DELAY,192) - always @ (posedge clk) - begin - if (areset) - begin - redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q <= qDivProdLTX_opA_uid98_fpDivTest_b; - end - end - - // qDivProdFracHigh_uid91_fpDivTest(BITSELECT,90)@31 - assign qDivProdFracHigh_uid91_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[47:0]; - assign qDivProdFracHigh_uid91_fpDivTest_b = qDivProdFracHigh_uid91_fpDivTest_in[47:24]; - - // qDivProdFracLow_uid92_fpDivTest(BITSELECT,91)@31 - assign qDivProdFracLow_uid92_fpDivTest_in = qDivProd_uid89_fpDivTest_cma_q[46:0]; - assign qDivProdFracLow_uid92_fpDivTest_b = qDivProdFracLow_uid92_fpDivTest_in[46:23]; - - // qDivProdFrac_uid93_fpDivTest(MUX,92)@31 - assign qDivProdFrac_uid93_fpDivTest_s = qDivProdNorm_uid90_fpDivTest_b; - always @(qDivProdFrac_uid93_fpDivTest_s or en or qDivProdFracLow_uid92_fpDivTest_b or qDivProdFracHigh_uid91_fpDivTest_b) - begin - unique case (qDivProdFrac_uid93_fpDivTest_s) - 1'b0 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracLow_uid92_fpDivTest_b; - 1'b1 : qDivProdFrac_uid93_fpDivTest_q = qDivProdFracHigh_uid91_fpDivTest_b; - default : qDivProdFrac_uid93_fpDivTest_q = 24'b0; - endcase - end - - // qDivProdFracWF_uid97_fpDivTest(BITSELECT,96)@31 - assign qDivProdFracWF_uid97_fpDivTest_b = qDivProdFrac_uid93_fpDivTest_q[23:1]; - - // redist7_qDivProdFracWF_uid97_fpDivTest_b_1(DELAY,193) - always @ (posedge clk) - begin - if (areset) - begin - redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q <= qDivProdFracWF_uid97_fpDivTest_b; - end - end - - // qDivProdLTX_opA_uid99_fpDivTest(BITJOIN,98)@32 - assign qDivProdLTX_opA_uid99_fpDivTest_q = {redist6_qDivProdLTX_opA_uid98_fpDivTest_b_1_q, redist7_qDivProdFracWF_uid97_fpDivTest_b_1_q}; - - // qDividerProdLTX_uid101_fpDivTest(COMPARE,100)@32 - assign qDividerProdLTX_uid101_fpDivTest_a = {2'b00, qDivProdLTX_opA_uid99_fpDivTest_q}; - assign qDividerProdLTX_uid101_fpDivTest_b = {2'b00, qDivProdLTX_opB_uid100_fpDivTest_q}; - assign qDividerProdLTX_uid101_fpDivTest_o = $unsigned(qDividerProdLTX_uid101_fpDivTest_a) - $unsigned(qDividerProdLTX_uid101_fpDivTest_b); - assign qDividerProdLTX_uid101_fpDivTest_c[0] = qDividerProdLTX_uid101_fpDivTest_o[32]; - - // extraUlp_uid103_fpDivTest(LOGICAL,102)@32 + 1 - assign extraUlp_uid103_fpDivTest_qi = qDividerProdLTX_uid101_fpDivTest_c & redist5_betweenFPwF_uid102_fpDivTest_b_7_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - extraUlp_uid103_fpDivTest_delay ( .xin(extraUlp_uid103_fpDivTest_qi), .xout(extraUlp_uid103_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expRPreExc_uid112_fpDivTest(MUX,111)@33 + 1 - assign expRPreExc_uid112_fpDivTest_s = extraUlp_uid103_fpDivTest_q; - always @ (posedge clk) - begin - if (areset) - begin - expRPreExc_uid112_fpDivTest_q <= 8'b0; - end - else if (en == 1'b1) - begin - unique case (expRPreExc_uid112_fpDivTest_s) - 1'b0 : expRPreExc_uid112_fpDivTest_q <= redist9_expPostRndFR_uid81_fpDivTest_b_9_q; - 1'b1 : expRPreExc_uid112_fpDivTest_q <= expFracPostRndR_uid111_fpDivTest_b; - default : expRPreExc_uid112_fpDivTest_q <= 8'b0; - endcase - end - end - - // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@25 - assign invExpXIsMax_uid43_fpDivTest_q = ~ (expXIsMax_uid38_fpDivTest_q); - - // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@25 - assign InvExpXIsZero_uid44_fpDivTest_q = ~ (excZ_y_uid37_fpDivTest_q); - - // excR_y_uid45_fpDivTest(LOGICAL,44)@25 - assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; - - // excXIYR_uid127_fpDivTest(LOGICAL,126)@25 - assign excXIYR_uid127_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; - - // excXIYZ_uid126_fpDivTest(LOGICAL,125)@25 - assign excXIYZ_uid126_fpDivTest_q = excI_x_uid27_fpDivTest_q & excZ_y_uid37_fpDivTest_q; - - // expRExt_uid114_fpDivTest(BITSELECT,113)@24 - assign expRExt_uid114_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[35:25]; - - // expOvf_uid118_fpDivTest(COMPARE,117)@24 + 1 - assign expOvf_uid118_fpDivTest_a = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; - assign expOvf_uid118_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; - always @ (posedge clk) - begin - if (areset) - begin - expOvf_uid118_fpDivTest_o <= 13'b0; - end - else if (en == 1'b1) - begin - expOvf_uid118_fpDivTest_o <= $signed(expOvf_uid118_fpDivTest_a) - $signed(expOvf_uid118_fpDivTest_b); - end - end - assign expOvf_uid118_fpDivTest_n[0] = ~ (expOvf_uid118_fpDivTest_o[12]); - - // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@24 - assign invExpXIsMax_uid29_fpDivTest_q = ~ (expXIsMax_uid24_fpDivTest_q); - - // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@24 - assign InvExpXIsZero_uid30_fpDivTest_q = ~ (excZ_x_uid23_fpDivTest_q); - - // excR_x_uid31_fpDivTest(LOGICAL,30)@24 + 1 - assign excR_x_uid31_fpDivTest_qi = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - excR_x_uid31_fpDivTest_delay ( .xin(excR_x_uid31_fpDivTest_qi), .xout(excR_x_uid31_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excXRYROvf_uid125_fpDivTest(LOGICAL,124)@25 - assign excXRYROvf_uid125_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid118_fpDivTest_n; - - // excXRYZ_uid124_fpDivTest(LOGICAL,123)@25 - assign excXRYZ_uid124_fpDivTest_q = excR_x_uid31_fpDivTest_q & excZ_y_uid37_fpDivTest_q; - - // excRInf_uid128_fpDivTest(LOGICAL,127)@25 - assign excRInf_uid128_fpDivTest_q = excXRYZ_uid124_fpDivTest_q | excXRYROvf_uid125_fpDivTest_q | excXIYZ_uid126_fpDivTest_q | excXIYR_uid127_fpDivTest_q; - - // xRegOrZero_uid121_fpDivTest(LOGICAL,120)@25 - assign xRegOrZero_uid121_fpDivTest_q = excR_x_uid31_fpDivTest_q | redist22_excZ_x_uid23_fpDivTest_q_1_q; - - // regOrZeroOverInf_uid122_fpDivTest(LOGICAL,121)@25 - assign regOrZeroOverInf_uid122_fpDivTest_q = xRegOrZero_uid121_fpDivTest_q & excI_y_uid41_fpDivTest_q; - - // expUdf_uid115_fpDivTest(COMPARE,114)@24 + 1 - assign expUdf_uid115_fpDivTest_a = {12'b000000000000, GND_q}; - assign expUdf_uid115_fpDivTest_b = {{2{expRExt_uid114_fpDivTest_b[10]}}, expRExt_uid114_fpDivTest_b}; - always @ (posedge clk) - begin - if (areset) - begin - expUdf_uid115_fpDivTest_o <= 13'b0; - end - else if (en == 1'b1) - begin - expUdf_uid115_fpDivTest_o <= $signed(expUdf_uid115_fpDivTest_a) - $signed(expUdf_uid115_fpDivTest_b); - end - end - assign expUdf_uid115_fpDivTest_n[0] = ~ (expUdf_uid115_fpDivTest_o[12]); - - // regOverRegWithUf_uid120_fpDivTest(LOGICAL,119)@25 - assign regOverRegWithUf_uid120_fpDivTest_q = expUdf_uid115_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; - - // zeroOverReg_uid119_fpDivTest(LOGICAL,118)@25 - assign zeroOverReg_uid119_fpDivTest_q = redist22_excZ_x_uid23_fpDivTest_q_1_q & excR_y_uid45_fpDivTest_q; - - // excRZero_uid123_fpDivTest(LOGICAL,122)@25 - assign excRZero_uid123_fpDivTest_q = zeroOverReg_uid119_fpDivTest_q | regOverRegWithUf_uid120_fpDivTest_q | regOrZeroOverInf_uid122_fpDivTest_q; - - // concExc_uid132_fpDivTest(BITJOIN,131)@25 - assign concExc_uid132_fpDivTest_q = {excRNaN_uid131_fpDivTest_q, excRInf_uid128_fpDivTest_q, excRZero_uid123_fpDivTest_q}; - - // excREnc_uid133_fpDivTest(LOOKUP,132)@25 + 1 - always @ (posedge clk) - begin - if (areset) - begin - excREnc_uid133_fpDivTest_q <= 2'b01; - end - else if (en == 1'b1) - begin - unique case (concExc_uid132_fpDivTest_q) - 3'b000 : excREnc_uid133_fpDivTest_q <= 2'b01; - 3'b001 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b010 : excREnc_uid133_fpDivTest_q <= 2'b10; - 3'b011 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b100 : excREnc_uid133_fpDivTest_q <= 2'b11; - 3'b101 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b110 : excREnc_uid133_fpDivTest_q <= 2'b00; - 3'b111 : excREnc_uid133_fpDivTest_q <= 2'b00; - default : begin - // unreachable - excREnc_uid133_fpDivTest_q <= 2'bxx; - end - endcase - end - end - - // redist3_excREnc_uid133_fpDivTest_q_9(DELAY,189) - dspba_delay_ver #( .width(2), .depth(8), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist3_excREnc_uid133_fpDivTest_q_9 ( .xin(excREnc_uid133_fpDivTest_q), .xout(redist3_excREnc_uid133_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expRPostExc_uid141_fpDivTest(MUX,140)@34 - assign expRPostExc_uid141_fpDivTest_s = redist3_excREnc_uid133_fpDivTest_q_9_q; - always @(expRPostExc_uid141_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or expRPreExc_uid112_fpDivTest_q or cstAllOWE_uid18_fpDivTest_q) - begin - unique case (expRPostExc_uid141_fpDivTest_s) - 2'b00 : expRPostExc_uid141_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; - 2'b01 : expRPostExc_uid141_fpDivTest_q = expRPreExc_uid112_fpDivTest_q; - 2'b10 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - 2'b11 : expRPostExc_uid141_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; - default : expRPostExc_uid141_fpDivTest_q = 8'b0; - endcase - end - - // oneFracRPostExc2_uid134_fpDivTest(CONSTANT,133) - assign oneFracRPostExc2_uid134_fpDivTest_q = 23'b00000000000000000000001; - - // fracPostRndFPostUlp_uid106_fpDivTest(BITSELECT,105)@33 - assign fracPostRndFPostUlp_uid106_fpDivTest_in = fracRPreExcExt_uid105_fpDivTest_q[22:0]; - assign fracPostRndFPostUlp_uid106_fpDivTest_b = fracPostRndFPostUlp_uid106_fpDivTest_in[22:0]; - - // fracRPreExc_uid107_fpDivTest(MUX,106)@33 + 1 - assign fracRPreExc_uid107_fpDivTest_s = extraUlp_uid103_fpDivTest_q; - always @ (posedge clk) - begin - if (areset) - begin - fracRPreExc_uid107_fpDivTest_q <= 23'b0; - end - else if (en == 1'b1) - begin - unique case (fracRPreExc_uid107_fpDivTest_s) - 1'b0 : fracRPreExc_uid107_fpDivTest_q <= redist4_fracPostRndFT_uid104_fpDivTest_b_8_mem_q; - 1'b1 : fracRPreExc_uid107_fpDivTest_q <= fracPostRndFPostUlp_uid106_fpDivTest_b; - default : fracRPreExc_uid107_fpDivTest_q <= 23'b0; - endcase - end - end - - // fracRPostExc_uid137_fpDivTest(MUX,136)@34 - assign fracRPostExc_uid137_fpDivTest_s = redist3_excREnc_uid133_fpDivTest_q_9_q; - always @(fracRPostExc_uid137_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or fracRPreExc_uid107_fpDivTest_q or oneFracRPostExc2_uid134_fpDivTest_q) - begin - unique case (fracRPostExc_uid137_fpDivTest_s) - 2'b00 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b01 : fracRPostExc_uid137_fpDivTest_q = fracRPreExc_uid107_fpDivTest_q; - 2'b10 : fracRPostExc_uid137_fpDivTest_q = paddingY_uid15_fpDivTest_q; - 2'b11 : fracRPostExc_uid137_fpDivTest_q = oneFracRPostExc2_uid134_fpDivTest_q; - default : fracRPostExc_uid137_fpDivTest_q = 23'b0; - endcase - end - - // divR_uid144_fpDivTest(BITJOIN,143)@34 - assign divR_uid144_fpDivTest_q = {redist2_sRPostExc_uid143_fpDivTest_q_9_q, expRPostExc_uid141_fpDivTest_q, fracRPostExc_uid137_fpDivTest_q}; - - // xOut(GPOUT,4)@34 - assign q = divR_uid144_fpDivTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex b/hw/rtl/fp_cores/altera/stratix10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex deleted file mode 100644 index 915d30cb..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex +++ /dev/null @@ -1,514 +0,0 @@ -:020000040000FA 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-:0201EE00021BF2 -:0201EF00021BF1 -:0201F0000218F3 -:0201F1000217F3 -:0201F2000216F3 -:0201F3000214F4 -:0201F4000212F5 -:0201F5000211F5 -:0201F600020FF6 -:0201F700020EF6 -:0201F800020CF7 -:0201F900020CF6 -:0201FA00020AF7 -:0201FB000207F9 -:0201FC000206F9 -:0201FD000205F9 -:0201FE000204F9 -:0201FF0001FFFE -:00000001ff diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv deleted file mode 100644 index c081092f..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_fmadd.sv +++ /dev/null @@ -1,74 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fmadd -// SystemVerilog created on Sun Dec 27 09:48:58 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fmadd ( - input wire [31:0] a, - input wire [31:0] b, - input wire [31:0] c, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire fpMultAddTest_impl_reset0; - wire fpMultAddTest_impl_ena0; - wire [31:0] fpMultAddTest_impl_ax0; - wire [31:0] fpMultAddTest_impl_ay0; - wire [31:0] fpMultAddTest_impl_az0; - wire [31:0] fpMultAddTest_impl_q0; - - - // fpMultAddTest_impl(FPCOLUMN,5)@0 - // out q0@4 - assign fpMultAddTest_impl_ax0 = c; - assign fpMultAddTest_impl_ay0 = b; - assign fpMultAddTest_impl_az0 = a; - assign fpMultAddTest_impl_reset0 = areset; - assign fpMultAddTest_impl_ena0 = en[0] | fpMultAddTest_impl_reset0; - fourteennm_fp_mac #( - .operation_mode("sp_mult_add"), - .ax_clock("0"), - .ay_clock("0"), - .az_clock("0"), - .mult_2nd_pipeline_clock("0"), - .adder_input_clock("0"), - .ax_chainin_pl_clock("0"), - .output_clock("0"), - .clear_type("sclr") - ) fpMultAddTest_impl_DSP0 ( - .clk({1'b0,1'b0,clk}), - .ena({ 1'b0, 1'b0, fpMultAddTest_impl_ena0 }), - .clr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }), - .ax(fpMultAddTest_impl_ax0), - .ay(fpMultAddTest_impl_ay0), - .az(fpMultAddTest_impl_az0), - .resulta(fpMultAddTest_impl_q0), - .accumulate(), - .chainin(), - .chainout() - ); - - // xOut(GPOUT,4)@4 - assign q = fpMultAddTest_impl_q0; - -endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv deleted file mode 100644 index 738d4c81..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt.sv +++ /dev/null @@ -1,2116 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_fsqrt -// SystemVerilog created on Sun Dec 27 09:48:58 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_fsqrt ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] expX_uid6_fpSqrtTest_b; - wire [0:0] signX_uid7_fpSqrtTest_b; - wire [7:0] cstAllOWE_uid8_fpSqrtTest_q; - wire [22:0] cstZeroWF_uid9_fpSqrtTest_q; - wire [7:0] cstAllZWE_uid10_fpSqrtTest_q; - wire [22:0] frac_x_uid12_fpSqrtTest_b; - wire [0:0] excZ_x_uid13_fpSqrtTest_qi; - reg [0:0] excZ_x_uid13_fpSqrtTest_q; - wire [0:0] expXIsMax_uid14_fpSqrtTest_qi; - reg [0:0] expXIsMax_uid14_fpSqrtTest_q; - wire [0:0] fracXIsZero_uid15_fpSqrtTest_qi; - reg [0:0] fracXIsZero_uid15_fpSqrtTest_q; - wire [0:0] fracXIsNotZero_uid16_fpSqrtTest_q; - wire [0:0] excI_x_uid17_fpSqrtTest_q; - wire [0:0] excN_x_uid18_fpSqrtTest_q; - wire [0:0] invExpXIsMax_uid19_fpSqrtTest_q; - wire [0:0] InvExpXIsZero_uid20_fpSqrtTest_q; - wire [0:0] excR_x_uid21_fpSqrtTest_q; - wire [7:0] sBias_uid22_fpSqrtTest_q; - wire [8:0] expEvenSig_uid24_fpSqrtTest_a; - wire [8:0] expEvenSig_uid24_fpSqrtTest_b; - logic [8:0] expEvenSig_uid24_fpSqrtTest_o; - wire [8:0] expEvenSig_uid24_fpSqrtTest_q; - wire [7:0] expREven_uid25_fpSqrtTest_b; - wire [7:0] sBiasM1_uid26_fpSqrtTest_q; - wire [8:0] expOddSig_uid27_fpSqrtTest_a; - wire [8:0] expOddSig_uid27_fpSqrtTest_b; - logic [8:0] expOddSig_uid27_fpSqrtTest_o; - wire [8:0] expOddSig_uid27_fpSqrtTest_q; - wire [7:0] expROdd_uid28_fpSqrtTest_b; - wire [0:0] expX0PS_uid29_fpSqrtTest_in; - wire [0:0] expX0PS_uid29_fpSqrtTest_b; - wire [0:0] expOddSelect_uid30_fpSqrtTest_q; - wire [0:0] expRMux_uid31_fpSqrtTest_s; - reg [7:0] expRMux_uid31_fpSqrtTest_q; - wire [23:0] addrFull_uid33_fpSqrtTest_q; - wire [7:0] yAddr_uid35_fpSqrtTest_b; - wire [15:0] yForPe_uid36_fpSqrtTest_in; - wire [15:0] yForPe_uid36_fpSqrtTest_b; - wire [30:0] expIncPEOnly_uid38_fpSqrtTest_in; - wire [0:0] expIncPEOnly_uid38_fpSqrtTest_b; - wire [28:0] fracRPreCR_uid39_fpSqrtTest_in; - wire [23:0] fracRPreCR_uid39_fpSqrtTest_b; - wire [24:0] fracPaddingOne_uid41_fpSqrtTest_q; - wire [23:0] oFracX_uid44_fpSqrtTest_q; - wire [24:0] oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; - wire [24:0] oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; - wire [0:0] normalizedXForComp_uid54_fpSqrtTest_s; - reg [24:0] normalizedXForComp_uid54_fpSqrtTest_q; - wire [24:0] paddingY_uid55_fpSqrtTest_q; - wire [49:0] updatedY_uid56_fpSqrtTest_q; - wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_a; - wire [51:0] squaredResultGTEIn_uid55_fpSqrtTest_b; - logic [51:0] squaredResultGTEIn_uid55_fpSqrtTest_o; - wire [0:0] squaredResultGTEIn_uid55_fpSqrtTest_n; - wire [0:0] pLTOne_uid58_fpSqrtTest_q; - wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a; - wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b; - logic [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o; - wire [24:0] fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q; - wire [0:0] fracPENotOne_uid62_fpSqrtTest_q; - wire [0:0] fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; - wire [0:0] expInc_uid64_fpSqrtTest_qi; - reg [0:0] expInc_uid64_fpSqrtTest_q; - wire [8:0] expR_uid66_fpSqrtTest_a; - wire [8:0] expR_uid66_fpSqrtTest_b; - logic [8:0] expR_uid66_fpSqrtTest_o; - wire [8:0] expR_uid66_fpSqrtTest_q; - wire [0:0] invSignX_uid67_fpSqrtTest_q; - wire [0:0] inInfAndNotNeg_uid68_fpSqrtTest_q; - wire [0:0] minReg_uid69_fpSqrtTest_q; - wire [0:0] minInf_uid70_fpSqrtTest_q; - wire [0:0] excRNaN_uid71_fpSqrtTest_q; - wire [2:0] excConc_uid72_fpSqrtTest_q; - wire [3:0] fracSelIn_uid73_fpSqrtTest_q; - reg [1:0] fracSel_uid74_fpSqrtTest_q; - wire [7:0] expRR_uid77_fpSqrtTest_in; - wire [7:0] expRR_uid77_fpSqrtTest_b; - wire [1:0] expRPostExc_uid79_fpSqrtTest_s; - reg [7:0] expRPostExc_uid79_fpSqrtTest_q; - wire [22:0] fracNaN_uid80_fpSqrtTest_q; - wire [1:0] fracRPostExc_uid84_fpSqrtTest_s; - reg [22:0] fracRPostExc_uid84_fpSqrtTest_q; - wire [0:0] negZero_uid85_fpSqrtTest_qi; - reg [0:0] negZero_uid85_fpSqrtTest_q; - wire [31:0] RSqrt_uid86_fpSqrtTest_q; - wire [11:0] yT1_uid100_invPolyEval_b; - wire [0:0] lowRangeB_uid102_invPolyEval_in; - wire [0:0] lowRangeB_uid102_invPolyEval_b; - wire [11:0] highBBits_uid103_invPolyEval_b; - wire [21:0] s1sumAHighB_uid104_invPolyEval_a; - wire [21:0] s1sumAHighB_uid104_invPolyEval_b; - logic [21:0] s1sumAHighB_uid104_invPolyEval_o; - wire [21:0] s1sumAHighB_uid104_invPolyEval_q; - wire [22:0] s1_uid105_invPolyEval_q; - wire [1:0] lowRangeB_uid108_invPolyEval_in; - wire [1:0] lowRangeB_uid108_invPolyEval_b; - wire [21:0] highBBits_uid109_invPolyEval_b; - wire [29:0] s2sumAHighB_uid110_invPolyEval_a; - wire [29:0] s2sumAHighB_uid110_invPolyEval_b; - logic [29:0] s2sumAHighB_uid110_invPolyEval_o; - wire [29:0] s2sumAHighB_uid110_invPolyEval_q; - wire [31:0] s2_uid111_invPolyEval_q; - wire [12:0] osig_uid114_pT1_uid101_invPolyEval_b; - wire [23:0] osig_uid117_pT2_uid107_invPolyEval_b; - wire memoryC0_uid88_sqrtTables_lutmem_reset0; - wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ia; - wire [7:0] memoryC0_uid88_sqrtTables_lutmem_aa; - wire [7:0] memoryC0_uid88_sqrtTables_lutmem_ab; - wire [28:0] memoryC0_uid88_sqrtTables_lutmem_ir; - wire [28:0] memoryC0_uid88_sqrtTables_lutmem_r; - wire memoryC0_uid88_sqrtTables_lutmem_enaOr_rst; - wire memoryC1_uid91_sqrtTables_lutmem_reset0; - wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ia; - wire [7:0] memoryC1_uid91_sqrtTables_lutmem_aa; - wire [7:0] memoryC1_uid91_sqrtTables_lutmem_ab; - wire [20:0] memoryC1_uid91_sqrtTables_lutmem_ir; - wire [20:0] memoryC1_uid91_sqrtTables_lutmem_r; - wire memoryC1_uid91_sqrtTables_lutmem_enaOr_rst; - wire memoryC2_uid94_sqrtTables_lutmem_reset0; - wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ia; - wire [7:0] memoryC2_uid94_sqrtTables_lutmem_aa; - wire [7:0] memoryC2_uid94_sqrtTables_lutmem_ab; - wire [11:0] memoryC2_uid94_sqrtTables_lutmem_ir; - wire [11:0] memoryC2_uid94_sqrtTables_lutmem_r; - wire memoryC2_uid94_sqrtTables_lutmem_enaOr_rst; - wire squaredResult_uid42_fpSqrtTest_cma_reset; - (* preserve_syn_only *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_ah [0:0]; - (* preserve_syn_only *) reg [24:0] squaredResult_uid42_fpSqrtTest_cma_ch [0:0]; - wire [24:0] squaredResult_uid42_fpSqrtTest_cma_a0; - wire [24:0] squaredResult_uid42_fpSqrtTest_cma_c0; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_s0; - wire [49:0] squaredResult_uid42_fpSqrtTest_cma_qq; - reg [49:0] squaredResult_uid42_fpSqrtTest_cma_q; - wire squaredResult_uid42_fpSqrtTest_cma_ena0; - wire squaredResult_uid42_fpSqrtTest_cma_ena1; - wire squaredResult_uid42_fpSqrtTest_cma_ena2; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_reset; - (* preserve_syn_only *) reg [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_ah [0:0]; - (* preserve_syn_only *) reg signed [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_ch [0:0]; - wire [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_a0; - wire [11:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_c0; - wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_s0; - wire [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_qq; - reg [23:0] prodXY_uid113_pT1_uid101_invPolyEval_cma_q; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1; - wire prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_reset; - (* preserve_syn_only *) reg [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_ah [0:0]; - (* preserve_syn_only *) reg signed [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_ch [0:0]; - wire [15:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_a0; - wire [22:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_c0; - wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_s0; - wire [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_qq; - reg [38:0] prodXY_uid116_pT2_uid107_invPolyEval_cma_q; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1; - wire prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2; - wire [0:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; - wire [22:0] expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c; - reg [22:0] redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; - reg [11:0] redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q; - reg [0:0] redist2_lowRangeB_uid102_invPolyEval_b_1_q; - reg [23:0] redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q; - reg [0:0] redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q; - reg [7:0] redist9_expRMux_uid31_fpSqrtTest_q_2_q; - reg [0:0] redist10_expOddSelect_uid30_fpSqrtTest_q_23_q; - reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_3_q; - reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0; - reg [22:0] redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1; - reg [0:0] redist13_signX_uid7_fpSqrtTest_b_24_q; - wire redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0; - wire [23:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ia; - wire [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_aa; - wire [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ab; - wire [23:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_iq; - wire [23:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_q; - wire redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_enaOr_rst; - wire [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i; - (* preserve_syn_only *) reg redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq; - wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s; - reg [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q; - reg [2:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q; - wire [3:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last_q; - wire [3:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_b; - wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_q; - reg [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q; - wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable_q; - wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor_q; - (* preserve_syn_only *) reg [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q; - wire [0:0] redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd_q; - reg [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q; - wire redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ia; - wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_aa; - wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ab; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_iq; - wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_q; - wire redist6_yForPe_uid36_fpSqrtTest_b_7_mem_enaOr_rst; - wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i; - (* preserve_syn_only *) reg redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s; - reg [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q; - reg [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q; - wire [2:0] redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_cmp_q; - reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_nor_q; - (* preserve_syn_only *) reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q; - wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd_q; - reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q; - wire redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0; - wire [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ia; - wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_aa; - wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ab; - wire [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_iq; - wire [7:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_q; - wire redist7_yAddr_uid35_fpSqrtTest_b_7_mem_enaOr_rst; - wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i; - (* preserve_syn_only *) reg redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq; - wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s; - reg [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q; - reg [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q; - wire [2:0] redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last_q; - wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_cmp_q; - reg [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q; - wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable_q; - wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_nor_q; - (* preserve_syn_only *) reg [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q; - wire [0:0] redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd_q; - reg [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q; - wire redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0; - wire [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ia; - wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_aa; - wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ab; - wire [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_iq; - wire [7:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_q; - wire redist8_yAddr_uid35_fpSqrtTest_b_14_mem_enaOr_rst; - wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q; - (* preserve_syn_only *) reg [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i; - (* preserve_syn_only *) reg redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq; - wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s; - reg [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q; - reg [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q; - wire [2:0] redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last_q; - wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_cmp_q; - reg [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q; - wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable_q; - wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_nor_q; - (* preserve_syn_only *) reg [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q; - wire [0:0] redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd_q; - wire redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0; - wire [22:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ia; - wire [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_aa; - wire [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ab; - wire [22:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_iq; - wire [22:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q; - wire redist12_frac_x_uid12_fpSqrtTest_b_23_mem_enaOr_rst; - wire [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q; - (* preserve_syn_only *) reg [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i; - (* preserve_syn_only *) reg redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq; - wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s; - reg [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q; - reg [4:0] redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q; - wire [5:0] redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last_q; - wire [5:0] redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_b; - wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_q; - reg [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q; - wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable_q; - wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_nor_q; - (* preserve_syn_only *) reg [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q; - wire [0:0] redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd_q; - wire redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0; - wire [7:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_ia; - wire [4:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_aa; - wire [4:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_ab; - wire [7:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_iq; - wire [7:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_q; - wire redist14_expX_uid6_fpSqrtTest_b_23_mem_enaOr_rst; - wire [4:0] redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q; - (* preserve_syn_only *) reg [4:0] redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i; - (* preserve_syn_only *) reg redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq; - wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s; - reg [4:0] redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q; - reg [4:0] redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q; - wire [5:0] redist14_expX_uid6_fpSqrtTest_b_23_mem_last_q; - wire [5:0] redist14_expX_uid6_fpSqrtTest_b_23_cmp_b; - wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_cmp_q; - reg [0:0] redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q; - wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_notEnable_q; - wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_nor_q; - (* preserve_syn_only *) reg [0:0] redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q; - wire [0:0] redist14_expX_uid6_fpSqrtTest_b_23_enaAnd_q; - - - // signX_uid7_fpSqrtTest(BITSELECT,6)@0 - assign signX_uid7_fpSqrtTest_b = a[31:31]; - - // redist13_signX_uid7_fpSqrtTest_b_24(DELAY,138) - dspba_delay_ver #( .width(1), .depth(24), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist13_signX_uid7_fpSqrtTest_b_24 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist13_signX_uid7_fpSqrtTest_b_24_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) - assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; - - // redist14_expX_uid6_fpSqrtTest_b_23_notEnable(LOGICAL,205) - assign redist14_expX_uid6_fpSqrtTest_b_23_notEnable_q = ~ (en); - - // redist14_expX_uid6_fpSqrtTest_b_23_nor(LOGICAL,206) - assign redist14_expX_uid6_fpSqrtTest_b_23_nor_q = ~ (redist14_expX_uid6_fpSqrtTest_b_23_notEnable_q | redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q); - - // redist14_expX_uid6_fpSqrtTest_b_23_mem_last(CONSTANT,202) - assign redist14_expX_uid6_fpSqrtTest_b_23_mem_last_q = 6'b010100; - - // redist14_expX_uid6_fpSqrtTest_b_23_cmp(LOGICAL,203) - assign redist14_expX_uid6_fpSqrtTest_b_23_cmp_b = {1'b0, redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q}; - assign redist14_expX_uid6_fpSqrtTest_b_23_cmp_q = redist14_expX_uid6_fpSqrtTest_b_23_mem_last_q == redist14_expX_uid6_fpSqrtTest_b_23_cmp_b ? 1'b1 : 1'b0; - - // redist14_expX_uid6_fpSqrtTest_b_23_cmpReg(REG,204) - always @ (posedge clk) - begin - if (areset) - begin - redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q <= redist14_expX_uid6_fpSqrtTest_b_23_cmp_q; - end - end - - // redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena(REG,207) - always @ (posedge clk) - begin - if (areset) - begin - redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q <= 1'b0; - end - else if (redist14_expX_uid6_fpSqrtTest_b_23_nor_q == 1'b1) - begin - redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q <= redist14_expX_uid6_fpSqrtTest_b_23_cmpReg_q; - end - end - - // redist14_expX_uid6_fpSqrtTest_b_23_enaAnd(LOGICAL,208) - assign redist14_expX_uid6_fpSqrtTest_b_23_enaAnd_q = redist14_expX_uid6_fpSqrtTest_b_23_sticky_ena_q & en; - - // redist14_expX_uid6_fpSqrtTest_b_23_rdcnt(COUNTER,199) - // low=0, high=21, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i <= 5'd0; - redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i == 5'd20) - begin - redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq <= 1'b1; - end - else - begin - redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; - end - if (redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_eq == 1'b1) - begin - redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd11); - end - else - begin - redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd1); - end - end - end - assign redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q = redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_i[4:0]; - - // redist14_expX_uid6_fpSqrtTest_b_23_rdmux(MUX,200) - assign redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s = en; - always @(redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s or redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q or redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q) - begin - unique case (redist14_expX_uid6_fpSqrtTest_b_23_rdmux_s) - 1'b0 : redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q = redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q; - 1'b1 : redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q = redist14_expX_uid6_fpSqrtTest_b_23_rdcnt_q; - default : redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q = 5'b0; - endcase - end - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // expX_uid6_fpSqrtTest(BITSELECT,5)@0 - assign expX_uid6_fpSqrtTest_b = a[30:23]; - - // redist14_expX_uid6_fpSqrtTest_b_23_wraddr(REG,201) - always @ (posedge clk) - begin - if (areset) - begin - redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q <= 5'b10101; - end - else - begin - redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q <= redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q; - end - end - - // redist14_expX_uid6_fpSqrtTest_b_23_mem(DUALMEM,198) - assign redist14_expX_uid6_fpSqrtTest_b_23_mem_ia = expX_uid6_fpSqrtTest_b; - assign redist14_expX_uid6_fpSqrtTest_b_23_mem_aa = redist14_expX_uid6_fpSqrtTest_b_23_wraddr_q; - assign redist14_expX_uid6_fpSqrtTest_b_23_mem_ab = redist14_expX_uid6_fpSqrtTest_b_23_rdmux_q; - assign redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(5), - .numwords_a(22), - .width_b(8), - .widthad_b(5), - .numwords_b(22), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist14_expX_uid6_fpSqrtTest_b_23_mem_dmem ( - .clocken1(redist14_expX_uid6_fpSqrtTest_b_23_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0), - .clock1(clk), - .address_a(redist14_expX_uid6_fpSqrtTest_b_23_mem_aa), - .data_a(redist14_expX_uid6_fpSqrtTest_b_23_mem_ia), - .wren_a(en[0]), - .address_b(redist14_expX_uid6_fpSqrtTest_b_23_mem_ab), - .q_b(redist14_expX_uid6_fpSqrtTest_b_23_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist14_expX_uid6_fpSqrtTest_b_23_mem_q = redist14_expX_uid6_fpSqrtTest_b_23_mem_iq[7:0]; - assign redist14_expX_uid6_fpSqrtTest_b_23_mem_enaOr_rst = redist14_expX_uid6_fpSqrtTest_b_23_enaAnd_q[0] | redist14_expX_uid6_fpSqrtTest_b_23_mem_reset0; - - // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@23 + 1 - assign excZ_x_uid13_fpSqrtTest_qi = redist14_expX_uid6_fpSqrtTest_b_23_mem_q == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // negZero_uid85_fpSqrtTest(LOGICAL,84)@24 + 1 - assign negZero_uid85_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist13_signX_uid7_fpSqrtTest_b_24_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - negZero_uid85_fpSqrtTest_delay ( .xin(negZero_uid85_fpSqrtTest_qi), .xout(negZero_uid85_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) - assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable(LOGICAL,194) - assign redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable_q = ~ (en); - - // redist12_frac_x_uid12_fpSqrtTest_b_23_nor(LOGICAL,195) - assign redist12_frac_x_uid12_fpSqrtTest_b_23_nor_q = ~ (redist12_frac_x_uid12_fpSqrtTest_b_23_notEnable_q | redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q); - - // redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last(CONSTANT,191) - assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last_q = 6'b010001; - - // redist12_frac_x_uid12_fpSqrtTest_b_23_cmp(LOGICAL,192) - assign redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_b = {1'b0, redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q}; - assign redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_q = redist12_frac_x_uid12_fpSqrtTest_b_23_mem_last_q == redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_b ? 1'b1 : 1'b0; - - // redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg(REG,193) - always @ (posedge clk) - begin - if (areset) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q <= redist12_frac_x_uid12_fpSqrtTest_b_23_cmp_q; - end - end - - // redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena(REG,196) - always @ (posedge clk) - begin - if (areset) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q <= 1'b0; - end - else if (redist12_frac_x_uid12_fpSqrtTest_b_23_nor_q == 1'b1) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q <= redist12_frac_x_uid12_fpSqrtTest_b_23_cmpReg_q; - end - end - - // redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd(LOGICAL,197) - assign redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd_q = redist12_frac_x_uid12_fpSqrtTest_b_23_sticky_ena_q & en; - - // redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt(COUNTER,188) - // low=0, high=18, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i <= 5'd0; - redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i == 5'd17) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq <= 1'b1; - end - else - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq <= 1'b0; - end - if (redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_eq == 1'b1) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd14); - end - else - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i <= $unsigned(redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i) + $unsigned(5'd1); - end - end - end - assign redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q = redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_i[4:0]; - - // redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux(MUX,189) - assign redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s = en; - always @(redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s or redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q or redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q) - begin - unique case (redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_s) - 1'b0 : redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q = redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q; - 1'b1 : redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q = redist12_frac_x_uid12_fpSqrtTest_b_23_rdcnt_q; - default : redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q = 5'b0; - endcase - end - - // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 - assign frac_x_uid12_fpSqrtTest_b = a[22:0]; - - // redist11_frac_x_uid12_fpSqrtTest_b_3(DELAY,136) - always @ (posedge clk) - begin - if (areset) - begin - redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0 <= '0; - redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1 <= '0; - redist11_frac_x_uid12_fpSqrtTest_b_3_q <= '0; - end - else if (en == 1'b1) - begin - redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0 <= frac_x_uid12_fpSqrtTest_b; - redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1 <= redist11_frac_x_uid12_fpSqrtTest_b_3_delay_0; - redist11_frac_x_uid12_fpSqrtTest_b_3_q <= redist11_frac_x_uid12_fpSqrtTest_b_3_delay_1; - end - end - - // redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr(REG,190) - always @ (posedge clk) - begin - if (areset) - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q <= 5'b10010; - end - else - begin - redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q <= redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q; - end - end - - // redist12_frac_x_uid12_fpSqrtTest_b_23_mem(DUALMEM,187) - assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ia = redist11_frac_x_uid12_fpSqrtTest_b_3_q; - assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_aa = redist12_frac_x_uid12_fpSqrtTest_b_23_wraddr_q; - assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ab = redist12_frac_x_uid12_fpSqrtTest_b_23_rdmux_q; - assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(23), - .widthad_a(5), - .numwords_a(19), - .width_b(23), - .widthad_b(5), - .numwords_b(19), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist12_frac_x_uid12_fpSqrtTest_b_23_mem_dmem ( - .clocken1(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0), - .clock1(clk), - .address_a(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_aa), - .data_a(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ia), - .wren_a(en[0]), - .address_b(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_ab), - .q_b(redist12_frac_x_uid12_fpSqrtTest_b_23_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q = redist12_frac_x_uid12_fpSqrtTest_b_23_mem_iq[22:0]; - assign redist12_frac_x_uid12_fpSqrtTest_b_23_mem_enaOr_rst = redist12_frac_x_uid12_fpSqrtTest_b_23_enaAnd_q[0] | redist12_frac_x_uid12_fpSqrtTest_b_23_mem_reset0; - - // oFracX_uid44_fpSqrtTest(BITJOIN,43)@23 - assign oFracX_uid44_fpSqrtTest_q = {VCC_q, redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q}; - - // oFracXZ_mergedSignalTM_uid47_fpSqrtTest(BITJOIN,46)@23 - assign oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q = {oFracX_uid44_fpSqrtTest_q, GND_q}; - - // oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest(BITJOIN,51)@23 - assign oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q = {GND_q, oFracX_uid44_fpSqrtTest_q}; - - // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 - assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; - assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; - - // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 - assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); - - // redist10_expOddSelect_uid30_fpSqrtTest_q_23(DELAY,135) - dspba_delay_ver #( .width(1), .depth(23), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist10_expOddSelect_uid30_fpSqrtTest_q_23 ( .xin(expOddSelect_uid30_fpSqrtTest_q), .xout(redist10_expOddSelect_uid30_fpSqrtTest_q_23_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // normalizedXForComp_uid54_fpSqrtTest(MUX,53)@23 - assign normalizedXForComp_uid54_fpSqrtTest_s = redist10_expOddSelect_uid30_fpSqrtTest_q_23_q; - always @(normalizedXForComp_uid54_fpSqrtTest_s or en or oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q or oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q) - begin - unique case (normalizedXForComp_uid54_fpSqrtTest_s) - 1'b0 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXSignExt_mergedSignalTM_uid52_fpSqrtTest_q; - 1'b1 : normalizedXForComp_uid54_fpSqrtTest_q = oFracXZ_mergedSignalTM_uid47_fpSqrtTest_q; - default : normalizedXForComp_uid54_fpSqrtTest_q = 25'b0; - endcase - end - - // paddingY_uid55_fpSqrtTest(CONSTANT,54) - assign paddingY_uid55_fpSqrtTest_q = 25'b0000000000000000000000000; - - // updatedY_uid56_fpSqrtTest(BITJOIN,55)@23 - assign updatedY_uid56_fpSqrtTest_q = {normalizedXForComp_uid54_fpSqrtTest_q, paddingY_uid55_fpSqrtTest_q}; - - // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 - assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; - - // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 - assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; - - // memoryC2_uid94_sqrtTables_lutmem(DUALMEM,120)@0 + 2 - // in j@20000000 - assign memoryC2_uid94_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; - assign memoryC2_uid94_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(12), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_sclr_a("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC2_uid94_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Stratix 10") - ) memoryC2_uid94_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .sclr(memoryC2_uid94_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC2_uid94_sqrtTables_lutmem_aa), - .q_a(memoryC2_uid94_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC2_uid94_sqrtTables_lutmem_r = memoryC2_uid94_sqrtTables_lutmem_ir[11:0]; - assign memoryC2_uid94_sqrtTables_lutmem_enaOr_rst = en[0] | memoryC2_uid94_sqrtTables_lutmem_reset0; - - // redist1_memoryC2_uid94_sqrtTables_lutmem_r_1(DELAY,126) - always @ (posedge clk) - begin - if (areset) - begin - redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q <= '0; - end - else if (en == 1'b1) - begin - redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q <= memoryC2_uid94_sqrtTables_lutmem_r; - end - end - - // yForPe_uid36_fpSqrtTest(BITSELECT,35)@3 - assign yForPe_uid36_fpSqrtTest_in = redist11_frac_x_uid12_fpSqrtTest_b_3_q[15:0]; - assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; - - // yT1_uid100_invPolyEval(BITSELECT,99)@3 - assign yT1_uid100_invPolyEval_b = yForPe_uid36_fpSqrtTest_b[15:4]; - - // prodXY_uid113_pT1_uid101_invPolyEval_cma(CHAINMULTADD,122)@3 + 5 - // out q@9 - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_reset = areset; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 = en[0] | prodXY_uid113_pT1_uid101_invPolyEval_cma_reset; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0; - always @ (posedge clk) - begin - if (0) - begin - end - else - begin - if (en == 1'b1) - begin - prodXY_uid113_pT1_uid101_invPolyEval_cma_ah[0] <= yT1_uid100_invPolyEval_b; - prodXY_uid113_pT1_uid101_invPolyEval_cma_ch[0] <= redist1_memoryC2_uid94_sqrtTables_lutmem_r_1_q; - end - end - end - - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_a0 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ah[0]; - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_c0 = prodXY_uid113_pT1_uid101_invPolyEval_cma_ch[0]; - fourteennm_mac #( - .operation_mode("m18x18_full"), - .clear_type("sclr"), - .ay_scan_in_clock("0"), - .ay_scan_in_width(12), - .ax_clock("0"), - .ax_width(12), - .signed_may("false"), - .signed_max("true"), - .input_pipeline_clock("2"), - .second_pipeline_clock("2"), - .output_clock("1"), - .result_a_width(24) - ) prodXY_uid113_pT1_uid101_invPolyEval_cma_DSP0 ( - .clk({clk,clk,clk}), - .ena({ prodXY_uid113_pT1_uid101_invPolyEval_cma_ena2, prodXY_uid113_pT1_uid101_invPolyEval_cma_ena1, prodXY_uid113_pT1_uid101_invPolyEval_cma_ena0 }), - .clr({ prodXY_uid113_pT1_uid101_invPolyEval_cma_reset, prodXY_uid113_pT1_uid101_invPolyEval_cma_reset }), - .ay(prodXY_uid113_pT1_uid101_invPolyEval_cma_a0), - .ax(prodXY_uid113_pT1_uid101_invPolyEval_cma_c0), - .resulta(prodXY_uid113_pT1_uid101_invPolyEval_cma_s0), - .accumulate(), - .loadconst(), - .negate(), - .sub(), - .az(), - .coefsela(), - .bx(), - .by(), - .bz(), - .coefselb(), - .scanin(), - .scanout(), - .chainin(), - .chainout(), - .resultb(), - .dfxlfsrena(), - .dfxmisrena(), - .dftout() - ); - dspba_delay_ver #( .width(24), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) - prodXY_uid113_pT1_uid101_invPolyEval_cma_delay ( .xin(prodXY_uid113_pT1_uid101_invPolyEval_cma_s0), .xout(prodXY_uid113_pT1_uid101_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid113_pT1_uid101_invPolyEval_cma_q = prodXY_uid113_pT1_uid101_invPolyEval_cma_qq[23:0]; - - // osig_uid114_pT1_uid101_invPolyEval(BITSELECT,113)@9 - assign osig_uid114_pT1_uid101_invPolyEval_b = prodXY_uid113_pT1_uid101_invPolyEval_cma_q[23:11]; - - // highBBits_uid103_invPolyEval(BITSELECT,102)@9 - assign highBBits_uid103_invPolyEval_b = osig_uid114_pT1_uid101_invPolyEval_b[12:1]; - - // redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable(LOGICAL,171) - assign redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable_q = ~ (en); - - // redist7_yAddr_uid35_fpSqrtTest_b_7_nor(LOGICAL,172) - assign redist7_yAddr_uid35_fpSqrtTest_b_7_nor_q = ~ (redist7_yAddr_uid35_fpSqrtTest_b_7_notEnable_q | redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q); - - // redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last(CONSTANT,168) - assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last_q = 3'b011; - - // redist7_yAddr_uid35_fpSqrtTest_b_7_cmp(LOGICAL,169) - assign redist7_yAddr_uid35_fpSqrtTest_b_7_cmp_q = redist7_yAddr_uid35_fpSqrtTest_b_7_mem_last_q == redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q ? 1'b1 : 1'b0; - - // redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg(REG,170) - always @ (posedge clk) - begin - if (areset) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_cmp_q; - end - end - - // redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena(REG,173) - always @ (posedge clk) - begin - if (areset) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q <= 1'b0; - end - else if (redist7_yAddr_uid35_fpSqrtTest_b_7_nor_q == 1'b1) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_cmpReg_q; - end - end - - // redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd(LOGICAL,174) - assign redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd_q = redist7_yAddr_uid35_fpSqrtTest_b_7_sticky_ena_q & en; - - // redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt(COUNTER,165) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i <= 3'd0; - redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i == 3'd3) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq <= 1'b1; - end - else - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; - end - if (redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_eq == 1'b1) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q = redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_i[2:0]; - - // redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux(MUX,166) - assign redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s = en; - always @(redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s or redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q or redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q) - begin - unique case (redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_s) - 1'b0 : redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q = redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q; - 1'b1 : redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q = redist7_yAddr_uid35_fpSqrtTest_b_7_rdcnt_q; - default : redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q = 3'b0; - endcase - end - - // redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr(REG,167) - always @ (posedge clk) - begin - if (areset) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q <= 3'b100; - end - else - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q; - end - end - - // redist7_yAddr_uid35_fpSqrtTest_b_7_mem(DUALMEM,164) - assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ia = yAddr_uid35_fpSqrtTest_b; - assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_aa = redist7_yAddr_uid35_fpSqrtTest_b_7_wraddr_q; - assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ab = redist7_yAddr_uid35_fpSqrtTest_b_7_rdmux_q; - assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(3), - .numwords_a(5), - .width_b(8), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist7_yAddr_uid35_fpSqrtTest_b_7_mem_dmem ( - .clocken1(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0), - .clock1(clk), - .address_a(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_aa), - .data_a(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ia), - .wren_a(en[0]), - .address_b(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_ab), - .q_b(redist7_yAddr_uid35_fpSqrtTest_b_7_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_q = redist7_yAddr_uid35_fpSqrtTest_b_7_mem_iq[7:0]; - assign redist7_yAddr_uid35_fpSqrtTest_b_7_mem_enaOr_rst = redist7_yAddr_uid35_fpSqrtTest_b_7_enaAnd_q[0] | redist7_yAddr_uid35_fpSqrtTest_b_7_mem_reset0; - - // redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0(DELAY,163) - always @ (posedge clk) - begin - if (areset) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q <= redist7_yAddr_uid35_fpSqrtTest_b_7_mem_q; - end - end - - // memoryC1_uid91_sqrtTables_lutmem(DUALMEM,119)@7 + 2 - // in j@20000000 - assign memoryC1_uid91_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q; - assign memoryC1_uid91_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(21), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_sclr_a("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Stratix 10") - ) memoryC1_uid91_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .sclr(memoryC1_uid91_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC1_uid91_sqrtTables_lutmem_aa), - .q_a(memoryC1_uid91_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC1_uid91_sqrtTables_lutmem_r = memoryC1_uid91_sqrtTables_lutmem_ir[20:0]; - assign memoryC1_uid91_sqrtTables_lutmem_enaOr_rst = en[0] | memoryC1_uid91_sqrtTables_lutmem_reset0; - - // s1sumAHighB_uid104_invPolyEval(ADD,103)@9 + 1 - assign s1sumAHighB_uid104_invPolyEval_a = {{1{memoryC1_uid91_sqrtTables_lutmem_r[20]}}, memoryC1_uid91_sqrtTables_lutmem_r}; - assign s1sumAHighB_uid104_invPolyEval_b = {{10{highBBits_uid103_invPolyEval_b[11]}}, highBBits_uid103_invPolyEval_b}; - always @ (posedge clk) - begin - if (areset) - begin - s1sumAHighB_uid104_invPolyEval_o <= 22'b0; - end - else if (en == 1'b1) - begin - s1sumAHighB_uid104_invPolyEval_o <= $signed(s1sumAHighB_uid104_invPolyEval_a) + $signed(s1sumAHighB_uid104_invPolyEval_b); - end - end - assign s1sumAHighB_uid104_invPolyEval_q = s1sumAHighB_uid104_invPolyEval_o[21:0]; - - // lowRangeB_uid102_invPolyEval(BITSELECT,101)@9 - assign lowRangeB_uid102_invPolyEval_in = osig_uid114_pT1_uid101_invPolyEval_b[0:0]; - assign lowRangeB_uid102_invPolyEval_b = lowRangeB_uid102_invPolyEval_in[0:0]; - - // redist2_lowRangeB_uid102_invPolyEval_b_1(DELAY,127) - always @ (posedge clk) - begin - if (areset) - begin - redist2_lowRangeB_uid102_invPolyEval_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist2_lowRangeB_uid102_invPolyEval_b_1_q <= lowRangeB_uid102_invPolyEval_b; - end - end - - // s1_uid105_invPolyEval(BITJOIN,104)@10 - assign s1_uid105_invPolyEval_q = {s1sumAHighB_uid104_invPolyEval_q, redist2_lowRangeB_uid102_invPolyEval_b_1_q}; - - // redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable(LOGICAL,159) - assign redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable_q = ~ (en); - - // redist6_yForPe_uid36_fpSqrtTest_b_7_nor(LOGICAL,160) - assign redist6_yForPe_uid36_fpSqrtTest_b_7_nor_q = ~ (redist6_yForPe_uid36_fpSqrtTest_b_7_notEnable_q | redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q); - - // redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last(CONSTANT,156) - assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last_q = 3'b011; - - // redist6_yForPe_uid36_fpSqrtTest_b_7_cmp(LOGICAL,157) - assign redist6_yForPe_uid36_fpSqrtTest_b_7_cmp_q = redist6_yForPe_uid36_fpSqrtTest_b_7_mem_last_q == redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q ? 1'b1 : 1'b0; - - // redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg(REG,158) - always @ (posedge clk) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_cmp_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena(REG,161) - always @ (posedge clk) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q <= 1'b0; - end - else if (redist6_yForPe_uid36_fpSqrtTest_b_7_nor_q == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_cmpReg_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd(LOGICAL,162) - assign redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd_q = redist6_yForPe_uid36_fpSqrtTest_b_7_sticky_ena_q & en; - - // redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt(COUNTER,153) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i <= 3'd0; - redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i == 3'd3) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq <= 1'b1; - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq <= 1'b0; - end - if (redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_eq == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q = redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_i[2:0]; - - // redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux(MUX,154) - assign redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s = en; - always @(redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s or redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q or redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q) - begin - unique case (redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_s) - 1'b0 : redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q; - 1'b1 : redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_7_rdcnt_q; - default : redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q = 3'b0; - endcase - end - - // redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr(REG,155) - always @ (posedge clk) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q <= 3'b100; - end - else - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q; - end - end - - // redist6_yForPe_uid36_fpSqrtTest_b_7_mem(DUALMEM,152) - assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ia = yForPe_uid36_fpSqrtTest_b; - assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_aa = redist6_yForPe_uid36_fpSqrtTest_b_7_wraddr_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ab = redist6_yForPe_uid36_fpSqrtTest_b_7_rdmux_q; - assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(16), - .widthad_a(3), - .numwords_a(5), - .width_b(16), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist6_yForPe_uid36_fpSqrtTest_b_7_mem_dmem ( - .clocken1(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0), - .clock1(clk), - .address_a(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_aa), - .data_a(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ia), - .wren_a(en[0]), - .address_b(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_ab), - .q_b(redist6_yForPe_uid36_fpSqrtTest_b_7_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_q = redist6_yForPe_uid36_fpSqrtTest_b_7_mem_iq[15:0]; - assign redist6_yForPe_uid36_fpSqrtTest_b_7_mem_enaOr_rst = redist6_yForPe_uid36_fpSqrtTest_b_7_enaAnd_q[0] | redist6_yForPe_uid36_fpSqrtTest_b_7_mem_reset0; - - // redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0(DELAY,151) - always @ (posedge clk) - begin - if (areset) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q <= redist6_yForPe_uid36_fpSqrtTest_b_7_mem_q; - end - end - - // prodXY_uid116_pT2_uid107_invPolyEval_cma(CHAINMULTADD,123)@10 + 5 - // out q@16 - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_reset = areset; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 = en[0] | prodXY_uid116_pT2_uid107_invPolyEval_cma_reset; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0; - always @ (posedge clk) - begin - if (0) - begin - end - else - begin - if (en == 1'b1) - begin - prodXY_uid116_pT2_uid107_invPolyEval_cma_ah[0] <= redist6_yForPe_uid36_fpSqrtTest_b_7_outputreg0_q; - prodXY_uid116_pT2_uid107_invPolyEval_cma_ch[0] <= s1_uid105_invPolyEval_q; - end - end - end - - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_a0 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ah[0]; - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_c0 = prodXY_uid116_pT2_uid107_invPolyEval_cma_ch[0]; - fourteennm_mac #( - .operation_mode("m27x27"), - .clear_type("sclr"), - .use_chainadder("false"), - .ay_scan_in_clock("0"), - .ay_scan_in_width(16), - .ax_clock("0"), - .ax_width(23), - .signed_may("false"), - .signed_max("true"), - .input_pipeline_clock("2"), - .second_pipeline_clock("2"), - .output_clock("1"), - .result_a_width(39) - ) prodXY_uid116_pT2_uid107_invPolyEval_cma_DSP0 ( - .clk({clk,clk,clk}), - .ena({ prodXY_uid116_pT2_uid107_invPolyEval_cma_ena2, prodXY_uid116_pT2_uid107_invPolyEval_cma_ena1, prodXY_uid116_pT2_uid107_invPolyEval_cma_ena0 }), - .clr({ prodXY_uid116_pT2_uid107_invPolyEval_cma_reset, prodXY_uid116_pT2_uid107_invPolyEval_cma_reset }), - .ay(prodXY_uid116_pT2_uid107_invPolyEval_cma_a0), - .ax(prodXY_uid116_pT2_uid107_invPolyEval_cma_c0), - .resulta(prodXY_uid116_pT2_uid107_invPolyEval_cma_s0), - .accumulate(), - .loadconst(), - .negate(), - .sub(), - .az(), - .coefsela(), - .bx(), - .by(), - .bz(), - .coefselb(), - .scanin(), - .scanout(), - .chainin(), - .chainout(), - .resultb(), - .dfxlfsrena(), - .dfxmisrena(), - .dftout() - ); - dspba_delay_ver #( .width(39), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) - prodXY_uid116_pT2_uid107_invPolyEval_cma_delay ( .xin(prodXY_uid116_pT2_uid107_invPolyEval_cma_s0), .xout(prodXY_uid116_pT2_uid107_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign prodXY_uid116_pT2_uid107_invPolyEval_cma_q = prodXY_uid116_pT2_uid107_invPolyEval_cma_qq[38:0]; - - // osig_uid117_pT2_uid107_invPolyEval(BITSELECT,116)@16 - assign osig_uid117_pT2_uid107_invPolyEval_b = prodXY_uid116_pT2_uid107_invPolyEval_cma_q[38:15]; - - // highBBits_uid109_invPolyEval(BITSELECT,108)@16 - assign highBBits_uid109_invPolyEval_b = osig_uid117_pT2_uid107_invPolyEval_b[23:2]; - - // redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable(LOGICAL,183) - assign redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable_q = ~ (en); - - // redist8_yAddr_uid35_fpSqrtTest_b_14_nor(LOGICAL,184) - assign redist8_yAddr_uid35_fpSqrtTest_b_14_nor_q = ~ (redist8_yAddr_uid35_fpSqrtTest_b_14_notEnable_q | redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q); - - // redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last(CONSTANT,180) - assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last_q = 3'b011; - - // redist8_yAddr_uid35_fpSqrtTest_b_14_cmp(LOGICAL,181) - assign redist8_yAddr_uid35_fpSqrtTest_b_14_cmp_q = redist8_yAddr_uid35_fpSqrtTest_b_14_mem_last_q == redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q ? 1'b1 : 1'b0; - - // redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg(REG,182) - always @ (posedge clk) - begin - if (areset) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_cmp_q; - end - end - - // redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena(REG,185) - always @ (posedge clk) - begin - if (areset) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q <= 1'b0; - end - else if (redist8_yAddr_uid35_fpSqrtTest_b_14_nor_q == 1'b1) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_cmpReg_q; - end - end - - // redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd(LOGICAL,186) - assign redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd_q = redist8_yAddr_uid35_fpSqrtTest_b_14_sticky_ena_q & en; - - // redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt(COUNTER,177) - // low=0, high=4, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i <= 3'd0; - redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i == 3'd3) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq <= 1'b1; - end - else - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq <= 1'b0; - end - if (redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_eq == 1'b1) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i <= $unsigned(redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i) + $unsigned(3'd4); - end - else - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i <= $unsigned(redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q = redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_i[2:0]; - - // redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux(MUX,178) - assign redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s = en; - always @(redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s or redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q or redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q) - begin - unique case (redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_s) - 1'b0 : redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q = redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q; - 1'b1 : redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q = redist8_yAddr_uid35_fpSqrtTest_b_14_rdcnt_q; - default : redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q = 3'b0; - endcase - end - - // redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr(REG,179) - always @ (posedge clk) - begin - if (areset) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q <= 3'b100; - end - else - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q; - end - end - - // redist8_yAddr_uid35_fpSqrtTest_b_14_mem(DUALMEM,176) - assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ia = redist7_yAddr_uid35_fpSqrtTest_b_7_outputreg0_q; - assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_aa = redist8_yAddr_uid35_fpSqrtTest_b_14_wraddr_q; - assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ab = redist8_yAddr_uid35_fpSqrtTest_b_14_rdmux_q; - assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(8), - .widthad_a(3), - .numwords_a(5), - .width_b(8), - .widthad_b(3), - .numwords_b(5), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist8_yAddr_uid35_fpSqrtTest_b_14_mem_dmem ( - .clocken1(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0), - .clock1(clk), - .address_a(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_aa), - .data_a(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ia), - .wren_a(en[0]), - .address_b(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_ab), - .q_b(redist8_yAddr_uid35_fpSqrtTest_b_14_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_q = redist8_yAddr_uid35_fpSqrtTest_b_14_mem_iq[7:0]; - assign redist8_yAddr_uid35_fpSqrtTest_b_14_mem_enaOr_rst = redist8_yAddr_uid35_fpSqrtTest_b_14_enaAnd_q[0] | redist8_yAddr_uid35_fpSqrtTest_b_14_mem_reset0; - - // redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0(DELAY,175) - always @ (posedge clk) - begin - if (areset) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q <= '0; - end - else if (en == 1'b1) - begin - redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q <= redist8_yAddr_uid35_fpSqrtTest_b_14_mem_q; - end - end - - // memoryC0_uid88_sqrtTables_lutmem(DUALMEM,118)@14 + 2 - // in j@20000000 - assign memoryC0_uid88_sqrtTables_lutmem_aa = redist8_yAddr_uid35_fpSqrtTest_b_14_outputreg0_q; - assign memoryC0_uid88_sqrtTables_lutmem_reset0 = areset; - altera_syncram #( - .ram_block_type("M20K"), - .operation_mode("ROM"), - .width_a(29), - .widthad_a(8), - .numwords_a(256), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .outdata_reg_a("CLOCK0"), - .outdata_sclr_a("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .power_up_uninitialized("FALSE"), - .init_file("acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex"), - .init_file_layout("PORT_A"), - .intended_device_family("Stratix 10") - ) memoryC0_uid88_sqrtTables_lutmem_dmem ( - .clocken0(en[0]), - .sclr(memoryC0_uid88_sqrtTables_lutmem_reset0), - .clock0(clk), - .address_a(memoryC0_uid88_sqrtTables_lutmem_aa), - .q_a(memoryC0_uid88_sqrtTables_lutmem_ir), - .wren_a(), - .wren_b(), - .rden_a(), - .rden_b(), - .data_a(), - .data_b(), - .address_b(), - .clock1(), - .clocken1(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_b(), - .eccstatus() - ); - assign memoryC0_uid88_sqrtTables_lutmem_r = memoryC0_uid88_sqrtTables_lutmem_ir[28:0]; - assign memoryC0_uid88_sqrtTables_lutmem_enaOr_rst = en[0] | memoryC0_uid88_sqrtTables_lutmem_reset0; - - // s2sumAHighB_uid110_invPolyEval(ADD,109)@16 - assign s2sumAHighB_uid110_invPolyEval_a = {{1{memoryC0_uid88_sqrtTables_lutmem_r[28]}}, memoryC0_uid88_sqrtTables_lutmem_r}; - assign s2sumAHighB_uid110_invPolyEval_b = {{8{highBBits_uid109_invPolyEval_b[21]}}, highBBits_uid109_invPolyEval_b}; - assign s2sumAHighB_uid110_invPolyEval_o = $signed(s2sumAHighB_uid110_invPolyEval_a) + $signed(s2sumAHighB_uid110_invPolyEval_b); - assign s2sumAHighB_uid110_invPolyEval_q = s2sumAHighB_uid110_invPolyEval_o[29:0]; - - // lowRangeB_uid108_invPolyEval(BITSELECT,107)@16 - assign lowRangeB_uid108_invPolyEval_in = osig_uid117_pT2_uid107_invPolyEval_b[1:0]; - assign lowRangeB_uid108_invPolyEval_b = lowRangeB_uid108_invPolyEval_in[1:0]; - - // s2_uid111_invPolyEval(BITJOIN,110)@16 - assign s2_uid111_invPolyEval_q = {s2sumAHighB_uid110_invPolyEval_q, lowRangeB_uid108_invPolyEval_b}; - - // fracRPreCR_uid39_fpSqrtTest(BITSELECT,38)@16 - assign fracRPreCR_uid39_fpSqrtTest_in = s2_uid111_invPolyEval_q[28:0]; - assign fracRPreCR_uid39_fpSqrtTest_b = fracRPreCR_uid39_fpSqrtTest_in[28:5]; - - // redist3_fracRPreCR_uid39_fpSqrtTest_b_1(DELAY,128) - always @ (posedge clk) - begin - if (areset) - begin - redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q <= fracRPreCR_uid39_fpSqrtTest_b; - end - end - - // fracPaddingOne_uid41_fpSqrtTest(BITJOIN,40)@17 - assign fracPaddingOne_uid41_fpSqrtTest_q = {VCC_q, redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q}; - - // squaredResult_uid42_fpSqrtTest_cma(CHAINMULTADD,121)@17 + 5 - // out q@23 - assign squaredResult_uid42_fpSqrtTest_cma_reset = areset; - assign squaredResult_uid42_fpSqrtTest_cma_ena0 = en[0] | squaredResult_uid42_fpSqrtTest_cma_reset; - assign squaredResult_uid42_fpSqrtTest_cma_ena1 = squaredResult_uid42_fpSqrtTest_cma_ena0; - assign squaredResult_uid42_fpSqrtTest_cma_ena2 = squaredResult_uid42_fpSqrtTest_cma_ena0; - always @ (posedge clk) - begin - if (0) - begin - end - else - begin - if (en == 1'b1) - begin - squaredResult_uid42_fpSqrtTest_cma_ah[0] <= fracPaddingOne_uid41_fpSqrtTest_q; - squaredResult_uid42_fpSqrtTest_cma_ch[0] <= fracPaddingOne_uid41_fpSqrtTest_q; - end - end - end - - assign squaredResult_uid42_fpSqrtTest_cma_a0 = squaredResult_uid42_fpSqrtTest_cma_ah[0]; - assign squaredResult_uid42_fpSqrtTest_cma_c0 = squaredResult_uid42_fpSqrtTest_cma_ch[0]; - fourteennm_mac #( - .operation_mode("m27x27"), - .clear_type("sclr"), - .use_chainadder("false"), - .ay_scan_in_clock("0"), - .ay_scan_in_width(25), - .ax_clock("0"), - .ax_width(25), - .signed_may("false"), - .signed_max("false"), - .input_pipeline_clock("2"), - .second_pipeline_clock("2"), - .output_clock("1"), - .result_a_width(50) - ) squaredResult_uid42_fpSqrtTest_cma_DSP0 ( - .clk({clk,clk,clk}), - .ena({ squaredResult_uid42_fpSqrtTest_cma_ena2, squaredResult_uid42_fpSqrtTest_cma_ena1, squaredResult_uid42_fpSqrtTest_cma_ena0 }), - .clr({ squaredResult_uid42_fpSqrtTest_cma_reset, squaredResult_uid42_fpSqrtTest_cma_reset }), - .ay(squaredResult_uid42_fpSqrtTest_cma_a0), - .ax(squaredResult_uid42_fpSqrtTest_cma_c0), - .resulta(squaredResult_uid42_fpSqrtTest_cma_s0), - .accumulate(), - .loadconst(), - .negate(), - .sub(), - .az(), - .coefsela(), - .bx(), - .by(), - .bz(), - .coefselb(), - .scanin(), - .scanout(), - .chainin(), - .chainout(), - .resultb(), - .dfxlfsrena(), - .dfxmisrena(), - .dftout() - ); - dspba_delay_ver #( .width(50), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1) ) - squaredResult_uid42_fpSqrtTest_cma_delay ( .xin(squaredResult_uid42_fpSqrtTest_cma_s0), .xout(squaredResult_uid42_fpSqrtTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); - assign squaredResult_uid42_fpSqrtTest_cma_q = squaredResult_uid42_fpSqrtTest_cma_qq[49:0]; - - // squaredResultGTEIn_uid55_fpSqrtTest(COMPARE,56)@23 + 1 - assign squaredResultGTEIn_uid55_fpSqrtTest_a = {2'b00, squaredResult_uid42_fpSqrtTest_cma_q}; - assign squaredResultGTEIn_uid55_fpSqrtTest_b = {2'b00, updatedY_uid56_fpSqrtTest_q}; - always @ (posedge clk) - begin - if (areset) - begin - squaredResultGTEIn_uid55_fpSqrtTest_o <= 52'b0; - end - else if (en == 1'b1) - begin - squaredResultGTEIn_uid55_fpSqrtTest_o <= $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_a) - $unsigned(squaredResultGTEIn_uid55_fpSqrtTest_b); - end - end - assign squaredResultGTEIn_uid55_fpSqrtTest_n[0] = ~ (squaredResultGTEIn_uid55_fpSqrtTest_o[51]); - - // pLTOne_uid58_fpSqrtTest(LOGICAL,57)@24 - assign pLTOne_uid58_fpSqrtTest_q = ~ (squaredResultGTEIn_uid55_fpSqrtTest_n); - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable(LOGICAL,147) - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable_q = ~ (en); - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor(LOGICAL,148) - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor_q = ~ (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_notEnable_q | redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q); - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last(CONSTANT,144) - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last_q = 4'b0100; - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp(LOGICAL,145) - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_b = {1'b0, redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q}; - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_last_q == redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_b ? 1'b1 : 1'b0; - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg(REG,146) - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q <= 1'b0; - end - else if (en == 1'b1) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q <= redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmp_q; - end - end - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena(REG,149) - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q <= 1'b0; - end - else if (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_nor_q == 1'b1) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q <= redist4_fracRPreCR_uid39_fpSqrtTest_b_8_cmpReg_q; - end - end - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd(LOGICAL,150) - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_sticky_ena_q & en; - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt(COUNTER,141) - // low=0, high=5, step=1, init=0 - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i <= 3'd0; - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq <= 1'b0; - end - else if (en == 1'b1) - begin - if (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i == 3'd4) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq <= 1'b1; - end - else - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq <= 1'b0; - end - if (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_eq == 1'b1) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i <= $unsigned(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i) + $unsigned(3'd3); - end - else - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i <= $unsigned(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i) + $unsigned(3'd1); - end - end - end - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_i[2:0]; - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux(MUX,142) - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s = en; - always @(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s or redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q or redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q) - begin - unique case (redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_s) - 1'b0 : redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q; - 1'b1 : redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdcnt_q; - default : redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q = 3'b0; - endcase - end - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr(REG,143) - always @ (posedge clk) - begin - if (areset) - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q <= 3'b101; - end - else - begin - redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q <= redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q; - end - end - - // redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem(DUALMEM,140) - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ia = redist3_fracRPreCR_uid39_fpSqrtTest_b_1_q; - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_aa = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_wraddr_q; - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ab = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_rdmux_q; - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0 = areset; - altera_syncram #( - .ram_block_type("MLAB"), - .operation_mode("DUAL_PORT"), - .width_a(24), - .widthad_a(3), - .numwords_a(6), - .width_b(24), - .widthad_b(3), - .numwords_b(6), - .lpm_type("altera_syncram"), - .width_byteena_a(1), - .address_reg_b("CLOCK0"), - .indata_reg_b("CLOCK0"), - .rdcontrol_reg_b("CLOCK0"), - .byteena_reg_b("CLOCK0"), - .outdata_reg_b("CLOCK1"), - .outdata_sclr_b("SCLEAR"), - .clock_enable_input_a("NORMAL"), - .clock_enable_input_b("NORMAL"), - .clock_enable_output_b("NORMAL"), - .read_during_write_mode_mixed_ports("DONT_CARE"), - .power_up_uninitialized("TRUE"), - .intended_device_family("Stratix 10") - ) redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_dmem ( - .clocken1(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_enaOr_rst), - .clocken0(VCC_q[0]), - .clock0(clk), - .sclr(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0), - .clock1(clk), - .address_a(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_aa), - .data_a(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ia), - .wren_a(en[0]), - .address_b(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_ab), - .q_b(redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_iq), - .wren_b(), - .rden_a(), - .rden_b(), - .data_b(), - .clocken2(), - .clocken3(), - .aclr0(), - .aclr1(), - .addressstall_a(), - .addressstall_b(), - .byteena_a(), - .byteena_b(), - .eccencbypass(), - .eccencparity(), - .address2_a(), - .address2_b(), - .q_a(), - .eccstatus() - ); - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_q = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_iq[23:0]; - assign redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_enaOr_rst = redist4_fracRPreCR_uid39_fpSqrtTest_b_8_enaAnd_q[0] | redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_reset0; - - // fxpSqrtResPostUpdateE_uid60_fpSqrtTest(ADD,59)@24 - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a = {1'b0, redist4_fracRPreCR_uid39_fpSqrtTest_b_8_mem_q}; - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b = {24'b000000000000000000000000, pLTOne_uid58_fpSqrtTest_q}; - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o = $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_a) + $unsigned(fxpSqrtResPostUpdateE_uid60_fpSqrtTest_b); - assign fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_o[24:0]; - - // expUpdateCRU_uid61_fpSqrtTest_merged_bit_select(BITSELECT,124)@24 - assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[24:24]; - assign expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c = fxpSqrtResPostUpdateE_uid60_fpSqrtTest_q[23:1]; - - // fracPENotOne_uid62_fpSqrtTest(LOGICAL,61)@24 - assign fracPENotOne_uid62_fpSqrtTest_q = ~ (redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q); - - // fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest(LOGICAL,62)@24 - assign fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q = fracPENotOne_uid62_fpSqrtTest_q & expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_b; - - // expIncPEOnly_uid38_fpSqrtTest(BITSELECT,37)@16 - assign expIncPEOnly_uid38_fpSqrtTest_in = s2_uid111_invPolyEval_q[30:0]; - assign expIncPEOnly_uid38_fpSqrtTest_b = expIncPEOnly_uid38_fpSqrtTest_in[30:30]; - - // redist5_expIncPEOnly_uid38_fpSqrtTest_b_8(DELAY,130) - dspba_delay_ver #( .width(1), .depth(8), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist5_expIncPEOnly_uid38_fpSqrtTest_b_8 ( .xin(expIncPEOnly_uid38_fpSqrtTest_b), .xout(redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expInc_uid64_fpSqrtTest(LOGICAL,63)@24 + 1 - assign expInc_uid64_fpSqrtTest_qi = redist5_expIncPEOnly_uid38_fpSqrtTest_b_8_q | fracPENotOneAndCRRoundsExp_uid63_fpSqrtTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - expInc_uid64_fpSqrtTest_delay ( .xin(expInc_uid64_fpSqrtTest_qi), .xout(expInc_uid64_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) - assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; - - // expOddSig_uid27_fpSqrtTest(ADD,26)@23 - assign expOddSig_uid27_fpSqrtTest_a = {1'b0, redist14_expX_uid6_fpSqrtTest_b_23_mem_q}; - assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; - assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); - assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; - - // expROdd_uid28_fpSqrtTest(BITSELECT,27)@23 - assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; - - // sBias_uid22_fpSqrtTest(CONSTANT,21) - assign sBias_uid22_fpSqrtTest_q = 8'b01111111; - - // expEvenSig_uid24_fpSqrtTest(ADD,23)@23 - assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, redist14_expX_uid6_fpSqrtTest_b_23_mem_q}; - assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; - assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); - assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; - - // expREven_uid25_fpSqrtTest(BITSELECT,24)@23 - assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; - - // expRMux_uid31_fpSqrtTest(MUX,30)@23 + 1 - assign expRMux_uid31_fpSqrtTest_s = redist10_expOddSelect_uid30_fpSqrtTest_q_23_q; - always @ (posedge clk) - begin - if (areset) - begin - expRMux_uid31_fpSqrtTest_q <= 8'b0; - end - else if (en == 1'b1) - begin - unique case (expRMux_uid31_fpSqrtTest_s) - 1'b0 : expRMux_uid31_fpSqrtTest_q <= expREven_uid25_fpSqrtTest_b; - 1'b1 : expRMux_uid31_fpSqrtTest_q <= expROdd_uid28_fpSqrtTest_b; - default : expRMux_uid31_fpSqrtTest_q <= 8'b0; - endcase - end - end - - // redist9_expRMux_uid31_fpSqrtTest_q_2(DELAY,134) - always @ (posedge clk) - begin - if (areset) - begin - redist9_expRMux_uid31_fpSqrtTest_q_2_q <= '0; - end - else if (en == 1'b1) - begin - redist9_expRMux_uid31_fpSqrtTest_q_2_q <= expRMux_uid31_fpSqrtTest_q; - end - end - - // expR_uid66_fpSqrtTest(ADD,65)@25 - assign expR_uid66_fpSqrtTest_a = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_2_q}; - assign expR_uid66_fpSqrtTest_b = {8'b00000000, expInc_uid64_fpSqrtTest_q}; - assign expR_uid66_fpSqrtTest_o = $unsigned(expR_uid66_fpSqrtTest_a) + $unsigned(expR_uid66_fpSqrtTest_b); - assign expR_uid66_fpSqrtTest_q = expR_uid66_fpSqrtTest_o[8:0]; - - // expRR_uid77_fpSqrtTest(BITSELECT,76)@25 - assign expRR_uid77_fpSqrtTest_in = expR_uid66_fpSqrtTest_q[7:0]; - assign expRR_uid77_fpSqrtTest_b = expRR_uid77_fpSqrtTest_in[7:0]; - - // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@23 + 1 - assign expXIsMax_uid14_fpSqrtTest_qi = redist14_expX_uid6_fpSqrtTest_b_23_mem_q == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@24 - assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); - - // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@24 - assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); - - // excR_x_uid21_fpSqrtTest(LOGICAL,20)@24 - assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; - - // minReg_uid69_fpSqrtTest(LOGICAL,68)@24 - assign minReg_uid69_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist13_signX_uid7_fpSqrtTest_b_24_q; - - // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) - assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@23 + 1 - assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == redist12_frac_x_uid12_fpSqrtTest_b_23_mem_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid17_fpSqrtTest(LOGICAL,16)@24 - assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; - - // minInf_uid70_fpSqrtTest(LOGICAL,69)@24 - assign minInf_uid70_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist13_signX_uid7_fpSqrtTest_b_24_q; - - // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@24 - assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); - - // excN_x_uid18_fpSqrtTest(LOGICAL,17)@24 - assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; - - // excRNaN_uid71_fpSqrtTest(LOGICAL,70)@24 - assign excRNaN_uid71_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid70_fpSqrtTest_q | minReg_uid69_fpSqrtTest_q; - - // invSignX_uid67_fpSqrtTest(LOGICAL,66)@24 - assign invSignX_uid67_fpSqrtTest_q = ~ (redist13_signX_uid7_fpSqrtTest_b_24_q); - - // inInfAndNotNeg_uid68_fpSqrtTest(LOGICAL,67)@24 - assign inInfAndNotNeg_uid68_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid67_fpSqrtTest_q; - - // excConc_uid72_fpSqrtTest(BITJOIN,71)@24 - assign excConc_uid72_fpSqrtTest_q = {excRNaN_uid71_fpSqrtTest_q, inInfAndNotNeg_uid68_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; - - // fracSelIn_uid73_fpSqrtTest(BITJOIN,72)@24 - assign fracSelIn_uid73_fpSqrtTest_q = {redist13_signX_uid7_fpSqrtTest_b_24_q, excConc_uid72_fpSqrtTest_q}; - - // fracSel_uid74_fpSqrtTest(LOOKUP,73)@24 + 1 - always @ (posedge clk) - begin - if (areset) - begin - fracSel_uid74_fpSqrtTest_q <= 2'b01; - end - else if (en == 1'b1) - begin - unique case (fracSelIn_uid73_fpSqrtTest_q) - 4'b0000 : fracSel_uid74_fpSqrtTest_q <= 2'b01; - 4'b0001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b0010 : fracSel_uid74_fpSqrtTest_q <= 2'b10; - 4'b0011 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b0100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b0101 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b0110 : fracSel_uid74_fpSqrtTest_q <= 2'b10; - 4'b0111 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b1000 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1001 : fracSel_uid74_fpSqrtTest_q <= 2'b00; - 4'b1010 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1011 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1100 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1101 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1110 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - 4'b1111 : fracSel_uid74_fpSqrtTest_q <= 2'b11; - default : begin - // unreachable - fracSel_uid74_fpSqrtTest_q <= 2'bxx; - end - endcase - end - end - - // expRPostExc_uid79_fpSqrtTest(MUX,78)@25 - assign expRPostExc_uid79_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; - always @(expRPostExc_uid79_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid77_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) - begin - unique case (expRPostExc_uid79_fpSqrtTest_s) - 2'b00 : expRPostExc_uid79_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; - 2'b01 : expRPostExc_uid79_fpSqrtTest_q = expRR_uid77_fpSqrtTest_b; - 2'b10 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - 2'b11 : expRPostExc_uid79_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; - default : expRPostExc_uid79_fpSqrtTest_q = 8'b0; - endcase - end - - // fracNaN_uid80_fpSqrtTest(CONSTANT,79) - assign fracNaN_uid80_fpSqrtTest_q = 23'b00000000000000000000001; - - // redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1(DELAY,125) - always @ (posedge clk) - begin - if (areset) - begin - redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q <= '0; - end - else if (en == 1'b1) - begin - redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q <= expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c; - end - end - - // fracRPostExc_uid84_fpSqrtTest(MUX,83)@25 - assign fracRPostExc_uid84_fpSqrtTest_s = fracSel_uid74_fpSqrtTest_q; - always @(fracRPostExc_uid84_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q or fracNaN_uid80_fpSqrtTest_q) - begin - unique case (fracRPostExc_uid84_fpSqrtTest_s) - 2'b00 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b01 : fracRPostExc_uid84_fpSqrtTest_q = redist0_expUpdateCRU_uid61_fpSqrtTest_merged_bit_select_c_1_q; - 2'b10 : fracRPostExc_uid84_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; - 2'b11 : fracRPostExc_uid84_fpSqrtTest_q = fracNaN_uid80_fpSqrtTest_q; - default : fracRPostExc_uid84_fpSqrtTest_q = 23'b0; - endcase - end - - // RSqrt_uid86_fpSqrtTest(BITJOIN,85)@25 - assign RSqrt_uid86_fpSqrtTest_q = {negZero_uid85_fpSqrtTest_q, expRPostExc_uid79_fpSqrtTest_q, fracRPostExc_uid84_fpSqrtTest_q}; - - // xOut(GPOUT,4)@25 - assign q = RSqrt_uid86_fpSqrtTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex b/hw/rtl/fp_cores/altera/stratix10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex deleted file mode 100644 index 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not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fadd - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPAdd@ -@latency 3@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method single path@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fsub - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPSub@ -@latency 3@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method single path@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fmul - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPMul@ -@latency 3@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fmadd - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 4 cycle(s) -@@start -@name FPMultAdd@ -@latency 4@ -@LUT 0@ -@DSP 2@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method multadd@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@inPort 2 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=23 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fdiv - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 1232, DSPs 7, RAMBits 34304, RAMBlocks 3 -The pipeline depth of the block is 34 cycle(s) -@@start -@name FPDiv@ -@latency 34@ -@LUT 1232@ -@DSP 7@ -@RAMBits 34304@ -@RAMBlockUsage 3@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method polynomial approximation@ -@inPort 0 fpieee 8 23@ -@inPort 1 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=22 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_fsqrt - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 609, DSPs 5, RAMBits 15872, RAMBlocks 3 -The pipeline depth of the block is 25 cycle(s) -@@start -@name FPSqrt@ -@latency 25@ -@LUT 609@ -@DSP 5@ -@RAMBits 15872@ -@RAMBlockUsage 3@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method polynomial approximation@ -@inPort 0 fpieee 8 23@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_ftoi - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 344, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPToFXP@ -@latency 3@ -@LUT 344@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fpieee 8 23@ -@outPort 0 fxp 32 0 1@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_ftou - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 272, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 3 cycle(s) -@@start -@name FPToFXP@ -@latency 3@ -@LUT 272@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fpieee 8 23@ -@outPort 0 fxp 32 0 0@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_itof - Frequency 250MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 362, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 7 cycle(s) -@@start -@name FXPToFP@ -@latency 7@ -@LUT 362@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fxp 32 0 1@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end -starting execution ... -build model options ... -argc=25 -Generation context: - Will not generate valid and channel signals - HardFP is enabled enabling set to true - Correct rounding constraint detected - Will not generate valid and channel signals - The new component name is acl_utof - Frequency 300MHz - Deployment FPGA Stratix10 -Estimated resources LUTs 310, DSPs 0, RAMBits 0, RAMBlocks 0 -The pipeline depth of the block is 7 cycle(s) -@@start -@name FXPToFP@ -@latency 7@ -@LUT 310@ -@DSP 0@ -@RAMBits 0@ -@RAMBlockUsage 0@ -@enable 1@ -@subnormals 0@ -@error 0.50@ -@rounding RNE@ -@method default@ -@inPort 0 fxp 32 0 0@ -@outPort 0 fpieee 8 23@ -@nochanvalid 1@ -@@end diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh b/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh deleted file mode 100755 index 6bba5c3a..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh +++ /dev/null @@ -1,33 +0,0 @@ -#!/bin/bash - -FAMILY=Stratix10 -PREFIX=acl - -CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 - -OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2" - -export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH - -CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" - -EXP_BITS=8 -MAN_BITS=23 - -FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" - -echo Generating IP cores for $FBITS -{ - #$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 - $CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 - #$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 - #$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS - #$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS -} > acl_gen.log 2>&1 - -#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv b/hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv deleted file mode 100644 index 4548682b..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/dspba_delay_ver.sv +++ /dev/null @@ -1,98 +0,0 @@ -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing device programming or simulation files), and -// any associated documentation or information are expressly subject to the -// terms and conditions of the Intel FPGA Software License Agreement, -// Intel MegaCore Function License Agreement, or other applicable license -// agreement, including, without limitation, that your use is for the sole -// purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -module dspba_delay_ver -#( - parameter width = 8, - parameter depth = 1, - parameter reset_high = 1'b1, - parameter reset_kind = "ASYNC", - parameter phase = 0, - parameter modulus = 1 -) ( - input clk, - input aclr, - input ena, - input [width-1:0] xin, - output [width-1:0] xout -); - - wire reset; - reg [width-1:0] delays [depth-1:0]; - - assign reset = aclr ^ reset_high; - - generate - if (depth > 0) - begin - genvar i; - for (i = 0; i < depth; ++i) - begin : delay_block - if ((reset_kind == "ASYNC") && (0 == (phase + i) % modulus)) - begin : async_reset - always @ (posedge clk or negedge reset) - begin: a - if (!reset) begin - delays[i] <= 0; - end else begin - if (ena) begin - if (i > 0) begin - delays[i] <= delays[i - 1]; - end else begin - delays[i] <= xin; - end - end - end - end - end - - if ((reset_kind == "SYNC") && (0 == (phase + i) % modulus)) - begin : sync_reset - always @ (posedge clk) - begin: a - if (!reset) begin - delays[i] <= 0; - end else begin - if (ena) begin - if (i > 0) begin - delays[i] <= delays[i - 1]; - end else begin - delays[i] <= xin; - end - end - end - end - end - - if ((reset_kind == "NONE") || (0 != (phase + i) % modulus)) - begin : no_reset - always @ (posedge clk) - begin: a - if (ena) begin - if (i > 0) begin - delays[i] <= delays[i - 1]; - end else begin - delays[i] <= xin; - end - end - end - end - end - - assign xout = delays[depth - 1]; - end else begin - assign xout = xin; - end - endgenerate - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_class.sv b/hw/rtl/fpu/VX_fpu_class.sv similarity index 54% rename from hw/rtl/fp_cores/VX_fp_class.sv rename to hw/rtl/fpu/VX_fpu_class.sv index a98d51d5..df55b95b 100644 --- a/hw/rtl/fp_cores/VX_fp_class.sv +++ b/hw/rtl/fpu/VX_fpu_class.sv @@ -1,13 +1,28 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_fpu_define.vh" -module VX_fp_class # ( +`ifdef FPU_DSP + +module VX_fpu_class import VX_fpu_pkg::*; #( parameter MAN_BITS = 23, parameter EXP_BITS = 8 ) ( input [EXP_BITS-1:0] exp_i, input [MAN_BITS-1:0] man_i, - output fp_class_t clss_o + output fclass_t clss_o ); wire is_normal = (exp_i != '0) && (exp_i != '1); wire is_zero = (exp_i == '0) && (man_i == '0); @@ -25,4 +40,6 @@ module VX_fp_class # ( assign clss_o.is_quiet = is_quiet; assign clss_o.is_signaling = is_signaling; -endmodule \ No newline at end of file +endmodule +`endif + diff --git a/hw/rtl/fpu/VX_fpu_cvt.sv b/hw/rtl/fpu/VX_fpu_cvt.sv new file mode 100644 index 00000000..34b2ed28 --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_cvt.sv @@ -0,0 +1,464 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +/// Modified port of cast module from fpnew Libray +/// reference: https://github.com/pulp-platform/fpnew + +module VX_fpu_cvt import VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter TAGW = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FRM_BITS-1:0] frm, + + input wire is_itof, + input wire is_signed, + + input wire [NUM_LANES-1:0][31:0] dataa, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + // Constants + + localparam MAN_BITS = 23; + localparam EXP_BITS = 8; + localparam EXP_BIAS = 2**(EXP_BITS-1)-1; + + localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = 2**EXP_BITS-1; + localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1); + + // Use 32-bit integer + localparam MAX_INT_WIDTH = 32; + + // The internal mantissa includes normal bit or an entire integer + localparam INT_MAN_WIDTH = `MAX(MAN_BITS + 1, MAX_INT_WIDTH); + + // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection + localparam LZC_RESULT_WIDTH = `CLOG2(INT_MAN_WIDTH); + + // The internal exponent must be able to represent the smallest denormal input value as signed + // or the number of bits in an integer + localparam INT_EXP_WIDTH = `MAX(`CLOG2(MAX_INT_WIDTH), `MAX(EXP_BITS, `CLOG2(EXP_BIAS + MAN_BITS))) + 1; + + // shift amount for denormalization + localparam SHAMT_BITS = `CLOG2(INT_MAN_WIDTH+1); + + localparam FMT_SHIFT_COMPENSATION = INT_MAN_WIDTH - 1 - MAN_BITS; + localparam NUM_FP_STICKY = 2 * INT_MAN_WIDTH - MAN_BITS - 1; // removed mantissa, 1. and R + localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - MAX_INT_WIDTH; // removed int and R + + // Input processing + + fclass_t [NUM_LANES-1:0] fclass; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + VX_fpu_class #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class ( + .exp_i (dataa[i][30:23]), + .man_i (dataa[i][22:0]), + .clss_o (fclass[i]) + ); + end + + wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant; + wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp; + wire [NUM_LANES-1:0] input_sign; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [INT_MAN_WIDTH-1:0] int_mantissa; + wire [INT_MAN_WIDTH-1:0] fmt_mantissa; + wire fmt_sign = dataa[i][31]; + wire int_sign = dataa[i][31] && is_signed; + assign int_mantissa = int_sign ? (-dataa[i]) : dataa[i]; + assign fmt_mantissa = INT_MAN_WIDTH'({fclass[i].is_normal, dataa[i][MAN_BITS-1:0]}); + assign input_exp[i] = {1'b0, dataa[i][MAN_BITS +: EXP_BITS]} + INT_EXP_WIDTH'({1'b0, fclass[i].is_subnormal}); + assign input_mant[i] = is_itof ? int_mantissa : fmt_mantissa; + assign input_sign[i] = is_itof ? int_sign : fmt_sign; + end + + // Pipeline stage0 + + wire valid_in_s0; + wire [NUM_LANES-1:0] lane_mask_s0; + wire [TAGW-1:0] tag_in_s0; + wire is_itof_s0; + wire unsigned_s0; + wire [2:0] rnd_mode_s0; + fclass_t [NUM_LANES-1:0] fclass_s0; + wire [NUM_LANES-1:0] input_sign_s0; + wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0; + wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0; + + wire stall; + + VX_pipe_register #( + .DATAW (1 + NUM_LANES + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)), + .RESETW (1) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in, lane_mask, tag_in, is_itof, !is_signed, frm, fclass, input_sign, input_exp, input_mant}), + .data_out ({valid_in_s0, lane_mask_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fclass_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0}) + ); + + // Normalization + + wire [NUM_LANES-1:0][LZC_RESULT_WIDTH-1:0] renorm_shamt_s0; // renormalization shift amount + wire [NUM_LANES-1:0] mant_is_zero_s0; // for integer zeroes + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire mant_is_nonzero_s0; + VX_lzc #( + .N (INT_MAN_WIDTH) + ) lzc ( + .data_in (encoded_mant_s0[i]), + .data_out (renorm_shamt_s0[i]), + .valid_out (mant_is_nonzero_s0) + ); + assign mant_is_zero_s0[i] = ~mant_is_nonzero_s0; + end + + wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_n_s0; // normalized input mantissa + wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_n_s0; // unbiased true exponent + + for (genvar i = 0; i < NUM_LANES; ++i) begin + // Realign input mantissa, append zeroes if destination is wider + assign input_mant_n_s0[i] = encoded_mant_s0[i] << renorm_shamt_s0[i]; + + // Unbias exponent and compensate for shift + wire [INT_EXP_WIDTH-1:0] fp_input_exp_s0 = fmt_exponent_s0[i] + INT_EXP_WIDTH'(FMT_SHIFT_COMPENSATION - EXP_BIAS) - INT_EXP_WIDTH'({1'b0, renorm_shamt_s0[i]}); + wire [INT_EXP_WIDTH-1:0] int_input_exp_s0 = INT_EXP_WIDTH'(INT_MAN_WIDTH-1) - INT_EXP_WIDTH'({1'b0, renorm_shamt_s0[i]}); + assign input_exp_n_s0[i] = is_itof_s0 ? int_input_exp_s0 : fp_input_exp_s0; + end + + // Pipeline stage1 + + wire valid_in_s1; + wire [NUM_LANES-1:0] lane_mask_s1; + wire [TAGW-1:0] tag_in_s1; + wire is_itof_s1; + wire unsigned_s1; + wire [2:0] rnd_mode_s1; + fclass_t [NUM_LANES-1:0] fclass_s1; + wire [NUM_LANES-1:0] input_sign_s1; + wire [NUM_LANES-1:0] mant_is_zero_s1; + wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1; + wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1; + + VX_pipe_register #( + .DATAW (1 + NUM_LANES + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)), + .RESETW (1) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in_s0, lane_mask_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fclass_s0, input_sign_s0, mant_is_zero_s0, input_mant_n_s0, input_exp_n_s0}), + .data_out ({valid_in_s1, lane_mask_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fclass_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1}) + ); + + // Perform adjustments to mantissa and exponent + + wire [NUM_LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s1; + wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s1; + wire [NUM_LANES-1:0] of_before_round_s1; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + reg [2*INT_MAN_WIDTH:0] preshift_mant_s1; // mantissa before final shift + reg [SHAMT_BITS-1:0] denorm_shamt_s1; // shift amount for denormalization + reg [INT_EXP_WIDTH-1:0] final_exp_tmp_s1; // after eventual adjustments + reg of_before_round_tmp_s1; + + always @(*) begin + final_exp_tmp_s1 = input_exp_s1[i] + INT_EXP_WIDTH'(EXP_BIAS); // take exponent as is, only look at lower bits + preshift_mant_s1 = {input_mant_s1[i], 33'b0}; + denorm_shamt_s1 = '0; + of_before_round_tmp_s1 = 1'b0; + + if (is_itof_s1) begin + if ($signed(input_exp_s1[i]) >= INT_EXP_WIDTH'($signed(2**EXP_BITS-1-EXP_BIAS))) begin + // Overflow or infinities (for proper rounding) + final_exp_tmp_s1 = (2**EXP_BITS-2); // largest normal value + preshift_mant_s1 = ~0; // largest normal value and RS bits set + of_before_round_tmp_s1 = 1'b1; + end else if ($signed(input_exp_s1[i]) < INT_EXP_WIDTH'($signed(-MAN_BITS-EXP_BIAS))) begin + // Limit the shift to retain sticky bits + final_exp_tmp_s1 = '0; // denormal result + denorm_shamt_s1 = (2 + MAN_BITS); // to sticky + end else if ($signed(input_exp_s1[i]) < INT_EXP_WIDTH'($signed(1-EXP_BIAS))) begin + // Denormalize underflowing values + final_exp_tmp_s1 = '0; // denormal result + denorm_shamt_s1 = SHAMT_BITS'(1-EXP_BIAS) - SHAMT_BITS'(input_exp_s1[i]); // adjust right shifting + end + end else begin + if ($signed(input_exp_s1[i]) >= $signed(INT_EXP_WIDTH'(MAX_INT_WIDTH-1) + INT_EXP_WIDTH'(unsigned_s1))) begin + // overflow: when converting to unsigned the range is larger by one + of_before_round_tmp_s1 = 1'b1; + end else if ($signed(input_exp_s1[i]) < INT_EXP_WIDTH'($signed(-1))) begin + // underflow + denorm_shamt_s1 = MAX_INT_WIDTH+1; // all bits go to the sticky + end else begin + // By default right shift mantissa to be an integer + denorm_shamt_s1 = SHAMT_BITS'(MAX_INT_WIDTH-1) - SHAMT_BITS'(input_exp_s1[i]); + end + end + end + + assign destination_mant_s1[i] = preshift_mant_s1 >> denorm_shamt_s1; + assign final_exp_s1[i] = final_exp_tmp_s1; + assign of_before_round_s1[i] = of_before_round_tmp_s1; + end + + // Pipeline stage2 + + wire valid_in_s2; + wire [NUM_LANES-1:0] lane_mask_s2; + wire [TAGW-1:0] tag_in_s2; + wire is_itof_s2; + wire unsigned_s2; + wire [2:0] rnd_mode_s2; + fclass_t [NUM_LANES-1:0] fclass_s2; + wire [NUM_LANES-1:0] mant_is_zero_s2; + wire [NUM_LANES-1:0] input_sign_s2; + wire [NUM_LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s2; + wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s2; + wire [NUM_LANES-1:0] of_before_round_s2; + + VX_pipe_register #( + .DATAW (1 + NUM_LANES + TAGW + 1 + 1 + `INST_FRM_BITS + NUM_LANES * ($bits(fclass_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)), + .RESETW (1) + ) pipe_reg2 ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in_s1, lane_mask_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fclass_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}), + .data_out ({valid_in_s2, lane_mask_s2, tag_in_s2, is_itof_s2, unsigned_s2, rnd_mode_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2}) + ); + + wire [NUM_LANES-1:0] rounded_sign_s2; + wire [NUM_LANES-1:0][31:0] rounded_abs_s2; // absolute value of result after rounding + wire [NUM_LANES-1:0] int_round_has_sticky_s2; + wire [NUM_LANES-1:0] fp_round_has_sticky_s2; + + // Rouding and classification + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [MAN_BITS-1:0] final_mant_s2; // mantissa after adjustments + wire [MAX_INT_WIDTH-1:0] final_int_s2; // integer shifted in position + wire [1:0] round_sticky_bits_s2; + wire [31:0] fmt_pre_round_abs_s2; + wire [31:0] pre_round_abs_s2; + wire [1:0] int_round_sticky_bits_s2, fp_round_sticky_bits_s2; + + // Extract final mantissa and round bit, discard the normal bit (for FP) + assign {final_mant_s2, fp_round_sticky_bits_s2[1]} = destination_mant_s2[i][2*INT_MAN_WIDTH-1 : 2*INT_MAN_WIDTH-1 - (MAN_BITS+1) + 1]; + assign {final_int_s2, int_round_sticky_bits_s2[1]} = destination_mant_s2[i][2*INT_MAN_WIDTH : 2*INT_MAN_WIDTH - (MAX_INT_WIDTH+1) + 1]; + + // Collapse sticky bits + assign fp_round_sticky_bits_s2[0] = (| destination_mant_s2[i][NUM_FP_STICKY-1:0]); + assign int_round_sticky_bits_s2[0] = (| destination_mant_s2[i][NUM_INT_STICKY-1:0]); + assign fp_round_has_sticky_s2[i] = (| fp_round_sticky_bits_s2); + assign int_round_has_sticky_s2[i] = (| int_round_sticky_bits_s2); + + // select RS bits for destination operation + assign round_sticky_bits_s2 = is_itof_s2 ? fp_round_sticky_bits_s2 : int_round_sticky_bits_s2; + + // Pack exponent and mantissa into proper rounding form + assign fmt_pre_round_abs_s2 = {1'b0, final_exp_s2[i][EXP_BITS-1:0], final_mant_s2[MAN_BITS-1:0]}; + + // Select output with destination format and operation + assign pre_round_abs_s2 = is_itof_s2 ? fmt_pre_round_abs_s2 : final_int_s2; + + // Perform the rounding + VX_fpu_rounding #( + .DAT_WIDTH (32) + ) fp_rounding ( + .abs_value_i (pre_round_abs_s2), + .sign_i (input_sign_s2[i]), + .round_sticky_bits_i (round_sticky_bits_s2), + .rnd_mode_i (rnd_mode_s2), + .effective_subtraction_i (1'b0), + .abs_rounded_o (rounded_abs_s2[i]), + .sign_o (rounded_sign_s2[i]), + `UNUSED_PIN (exact_zero_o) + ); + end + + // Pipeline stage3 + + wire valid_in_s3; + wire [NUM_LANES-1:0] lane_mask_s3; + wire [TAGW-1:0] tag_in_s3; + wire is_itof_s3; + wire unsigned_s3; + fclass_t [NUM_LANES-1:0] fclass_s3; + wire [NUM_LANES-1:0] mant_is_zero_s3; + wire [NUM_LANES-1:0] input_sign_s3; + wire [NUM_LANES-1:0] rounded_sign_s3; + wire [NUM_LANES-1:0][31:0] rounded_abs_s3; + wire [NUM_LANES-1:0] of_before_round_s3; + wire [NUM_LANES-1:0] int_round_has_sticky_s3; + wire [NUM_LANES-1:0] fp_round_has_sticky_s3; + + VX_pipe_register #( + .DATAW (1 + NUM_LANES + TAGW + 1 + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + 32 + 1 + 1 + 1 + 1)), + .RESETW (1) + ) pipe_reg3 ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in_s2, lane_mask_s2, tag_in_s2, is_itof_s2, unsigned_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, rounded_abs_s2, rounded_sign_s2, of_before_round_s2, int_round_has_sticky_s2, fp_round_has_sticky_s2}), + .data_out ({valid_in_s3, lane_mask_s3, tag_in_s3, is_itof_s3, unsigned_s3, fclass_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3, int_round_has_sticky_s3, fp_round_has_sticky_s3}) + ); + + wire [NUM_LANES-1:0] of_after_round_s3; + wire [NUM_LANES-1:0] uf_after_round_s3; + wire [NUM_LANES-1:0][31:0] fmt_result_s3; + wire [NUM_LANES-1:0][31:0] rounded_int_res_s3; // after possible inversion + wire [NUM_LANES-1:0] rounded_int_res_zero_s3; // after rounding + + for (genvar i = 0; i < NUM_LANES; ++i) begin + // Assemble regular result, nan box short ones. Int zeroes need to be detected + assign fmt_result_s3[i] = (is_itof_s3 & mant_is_zero_s3[i]) ? 0 : {rounded_sign_s3[i], rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:0]}; + + // Classification after rounding select by destination format + assign uf_after_round_s3[i] = (rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == 0); // denormal + assign of_after_round_s3[i] = (rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == ~0); // inf exp. + + // Negative integer result needs to be brought into two's complement + assign rounded_int_res_s3[i] = rounded_sign_s3[i] ? (-rounded_abs_s3[i]) : rounded_abs_s3[i]; + assign rounded_int_res_zero_s3[i] = (rounded_int_res_s3[i] == 0); + end + + // FP Special case handling + + wire [NUM_LANES-1:0][31:0] fp_special_result_s3; + fflags_t [NUM_LANES-1:0] fp_special_status_s3; + wire [NUM_LANES-1:0] fp_result_is_special_s3; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + // Detect special case from source format, I2F casts don't produce a special result + assign fp_result_is_special_s3[i] = ~is_itof_s3 & (fclass_s3[i].is_zero | fclass_s3[i].is_nan); + + // Signalling input NaNs raise invalid flag, otherwise no flags set + assign fp_special_status_s3[i] = fclass_s3[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation + + // Assemble result according to destination format + assign fp_special_result_s3[i] = fclass_s3[i].is_zero ? (32'(input_sign_s3) << 31) // signed zero + : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN + end + + // INT Special case handling + + reg [NUM_LANES-1:0][31:0] int_special_result_s3; + fflags_t [NUM_LANES-1:0] int_special_status_s3; + wire [NUM_LANES-1:0] int_result_is_special_s3; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + // Assemble result according to destination format + always @(*) begin + if (input_sign_s3[i] && !fclass_s3[i].is_nan) begin + int_special_result_s3[i][30:0] = '0; // alone yields 2**(31)-1 + int_special_result_s3[i][31] = ~unsigned_s3; // for unsigned casts yields 2**31 + end else begin + int_special_result_s3[i][30:0] = 2**(31) - 1; // alone yields 2**(31)-1 + int_special_result_s3[i][31] = unsigned_s3; // for unsigned casts yields 2**31 + end + end + + // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned) + assign int_result_is_special_s3[i] = fclass_s3[i].is_nan + | fclass_s3[i].is_inf + | of_before_round_s3[i] + | (input_sign_s3[i] & unsigned_s3 & ~rounded_int_res_zero_s3[i]); + + // All integer special cases are invalid + assign int_special_status_s3[i] = {1'b1, 4'h0}; + end + + // Result selection and Output handshake + + fflags_t [NUM_LANES-1:0] tmp_fflags_s3; + wire [NUM_LANES-1:0][31:0] tmp_result_s3; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + fflags_t fp_regular_status_s3, int_regular_status_s3; + fflags_t fp_status_s3, int_status_s3; + wire [31:0] fp_result_s3, int_result_s3; + + wire inexact_s3 = is_itof_s3 ? fp_round_has_sticky_s3[i] // overflow is invalid in i2f; + : (fp_round_has_sticky_s3[i] || (~fclass_s3[i].is_inf && (of_before_round_s3[i] || of_after_round_s3[i]))); + + assign fp_regular_status_s3.NV = is_itof_s3 & (of_before_round_s3[i] | of_after_round_s3[i]); // overflow is invalid for I2F casts + assign fp_regular_status_s3.DZ = 1'b0; // no divisions + assign fp_regular_status_s3.OF = ~is_itof_s3 & (~fclass_s3[i].is_inf & (of_before_round_s3[i] | of_after_round_s3[i])); // inf casts no OF + assign fp_regular_status_s3.UF = uf_after_round_s3[i] & inexact_s3; + assign fp_regular_status_s3.NX = inexact_s3; + + assign int_regular_status_s3 = int_round_has_sticky_s3[i] ? {4'h0, 1'b1} : 5'h0; + + assign fp_result_s3 = fp_result_is_special_s3[i] ? fp_special_result_s3[i] : fmt_result_s3[i]; + assign int_result_s3 = int_result_is_special_s3[i] ? int_special_result_s3[i] : rounded_int_res_s3[i]; + + assign fp_status_s3 = fp_result_is_special_s3[i] ? fp_special_status_s3[i] : fp_regular_status_s3; + assign int_status_s3 = int_result_is_special_s3[i] ? int_special_status_s3[i] : int_regular_status_s3; + + // Select output depending on special case detection + assign tmp_result_s3[i] = is_itof_s3 ? fp_result_s3 : int_result_s3; + assign tmp_fflags_s3[i] = is_itof_s3 ? fp_status_s3 : int_status_s3; + end + + assign stall = ~ready_out && valid_out; + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, tmp_fflags_s3, lane_mask_s3, NUM_LANES); + + VX_pipe_register #( + .DATAW (1 + TAGW + (NUM_LANES * 32) + `FP_FLAGS_BITS), + .RESETW (1) + ) pipe_reg4 ( + .clk (clk), + .reset (reset), + .enable (!stall), + .data_in ({valid_in_s3, tag_in_s3, tmp_result_s3, fflags_merged}), + .data_out ({valid_out, tag_out, result, fflags}) + ); + + assign ready_in = ~stall; + + assign has_fflags = 1'b1; + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_define.vh b/hw/rtl/fpu/VX_fpu_define.vh new file mode 100644 index 00000000..a72914ef --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_define.vh @@ -0,0 +1,42 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_FPU_DEFINE_VH +`define VX_FPU_DEFINE_VH + +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +`define FPU_MERGE_FFLAGS(out, in, mask, lanes) \ + fflags_t __``out; \ + always @(*) begin \ + __``out = '0; \ + for (integer __i = 0; __i < lanes; ++__i) begin \ + if (mask[__i]) begin \ + __``out.NX |= in[__i].NX; \ + __``out.UF |= in[__i].UF; \ + __``out.OF |= in[__i].OF; \ + __``out.DZ |= in[__i].DZ; \ + __``out.NV |= in[__i].NV; \ + end \ + end \ + end \ + assign out = __``out + +`define FP_CLASS_BITS $bits(VX_fpu_pkg::fclass_t) +`define FP_FLAGS_BITS $bits(VX_fpu_pkg::fflags_t) + +`endif // VX_FPU_DEFINE_VH diff --git a/hw/rtl/fpu/VX_fpu_div.sv b/hw/rtl/fpu/VX_fpu_div.sv new file mode 100644 index 00000000..3a930715 --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_div.sv @@ -0,0 +1,137 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_div import VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter TAGW = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + `UNUSED_VAR (frm) + + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + wire [NUM_LANES-1:0] lane_mask_out; + + VX_shift_register #( + .DATAW (1 + NUM_LANES + TAGW), + .DEPTH (`LATENCY_FDIV), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({valid_in, lane_mask, tag_in}), + .data_out ({valid_out, lane_mask_out, tag_out}) + ); + + assign ready_in = enable; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_LANES; ++i) begin + acl_fdiv fdiv ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .q (result[i]) + ); + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + +`elsif VIVADO + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [3:0] tuser; + + xil_fdiv fdiv ( + .aclk (clk), + .aclken (enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (dataa[i]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (datab[i]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (result[i]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign per_lane_fflags[i] = {tuser[2], tuser[3], tuser[1], tuser[0], 1'b0}; + end + + assign has_fflags = 1; + +`else + + for (genvar i = 0; i < NUM_LANES; ++i) begin + reg [63:0] r; + `UNUSED_VAR (r) + + fflags_t f; + + always @(*) begin + dpi_fdiv (enable && valid_in, int'(0), {32'hffffffff, dataa[i]}, {32'hffffffff, datab[i]}, frm, r, f); + end + + VX_shift_register #( + .DATAW (32 + $bits(fflags_t)), + .DEPTH (`LATENCY_FDIV) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (enable), + .data_in ({r[31:0], f}), + .data_out ({result[i], per_lane_fflags[i]}) + ); + end + + assign has_fflags = 1; + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES); + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_dpi.sv b/hw/rtl/fpu/VX_fpu_dpi.sv new file mode 100644 index 00000000..4d8d110f --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_dpi.sv @@ -0,0 +1,490 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DPI + +module VX_fpu_dpi import VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter TAGW = 1, + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_FMT_BITS-1:0] fmt, + input wire [`INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][`XLEN-1:0] dataa, + input wire [NUM_LANES-1:0][`XLEN-1:0] datab, + input wire [NUM_LANES-1:0][`XLEN-1:0] datac, + output wire [NUM_LANES-1:0][`XLEN-1:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam FPU_FMA = 0; + localparam FPU_DIVSQRT = 1; + localparam FPU_CVT = 2; + localparam FPU_NCP = 3; + localparam NUM_FPC = 4; + localparam FPC_BITS = `LOG2UP(NUM_FPC); + + localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAGW; + + wire [NUM_FPC-1:0] per_core_ready_in; + wire [NUM_FPC-1:0][NUM_LANES-1:0][`XLEN-1:0] per_core_result; + wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out; + reg [NUM_FPC-1:0] per_core_ready_out; + wire [NUM_FPC-1:0] per_core_valid_out; + wire [NUM_FPC-1:0] per_core_has_fflags; + fflags_t [NUM_FPC-1:0] per_core_fflags; + + wire div_ready_in, sqrt_ready_in; + wire [NUM_LANES-1:0][`XLEN-1:0] div_result, sqrt_result; + wire [TAGW-1:0] div_tag_out, sqrt_tag_out; + wire div_ready_out, sqrt_ready_out; + wire div_valid_out, sqrt_valid_out; + wire div_has_fflags, sqrt_has_fflags; + fflags_t div_fflags, sqrt_fflags; + + reg [FPC_BITS-1:0] core_select; + + reg is_fadd, is_fsub, is_fmul, is_fmadd, is_fmsub, is_fnmadd, is_fnmsub; + reg is_div, is_fcmp, is_itof, is_utof, is_ftoi, is_ftou, is_f2f; + reg dst_fmt, int_fmt; + + reg [NUM_LANES-1:0][63:0] operands [3]; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + operands[0][i] = 64'(dataa[i]); + operands[1][i] = 64'(datab[i]); + operands[2][i] = 64'(datac[i]); + end + end + + `UNUSED_VAR (fmt) + + always @(*) begin + is_fadd = 0; + is_fsub = 0; + is_fmul = 0; + is_fmadd = 0; + is_fmsub = 0; + is_fnmadd = 0; + is_fnmsub = 0; + is_div = 0; + is_fcmp = 0; + is_itof = 0; + is_utof = 0; + is_ftoi = 0; + is_ftou = 0; + is_f2f = 0; + + dst_fmt = 0; + int_fmt = 0; + + `ifdef FLEN_64 + dst_fmt = fmt[0]; + `endif + + `ifdef XLEN_64 + int_fmt = fmt[1]; + `endif + + case (op_type) + `INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end + `INST_FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end + `INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end + `INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end + `INST_FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end + `INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end + `INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end + `INST_FPU_DIV: begin core_select = FPU_DIVSQRT; is_div = 1; end + `INST_FPU_SQRT: begin core_select = FPU_DIVSQRT; end + `INST_FPU_CMP: begin core_select = FPU_NCP; is_fcmp = 1; end + `INST_FPU_F2I: begin core_select = FPU_CVT; is_ftoi = 1; end + `INST_FPU_F2U: begin core_select = FPU_CVT; is_ftou = 1; end + `INST_FPU_I2F: begin core_select = FPU_CVT; is_itof = 1; end + `INST_FPU_U2F: begin core_select = FPU_CVT; is_utof = 1; end + `INST_FPU_F2F: begin core_select = FPU_CVT; is_f2f = 1; end + default: begin core_select = FPU_NCP; end + endcase + end + + generate + begin : fma + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fma; + wire [NUM_LANES-1:0][63:0] result_fadd; + wire [NUM_LANES-1:0][63:0] result_fsub; + wire [NUM_LANES-1:0][63:0] result_fmul; + wire [NUM_LANES-1:0][63:0] result_fmadd; + wire [NUM_LANES-1:0][63:0] result_fmsub; + wire [NUM_LANES-1:0][63:0] result_fnmadd; + wire [NUM_LANES-1:0][63:0] result_fnmsub; + + fflags_t [NUM_LANES-1:0] fflags_fma; + fflags_t [NUM_LANES-1:0] fflags_fadd; + fflags_t [NUM_LANES-1:0] fflags_fsub; + fflags_t [NUM_LANES-1:0] fflags_fmul; + fflags_t [NUM_LANES-1:0] fflags_fmadd; + fflags_t [NUM_LANES-1:0] fflags_fmsub; + fflags_t [NUM_LANES-1:0] fflags_fnmadd; + fflags_t [NUM_LANES-1:0] fflags_fnmsub; + + wire fma_valid = (valid_in && core_select == FPU_FMA); + wire fma_ready = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA]; + wire fma_fire = fma_valid && fma_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fadd[i], fflags_fadd[i]); + dpi_fsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fsub[i], fflags_fsub[i]); + dpi_fmul (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fmul[i], fflags_fmul[i]); + dpi_fmadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmadd[i], fflags_fmadd[i]); + dpi_fmsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmsub[i], fflags_fmsub[i]); + dpi_fnmadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmadd[i], fflags_fnmadd[i]); + dpi_fnmsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmsub[i], fflags_fnmsub[i]); + + result_fma[i] = is_fadd ? result_fadd[i][`XLEN-1:0] : + is_fsub ? result_fsub[i][`XLEN-1:0] : + is_fmul ? result_fmul[i][`XLEN-1:0] : + is_fmadd ? result_fmadd[i][`XLEN-1:0] : + is_fmsub ? result_fmsub[i][`XLEN-1:0] : + is_fnmadd ? result_fnmadd[i][`XLEN-1:0] : + is_fnmsub ? result_fnmsub[i][`XLEN-1:0] : + '0; + + fflags_fma[i] = is_fadd ? fflags_fadd[i] : + is_fsub ? fflags_fsub[i] : + is_fmul ? fflags_fmul[i] : + is_fmadd ? fflags_fmadd[i] : + is_fmsub ? fflags_fmsub[i] : + is_fnmadd ? fflags_fnmadd[i] : + is_fnmsub ? fflags_fnmsub[i] : + '0; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fma, lane_mask, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FMA), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fma_ready), + .data_in ({fma_valid, tag_in, result_fma, fflags_merged}), + .data_out ({per_core_valid_out[FPU_FMA], per_core_tag_out[FPU_FMA], per_core_result[FPU_FMA], per_core_fflags[FPU_FMA]}) + ); + + assign per_core_has_fflags[FPU_FMA] = 1; + assign per_core_ready_in[FPU_FMA] = fma_ready; + + end + endgenerate + + generate + begin : fdiv + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fdiv_r; + wire [NUM_LANES-1:0][63:0] result_fdiv; + fflags_t [NUM_LANES-1:0] fflags_fdiv; + + wire fdiv_valid = (valid_in && core_select == FPU_DIVSQRT) && is_div; + wire fdiv_ready = div_ready_out || ~div_valid_out; + wire fdiv_fire = fdiv_valid && fdiv_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fdiv (fdiv_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fdiv[i], fflags_fdiv[i]); + result_fdiv_r[i] = result_fdiv[i][`XLEN-1:0]; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fdiv, lane_mask, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FDIV), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fdiv_ready), + .data_in ({fdiv_valid, tag_in, result_fdiv_r, fflags_merged}), + .data_out ({div_valid_out, div_tag_out, div_result, div_fflags}) + ); + + assign div_has_fflags = 1; + assign div_ready_in = fdiv_ready; + + end + endgenerate + + generate + begin : fsqrt + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fsqrt_r; + wire [NUM_LANES-1:0][63:0] result_fsqrt; + fflags_t [NUM_LANES-1:0] fflags_fsqrt; + + wire fsqrt_valid = (valid_in && core_select == FPU_DIVSQRT) && ~is_div; + wire fsqrt_ready = sqrt_ready_out || ~sqrt_valid_out; + wire fsqrt_fire = fsqrt_valid && fsqrt_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fsqrt (fsqrt_fire, int'(dst_fmt), operands[0][i], frm, result_fsqrt[i], fflags_fsqrt[i]); + result_fsqrt_r[i] = result_fsqrt[i][`XLEN-1:0]; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fsqrt, lane_mask, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FSQRT), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fsqrt_ready), + .data_in ({fsqrt_valid, tag_in, result_fsqrt_r, fflags_merged}), + .data_out ({sqrt_valid_out, sqrt_tag_out, sqrt_result, sqrt_fflags}) + ); + + assign sqrt_has_fflags = 1; + assign sqrt_ready_in = fsqrt_ready; + + end + endgenerate + + generate + begin : fcvt + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fcvt; + wire [NUM_LANES-1:0][63:0] result_itof; + wire [NUM_LANES-1:0][63:0] result_utof; + wire [NUM_LANES-1:0][63:0] result_ftoi; + wire [NUM_LANES-1:0][63:0] result_ftou; + wire [NUM_LANES-1:0][63:0] result_f2f; + + fflags_t [NUM_LANES-1:0] fflags_fcvt; + fflags_t [NUM_LANES-1:0] fflags_itof; + fflags_t [NUM_LANES-1:0] fflags_utof; + fflags_t [NUM_LANES-1:0] fflags_ftoi; + fflags_t [NUM_LANES-1:0] fflags_ftou; + + wire fcvt_valid = (valid_in && core_select == FPU_CVT); + wire fcvt_ready = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT]; + wire fcvt_fire = fcvt_valid && fcvt_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_itof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_itof[i], fflags_itof[i]); + dpi_utof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_utof[i], fflags_utof[i]); + dpi_ftoi (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftoi[i], fflags_ftoi[i]); + dpi_ftou (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftou[i], fflags_ftou[i]); + dpi_f2f (fcvt_fire, int'(dst_fmt), operands[0][i], result_f2f[i]); + + result_fcvt[i] = is_itof ? result_itof[i][`XLEN-1:0] : + is_utof ? result_utof[i][`XLEN-1:0] : + is_ftoi ? result_ftoi[i][`XLEN-1:0] : + is_ftou ? result_ftou[i][`XLEN-1:0] : + is_f2f ? result_f2f[i][`XLEN-1:0] : + '0; + + fflags_fcvt[i] = is_itof ? fflags_itof[i] : + is_utof ? fflags_utof[i] : + is_ftoi ? fflags_ftoi[i] : + is_ftou ? fflags_ftou[i] : + '0; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fcvt, lane_mask, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FCVT), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fcvt_ready), + .data_in ({fcvt_valid, tag_in, result_fcvt, fflags_merged}), + .data_out ({per_core_valid_out[FPU_CVT], per_core_tag_out[FPU_CVT], per_core_result[FPU_CVT], per_core_fflags[FPU_CVT]}) + ); + + assign per_core_has_fflags[FPU_CVT] = 1; + assign per_core_ready_in[FPU_CVT] = fcvt_ready; + + end + endgenerate + + generate + begin : fncp + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fncp; + wire [NUM_LANES-1:0][63:0] result_fclss; + wire [NUM_LANES-1:0][63:0] result_flt; + wire [NUM_LANES-1:0][63:0] result_fle; + wire [NUM_LANES-1:0][63:0] result_feq; + wire [NUM_LANES-1:0][63:0] result_fmin; + wire [NUM_LANES-1:0][63:0] result_fmax; + wire [NUM_LANES-1:0][63:0] result_fsgnj; + wire [NUM_LANES-1:0][63:0] result_fsgnjn; + wire [NUM_LANES-1:0][63:0] result_fsgnjx; + reg [NUM_LANES-1:0][63:0] result_fmvx; + reg [NUM_LANES-1:0][63:0] result_fmvf; + + fflags_t [NUM_LANES-1:0] fflags_fncp; + fflags_t [NUM_LANES-1:0] fflags_flt; + fflags_t [NUM_LANES-1:0] fflags_fle; + fflags_t [NUM_LANES-1:0] fflags_feq; + fflags_t [NUM_LANES-1:0] fflags_fmin; + fflags_t [NUM_LANES-1:0] fflags_fmax; + + wire fncp_valid = (valid_in && core_select == FPU_NCP); + wire fncp_ready = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP]; + wire fncp_fire = fncp_valid && fncp_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fclss (fncp_fire, int'(dst_fmt), operands[0][i], result_fclss[i]); + dpi_fle (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fle[i], fflags_fle[i]); + dpi_flt (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_flt[i], fflags_flt[i]); + dpi_feq (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_feq[i], fflags_feq[i]); + dpi_fmin (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmin[i], fflags_fmin[i]); + dpi_fmax (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmax[i], fflags_fmax[i]); + dpi_fsgnj (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnj[i]); + dpi_fsgnjn (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjn[i]); + dpi_fsgnjx (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjx[i]); + result_fmvx[i] = dst_fmt ? operands[0][i] : 64'($signed(operands[0][i][31:0])); // sign-extension + result_fmvf[i] = dst_fmt ? operands[0][i] : (operands[0][i] | 64'hffffffff00000000); // nan-boxing + end + end + + always @(*) begin + result_fncp = 'x; + fflags_fncp = 'x; + for (integer i = 0; i < NUM_LANES; ++i) begin + case (frm) + 0: begin result_fncp[i] = is_fcmp ? result_fle[i][`XLEN-1:0] : result_fsgnj[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fle[i]; end + 1: begin result_fncp[i] = is_fcmp ? result_flt[i][`XLEN-1:0] : result_fsgnjn[i][`XLEN-1:0]; fflags_fncp[i] = fflags_flt[i]; end + 2: begin result_fncp[i] = is_fcmp ? result_feq[i][`XLEN-1:0] : result_fsgnjx[i][`XLEN-1:0]; fflags_fncp[i] = fflags_feq[i]; end + 3: begin result_fncp[i] = result_fclss[i][`XLEN-1:0]; end + 4: begin result_fncp[i] = result_fmvx[i][`XLEN-1:0]; end + 5: begin result_fncp[i] = result_fmvf[i][`XLEN-1:0]; end + 6: begin result_fncp[i] = result_fmin[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmin[i]; end + 7: begin result_fncp[i] = result_fmax[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmax[i]; end + endcase + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fncp, lane_mask, NUM_LANES); + + wire has_fflags_fncp = (frm >= 6) || is_fcmp; + + VX_shift_register #( + .DATAW (1 + TAGW + 1 + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FNCP), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fncp_ready), + .data_in ({fncp_valid, tag_in, has_fflags_fncp, result_fncp, fflags_merged}), + .data_out ({per_core_valid_out[FPU_NCP], per_core_tag_out[FPU_NCP], per_core_has_fflags[FPU_NCP], per_core_result[FPU_NCP], per_core_fflags[FPU_NCP]}) + ); + + assign per_core_ready_in[FPU_NCP] = fncp_ready; + + end + endgenerate + + /////////////////////////////////////////////////////////////////////////// + + assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in; + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (RSP_DATAW), + .ARBITER ("R"), + .OUT_REG (0) + ) div_sqrt_arb ( + .clk (clk), + .reset (reset), + .valid_in ({sqrt_valid_out, div_valid_out}), + .ready_in ({sqrt_ready_out, div_ready_out}), + .data_in ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out}, + {div_result, div_has_fflags, div_fflags, div_tag_out}}), + .data_out ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}), + .valid_out (per_core_valid_out[FPU_DIVSQRT]), + .ready_out (per_core_ready_out[FPU_DIVSQRT]), + `UNUSED_PIN (sel_out) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_FPC-1:0][RSP_DATAW-1:0] per_core_data_out; + + for (genvar i = 0; i < NUM_FPC; ++i) begin + assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]}; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_FPC), + .DATAW (RSP_DATAW), + .ARBITER ("R"), + .OUT_REG (OUT_REG) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_out), + .ready_in (per_core_ready_out), + .data_in (per_core_data_out), + .data_out ({result, has_fflags, fflags, tag_out}), + .valid_out (valid_out), + .ready_out (ready_out), + `UNUSED_PIN (sel_out) + ); + + assign ready_in = per_core_ready_in[core_select]; + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_dsp.sv b/hw/rtl/fpu/VX_fpu_dsp.sv new file mode 100644 index 00000000..cac648d3 --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_dsp.sv @@ -0,0 +1,325 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_dsp import VX_fpu_pkg::*; #( + parameter NUM_LANES = 4, + parameter TAGW = 4, + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_FMT_BITS-1:0] fmt, + input wire [`INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][`XLEN-1:0] dataa, + input wire [NUM_LANES-1:0][`XLEN-1:0] datab, + input wire [NUM_LANES-1:0][`XLEN-1:0] datac, + output wire [NUM_LANES-1:0][`XLEN-1:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam FPU_FMA = 0; + localparam FPU_DIVSQRT = 1; + localparam FPU_CVT = 2; + localparam FPU_NCP = 3; + localparam NUM_FPC = 4; + localparam FPC_BITS = `LOG2UP(NUM_FPC); + + localparam RSP_DATAW = (NUM_LANES * 32) + 1 + $bits(fflags_t) + TAGW; + + `UNUSED_VAR (fmt) + + wire [NUM_FPC-1:0] per_core_ready_in; + wire [NUM_FPC-1:0][NUM_LANES-1:0][31:0] per_core_result; + wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out; + wire [NUM_FPC-1:0] per_core_ready_out; + wire [NUM_FPC-1:0] per_core_valid_out; + wire [NUM_FPC-1:0] per_core_has_fflags; + fflags_t [NUM_FPC-1:0] per_core_fflags; + + wire div_ready_in, sqrt_ready_in; + wire [NUM_LANES-1:0][31:0] div_result, sqrt_result; + wire [TAGW-1:0] div_tag_out, sqrt_tag_out; + wire div_ready_out, sqrt_ready_out; + wire div_valid_out, sqrt_valid_out; + wire div_has_fflags, sqrt_has_fflags; + fflags_t div_fflags, sqrt_fflags; + + reg [FPC_BITS-1:0] core_select; + reg is_madd, is_sub, is_neg, is_div, is_itof, is_signed; + + always @(*) begin + is_madd = 0; + is_sub = 0; + is_neg = 0; + is_div = 0; + is_itof = 0; + is_signed = 0; + case (op_type) + `INST_FPU_ADD: begin core_select = FPU_FMA; end + `INST_FPU_SUB: begin core_select = FPU_FMA; is_sub = 1; end + `INST_FPU_MUL: begin core_select = FPU_FMA; is_neg = 1; end + `INST_FPU_MADD: begin core_select = FPU_FMA; is_madd = 1; end + `INST_FPU_MSUB: begin core_select = FPU_FMA; is_madd = 1; is_sub = 1; end + `INST_FPU_NMADD: begin core_select = FPU_FMA; is_madd = 1; is_neg = 1; end + `INST_FPU_NMSUB: begin core_select = FPU_FMA; is_madd = 1; is_sub = 1; is_neg = 1; end + `INST_FPU_DIV: begin core_select = FPU_DIVSQRT; is_div = 1; end + `INST_FPU_SQRT: begin core_select = FPU_DIVSQRT; end + `INST_FPU_F2I: begin core_select = FPU_CVT; is_signed = 1; end + `INST_FPU_F2U: begin core_select = FPU_CVT; end + `INST_FPU_I2F: begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end + `INST_FPU_U2F: begin core_select = FPU_CVT; is_itof = 1; end + default: begin core_select = FPU_NCP; end + endcase + end + + `RESET_RELAY (fma_reset, reset); + `RESET_RELAY (div_reset, reset); + `RESET_RELAY (sqrt_reset, reset); + `RESET_RELAY (cvt_reset, reset); + `RESET_RELAY (ncp_reset, reset); + + wire [NUM_LANES-1:0][31:0] dataa_s; + wire [NUM_LANES-1:0][31:0] datab_s; + wire [NUM_LANES-1:0][31:0] datac_s; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign dataa_s[i] = dataa[i][31:0]; + assign datab_s[i] = datab[i][31:0]; + assign datac_s[i] = datac[i][31:0]; + end + + `UNUSED_VAR (dataa) + `UNUSED_VAR (datab) + `UNUSED_VAR (datac) + + VX_fpu_fma #( + .NUM_LANES (NUM_LANES), + .TAGW (TAGW) + ) fpu_fma ( + .clk (clk), + .reset (fma_reset), + .valid_in (valid_in && (core_select == FPU_FMA)), + .ready_in (per_core_ready_in[FPU_FMA]), + .lane_mask (lane_mask), + .tag_in (tag_in), + .frm (frm), + .is_madd (is_madd), + .is_sub (is_sub), + .is_neg (is_neg), + .dataa (dataa_s), + .datab (datab_s), + .datac (datac_s), + .has_fflags (per_core_has_fflags[FPU_FMA]), + .fflags (per_core_fflags[FPU_FMA]), + .result (per_core_result[FPU_FMA]), + .tag_out (per_core_tag_out[FPU_FMA]), + .ready_out (per_core_ready_out[FPU_FMA]), + .valid_out (per_core_valid_out[FPU_FMA]) + ); + + VX_fpu_div #( + .NUM_LANES (NUM_LANES), + .TAGW (TAGW) + ) fpu_div ( + .clk (clk), + .reset (div_reset), + .valid_in (valid_in && (core_select == FPU_DIVSQRT) && is_div), + .ready_in (div_ready_in), + .lane_mask (lane_mask), + .tag_in (tag_in), + .frm (frm), + .dataa (dataa_s), + .datab (datab_s), + .has_fflags (div_has_fflags), + .fflags (div_fflags), + .result (div_result), + .tag_out (div_tag_out), + .valid_out (div_valid_out), + .ready_out (div_ready_out) + ); + + VX_fpu_sqrt #( + .NUM_LANES (NUM_LANES), + .TAGW (TAGW) + ) fpu_sqrt ( + .clk (clk), + .reset (sqrt_reset), + .valid_in (valid_in && (core_select == FPU_DIVSQRT) && ~is_div), + .ready_in (sqrt_ready_in), + .lane_mask (lane_mask), + .tag_in (tag_in), + .frm (frm), + .dataa (dataa_s), + .has_fflags (sqrt_has_fflags), + .fflags (sqrt_fflags), + .result (sqrt_result), + .tag_out (sqrt_tag_out), + .valid_out (sqrt_valid_out), + .ready_out (sqrt_ready_out) + ); + + wire cvt_rt_int_in = ~is_itof; + wire cvt_rt_int_out; + + VX_fpu_cvt #( + .NUM_LANES (NUM_LANES), + .TAGW (TAGW+1) + ) fpu_cvt ( + .clk (clk), + .reset (cvt_reset), + .valid_in (valid_in && (core_select == FPU_CVT)), + .ready_in (per_core_ready_in[FPU_CVT]), + .lane_mask (lane_mask), + .tag_in ({cvt_rt_int_in, tag_in}), + .frm (frm), + .is_itof (is_itof), + .is_signed (is_signed), + .dataa (dataa_s), + .has_fflags (per_core_has_fflags[FPU_CVT]), + .fflags (per_core_fflags[FPU_CVT]), + .result (per_core_result[FPU_CVT]), + .tag_out ({cvt_rt_int_out, per_core_tag_out[FPU_CVT]}), + .valid_out (per_core_valid_out[FPU_CVT]), + .ready_out (per_core_ready_out[FPU_CVT]) + ); + + wire ncp_rt_int_in = (op_type == `INST_FPU_CMP) + || `INST_FPU_IS_CLASS(op_type, frm) + || `INST_FPU_IS_MVXW(op_type, frm); + wire ncp_rt_int_out; + + wire ncp_rt_sext_in = `INST_FPU_IS_MVXW(op_type, frm); + wire ncp_rt_sext_out; + + VX_fpu_ncomp #( + .NUM_LANES (NUM_LANES), + .TAGW (TAGW+2) + ) fpu_ncomp ( + .clk (clk), + .reset (ncp_reset), + .valid_in (valid_in && (core_select == FPU_NCP)), + .ready_in (per_core_ready_in[FPU_NCP]), + .lane_mask (lane_mask), + .tag_in ({ncp_rt_sext_in, ncp_rt_int_in, tag_in}), + .op_type (op_type), + .frm (frm), + .dataa (dataa_s), + .datab (datab_s), + .result (per_core_result[FPU_NCP]), + .has_fflags (per_core_has_fflags[FPU_NCP]), + .fflags (per_core_fflags[FPU_NCP]), + .tag_out ({ncp_rt_sext_out, ncp_rt_int_out, per_core_tag_out[FPU_NCP]}), + .valid_out (per_core_valid_out[FPU_NCP]), + .ready_out (per_core_ready_out[FPU_NCP]) + ); + + /////////////////////////////////////////////////////////////////////////// + + assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in; + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (RSP_DATAW), + .ARBITER ("R"), + .OUT_REG (0) + ) div_sqrt_arb ( + .clk (clk), + .reset (reset), + .valid_in ({sqrt_valid_out, div_valid_out}), + .ready_in ({sqrt_ready_out, div_ready_out}), + .data_in ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out}, + {div_result, div_has_fflags, div_fflags, div_tag_out}}), + .data_out ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}), + .valid_out (per_core_valid_out[FPU_DIVSQRT]), + .ready_out (per_core_ready_out[FPU_DIVSQRT]), + `UNUSED_PIN (sel_out) + ); + + /////////////////////////////////////////////////////////////////////////// + + reg [NUM_FPC-1:0][RSP_DATAW+2-1:0] per_core_data_out; + + always @(*) begin + for (integer i = 0; i < NUM_FPC; ++i) begin + per_core_data_out[i][RSP_DATAW+1:2] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]}; + per_core_data_out[i][1:0] = '0; + end + per_core_data_out[FPU_CVT][1:0] = {1'b1, cvt_rt_int_out}; + per_core_data_out[FPU_NCP][1:0] = {ncp_rt_sext_out, ncp_rt_int_out}; + end + + wire [NUM_LANES-1:0][31:0] result_s; + wire [1:0] op_rt_int_out; + + VX_stream_arb #( + .NUM_INPUTS (NUM_FPC), + .DATAW (RSP_DATAW + 2), + .ARBITER ("R"), + .OUT_REG (OUT_REG) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_out), + .ready_in (per_core_ready_out), + .data_in (per_core_data_out), + .data_out ({result_s, has_fflags, fflags, tag_out, op_rt_int_out}), + .valid_out (valid_out), + .ready_out (ready_out), + `UNUSED_PIN (sel_out) + ); + +`ifndef FPU_RV64F + `UNUSED_VAR (op_rt_int_out) +`endif + + for (genvar i = 0; i < NUM_LANES; ++i) begin + `ifdef FPU_RV64F + reg [`XLEN-1:0] result_r; + always @(*) begin + case (op_rt_int_out) + 2'b11: result_r = `XLEN'($signed(result_s[i])); + 2'b01: result_r = {32'h00000000, result_s[i]}; + default: result_r = {32'hffffffff, result_s[i]}; + endcase + end + assign result[i] = result_r; + `else + assign result[i] = result_s[i]; + `endif + end + + // can accept new request? + assign ready_in = per_core_ready_in[core_select]; + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_fma.sv b/hw/rtl/fpu/VX_fpu_fma.sv new file mode 100644 index 00000000..5aff08ce --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_fma.sv @@ -0,0 +1,170 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_fma import VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter TAGW = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FRM_BITS-1:0] frm, + + input wire is_madd, + input wire is_sub, + input wire is_neg, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + input wire [NUM_LANES-1:0][31:0] datac, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + `UNUSED_VAR (frm) + + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + wire [NUM_LANES-1:0] lane_mask_out; + + VX_shift_register #( + .DATAW (1 + NUM_LANES + TAGW), + .DEPTH (`LATENCY_FMA), + .RESETW (1) + ) shift_reg ( + .clk(clk), + .reset (reset), + .enable (enable), + .data_in ({valid_in, lane_mask, tag_in}), + .data_out ({valid_out, lane_mask_out, tag_out}) + ); + + assign ready_in = enable; + + reg [NUM_LANES-1:0][31:0] a, b, c; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + if (is_madd) begin + // MADD / MSUB / NMADD / NMSUB + a[i] = is_neg ? {~dataa[i][31], dataa[i][30:0]} : dataa[i]; + b[i] = datab[i]; + c[i] = (is_neg ^ is_sub) ? {~datac[i][31], datac[i][30:0]} : datac[i]; + end else begin + if (is_neg) begin + // MUL + a[i] = dataa[i]; + b[i] = datab[i]; + c[i] = '0; + end else begin + // ADD / SUB + a[i] = 32'h3f800000; // 1.0f + b[i] = dataa[i]; + c[i] = is_sub ? {~datab[i][31], datab[i][30:0]} : datab[i]; + end + end + end + end + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_LANES; ++i) begin + acl_fmadd fmadd ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (a[i]), + .b (b[i]), + .c (c[i]), + .q (result[i]) + ); + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + +`elsif VIVADO + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [2:0] tuser; + + xil_fma fma ( + .aclk (clk), + .aclken (enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (a[i]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (b[i]), + .s_axis_c_tvalid (1'b1), + .s_axis_c_tdata (c[i]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (result[i]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign per_lane_fflags[i] = {tuser[2], 1'b0, tuser[1], tuser[0], 1'b0}; + end + + assign has_fflags = 1; + +`else + + for (genvar i = 0; i < NUM_LANES; ++i) begin + reg [63:0] r; + `UNUSED_VAR (r) + + fflags_t f; + + always @(*) begin + dpi_fmadd (enable && valid_in, int'(0), {32'hffffffff, a[i]}, {32'hffffffff, b[i]}, {32'hffffffff, c[i]}, frm, r, f); + end + + VX_shift_register #( + .DATAW (32 + $bits(fflags_t)), + .DEPTH (`LATENCY_FMA) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (enable), + .data_in ({r[31:0], f}), + .data_out ({result[i], per_lane_fflags[i]}) + ); + end + + assign has_fflags = 1; + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES); + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_fpnew.sv b/hw/rtl/fpu/VX_fpu_fpnew.sv new file mode 100644 index 00000000..447f120a --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_fpnew.sv @@ -0,0 +1,286 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_FPNEW + +module VX_fpu_fpnew + import VX_fpu_pkg::*; + import fpnew_pkg::*; + import cf_math_pkg::*; + import defs_div_sqrt_mvp::*; +#( + parameter NUM_LANES = 1, + parameter TAGW = 1, + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_FMT_BITS-1:0] fmt, + input wire [`INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][`XLEN-1:0] dataa, + input wire [NUM_LANES-1:0][`XLEN-1:0] datab, + input wire [NUM_LANES-1:0][`XLEN-1:0] datac, + output wire [NUM_LANES-1:0][`XLEN-1:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam LATENCY_FDIVSQRT = `MAX(`LATENCY_FDIV, `LATENCY_FSQRT); + localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAGW; + +`ifdef XLEN_64 + // use scalar configuration for mixed formats + localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ + Width: unsigned'(`XLEN), + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + `ifdef FLEN_64 + FpFmtMask: 5'b11000, + `else + FpFmtMask: 5'b11000, // TODO: added FP64 to fix CVT bug in FpNew + `endif + IntFmtMask: 4'b0011 + }; +`else + localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ + Width: unsigned'(`XLEN * NUM_LANES), + EnableVectors: 1'b1, + EnableNanBox: 1'b0, + FpFmtMask: 5'b10000, + IntFmtMask: 4'b0010 + }; +`endif + + localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ + PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL + '{default: unsigned'(LATENCY_FDIVSQRT)}, // DIVSQRT + '{default: `LATENCY_FNCP}, // NONCOMP + '{default: `LATENCY_FCVT}}, // CONV + UnitTypes:'{'{default: fpnew_pkg::PARALLEL}, // ADDMUL + '{default: fpnew_pkg::MERGED}, // DIVSQRT + '{default: fpnew_pkg::PARALLEL}, // NONCOMP + '{default: fpnew_pkg::MERGED}}, // CONV + PipeConfig: fpnew_pkg::DISTRIBUTED + }; + + wire fpu_ready_in, fpu_valid_in; + wire fpu_ready_out, fpu_valid_out; + + reg [TAGW-1:0] fpu_tag_in, fpu_tag_out; + + reg [2:0][NUM_LANES-1:0][`XLEN-1:0] fpu_operands; + + wire [NUM_LANES-1:0][`XLEN-1:0] fpu_result; + fpnew_pkg::status_t fpu_status; + + fpnew_pkg::operation_e fpu_op; + reg [`INST_FRM_BITS-1:0] fpu_rnd; + reg fpu_op_mod; + reg fpu_has_fflags, fpu_has_fflags_out; + fpnew_pkg::fp_format_e fpu_src_fmt, fpu_dst_fmt; + fpnew_pkg::int_format_e fpu_int_fmt; + + `UNUSED_VAR (fmt) + + always @(*) begin + fpu_op = 'x; + fpu_rnd = frm; + fpu_op_mod = 0; + fpu_has_fflags = 1; + fpu_operands[0] = dataa; + fpu_operands[1] = datab; + fpu_operands[2] = datac; + fpu_dst_fmt = fpnew_pkg::FP32; + fpu_int_fmt = fpnew_pkg::INT32; + + `ifdef FLEN_64 + if (fmt[0]) begin + fpu_dst_fmt = fpnew_pkg::FP64; + end + `endif + + `ifdef XLEN_64 + if (fmt[1]) begin + fpu_int_fmt = fpnew_pkg::INT64; + end + `endif + + fpu_src_fmt = fpu_dst_fmt; + + case (op_type) + `INST_FPU_ADD: begin + fpu_op = fpnew_pkg::ADD; + fpu_operands[1] = dataa; + fpu_operands[2] = datab; + end + `INST_FPU_SUB: begin + fpu_op = fpnew_pkg::ADD; + fpu_operands[1] = dataa; + fpu_operands[2] = datab; + fpu_op_mod = 1; + end + `INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end + `INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end + `INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end + `INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end + `INST_FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end + `INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end + `INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end + `ifdef FLEN_64 + `INST_FPU_F2F: begin fpu_op = fpnew_pkg::F2F; fpu_src_fmt = fmt[0] ? fpnew_pkg::FP32 : fpnew_pkg::FP64; end + `endif + `INST_FPU_F2I, + `INST_FPU_F2U: begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = op_type[0]; end + `INST_FPU_I2F, + `INST_FPU_U2F: begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = op_type[0]; end + `INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end + `INST_FPU_MISC:begin + case (frm) + 0,1,2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = {1'b0, frm[1:0]}; fpu_has_fflags = 0; end // FSGNJ + 3: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end // CLASS + 4,5: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = 3'b011; fpu_op_mod = ~frm[0]; fpu_has_fflags = 0; end // FMV.X.W, FMV.W.X + 6,7: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = {2'b00, frm[0]}; end // MIN, MAX + endcase + end + default:; + endcase + + `ifdef FPU_RV64F + // apply nan-boxing to floating-point operands + for (integer i = 0; i < NUM_LANES; ++i) begin + if (op_type != `INST_FPU_I2F && op_type != `INST_FPU_U2F) begin + fpu_operands[0][i] |= 64'hffffffff00000000; + end + fpu_operands[1][i] |= 64'hffffffff00000000; + fpu_operands[2][i] |= 64'hffffffff00000000; + end + `endif + end + +`ifdef XLEN_64 + `UNUSED_VAR (lane_mask) + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire [(TAGW+1)-1:0] fpu_tag; + wire fpu_valid_out_uq; + wire fpu_ready_in_uq; + fpnew_pkg::status_t fpu_status_uq; + `UNUSED_VAR (fpu_tag) + `UNUSED_VAR (fpu_valid_out_uq) + `UNUSED_VAR (fpu_ready_in_uq) + `UNUSED_VAR (fpu_status_uq) + + fpnew_top #( + .Features (FPU_FEATURES), + .Implementation (FPU_IMPLEMENTATION), + .TagType (logic[(TAGW+1)-1:0]) + ) fpnew_core ( + .clk_i (clk), + .rst_ni (~reset), + .operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}), + .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)), + .op_i (fpu_op), + .op_mod_i (fpu_op_mod), + .src_fmt_i (fpu_src_fmt), + .dst_fmt_i (fpu_dst_fmt), + .int_fmt_i (fpu_int_fmt), + `UNUSED_PIN (vectorial_op_i), + `UNUSED_PIN (simd_mask_i), + .tag_i ({fpu_tag_in, fpu_has_fflags}), + .in_valid_i (fpu_valid_in), + .in_ready_o (fpu_ready_in_uq), + .flush_i (reset), + .result_o (fpu_result[i]), + .status_o (fpu_status_uq), + .tag_o (fpu_tag), + .out_valid_o (fpu_valid_out_uq), + .out_ready_i (fpu_ready_out), + `UNUSED_PIN (busy_o) + ); + + if (i == 0) begin + assign {fpu_tag_out, fpu_has_fflags_out} = fpu_tag; + assign fpu_valid_out = fpu_valid_out_uq; + assign fpu_ready_in = fpu_ready_in_uq; + assign fpu_status = fpu_status_uq; + end + end +`else + fpnew_top #( + .Features (FPU_FEATURES), + .Implementation (FPU_IMPLEMENTATION), + .TagType (logic[(TAGW+1)-1:0]), + .TrueSIMDClass (1), + .EnableSIMDMask (1) + ) fpnew_core ( + .clk_i (clk), + .rst_ni (~reset), + .operands_i (fpu_operands), + .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)), + .op_i (fpu_op), + .op_mod_i (fpu_op_mod), + .src_fmt_i (fpu_src_fmt), + .dst_fmt_i (fpu_dst_fmt), + .int_fmt_i (fpu_int_fmt), + .vectorial_op_i (1'b1), + .simd_mask_i (lane_mask), + .tag_i ({fpu_tag_in, fpu_has_fflags}), + .in_valid_i (fpu_valid_in), + .in_ready_o (fpu_ready_in), + .flush_i (reset), + .result_o (fpu_result), + .status_o (fpu_status), + .tag_o ({fpu_tag_out, fpu_has_fflags_out}), + .out_valid_o (fpu_valid_out), + .out_ready_i (fpu_ready_out), + `UNUSED_PIN (busy_o) + ); +`endif + + assign fpu_valid_in = valid_in; + assign ready_in = fpu_ready_in; + assign fpu_tag_in = tag_in; + + VX_elastic_buffer #( + .DATAW (RSP_DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (fpu_valid_out), + .ready_in (fpu_ready_out), + .data_in ({fpu_result, fpu_has_fflags_out, fpu_status, fpu_tag_out}), + .data_out ({result, has_fflags, fflags, tag_out}), + .valid_out (valid_out), + .ready_out (ready_out) + ); + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_ncomp.sv b/hw/rtl/fpu/VX_fpu_ncomp.sv new file mode 100644 index 00000000..7d99502e --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_ncomp.sv @@ -0,0 +1,292 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +/// Modified port of noncomp module from fpnew Libray +/// reference: https://github.com/pulp-platform/fpnew + +module VX_fpu_ncomp import VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter TAGW = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FPU_BITS-1:0] op_type, + input wire [`INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam EXP_BITS = 8; + localparam MAN_BITS = 23; + + localparam NEG_INF = 32'h00000001, + NEG_NORM = 32'h00000002, + NEG_SUBNORM = 32'h00000004, + NEG_ZERO = 32'h00000008, + POS_ZERO = 32'h00000010, + POS_SUBNORM = 32'h00000020, + POS_NORM = 32'h00000040, + POS_INF = 32'h00000080, + //SIG_NAN = 32'h00000100, + QUT_NAN = 32'h00000200; + + wire [NUM_LANES-1:0] a_sign, b_sign; + wire [NUM_LANES-1:0][7:0] a_exponent, b_exponent; + wire [NUM_LANES-1:0][22:0] a_mantissa, b_mantissa; + fclass_t [NUM_LANES-1:0] a_fclass, b_fclass; + wire [NUM_LANES-1:0] a_smaller, ab_equal; + + // Setup + for (genvar i = 0; i < NUM_LANES; ++i) begin + assign a_sign[i] = dataa[i][31]; + assign a_exponent[i] = dataa[i][30:23]; + assign a_mantissa[i] = dataa[i][22:0]; + + assign b_sign[i] = datab[i][31]; + assign b_exponent[i] = datab[i][30:23]; + assign b_mantissa[i] = datab[i][22:0]; + + VX_fpu_class #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class_a ( + .exp_i (a_exponent[i]), + .man_i (a_mantissa[i]), + .clss_o (a_fclass[i]) + ); + + VX_fpu_class #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class_b ( + .exp_i (b_exponent[i]), + .man_i (b_mantissa[i]), + .clss_o (b_fclass[i]) + ); + + assign a_smaller[i] = (dataa[i] < datab[i]) ^ (a_sign[i] || b_sign[i]); + assign ab_equal[i] = (dataa[i] == datab[i]) + || (a_fclass[i].is_zero && b_fclass[i].is_zero); // +0 == -0 + end + + // Pipeline stage0 + + wire valid_in_s0; + wire [NUM_LANES-1:0] lane_mask_s0; + wire [TAGW-1:0] tag_in_s0; + wire [3:0] op_mod_s0; + wire [NUM_LANES-1:0][31:0] dataa_s0, datab_s0; + wire [NUM_LANES-1:0] a_sign_s0, b_sign_s0; + wire [NUM_LANES-1:0][7:0] a_exponent_s0; + wire [NUM_LANES-1:0][22:0] a_mantissa_s0; + fclass_t [NUM_LANES-1:0] a_fclass_s0, b_fclass_s0; + wire [NUM_LANES-1:0] a_smaller_s0, ab_equal_s0; + + wire stall; + + wire [3:0] op_mod = {(op_type == `INST_FPU_CMP), frm}; + + VX_pipe_register #( + .DATAW (1 + NUM_LANES + TAGW + 4 + NUM_LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fclass_t) + 1 + 1)), + .RESETW (1) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (!stall), + .data_in ({valid_in, lane_mask, tag_in, op_mod, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_fclass, b_fclass, a_smaller, ab_equal}), + .data_out ({valid_in_s0, lane_mask_s0, tag_in_s0, op_mod_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_fclass_s0, b_fclass_s0, a_smaller_s0, ab_equal_s0}) + ); + + // FCLASS + reg [NUM_LANES-1:0][31:0] fclass_mask_s0; // generate a 10-bit mask for integer reg + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + if (a_fclass_s0[i].is_normal) begin + fclass_mask_s0[i] = a_sign_s0[i] ? NEG_NORM : POS_NORM; + end + else if (a_fclass_s0[i].is_inf) begin + fclass_mask_s0[i] = a_sign_s0[i] ? NEG_INF : POS_INF; + end + else if (a_fclass_s0[i].is_zero) begin + fclass_mask_s0[i] = a_sign_s0[i] ? NEG_ZERO : POS_ZERO; + end + else if (a_fclass_s0[i].is_subnormal) begin + fclass_mask_s0[i] = a_sign_s0[i] ? NEG_SUBNORM : POS_SUBNORM; + end + else if (a_fclass_s0[i].is_nan) begin + fclass_mask_s0[i] = {22'h0, a_fclass_s0[i].is_quiet, a_fclass_s0[i].is_signaling, 8'h0}; + end + else begin + fclass_mask_s0[i] = QUT_NAN; + end + end + end + + // Min/Max + reg [NUM_LANES-1:0][31:0] fminmax_res_s0; + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + if (a_fclass_s0[i].is_nan && b_fclass_s0[i].is_nan) + fminmax_res_s0[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN + else if (a_fclass_s0[i].is_nan) + fminmax_res_s0[i] = datab_s0[i]; + else if (b_fclass_s0[i].is_nan) + fminmax_res_s0[i] = dataa_s0[i]; + else begin + // FMIN, FMAX + fminmax_res_s0[i] = (op_mod_s0[0] ^ a_smaller_s0[i]) ? dataa_s0[i] : datab_s0[i]; + end + end + end + + // Sign injection + reg [NUM_LANES-1:0][31:0] fsgnj_res_s0; // result of sign injection + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + case (op_mod_s0[1:0]) + 0: fsgnj_res_s0[i] = { b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]}; + 1: fsgnj_res_s0[i] = {~b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]}; + default: fsgnj_res_s0[i] = { a_sign_s0[i] ^ b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]}; + endcase + end + end + + // Comparison + reg [NUM_LANES-1:0] fcmp_res_s0; // result of comparison + reg [NUM_LANES-1:0] fcmp_fflags_NV_s0; // comparison fflags + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + case (op_mod_s0[1:0]) + 0: begin // LE + if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin + fcmp_res_s0[i] = 0; + fcmp_fflags_NV_s0[i] = 1; + end else begin + fcmp_res_s0[i] = (a_smaller_s0[i] | ab_equal_s0[i]); + fcmp_fflags_NV_s0[i] = 0; + end + end + 1: begin // LT + if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin + fcmp_res_s0[i] = 0; + fcmp_fflags_NV_s0[i] = 1; + end else begin + fcmp_res_s0[i] = (a_smaller_s0[i] & ~ab_equal_s0[i]); + fcmp_fflags_NV_s0[i] = 0; + end + end + 2: begin // EQ + if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin + fcmp_res_s0[i] = 0; + fcmp_fflags_NV_s0[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling; + end else begin + fcmp_res_s0[i] = ab_equal_s0[i]; + fcmp_fflags_NV_s0[i] = 0; + end + end + default: begin + fcmp_res_s0[i] = 'x; + fcmp_fflags_NV_s0[i] = 'x; + end + endcase + end + end + + // outputs + + reg [NUM_LANES-1:0][31:0] result_s0; + reg [NUM_LANES-1:0] fflags_NV_s0; + + for (genvar i = 0; i < NUM_LANES; ++i) begin + always @(*) begin + case (op_mod_s0[2:0]) + 0,1,2: begin + // SGNJ, CMP + result_s0[i] = op_mod_s0[3] ? 32'(fcmp_res_s0[i]) : fsgnj_res_s0[i]; + fflags_NV_s0[i] = fcmp_fflags_NV_s0[i]; + end + 3: begin + // CLASS + result_s0[i] = fclass_mask_s0[i]; + fflags_NV_s0[i] = 'x; + end + 4,5: begin + // FMV + result_s0[i] = dataa_s0[i]; + fflags_NV_s0[i] = 'x; + end + 6,7: begin + // MIN/MAX + result_s0[i] = fminmax_res_s0[i]; + fflags_NV_s0[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling; + end + endcase + end + end + + // only MIN/MAX and CMP return status flags + wire has_fflags_s0 = (op_mod_s0[2:0] >= 6) || op_mod_s0[3]; + + assign stall = ~ready_out && valid_out; + + wire fflags_NV; + reg fflags_merged; + + always @(*) begin + fflags_merged = 0; + for (integer i = 0; i < NUM_LANES; ++i) begin + if (lane_mask_s0[i]) begin + fflags_merged |= fflags_NV_s0[i]; + end + end + end + + VX_pipe_register #( + .DATAW (1 + TAGW + (NUM_LANES * 32) + 1 + 1), + .RESETW (1) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (!stall), + .data_in ({valid_in_s0, tag_in_s0, result_s0, has_fflags_s0, fflags_merged}), + .data_out ({valid_out, tag_out, result, has_fflags, fflags_NV}) + ); + + assign ready_in = ~stall; + + // NV, DZ, OF, UF, NX + assign fflags = {fflags_NV, 1'b0, 1'b0, 1'b0, 1'b0}; + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_pkg.sv b/hw/rtl/fpu/VX_fpu_pkg.sv new file mode 100644 index 00000000..9fa9ea5b --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_pkg.sv @@ -0,0 +1,41 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_FPU_PKG_VH +`define VX_FPU_PKG_VH + +`include "VX_define.vh" + +package VX_fpu_pkg; + +typedef struct packed { + logic is_normal; + logic is_zero; + logic is_subnormal; + logic is_inf; + logic is_nan; + logic is_quiet; + logic is_signaling; +} fclass_t; + +typedef struct packed { + logic NV; // 4-Invalid + logic DZ; // 3-Divide by zero + logic OF; // 2-Overflow + logic UF; // 1-Underflow + logic NX; // 0-Inexact +} fflags_t; + +endpackage + +`endif // VX_FPU_PKG_VH diff --git a/hw/rtl/fp_cores/VX_fp_rounding.sv b/hw/rtl/fpu/VX_fpu_rounding.sv similarity index 75% rename from hw/rtl/fp_cores/VX_fp_rounding.sv rename to hw/rtl/fpu/VX_fpu_rounding.sv index 415dd29d..5168fada 100644 --- a/hw/rtl/fp_cores/VX_fp_rounding.sv +++ b/hw/rtl/fpu/VX_fpu_rounding.sv @@ -1,20 +1,35 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_fpu_define.vh" +`ifdef FPU_DSP + /// Modified port of rouding module from fpnew Libray /// reference: https://github.com/pulp-platform/fpnew -module VX_fp_rounding #( +module VX_fpu_rounding #( parameter DAT_WIDTH = 2 // Width of the abolute value, without sign bit ) ( // inputs - input wire [DAT_WIDTH-1:0] abs_value_i, // absolute value without sign + input wire [DAT_WIDTH-1:0] abs_value_i, // absolute value without sign input wire sign_i, // rounding information - input wire [1:0] round_sticky_bits_i, // round and sticky bits {RS} + input wire [1:0] round_sticky_bits_i, // round and sticky bits {RS} input wire [2:0] rnd_mode_i, input wire effective_subtraction_i, // sign of inputs affects rounding of zeroes // outputs - output wire [DAT_WIDTH-1:0] abs_rounded_o, // absolute value without sign + output wire [DAT_WIDTH-1:0] abs_rounded_o, // absolute value without sign output wire sign_o, output wire exact_zero_o // output is an exact zero ); @@ -60,4 +75,5 @@ module VX_fp_rounding #( assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `INST_FRM_RDN) : sign_i; -endmodule \ No newline at end of file +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_sqrt.sv b/hw/rtl/fpu/VX_fpu_sqrt.sv new file mode 100644 index 00000000..f69c594e --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_sqrt.sv @@ -0,0 +1,134 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_sqrt import VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter TAGW = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] lane_mask, + + input wire [TAGW-1:0] tag_in, + + input wire [`INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + + `UNUSED_VAR (frm) + + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + wire [NUM_LANES-1:0] lane_mask_out; + + VX_shift_register #( + .DATAW (1 + NUM_LANES + TAGW), + .DEPTH (`LATENCY_FSQRT), + .RESETW (1) + ) shift_reg ( + .clk(clk), + .reset (reset), + .enable (enable), + .data_in ({valid_in, lane_mask, tag_in}), + .data_out ({valid_out, lane_mask_out, tag_out}) + ); + + assign ready_in = enable; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_LANES; ++i) begin + acl_fsqrt fsqrt ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result[i]) + ); + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + +`elsif VIVADO + + for (genvar i = 0; i < NUM_LANES; ++i) begin + wire tuser; + + xil_fsqrt fsqrt ( + .aclk (clk), + .aclken (enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (dataa[i][31:0]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (result[i][31:0]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign per_lane_fflags[i] = {tuser, 1'b0, 1'b0, 1'b0, 1'b0}; + end + + assign has_fflags = 1; + +`else + + for (genvar i = 0; i < NUM_LANES; ++i) begin + reg [63:0] r; + `UNUSED_VAR (r) + + fflags_t f; + + always @(*) begin + dpi_fsqrt (enable && valid_in, int'(0), {32'hffffffff, dataa[i]}, frm, r, f); + end + + VX_shift_register #( + .DATAW (32 + $bits(fflags_t)), + .DEPTH (`LATENCY_FSQRT) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (enable), + .data_in ({r[31:0], f}), + .data_out ({result[i], per_lane_fflags[i]}) + ); + end + + assign has_fflags = 1; + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES); + +endmodule +`endif diff --git a/hw/rtl/fpu/VX_fpu_to_csr_if.sv b/hw/rtl/fpu/VX_fpu_to_csr_if.sv new file mode 100644 index 00000000..879cbb73 --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_to_csr_if.sv @@ -0,0 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +interface VX_fpu_to_csr_if import VX_fpu_pkg::*; (); + + wire write_enable; + wire [`NW_WIDTH-1:0] write_wid; + fflags_t write_fflags; + + wire [`NW_WIDTH-1:0] read_wid; + wire [`INST_FRM_BITS-1:0] read_frm; + + modport master ( + output write_enable, + output write_wid, + output write_fflags, + + output read_wid, + input read_frm + ); + + modport slave ( + input write_enable, + input write_wid, + input write_fflags, + + input read_wid, + output read_frm + ); + +endinterface diff --git a/hw/rtl/fpu/VX_fpu_unit.sv b/hw/rtl/fpu/VX_fpu_unit.sv new file mode 100644 index 00000000..1aecd3e8 --- /dev/null +++ b/hw/rtl/fpu/VX_fpu_unit.sv @@ -0,0 +1,259 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" +`include "VX_fpu_define.vh" + +module VX_fpu_unit import VX_fpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + VX_fpu_to_csr_if.master fpu_to_csr_if[`NUM_FPU_BLOCKS], + + VX_commit_if.master commit_if [`ISSUE_WIDTH] +); + `UNUSED_PARAM (CORE_ID) + localparam BLOCK_SIZE = `NUM_FPU_BLOCKS; + localparam NUM_LANES = `NUM_FPU_LANES; + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam TAG_WIDTH = `LOG2UP(`FPU_REQ_QUEUE_SIZE); + localparam PARTIAL_BW = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `NUM_THREADS); + + VX_execute_if #( + .NUM_LANES (NUM_LANES) + ) execute_if[BLOCK_SIZE](); + + `RESET_RELAY (dispatch_reset, reset); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (PARTIAL_BW ? 1 : 0) + ) dispatch_unit ( + .clk (clk), + .reset (dispatch_reset), + .dispatch_if(dispatch_if), + .execute_if (execute_if) + ); + + VX_commit_if #( + .NUM_LANES (NUM_LANES) + ) commit_block_if[BLOCK_SIZE](); + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin + `UNUSED_VAR (execute_if[block_idx].data.tid) + `UNUSED_VAR (execute_if[block_idx].data.wb) + `UNUSED_VAR (execute_if[block_idx].data.use_PC) + `UNUSED_VAR (execute_if[block_idx].data.use_imm) + + // Store request info + wire fpu_req_valid, fpu_req_ready; + wire fpu_rsp_valid, fpu_rsp_ready; + wire [NUM_LANES-1:0][`XLEN-1:0] fpu_rsp_result; + fflags_t fpu_rsp_fflags; + wire fpu_rsp_has_fflags; + + wire [`UUID_WIDTH-1:0] fpu_rsp_uuid; + wire [`NW_WIDTH-1:0] fpu_rsp_wid; + wire [NUM_LANES-1:0] fpu_rsp_tmask; + wire [`XLEN-1:0] fpu_rsp_PC; + wire [`NR_BITS-1:0] fpu_rsp_rd; + wire [PID_WIDTH-1:0] fpu_rsp_pid; + wire fpu_rsp_sop; + wire fpu_rsp_eop; + + wire [TAG_WIDTH-1:0] fpu_req_tag, fpu_rsp_tag; + wire mdata_full; + + wire [`INST_FMT_BITS-1:0] fpu_fmt = execute_if[block_idx].data.imm[`INST_FMT_BITS-1:0]; + wire [`INST_FRM_BITS-1:0] fpu_frm = execute_if[block_idx].data.op_mod[`INST_FRM_BITS-1:0]; + + wire execute_fire = execute_if[block_idx].valid && execute_if[block_idx].ready; + wire fpu_rsp_fire = fpu_rsp_valid && fpu_rsp_ready; + + VX_index_buffer #( + .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + PID_WIDTH + 1 + 1), + .SIZE (`FPU_REQ_QUEUE_SIZE) + ) tag_store ( + .clk (clk), + .reset (reset), + .acquire_en (execute_fire), + .write_addr (fpu_req_tag), + .write_data ({execute_if[block_idx].data.uuid, execute_if[block_idx].data.wid, execute_if[block_idx].data.tmask, execute_if[block_idx].data.PC, execute_if[block_idx].data.rd, execute_if[block_idx].data.pid, execute_if[block_idx].data.sop, execute_if[block_idx].data.eop}), + .read_data ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop}), + .read_addr (fpu_rsp_tag), + .release_en (fpu_rsp_fire), + .full (mdata_full), + `UNUSED_PIN (empty) + ); + + // resolve dynamic FRM from CSR + wire [`INST_FRM_BITS-1:0] fpu_req_frm; + `ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].read_wid, execute_if[block_idx].data.wid, block_idx, `NUM_FPU_BLOCKS) + assign fpu_req_frm = (execute_if[block_idx].data.op_type != `INST_FPU_MISC + && fpu_frm == `INST_FRM_DYN) ? fpu_to_csr_if[block_idx].read_frm : fpu_frm; + + // submit FPU request + + assign fpu_req_valid = execute_if[block_idx].valid && ~mdata_full; + assign execute_if[block_idx].ready = fpu_req_ready && ~mdata_full; + + `RESET_RELAY (fpu_reset, reset); + + `ifdef FPU_DPI + + VX_fpu_dpi #( + .NUM_LANES (NUM_LANES), + .TAGW (TAG_WIDTH), + .OUT_REG (PARTIAL_BW ? 1 : 3) + ) fpu_dpi ( + .clk (clk), + .reset (fpu_reset), + + .valid_in (fpu_req_valid), + .op_type (execute_if[block_idx].data.op_type), + .lane_mask (execute_if[block_idx].data.tmask), + .fmt (fpu_fmt), + .frm (fpu_req_frm), + .dataa (execute_if[block_idx].data.rs1_data), + .datab (execute_if[block_idx].data.rs2_data), + .datac (execute_if[block_idx].data.rs3_data), + .tag_in (fpu_req_tag), + .ready_in (fpu_req_ready), + + .valid_out (fpu_rsp_valid), + .result (fpu_rsp_result), + .has_fflags (fpu_rsp_has_fflags), + .fflags (fpu_rsp_fflags), + .tag_out (fpu_rsp_tag), + .ready_out (fpu_rsp_ready) + ); + + `elsif FPU_FPNEW + + VX_fpu_fpnew #( + .NUM_LANES (NUM_LANES), + .TAGW (TAG_WIDTH), + .OUT_REG (PARTIAL_BW ? 1 : 3) + ) fpu_fpnew ( + .clk (clk), + .reset (fpu_reset), + + .valid_in (fpu_req_valid), + .op_type (execute_if[block_idx].data.op_type), + .lane_mask (execute_if[block_idx].data.tmask), + .fmt (fpu_fmt), + .frm (fpu_req_frm), + .dataa (execute_if[block_idx].data.rs1_data), + .datab (execute_if[block_idx].data.rs2_data), + .datac (execute_if[block_idx].data.rs3_data), + .tag_in (fpu_req_tag), + .ready_in (fpu_req_ready), + + .valid_out (fpu_rsp_valid), + .result (fpu_rsp_result), + .has_fflags (fpu_rsp_has_fflags), + .fflags (fpu_rsp_fflags), + .tag_out (fpu_rsp_tag), + .ready_out (fpu_rsp_ready) + ); + + `elsif FPU_DSP + + VX_fpu_dsp #( + .NUM_LANES (NUM_LANES), + .TAGW (TAG_WIDTH), + .OUT_REG (PARTIAL_BW ? 1 : 3) + ) fpu_dsp ( + .clk (clk), + .reset (fpu_reset), + + .valid_in (fpu_req_valid), + .lane_mask (execute_if[block_idx].data.tmask), + .op_type (execute_if[block_idx].data.op_type), + .fmt (fpu_fmt), + .frm (fpu_req_frm), + .dataa (execute_if[block_idx].data.rs1_data), + .datab (execute_if[block_idx].data.rs2_data), + .datac (execute_if[block_idx].data.rs3_data), + .tag_in (fpu_req_tag), + .ready_in (fpu_req_ready), + + .valid_out (fpu_rsp_valid), + .result (fpu_rsp_result), + .has_fflags (fpu_rsp_has_fflags), + .fflags (fpu_rsp_fflags), + .tag_out (fpu_rsp_tag), + .ready_out (fpu_rsp_ready) + ); + + `endif + + // handle FPU response + + fflags_t fpu_rsp_fflags_q; + + if (PID_BITS != 0) begin + fflags_t fpu_rsp_fflags_r; + always @(posedge clk) begin + if (reset) begin + fpu_rsp_fflags_r <= '0; + end else if (fpu_rsp_fire) begin + fpu_rsp_fflags_r <= fpu_rsp_eop ? '0 : (fpu_rsp_fflags_r | fpu_rsp_fflags); + end + end + assign fpu_rsp_fflags_q = fpu_rsp_fflags_r | fpu_rsp_fflags; + end else begin + assign fpu_rsp_fflags_q = fpu_rsp_fflags; + end + + assign fpu_to_csr_if[block_idx].write_enable = fpu_rsp_fire && fpu_rsp_eop && fpu_rsp_has_fflags; + `ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].write_wid, fpu_rsp_wid, block_idx, `NUM_FPU_BLOCKS) + assign fpu_to_csr_if[block_idx].write_fflags = fpu_rsp_fflags_q; + + // send response + + VX_elastic_buffer #( + .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + (NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1), + .SIZE (0) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (fpu_rsp_valid), + .ready_in (fpu_rsp_ready), + .data_in ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_result, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop}), + .data_out ({commit_block_if[block_idx].data.uuid, commit_block_if[block_idx].data.wid, commit_block_if[block_idx].data.tmask, commit_block_if[block_idx].data.PC, commit_block_if[block_idx].data.rd, commit_block_if[block_idx].data.data, commit_block_if[block_idx].data.pid, commit_block_if[block_idx].data.sop, commit_block_if[block_idx].data.eop}), + .valid_out (commit_block_if[block_idx].valid), + .ready_out (commit_block_if[block_idx].ready) + ); + assign commit_block_if[block_idx].data.wb = 1'b1; + end + + `RESET_RELAY (commit_reset, reset); + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_REG (PARTIAL_BW ? 3 : 0) + ) gather_unit ( + .clk (clk), + .reset (commit_reset), + .commit_in_if (commit_block_if), + .commit_out_if (commit_if) + ); + +endmodule diff --git a/hw/rtl/interfaces/VX_alu_req_if.sv b/hw/rtl/interfaces/VX_alu_req_if.sv deleted file mode 100644 index f6818e7d..00000000 --- a/hw/rtl/interfaces/VX_alu_req_if.sv +++ /dev/null @@ -1,68 +0,0 @@ -`ifndef VX_ALU_REQ_IF -`define VX_ALU_REQ_IF - -`include "VX_define.vh" - -interface VX_alu_req_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [31:0] next_PC; - wire [`INST_ALU_BITS-1:0] op_type; - wire [`INST_MOD_BITS-1:0] op_mod; - wire use_PC; - wire use_imm; - wire [31:0] imm; - wire [`NT_BITS-1:0] tid; - wire [`NUM_THREADS-1:0][31:0] rs1_data; - wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - - modport master ( - output valid, - output uuid, - output wid, - output tmask, - output PC, - output next_PC, - output op_type, - output op_mod, - output use_PC, - output use_imm, - output imm, - output tid, - output rs1_data, - output rs2_data, - output rd, - output wb, - input ready - ); - - modport slave ( - input valid, - input uuid, - input wid, - input tmask, - input PC, - input next_PC, - input op_type, - input op_mod, - input use_PC, - input use_imm, - input imm, - input tid, - input rs1_data, - input rs2_data, - input rd, - input wb, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_branch_ctl_if.sv b/hw/rtl/interfaces/VX_branch_ctl_if.sv index f71c43fe..9c2e3d10 100644 --- a/hw/rtl/interfaces/VX_branch_ctl_if.sv +++ b/hw/rtl/interfaces/VX_branch_ctl_if.sv @@ -1,14 +1,24 @@ -`ifndef VX_BRANCH_RSP_IF -`define VX_BRANCH_RSP_IF +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. `include "VX_define.vh" interface VX_branch_ctl_if (); - wire valid; - wire [`NW_BITS-1:0] wid; - wire taken; - wire [31:0] dest; + wire valid; + wire [`NW_WIDTH-1:0] wid; + wire taken; + wire [`XLEN-1:0] dest; modport master ( output valid, @@ -25,5 +35,3 @@ interface VX_branch_ctl_if (); ); endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cmt_to_csr_if.sv b/hw/rtl/interfaces/VX_cmt_to_csr_if.sv deleted file mode 100644 index ed5ffc24..00000000 --- a/hw/rtl/interfaces/VX_cmt_to_csr_if.sv +++ /dev/null @@ -1,26 +0,0 @@ -`ifndef VX_CMT_TO_CSR_IF -`define VX_CMT_TO_CSR_IF - -`include "VX_define.vh" - -interface VX_cmt_to_csr_if (); - - wire valid; -`ifdef EXT_F_ENABLE - wire [$clog2(6*`NUM_THREADS+1)-1:0] commit_size; -`else - wire [$clog2(5*`NUM_THREADS+1)-1:0] commit_size; -`endif - modport master ( - output valid, - output commit_size - ); - - modport slave ( - input valid, - input commit_size - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_commit_csr_if.sv b/hw/rtl/interfaces/VX_commit_csr_if.sv new file mode 100644 index 00000000..d226855e --- /dev/null +++ b/hw/rtl/interfaces/VX_commit_csr_if.sv @@ -0,0 +1,28 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_commit_csr_if (); + + wire [`PERF_CTR_BITS-1:0] instret; + + modport master ( + output instret + ); + + modport slave ( + input instret + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_commit_if.sv b/hw/rtl/interfaces/VX_commit_if.sv index ddbd9600..e5bfa13a 100644 --- a/hw/rtl/interfaces/VX_commit_if.sv +++ b/hw/rtl/interfaces/VX_commit_if.sv @@ -1,47 +1,50 @@ -`ifndef VX_COMMIT_IF -`define VX_COMMIT_IF +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. `include "VX_define.vh" -interface VX_commit_if (); +interface VX_commit_if #( + parameter NUM_LANES = `NUM_THREADS, + parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES) +) (); + + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [`NW_WIDTH-1:0] wid; + logic [NUM_LANES-1:0] tmask; + logic [`XLEN-1:0] PC; + logic wb; + logic [`NR_BITS-1:0] rd; + logic [NUM_LANES-1:0][`XLEN-1:0] data; + logic [PID_WIDTH-1:0] pid; + logic sop; + logic eop; + } data_t; - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`NUM_THREADS-1:0][31:0] data; - wire [`NR_BITS-1:0] rd; - wire wb; - wire eop; - wire ready; + logic valid; + data_t data; + logic ready; modport master ( output valid, - output uuid, - output wid, - output tmask, - output PC, output data, - output rd, - output wb, - output eop, input ready ); modport slave ( input valid, - input uuid, - input wid, - input tmask, - input PC, input data, - input rd, - input wb, - input eop, output ready ); endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_commit_sched_if.sv b/hw/rtl/interfaces/VX_commit_sched_if.sv new file mode 100644 index 00000000..487a3c6c --- /dev/null +++ b/hw/rtl/interfaces/VX_commit_sched_if.sv @@ -0,0 +1,31 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_commit_sched_if (); + + wire [`ISSUE_WIDTH-1:0] committed; + wire [`ISSUE_WIDTH-1:0][`NW_WIDTH-1:0] committed_wid; + + modport master ( + output committed, + output committed_wid + ); + + modport slave ( + input committed, + input committed_wid + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_csr_req_if.sv b/hw/rtl/interfaces/VX_csr_req_if.sv deleted file mode 100644 index c8eef24a..00000000 --- a/hw/rtl/interfaces/VX_csr_req_if.sv +++ /dev/null @@ -1,56 +0,0 @@ -`ifndef VX_CSR_REQ_IF -`define VX_CSR_REQ_IF - -`include "VX_define.vh" - -interface VX_csr_req_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`INST_CSR_BITS-1:0] op_type; - wire [`CSR_ADDR_BITS-1:0] addr; - wire [31:0] rs1_data; - wire use_imm; - wire [`NRI_BITS-1:0] imm; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - - modport master ( - output valid, - output uuid, - output wid, - output tmask, - output PC, - output op_type, - output addr, - output rs1_data, - output use_imm, - output imm, - output rd, - output wb, - input ready - ); - - modport slave ( - input valid, - input uuid, - input wid, - input tmask, - input PC, - input op_type, - input addr, - input rs1_data, - input use_imm, - input imm, - input rd, - input wb, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_dcache_req_if.sv b/hw/rtl/interfaces/VX_dcache_req_if.sv deleted file mode 100644 index 13f3b00b..00000000 --- a/hw/rtl/interfaces/VX_dcache_req_if.sv +++ /dev/null @@ -1,42 +0,0 @@ -`ifndef VX_DCACHE_REQ_IF -`define VX_DCACHE_REQ_IF - -`include "../cache/VX_cache_define.vh" - -interface VX_dcache_req_if #( - parameter NUM_REQS = 1, - parameter WORD_SIZE = 1, - parameter TAG_WIDTH = 1 -) (); - - wire [NUM_REQS-1:0] valid; - wire [NUM_REQS-1:0] rw; - wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen; - wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] addr; - wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data; - wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag; - wire [NUM_REQS-1:0] ready; - - modport master ( - output valid, - output rw, - output byteen, - output addr, - output data, - output tag, - input ready - ); - - modport slave ( - input valid, - input rw, - input byteen, - input addr, - input data, - input tag, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_dcache_rsp_if.sv b/hw/rtl/interfaces/VX_dcache_rsp_if.sv deleted file mode 100644 index 0f424501..00000000 --- a/hw/rtl/interfaces/VX_dcache_rsp_if.sv +++ /dev/null @@ -1,36 +0,0 @@ -`ifndef VX_DCACHE_RSP_IF -`define VX_DCACHE_RSP_IF - -`include "../cache/VX_cache_define.vh" - -interface VX_dcache_rsp_if #( - parameter NUM_REQS = 1, - parameter WORD_SIZE = 1, - parameter TAG_WIDTH = 1 -) (); - - wire valid; - wire [NUM_REQS-1:0] tmask; - wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data; - wire [TAG_WIDTH-1:0] tag; - wire ready; - - modport master ( - output valid, - output tmask, - output data, - output tag, - input ready - ); - - modport slave ( - input valid, - input tmask, - input data, - input tag, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_dcr_bus_if.sv b/hw/rtl/interfaces/VX_dcr_bus_if.sv new file mode 100644 index 00000000..6036661a --- /dev/null +++ b/hw/rtl/interfaces/VX_dcr_bus_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_dcr_bus_if (); + + wire write_valid; + wire [`VX_DCR_ADDR_WIDTH-1:0] write_addr; + wire [`VX_DCR_DATA_WIDTH-1:0] write_data; + + modport master ( + output write_valid, + output write_addr, + output write_data + ); + + modport slave ( + input write_valid, + input write_addr, + input write_data + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_decode_if.sv b/hw/rtl/interfaces/VX_decode_if.sv index 5c00fb0f..d433ca47 100644 --- a/hw/rtl/interfaces/VX_decode_if.sv +++ b/hw/rtl/interfaces/VX_decode_if.sv @@ -1,68 +1,56 @@ -`ifndef VX_DECODE_IF -`define VX_DECODE_IF +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. `include "VX_define.vh" interface VX_decode_if (); - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`EX_BITS-1:0] ex_type; - wire [`INST_OP_BITS-1:0] op_type; - wire [`INST_MOD_BITS-1:0] op_mod; - wire wb; - wire use_PC; - wire use_imm; - wire [31:0] imm; - wire [`NR_BITS-1:0] rd; - wire [`NR_BITS-1:0] rs1; - wire [`NR_BITS-1:0] rs2; - wire [`NR_BITS-1:0] rs3; - wire ready; + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [`NW_WIDTH-1:0] wid; + logic [`NUM_THREADS-1:0] tmask; + logic [`EX_BITS-1:0] ex_type; + logic [`INST_OP_BITS-1:0] op_type; + logic [`INST_MOD_BITS-1:0] op_mod; + logic wb; + logic use_PC; + logic use_imm; + logic [`XLEN-1:0] PC; + logic [`XLEN-1:0] imm; + logic [`NR_BITS-1:0] rd; + logic [`NR_BITS-1:0] rs1; + logic [`NR_BITS-1:0] rs2; + logic [`NR_BITS-1:0] rs3; + } data_t; + + logic valid; + data_t data; + logic ready; + + wire [`ISSUE_WIDTH-1:0] ibuf_pop; modport master ( output valid, - output uuid, - output wid, - output tmask, - output PC, - output ex_type, - output op_type, - output op_mod, - output wb, - output use_PC, - output use_imm, - output imm, - output rd, - output rs1, - output rs2, - output rs3, + output data, + input ibuf_pop, input ready ); modport slave ( input valid, - input uuid, - input wid, - input tmask, - input PC, - input ex_type, - input op_type, - input op_mod, - input wb, - input use_PC, - input use_imm, - input imm, - input rd, - input rs1, - input rs2, - input rs3, + input data, + output ibuf_pop, output ready ); endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_decode_sched_if.sv b/hw/rtl/interfaces/VX_decode_sched_if.sv new file mode 100644 index 00000000..b82aafb5 --- /dev/null +++ b/hw/rtl/interfaces/VX_decode_sched_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_decode_sched_if (); + + wire valid; + wire is_wstall; + wire [`NW_WIDTH-1:0] wid; + + modport master ( + output valid, + output is_wstall, + output wid + ); + + modport slave ( + input valid, + input is_wstall, + input wid + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_dispatch_if.sv b/hw/rtl/interfaces/VX_dispatch_if.sv new file mode 100644 index 00000000..9dd58fa6 --- /dev/null +++ b/hw/rtl/interfaces/VX_dispatch_if.sv @@ -0,0 +1,52 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_dispatch_if import VX_gpu_pkg::*; (); + // warning: this layout should not be modified without updating VX_dispatch_unit!!! + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [`NUM_THREADS-1:0] tmask; + logic [`INST_ALU_BITS-1:0] op_type; + logic [`INST_MOD_BITS-1:0] op_mod; + logic wb; + logic use_PC; + logic use_imm; + logic [`XLEN-1:0] PC; + logic [`XLEN-1:0] imm; + logic [`NR_BITS-1:0] rd; + logic [`NT_WIDTH-1:0] tid; + logic [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data; + logic [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data; + logic [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data; + } data_t; + + logic valid; + data_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_execute_if.sv b/hw/rtl/interfaces/VX_execute_if.sv new file mode 100644 index 00000000..b0c528d5 --- /dev/null +++ b/hw/rtl/interfaces/VX_execute_if.sv @@ -0,0 +1,57 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_execute_if #( + parameter NUM_LANES = 1, + parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES) +) (); + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [`NW_WIDTH-1:0] wid; + logic [NUM_LANES-1:0] tmask; + logic [`INST_ALU_BITS-1:0] op_type; + logic [`INST_MOD_BITS-1:0] op_mod; + logic wb; + logic use_PC; + logic use_imm; + logic [`XLEN-1:0] PC; + logic [`XLEN-1:0] imm; + logic [`NR_BITS-1:0] rd; + logic [`NT_WIDTH-1:0] tid; + logic [NUM_LANES-1:0][`XLEN-1:0] rs1_data; + logic [NUM_LANES-1:0][`XLEN-1:0] rs2_data; + logic [NUM_LANES-1:0][`XLEN-1:0] rs3_data; + logic [PID_WIDTH-1:0] pid; + logic sop; + logic eop; + } data_t; + + logic valid; + data_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_fetch_if.sv b/hw/rtl/interfaces/VX_fetch_if.sv new file mode 100644 index 00000000..06b27d90 --- /dev/null +++ b/hw/rtl/interfaces/VX_fetch_if.sv @@ -0,0 +1,46 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_fetch_if (); + + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [`NW_WIDTH-1:0] wid; + logic [`NUM_THREADS-1:0] tmask; + logic [`XLEN-1:0] PC; + logic [31:0] instr; + } data_t; + + logic valid; + data_t data; + logic ready; + + logic [`ISSUE_WIDTH-1:0] ibuf_pop; + + modport master ( + output valid, + output data, + input ibuf_pop, + input ready + ); + + modport slave ( + input valid, + input data, + output ibuf_pop, + output ready + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_fetch_to_csr_if.sv b/hw/rtl/interfaces/VX_fetch_to_csr_if.sv deleted file mode 100644 index 1c2e3ddb..00000000 --- a/hw/rtl/interfaces/VX_fetch_to_csr_if.sv +++ /dev/null @@ -1,20 +0,0 @@ -`ifndef VX_FETCH_TO_CSR_IF -`define VX_FETCH_TO_CSR_IF - -`include "VX_define.vh" - -interface VX_fetch_to_csr_if (); - - wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks; - - modport master ( - output thread_masks - ); - - modport slave ( - input thread_masks - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_req_if.sv b/hw/rtl/interfaces/VX_fpu_req_if.sv deleted file mode 100644 index 62ea9255..00000000 --- a/hw/rtl/interfaces/VX_fpu_req_if.sv +++ /dev/null @@ -1,56 +0,0 @@ -`ifndef VX_FPU_REQ_IF -`define VX_FPU_REQ_IF - -`include "VX_define.vh" - -interface VX_fpu_req_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`INST_FPU_BITS-1:0] op_type; - wire [`INST_MOD_BITS-1:0] op_mod; - wire [`NUM_THREADS-1:0][31:0] rs1_data; - wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NUM_THREADS-1:0][31:0] rs3_data; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - - modport master ( - output valid, - output uuid, - output wid, - output tmask, - output PC, - output op_type, - output op_mod, - output rs1_data, - output rs2_data, - output rs3_data, - output rd, - output wb, - input ready - ); - - modport slave ( - input valid, - input uuid, - input wid, - input tmask, - input PC, - input op_type, - input op_mod, - input rs1_data, - input rs2_data, - input rs3_data, - input rd, - input wb, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.sv b/hw/rtl/interfaces/VX_fpu_to_csr_if.sv deleted file mode 100644 index 62fe9628..00000000 --- a/hw/rtl/interfaces/VX_fpu_to_csr_if.sv +++ /dev/null @@ -1,33 +0,0 @@ -`ifndef VX_FPU_TO_CSR_IF -`define VX_FPU_TO_CSR_IF - -`include "VX_define.vh" - -interface VX_fpu_to_csr_if (); - - wire write_enable; - wire [`NW_BITS-1:0] write_wid; - fpu_types::fflags_t write_fflags; - - wire [`NW_BITS-1:0] read_wid; - wire [`INST_FRM_BITS-1:0] read_frm; - - modport master ( - output write_enable, - output write_wid, - output write_fflags, - output read_wid, - input read_frm - ); - - modport slave ( - input write_enable, - input write_wid, - input write_fflags, - input read_wid, - output read_frm - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_req_if.sv b/hw/rtl/interfaces/VX_gpr_req_if.sv deleted file mode 100644 index d34448f4..00000000 --- a/hw/rtl/interfaces/VX_gpr_req_if.sv +++ /dev/null @@ -1,29 +0,0 @@ -`ifndef VX_GPR_REQ_IF -`define VX_GPR_REQ_IF - -`include "VX_define.vh" - -interface VX_gpr_req_if (); - - wire [`NW_BITS-1:0] wid; - wire [`NR_BITS-1:0] rs1; - wire [`NR_BITS-1:0] rs2; - wire [`NR_BITS-1:0] rs3; - - modport master ( - output wid, - output rs1, - output rs2, - output rs3 - ); - - modport slave ( - input wid, - input rs1, - input rs2, - input rs3 - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_rsp_if.sv b/hw/rtl/interfaces/VX_gpr_rsp_if.sv deleted file mode 100644 index c323555c..00000000 --- a/hw/rtl/interfaces/VX_gpr_rsp_if.sv +++ /dev/null @@ -1,26 +0,0 @@ -`ifndef VX_GPR_RSP_IF -`define VX_GPR_RSP_IF - -`include "VX_define.vh" - -interface VX_gpr_rsp_if (); - - wire [`NUM_THREADS-1:0][31:0] rs1_data; - wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NUM_THREADS-1:0][31:0] rs3_data; - - modport master ( - output rs1_data, - output rs2_data, - output rs3_data - ); - - modport slave ( - input rs1_data, - input rs2_data, - input rs3_data - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_req_if.sv b/hw/rtl/interfaces/VX_gpu_req_if.sv deleted file mode 100644 index 027f7a2b..00000000 --- a/hw/rtl/interfaces/VX_gpu_req_if.sv +++ /dev/null @@ -1,62 +0,0 @@ -`ifndef VX_GPU_REQ_IF -`define VX_GPU_REQ_IF - -`include "VX_define.vh" - -interface VX_gpu_req_if(); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [31:0] next_PC; - wire [`INST_GPU_BITS-1:0] op_type; - wire [`INST_MOD_BITS-1:0] op_mod; - wire [`NT_BITS-1:0] tid; - wire [`NUM_THREADS-1:0][31:0] rs1_data; - wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NUM_THREADS-1:0][31:0] rs3_data; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - - modport master ( - output valid, - output uuid, - output wid, - output tmask, - output PC, - output next_PC, - output op_type, - output op_mod, - output tid, - output rs1_data, - output rs2_data, - output rs3_data, - output rd, - output wb, - input ready - ); - - modport slave ( - input valid, - input uuid, - input wid, - input tmask, - input PC, - input next_PC, - input op_type, - input op_mod, - input tid, - input rs1_data, - input rs2_data, - input rs3_data, - input rd, - input wb, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ibuffer_if.sv b/hw/rtl/interfaces/VX_ibuffer_if.sv index 2f9c17b6..f1ff15b7 100644 --- a/hw/rtl/interfaces/VX_ibuffer_if.sv +++ b/hw/rtl/interfaces/VX_ibuffer_if.sv @@ -1,85 +1,52 @@ -`ifndef VX_IBUFFER_IF -`define VX_IBUFFER_IF +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. `include "VX_define.vh" -interface VX_ibuffer_if (); +interface VX_ibuffer_if import VX_gpu_pkg::*; (); - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`EX_BITS-1:0] ex_type; - wire [`INST_OP_BITS-1:0] op_type; - wire [`INST_MOD_BITS-1:0] op_mod; - wire wb; - wire use_PC; - wire use_imm; - wire [31:0] imm; - wire [`NR_BITS-1:0] rd; - wire [`NR_BITS-1:0] rs1; - wire [`NR_BITS-1:0] rs2; - wire [`NR_BITS-1:0] rs3; - - wire [`NR_BITS-1:0] rd_n; - wire [`NR_BITS-1:0] rs1_n; - wire [`NR_BITS-1:0] rs2_n; - wire [`NR_BITS-1:0] rs3_n; - wire [`NW_BITS-1:0] wid_n; + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [`NUM_THREADS-1:0] tmask; + logic [`EX_BITS-1:0] ex_type; + logic [`INST_OP_BITS-1:0] op_type; + logic [`INST_MOD_BITS-1:0] op_mod; + logic wb; + logic use_PC; + logic use_imm; + logic [`XLEN-1:0] PC; + logic [`XLEN-1:0] imm; + logic [`NR_BITS-1:0] rd; + logic [`NR_BITS-1:0] rs1; + logic [`NR_BITS-1:0] rs2; + logic [`NR_BITS-1:0] rs3; + } data_t; - wire ready; + logic valid; + data_t data; + logic ready; modport master ( output valid, - output uuid, - output wid, - output tmask, - output PC, - output ex_type, - output op_type, - output op_mod, - output wb, - output use_PC, - output use_imm, - output imm, - output rd, - output rs1, - output rs2, - output rs3, - output rd_n, - output rs1_n, - output rs2_n, - output rs3_n, - output wid_n, + output data, input ready ); modport slave ( input valid, - input uuid, - input wid, - input tmask, - input PC, - input ex_type, - input op_type, - input op_mod, - input wb, - input use_PC, - input use_imm, - input imm, - input rd, - input rs1, - input rs2, - input rs3, - input rd_n, - input rs1_n, - input rs2_n, - input rs3_n, - input wid_n, + input data, output ready ); - -endinterface -`endif \ No newline at end of file +endinterface diff --git a/hw/rtl/interfaces/VX_icache_req_if.sv b/hw/rtl/interfaces/VX_icache_req_if.sv deleted file mode 100644 index 1decc6a5..00000000 --- a/hw/rtl/interfaces/VX_icache_req_if.sv +++ /dev/null @@ -1,32 +0,0 @@ -`ifndef VX_ICACHE_CORE_REQ_IF -`define VX_ICACHE_CORE_REQ_IF - -`include "../cache/VX_cache_define.vh" - -interface VX_icache_req_if #( - parameter WORD_SIZE = 1, - parameter TAG_WIDTH = 1 -) (); - - wire valid; - wire [`WORD_ADDR_WIDTH-1:0] addr; - wire [TAG_WIDTH-1:0] tag; - wire ready; - - modport master ( - output valid, - output addr, - output tag, - input ready - ); - - modport slave ( - input valid, - input addr, - input tag, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_icache_rsp_if.sv b/hw/rtl/interfaces/VX_icache_rsp_if.sv deleted file mode 100644 index 71cee32b..00000000 --- a/hw/rtl/interfaces/VX_icache_rsp_if.sv +++ /dev/null @@ -1,32 +0,0 @@ -`ifndef VX_ICACHE_CORE_RSP_IF -`define VX_ICACHE_CORE_RSP_IF - -`include "../cache/VX_cache_define.vh" - -interface VX_icache_rsp_if #( - parameter WORD_SIZE = 1, - parameter TAG_WIDTH = 1 -) (); - - wire valid; - wire [`WORD_WIDTH-1:0] data; - wire [TAG_WIDTH-1:0] tag; - wire ready; - - modport master ( - output valid, - output data, - output tag, - input ready - ); - - modport slave ( - input valid, - input data, - input tag, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ifetch_req_if.sv b/hw/rtl/interfaces/VX_ifetch_req_if.sv deleted file mode 100644 index 95e88223..00000000 --- a/hw/rtl/interfaces/VX_ifetch_req_if.sv +++ /dev/null @@ -1,35 +0,0 @@ -`ifndef VX_IFETCH_REQ_IF -`define VX_IFETCH_REQ_IF - -`include "VX_define.vh" - -interface VX_ifetch_req_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NUM_THREADS-1:0] tmask; - wire [`NW_BITS-1:0] wid; - wire [31:0] PC; - wire ready; - - modport master ( - output valid, - output uuid, - output tmask, - output wid, - output PC, - input ready - ); - - modport slave ( - input valid, - input uuid, - input tmask, - input wid, - input PC, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ifetch_rsp_if.sv b/hw/rtl/interfaces/VX_ifetch_rsp_if.sv deleted file mode 100644 index f47e8749..00000000 --- a/hw/rtl/interfaces/VX_ifetch_rsp_if.sv +++ /dev/null @@ -1,38 +0,0 @@ -`ifndef VX_IFETCH_RSP_IF -`define VX_IFETCH_RSP_IF - -`include "VX_define.vh" - -interface VX_ifetch_rsp_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NUM_THREADS-1:0] tmask; - wire [`NW_BITS-1:0] wid; - wire [31:0] PC; - wire [31:0] data; - wire ready; - - modport master ( - output valid, - output uuid, - output tmask, - output wid, - output PC, - output data, - input ready - ); - - modport slave ( - input valid, - input uuid, - input tmask, - input wid, - input PC, - input data, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_join_if.sv b/hw/rtl/interfaces/VX_join_if.sv deleted file mode 100644 index d39ed9c0..00000000 --- a/hw/rtl/interfaces/VX_join_if.sv +++ /dev/null @@ -1,23 +0,0 @@ -`ifndef VX_JOIN_IF -`define VX_JOIN_IF - -`include "VX_define.vh" - -interface VX_join_if (); - - wire valid; - wire [`NW_BITS-1:0] wid; - - modport master ( - output valid, - output wid - ); - - modport slave ( - input valid, - input wid - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_lsu_req_if.sv b/hw/rtl/interfaces/VX_lsu_req_if.sv deleted file mode 100644 index f52b22da..00000000 --- a/hw/rtl/interfaces/VX_lsu_req_if.sv +++ /dev/null @@ -1,59 +0,0 @@ -`ifndef VX_LSU_REQ_IF -`define VX_LSU_REQ_IF - -`include "VX_define.vh" - -interface VX_lsu_req_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`INST_LSU_BITS-1:0] op_type; - wire is_fence; - wire [`NUM_THREADS-1:0][31:0] store_data; - wire [`NUM_THREADS-1:0][31:0] base_addr; - wire [31:0] offset; - wire [`NR_BITS-1:0] rd; - wire wb; - wire ready; - wire is_prefetch; - - modport master ( - output valid, - output uuid, - output wid, - output tmask, - output PC, - output op_type, - output is_fence, - output store_data, - output base_addr, - output offset, - output rd, - output wb, - output is_prefetch, - input ready - ); - - modport slave ( - input valid, - input uuid, - input wid, - input tmask, - input PC, - input op_type, - input is_fence, - input store_data, - input base_addr, - input offset, - input rd, - input wb, - input is_prefetch, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_mem_req_if.sv b/hw/rtl/interfaces/VX_mem_req_if.sv deleted file mode 100644 index 50bde8a2..00000000 --- a/hw/rtl/interfaces/VX_mem_req_if.sv +++ /dev/null @@ -1,43 +0,0 @@ -`ifndef VX_MEM_REQ_IF -`define VX_MEM_REQ_IF - -`include "../cache/VX_cache_define.vh" - -interface VX_mem_req_if #( - parameter DATA_WIDTH = 1, - parameter ADDR_WIDTH = 1, - parameter TAG_WIDTH = 1, - parameter DATA_SIZE = DATA_WIDTH / 8 -) (); - - wire valid; - wire rw; - wire [DATA_SIZE-1:0] byteen; - wire [ADDR_WIDTH-1:0] addr; - wire [DATA_WIDTH-1:0] data; - wire [TAG_WIDTH-1:0] tag; - wire ready; - - modport master ( - output valid, - output rw, - output byteen, - output addr, - output data, - output tag, - input ready - ); - - modport slave ( - input valid, - input rw, - input byteen, - input addr, - input data, - input tag, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_mem_rsp_if.sv b/hw/rtl/interfaces/VX_mem_rsp_if.sv deleted file mode 100644 index 3ee69d88..00000000 --- a/hw/rtl/interfaces/VX_mem_rsp_if.sv +++ /dev/null @@ -1,32 +0,0 @@ -`ifndef VX_MEM_RSP_IF -`define VX_MEM_RSP_IF - -`include "../cache/VX_cache_define.vh" - -interface VX_mem_rsp_if #( - parameter DATA_WIDTH = 1, - parameter TAG_WIDTH = 1 -) (); - - wire valid; - wire [DATA_WIDTH-1:0] data; - wire [TAG_WIDTH-1:0] tag; - wire ready; - - modport master ( - output valid, - output data, - output tag, - input ready - ); - - modport slave ( - input valid, - input data, - input tag, - output ready - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_operands_if.sv b/hw/rtl/interfaces/VX_operands_if.sv new file mode 100644 index 00000000..7ac7a27b --- /dev/null +++ b/hw/rtl/interfaces/VX_operands_if.sv @@ -0,0 +1,52 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_operands_if import VX_gpu_pkg::*; (); + + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [`NUM_THREADS-1:0] tmask; + logic [`XLEN-1:0] PC; + logic [`EX_BITS-1:0] ex_type; + logic [`INST_OP_BITS-1:0] op_type; + logic [`INST_MOD_BITS-1:0] op_mod; + logic wb; + logic use_PC; + logic use_imm; + logic [`XLEN-1:0] imm; + logic [`NR_BITS-1:0] rd; + logic [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data; + logic [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data; + logic [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data; + } data_t; + + logic valid; + data_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_perf_memsys_if.sv b/hw/rtl/interfaces/VX_perf_memsys_if.sv deleted file mode 100644 index 9a38dc26..00000000 --- a/hw/rtl/interfaces/VX_perf_memsys_if.sv +++ /dev/null @@ -1,59 +0,0 @@ -`ifndef VX_PERF_MEMSYS_IF -`define VX_PERF_MEMSYS_IF - -`include "VX_define.vh" - -interface VX_perf_memsys_if (); - - wire [`PERF_CTR_BITS-1:0] icache_reads; - wire [`PERF_CTR_BITS-1:0] icache_read_misses; - wire [`PERF_CTR_BITS-1:0] dcache_reads; - wire [`PERF_CTR_BITS-1:0] dcache_writes; - wire [`PERF_CTR_BITS-1:0] dcache_read_misses; - wire [`PERF_CTR_BITS-1:0] dcache_write_misses; - wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls; - wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls; - wire [`PERF_CTR_BITS-1:0] smem_reads; - wire [`PERF_CTR_BITS-1:0] smem_writes; - wire [`PERF_CTR_BITS-1:0] smem_bank_stalls; - wire [`PERF_CTR_BITS-1:0] mem_reads; - wire [`PERF_CTR_BITS-1:0] mem_writes; - wire [`PERF_CTR_BITS-1:0] mem_latency; - - modport master ( - output icache_reads, - output icache_read_misses, - output dcache_reads, - output dcache_writes, - output dcache_read_misses, - output dcache_write_misses, - output dcache_bank_stalls, - output dcache_mshr_stalls, - output smem_reads, - output smem_writes, - output smem_bank_stalls, - output mem_reads, - output mem_writes, - output mem_latency - ); - - modport slave ( - input icache_reads, - input icache_read_misses, - input dcache_reads, - input dcache_writes, - input dcache_read_misses, - input dcache_write_misses, - input dcache_bank_stalls, - input dcache_mshr_stalls, - input smem_reads, - input smem_writes, - input smem_bank_stalls, - input mem_reads, - input mem_writes, - input mem_latency - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_pipeline_if.sv b/hw/rtl/interfaces/VX_perf_pipeline_if.sv deleted file mode 100644 index a4470e4c..00000000 --- a/hw/rtl/interfaces/VX_perf_pipeline_if.sv +++ /dev/null @@ -1,56 +0,0 @@ -`ifndef VX_PERF_PIPELINE_IF -`define VX_PERF_PIPELINE_IF - -`include "VX_define.vh" - -interface VX_perf_pipeline_if (); - wire [`PERF_CTR_BITS-1:0] loads; - wire [`PERF_CTR_BITS-1:0] stores; - wire [`PERF_CTR_BITS-1:0] branches; - - wire [`PERF_CTR_BITS-1:0] ibf_stalls; - wire [`PERF_CTR_BITS-1:0] scb_stalls; - wire [`PERF_CTR_BITS-1:0] lsu_stalls; - wire [`PERF_CTR_BITS-1:0] csr_stalls; - wire [`PERF_CTR_BITS-1:0] alu_stalls; -`ifdef EXT_F_ENABLE - wire [`PERF_CTR_BITS-1:0] fpu_stalls; -`endif - wire [`PERF_CTR_BITS-1:0] gpu_stalls; - - modport decode ( - output loads, - output stores, - output branches - ); - - modport issue ( - output ibf_stalls, - output scb_stalls, - output lsu_stalls, - output csr_stalls, - output alu_stalls, - `ifdef EXT_F_ENABLE - output fpu_stalls, - `endif - output gpu_stalls - ); - - modport slave ( - input loads, - input stores, - input branches, - input ibf_stalls, - input scb_stalls, - input lsu_stalls, - input csr_stalls, - input alu_stalls, - `ifdef EXT_F_ENABLE - input fpu_stalls, - `endif - input gpu_stalls - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_tex_if.sv b/hw/rtl/interfaces/VX_perf_tex_if.sv deleted file mode 100644 index 222ade53..00000000 --- a/hw/rtl/interfaces/VX_perf_tex_if.sv +++ /dev/null @@ -1,23 +0,0 @@ -`ifndef VX_PERF_TEX_IF -`define VX_PERF_TEX_IF - -`include "VX_define.vh" - -interface VX_perf_tex_if (); - - wire [`PERF_CTR_BITS-1:0] mem_reads; - wire [`PERF_CTR_BITS-1:0] mem_latency; - - modport master ( - output mem_reads, - output mem_latency - ); - - modport slave ( - input mem_reads, - input mem_latency - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_pipeline_perf_if.sv b/hw/rtl/interfaces/VX_pipeline_perf_if.sv new file mode 100644 index 00000000..b6123b7f --- /dev/null +++ b/hw/rtl/interfaces/VX_pipeline_perf_if.sv @@ -0,0 +1,44 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_pipeline_perf_if (); + wire [`PERF_CTR_BITS-1:0] ibf_stalls; + wire [`PERF_CTR_BITS-1:0] scb_stalls; + wire [`PERF_CTR_BITS-1:0] dsp_stalls [`NUM_EX_UNITS]; + + wire [`PERF_CTR_BITS-1:0] ifetches; + wire [`PERF_CTR_BITS-1:0] loads; + wire [`PERF_CTR_BITS-1:0] stores; + wire [`PERF_CTR_BITS-1:0] ifetch_latency; + wire [`PERF_CTR_BITS-1:0] load_latency; + + modport issue ( + output ibf_stalls, + output scb_stalls, + output dsp_stalls + ); + + modport slave ( + input ibf_stalls, + input scb_stalls, + input dsp_stalls, + input ifetches, + input loads, + input stores, + input ifetch_latency, + input load_latency + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_sched_csr_if.sv b/hw/rtl/interfaces/VX_sched_csr_if.sv new file mode 100644 index 00000000..8c7f7ee4 --- /dev/null +++ b/hw/rtl/interfaces/VX_sched_csr_if.sv @@ -0,0 +1,46 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_sched_csr_if (); + + wire [`PERF_CTR_BITS-1:0] cycles; + wire [`NUM_WARPS-1:0] active_warps; + wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks; + wire alm_empty; + wire [`NW_WIDTH-1:0] alm_empty_wid; + wire unlock_warp; + wire [`NW_WIDTH-1:0] unlock_wid; + + modport master ( + output cycles, + output active_warps, + output thread_masks, + input alm_empty_wid, + output alm_empty, + input unlock_wid, + input unlock_warp + ); + + modport slave ( + input cycles, + input active_warps, + input thread_masks, + output alm_empty_wid, + input alm_empty, + output unlock_wid, + output unlock_warp + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_schedule_if.sv b/hw/rtl/interfaces/VX_schedule_if.sv new file mode 100644 index 00000000..1d2c1c70 --- /dev/null +++ b/hw/rtl/interfaces/VX_schedule_if.sv @@ -0,0 +1,41 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_schedule_if (); + + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [`NW_WIDTH-1:0] wid; + logic [`NUM_THREADS-1:0] tmask; + logic [`XLEN-1:0] PC; + } data_t; + + logic valid; + data_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_sfu_csr_if.sv b/hw/rtl/interfaces/VX_sfu_csr_if.sv new file mode 100644 index 00000000..4b968014 --- /dev/null +++ b/hw/rtl/interfaces/VX_sfu_csr_if.sv @@ -0,0 +1,73 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_sfu_csr_if #( + parameter NUM_LANES = `NUM_SFU_LANES, + parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES) +) (); + + wire read_enable; + wire [`UUID_WIDTH-1:0] read_uuid; + wire [`NW_WIDTH-1:0] read_wid; + wire [NUM_LANES-1:0] read_tmask; + wire [PID_WIDTH-1:0] read_pid; + wire [`VX_CSR_ADDR_BITS-1:0] read_addr; + wire [NUM_LANES-1:0][31:0] read_data; + + wire write_enable; + wire [`UUID_WIDTH-1:0] write_uuid; + wire [`NW_WIDTH-1:0] write_wid; + wire [NUM_LANES-1:0] write_tmask; + wire [PID_WIDTH-1:0] write_pid; + wire [`VX_CSR_ADDR_BITS-1:0] write_addr; + wire [NUM_LANES-1:0][31:0] write_data; + + modport master ( + output read_enable, + output read_uuid, + output read_wid, + output read_tmask, + output read_pid, + output read_addr, + input read_data, + + output write_enable, + output write_uuid, + output write_wid, + output write_tmask, + output write_pid, + output write_addr, + output write_data + ); + + modport slave ( + input read_enable, + input read_uuid, + input read_wid, + input read_tmask, + input read_pid, + input read_addr, + output read_data, + + input write_enable, + input write_uuid, + input write_wid, + input write_tmask, + input write_pid, + input write_addr, + input write_data + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_sfu_perf_if.sv b/hw/rtl/interfaces/VX_sfu_perf_if.sv new file mode 100644 index 00000000..db9c5d12 --- /dev/null +++ b/hw/rtl/interfaces/VX_sfu_perf_if.sv @@ -0,0 +1,27 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_sfu_perf_if (); + wire [`PERF_CTR_BITS-1:0] wctl_stalls; + + modport master ( + output wctl_stalls + ); + + modport slave ( + input wctl_stalls + ); + +endinterface diff --git a/hw/rtl/interfaces/VX_tex_csr_if.sv b/hw/rtl/interfaces/VX_tex_csr_if.sv deleted file mode 100644 index e0c626a5..00000000 --- a/hw/rtl/interfaces/VX_tex_csr_if.sv +++ /dev/null @@ -1,29 +0,0 @@ -`ifndef VX_TEX_CSR_IF -`define VX_TEX_CSR_IF - -`include "VX_define.vh" - -interface VX_tex_csr_if (); - - wire write_enable; - wire [`CSR_ADDR_BITS-1:0] write_addr; - wire [31:0] write_data; - wire [`UUID_BITS-1:0] write_uuid; - - modport master ( - output write_enable, - output write_addr, - output write_data, - output write_uuid - ); - - modport slave ( - input write_enable, - input write_addr, - input write_data, - input write_uuid - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_tex_req_if.sv b/hw/rtl/interfaces/VX_tex_req_if.sv deleted file mode 100644 index a3fec613..00000000 --- a/hw/rtl/interfaces/VX_tex_req_if.sv +++ /dev/null @@ -1,54 +0,0 @@ -`ifndef VX_TEX_REQ_IF -`define VX_TEX_REQ_IF - -`include "VX_define.vh" - -interface VX_tex_req_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`NR_BITS-1:0] rd; - wire wb; - - wire [`NTEX_BITS-1:0] unit; - wire [1:0][`NUM_THREADS-1:0][31:0] coords; - wire [`NUM_THREADS-1:0][31:0] lod; - - wire ready; - - modport master ( - output valid, - output uuid, - output wid, - output tmask, - output PC, - output rd, - output wb, - output unit, - output coords, - output lod, - input ready - ); - - modport slave ( - input valid, - input uuid, - input wid, - input tmask, - input PC, - input rd, - input wb, - input unit, - input coords, - input lod, - output ready - ); - -endinterface -`endif - - - \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_tex_rsp_if.sv b/hw/rtl/interfaces/VX_tex_rsp_if.sv deleted file mode 100644 index b6fe625a..00000000 --- a/hw/rtl/interfaces/VX_tex_rsp_if.sv +++ /dev/null @@ -1,46 +0,0 @@ -`ifndef VX_TEX_RSP_IF -`define VX_TEX_RSP_IF - -`include "VX_define.vh" - -interface VX_tex_rsp_if (); - - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NW_BITS-1:0] wid; - wire [`NUM_THREADS-1:0] tmask; - wire [31:0] PC; - wire [`NR_BITS-1:0] rd; - wire wb; - wire [`NUM_THREADS-1:0][31:0] data; - wire ready; - - modport master ( - output valid, - output uuid, - output wid, - output tmask, - output PC, - output rd, - output wb, - output data, - input ready - ); - - modport slave ( - input valid, - input uuid, - input wid, - input tmask, - input PC, - input rd, - input wb, - input data, - output ready - ); - -endinterface - -`endif - - diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.sv b/hw/rtl/interfaces/VX_warp_ctl_if.sv index d38d29b1..2180b1fd 100644 --- a/hw/rtl/interfaces/VX_warp_ctl_if.sv +++ b/hw/rtl/interfaces/VX_warp_ctl_if.sv @@ -1,35 +1,46 @@ -`ifndef VX_WARP_CTL_IF -`define VX_WARP_CTL_IF +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. `include "VX_define.vh" -interface VX_warp_ctl_if (); +interface VX_warp_ctl_if import VX_gpu_pkg::*; (); - wire valid; - wire [`NW_BITS-1:0] wid; - gpu_types::gpu_tmc_t tmc; - gpu_types::gpu_wspawn_t wspawn; - gpu_types::gpu_barrier_t barrier; - gpu_types::gpu_split_t split; + wire valid; + wire [`NW_WIDTH-1:0] wid; + tmc_t tmc; + wspawn_t wspawn; + split_t split; + join_t sjoin; + barrier_t barrier; modport master ( output valid, output wid, - output tmc, output wspawn, - output barrier, - output split + output tmc, + output split, + output sjoin, + output barrier ); modport slave ( input valid, input wid, - input tmc, input wspawn, - input barrier, - input split + input tmc, + input split, + input sjoin, + input barrier ); endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_writeback_if.sv b/hw/rtl/interfaces/VX_writeback_if.sv index 6b93a04f..ce6241ef 100644 --- a/hw/rtl/interfaces/VX_writeback_if.sv +++ b/hw/rtl/interfaces/VX_writeback_if.sv @@ -1,44 +1,42 @@ -`ifndef VX_WRITEBACK_IF -`define VX_WRITEBACK_IF +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. `include "VX_define.vh" -interface VX_writeback_if (); +interface VX_writeback_if import VX_gpu_pkg::*; (); - wire valid; - wire [`UUID_BITS-1:0] uuid; - wire [`NUM_THREADS-1:0] tmask; - wire [`NW_BITS-1:0] wid; - wire [31:0] PC; - wire [`NR_BITS-1:0] rd; - wire [`NUM_THREADS-1:0][31:0] data; - wire eop; - wire ready; + typedef struct packed { + logic [`UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [`NUM_THREADS-1:0] tmask; + logic [`XLEN-1:0] PC; + logic [`NR_BITS-1:0] rd; + logic [`NUM_THREADS-1:0][`XLEN-1:0] data; + logic sop; + logic eop; + } data_t; + + logic valid; + data_t data; modport master ( output valid, - output uuid, - output tmask, - output wid, - output PC, - output rd, - output data, - output eop, - input ready + output data ); modport slave ( - input valid, - input uuid, - input tmask, - input wid, - input PC, - input rd, - input data, - input eop, - output ready + input valid, + input data ); endinterface - -`endif diff --git a/hw/rtl/interfaces/VX_wstall_if.sv b/hw/rtl/interfaces/VX_wstall_if.sv deleted file mode 100644 index cff00327..00000000 --- a/hw/rtl/interfaces/VX_wstall_if.sv +++ /dev/null @@ -1,26 +0,0 @@ -`ifndef VX_WSTALL_IF -`define VX_WSTALL_IF - -`include "VX_define.vh" - -interface VX_wstall_if(); - - wire valid; - wire [`NW_BITS-1:0] wid; - wire stalled; - - modport master ( - output valid, - output wid, - output stalled - ); - - modport slave ( - input valid, - input wid, - input stalled - ); - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/libs/VX_allocator.sv b/hw/rtl/libs/VX_allocator.sv new file mode 100644 index 00000000..c7fb7cbc --- /dev/null +++ b/hw/rtl/libs/VX_allocator.sv @@ -0,0 +1,87 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_allocator #( + parameter SIZE = 1, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + + input wire acquire_en, + output wire [ADDRW-1:0] acquire_addr, + + input wire release_en, + input wire [ADDRW-1:0] release_addr, + + output wire empty, + output wire full +); + reg [SIZE-1:0] free_slots, free_slots_n; + reg [ADDRW-1:0] acquire_addr_r; + reg empty_r, full_r; + wire [ADDRW-1:0] free_index; + wire free_valid; + + always @(*) begin + free_slots_n = free_slots; + if (release_en) begin + free_slots_n[release_addr] = 1; + end + if (acquire_en) begin + free_slots_n[acquire_addr_r] = 0; + end + end + + VX_lzc #( + .N (SIZE), + .REVERSE (1) + ) free_slots_sel ( + .data_in (free_slots_n), + .data_out (free_index), + .valid_out (free_valid) + ); + + always @(posedge clk) begin + if (reset) begin + acquire_addr_r <= ADDRW'(1'b0); + free_slots <= {SIZE{1'b1}}; + empty_r <= 1'b1; + full_r <= 1'b0; + end else begin + if (release_en) begin + `ASSERT(0 == free_slots[release_addr], ("%t: releasing invalid addr %d", $time, release_addr)); + end + if (acquire_en) begin + `ASSERT(~full_r, ("%t: allocator is full", $time)); + end + + if (acquire_en || (release_en && full_r)) begin + acquire_addr_r <= free_index; + end + + free_slots <= free_slots_n; + empty_r <= (& free_slots_n); + full_r <= ~free_valid; + end + end + + assign acquire_addr = acquire_addr_r; + assign empty = empty_r; + assign full = full_r; + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_avs_adapter.sv b/hw/rtl/libs/VX_avs_adapter.sv new file mode 100644 index 00000000..779eb45e --- /dev/null +++ b/hw/rtl/libs/VX_avs_adapter.sv @@ -0,0 +1,211 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`TRACING_OFF +module VX_avs_adapter #( + parameter DATA_WIDTH = 1, + parameter ADDR_WIDTH = 1, + parameter BURST_WIDTH = 1, + parameter NUM_BANKS = 1, + parameter TAG_WIDTH = 1, + parameter RD_QUEUE_SIZE = 1, + parameter OUT_REG_REQ = 0, + parameter OUT_REG_RSP = 0 +) ( + input wire clk, + input wire reset, + + // Memory request + input wire mem_req_valid, + input wire mem_req_rw, + input wire [DATA_WIDTH/8-1:0] mem_req_byteen, + input wire [ADDR_WIDTH-1:0] mem_req_addr, + input wire [DATA_WIDTH-1:0] mem_req_data, + input wire [TAG_WIDTH-1:0] mem_req_tag, + output wire mem_req_ready, + + // Memory response + output wire mem_rsp_valid, + output wire [DATA_WIDTH-1:0] mem_rsp_data, + output wire [TAG_WIDTH-1:0] mem_rsp_tag, + input wire mem_rsp_ready, + + // AVS bus + output wire [DATA_WIDTH-1:0] avs_writedata [NUM_BANKS], + input wire [DATA_WIDTH-1:0] avs_readdata [NUM_BANKS], + output wire [ADDR_WIDTH-1:0] avs_address [NUM_BANKS], + input wire avs_waitrequest [NUM_BANKS], + output wire avs_write [NUM_BANKS], + output wire avs_read [NUM_BANKS], + output wire [DATA_WIDTH/8-1:0] avs_byteenable [NUM_BANKS], + output wire [BURST_WIDTH-1:0] avs_burstcount [NUM_BANKS], + input wire avs_readdatavalid [NUM_BANKS] +); + localparam DATA_SIZE = DATA_WIDTH/8; + localparam RD_QUEUE_ADDR_WIDTH = `CLOG2(RD_QUEUE_SIZE+1); + localparam BANK_ADDRW = `LOG2UP(NUM_BANKS); + localparam LOG2_NUM_BANKS = `CLOG2(NUM_BANKS); + localparam BANK_OFFSETW = ADDR_WIDTH - LOG2_NUM_BANKS; + + // Requests handling ////////////////////////////////////////////////////// + + wire [NUM_BANKS-1:0] req_queue_push, req_queue_pop; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] req_queue_tag_out; + wire [NUM_BANKS-1:0] req_queue_going_full; + wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size; + wire [BANK_ADDRW-1:0] req_bank_sel; + wire [BANK_OFFSETW-1:0] req_bank_off; + wire [NUM_BANKS-1:0] bank_req_ready; + + if (NUM_BANKS > 1) begin + assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0]; + end else begin + assign req_bank_sel = '0; + end + + assign req_bank_off = mem_req_addr[ADDR_WIDTH-1:LOG2_NUM_BANKS]; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign req_queue_push[i] = mem_req_valid && ~mem_req_rw && bank_req_ready[i] && (req_bank_sel == i); + end + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + VX_pending_size #( + .SIZE (RD_QUEUE_SIZE) + ) pending_size ( + .clk (clk), + .reset (reset), + .incr (req_queue_push[i]), + .decr (req_queue_pop[i]), + .full (req_queue_going_full[i]), + .size (req_queue_size[i]), + `UNUSED_PIN (empty) + ); + `UNUSED_VAR (req_queue_size) + + VX_fifo_queue #( + .DATAW (TAG_WIDTH), + .DEPTH (RD_QUEUE_SIZE) + ) rd_req_queue ( + .clk (clk), + .reset (reset), + .push (req_queue_push[i]), + .pop (req_queue_pop[i]), + .data_in (mem_req_tag), + .data_out (req_queue_tag_out[i]), + `UNUSED_PIN (empty), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + end + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + wire valid_out; + wire rw_out; + wire [DATA_SIZE-1:0] byteen_out; + wire [BANK_OFFSETW-1:0] addr_out; + wire [DATA_WIDTH-1:0] data_out; + wire ready_out; + + wire valid_out_w = mem_req_valid && ~req_queue_going_full[i] && (req_bank_sel == i); + wire ready_out_w; + + VX_elastic_buffer #( + .DATAW (1 + DATA_SIZE + BANK_OFFSETW + DATA_WIDTH), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG_REQ)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG_REQ)) + ) req_out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_w), + .ready_in (ready_out_w), + .data_in ({mem_req_rw, mem_req_byteen, req_bank_off, mem_req_data}), + .data_out ({rw_out, byteen_out, addr_out, data_out}), + .valid_out (valid_out), + .ready_out (ready_out) + ); + + assign avs_read[i] = valid_out && ~rw_out; + assign avs_write[i] = valid_out && rw_out; + assign avs_address[i] = ADDR_WIDTH'(addr_out); + assign avs_byteenable[i] = byteen_out; + assign avs_writedata[i] = data_out; + assign avs_burstcount[i] = BURST_WIDTH'(1); + assign ready_out = ~avs_waitrequest[i]; + + assign bank_req_ready[i] = ready_out_w && ~req_queue_going_full[i]; + end + + if (NUM_BANKS > 1) begin + assign mem_req_ready = bank_req_ready[req_bank_sel]; + end else begin + assign mem_req_ready = bank_req_ready; + end + + // Responses handling ///////////////////////////////////////////////////// + + wire [NUM_BANKS-1:0] rsp_arb_valid_in; + wire [NUM_BANKS-1:0][DATA_WIDTH+TAG_WIDTH-1:0] rsp_arb_data_in; + wire [NUM_BANKS-1:0] rsp_arb_ready_in; + + wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] rsp_queue_data_out; + wire [NUM_BANKS-1:0] rsp_queue_empty; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + VX_fifo_queue #( + .DATAW (DATA_WIDTH), + .DEPTH (RD_QUEUE_SIZE) + ) rd_rsp_queue ( + .clk (clk), + .reset (reset), + .push (avs_readdatavalid[i]), + .pop (req_queue_pop[i]), + .data_in (avs_readdata[i]), + .data_out (rsp_queue_data_out[i]), + .empty (rsp_queue_empty[i]), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + end + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign rsp_arb_valid_in[i] = !rsp_queue_empty[i]; + assign rsp_arb_data_in[i] = {rsp_queue_data_out[i], req_queue_tag_out[i]}; + assign req_queue_pop[i] = rsp_arb_valid_in[i] && rsp_arb_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_BANKS), + .DATAW (DATA_WIDTH + TAG_WIDTH), + .ARBITER ("R"), + .OUT_REG (OUT_REG_RSP) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_arb_valid_in), + .data_in (rsp_arb_data_in), + .ready_in (rsp_arb_ready_in), + .data_out ({mem_rsp_data, mem_rsp_tag}), + .valid_out (mem_rsp_valid), + .ready_out (mem_rsp_ready), + `UNUSED_PIN (sel_out) + ); + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_axi_adapter.sv b/hw/rtl/libs/VX_axi_adapter.sv index 9e96eedb..967c3af1 100644 --- a/hw/rtl/libs/VX_axi_adapter.sv +++ b/hw/rtl/libs/VX_axi_adapter.sv @@ -1,154 +1,225 @@ -`include "VX_define.vh" +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +`include "VX_platform.vh" + +`TRACING_OFF module VX_axi_adapter #( - parameter VX_DATA_WIDTH = 512, - parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)), - parameter VX_TAG_WIDTH = 8, - parameter AXI_DATA_WIDTH = VX_DATA_WIDTH, - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_TID_WIDTH = VX_TAG_WIDTH, - - parameter VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8), - parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8) + parameter DATA_WIDTH = 512, + parameter ADDR_WIDTH = 32, + parameter TAG_WIDTH = 8, + parameter NUM_BANKS = 1, + parameter AVS_ADDR_WIDTH = (ADDR_WIDTH - `CLOG2(DATA_WIDTH/8)), + parameter OUT_REG_RSP = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Vortex request - input wire mem_req_valid, - input wire mem_req_rw, - input wire [VX_BYTEEN_WIDTH-1:0] mem_req_byteen, - input wire [VX_ADDR_WIDTH-1:0] mem_req_addr, - input wire [VX_DATA_WIDTH-1:0] mem_req_data, - input wire [VX_TAG_WIDTH-1:0] mem_req_tag, + input wire mem_req_valid, + input wire mem_req_rw, + input wire [DATA_WIDTH/8-1:0] mem_req_byteen, + input wire [AVS_ADDR_WIDTH-1:0] mem_req_addr, + input wire [DATA_WIDTH-1:0] mem_req_data, + input wire [TAG_WIDTH-1:0] mem_req_tag, + output wire mem_req_ready, - // Vortex response - input wire mem_rsp_ready, - output wire mem_rsp_valid, - output wire [VX_DATA_WIDTH-1:0] mem_rsp_data, - output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag, - output wire mem_req_ready, + // Vortex response + output wire mem_rsp_valid, + output wire [DATA_WIDTH-1:0] mem_rsp_data, + output wire [TAG_WIDTH-1:0] mem_rsp_tag, + input wire mem_rsp_ready, - // AXI write request address channel - output wire [AXI_TID_WIDTH-1:0] m_axi_awid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, - output wire [7:0] m_axi_awlen, - output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, - output wire m_axi_awlock, - output wire [3:0] m_axi_awcache, - output wire [2:0] m_axi_awprot, - output wire [3:0] m_axi_awqos, - output wire m_axi_awvalid, - input wire m_axi_awready, + // AXI write request address channel + output wire m_axi_awvalid [NUM_BANKS], + input wire m_axi_awready [NUM_BANKS], + output wire [ADDR_WIDTH-1:0] m_axi_awaddr [NUM_BANKS], + output wire [TAG_WIDTH-1:0] m_axi_awid [NUM_BANKS], + output wire [7:0] m_axi_awlen [NUM_BANKS], + output wire [2:0] m_axi_awsize [NUM_BANKS], + output wire [1:0] m_axi_awburst [NUM_BANKS], + output wire [1:0] m_axi_awlock [NUM_BANKS], + output wire [3:0] m_axi_awcache [NUM_BANKS], + output wire [2:0] m_axi_awprot [NUM_BANKS], + output wire [3:0] m_axi_awqos [NUM_BANKS], + output wire [3:0] m_axi_awregion [NUM_BANKS], - // AXI write request data channel - output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, - output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, - output wire m_axi_wlast, - output wire m_axi_wvalid, - input wire m_axi_wready, + // AXI write request data channel + output wire m_axi_wvalid [NUM_BANKS], + input wire m_axi_wready [NUM_BANKS], + output wire [DATA_WIDTH-1:0] m_axi_wdata [NUM_BANKS], + output wire [DATA_WIDTH/8-1:0] m_axi_wstrb [NUM_BANKS], + output wire m_axi_wlast [NUM_BANKS], // AXI write response channel - input wire [AXI_TID_WIDTH-1:0] m_axi_bid, - input wire [1:0] m_axi_bresp, - input wire m_axi_bvalid, - output wire m_axi_bready, + input wire m_axi_bvalid [NUM_BANKS], + output wire m_axi_bready [NUM_BANKS], + input wire [TAG_WIDTH-1:0] m_axi_bid [NUM_BANKS], + input wire [1:0] m_axi_bresp [NUM_BANKS], // AXI read address channel - output wire [AXI_TID_WIDTH-1:0] m_axi_arid, - output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, - output wire [7:0] m_axi_arlen, - output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, - output wire m_axi_arlock, - output wire [3:0] m_axi_arcache, - output wire [2:0] m_axi_arprot, - output wire [3:0] m_axi_arqos, - output wire m_axi_arvalid, - input wire m_axi_arready, + output wire m_axi_arvalid [NUM_BANKS], + input wire m_axi_arready [NUM_BANKS], + output wire [ADDR_WIDTH-1:0] m_axi_araddr [NUM_BANKS], + output wire [TAG_WIDTH-1:0] m_axi_arid [NUM_BANKS], + output wire [7:0] m_axi_arlen [NUM_BANKS], + output wire [2:0] m_axi_arsize [NUM_BANKS], + output wire [1:0] m_axi_arburst [NUM_BANKS], + output wire [1:0] m_axi_arlock [NUM_BANKS], + output wire [3:0] m_axi_arcache [NUM_BANKS], + output wire [2:0] m_axi_arprot [NUM_BANKS], + output wire [3:0] m_axi_arqos [NUM_BANKS], + output wire [3:0] m_axi_arregion [NUM_BANKS], // AXI read response channel - input wire [AXI_TID_WIDTH-1:0] m_axi_rid, - input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, - input wire [1:0] m_axi_rresp, - input wire m_axi_rlast, - input wire m_axi_rvalid, - output wire m_axi_rready -); - localparam AXSIZE = $clog2(VX_DATA_WIDTH/8); + input wire m_axi_rvalid [NUM_BANKS], + output wire m_axi_rready [NUM_BANKS], + input wire [DATA_WIDTH-1:0] m_axi_rdata [NUM_BANKS], + input wire m_axi_rlast [NUM_BANKS], + input wire [TAG_WIDTH-1:0] m_axi_rid [NUM_BANKS], + input wire [1:0] m_axi_rresp [NUM_BANKS] +); + localparam AXSIZE = `CLOG2(DATA_WIDTH/8); + localparam BANK_ADDRW = `LOG2UP(NUM_BANKS); + localparam LOG2_NUM_BANKS = `CLOG2(NUM_BANKS); - `STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter")) - `STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter")) + wire [BANK_ADDRW-1:0] req_bank_sel; - //`UNUSED_VAR () - - reg awvalid_ack; - reg wvalid_ack; + if (NUM_BANKS > 1) begin + assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0]; + end else begin + assign req_bank_sel = '0; + end wire mem_req_fire = mem_req_valid && mem_req_ready; - always @(posedge clk) begin - if (reset) begin - awvalid_ack <= 0; - wvalid_ack <= 0; - end else begin - if (mem_req_fire) begin - awvalid_ack <= 0; - wvalid_ack <= 0; - end else begin - awvalid_ack <= m_axi_awvalid && m_axi_awready; - wvalid_ack <= m_axi_wvalid && m_axi_wready; + reg [NUM_BANKS-1:0] m_axi_aw_ack; + reg [NUM_BANKS-1:0] m_axi_w_ack; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + wire m_axi_aw_fire = m_axi_awvalid[i] && m_axi_awready[i]; + wire m_axi_w_fire = m_axi_wvalid[i] && m_axi_wready[i]; + always @(posedge clk) begin + if (reset) begin + m_axi_aw_ack[i] <= 0; + m_axi_w_ack[i] <= 0; + end else begin + if (mem_req_fire && (req_bank_sel == i)) begin + m_axi_aw_ack[i] <= 0; + m_axi_w_ack[i] <= 0; + end else begin + if (m_axi_aw_fire) + m_axi_aw_ack[i] <= 1; + if (m_axi_w_fire) + m_axi_w_ack[i] <= 1; + end end - end - end + end + end - wire axi_write_ready = (m_axi_awready || awvalid_ack) && (m_axi_wready || wvalid_ack); + wire axi_write_ready [NUM_BANKS]; - // AXI write request address channel - assign m_axi_awvalid = mem_req_valid && mem_req_rw && !awvalid_ack; - assign m_axi_awid = mem_req_tag; - assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; - assign m_axi_awlen = 8'b00000000; - assign m_axi_awsize = 3'(AXSIZE); - assign m_axi_awburst = 2'b00; - assign m_axi_awlock = 1'b0; - assign m_axi_awcache = 4'b0; - assign m_axi_awprot = 3'b0; - assign m_axi_awqos = 4'b0; - - // AXI write request data channel - assign m_axi_wvalid = mem_req_valid && mem_req_rw && !wvalid_ack; - assign m_axi_wdata = mem_req_data; - assign m_axi_wstrb = mem_req_byteen; - assign m_axi_wlast = 1'b1; - - // AXI write response channel - `UNUSED_VAR (m_axi_bid); - `RUNTIME_ASSERT(~m_axi_bvalid || m_axi_bresp == 0, ("%t: *** AXI response error", $time)); - assign m_axi_bready = 1'b1; - - // AXI read request channel - assign m_axi_arvalid = mem_req_valid && !mem_req_rw; - assign m_axi_arid = mem_req_tag; - assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; - assign m_axi_arlen = 8'b00000000; - assign m_axi_arsize = 3'(AXSIZE); - assign m_axi_arburst = 2'b00; - assign m_axi_arlock = 1'b0; - assign m_axi_arcache = 4'b0; - assign m_axi_arprot = 3'b0; - assign m_axi_arqos = 4'b0; - - // AXI read response channel - assign mem_rsp_valid = m_axi_rvalid; - assign mem_rsp_tag = m_axi_rid; - assign mem_rsp_data = m_axi_rdata; - `RUNTIME_ASSERT(~m_axi_rvalid || m_axi_rresp == 0, ("%t: *** AXI response error", $time)); - `UNUSED_VAR (m_axi_rlast); - assign m_axi_rready = mem_rsp_ready; + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign axi_write_ready[i] = (m_axi_awready[i] || m_axi_aw_ack[i]) + && (m_axi_wready[i] || m_axi_w_ack[i]); + end // Vortex request ack - assign mem_req_ready = mem_req_rw ? axi_write_ready : m_axi_arready; + if (NUM_BANKS > 1) begin + assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel]; + end else begin + assign mem_req_ready = mem_req_rw ? axi_write_ready[0] : m_axi_arready[0]; + end -endmodule \ No newline at end of file + // AXI write request address channel + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign m_axi_awvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_aw_ack[i]; + assign m_axi_awaddr[i] = (ADDR_WIDTH'(mem_req_addr) >> LOG2_NUM_BANKS) << AXSIZE; + assign m_axi_awid[i] = mem_req_tag; + assign m_axi_awlen[i] = 8'b00000000; + assign m_axi_awsize[i] = 3'(AXSIZE); + assign m_axi_awburst[i] = 2'b00; + assign m_axi_awlock[i] = 2'b00; + assign m_axi_awcache[i] = 4'b0000; + assign m_axi_awprot[i] = 3'b000; + assign m_axi_awqos[i] = 4'b0000; + assign m_axi_awregion[i]= 4'b0000; + end + + // AXI write request data channel + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign m_axi_wvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_w_ack[i]; + assign m_axi_wdata[i] = mem_req_data; + assign m_axi_wstrb[i] = mem_req_byteen; + assign m_axi_wlast[i] = 1'b1; + end + + // AXI write response channel (ignore) + for (genvar i = 0; i < NUM_BANKS; ++i) begin + `UNUSED_VAR (m_axi_bvalid[i]) + `UNUSED_VAR (m_axi_bid[i]) + `UNUSED_VAR (m_axi_bresp[i]) + assign m_axi_bready[i] = 1'b1; + `RUNTIME_ASSERT(~m_axi_bvalid[i] || m_axi_bresp[i] == 0, ("%t: *** AXI response error", $time)); + end + + // AXI read request channel + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign m_axi_arvalid[i] = mem_req_valid && ~mem_req_rw && (req_bank_sel == i); + assign m_axi_araddr[i] = (ADDR_WIDTH'(mem_req_addr) >> LOG2_NUM_BANKS) << AXSIZE; + assign m_axi_arid[i] = mem_req_tag; + assign m_axi_arlen[i] = 8'b00000000; + assign m_axi_arsize[i] = 3'(AXSIZE); + assign m_axi_arburst[i] = 2'b00; + assign m_axi_arlock[i] = 2'b00; + assign m_axi_arcache[i] = 4'b0000; + assign m_axi_arprot[i] = 3'b000; + assign m_axi_arqos[i] = 4'b0000; + assign m_axi_arregion[i]= 4'b0000; + end + + // AXI read response channel + + wire [NUM_BANKS-1:0] rsp_arb_valid_in; + wire [NUM_BANKS-1:0][DATA_WIDTH+TAG_WIDTH-1:0] rsp_arb_data_in; + wire [NUM_BANKS-1:0] rsp_arb_ready_in; + + `UNUSED_VAR (m_axi_rlast) + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign rsp_arb_valid_in[i] = m_axi_rvalid[i]; + assign rsp_arb_data_in[i] = {m_axi_rdata[i], m_axi_rid[i]}; + assign m_axi_rready[i] = rsp_arb_ready_in[i]; + `RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rlast[i] == 1, ("%t: *** AXI response error", $time)); + `RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rresp[i] == 0, ("%t: *** AXI response error", $time)); + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_BANKS), + .DATAW (DATA_WIDTH + TAG_WIDTH), + .ARBITER ("R"), + .OUT_REG (OUT_REG_RSP) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_arb_valid_in), + .data_in (rsp_arb_data_in), + .ready_in (rsp_arb_ready_in), + .data_out ({mem_rsp_data, mem_rsp_tag}), + .valid_out (mem_rsp_valid), + .ready_out (mem_rsp_ready), + `UNUSED_PIN (sel_out) + ); + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_bits_insert.sv b/hw/rtl/libs/VX_bits_insert.sv index 63b09513..d08534b8 100644 --- a/hw/rtl/libs/VX_bits_insert.sv +++ b/hw/rtl/libs/VX_bits_insert.sv @@ -1,20 +1,40 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" +`TRACING_OFF module VX_bits_insert #( parameter N = 1, parameter S = 1, parameter POS = 0 ) ( - input wire [N-1:0] data_in, - input wire [S-1:0] sel_in, - output wire [N+S-1:0] data_out + input wire [N-1:0] data_in, + input wire [`UP(S)-1:0] sel_in, + output wire [N+S-1:0] data_out ); - if (POS == 0) begin - assign data_out = {data_in, sel_in}; - end else if (POS == N) begin - assign data_out = {sel_in, data_in}; + if (S == 0) begin + `UNUSED_VAR (sel_in) + assign data_out = data_in; end else begin - assign data_out = {data_in[N-1:POS], sel_in, data_in[POS-1:0]}; - end + if (POS == 0) begin + assign data_out = {data_in, sel_in}; + end else if (POS == N) begin + assign data_out = {sel_in, data_in}; + end else begin + assign data_out = {data_in[N-1:POS], sel_in, data_in[POS-1:0]}; + end + end -endmodule \ No newline at end of file +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_bits_remove.sv b/hw/rtl/libs/VX_bits_remove.sv index 00ba5e75..bc2f60a7 100644 --- a/hw/rtl/libs/VX_bits_remove.sv +++ b/hw/rtl/libs/VX_bits_remove.sv @@ -1,21 +1,38 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" +`TRACING_OFF module VX_bits_remove #( - parameter N = 1, + parameter N = 2, parameter S = 1, parameter POS = 0 ) ( - input wire [N-1:0] data_in, + input wire [N-1:0] data_in, output wire [N-S-1:0] data_out ); + `STATIC_ASSERT (((0 == S) || ((POS + S) <= N)), ("invalid parameter")) + + if (POS == 0 || S == 0) begin + assign data_out = data_in[N-1:S]; + end else if ((POS + S) < N) begin + assign data_out = {data_in[N-1:(POS+S)], data_in[POS-1:0]}; + end else begin + assign data_out = data_in[POS-1:0]; + end + `UNUSED_VAR (data_in) - if (POS == 0) begin - assign data_out = data_in[N-1:S]; - end else if (POS == N) begin - assign data_out = data_in[N-S-1:0]; - end else begin - assign data_out = {data_in[N-1:(POS+S)], data_in[POS-1:0]}; - end - -endmodule \ No newline at end of file +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_bypass_buffer.sv b/hw/rtl/libs/VX_bypass_buffer.sv index efb5517f..7e723a45 100644 --- a/hw/rtl/libs/VX_bypass_buffer.sv +++ b/hw/rtl/libs/VX_bypass_buffer.sv @@ -1,5 +1,19 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" +`TRACING_OFF module VX_bypass_buffer #( parameter DATAW = 1, parameter PASSTHRU = 0 @@ -13,7 +27,7 @@ module VX_bypass_buffer #( input wire ready_out, output wire valid_out ); - if (PASSTHRU) begin + if (PASSTHRU != 0) begin `UNUSED_VAR (clk) `UNUSED_VAR (reset) assign ready_in = ready_out; @@ -46,4 +60,5 @@ module VX_bypass_buffer #( assign valid_out = valid_in || buffer_valid; end -endmodule \ No newline at end of file +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_cyclic_arbiter.sv b/hw/rtl/libs/VX_cyclic_arbiter.sv new file mode 100644 index 00000000..cd7d91f9 --- /dev/null +++ b/hw/rtl/libs/VX_cyclic_arbiter.sv @@ -0,0 +1,73 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_cyclic_arbiter #( + parameter NUM_REQS = 1, + parameter LOCK_ENABLE = 0, + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) +) ( + input wire clk, + input wire reset, + input wire [NUM_REQS-1:0] requests, + input wire unlock, + output wire [LOG_NUM_REQS-1:0] grant_index, + output wire [NUM_REQS-1:0] grant_onehot, + output wire grant_valid +); + `UNUSED_PARAM (LOCK_ENABLE) + `UNUSED_VAR (unlock) + + if (NUM_REQS == 1) begin + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + assign grant_index = '0; + assign grant_onehot = requests; + assign grant_valid = requests[0]; + + end else begin + + localparam IS_POW2 = (1 << LOG_NUM_REQS) == NUM_REQS; + + reg [LOG_NUM_REQS-1:0] grant_index_r; + + always @(posedge clk) begin + if (reset) begin + grant_index_r <= '0; + end else begin + if (!IS_POW2 && grant_index_r == LOG_NUM_REQS'(NUM_REQS-1)) begin + grant_index_r <= '0; + end else begin + grant_index_r <= grant_index_r + LOG_NUM_REQS'(1); + end + end + end + + reg [NUM_REQS-1:0] grant_onehot_r; + always @(*) begin + grant_onehot_r = '0; + grant_onehot_r[grant_index_r] = 1'b1; + end + + assign grant_index = grant_index_r; + assign grant_onehot = grant_onehot_r; + assign grant_valid = requests[grant_index_r]; + + end + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_divider.sv b/hw/rtl/libs/VX_divider.sv index d30c7993..551940da 100644 --- a/hw/rtl/libs/VX_divider.sv +++ b/hw/rtl/libs/VX_divider.sv @@ -1,27 +1,40 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_divider #( - parameter WIDTHN = 1, - parameter WIDTHD = 1, - parameter WIDTHQ = 1, - parameter WIDTHR = 1, - parameter NSIGNED = 0, - parameter DSIGNED = 0, - parameter LATENCY = 0 + parameter N_WIDTH = 1, + parameter D_WIDTH = 1, + parameter Q_WIDTH = 1, + parameter R_WIDTH = 1, + parameter N_SIGNED = 0, + parameter D_SIGNED = 0, + parameter LATENCY = 0 ) ( - input wire clk, - input wire enable, - input wire [WIDTHN-1:0] numer, - input wire [WIDTHD-1:0] denom, - output wire [WIDTHQ-1:0] quotient, - output wire [WIDTHR-1:0] remainder + input wire clk, + input wire enable, + input wire [N_WIDTH-1:0] numer, + input wire [D_WIDTH-1:0] denom, + output wire [Q_WIDTH-1:0] quotient, + output wire [R_WIDTH-1:0] remainder ); `ifdef QUARTUS - wire [WIDTHN-1:0] quotient_unqual; - wire [WIDTHD-1:0] remainder_unqual; + wire [N_WIDTH-1:0] quotient_unqual; + wire [D_WIDTH-1:0] remainder_unqual; lpm_divide divide ( .clock (clk), @@ -34,32 +47,32 @@ module VX_divider #( defparam divide.lpm_type = "LPM_DIVIDE", - divide.lpm_widthn = WIDTHN, - divide.lpm_widthd = WIDTHD, - divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", - divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_widthn = N_WIDTH, + divide.lpm_widthd = D_WIDTH, + divide.lpm_nrepresentation = N_SIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_drepresentation = D_SIGNED ? "SIGNED" : "UNSIGNED", divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", divide.lpm_pipeline = LATENCY; - assign quotient = quotient_unqual [WIDTHQ-1:0]; - assign remainder = remainder_unqual [WIDTHR-1:0]; + assign quotient = quotient_unqual [Q_WIDTH-1:0]; + assign remainder = remainder_unqual [R_WIDTH-1:0]; `else - reg [WIDTHN-1:0] quotient_unqual; - reg [WIDTHD-1:0] remainder_unqual; + reg [N_WIDTH-1:0] quotient_unqual; + reg [D_WIDTH-1:0] remainder_unqual; always @(*) begin begin - if (NSIGNED && DSIGNED) begin + if (N_SIGNED && D_SIGNED) begin quotient_unqual = $signed(numer) / $signed(denom); remainder_unqual = $signed(numer) % $signed(denom); end - else if (NSIGNED && !DSIGNED) begin + else if (N_SIGNED && !D_SIGNED) begin quotient_unqual = $signed(numer) / denom; remainder_unqual = $signed(numer) % denom; end - else if (!NSIGNED && DSIGNED) begin + else if (!N_SIGNED && D_SIGNED) begin quotient_unqual = numer / $signed(denom); remainder_unqual = numer % $signed(denom); end @@ -71,13 +84,13 @@ module VX_divider #( end if (LATENCY == 0) begin - assign quotient = quotient_unqual [WIDTHQ-1:0]; - assign remainder = remainder_unqual [WIDTHR-1:0]; + assign quotient = quotient_unqual [Q_WIDTH-1:0]; + assign remainder = remainder_unqual [R_WIDTH-1:0]; end else begin - reg [WIDTHN-1:0] quotient_pipe [LATENCY-1:0]; - reg [WIDTHD-1:0] remainder_pipe [LATENCY-1:0]; + reg [N_WIDTH-1:0] quotient_pipe [LATENCY-1:0]; + reg [D_WIDTH-1:0] remainder_pipe [LATENCY-1:0]; - for (genvar i = 0; i < LATENCY; i++) begin + for (genvar i = 0; i < LATENCY; ++i) begin always @(posedge clk) begin if (enable) begin quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1]; @@ -86,11 +99,11 @@ module VX_divider #( end end - assign quotient = quotient_pipe[LATENCY-1][WIDTHQ-1:0]; - assign remainder = remainder_pipe[LATENCY-1][WIDTHR-1:0]; + assign quotient = quotient_pipe[LATENCY-1][Q_WIDTH-1:0]; + assign remainder = remainder_pipe[LATENCY-1][R_WIDTH-1:0]; end `endif endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_dp_ram.sv b/hw/rtl/libs/VX_dp_ram.sv index 7b39246f..8ecfd837 100644 --- a/hw/rtl/libs/VX_dp_ram.sv +++ b/hw/rtl/libs/VX_dp_ram.sv @@ -1,252 +1,314 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_dp_ram #( parameter DATAW = 1, parameter SIZE = 1, - parameter BYTEENW = 1, + parameter WRENW = 1, parameter OUT_REG = 0, parameter NO_RWCHECK = 0, - parameter LUTRAM = 0, - parameter ADDRW = $clog2(SIZE), + parameter LUTRAM = 0, parameter INIT_ENABLE = 0, parameter INIT_FILE = "", - parameter [DATAW-1:0] INIT_VALUE = 0 + parameter [DATAW-1:0] INIT_VALUE = 0, + parameter ADDRW = `LOG2UP(SIZE) ) ( input wire clk, - input wire [BYTEENW-1:0] wren, + input wire read, + input wire write, + input wire [WRENW-1:0] wren, input wire [ADDRW-1:0] waddr, input wire [DATAW-1:0] wdata, input wire [ADDRW-1:0] raddr, output wire [DATAW-1:0] rdata ); + localparam WSELW = DATAW / WRENW; + `STATIC_ASSERT((WRENW * WSELW == DATAW), ("invalid parameter")) - `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) - -`define RAM_INITIALIZATION \ - if (INIT_ENABLE) begin \ - if (INIT_FILE != "") begin \ - initial $readmemh(INIT_FILE, ram); \ - end else begin \ - initial \ - for (integer i = 0; i < SIZE; ++i)\ - ram[i] = INIT_VALUE; \ - end \ +`define RAM_INITIALIZATION \ + if (INIT_ENABLE != 0) begin \ + if (INIT_FILE != "") begin \ + initial $readmemh(INIT_FILE, ram); \ + end else begin \ + initial \ + for (integer i = 0; i < SIZE; ++i) \ + ram[i] = INIT_VALUE; \ + end \ end + + `UNUSED_VAR (read) `ifdef SYNTHESIS - if (LUTRAM) begin - if (OUT_REG) begin - reg [DATAW-1:0] rdata_r; - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - + if (WRENW > 1) begin + `ifdef QUARTUS + if (LUTRAM != 0) begin + if (OUT_REG != 0) begin + reg [DATAW-1:0] rdata_r; + `USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0]; `RAM_INITIALIZATION - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[waddr][i] <= wdata[i * 8 +: 8]; - end - rdata_r <= ram[raddr]; - end - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[waddr] <= wdata; - rdata_r <= ram[raddr]; - end - end - assign rdata = rdata_r; - end else begin - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[waddr][i] <= wdata[i * 8 +: 8]; - end - end - assign rdata = ram[raddr]; - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[waddr] <= wdata; - end - assign rdata = ram[raddr]; - end - end - end else begin - if (OUT_REG) begin - reg [DATAW-1:0] rdata_r; - - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[waddr][i] <= wdata[i * 8 +: 8]; - end - rdata_r <= ram[raddr]; - end - end else begin - reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[waddr] <= wdata; - rdata_r <= ram[raddr]; - end - end - assign rdata = rdata_r; - end else begin - if (NO_RWCHECK) begin - if (BYTEENW > 1) begin - `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin if (wren[i]) - ram[waddr][i] <= wdata[i * 8 +: 8]; + ram[waddr][i] <= wdata[i * WSELW +: WSELW]; + end + end + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + `USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * WSELW +: WSELW]; + end + end + end + assign rdata = ram[raddr]; + end + end else begin + if (OUT_REG != 0) begin + reg [DATAW-1:0] rdata_r; + reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * WSELW +: WSELW]; + end + end + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + if (NO_RWCHECK != 0) begin + `NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * WSELW +: WSELW]; + end end end assign rdata = ram[raddr]; end else begin - `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; - + reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0]; `RAM_INITIALIZATION - always @(posedge clk) begin - if (wren) - ram[waddr] <= wdata; + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i] <= wdata[i * WSELW +: WSELW]; + end + end end assign rdata = ram[raddr]; end - end else begin - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin + end + end + `else + // default synthesis + if (LUTRAM != 0) begin + `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + if (OUT_REG != 0) begin + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin if (wren[i]) - ram[waddr][i] <= wdata[i * 8 +: 8]; + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; + end + end + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; + end + end + end + assign rdata = ram[raddr]; + end + end else begin + if (OUT_REG != 0) begin + reg [DATAW-1:0] ram [SIZE-1:0]; + reg [DATAW-1:0] rdata_r; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; + end + end + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + if (NO_RWCHECK != 0) begin + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; + end end end assign rdata = ram[raddr]; end else begin reg [DATAW-1:0] ram [SIZE-1:0]; - `RAM_INITIALIZATION - always @(posedge clk) begin - if (wren) - ram[waddr] <= wdata; + if (write) begin + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; + end + end end assign rdata = ram[raddr]; - end + end end end - end -`else - if (OUT_REG) begin - reg [DATAW-1:0] rdata_r; - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - + `endif + end else begin + // (WRENW == 1) + if (LUTRAM != 0) begin + `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[waddr][i] <= wdata[i * 8 +: 8]; + if (OUT_REG != 0) begin + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (write) begin + ram[waddr] <= wdata; + end + if (read) begin + rdata_r <= ram[raddr]; + end end - rdata_r <= ram[raddr]; + assign rdata = rdata_r; + end else begin + always @(posedge clk) begin + if (write) begin + ram[waddr] <= wdata; + end + end + assign rdata = ram[raddr]; end end else begin - reg [DATAW-1:0] ram [SIZE-1:0]; + if (OUT_REG != 0) begin + reg [DATAW-1:0] ram [SIZE-1:0]; + reg [DATAW-1:0] rdata_r; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + ram[waddr] <= wdata; + end + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin + if (NO_RWCHECK != 0) begin + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + ram[waddr] <= wdata; + end + end + assign rdata = ram[raddr]; + end else begin + reg [DATAW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION + always @(posedge clk) begin + if (write) begin + ram[waddr] <= wdata; + end + end + assign rdata = ram[raddr]; + end + end + end + end +`else + // RAM emulation + reg [DATAW-1:0] ram [SIZE-1:0]; + `RAM_INITIALIZATION - `RAM_INITIALIZATION + wire [DATAW-1:0] ram_n; + for (genvar i = 0; i < WRENW; ++i) begin + assign ram_n[i * WSELW +: WSELW] = ((WRENW == 1) | wren[i]) ? wdata[i * WSELW +: WSELW] : ram[waddr][i * WSELW +: WSELW]; + end - always @(posedge clk) begin - if (wren) - ram[waddr] <= wdata; + if (OUT_REG != 0) begin + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (write) begin + ram[waddr] <= ram_n; + end + if (read) begin rdata_r <= ram[raddr]; end end assign rdata = rdata_r; - end else begin - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - reg [DATAW-1:0] prev_data; - reg [ADDRW-1:0] prev_waddr; - reg prev_write; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[waddr][i] <= wdata[i * 8 +: 8]; - end - prev_write <= (| wren); - prev_data <= ram[waddr]; - prev_waddr <= waddr; - end - - if (LUTRAM || !NO_RWCHECK) begin - `UNUSED_VAR (prev_write) - `UNUSED_VAR (prev_data) - `UNUSED_VAR (prev_waddr) - assign rdata = ram[raddr]; - end else begin - assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; + end else begin + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_waddr; + reg prev_write; + always @(posedge clk) begin + if (write) begin + ram[waddr] <= ram_n; end + prev_write <= (| wren); + prev_data <= ram[waddr]; + prev_waddr <= waddr; + end + if (LUTRAM || !NO_RWCHECK) begin + `UNUSED_VAR (prev_write) + `UNUSED_VAR (prev_data) + `UNUSED_VAR (prev_waddr) + assign rdata = ram[raddr]; end else begin - reg [DATAW-1:0] ram [SIZE-1:0]; - reg [DATAW-1:0] prev_data; - reg [ADDRW-1:0] prev_waddr; - reg prev_write; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[waddr] <= wdata; - prev_write <= wren; - prev_data <= ram[waddr]; - prev_waddr <= waddr; - end - if (LUTRAM || !NO_RWCHECK) begin - `UNUSED_VAR (prev_write) - `UNUSED_VAR (prev_data) - `UNUSED_VAR (prev_waddr) - assign rdata = ram[raddr]; - end else begin - assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; - end + assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; end end `endif endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_elastic_adapter.sv b/hw/rtl/libs/VX_elastic_adapter.sv new file mode 100644 index 00000000..8a24a808 --- /dev/null +++ b/hw/rtl/libs/VX_elastic_adapter.sv @@ -0,0 +1,53 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_elastic_adapter ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire ready_out, + output wire valid_out, + + input wire busy, + output wire strobe +); + wire push = valid_in && ready_in; + wire pop = valid_out && ready_out; + + reg loaded; + + always @(posedge clk) begin + if (reset) begin + loaded <= 0; + end else begin + if (push) begin + loaded <= 1; + end + if (pop) begin + loaded <= 0; + end + end + end + + assign ready_in = ~loaded; + assign valid_out = loaded && ~busy; + assign strobe = push; + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_elastic_buffer.sv b/hw/rtl/libs/VX_elastic_buffer.sv index 4eb5dc90..8cd8a3ab 100644 --- a/hw/rtl/libs/VX_elastic_buffer.sv +++ b/hw/rtl/libs/VX_elastic_buffer.sv @@ -1,9 +1,22 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_elastic_buffer #( parameter DATAW = 1, - parameter SIZE = 2, + parameter SIZE = 1, parameter OUT_REG = 0, parameter LUTRAM = 0 ) ( @@ -18,8 +31,6 @@ module VX_elastic_buffer #( input wire ready_out, output wire valid_out ); - `STATIC_ASSERT (SIZE != 1, ("invalid value")) - if (SIZE == 0) begin `UNUSED_VAR (clk) @@ -29,19 +40,36 @@ module VX_elastic_buffer #( assign data_out = data_in; assign ready_in = ready_out; + end else if (SIZE == 1) begin + + wire stall = valid_out && ~ready_out; + + VX_pipe_register #( + .DATAW (1 + DATAW), + .RESETW (1) + ) pipe_register ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in, data_in}), + .data_out ({valid_out, data_out}) + ); + + assign ready_in = ~stall; + end else if (SIZE == 2) begin VX_skid_buffer #( .DATAW (DATAW), .OUT_REG (OUT_REG) - ) queue ( + ) skid_buffer ( .clk (clk), .reset (reset), - .valid_in (valid_in), - .data_in (data_in), - .ready_in (ready_in), - .valid_out (valid_out), + .valid_in (valid_in), + .ready_in (ready_in), + .data_in (data_in), .data_out (data_out), + .valid_out (valid_out), .ready_out (ready_out) ); @@ -49,21 +77,24 @@ module VX_elastic_buffer #( wire empty, full; + wire [DATAW-1:0] data_out_t; + wire ready_out_t; + wire push = valid_in && ready_in; - wire pop = valid_out && ready_out; + wire pop = ~empty && ready_out_t; VX_fifo_queue #( .DATAW (DATAW), - .SIZE (SIZE), - .OUT_REG (OUT_REG), + .DEPTH (SIZE), + .OUT_REG (OUT_REG == 1), .LUTRAM (LUTRAM) - ) queue ( + ) fifo_queue ( .clk (clk), .reset (reset), .push (push), .pop (pop), .data_in(data_in), - .data_out(data_out), + .data_out(data_out_t), .empty (empty), .full (full), `UNUSED_PIN (alm_empty), @@ -71,10 +102,23 @@ module VX_elastic_buffer #( `UNUSED_PIN (size) ); - assign ready_in = ~full; - assign valid_out = ~empty; + assign ready_in = ~full; + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (OUT_REG == 2) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (~empty), + .ready_in (ready_out_t), + .data_in (data_out_t), + .data_out (data_out), + .valid_out (valid_out), + .ready_out (ready_out) + ); end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_fair_arbiter.sv b/hw/rtl/libs/VX_fair_arbiter.sv index 0e24efd5..c1b1a4b7 100644 --- a/hw/rtl/libs/VX_fair_arbiter.sv +++ b/hw/rtl/libs/VX_fair_arbiter.sv @@ -1,60 +1,72 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_fair_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, - parameter LOG_NUM_REQS = $clog2(NUM_REQS) + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) ) ( input wire clk, input wire reset, - input wire enable, + input wire unlock, input wire [NUM_REQS-1:0] requests, output wire [LOG_NUM_REQS-1:0] grant_index, output wire [NUM_REQS-1:0] grant_onehot, output wire grant_valid - ); - +); if (NUM_REQS == 1) begin `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - assign grant_index = 0; + `UNUSED_VAR (reset) + `UNUSED_VAR (unlock) + + assign grant_index = '0; assign grant_onehot = requests; assign grant_valid = requests[0]; end else begin reg [NUM_REQS-1:0] buffer; - reg use_buffer; - wire [NUM_REQS-1:0] requests_qual = use_buffer ? buffer : requests; - wire [NUM_REQS-1:0] buffer_n = requests_qual & ~grant_onehot; + wire [NUM_REQS-1:0] buffer_qual = buffer & requests; + wire [NUM_REQS-1:0] requests_qual = (| buffer) ? buffer_qual : requests; + wire [NUM_REQS-1:0] buffer_n = requests_qual & ~grant_onehot; always @(posedge clk) begin if (reset) begin - use_buffer <= 0; - end else if (!LOCK_ENABLE || enable) begin - use_buffer <= (buffer_n != 0); - end - if (!LOCK_ENABLE || enable) begin + buffer <= '0; + end else if (!LOCK_ENABLE || unlock) begin buffer <= buffer_n; end end - VX_fixed_arbiter #( + VX_priority_arbiter #( .NUM_REQS (NUM_REQS), .LOCK_ENABLE (LOCK_ENABLE) - ) fixed_arbiter ( + ) priority_arbiter ( .clk (clk), .reset (reset), - .enable (enable), + .unlock (unlock), .requests (requests_qual), .grant_index (grant_index), .grant_onehot (grant_onehot), .grant_valid (grant_valid) ); + end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_fifo_queue.sv b/hw/rtl/libs/VX_fifo_queue.sv index 42f36885..78a2785c 100644 --- a/hw/rtl/libs/VX_fifo_queue.sv +++ b/hw/rtl/libs/VX_fifo_queue.sv @@ -1,15 +1,27 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_fifo_queue #( parameter DATAW = 1, - parameter SIZE = 2, - parameter ALM_FULL = (SIZE - 1), + parameter DEPTH = 2, + parameter ALM_FULL = (DEPTH - 1), parameter ALM_EMPTY = 1, - parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), parameter OUT_REG = 0, - parameter LUTRAM = 1 + parameter LUTRAM = 1, + parameter SIZEW = `CLOG2(DEPTH+1) ) ( input wire clk, input wire reset, @@ -23,26 +35,33 @@ module VX_fifo_queue #( output wire alm_full, output wire [SIZEW-1:0] size ); - `STATIC_ASSERT(`ISPOW2(SIZE), ("must be 0 or power of 2!")) - if (SIZE == 1) begin + localparam ADDRW = `CLOG2(DEPTH); + + `STATIC_ASSERT(ALM_FULL > 0, ("alm_full must be greater than 0!")) + `STATIC_ASSERT(ALM_FULL < DEPTH, ("alm_full must be smaller than size!")) + `STATIC_ASSERT(ALM_EMPTY > 0, ("alm_empty must be greater than 0!")) + `STATIC_ASSERT(ALM_EMPTY < DEPTH, ("alm_empty must be smaller than size!")) + `STATIC_ASSERT(`ISPOW2(DEPTH), ("size must be a power of 2!")) + + if (DEPTH == 1) begin reg [DATAW-1:0] head_r; reg size_r; always @(posedge clk) begin if (reset) begin - head_r <= 0; - size_r <= 0; + head_r <= '0; + size_r <= '0; end else begin - `ASSERT(!push || !full, ("runtime error")); - `ASSERT(!pop || !empty, ("runtime error")); + `ASSERT(~push || ~full, ("runtime error: writing to a full queue")); + `ASSERT(~pop || ~empty, ("runtime error: reading an empty queue")); if (push) begin - if (!pop) begin + if (~pop) begin size_r <= 1; end end else if (pop) begin - size_r <= 0; + size_r <= '0; end if (push) begin head_r <= data_in; @@ -62,6 +81,7 @@ module VX_fifo_queue #( reg empty_r, alm_empty_r; reg full_r, alm_full_r; reg [ADDRW-1:0] used_r; + wire [ADDRW-1:0] used_n; always @(posedge clk) begin if (reset) begin @@ -69,43 +89,40 @@ module VX_fifo_queue #( alm_empty_r <= 1; full_r <= 0; alm_full_r <= 0; - used_r <= 0; + used_r <= '0; end else begin - `ASSERT(!push || !full, ("runtime error")); - `ASSERT(!pop || !empty, ("runtime error")); + `ASSERT(~(push && ~pop) || ~full, ("runtime error: incrementing full queue")); + `ASSERT(~(pop && ~push) || ~empty, ("runtime error: decrementing empty queue")); if (push) begin - if (!pop) begin + if (~pop) begin empty_r <= 0; if (used_r == ADDRW'(ALM_EMPTY)) alm_empty_r <= 0; - if (used_r == ADDRW'(SIZE-1)) + if (used_r == ADDRW'(DEPTH-1)) full_r <= 1; if (used_r == ADDRW'(ALM_FULL-1)) alm_full_r <= 1; end end else if (pop) begin - full_r <= 0; + full_r <= 0; if (used_r == ADDRW'(ALM_FULL)) alm_full_r <= 0; if (used_r == ADDRW'(1)) empty_r <= 1; if (used_r == ADDRW'(ALM_EMPTY+1)) alm_empty_r <= 1; - end - if (SIZE > 2) begin - used_r <= used_r + ADDRW'($signed(2'(push) - 2'(pop))); - end else begin - // (SIZE == 2); - used_r[0] <= used_r[0] ^ (push ^ pop); end + used_r <= used_n; end end - if (SIZE == 2) begin + if (DEPTH == 2) begin + + assign used_n = used_r ^ (push ^ pop); if (0 == OUT_REG) begin - reg [DATAW-1:0] shift_reg [1:0]; + reg [1:0][DATAW-1:0] shift_reg; always @(posedge clk) begin if (push) begin @@ -137,6 +154,8 @@ module VX_fifo_queue #( end end else begin + + assign used_n = $signed(used_r) + ADDRW'($signed(2'(push) - 2'(pop))); if (0 == OUT_REG) begin @@ -145,8 +164,8 @@ module VX_fifo_queue #( always @(posedge clk) begin if (reset) begin - rd_ptr_r <= 0; - wr_ptr_r <= 0; + rd_ptr_r <= '0; + wr_ptr_r <= '0; end else begin wr_ptr_r <= wr_ptr_r + ADDRW'(push); rd_ptr_r <= rd_ptr_r + ADDRW'(pop); @@ -154,13 +173,14 @@ module VX_fifo_queue #( end VX_dp_ram #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUT_REG (0), - .LUTRAM (LUTRAM) + .DATAW (DATAW), + .SIZE (DEPTH), + .LUTRAM (LUTRAM) ) dp_ram ( .clk(clk), - .wren (push), + .read (1'b1), + .write (push), + `UNUSED_PIN (wren), .waddr (wr_ptr_r), .wdata (data_in), .raddr (rd_ptr_r), @@ -177,8 +197,8 @@ module VX_fifo_queue #( always @(posedge clk) begin if (reset) begin - wr_ptr_r <= 0; - rd_ptr_r <= 0; + wr_ptr_r <= '0; + rd_ptr_r <= '0; rd_ptr_n_r <= 1; end else begin if (push) begin @@ -186,23 +206,31 @@ module VX_fifo_queue #( end if (pop) begin rd_ptr_r <= rd_ptr_n_r; - if (SIZE > 2) begin + if (DEPTH > 2) begin rd_ptr_n_r <= rd_ptr_r + ADDRW'(2); - end else begin // (SIZE == 2); + end else begin // (DEPTH == 2); rd_ptr_n_r <= ~rd_ptr_n_r; end end end end + wire going_empty; + if (ALM_EMPTY == 1) begin + assign going_empty = alm_empty_r; + end else begin + assign going_empty = (used_r == ADDRW'(1)); + end + VX_dp_ram #( - .DATAW (DATAW), - .SIZE (SIZE), - .OUT_REG (0), - .LUTRAM (LUTRAM) + .DATAW (DATAW), + .SIZE (DEPTH), + .LUTRAM (LUTRAM) ) dp_ram ( .clk (clk), - .wren (push), + .read (1'b1), + .write (push), + `UNUSED_PIN (wren), .waddr (wr_ptr_r), .wdata (data_in), .raddr (rd_ptr_n_r), @@ -210,7 +238,7 @@ module VX_fifo_queue #( ); always @(posedge clk) begin - if (push && (empty_r || ((used_r == ADDRW'(1)) && pop))) begin + if (push && (empty_r || (going_empty && pop))) begin dout_r <= data_in; end else if (pop) begin dout_r <= dout; @@ -229,4 +257,4 @@ module VX_fifo_queue #( end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_find_first.sv b/hw/rtl/libs/VX_find_first.sv index 048a803c..f0697110 100644 --- a/hw/rtl/libs/VX_find_first.sv +++ b/hw/rtl/libs/VX_find_first.sv @@ -1,19 +1,32 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_find_first #( parameter N = 1, parameter DATAW = 1, - parameter REVERSE = 0, - parameter LOGN = $clog2(N) + parameter REVERSE = 0 ) ( - input wire [N-1:0][DATAW-1:0] data_i, - input wire [N-1:0] valid_i, - output wire [DATAW-1:0] data_o, - output wire valid_o + input wire [N-1:0][DATAW-1:0] data_in, + input wire [N-1:0] valid_in, + output wire [DATAW-1:0] data_out, + output wire valid_out ); - localparam TL = (1 << LOGN) - 1; - localparam TN = (1 << (LOGN+1)) - 1; + localparam LOGN = `CLOG2(N); + localparam TL = (1 << LOGN) - 1; + localparam TN = (1 << (LOGN+1)) - 1; `IGNORE_WARNINGS_BEGIN wire [TN-1:0] s_n; @@ -21,13 +34,13 @@ module VX_find_first #( `IGNORE_WARNINGS_END for (genvar i = 0; i < N; ++i) begin - assign s_n[TL+i] = REVERSE ? valid_i[N-1-i] : valid_i[i]; - assign d_n[TL+i] = REVERSE ? data_i[N-1-i] : data_i[i]; + assign s_n[TL+i] = REVERSE ? valid_in[N-1-i] : valid_in[i]; + assign d_n[TL+i] = REVERSE ? data_in[N-1-i] : data_in[i]; end for (genvar i = TL+N; i < TN; ++i) begin assign s_n[i] = 0; - assign d_n[i] = 'x; + assign d_n[i] = '0; end for (genvar j = 0; j < LOGN; ++j) begin @@ -37,8 +50,8 @@ module VX_find_first #( end end - assign valid_o = s_n[0]; - assign data_o = d_n[0]; + assign valid_out = s_n[0]; + assign data_out = d_n[0]; endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_generic_arbiter.sv b/hw/rtl/libs/VX_generic_arbiter.sv new file mode 100644 index 00000000..adeefc7d --- /dev/null +++ b/hw/rtl/libs/VX_generic_arbiter.sv @@ -0,0 +1,113 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_generic_arbiter #( + parameter NUM_REQS = 1, + parameter LOCK_ENABLE = 0, + parameter `STRING TYPE = "P", + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) +) ( + input wire clk, + input wire reset, + input wire unlock, + input wire [NUM_REQS-1:0] requests, + output wire [LOG_NUM_REQS-1:0] grant_index, + output wire [NUM_REQS-1:0] grant_onehot, + output wire grant_valid +); + if (TYPE == "P") begin + + VX_priority_arbiter #( + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) + ) priority_arbiter ( + .clk (clk), + .reset (reset), + .unlock (unlock), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot) + ); + + end else if (TYPE == "R") begin + + VX_rr_arbiter #( + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) + ) rr_arbiter ( + .clk (clk), + .reset (reset), + .unlock (unlock), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot) + ); + + end else if (TYPE == "F") begin + + VX_fair_arbiter #( + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) + ) fair_arbiter ( + .clk (clk), + .reset (reset), + .unlock (unlock), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot) + ); + + end else if (TYPE == "M") begin + + VX_matrix_arbiter #( + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) + ) matrix_arbiter ( + .clk (clk), + .reset (reset), + .unlock (unlock), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot) + ); + + end else if (TYPE == "C") begin + + VX_cyclic_arbiter #( + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) + ) cyclic_arbiter ( + .clk (clk), + .reset (reset), + .unlock (unlock), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot) + ); + + end else begin + + `ERROR(("invalid parameter")); + + end + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_index_buffer.sv b/hw/rtl/libs/VX_index_buffer.sv index 19efefcf..9c19b918 100644 --- a/hw/rtl/libs/VX_index_buffer.sv +++ b/hw/rtl/libs/VX_index_buffer.sv @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF @@ -7,82 +20,48 @@ module VX_index_buffer #( parameter LUTRAM = 1, parameter ADDRW = `LOG2UP(SIZE) ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, output wire [ADDRW-1:0] write_addr, input wire [DATAW-1:0] write_data, - input wire acquire_slot, + input wire acquire_en, input wire [ADDRW-1:0] read_addr, output wire [DATAW-1:0] read_data, - input wire [ADDRW-1:0] release_addr, - input wire release_slot, + input wire release_en, - output wire empty, - output wire full + output wire empty, + output wire full ); - reg [SIZE-1:0] free_slots, free_slots_n; - reg [ADDRW-1:0] write_addr_r; - reg empty_r, full_r; - - wire free_valid; - wire [ADDRW-1:0] free_index; - - VX_lzc #( - .N (SIZE) - ) free_slots_sel ( - .in_i (free_slots_n), - .cnt_o (free_index), - .valid_o (free_valid) - ); - - always @(*) begin - free_slots_n = free_slots; - if (release_slot) begin - free_slots_n[release_addr] = 1; - end - if (acquire_slot) begin - free_slots_n[write_addr_r] = 0; - end - end - - always @(posedge clk) begin - if (reset) begin - write_addr_r <= ADDRW'(1'b0); - free_slots <= {SIZE{1'b1}}; - empty_r <= 1'b1; - full_r <= 1'b0; - end else begin - if (release_slot) begin - `ASSERT(0 == free_slots[release_addr], ("%t: releasing invalid slot at port %d", $time, release_addr)); - end - if (acquire_slot) begin - `ASSERT(1 == free_slots[write_addr], ("%t: acquiring used slot at port %d", $time, write_addr)); - end - write_addr_r <= free_index; - free_slots <= free_slots_n; - empty_r <= (& free_slots_n); - full_r <= ~free_valid; - end - end + + VX_allocator #( + .SIZE (SIZE) + ) allocator ( + .clk (clk), + .reset (reset), + .acquire_en (acquire_en), + .acquire_addr (write_addr), + .release_en (release_en), + .release_addr (read_addr), + .empty (empty), + .full (full) + ); VX_dp_ram #( .DATAW (DATAW), .SIZE (SIZE), .LUTRAM (LUTRAM) ) data_table ( - .clk (clk), - .wren (acquire_slot), - .waddr (write_addr_r), + .clk (clk), + .read (1'b1), + .write (acquire_en), + `UNUSED_PIN (wren), + .waddr (write_addr), .wdata (write_data), .raddr (read_addr), .rdata (read_data) - ); - - assign write_addr = write_addr_r; - assign empty = empty_r; - assign full = full_r; + ); endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_index_queue.sv b/hw/rtl/libs/VX_index_queue.sv index 201287fb..23ec6ed8 100644 --- a/hw/rtl/libs/VX_index_queue.sv +++ b/hw/rtl/libs/VX_index_queue.sv @@ -1,20 +1,33 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_index_queue #( parameter DATAW = 1, - parameter SIZE = 1 + parameter SIZE = 1 ) ( - input wire clk, - input wire reset, - input wire [DATAW-1:0] write_data, + input wire clk, + input wire reset, + input wire [DATAW-1:0] write_data, output wire [`LOG2UP(SIZE)-1:0] write_addr, - input wire push, - input wire pop, - output wire full, - output wire empty, + input wire push, + input wire pop, + output wire full, + output wire empty, input wire [`LOG2UP(SIZE)-1:0] read_addr, - output wire [DATAW-1:0] read_data + output wire [DATAW-1:0] read_data ); reg [DATAW-1:0] entries [SIZE-1:0]; reg [SIZE-1:0] valid; @@ -36,9 +49,9 @@ module VX_index_queue #( always @(posedge clk) begin if (reset) begin - rd_ptr <= 0; - wr_ptr <= 0; - valid <= 0; + rd_ptr <= '0; + wr_ptr <= '0; + valid <= '0; end else begin if (enqueue) begin valid[wr_a] <= 1; @@ -61,4 +74,4 @@ module VX_index_queue #( assign read_data = entries[read_addr]; endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_lzc.sv b/hw/rtl/libs/VX_lzc.sv index cf89f586..2589bf5a 100644 --- a/hw/rtl/libs/VX_lzc.sv +++ b/hw/rtl/libs/VX_lzc.sv @@ -1,31 +1,55 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_lzc #( - parameter N = 2, - parameter MODE = 0, // 0 -> trailing zero, 1 -> leading zero - parameter LOGN = $clog2(N) + parameter N = 2, + parameter REVERSE = 0, // 0 -> leading zero, 1 -> trailing zero, + parameter LOGN = `LOG2UP(N) ) ( - input wire [N-1:0] in_i, - output wire [LOGN-1:0] cnt_o, - output wire valid_o + input wire [N-1:0] data_in, + output wire [LOGN-1:0] data_out, + output wire valid_out ); - wire [N-1:0][LOGN-1:0] indices; + if (N == 1) begin + + `UNUSED_PARAM (REVERSE) + + assign data_out = '0; + assign valid_out = data_in; + + end else begin + + wire [N-1:0][LOGN-1:0] indices; + + for (genvar i = 0; i < N; ++i) begin + assign indices[i] = REVERSE ? LOGN'(i) : LOGN'(N-1-i); + end + + VX_find_first #( + .N (N), + .DATAW (LOGN), + .REVERSE (!REVERSE) + ) find_first ( + .data_in (indices), + .valid_in (data_in), + .data_out (data_out), + .valid_out (valid_out) + ); - for (genvar i = 0; i < N; ++i) begin - assign indices[i] = MODE ? LOGN'(N-1-i) : LOGN'(i); end - - VX_find_first #( - .N (N), - .DATAW (LOGN), - .REVERSE (MODE) - ) find_first ( - .data_i (indices), - .valid_i (in_i), - .data_o (cnt_o), - .valid_o (valid_o) - ); endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_matrix_arbiter.sv b/hw/rtl/libs/VX_matrix_arbiter.sv index a6624ac5..e076e06e 100644 --- a/hw/rtl/libs/VX_matrix_arbiter.sv +++ b/hw/rtl/libs/VX_matrix_arbiter.sv @@ -1,26 +1,39 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_matrix_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, - parameter LOG_NUM_REQS = $clog2(NUM_REQS) + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) ) ( input wire clk, input wire reset, - input wire enable, + input wire unlock, input wire [NUM_REQS-1:0] requests, output wire [LOG_NUM_REQS-1:0] grant_index, output wire [NUM_REQS-1:0] grant_onehot, output wire grant_valid - ); - +); if (NUM_REQS == 1) begin `UNUSED_VAR (clk) `UNUSED_VAR (reset) + `UNUSED_VAR (unlock) - assign grant_index = 0; + assign grant_index = '0; assign grant_onehot = requests; assign grant_valid = requests[0]; @@ -30,8 +43,8 @@ module VX_matrix_arbiter #( wire [NUM_REQS-1:0] pri [NUM_REQS-1:0]; wire [NUM_REQS-1:0] grant_unqual; - for (genvar i = 0; i < NUM_REQS; i++) begin - for (genvar j = 0; j < NUM_REQS; j++) begin + for (genvar i = 0; i < NUM_REQS; ++i) begin + for (genvar j = 0; j < NUM_REQS; ++j) begin if (j > i) begin assign pri[j][i] = requests[i] && state[i][j]; end @@ -45,11 +58,11 @@ module VX_matrix_arbiter #( assign grant_unqual[i] = requests[i] && !(| pri[i]); end - for (genvar i = 0; i < NUM_REQS; i++) begin - for (genvar j = i + 1; j < NUM_REQS; j++) begin + for (genvar i = 0; i < NUM_REQS; ++i) begin + for (genvar j = i + 1; j < NUM_REQS; ++j) begin always @(posedge clk) begin if (reset) begin - state[i][j] <= 0; + state[i][j] <= '0; end else begin state[i][j] <= (state[i][j] || grant_unqual[j]) && !grant_unqual[i]; end @@ -58,18 +71,18 @@ module VX_matrix_arbiter #( end if (LOCK_ENABLE == 0) begin - `UNUSED_VAR (enable) + `UNUSED_VAR (unlock) assign grant_onehot = grant_unqual; end else begin reg [NUM_REQS-1:0] grant_unqual_prev; always @(posedge clk) begin if (reset) begin - grant_unqual_prev <= 0; - end else if (enable) begin + grant_unqual_prev <= '0; + end else if (unlock) begin grant_unqual_prev <= grant_unqual; end end - assign grant_onehot = enable ? grant_unqual : grant_unqual_prev; + assign grant_onehot = unlock ? grant_unqual : grant_unqual_prev; end VX_onehot_encoder #( @@ -85,4 +98,4 @@ module VX_matrix_arbiter #( end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_mem_adapter.sv b/hw/rtl/libs/VX_mem_adapter.sv new file mode 100644 index 00000000..19d65240 --- /dev/null +++ b/hw/rtl/libs/VX_mem_adapter.sv @@ -0,0 +1,240 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mem_adapter #( + parameter SRC_DATA_WIDTH = 1, + parameter SRC_ADDR_WIDTH = 1, + parameter DST_DATA_WIDTH = 1, + parameter DST_ADDR_WIDTH = 1, + parameter SRC_TAG_WIDTH = 1, + parameter DST_TAG_WIDTH = 1, + parameter OUT_REG_REQ = 0, + parameter OUT_REG_RSP = 0 +) ( + input wire clk, + input wire reset, + + input wire mem_req_valid_in, + input wire [SRC_ADDR_WIDTH-1:0] mem_req_addr_in, + input wire mem_req_rw_in, + input wire [SRC_DATA_WIDTH/8-1:0] mem_req_byteen_in, + input wire [SRC_DATA_WIDTH-1:0] mem_req_data_in, + input wire [SRC_TAG_WIDTH-1:0] mem_req_tag_in, + output wire mem_req_ready_in, + + output wire mem_rsp_valid_in, + output wire [SRC_DATA_WIDTH-1:0] mem_rsp_data_in, + output wire [SRC_TAG_WIDTH-1:0] mem_rsp_tag_in, + input wire mem_rsp_ready_in, + + output wire mem_req_valid_out, + output wire [DST_ADDR_WIDTH-1:0] mem_req_addr_out, + output wire mem_req_rw_out, + output wire [DST_DATA_WIDTH/8-1:0] mem_req_byteen_out, + output wire [DST_DATA_WIDTH-1:0] mem_req_data_out, + output wire [DST_TAG_WIDTH-1:0] mem_req_tag_out, + input wire mem_req_ready_out, + + input wire mem_rsp_valid_out, + input wire [DST_DATA_WIDTH-1:0] mem_rsp_data_out, + input wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_out, + output wire mem_rsp_ready_out +); + `STATIC_ASSERT ((DST_TAG_WIDTH >= SRC_TAG_WIDTH), ("oops!")) + + localparam DST_DATA_SIZE = (DST_DATA_WIDTH / 8); + localparam DST_LDATAW = `CLOG2(DST_DATA_WIDTH); + localparam SRC_LDATAW = `CLOG2(SRC_DATA_WIDTH); + localparam D = `ABS(DST_LDATAW - SRC_LDATAW); + localparam P = 2**D; + + wire mem_req_valid_out_w; + wire [DST_ADDR_WIDTH-1:0] mem_req_addr_out_w; + wire mem_req_rw_out_w; + wire [DST_DATA_WIDTH/8-1:0] mem_req_byteen_out_w; + wire [DST_DATA_WIDTH-1:0] mem_req_data_out_w; + wire [DST_TAG_WIDTH-1:0] mem_req_tag_out_w; + wire mem_req_ready_out_w; + + wire mem_rsp_valid_in_w; + wire [SRC_DATA_WIDTH-1:0] mem_rsp_data_in_w; + wire [SRC_TAG_WIDTH-1:0] mem_rsp_tag_in_w; + wire mem_rsp_ready_in_w; + + `UNUSED_VAR (mem_rsp_tag_out) + + if (DST_LDATAW > SRC_LDATAW) begin + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + wire [D-1:0] req_idx = mem_req_addr_in[D-1:0]; + wire [D-1:0] rsp_idx = mem_rsp_tag_out[D-1:0]; + + wire [SRC_ADDR_WIDTH-D-1:0] mem_req_addr_in_qual = mem_req_addr_in[SRC_ADDR_WIDTH-1:D]; + + wire [P-1:0][SRC_DATA_WIDTH-1:0] mem_rsp_data_out_w = mem_rsp_data_out; + + if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH - D)) begin + `UNUSED_VAR (mem_req_addr_in_qual) + assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0]; + end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH - D)) begin + assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual); + end else begin + assign mem_req_addr_out_w = mem_req_addr_in_qual; + end + + assign mem_req_valid_out_w = mem_req_valid_in; + assign mem_req_rw_out_w = mem_req_rw_in; + assign mem_req_byteen_out_w = DST_DATA_SIZE'(mem_req_byteen_in) << ((DST_LDATAW-3)'(req_idx) << (SRC_LDATAW-3)); + assign mem_req_data_out_w = DST_DATA_WIDTH'(mem_req_data_in) << ((DST_LDATAW'(req_idx)) << SRC_LDATAW); + assign mem_req_tag_out_w = DST_TAG_WIDTH'({mem_req_tag_in, req_idx}); + assign mem_req_ready_in = mem_req_ready_out_w; + + assign mem_rsp_valid_in_w = mem_rsp_valid_out; + assign mem_rsp_data_in_w = mem_rsp_data_out_w[rsp_idx]; + assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out[SRC_TAG_WIDTH+D-1:D]); + assign mem_rsp_ready_out = mem_rsp_ready_in_w; + + end else if (DST_LDATAW < SRC_LDATAW) begin + + reg [D-1:0] req_ctr, rsp_ctr; + + reg [P-1:0][DST_DATA_WIDTH-1:0] mem_rsp_data_out_r, mem_rsp_data_out_n; + + wire mem_req_out_fire = mem_req_valid_out && mem_req_ready_out; + wire mem_rsp_in_fire = mem_rsp_valid_out && mem_rsp_ready_out; + + wire [P-1:0][DST_DATA_WIDTH-1:0] mem_req_data_in_w = mem_req_data_in; + wire [P-1:0][DST_DATA_SIZE-1:0] mem_req_byteen_in_w = mem_req_byteen_in; + + always @(*) begin + mem_rsp_data_out_n = mem_rsp_data_out_r; + if (mem_rsp_in_fire) begin + mem_rsp_data_out_n[rsp_ctr] = mem_rsp_data_out; + end + end + + always @(posedge clk) begin + if (reset) begin + req_ctr <= '0; + rsp_ctr <= '0; + end else begin + if (mem_req_out_fire) begin + req_ctr <= req_ctr + 1; + end + if (mem_rsp_in_fire) begin + rsp_ctr <= rsp_ctr + 1; + end + end + mem_rsp_data_out_r <= mem_rsp_data_out_n; + end + + reg [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_r; + wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_x; + + always @(posedge clk) begin + if (mem_rsp_in_fire) begin + mem_rsp_tag_in_r <= mem_rsp_tag_out; + end + end + assign mem_rsp_tag_in_x = (rsp_ctr != 0) ? mem_rsp_tag_in_r : mem_rsp_tag_out; + `RUNTIME_ASSERT(!mem_rsp_in_fire || (mem_rsp_tag_in_x == mem_rsp_tag_out), + ("%t: *** out-of-order memory reponse! cur=%d, expected=%d", $time, mem_rsp_tag_in_x, mem_rsp_tag_out)) + + wire [SRC_ADDR_WIDTH+D-1:0] mem_req_addr_in_qual = {mem_req_addr_in, req_ctr}; + + if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH + D)) begin + `UNUSED_VAR (mem_req_addr_in_qual) + assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0]; + end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH + D)) begin + assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual); + end else begin + assign mem_req_addr_out_w = mem_req_addr_in_qual; + end + + assign mem_req_valid_out_w = mem_req_valid_in; + assign mem_req_rw_out_w = mem_req_rw_in; + assign mem_req_byteen_out_w = mem_req_byteen_in_w[req_ctr]; + assign mem_req_data_out_w = mem_req_data_in_w[req_ctr]; + assign mem_req_tag_out_w = DST_TAG_WIDTH'(mem_req_tag_in); + assign mem_req_ready_in = mem_req_ready_out_w && (req_ctr == (P-1)); + + assign mem_rsp_valid_in_w = mem_rsp_valid_out && (rsp_ctr == (P-1)); + assign mem_rsp_data_in_w = mem_rsp_data_out_n; + assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out); + assign mem_rsp_ready_out = mem_rsp_ready_in_w; + + end else begin + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + if (DST_ADDR_WIDTH < SRC_ADDR_WIDTH) begin + `UNUSED_VAR (mem_req_addr_in) + assign mem_req_addr_out_w = mem_req_addr_in[DST_ADDR_WIDTH-1:0]; + end else if (DST_ADDR_WIDTH > SRC_ADDR_WIDTH) begin + assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in); + end else begin + assign mem_req_addr_out_w = mem_req_addr_in; + end + + assign mem_req_valid_out_w = mem_req_valid_in; + assign mem_req_rw_out_w = mem_req_rw_in; + assign mem_req_byteen_out_w = mem_req_byteen_in; + assign mem_req_data_out_w = mem_req_data_in; + assign mem_req_tag_out_w = DST_TAG_WIDTH'(mem_req_tag_in); + assign mem_req_ready_in = mem_req_ready_out_w; + + assign mem_rsp_valid_in_w = mem_rsp_valid_out; + assign mem_rsp_data_in_w = mem_rsp_data_out; + assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out); + assign mem_rsp_ready_out = mem_rsp_ready_in_w; + + end + + VX_elastic_buffer #( + .DATAW (1 + DST_DATA_SIZE + DST_ADDR_WIDTH + DST_DATA_WIDTH + DST_TAG_WIDTH), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG_REQ)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG_REQ)) + ) req_out_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_valid_out_w), + .ready_in (mem_req_ready_out_w), + .data_in ({mem_req_rw_out_w, mem_req_byteen_out_w, mem_req_addr_out_w, mem_req_data_out_w, mem_req_tag_out_w}), + .data_out ({mem_req_rw_out, mem_req_byteen_out, mem_req_addr_out, mem_req_data_out, mem_req_tag_out}), + .valid_out (mem_req_valid_out), + .ready_out (mem_req_ready_out) + ); + + VX_elastic_buffer #( + .DATAW (SRC_DATA_WIDTH + SRC_TAG_WIDTH), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG_RSP)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG_RSP)) + ) rsp_in_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_rsp_valid_in_w), + .ready_in (mem_rsp_ready_in_w), + .data_in ({mem_rsp_data_in_w, mem_rsp_tag_in_w}), + .data_out ({mem_rsp_data_in, mem_rsp_tag_in}), + .valid_out (mem_rsp_valid_in), + .ready_out (mem_rsp_ready_in) + ); + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_mem_rsp_sel.sv b/hw/rtl/libs/VX_mem_rsp_sel.sv new file mode 100644 index 00000000..120bc80d --- /dev/null +++ b/hw/rtl/libs/VX_mem_rsp_sel.sv @@ -0,0 +1,111 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mem_rsp_sel #( + parameter NUM_REQS = 1, + parameter DATA_WIDTH = 1, + parameter TAG_WIDTH = 1, + parameter TAG_SEL_BITS = 0, + parameter OUT_REG = 0 +) ( +input wire clk, + input wire reset, + + // input response + input wire [NUM_REQS-1:0] rsp_valid_in, + input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in, + input wire [NUM_REQS-1:0][TAG_WIDTH-1:0] rsp_tag_in, + output wire [NUM_REQS-1:0] rsp_ready_in, + + // output responses + output wire rsp_valid_out, + output wire [NUM_REQS-1:0] rsp_mask_out, + output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_out, + output wire [TAG_WIDTH-1:0] rsp_tag_out, + input wire rsp_ready_out +); + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + localparam LOG_NUM_REQS = `CLOG2(NUM_REQS); + + if (NUM_REQS > 1) begin + + wire [LOG_NUM_REQS-1:0] grant_index; + wire grant_valid; + wire rsp_fire; + + VX_priority_arbiter #( + .NUM_REQS (NUM_REQS) + ) arbiter ( + .clk (clk), + .reset (reset), + .unlock (rsp_fire), + .requests (rsp_valid_in), + .grant_valid (grant_valid), + .grant_index (grant_index), + `UNUSED_PIN (grant_onehot) + ); + + reg [NUM_REQS-1:0] rsp_valid_sel; + reg [NUM_REQS-1:0] rsp_ready_sel; + wire rsp_ready_unqual; + + wire [TAG_WIDTH-1:0] rsp_tag_sel = rsp_tag_in[grant_index]; + + always @(*) begin + rsp_valid_sel = '0; + rsp_ready_sel = '0; + + for (integer i = 0; i < NUM_REQS; ++i) begin + if (rsp_tag_in[i][TAG_SEL_BITS-1:0] == rsp_tag_sel[TAG_SEL_BITS-1:0]) begin + rsp_valid_sel[i] = rsp_valid_in[i]; + rsp_ready_sel[i] = rsp_ready_unqual; + end + end + end + + assign rsp_fire = grant_valid && rsp_ready_unqual; + + VX_elastic_buffer #( + .DATAW (NUM_REQS + TAG_WIDTH + (NUM_REQS * DATA_WIDTH)), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (grant_valid), + .data_in ({rsp_valid_sel, rsp_tag_sel, rsp_data_in}), + .ready_in (rsp_ready_unqual), + .valid_out (rsp_valid_out), + .data_out ({rsp_mask_out, rsp_tag_out, rsp_data_out}), + .ready_out (rsp_ready_out) + ); + + assign rsp_ready_in = rsp_ready_sel; + + end else begin + + assign rsp_valid_out = rsp_valid_in; + assign rsp_mask_out = 1'b1; + assign rsp_tag_out = rsp_tag_in; + assign rsp_data_out = rsp_data_in; + assign rsp_ready_in = rsp_ready_out; + + end + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_mem_scheduler.sv b/hw/rtl/libs/VX_mem_scheduler.sv new file mode 100644 index 00000000..17ccd63f --- /dev/null +++ b/hw/rtl/libs/VX_mem_scheduler.sv @@ -0,0 +1,578 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mem_scheduler #( + parameter `STRING INSTANCE_ID = "", + parameter NUM_REQS = 4, + parameter NUM_BANKS = 4, + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32, + parameter TAG_WIDTH = 32, + parameter MEM_TAG_ID = 0, // upper section of the tag sent to the memory interface + parameter UUID_WIDTH = 0, // upper section of the mem_tag_id containing the UUID + parameter QUEUE_SIZE = 16, + parameter RSP_PARTIAL = 0, + parameter CORE_OUT_REG = 0, + parameter MEM_OUT_REG = 0, + + parameter BYTEENW = DATA_WIDTH / 8, + parameter NUM_BATCHES = (NUM_REQS + NUM_BANKS - 1) / NUM_BANKS, + parameter QUEUE_ADDRW = `CLOG2(QUEUE_SIZE), + parameter BATCH_SEL_BITS = `CLOG2(NUM_BATCHES), + parameter MEM_TAGW = MEM_TAG_ID + QUEUE_ADDRW + BATCH_SEL_BITS +) ( + input wire clk, + input wire reset, + + // Input request + input wire req_valid, + input wire req_rw, + input wire [NUM_REQS-1:0] req_mask, + input wire [NUM_REQS-1:0][BYTEENW-1:0] req_byteen, + input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr, + input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data, + input wire [TAG_WIDTH-1:0] req_tag, + output wire req_empty, + output wire req_ready, + output wire write_notify, + + // Output response + output wire rsp_valid, + output wire [NUM_REQS-1:0] rsp_mask, + output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data, + output wire [TAG_WIDTH-1:0] rsp_tag, + output wire rsp_sop, + output wire rsp_eop, + input wire rsp_ready, + + // Memory request + output wire [NUM_BANKS-1:0] mem_req_valid, + output wire [NUM_BANKS-1:0] mem_req_rw, + output wire [NUM_BANKS-1:0][BYTEENW-1:0] mem_req_byteen, + output wire [NUM_BANKS-1:0][ADDR_WIDTH-1:0] mem_req_addr, + output wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_req_data, + output wire [NUM_BANKS-1:0][MEM_TAGW-1:0]mem_req_tag, + input wire [NUM_BANKS-1:0] mem_req_ready, + + // Memory response + input wire [NUM_BANKS-1:0] mem_rsp_valid, + input wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_rsp_data, + input wire [NUM_BANKS-1:0][MEM_TAGW-1:0] mem_rsp_tag, + output wire [NUM_BANKS-1:0] mem_rsp_ready + ); + + localparam MEM_TAG_WIDTH = `UP(MEM_TAG_ID); + localparam BATCH_SEL_WIDTH = `UP(BATCH_SEL_BITS); + localparam TAG_ONLY_WIDTH = TAG_WIDTH - MEM_TAG_ID; + localparam STALL_TIMEOUT = 10000000; + + `STATIC_ASSERT ((MEM_TAG_ID >= UUID_WIDTH), ("invalid parameter")) + `STATIC_ASSERT (DATA_WIDTH == 8 * (DATA_WIDTH / 8), ("invalid parameter")) + `STATIC_ASSERT ((0 == RSP_PARTIAL) || (1 == RSP_PARTIAL), ("invalid parameter")) + `RUNTIME_ASSERT ((~req_valid || req_mask != 0), ("invalid request mask")); + + wire [NUM_BANKS-1:0] mem_req_valid_s; + wire [NUM_BANKS-1:0] mem_req_mask_s; + wire [NUM_BANKS-1:0] mem_req_rw_s; + wire [NUM_BANKS-1:0][BYTEENW-1:0] mem_req_byteen_s; + wire [NUM_BANKS-1:0][ADDR_WIDTH-1:0] mem_req_addr_s; + wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_req_data_s; + wire [MEM_TAGW-1:0] mem_req_tag_s; + wire [NUM_BANKS-1:0] mem_req_ready_s; + + wire mem_rsp_valid_s; + wire [NUM_BANKS-1:0] mem_rsp_mask_s; + wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_rsp_data_s; + wire [MEM_TAGW-1:0] mem_rsp_tag_s; + wire mem_rsp_ready_s; + wire mem_rsp_fire_s; + + wire reqq_push; + wire reqq_pop; + wire reqq_full; + wire reqq_empty; + wire reqq_rw; + wire [NUM_REQS-1:0] reqq_mask; + wire [NUM_REQS-1:0][BYTEENW-1:0] reqq_byteen; + wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] reqq_addr; + wire [NUM_REQS-1:0][DATA_WIDTH-1:0] reqq_data; + wire [QUEUE_ADDRW-1:0] reqq_tag; + wire [MEM_TAG_WIDTH-1:0] reqq_mtid; + + wire ibuf_push; + wire ibuf_pop; + wire [QUEUE_ADDRW-1:0] ibuf_waddr; + wire [QUEUE_ADDRW-1:0] ibuf_raddr; + wire ibuf_full; + wire ibuf_empty; + wire [TAG_ONLY_WIDTH-1:0] ibuf_din; + wire [TAG_ONLY_WIDTH-1:0] ibuf_dout; + + wire crsp_valid; + wire [NUM_REQS-1:0] crsp_mask; + wire [NUM_REQS-1:0][DATA_WIDTH-1:0] crsp_data; + wire [TAG_WIDTH-1:0] crsp_tag; + wire crsp_sop; + wire crsp_eop; + wire crsp_ready; + + // Request queue ////////////////////////////////////////////////////////// + + wire req_sent_all; + + assign reqq_push = req_valid && req_ready; + assign reqq_pop = ~reqq_empty && req_sent_all; + + wire [MEM_TAG_WIDTH-1:0] req_mtid; + if (MEM_TAG_ID != 0) begin + assign req_mtid = req_tag[TAG_WIDTH-1 -: MEM_TAG_ID]; + end else begin + assign req_mtid = '0; + end + + wire [`CLOG2(QUEUE_SIZE+1)-1:0] reqq_size; + `UNUSED_VAR (reqq_size) + + VX_fifo_queue #( + .DATAW (1 + NUM_REQS * (1 + BYTEENW + ADDR_WIDTH + DATA_WIDTH) + MEM_TAG_WIDTH + QUEUE_ADDRW), + .DEPTH (QUEUE_SIZE), + .OUT_REG (1) + ) req_queue ( + .clk (clk), + .reset (reset), + .push (reqq_push), + .pop (reqq_pop), + .data_in ({req_rw, req_mask, req_byteen, req_addr, req_data, req_mtid, ibuf_waddr}), + .data_out ({reqq_rw, reqq_mask, reqq_byteen, reqq_addr, reqq_data, reqq_mtid, reqq_tag}), + .full (reqq_full), + .empty (reqq_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (alm_empty), + .size (reqq_size) + ); + + // can accept another request? + assign req_ready = ~reqq_full && (req_rw || ~ibuf_full); + + // no pending requests + assign req_empty = reqq_empty && ibuf_empty; + + // notify write submisison + assign write_notify = reqq_pop && reqq_rw; + + // Index buffer /////////////////////////////////////////////////////////// + + wire rsp_complete; + + assign ibuf_push = reqq_push && ~req_rw; + assign ibuf_pop = crsp_valid && crsp_ready && rsp_complete; + assign ibuf_raddr = mem_rsp_tag_s[0 +: QUEUE_ADDRW]; + assign ibuf_din = req_tag[TAG_ONLY_WIDTH-1:0]; + + VX_index_buffer #( + .DATAW (TAG_ONLY_WIDTH), + .SIZE (QUEUE_SIZE) + ) req_ibuf ( + .clk (clk), + .reset (reset), + .acquire_en (ibuf_push), + .write_addr (ibuf_waddr), + .write_data (ibuf_din), + .read_data (ibuf_dout), + .read_addr (ibuf_raddr), + .release_en (ibuf_pop), + .full (ibuf_full), + .empty (ibuf_empty) + ); + + `UNUSED_VAR (ibuf_empty) + + // Handle memory requests ///////////////////////////////////////////////// + + wire [NUM_BATCHES-1:0][NUM_BANKS-1:0] mem_req_mask_b; + wire [NUM_BATCHES-1:0][NUM_BANKS-1:0] mem_req_rw_b; + wire [NUM_BATCHES-1:0][NUM_BANKS-1:0][BYTEENW-1:0] mem_req_byteen_b; + wire [NUM_BATCHES-1:0][NUM_BANKS-1:0][ADDR_WIDTH-1:0] mem_req_addr_b; + wire [NUM_BATCHES-1:0][NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_req_data_b; + + wire [BATCH_SEL_WIDTH-1:0] req_batch_idx; + + for (genvar i = 0; i < NUM_BATCHES; ++i) begin + for (genvar j = 0; j < NUM_BANKS; ++j) begin + localparam r = i * NUM_BANKS + j; + if (r < NUM_REQS) begin + assign mem_req_mask_b[i][j] = reqq_mask[r]; + assign mem_req_rw_b[i][j] = reqq_rw; + assign mem_req_byteen_b[i][j] = reqq_byteen[r]; + assign mem_req_addr_b[i][j] = reqq_addr[r]; + assign mem_req_data_b[i][j] = reqq_data[r]; + end else begin + assign mem_req_mask_b[i][j] = 0; + assign mem_req_rw_b[i][j] = '0; + assign mem_req_byteen_b[i][j] = '0; + assign mem_req_addr_b[i][j] = '0; + assign mem_req_data_b[i][j] = '0; + end + end + end + + assign mem_req_mask_s = mem_req_mask_b[req_batch_idx]; + assign mem_req_rw_s = mem_req_rw_b[req_batch_idx]; + assign mem_req_byteen_s = mem_req_byteen_b[req_batch_idx]; + assign mem_req_addr_s = mem_req_addr_b[req_batch_idx]; + assign mem_req_data_s = mem_req_data_b[req_batch_idx]; + + reg [NUM_BANKS-1:0] batch_sent_mask; + + wire [NUM_BANKS-1:0] batch_sent_mask_n = batch_sent_mask | mem_req_ready_s; + + wire batch_sent_all = (mem_req_mask_s & ~batch_sent_mask_n) == 0; + + always @(posedge clk) begin + if (reset) begin + batch_sent_mask <= '0; + end else begin + if (~reqq_empty) begin + if (batch_sent_all) begin + batch_sent_mask <= '0; + end else begin + batch_sent_mask <= batch_sent_mask_n; + end + end + end + end + + if (NUM_BATCHES > 1) begin + reg [BATCH_SEL_BITS-1:0] req_batch_idx_r; + always @(posedge clk) begin + if (reset) begin + req_batch_idx_r <= '0; + end else begin + if (~reqq_empty && batch_sent_all) begin + if (req_sent_all) begin + req_batch_idx_r <= '0; + end else begin + req_batch_idx_r <= req_batch_idx_r + BATCH_SEL_BITS'(1); + end + end + end + end + + wire [NUM_BATCHES-1:0] req_batch_valids; + wire [NUM_BATCHES-1:0][BATCH_SEL_BITS-1:0] req_batch_idxs; + wire [BATCH_SEL_BITS-1:0] req_batch_idx_last; + + for (genvar i = 0; i < NUM_BATCHES; ++i) begin + assign req_batch_valids[i] = (| mem_req_mask_b[i]); + assign req_batch_idxs[i] = BATCH_SEL_BITS'(i); + end + + VX_find_first #( + .N (NUM_BATCHES), + .DATAW (BATCH_SEL_BITS), + .REVERSE (1) + ) find_last ( + .valid_in (req_batch_valids), + .data_in (req_batch_idxs), + .data_out (req_batch_idx_last), + `UNUSED_PIN (valid_out) + ); + + assign req_batch_idx = req_batch_idx_r; + + assign req_sent_all = batch_sent_all && (req_batch_idx_r == req_batch_idx_last); + + if (MEM_TAG_ID != 0) begin + assign mem_req_tag_s = {reqq_mtid, req_batch_idx, reqq_tag}; + end else begin + `UNUSED_VAR (reqq_mtid) + assign mem_req_tag_s = {req_batch_idx, reqq_tag}; + end + + end else begin + + assign req_batch_idx = '0; + assign req_sent_all = batch_sent_all; + + if (MEM_TAG_ID != 0) begin + assign mem_req_tag_s = {reqq_mtid, reqq_tag}; + end else begin + `UNUSED_VAR (reqq_mtid) + assign mem_req_tag_s = reqq_tag; + end + end + + assign mem_req_valid_s = {NUM_BANKS{~reqq_empty}} & mem_req_mask_s & ~batch_sent_mask; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + VX_elastic_buffer #( + .DATAW (1 + BYTEENW + ADDR_WIDTH + DATA_WIDTH + MEM_TAGW), + .SIZE (`OUT_REG_TO_EB_SIZE(MEM_OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG)) + ) mem_req_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_valid_s[i]), + .ready_in (mem_req_ready_s[i]), + .data_in ({mem_req_rw_s[i], mem_req_byteen_s[i], mem_req_addr_s[i], mem_req_data_s[i], mem_req_tag_s}), + .data_out ({mem_req_rw[i], mem_req_byteen[i], mem_req_addr[i], mem_req_data[i], mem_req_tag[i]}), + .valid_out (mem_req_valid[i]), + .ready_out (mem_req_ready[i]) + ); + end + + // Handle memory responses //////////////////////////////////////////////// + + reg [QUEUE_SIZE-1:0][NUM_REQS-1:0] rsp_rem_mask; + wire [NUM_REQS-1:0] rsp_rem_mask_n, curr_mask; + wire [BATCH_SEL_WIDTH-1:0] rsp_batch_idx; + + // Select memory response + VX_mem_rsp_sel #( + .NUM_REQS (NUM_BANKS), + .DATA_WIDTH (DATA_WIDTH), + .TAG_WIDTH (MEM_TAGW), + .TAG_SEL_BITS (MEM_TAGW - MEM_TAG_ID), + .OUT_REG (2) + ) mem_rsp_sel ( + .clk (clk), + .reset (reset), + .rsp_valid_in (mem_rsp_valid), + .rsp_data_in (mem_rsp_data), + .rsp_tag_in (mem_rsp_tag), + .rsp_ready_in (mem_rsp_ready), + .rsp_valid_out (mem_rsp_valid_s), + .rsp_mask_out (mem_rsp_mask_s), + .rsp_data_out (mem_rsp_data_s), + .rsp_tag_out (mem_rsp_tag_s), + .rsp_ready_out (mem_rsp_ready_s) + ); + + for (genvar r = 0; r < NUM_REQS; ++r) begin + localparam i = r / NUM_BANKS; + localparam j = r % NUM_BANKS; + assign curr_mask[r] = (BATCH_SEL_WIDTH'(i) == rsp_batch_idx) && mem_rsp_mask_s[j]; + end + + assign rsp_rem_mask_n = rsp_rem_mask[ibuf_raddr] & ~curr_mask; + + if (NUM_BATCHES > 1) begin + assign rsp_batch_idx = mem_rsp_tag_s[QUEUE_ADDRW +: BATCH_SEL_BITS]; + end else begin + assign rsp_batch_idx = '0; + end + + assign rsp_complete = ~(| rsp_rem_mask_n); + + always @(posedge clk) begin + if (ibuf_push) begin + rsp_rem_mask[ibuf_waddr] <= req_mask; + end + if (mem_rsp_fire_s) begin + rsp_rem_mask[ibuf_raddr] <= rsp_rem_mask_n; + end + end + + assign mem_rsp_fire_s = mem_rsp_valid_s && mem_rsp_ready_s; + + if (RSP_PARTIAL == 1) begin + + reg [QUEUE_SIZE-1:0] rsp_sop_r; + + always @(posedge clk) begin + if (ibuf_push) begin + rsp_sop_r[ibuf_waddr] <= 1; + end + if (mem_rsp_fire_s) begin + rsp_sop_r[ibuf_raddr] <= 0; + end + end + + assign mem_rsp_ready_s = crsp_ready; + + assign crsp_valid = mem_rsp_valid_s; + + assign crsp_mask = curr_mask; + assign crsp_sop = rsp_sop_r[ibuf_raddr]; + + for (genvar r = 0; r < NUM_REQS; ++r) begin + localparam j = r % NUM_BANKS; + assign crsp_data[r] = mem_rsp_data_s[j]; + end + + end else begin + + reg [NUM_BATCHES*NUM_BANKS*DATA_WIDTH-1:0] rsp_store [QUEUE_SIZE-1:0]; + reg [NUM_BATCHES*NUM_BANKS*DATA_WIDTH-1:0] rsp_store_n; + reg [NUM_REQS-1:0] rsp_orig_mask [QUEUE_SIZE-1:0]; + + always @(*) begin + rsp_store_n = rsp_store[ibuf_raddr]; + for (integer i = 0; i < NUM_BANKS; ++i) begin + if ((NUM_BANKS == 1) || mem_rsp_mask_s[i]) begin + rsp_store_n[(rsp_batch_idx * NUM_BANKS + i) * DATA_WIDTH +: DATA_WIDTH] = mem_rsp_data_s[i]; + end + end + end + + always @(posedge clk) begin + if (ibuf_push) begin + rsp_orig_mask[ibuf_waddr] <= req_mask; + end + if (mem_rsp_valid_s) begin + rsp_store[ibuf_raddr] <= rsp_store_n; + end + end + + assign mem_rsp_ready_s = crsp_ready || ~rsp_complete; + + assign crsp_valid = mem_rsp_valid_s && rsp_complete; + + assign crsp_mask = rsp_orig_mask[ibuf_raddr]; + assign crsp_sop = 1'b1; + + for (genvar r = 0; r < NUM_REQS; ++r) begin + localparam i = r / NUM_BANKS; + localparam j = r % NUM_BANKS; + assign crsp_data[r] = rsp_store_n[(i * NUM_BANKS + j) * DATA_WIDTH +: DATA_WIDTH]; + end + end + + if (MEM_TAG_ID != 0) begin + assign crsp_tag = {mem_rsp_tag_s[MEM_TAGW-1 -: MEM_TAG_ID], ibuf_dout}; + end else begin + assign crsp_tag = ibuf_dout; + end + + assign crsp_eop = ibuf_pop; + + // Send response to caller + + VX_elastic_buffer #( + .DATAW (NUM_REQS + 1 + 1 + (NUM_REQS * DATA_WIDTH) + TAG_WIDTH), + .SIZE (`OUT_REG_TO_EB_SIZE(CORE_OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG)) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (crsp_valid), + .ready_in (crsp_ready), + .data_in ({crsp_mask, crsp_sop, crsp_eop, crsp_data, crsp_tag}), + .data_out ({rsp_mask, rsp_sop, rsp_eop, rsp_data, rsp_tag}), + .valid_out (rsp_valid), + .ready_out (rsp_ready) + ); + +`ifdef SIMULATION + wire [`UP(UUID_WIDTH)-1:0] req_dbg_uuid; + wire [`UP(UUID_WIDTH)-1:0] rsp_dbg_uuid; + wire [`UP(UUID_WIDTH)-1:0] mem_req_dbg_uuid; + wire [`UP(UUID_WIDTH)-1:0] mem_rsp_dbg_uuid; + + if (UUID_WIDTH != 0) begin + assign req_dbg_uuid = req_tag[TAG_WIDTH-1 -: UUID_WIDTH]; + assign rsp_dbg_uuid = rsp_tag[TAG_WIDTH-1 -: UUID_WIDTH]; + assign mem_req_dbg_uuid = reqq_mtid[MEM_TAG_ID-1 -: UUID_WIDTH]; + assign mem_rsp_dbg_uuid = mem_rsp_tag_s[MEM_TAGW-1 -: UUID_WIDTH]; + end else begin + assign req_dbg_uuid = '0; + assign rsp_dbg_uuid = '0; + assign mem_req_dbg_uuid = '0; + assign mem_rsp_dbg_uuid = '0; + end + + `UNUSED_VAR (req_dbg_uuid) + `UNUSED_VAR (rsp_dbg_uuid) + `UNUSED_VAR (mem_req_dbg_uuid) + `UNUSED_VAR (mem_rsp_dbg_uuid) + + reg [(`UP(UUID_WIDTH) + TAG_ONLY_WIDTH + 64)-1:0] pending_reqs [QUEUE_SIZE-1:0]; + reg [QUEUE_SIZE-1:0] pending_req_valids; + + always @(posedge clk) begin + if (reset) begin + pending_req_valids <= '0; + end else begin + if (ibuf_push) begin + pending_req_valids[ibuf_waddr] <= 1'b1; + end + if (ibuf_pop) begin + pending_req_valids[ibuf_raddr] <= 1'b0; + end + end + + if (ibuf_push) begin + pending_reqs[ibuf_waddr] <= {req_dbg_uuid, ibuf_din, $time}; + end + + for (integer i = 0; i < QUEUE_SIZE; ++i) begin + if (pending_req_valids[i]) begin + `ASSERT(($time - pending_reqs[i][0 +: 64]) < STALL_TIMEOUT, + ("%t: *** %s response timeout: remaining=%b, tag=0x%0h (#%0d)", + $time, INSTANCE_ID, rsp_rem_mask[i], pending_reqs[i][64 +: TAG_ONLY_WIDTH], pending_reqs[i][64+TAG_ONLY_WIDTH +: `UP(UUID_WIDTH)])); + end + end + end +`endif + + /////////////////////////////////////////////////////////////////////////// + +`ifndef NDEBUG + wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s; + always @(posedge clk) begin + if (req_valid && req_ready) begin + if (req_rw) begin + `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INSTANCE_ID, req_mask)); + `TRACE_ARRAY1D(1, req_addr, NUM_REQS); + `TRACE(1, (", byteen=")); + `TRACE_ARRAY1D(1, req_byteen, NUM_REQS); + `TRACE(1, (", data=")); + `TRACE_ARRAY1D(1, req_data, NUM_REQS); + end else begin + `TRACE(1, ("%d: %s-core-req-rd: valid=%b, addr=", $time, INSTANCE_ID, req_mask)); + `TRACE_ARRAY1D(1, req_addr, NUM_REQS); + end + `TRACE(1, (", tag=0x%0h (#%0d)\n", req_tag, req_dbg_uuid)); + end + if (rsp_valid && rsp_ready) begin + `TRACE(1, ("%d: %s-rsp: valid=%b, sop=%b, eop=%b, data=", $time, INSTANCE_ID, rsp_mask, rsp_sop, rsp_eop)); + `TRACE_ARRAY1D(1, rsp_data, NUM_REQS); + `TRACE(1, (", tag=0x%0h (#%0d)\n", rsp_tag, rsp_dbg_uuid)); + end + if (| mem_req_fire_s) begin + if (| mem_req_rw_s) begin + `TRACE(1, ("%d: %s-mem-req-wr: valid=%b, addr=", $time, INSTANCE_ID, mem_req_fire_s)); + `TRACE_ARRAY1D(1, mem_req_addr_s, NUM_BANKS); + `TRACE(1, (", byteen=")); + `TRACE_ARRAY1D(1, mem_req_byteen_s, NUM_BANKS); + `TRACE(1, (", data=")); + `TRACE_ARRAY1D(1, mem_req_data_s, NUM_BANKS); + end else begin + `TRACE(1, ("%d: %s-mem-req-rd: valid=%b, addr=", $time, INSTANCE_ID, mem_req_fire_s)); + `TRACE_ARRAY1D(1, mem_req_addr_s, NUM_BANKS); + end + `TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_waddr, req_batch_idx, mem_req_dbg_uuid)); + end + if (mem_rsp_fire_s) begin + `TRACE(1, ("%d: %s-mem-rsp: valid=%b, data=", $time, INSTANCE_ID, mem_rsp_mask_s)); + `TRACE_ARRAY1D(1, mem_rsp_data_s, NUM_BANKS); + `TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid)); + end + end +`endif + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_multiplier.sv b/hw/rtl/libs/VX_multiplier.sv index cbb52727..2f046779 100644 --- a/hw/rtl/libs/VX_multiplier.sv +++ b/hw/rtl/libs/VX_multiplier.sv @@ -1,70 +1,54 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_multiplier #( - parameter WIDTHA = 1, - parameter WIDTHB = 1, - parameter WIDTHP = 1, + parameter A_WIDTH = 1, + parameter B_WIDTH = A_WIDTH, + parameter R_WIDTH = A_WIDTH + B_WIDTH, parameter SIGNED = 0, parameter LATENCY = 0 ) ( input wire clk, input wire enable, - input wire [WIDTHA-1:0] dataa, - input wire [WIDTHB-1:0] datab, - output wire [WIDTHP-1:0] result + input wire [A_WIDTH-1:0] dataa, + input wire [B_WIDTH-1:0] datab, + output wire [R_WIDTH-1:0] result ); + wire [R_WIDTH-1:0] prod_w; -`ifdef QUARTUS - - lpm_mult mult ( - .clock (clk), - .clken (enable), - .dataa (dataa), - .datab (datab), - .result (result), - .aclr (1'b0), - .sclr (1'b0), - .sum (1'b0) - ); - - defparam mult.lpm_type = "LPM_MULT", - mult.lpm_widtha = WIDTHA, - mult.lpm_widthb = WIDTHB, - mult.lpm_widthp = WIDTHP, - mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", - mult.lpm_pipeline = LATENCY, - mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"; -`else - - wire [WIDTHP-1:0] result_unqual; - - if (SIGNED) begin - assign result_unqual = $signed(dataa) * $signed(datab); + if (SIGNED != 0) begin + assign prod_w = R_WIDTH'($signed(dataa) * $signed(datab)); end else begin - assign result_unqual = dataa * datab; + assign prod_w = R_WIDTH'(dataa * datab); end if (LATENCY == 0) begin - assign result = result_unqual; + assign result = prod_w; end else begin - reg [WIDTHP-1:0] result_pipe [LATENCY-1:0]; + reg [LATENCY-1:0][R_WIDTH-1:0] prod_r; always @(posedge clk) begin if (enable) begin - result_pipe[0] <= result_unqual; - end - end - for (genvar i = 1; i < LATENCY; i++) begin - always @(posedge clk) begin - if (enable) begin - result_pipe[i] <= result_pipe[i-1]; + prod_r[0] <= prod_w; + for (integer i = 1; i < LATENCY; ++i) begin + prod_r[i] <= prod_r[i-1]; end end - end - assign result = result_pipe[LATENCY-1]; + end + assign result = prod_r[LATENCY-1]; end -`endif - endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_mux.sv b/hw/rtl/libs/VX_mux.sv index 3b5c3030..f0bc78ca 100644 --- a/hw/rtl/libs/VX_mux.sv +++ b/hw/rtl/libs/VX_mux.sv @@ -1,10 +1,23 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_mux #( parameter DATAW = 1, parameter N = 1, - parameter LN = $clog2(N) + parameter LN = `LOG2UP(N) ) ( input wire [N-1:0][DATAW-1:0] data_in, input wire [LN-1:0] sel_in, @@ -18,4 +31,4 @@ module VX_mux #( end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_onehot_encoder.sv b/hw/rtl/libs/VX_onehot_encoder.sv index 8b85acb6..92c7d1ea 100644 --- a/hw/rtl/libs/VX_onehot_encoder.sv +++ b/hw/rtl/libs/VX_onehot_encoder.sv @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" // Fast encoder using parallel prefix computation @@ -5,7 +18,7 @@ `TRACING_OFF module VX_onehot_encoder #( - parameter N = 1, + parameter N = 1, parameter REVERSE = 0, parameter MODEL = 1, parameter LN = `LOG2UP(N) @@ -24,53 +37,50 @@ module VX_onehot_encoder #( assign data_out = data_in[!REVERSE]; assign valid_out = (| data_in); - end else if (MODEL == 1) begin - `IGNORE_WARNINGS_BEGIN - localparam levels_lp = $clog2(N); - localparam aligned_width_lp = 1 << $clog2(N); - - wire [levels_lp:0][aligned_width_lp-1:0] addr; - wire [levels_lp:0][aligned_width_lp-1:0] v; + end else if (MODEL == 1) begin + localparam M = 1 << LN; + `IGNORE_UNOPTFLAT_BEGIN + wire [LN-1:0][M-1:0] addr; + wire [LN:0][M-1:0] v; + `IGNORE_UNOPTFLAT_END // base case, also handle padding for non-power of two inputs - assign v[0] = REVERSE ? (data_in << (aligned_width_lp - N)) : ((aligned_width_lp)'(data_in)); - assign addr[0] = 'x; + assign v[0] = REVERSE ? (M'(data_in) << (M - N)) : M'(data_in); - for (genvar level = 1; level < levels_lp+1; level=level+1) begin - localparam segments_lp = 2**(levels_lp-level); - localparam segment_slot_lp = aligned_width_lp/segments_lp; - localparam segment_width_lp = level; // how many bits are needed at each level + for (genvar lvl = 1; lvl < (LN+1); ++lvl) begin + localparam SN = 1 << (LN - lvl); + localparam SI = M / SN; + localparam SW = lvl; - for (genvar segment = 0; segment < segments_lp; segment=segment+1) begin - wire [1:0] vs = { - v[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)], - v[level-1][segment*segment_slot_lp] - }; - - assign v[level][segment*segment_slot_lp] = (| vs); + for (genvar s = 0; s < SN; ++s) begin + `IGNORE_UNOPTFLAT_BEGIN + wire [1:0] vs = {v[lvl-1][s*SI+(SI>>1)], v[lvl-1][s*SI]}; + `IGNORE_UNOPTFLAT_END + + assign v[lvl][s*SI] = (| vs); - if (level == 1) begin - assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = vs[!REVERSE]; + if (lvl == 1) begin + assign addr[lvl-1][s*SI +: SW] = vs[!REVERSE]; end else begin - assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = { + assign addr[lvl-1][s*SI +: SW] = { vs[!REVERSE], - addr[level-1][segment*segment_slot_lp+:segment_width_lp-1] | addr[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)+:segment_width_lp-1] + addr[lvl-2][s*SI +: SW-1] | addr[lvl-2][s*SI+(SI>>1) +: SW-1] }; end end end - assign data_out = addr[levels_lp][`LOG2UP(N)-1:0]; - assign valid_out = v[levels_lp][0]; - `IGNORE_WARNINGS_END - end else if (MODEL == 2) begin + assign data_out = addr[LN-1][LN-1:0]; + assign valid_out = v[LN][0]; + + end else if (MODEL == 2 && REVERSE == 0) begin for (genvar j = 0; j < LN; ++j) begin wire [N-1:0] mask; for (genvar i = 0; i < N; ++i) begin assign mask[i] = i[j]; end - assign data_out[j] = |(mask & data_in); + assign data_out[j] = | (mask & data_in); end assign valid_out = (| data_in); @@ -79,21 +89,21 @@ module VX_onehot_encoder #( reg [LN-1:0] index_r; - if (REVERSE) begin + if (REVERSE != 0) begin always @(*) begin index_r = 'x; for (integer i = N-1; i >= 0; --i) begin if (data_in[i]) begin - index_r = `LOG2UP(N)'(i); + index_r = LN'(N-1-i); end end end end else begin always @(*) begin index_r = 'x; - for (integer i = 0; i < N; i++) begin + for (integer i = 0; i < N; ++i) begin if (data_in[i]) begin - index_r = `LOG2UP(N)'(i); + index_r = LN'(i); end end end @@ -104,4 +114,4 @@ module VX_onehot_encoder #( end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_onehot_mux.sv b/hw/rtl/libs/VX_onehot_mux.sv index 375ae105..9c8fdb9c 100644 --- a/hw/rtl/libs/VX_onehot_mux.sv +++ b/hw/rtl/libs/VX_onehot_mux.sv @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF @@ -10,11 +23,105 @@ module VX_onehot_mux #( input wire [N-1:0] sel_in, output wire [DATAW-1:0] data_out ); - if (N > 1) begin + if (N == 1) begin + `UNUSED_VAR (sel_in) + assign data_out = data_in; + end else if (N == 2) begin + `UNUSED_VAR (sel_in) + assign data_out = sel_in[0] ? data_in[0] : data_in[1]; + end else if (N == 3) begin + reg [DATAW-1:0] data_out_r; + always @(*) begin + case (sel_in) + 3'b001: data_out_r = data_in[0]; + 3'b010: data_out_r = data_in[1]; + 3'b100: data_out_r = data_in[2]; + default: data_out_r = 'x; + endcase + end + assign data_out = data_out_r; + end else if (N == 4) begin + reg [DATAW-1:0] data_out_r; + always @(*) begin + case (sel_in) + 4'b0001: data_out_r = data_in[0]; + 4'b0010: data_out_r = data_in[1]; + 4'b0100: data_out_r = data_in[2]; + 4'b1000: data_out_r = data_in[3]; + default: data_out_r = 'x; + endcase + end + assign data_out = data_out_r; + end else if (N == 5) begin + reg [DATAW-1:0] data_out_r; + always @(*) begin + case (sel_in) + 5'b00001: data_out_r = data_in[0]; + 5'b00010: data_out_r = data_in[1]; + 5'b00100: data_out_r = data_in[2]; + 5'b01000: data_out_r = data_in[3]; + 5'b10000: data_out_r = data_in[4]; + default: data_out_r = 'x; + endcase + end + assign data_out = data_out_r; + end else if (N == 6) begin + reg [DATAW-1:0] data_out_r; + always @(*) begin + case (sel_in) + 6'b000001: data_out_r = data_in[0]; + 6'b000010: data_out_r = data_in[1]; + 6'b000100: data_out_r = data_in[2]; + 6'b001000: data_out_r = data_in[3]; + 6'b010000: data_out_r = data_in[4]; + 6'b100000: data_out_r = data_in[5]; + default: data_out_r = 'x; + endcase + end + assign data_out = data_out_r; + end else if (N == 7) begin + reg [DATAW-1:0] data_out_r; + always @(*) begin + case (sel_in) + 7'b0000001: data_out_r = data_in[0]; + 7'b0000010: data_out_r = data_in[1]; + 7'b0000100: data_out_r = data_in[2]; + 7'b0001000: data_out_r = data_in[3]; + 7'b0010000: data_out_r = data_in[4]; + 7'b0100000: data_out_r = data_in[5]; + 7'b1000000: data_out_r = data_in[6]; + default: data_out_r = 'x; + endcase + end + assign data_out = data_out_r; + end else if (N == 8) begin + reg [DATAW-1:0] data_out_r; + always @(*) begin + case (sel_in) + 8'b00000001: data_out_r = data_in[0]; + 8'b00000010: data_out_r = data_in[1]; + 8'b00000100: data_out_r = data_in[2]; + 8'b00001000: data_out_r = data_in[3]; + 8'b00010000: data_out_r = data_in[4]; + 8'b00100000: data_out_r = data_in[5]; + 8'b01000000: data_out_r = data_in[6]; + 8'b10000000: data_out_r = data_in[7]; + default: data_out_r = 'x; + endcase + end + assign data_out = data_out_r; + end else begin if (MODEL == 1) begin - for (genvar i = 0; i < N; ++i) begin - assign data_out = sel_in[i] ? data_in[i] : 'z; + reg [DATAW-1:0] data_out_r; + always @(*) begin + data_out_r = 'x; + for (integer i = 0; i < N; ++i) begin + if (sel_in[i]) begin + data_out_r = data_in[i]; + end + end end + assign data_out = data_out_r; end else if (MODEL == 2) begin reg [DATAW-1:0] data_out_r; always @(*) begin @@ -36,22 +143,8 @@ module VX_onehot_mux #( end assign data_out[i] = (| gather); end - end else begin - reg [DATAW-1:0] data_out_r; - always @(*) begin - data_out_r = 'x; - for (integer i = N-1; i >= 0; --i) begin - if (sel_in[i]) begin - data_out_r = data_in[i]; - end - end - end - assign data_out = data_out_r; end - end else begin - `UNUSED_VAR (sel_in) - assign data_out = data_in; end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_pending_size.sv b/hw/rtl/libs/VX_pending_size.sv index 2964fdd0..4f400617 100644 --- a/hw/rtl/libs/VX_pending_size.sv +++ b/hw/rtl/libs/VX_pending_size.sv @@ -1,49 +1,102 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_pending_size #( parameter SIZE = 1, - parameter SIZEW = $clog2(SIZE+1) + parameter INCRW = 1, + parameter DECRW = 1, + parameter SIZEW = `CLOG2(SIZE+1) ) ( input wire clk, input wire reset, - input wire incr, - input wire decr, + input wire [INCRW-1:0] incr, + input wire [DECRW-1:0] decr, output wire empty, output wire full, output wire [SIZEW-1:0] size ); - localparam ADDRW = $clog2(SIZE); + `STATIC_ASSERT(INCRW <= SIZEW, ("invalid parameter")) + `STATIC_ASSERT(DECRW <= SIZEW, ("invalid parameter")) + localparam ADDRW = `LOG2UP(SIZE); - reg [ADDRW-1:0] used_r; - reg empty_r; - reg full_r; + reg empty_r; + reg full_r; - always @(posedge clk) begin - if (reset) begin - used_r <= 0; - empty_r <= 1; - full_r <= 0; - end else begin - `ASSERT(!incr || !full, ("runtime error")); - if (incr) begin - if (!decr) begin - empty_r <= 0; - if (used_r == ADDRW'(SIZE-1)) - full_r <= 1; - end - end else if (decr) begin - full_r <= 0; - if (used_r == ADDRW'(1)) - empty_r <= 1; + if (INCRW != 1 || DECRW != 1) begin + + reg [SIZEW-1:0] size_r; + wire [SIZEW-1:0] size_n; + + assign size_n = size_r + SIZEW'(incr) - SIZEW'(decr); + + always @(posedge clk) begin + if (reset) begin + size_r <= '0; + empty_r <= 1; + full_r <= 0; + end else begin + size_r <= size_n; + empty_r <= (size_n == SIZEW'(0)); + full_r <= (size_n == SIZEW'(SIZE)); end - used_r <= used_r + ADDRW'($signed(2'(incr && !decr) - 2'(decr && !incr))); end + + assign size = size_r; + + end else begin + + reg [ADDRW-1:0] used_r; + + always @(posedge clk) begin + if (reset) begin + used_r <= '0; + empty_r <= 1; + full_r <= 0; + end else begin + `ASSERT(~(incr && ~decr) || ~full, ("runtime error: incrementing full counter")); + `ASSERT(~(decr && ~incr) || ~empty, ("runtime error: decrementing empty counter")); + if (incr) begin + if (~decr) begin + empty_r <= 0; + if (used_r == ADDRW'(SIZE-1)) + full_r <= 1; + end + end else if (decr) begin + full_r <= 0; + if (used_r == ADDRW'(1)) + empty_r <= 1; + end + used_r <= $signed(used_r) + ADDRW'($signed(2'(incr) - 2'(decr))); + end + end + + if (SIZE > 1) begin + if (SIZEW > ADDRW) begin + assign size = {full_r, used_r}; + end else begin + assign size = used_r; + end + end else begin + assign size = full_r; + end + end assign empty = empty_r; assign full = full_r; - assign size = {full_r, used_r}; endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_pipe_register.sv b/hw/rtl/libs/VX_pipe_register.sv index f1d3dfe7..f8537ba7 100644 --- a/hw/rtl/libs/VX_pipe_register.sv +++ b/hw/rtl/libs/VX_pipe_register.sv @@ -1,9 +1,22 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_pipe_register #( parameter DATAW = 1, - parameter RESETW = DATAW, + parameter RESETW = 0, parameter DEPTH = 1 ) ( input wire clk, @@ -12,7 +25,6 @@ module VX_pipe_register #( input wire [DATAW-1:0] data_in, output wire [DATAW-1:0] data_out ); - if (DEPTH == 0) begin `UNUSED_VAR (clk) `UNUSED_VAR (reset) @@ -60,18 +72,22 @@ module VX_pipe_register #( assign data_out = {value_r, value_d}; end end else begin - VX_shift_register #( - .DATAW (DATAW), - .RESETW (RESETW), - .DEPTH (DEPTH) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in (data_in), - .data_out (data_out) - ); + wire [DEPTH:0][DATAW-1:0] data_delayed; + assign data_delayed[0] = data_in; + for (genvar i = 1; i <= DEPTH; ++i) begin + VX_pipe_register #( + .DATAW (DATAW), + .RESETW (RESETW) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (data_delayed[i-1]), + .data_out (data_delayed[i]) + ); + end + assign data_out = data_delayed[DEPTH]; end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_popcount.sv b/hw/rtl/libs/VX_popcount.sv index b1500af4..eaec7878 100644 --- a/hw/rtl/libs/VX_popcount.sv +++ b/hw/rtl/libs/VX_popcount.sv @@ -1,49 +1,209 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF +module VX_popcount63( + input wire [5:0] data_in, + output wire [2:0] data_out +); + reg [2:0] sum; + always @(*) begin + case (data_in) + 6'd0: sum=3'd0; 6'd1: sum=3'd1; 6'd2: sum=3'd1; 6'd3: sum=3'd2; + 6'd4: sum=3'd1; 6'd5: sum=3'd2; 6'd6: sum=3'd2; 6'd7: sum=3'd3; + 6'd8: sum=3'd1; 6'd9: sum=3'd2; 6'd10: sum=3'd2; 6'd11: sum=3'd3; + 6'd12: sum=3'd2; 6'd13: sum=3'd3; 6'd14: sum=3'd3; 6'd15: sum=3'd4; + 6'd16: sum=3'd1; 6'd17: sum=3'd2; 6'd18: sum=3'd2; 6'd19: sum=3'd3; + 6'd20: sum=3'd2; 6'd21: sum=3'd3; 6'd22: sum=3'd3; 6'd23: sum=3'd4; + 6'd24: sum=3'd2; 6'd25: sum=3'd3; 6'd26: sum=3'd3; 6'd27: sum=3'd4; + 6'd28: sum=3'd3; 6'd29: sum=3'd4; 6'd30: sum=3'd4; 6'd31: sum=3'd5; + 6'd32: sum=3'd1; 6'd33: sum=3'd2; 6'd34: sum=3'd2; 6'd35: sum=3'd3; + 6'd36: sum=3'd2; 6'd37: sum=3'd3; 6'd38: sum=3'd3; 6'd39: sum=3'd4; + 6'd40: sum=3'd2; 6'd41: sum=3'd3; 6'd42: sum=3'd3; 6'd43: sum=3'd4; + 6'd44: sum=3'd3; 6'd45: sum=3'd4; 6'd46: sum=3'd4; 6'd47: sum=3'd5; + 6'd48: sum=3'd2; 6'd49: sum=3'd3; 6'd50: sum=3'd3; 6'd51: sum=3'd4; + 6'd52: sum=3'd3; 6'd53: sum=3'd4; 6'd54: sum=3'd4; 6'd55: sum=3'd5; + 6'd56: sum=3'd3; 6'd57: sum=3'd4; 6'd58: sum=3'd4; 6'd59: sum=3'd5; + 6'd60: sum=3'd4; 6'd61: sum=3'd5; 6'd62: sum=3'd5; 6'd63: sum=3'd6; + endcase + end + assign data_out = sum; +endmodule + +module VX_popcount32( + input wire [2:0] data_in, + output wire [1:0] data_out +); + reg [1:0] sum; + always @(*) begin + case (data_in) + 3'd0: sum=2'd0; 3'd1: sum=2'd1; 3'd2: sum=2'd1; 3'd3: sum=2'd2; + 3'd4: sum=2'd1; 3'd5: sum=2'd2; 3'd6: sum=2'd2; 3'd7: sum=2'd3; + endcase + end + assign data_out = sum; +endmodule + +module VX_sum33( + input wire [2:0] data_in1, + input wire [2:0] data_in2, + output wire [3:0] data_out +); + reg [3:0] sum; + always @(*) begin + case ({data_in1, data_in2}) + 6'd0: sum=4'd0; 6'd1: sum=4'd1; 6'd2: sum=4'd2; 6'd3: sum=4'd3; + 6'd4: sum=4'd4; 6'd5: sum=4'd5; 6'd6: sum=4'd6; 6'd7: sum=4'd7; + 6'd8: sum=4'd1; 6'd9: sum=4'd2; 6'd10: sum=4'd3; 6'd11: sum=4'd4; + 6'd12: sum=4'd5; 6'd13: sum=4'd6; 6'd14: sum=4'd7; 6'd15: sum=4'd8; + 6'd16: sum=4'd2; 6'd17: sum=4'd3; 6'd18: sum=4'd4; 6'd19: sum=4'd5; + 6'd20: sum=4'd6; 6'd21: sum=4'd7; 6'd22: sum=4'd8; 6'd23: sum=4'd9; + 6'd24: sum=4'd3; 6'd25: sum=4'd4; 6'd26: sum=4'd5; 6'd27: sum=4'd6; + 6'd28: sum=4'd7; 6'd29: sum=4'd8; 6'd30: sum=4'd9; 6'd31: sum=4'd10; + 6'd32: sum=4'd4; 6'd33: sum=4'd5; 6'd34: sum=4'd6; 6'd35: sum=4'd7; + 6'd36: sum=4'd8; 6'd37: sum=4'd9; 6'd38: sum=4'd10; 6'd39: sum=4'd11; + 6'd40: sum=4'd5; 6'd41: sum=4'd6; 6'd42: sum=4'd7; 6'd43: sum=4'd8; + 6'd44: sum=4'd9; 6'd45: sum=4'd10; 6'd46: sum=4'd11; 6'd47: sum=4'd12; + 6'd48: sum=4'd6; 6'd49: sum=4'd7; 6'd50: sum=4'd8; 6'd51: sum=4'd9; + 6'd52: sum=4'd10; 6'd53: sum=4'd11; 6'd54: sum=4'd12; 6'd55: sum=4'd13; + 6'd56: sum=4'd7; 6'd57: sum=4'd8; 6'd58: sum=4'd9; 6'd59: sum=4'd10; + 6'd60: sum=4'd11; 6'd61: sum=4'd12; 6'd62: sum=4'd13; 6'd63: sum=4'd14; + endcase + end + assign data_out = sum; +endmodule + module VX_popcount #( parameter MODEL = 1, parameter N = 1, - parameter M = $clog2(N+1) + parameter M = `CLOG2(N+1) ) ( - input wire [N-1:0] in_i, - output wire [M-1:0] cnt_o + input wire [N-1:0] data_in, + output wire [M-1:0] data_out ); - `UNUSED_PARAM (MODEL) + `UNUSED_PARAM (MODEL) `ifndef SYNTHESIS - assign cnt_o = $countones(in_i); -`else -`ifdef QUARTUS - assign cnt_o = $countones(in_i); + assign data_out = $countones(data_in); +`elsif QUARTUS + assign data_out = $countones(data_in); `else if (N == 1) begin - assign cnt_o = in_i; + assign data_out = data_in; + + end else if (N <= 3) begin + + reg [2:0] t_in; + wire [1:0] t_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount32 pc32(t_in, t_out); + assign data_out = t_out[M-1:0]; + + end else if (N <= 6) begin + + reg [5:0] t_in; + wire [2:0] t_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63(t_in, t_out); + assign data_out = t_out[M-1:0]; + + end else if (N <= 9) begin + + reg [8:0] t_in; + wire [4:0] t1_out; + wire [3:0] t2_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63(t_in[5:0], t1_out[2:0]); + VX_popcount32 pc32(t_in[8:6], t1_out[4:3]); + VX_sum33 sum33(t1_out[2:0], {1'b0, t1_out[4:3]}, t2_out); + assign data_out = t2_out[M-1:0]; + + end else if (N <= 12) begin + + reg [11:0] t_in; + wire [5:0] t1_out; + wire [3:0] t2_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]); + VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]); + VX_sum33 sum33(t1_out[2:0], t1_out[5:3], t2_out); + assign data_out = t2_out[M-1:0]; + + end else if (N <= 18) begin + + reg [17:0] t_in; + wire [8:0] t1_out; + wire [5:0] t2_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]); + VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]); + VX_popcount63 pc63c(t_in[17:12], t1_out[8:6]); + VX_popcount32 pc32a({t1_out[0], t1_out[3], t1_out[6]}, t2_out[1:0]); + VX_popcount32 pc32b({t1_out[1], t1_out[4], t1_out[7]}, t2_out[3:2]); + VX_popcount32 pc32c({t1_out[2], t1_out[5], t1_out[8]}, t2_out[5:4]); + assign data_out = {2'b0,t2_out[1:0]} + {1'b0,t2_out[3:2],1'b0} + {t2_out[5:4],2'b0}; end else if (MODEL == 1) begin - `IGNORE_WARNINGS_BEGIN - localparam PN = 1 << $clog2(N); - localparam LOGPN = $clog2(PN); - - wire [M-1:0] tmp [0:PN-1] [0:PN-1]; - - for (genvar i = 0; i < N; ++i) begin - assign tmp[0][i] = in_i[i]; - end - for (genvar i = N; i < PN; ++i) begin - assign tmp[0][i] = '0; - end + localparam PN = 1 << `CLOG2(N); + localparam LOGPN = `CLOG2(PN); + + `IGNORE_UNOPTFLAT_BEGIN + wire [M-1:0] tmp [LOGPN-1:0][PN-1:0]; + `IGNORE_UNOPTFLAT_END for (genvar j = 0; j < LOGPN; ++j) begin - for (genvar i = 0; i < (1 << (LOGPN-j-1)); ++i) begin - assign tmp[j+1][i] = tmp[j][i*2] + tmp[j][i*2+1]; + localparam D = j + 1; + localparam Q = (D < LOGPN) ? (D + 1) : M; + for (genvar i = 0; i < (1 << (LOGPN-j-1)); ++i) begin + localparam l = i * 2; + localparam r = i * 2 + 1; + wire [Q-1:0] res; + if (j == 0) begin + if (r < N) begin + assign res = data_in[l] + data_in[r]; + end else if (l < N) begin + assign res = 2'(data_in[l]); + end else begin + assign res = 2'b0; + end + end else begin + assign res = D'(tmp[j-1][l]) + D'(tmp[j-1][r]); + end + assign tmp[j][i] = M'(res); end end - assign cnt_o = tmp[LOGPN][0]; - `IGNORE_WARNINGS_END + assign data_out = tmp[LOGPN-1][0]; + end else begin reg [M-1:0] cnt_r; @@ -51,17 +211,14 @@ module VX_popcount #( always @(*) begin cnt_r = '0; for (integer i = 0; i < N; ++i) begin - `IGNORE_WARNINGS_BEGIN - cnt_r = cnt_r + in_i[i]; - `IGNORE_WARNINGS_END + cnt_r = cnt_r + M'(data_in[i]); end end - assign cnt_o = cnt_r; + assign data_out = cnt_r; end `endif -`endif endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_fixed_arbiter.sv b/hw/rtl/libs/VX_priority_arbiter.sv similarity index 52% rename from hw/rtl/libs/VX_fixed_arbiter.sv rename to hw/rtl/libs/VX_priority_arbiter.sv index 5fee1308..c47bc63a 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.sv +++ b/hw/rtl/libs/VX_priority_arbiter.sv @@ -1,28 +1,40 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF -module VX_fixed_arbiter #( +module VX_priority_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, - parameter LOG_NUM_REQS = $clog2(NUM_REQS) + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) ) ( input wire clk, input wire reset, input wire [NUM_REQS-1:0] requests, - input wire enable, + input wire unlock, output wire [LOG_NUM_REQS-1:0] grant_index, output wire [NUM_REQS-1:0] grant_onehot, output wire grant_valid - ); - +); `UNUSED_PARAM (LOCK_ENABLE) `UNUSED_VAR (clk) `UNUSED_VAR (reset) - `UNUSED_VAR (enable) + `UNUSED_VAR (unlock) if (NUM_REQS == 1) begin - assign grant_index = 0; + assign grant_index = '0; assign grant_onehot = requests; assign grant_valid = requests[0]; @@ -30,7 +42,7 @@ module VX_fixed_arbiter #( VX_priority_encoder #( .N (NUM_REQS) - ) tid_select ( + ) priority_encoder ( .data_in (requests), .index (grant_index), .onehot (grant_onehot), @@ -40,4 +52,4 @@ module VX_fixed_arbiter #( end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_priority_encoder.sv b/hw/rtl/libs/VX_priority_encoder.sv index ea5e27d7..5a08e341 100644 --- a/hw/rtl/libs/VX_priority_encoder.sv +++ b/hw/rtl/libs/VX_priority_encoder.sv @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF @@ -14,7 +27,7 @@ module VX_priority_encoder #( ); wire [N-1:0] reversed; - if (REVERSE) begin + if (REVERSE != 0) begin for (genvar i = 0; i < N; ++i) begin assign reversed[N-i-1] = data_in[i]; end @@ -25,7 +38,7 @@ module VX_priority_encoder #( if (N == 1) begin assign onehot = reversed; - assign index = 0; + assign index = '0; assign valid_out = reversed; end else if (N == 2) begin @@ -47,11 +60,12 @@ module VX_priority_encoder #( ); VX_lzc #( - .N (N) + .N (N), + .REVERSE (1) ) lzc ( - .in_i (reversed), - .cnt_o (index), - `UNUSED_PIN (valid_o) + .data_in (reversed), + .data_out (index), + `UNUSED_PIN (valid_out) ); assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1}; @@ -67,23 +81,25 @@ module VX_priority_encoder #( assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0]; VX_lzc #( - .N (N) + .N (N), + .REVERSE (1) ) lzc ( - .in_i (reversed), - .cnt_o (index), - .valid_o (valid_out) + .data_in (reversed), + .data_out (index), + .valid_out (valid_out) ); end else if (MODEL == 3) begin - assign onehot = reversed & ~(reversed-1); + assign onehot = reversed & -reversed; VX_lzc #( - .N (N) + .N (N), + .REVERSE (1) ) lzc ( - .in_i (reversed), - .cnt_o (index), - .valid_o (valid_out) + .data_in (reversed), + .data_out (index), + .valid_out (valid_out) ); end else begin @@ -97,7 +113,7 @@ module VX_priority_encoder #( for (integer i = N-1; i >= 0; --i) begin if (reversed[i]) begin index_r = LN'(i); - onehot_r = 0; + onehot_r = '0; onehot_r[i] = 1'b1; end end @@ -110,4 +126,4 @@ module VX_priority_encoder #( end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_reduce.sv b/hw/rtl/libs/VX_reduce.sv new file mode 100644 index 00000000..ac011756 --- /dev/null +++ b/hw/rtl/libs/VX_reduce.sv @@ -0,0 +1,72 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_reduce #( + parameter DATAW_IN = 1, + parameter DATAW_OUT = DATAW_IN, + parameter N = 1, + parameter `STRING OP = "+" +) ( + input wire [N-1:0][DATAW_IN-1:0] data_in, + output wire [DATAW_OUT-1:0] data_out +); + if (N == 1) begin + assign data_out = DATAW_OUT'(data_in[0]); + end else begin + localparam int N_A = N / 2; + localparam int N_B = N - N_A; + + wire [N_A-1:0][DATAW_IN-1:0] in_A; + wire [N_B-1:0][DATAW_IN-1:0] in_B; + wire [DATAW_OUT-1:0] out_A, out_B; + + for (genvar i = 0; i < N_A; i++) begin + assign in_A[i] = data_in[i]; + end + + for (genvar i = 0; i < N_B; i++) begin + assign in_B[i] = data_in[N_A + i]; + end + + VX_reduce #( + .DATAW_IN (DATAW_IN), + .DATAW_OUT (DATAW_OUT), + .N (N_A), + .OP (OP) + ) reduce_A ( + .data_in (in_A), + .data_out (out_A) + ); + + VX_reduce #( + .DATAW_IN (DATAW_IN), + .DATAW_OUT (DATAW_OUT), + .N (N_B), + .OP (OP) + ) reduce_B ( + .data_in (in_B), + .data_out (out_B) + ); + + if (OP == "+") assign data_out = out_A + out_B; + else if (OP == "^") assign data_out = out_A ^ out_B; + else if (OP == "&") assign data_out = out_A & out_B; + else if (OP == "|") assign data_out = out_A | out_B; + else `ERROR(("invalid parameter")); + end + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_reset_relay.sv b/hw/rtl/libs/VX_reset_relay.sv index 94b24250..d2469a1c 100644 --- a/hw/rtl/libs/VX_reset_relay.sv +++ b/hw/rtl/libs/VX_reset_relay.sv @@ -1,31 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" +`TRACING_OFF module VX_reset_relay #( - parameter N = 1, - parameter DEPTH = 1 + parameter N = 1, + parameter MAX_FANOUT = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, output wire [N-1:0] reset_o -); - - if (DEPTH > 1) begin - `PRESERVE_REG `DISABLE_BRAM reg [N-1:0] reset_r [DEPTH-1:0]; - always @(posedge clk) begin - for (integer i = DEPTH-1; i > 0; --i) - reset_r[i] <= reset_r[i-1]; - reset_r[0] <= {N{reset}}; - end - assign reset_o = reset_r[DEPTH-1]; - end else if (DEPTH == 1) begin - `PRESERVE_REG reg [N-1:0] reset_r; - always @(posedge clk) begin - reset_r <= {N{reset}}; +); + if (MAX_FANOUT >= 0 && N > (MAX_FANOUT + MAX_FANOUT/2)) begin + localparam F = `UP(MAX_FANOUT); + localparam R = N / F; + `PRESERVE_NET reg [R-1:0] reset_r; + for (genvar i = 0; i < R; ++i) begin + always @(posedge clk) begin + reset_r[i] <= reset; + end + end + for (genvar i = 0; i < N; ++i) begin + assign reset_o[i] = reset_r[i / F]; end - assign reset_o = reset_r; end else begin `UNUSED_VAR (clk) assign reset_o = {N{reset}}; end -endmodule \ No newline at end of file +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_rr_arbiter.sv b/hw/rtl/libs/VX_rr_arbiter.sv index d9b9ae12..d4d6fb1a 100644 --- a/hw/rtl/libs/VX_rr_arbiter.sv +++ b/hw/rtl/libs/VX_rr_arbiter.sv @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF @@ -5,23 +18,23 @@ module VX_rr_arbiter #( parameter NUM_REQS = 1, parameter LOCK_ENABLE = 0, parameter MODEL = 1, - parameter LOG_NUM_REQS = $clog2(NUM_REQS) + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) ) ( input wire clk, input wire reset, - input wire enable, + input wire unlock, input wire [NUM_REQS-1:0] requests, output wire [LOG_NUM_REQS-1:0] grant_index, output wire [NUM_REQS-1:0] grant_onehot, output wire grant_valid - ); - +); if (NUM_REQS == 1) begin `UNUSED_VAR (clk) `UNUSED_VAR (reset) + `UNUSED_VAR (unlock) - assign grant_index = 0; + assign grant_index = '0; assign grant_onehot = requests; assign grant_valid = requests[0]; @@ -41,8 +54,8 @@ module VX_rr_arbiter #( always @(posedge clk) begin if (reset) begin - state <= 0; - end else if (!LOCK_ENABLE || enable) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin state <= grant_index_r; end end @@ -51,7 +64,37 @@ module VX_rr_arbiter #( assign grant_onehot = grant_onehot_r; assign grant_valid = (| requests); - end else if (NUM_REQS == 4) begin + end /*else if (NUM_REQS == 3) begin + + reg [LOG_NUM_REQS-1:0] grant_index_r; + reg [NUM_REQS-1:0] grant_onehot_r; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 5'b00_001, + 5'b01_0?1, + 5'b10_??1: begin grant_onehot_r = 3'b001; grant_index_r = LOG_NUM_REQS'(0); end + 5'b00_?1?, + 5'b01_010, + 5'b10_?10: begin grant_onehot_r = 3'b010; grant_index_r = LOG_NUM_REQS'(1); end + default: begin grant_onehot_r = 3'b100; grant_index_r = LOG_NUM_REQS'(2); end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin + state <= grant_index_r; + end + end + + assign grant_index = grant_index_r; + assign grant_onehot = grant_onehot_r; + assign grant_valid = (| requests); + + end */else if (NUM_REQS == 4) begin reg [LOG_NUM_REQS-1:0] grant_index_r; reg [NUM_REQS-1:0] grant_onehot_r; @@ -77,8 +120,8 @@ module VX_rr_arbiter #( always @(posedge clk) begin if (reset) begin - state <= 0; - end else if (!LOCK_ENABLE || enable) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin state <= grant_index_r; end end @@ -87,7 +130,171 @@ module VX_rr_arbiter #( assign grant_onehot = grant_onehot_r; assign grant_valid = (| requests); - end else if (NUM_REQS == 8) begin + end /*else if (NUM_REQS == 5) begin + + reg [LOG_NUM_REQS-1:0] grant_index_r; + reg [NUM_REQS-1:0] grant_onehot_r; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 8'b000_00001, + 8'b001_000?1, + 8'b010_00??1, + 8'b011_0???1, + 8'b100_????1: begin grant_onehot_r = 5'b00001; grant_index_r = LOG_NUM_REQS'(0); end + 8'b000_???1?, + 8'b001_00010, + 8'b010_00?10, + 8'b011_0??10, + 8'b100_???10: begin grant_onehot_r = 5'b00010; grant_index_r = LOG_NUM_REQS'(1); end + 8'b000_??10?, + 8'b001_??1??, + 8'b010_00100, + 8'b011_0?100, + 8'b100_??100: begin grant_onehot_r = 5'b00100; grant_index_r = LOG_NUM_REQS'(2); end + 8'b000_?100?, + 8'b001_?10??, + 8'b010_?1???, + 8'b011_01000, + 8'b100_?1000: begin grant_onehot_r = 5'b01000; grant_index_r = LOG_NUM_REQS'(3); end + default: begin grant_onehot_r = 5'b10000; grant_index_r = LOG_NUM_REQS'(4); end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin + state <= grant_index_r; + end + end + + assign grant_index = grant_index_r; + assign grant_onehot = grant_onehot_r; + assign grant_valid = (| requests); + + end else if (NUM_REQS == 6) begin + + reg [LOG_NUM_REQS-1:0] grant_index_r; + reg [NUM_REQS-1:0] grant_onehot_r; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 9'b000_000001, + 9'b001_0000?1, + 9'b010_000??1, + 9'b011_00???1, + 9'b100_0????1, + 9'b101_?????1: begin grant_onehot_r = 6'b000001; grant_index_r = LOG_NUM_REQS'(0); end + 9'b000_????1?, + 9'b001_000010, + 9'b010_000?10, + 9'b011_00??10, + 9'b100_0???10, + 9'b101_????10: begin grant_onehot_r = 6'b000010; grant_index_r = LOG_NUM_REQS'(1); end + 9'b000_???10?, + 9'b001_???1??, + 9'b010_000100, + 9'b011_00?100, + 9'b100_0??100, + 9'b101_???100: begin grant_onehot_r = 6'b000100; grant_index_r = LOG_NUM_REQS'(2); end + 9'b000_??100?, + 9'b001_??10??, + 9'b010_??1???, + 9'b011_001000, + 9'b100_0?1000, + 9'b101_??1000: begin grant_onehot_r = 6'b001000; grant_index_r = LOG_NUM_REQS'(3); end + 9'b000_?1000?, + 9'b001_?100??, + 9'b010_?10???, + 9'b011_?1????, + 9'b100_010000, + 9'b101_?10000: begin grant_onehot_r = 6'b010000; grant_index_r = LOG_NUM_REQS'(4); end + default: begin grant_onehot_r = 6'b100000; grant_index_r = LOG_NUM_REQS'(5); end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin + state <= grant_index_r; + end + end + + assign grant_index = grant_index_r; + assign grant_onehot = grant_onehot_r; + assign grant_valid = (| requests); + + end else if (NUM_REQS == 7) begin + + reg [LOG_NUM_REQS-1:0] grant_index_r; + reg [NUM_REQS-1:0] grant_onehot_r; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 10'b000_000001, + 10'b001_0000?1, + 10'b010_000??1, + 10'b011_00???1, + 10'b100_00???1, + 10'b101_0????1, + 10'b110_?????1: begin grant_onehot_r = 7'b0000001; grant_index_r = LOG_NUM_REQS'(0); end + 10'b000_?????1?, + 10'b001_0000010, + 10'b010_0000?10, + 10'b011_000??10, + 10'b100_00???10, + 10'b101_0????10, + 10'b110_?????10: begin grant_onehot_r = 7'b0000010; grant_index_r = LOG_NUM_REQS'(1); end + 10'b000_????10?, + 10'b001_????1??, + 10'b010_0000100, + 10'b011_000?100, + 10'b100_00??100, + 10'b101_0???100, + 10'b110_????100: begin grant_onehot_r = 7'b0000100; grant_index_r = LOG_NUM_REQS'(2); end + 10'b000_???100?, + 10'b001_???10??, + 10'b010_???1???, + 10'b011_0001000, + 10'b100_00?1000, + 10'b101_0??1000, + 10'b110_???1000: begin grant_onehot_r = 7'b0001000; grant_index_r = LOG_NUM_REQS'(3); end + 10'b000_??1000?, + 10'b001_??100??, + 10'b010_??10???, + 10'b011_??1????, + 10'b100_0010000, + 10'b101_0?10000, + 10'b110_??10000: begin grant_onehot_r = 7'b0010000; grant_index_r = LOG_NUM_REQS'(4); end + 10'b000_?10000?, + 10'b001_?1000??, + 10'b010_?100???, + 10'b011_?10????, + 10'b100_?1?????, + 10'b101_0100000, + 10'b110_?100000: begin grant_onehot_r = 7'b0100000; grant_index_r = LOG_NUM_REQS'(5); end + default: begin grant_onehot_r = 7'b1000000; grant_index_r = LOG_NUM_REQS'(6); end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin + state <= grant_index_r; + end + end + + assign grant_index = grant_index_r; + assign grant_onehot = grant_onehot_r; + assign grant_valid = (| requests); + + end */else if (NUM_REQS == 8) begin reg [LOG_NUM_REQS-1:0] grant_index_r; reg [NUM_REQS-1:0] grant_onehot_r; @@ -157,8 +364,8 @@ module VX_rr_arbiter #( always @(posedge clk) begin if (reset) begin - state <= 0; - end else if (!LOCK_ENABLE || enable) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin state <= grant_index_r; end end @@ -169,9 +376,9 @@ module VX_rr_arbiter #( end else if (MODEL == 1) begin - `IGNORE_WARNINGS_BEGIN + `IGNORE_UNOPTFLAT_BEGIN wire [NUM_REQS-1:0] mask_higher_pri_regs, unmask_higher_pri_regs; - `IGNORE_WARNINGS_END + `IGNORE_UNOPTFLAT_END wire [NUM_REQS-1:0] grant_masked, grant_unmasked; reg [NUM_REQS-1:0] pointer_reg; @@ -192,7 +399,7 @@ module VX_rr_arbiter #( always @(posedge clk) begin if (reset) begin pointer_reg <= {NUM_REQS{1'b1}}; - end else if (!LOCK_ENABLE || enable) begin + end else if (!LOCK_ENABLE || unlock) begin if (|req_masked) begin pointer_reg <= mask_higher_pri_regs; end else if (|requests) begin @@ -235,8 +442,8 @@ module VX_rr_arbiter #( always @(posedge clk) begin if (reset) begin - state <= 0; - end else if (!LOCK_ENABLE || enable) begin + state <= '0; + end else if (!LOCK_ENABLE || unlock) begin state <= grant_index_r; end end @@ -247,4 +454,4 @@ module VX_rr_arbiter #( end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_scan.sv b/hw/rtl/libs/VX_scan.sv index 2ccec7e9..f263dd21 100644 --- a/hw/rtl/libs/VX_scan.sv +++ b/hw/rtl/libs/VX_scan.sv @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" // Fast Paralllel scan using Kogge-Stone style prefix tree with configurable operator @@ -12,14 +25,14 @@ module VX_scan #( input wire [N-1:0] data_in, output wire [N-1:0] data_out ); -`IGNORE_WARNINGS_BEGIN - - localparam LOGN = $clog2(N); + localparam LOGN = `CLOG2(N); +`IGNORE_UNOPTFLAT_BEGIN wire [LOGN:0][N-1:0] t; +`IGNORE_UNOPTFLAT_END // reverses bits - if (REVERSE) begin + if (REVERSE != 0) begin assign t[0] = data_in; end else begin assign t[0] = {<<{data_in}}; @@ -35,7 +48,7 @@ module VX_scan #( end else begin // general case wire [N-1:0] fill; - for (genvar i = 0; i < LOGN; i++) begin + for (genvar i = 0; i < LOGN; ++i) begin wire [N-1:0] shifted = N'({fill, t[i]} >> (1<= waddr_end)) begin - `ifdef DBG_TRACE_SCOPE - dpi_trace("%d: *** scope: recording stop - waddr=(%0d, %0d)\n", $time, waddr, waddr_end); - `endif - waddr <= waddr; // keep last address - recording <= 0; - data_valid <= 1; - read_delta <= 1; - end - end - - if (bus_read - && (get_cmd == GET_DATA) - && data_valid) begin - if (read_delta) begin - read_delta <= 0; - end else begin - if (DATAW > BUSW) begin - if (read_offset < $bits(read_offset)'(DATAW-BUSW)) begin - read_offset <= read_offset + $bits(read_offset)'(BUSW); - end else begin - raddr <= raddr + $bits(raddr)'(1); - read_offset <= 0; - read_delta <= 1; - if (raddr == waddr) begin - data_valid <= 0; - end - end - end else begin - raddr <= raddr + 1; - read_delta <= 1; - if (raddr == waddr) begin - data_valid <= 0; - end - end - end - end - end - - if (recording) begin - if (UPDW_ENABLE) begin - if (delta_flush - || changed - || (trigger_id != prev_trigger_id)) begin - delta_store[waddr] <= delta; - data_store[waddr] <= data_in; - end - end else begin - delta_store[waddr] <= 0; - data_store[waddr] <= data_in; - end - end - end - - always @(*) begin - case (get_cmd) - GET_VALID : bus_out_r = BUSW'(data_valid); - GET_WIDTH : bus_out_r = BUSW'(DATAW); - GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1); - GET_OFFSET: bus_out_r = BUSW'(start_time); - /* verilator lint_off WIDTH */ - GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset); - /* verilator lint_on WIDTH */ - default : bus_out_r = 0; - endcase - end - - assign bus_out = bus_out_r; - -`ifdef DBG_TRACE_SCOPE - always @(posedge clk) begin - if (bus_read) begin - dpi_trace("%d: scope-read: cmd=%0d, addr=%0d, value=%0h\n", $time, get_cmd, raddr, bus_out); - end - if (bus_write) begin - dpi_trace("%d: scope-write: cmd=%0d, value=%0d\n", $time, cmd_type, cmd_data); - end - end -`endif - -endmodule -`TRACING_ON \ No newline at end of file diff --git a/hw/rtl/libs/VX_scope_switch.sv b/hw/rtl/libs/VX_scope_switch.sv new file mode 100644 index 00000000..68101997 --- /dev/null +++ b/hw/rtl/libs/VX_scope_switch.sv @@ -0,0 +1,63 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_scope_switch #( + parameter N = 0 +) ( + input wire clk, + input wire reset, + input wire req_in, + output wire req_out [N], + input wire rsp_in [N], + output wire rsp_out +); + if (N > 1) begin + reg req_out_r [N]; + reg rsp_out_r; + + always @(posedge clk) begin + if (reset) begin + for (integer i = 0; i < N; ++i) begin + req_out_r[i] <= 0; + end + rsp_out_r <= 0; + end else begin + for (integer i = 0; i < N; ++i) begin + req_out_r[i] <= req_in; + end + rsp_out_r <= 0; + for (integer i = 0; i < N; ++i) begin + if (rsp_in[i]) + rsp_out_r <= 1; + end + end + end + + assign req_out = req_out_r; + assign rsp_out = rsp_out_r; + + end else begin + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + assign req_out[0] = req_in; + assign rsp_out = rsp_in[0]; + + end + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_scope_tap.sv b/hw/rtl/libs/VX_scope_tap.sv new file mode 100644 index 00000000..c5ba778a --- /dev/null +++ b/hw/rtl/libs/VX_scope_tap.sv @@ -0,0 +1,313 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_scope_tap #( + parameter SCOPE_ID = 0, // scope identifier + parameter SCOPE_IDW = 8, // scope identifier width + parameter TRIGGERW = 0, // trigger signals width + parameter PROBEW = 0, // probe signal width + parameter SIZE = 256, // trace buffer size + parameter IDLE_CTRW = 16 // idle time between triggers counter width +) ( + input wire clk, + input wire reset, + input wire start, + input wire stop, + input wire [TRIGGERW-1:0] triggers, + input wire [PROBEW-1:0] probes, + input wire bus_in, + output wire bus_out +); + localparam TX_DATAW = 64; + localparam TX_DATA_BITS = `LOG2UP(TX_DATAW); + localparam DATAW = PROBEW + TRIGGERW; + localparam DATA_BITS = `LOG2UP(DATAW); + localparam ADDRW = `CLOG2(SIZE); + localparam TRIGGER_ENABLE = (TRIGGERW != 0); + localparam MAX_IDLE_CTR = (2 ** IDLE_CTRW) - 1; + + localparam CTRL_STATE_IDLE = 2'd0; + localparam CTRL_STATE_RECV = 2'd1; + localparam CTRL_STATE_CMD = 2'd2; + localparam CTRL_STATE_SEND = 2'd3; + localparam CTRL_STATE_BITS = 2; + + localparam TAP_STATE_IDLE = 2'd0; + localparam TAP_STATE_WAIT = 2'd1; + localparam TAP_STATE_RUN = 2'd2; + localparam TAP_STATE_BITS = 2; + + localparam CMD_GET_WIDTH = 3'd0; + localparam CMD_GET_COUNT = 3'd1; + localparam CMD_GET_START = 3'd2; + localparam CMD_GET_DATA = 3'd3; + localparam CMD_SET_START = 3'd4; + localparam CMD_SET_STOP = 3'd5; + localparam CMD_TYPE_BITS = 3; + + localparam GET_TYPE_WIDTH = 2'd0; + localparam GET_TYPE_COUNT = 2'd1; + localparam GET_TYPE_START = 2'd2; + localparam GET_TYPE_DATA = 2'd3; + localparam GET_TYPE_BITS = 2; + + `NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [SIZE-1:0]; + `NO_RW_RAM_CHECK reg [IDLE_CTRW-1:0] delta_store [SIZE-1:0]; + + reg [TRIGGERW-1:0] prev_triggers; + reg [IDLE_CTRW-1:0] delta; + reg [63:0] timestamp, start_time; + + reg [ADDRW-1:0] waddr, waddr_end; + + reg cmd_start, delta_flush; + + reg [63:0] start_delay, delay_cntr; + + reg [TAP_STATE_BITS-1:0] tap_state; + reg [CTRL_STATE_BITS-1:0] ctrl_state; + reg [GET_TYPE_BITS-1:0] get_type; + + reg [TX_DATA_BITS-1:0] ser_tx_ctr; + reg [DATA_BITS-1:0] read_offset; + reg [ADDRW-1:0] raddr; + reg read_data; + + // + // trace capture + // + + wire [ADDRW-1:0] raddr_n = raddr + 1; + + wire [ADDRW:0] count = (ADDRW+1)'(waddr) + 1; + + always @(posedge clk) begin + if (reset) begin + tap_state <= TAP_STATE_IDLE; + raddr <= '0; + waddr <= '0; + delta <= '0; + prev_triggers <= '0; + read_offset <= '0; + read_data <= 0; + timestamp <= '0; + end else begin + timestamp <= timestamp + 1; + + case (tap_state) + TAP_STATE_IDLE: begin + if (start || cmd_start) begin + delta <= '0; + delta_flush <= 1; + if (0 == start_delay) begin + tap_state <= TAP_STATE_RUN; + start_time <= timestamp; + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%d: *** scope #%0d: recording start - time=%0d\n", $time, SCOPE_ID, timestamp)); + `endif + end else begin + tap_state <= TAP_STATE_WAIT; + delay_cntr <= start_delay; + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%d: *** scope #%0d: delayed start - time=%0d\n", $time, SCOPE_ID, start_delay)); + `endif + end + end + end + TAP_STATE_WAIT: begin + delay_cntr <= delay_cntr - 1; + if (1 == delay_cntr) begin + tap_state <= TAP_STATE_RUN; + start_time <= timestamp; + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%d: *** scope #%0d: recording start - time=%0d\n", $time, SCOPE_ID, timestamp)); + `endif + end + end + TAP_STATE_RUN: begin + if (TRIGGER_ENABLE != 0) begin + if (delta_flush || (triggers != prev_triggers)) begin + data_store[waddr] <= {probes, triggers}; + delta_store[waddr] <= delta; + waddr <= waddr + 1; + delta <= '0; + delta_flush <= 0; + end else begin + delta <= delta + 1; + delta_flush <= (delta == (MAX_IDLE_CTR-1)); + end + prev_triggers <= triggers; + end else begin + data_store[waddr] <= {probes, triggers}; + delta_store[waddr] <= '0; + waddr <= waddr + 1; + end + if (stop || (waddr >= waddr_end)) begin + waddr <= waddr; + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%d: *** scope #%0d: recording stop - waddr=(%0d, %0d)\n", $time, SCOPE_ID, waddr, waddr_end)); + `endif + tap_state <= TAP_STATE_IDLE; + end + end + default:; + endcase + + if (ctrl_state == CTRL_STATE_SEND + && get_type == GET_TYPE_DATA + && ser_tx_ctr == 0) begin + if (~read_data) begin + read_data <= 1; + end else begin + if (DATAW > TX_DATAW) begin + `IGNORE_WARNINGS_BEGIN + if (read_offset < DATA_BITS'(DATAW-TX_DATAW)) begin + read_offset <= read_offset + DATA_BITS'(TX_DATAW); + end else begin + raddr <= raddr_n; + read_data <= 0; + read_offset <= '0; + end + `IGNORE_WARNINGS_END + end else begin + raddr <= raddr_n; + read_data <= 0; + end + if (raddr_n == waddr) begin + raddr <= 0; + end + end + end + end + end + + // + // command controller + // + + reg bus_out_r; + + reg [TX_DATAW-1:0] ser_buf_in; + wire [TX_DATAW-1:0] ser_buf_in_n = {ser_buf_in[TX_DATAW-2:0], bus_in}; + `UNUSED_VAR (ser_buf_in) + + wire [CMD_TYPE_BITS-1:0] cmd_type = ser_buf_in[CMD_TYPE_BITS-1:0]; + wire [SCOPE_IDW-1:0] cmd_scope_id = ser_buf_in_n[CMD_TYPE_BITS +: SCOPE_IDW]; + wire [TX_DATAW-CMD_TYPE_BITS-SCOPE_IDW-1:0] cmd_data = ser_buf_in[TX_DATAW-1:CMD_TYPE_BITS+SCOPE_IDW]; + + wire [TX_DATAW-1:0] data_chunk = TX_DATAW'(DATAW'(data_store[raddr] >> read_offset)); + wire [TX_DATAW-1:0] get_data = read_data ? data_chunk : TX_DATAW'(delta_store[raddr]); + + always @(posedge clk) begin + if (reset) begin + ctrl_state <= CTRL_STATE_IDLE; + cmd_start <= 0; + start_delay <= '0; + waddr_end <= ADDRW'(SIZE-1); + bus_out_r <= 0; + end else begin + bus_out_r <= 0; + cmd_start <= 0; + + case (ctrl_state) + CTRL_STATE_IDLE: begin + if (bus_in) begin + ctrl_state <= CTRL_STATE_RECV; + end + ser_tx_ctr <= TX_DATA_BITS'(TX_DATAW-1); + end + CTRL_STATE_RECV: begin + ser_tx_ctr <= ser_tx_ctr - 1; + ser_buf_in <= ser_buf_in_n; + if (ser_tx_ctr == 0) begin + ctrl_state <= (cmd_scope_id == SCOPE_ID) ? CTRL_STATE_CMD : CTRL_STATE_IDLE; + end + end + CTRL_STATE_CMD: begin + ctrl_state <= CTRL_STATE_IDLE; + case (cmd_type) + CMD_SET_START: begin + start_delay <= 64'(cmd_data); + cmd_start <= 1; + end + CMD_SET_STOP: begin + waddr_end <= ADDRW'(cmd_data); + end + CMD_GET_WIDTH, + CMD_GET_START, + CMD_GET_COUNT, + CMD_GET_DATA: begin + ctrl_state <= CTRL_STATE_SEND; + get_type <= GET_TYPE_BITS'(cmd_type); + ser_tx_ctr <= TX_DATA_BITS'(TX_DATAW-1); + bus_out_r <= 1; + end + default:; + endcase + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%d: *** scope #%0d: CMD: type=%0d\n", $time, SCOPE_ID, cmd_type)); + `endif + end + CTRL_STATE_SEND: begin + ser_tx_ctr <= ser_tx_ctr - 1; + case (get_type) + GET_TYPE_WIDTH: begin + bus_out_r <= 1'(DATAW >> ser_tx_ctr); + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + `TRACE(2, ("%d: *** scope #%0d: SEND width=%0d\n", $time, SCOPE_ID, DATAW)); + end + `endif + end + GET_TYPE_COUNT: begin + bus_out_r <= 1'(count >> ser_tx_ctr); + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + `TRACE(2, ("%d: *** scope #%0d: SEND count=%0d\n", $time, SCOPE_ID, count)); + end + `endif + end + GET_TYPE_START: begin + bus_out_r <= 1'(start_time >> ser_tx_ctr); + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + `TRACE(2, ("%d: *** scope #%0d: SEND start=%0d\n", $time, SCOPE_ID, start_time)); + end + `endif + end + GET_TYPE_DATA: begin + bus_out_r <= 1'(get_data >> ser_tx_ctr); + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + `TRACE(2, ("%d: *** scope #%0d: SEND data=%0d\n", $time, SCOPE_ID, get_data)); + end + `endif + end + default:; + endcase + if (ser_tx_ctr == 0) begin + ctrl_state <= CTRL_STATE_IDLE; + end + end + default:; + endcase + end + end + + assign bus_out = bus_out_r; + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_serial_div.sv b/hw/rtl/libs/VX_serial_div.sv index a87b7a5d..e7af4000 100644 --- a/hw/rtl/libs/VX_serial_div.sv +++ b/hw/rtl/libs/VX_serial_div.sv @@ -1,32 +1,41 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_serial_div #( - parameter WIDTHN = 1, - parameter WIDTHD = 1, - parameter WIDTHQ = 1, - parameter WIDTHR = 1, - parameter LANES = 1, - parameter TAGW = 1 + parameter WIDTHN = 32, + parameter WIDTHD = 32, + parameter WIDTHQ = 32, + parameter WIDTHR = 32, + parameter LANES = 1 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, - input wire valid_in, - output wire ready_in, + input wire strobe, + output wire busy, + + input wire is_signed, input wire [LANES-1:0][WIDTHN-1:0] numer, - input wire [LANES-1:0][WIDTHD-1:0] denom, - input wire signed_mode, - input wire [TAGW-1:0] tag_in, + input wire [LANES-1:0][WIDTHD-1:0] denom, output wire [LANES-1:0][WIDTHQ-1:0] quotient, - output wire [LANES-1:0][WIDTHR-1:0] remainder, - input wire ready_out, - output wire valid_out, - output wire [TAGW-1:0] tag_out + output wire [LANES-1:0][WIDTHR-1:0] remainder ); localparam MIN_ND = (WIDTHN < WIDTHD) ? WIDTHN : WIDTHD; - localparam CNTRW = $clog2(WIDTHN+1); + localparam CNTRW = `CLOG2(WIDTHN); reg [LANES-1:0][WIDTHN + MIN_ND:0] working; reg [LANES-1:0][WIDTHD-1:0] denom_r; @@ -38,18 +47,11 @@ module VX_serial_div #( reg [LANES-1:0] inv_quot, inv_rem; reg [CNTRW-1:0] cntr; - reg is_busy; - - reg [TAGW-1:0] tag_r; - - wire done = ~(| cntr); - - wire push = valid_in && ready_in; - wire pop = valid_out && ready_out; + reg busy_r; for (genvar i = 0; i < LANES; ++i) begin - wire negate_numer = signed_mode && numer[i][WIDTHN-1]; - wire negate_denom = signed_mode && denom[i][WIDTHD-1]; + wire negate_numer = is_signed && numer[i][WIDTHN-1]; + wire negate_denom = is_signed && denom[i][WIDTHD-1]; assign numer_qual[i] = negate_numer ? -$signed(numer[i]) : numer[i]; assign denom_qual[i] = negate_denom ? -$signed(denom[i]) : denom[i]; assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i]; @@ -57,46 +59,40 @@ module VX_serial_div #( always @(posedge clk) begin if (reset) begin - cntr <= 0; - is_busy <= 0; + busy_r <= 0; end else begin - if (push) begin - cntr <= WIDTHN; - is_busy <= 1; - end else if (!done) begin - cntr <= cntr - CNTRW'(1); + if (strobe) begin + busy_r <= 1; end - if (pop) begin - is_busy <= 0; + if (busy && cntr == 0) begin + busy_r <= 0; end end - - if (push) begin - for (integer i = 0; i < LANES; ++i) begin - working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0}; - denom_r[i] <= denom_qual[i]; - inv_quot[i] <= (denom[i] != 0) && signed_mode && (numer[i][31] ^ denom[i][31]); - inv_rem[i] <= signed_mode && numer[i][31]; - end - tag_r <= tag_in; - end else if (!done) begin - for (integer i = 0; i < LANES; ++i) begin - working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} : - {sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1}; - end + cntr <= cntr - CNTRW'(1); + if (strobe) begin + cntr <= CNTRW'(WIDTHN-1); end end for (genvar i = 0; i < LANES; ++i) begin + always @(posedge clk) begin + if (strobe) begin + working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0}; + denom_r[i] <= denom_qual[i]; + inv_quot[i] <= (denom[i] != 0) && is_signed && (numer[i][31] ^ denom[i][31]); + inv_rem[i] <= is_signed && numer[i][31]; + end else if (busy_r) begin + working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} : + {sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1}; + end + end wire [WIDTHQ-1:0] q = working[i][WIDTHQ-1:0]; wire [WIDTHR-1:0] r = working[i][WIDTHN+WIDTHR:WIDTHN+1]; assign quotient[i] = inv_quot[i] ? -$signed(q) : q; assign remainder[i] = inv_rem[i] ? -$signed(r) : r; end - - assign ready_in = !is_busy; - assign tag_out = tag_r; - assign valid_out = is_busy && done; + + assign busy = busy_r; endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_serial_mul.sv b/hw/rtl/libs/VX_serial_mul.sv new file mode 100644 index 00000000..9369dfd1 --- /dev/null +++ b/hw/rtl/libs/VX_serial_mul.sv @@ -0,0 +1,107 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +// Iterative integer multiplier +// An adaptation of ZipCPU algorithm for a multi-lane elastic architecture. +// https://zipcpu.com/zipcpu/2021/07/03/slowmpy.html + +`TRACING_OFF +module VX_serial_mul #( + parameter A_WIDTH = 32, + parameter B_WIDTH = A_WIDTH, + parameter R_WIDTH = A_WIDTH + B_WIDTH, + parameter SIGNED = 0, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + input wire strobe, + output wire busy, + + input wire [LANES-1:0][A_WIDTH-1:0] dataa, + input wire [LANES-1:0][B_WIDTH-1:0] datab, + output wire [LANES-1:0][R_WIDTH-1:0] result +); + localparam X_WIDTH = SIGNED ? `MAX(A_WIDTH, B_WIDTH) : A_WIDTH; + localparam Y_WIDTH = SIGNED ? `MAX(A_WIDTH, B_WIDTH) : B_WIDTH; + localparam P_WIDTH = X_WIDTH + Y_WIDTH; + + localparam CNTRW = `CLOG2(X_WIDTH); + + reg [LANES-1:0][X_WIDTH-1:0] a; + reg [LANES-1:0][Y_WIDTH-1:0] b; + reg [LANES-1:0][P_WIDTH-1:0] p; + + reg [CNTRW-1:0] cntr; + reg busy_r; + + always @(posedge clk) begin + if (reset) begin + busy_r <= 0; + end else begin + if (strobe) begin + busy_r <= 1; + end + if (busy_r && cntr == 0) begin + busy_r <= 0; + end + end + cntr <= cntr - CNTRW'(1); + if (strobe) begin + cntr <= CNTRW'(X_WIDTH-1); + end + end + + for (genvar i = 0; i < LANES; ++i) begin + wire [X_WIDTH-1:0] axb = b[i][0] ? a[i] : '0; + + always @(posedge clk) begin + if (strobe) begin + if (SIGNED) begin + a[i] <= X_WIDTH'($signed(dataa[i])); + b[i] <= Y_WIDTH'($signed(datab[i])); + end else begin + a[i] <= dataa[i]; + b[i] <= datab[i]; + end + p[i] <= 0; + end else if (busy_r) begin + b[i] <= (b[i] >> 1); + p[i][Y_WIDTH-2:0] <= p[i][Y_WIDTH-1:1]; + if (SIGNED) begin + if (cntr == 0) begin + p[i][P_WIDTH-1:Y_WIDTH-1] <= {1'b0, p[i][P_WIDTH-1:Y_WIDTH]} + {1'b0, axb[X_WIDTH-1], ~axb[X_WIDTH-2:0]}; + end else begin + p[i][P_WIDTH-1:Y_WIDTH-1] <= {1'b0, p[i][P_WIDTH-1:Y_WIDTH]} + {1'b0, ~axb[X_WIDTH-1], axb[X_WIDTH-2:0]}; + end + end else begin + p[i][P_WIDTH-1:Y_WIDTH-1] <= {1'b0, p[i][P_WIDTH-1:Y_WIDTH]} + ((b[i][0]) ? {1'b0, a[i]} : 0); + end + end + end + + if (SIGNED) begin + assign result[i] = R_WIDTH'(p[i][P_WIDTH-1:0] + {1'b1, {(X_WIDTH-2){1'b0}}, 1'b1, {(Y_WIDTH){1'b0}}}); + end else begin + assign result[i] = R_WIDTH'(p[i]); + end + end + `UNUSED_VAR (p) + + assign busy = busy_r; + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_shift_register.sv b/hw/rtl/libs/VX_shift_register.sv index e30f1f6c..56726d2c 100644 --- a/hw/rtl/libs/VX_shift_register.sv +++ b/hw/rtl/libs/VX_shift_register.sv @@ -1,141 +1,58 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF -module VX_shift_register_nr #( - parameter DATAW = 1, - parameter DEPTH = 1, - parameter NTAPS = 1, - parameter DEPTHW = $clog2(DEPTH), - parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}} -) ( - input wire clk, - input wire enable, - input wire [DATAW-1:0] data_in, - output wire [(NTAPS*DATAW)-1:0] data_out -); - reg [DEPTH-1:0][DATAW-1:0] entries; - - always @(posedge clk) begin - if (enable) begin - for (integer i = DEPTH-1; i > 0; --i) - entries[i] <= entries[i-1]; - entries[0] <= data_in; - end - end - - for (genvar i = 0; i < NTAPS; ++i) begin - assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]]; - end - -endmodule - -module VX_shift_register_wr #( - parameter DATAW = 1, - parameter DEPTH = 1, - parameter NTAPS = 1, - parameter DEPTHW = $clog2(DEPTH), - parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}} -) ( - input wire clk, - input wire reset, - input wire enable, - input wire [DATAW-1:0] data_in, - output wire [(NTAPS*DATAW)-1:0] data_out -); - reg [DEPTH-1:0][DATAW-1:0] entries; - - always @(posedge clk) begin - if (reset) begin - entries <= '0; - end else if (enable) begin - for (integer i = DEPTH-1; i > 0; --i) - entries[i] <= entries[i-1]; - entries[0] <= data_in; - end - end - - for (genvar i = 0; i < NTAPS; ++i) begin - assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]]; - end - -endmodule - module VX_shift_register #( - parameter DATAW = 1, - parameter RESETW = 0, - parameter DEPTH = 1, - parameter NTAPS = 1, - parameter DEPTHW = $clog2(DEPTH), - parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}} + parameter DATAW = 1, + parameter RESETW = 0, + parameter DEPTH = 1, + parameter NUM_TAPS = 1, + parameter TAP_START = 0, + parameter TAP_STRIDE = 1 ) ( - input wire clk, - input wire reset, - input wire enable, - input wire [DATAW-1:0] data_in, - output wire [(NTAPS*DATAW)-1:0] data_out + input wire clk, + input wire reset, + input wire enable, + input wire [DATAW-1:0] data_in, + output wire [NUM_TAPS-1:0][DATAW-1:0] data_out ); - if (RESETW != 0) begin - if (RESETW == DATAW) begin - - VX_shift_register_wr #( - .DATAW (DATAW), - .DEPTH (DEPTH), - .NTAPS (NTAPS), - .TAPS (TAPS) - ) sr ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in (data_in), - .data_out (data_out) - ); - - end else begin - - VX_shift_register_wr #( - .DATAW (RESETW), - .DEPTH (DEPTH), - .NTAPS (NTAPS), - .TAPS (TAPS) - ) sr_wr ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in (data_in[DATAW-1:DATAW-RESETW]), - .data_out (data_out[DATAW-1:DATAW-RESETW]) - ); - - VX_shift_register_nr #( - .DATAW (DATAW-RESETW), - .DEPTH (DEPTH), - .NTAPS (NTAPS), - .TAPS (TAPS) - ) sr_nr ( - .clk (clk), - .enable (enable), - .data_in (data_in[DATAW-RESETW-1:0]), - .data_out (data_out[DATAW-RESETW-1:0]) - ); + if (DEPTH != 0) begin + reg [DEPTH-1:0][DATAW-1:0] entries; + always @(posedge clk) begin + for (integer i = 0; i < DATAW; ++i) begin + if ((i >= (DATAW-RESETW)) && reset) begin + for (integer j = 0; j < DEPTH; ++j) + entries[j][i] <= 0; + end else if (enable) begin + for (integer j = 1; j < DEPTH; ++j) + entries[j-1][i] <= entries[j][i]; + entries[DEPTH-1][i] <= data_in[i]; + end + end end - end else begin - + for (genvar i = 0; i < NUM_TAPS; ++i) begin + assign data_out[i] = entries[i * TAP_STRIDE + TAP_START]; + end + end else begin + `UNUSED_VAR (clk) `UNUSED_VAR (reset) - - VX_shift_register_nr #( - .DATAW (DATAW), - .DEPTH (DEPTH), - .NTAPS (NTAPS), - .TAPS (TAPS) - ) sr ( - .clk (clk), - .enable (enable), - .data_in (data_in), - .data_out (data_out) - ); - - end + `UNUSED_VAR (enable) + assign data_out = data_in; + end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_skid_buffer.sv b/hw/rtl/libs/VX_skid_buffer.sv index c6820f75..a6876f5c 100644 --- a/hw/rtl/libs/VX_skid_buffer.sv +++ b/hw/rtl/libs/VX_skid_buffer.sv @@ -1,11 +1,23 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_skid_buffer #( - parameter DATAW = 1, - parameter PASSTHRU = 0, - parameter NOBACKPRESSURE = 0, - parameter OUT_REG = 0 + parameter DATAW = 32, + parameter PASSTHRU = 0, + parameter OUT_REG = 0 ) ( input wire clk, input wire reset, @@ -18,8 +30,9 @@ module VX_skid_buffer #( input wire ready_out, output wire valid_out ); + `STATIC_ASSERT ((OUT_REG <= 2), ("invalid parameter")) - if (PASSTHRU) begin + if (PASSTHRU != 0) begin `UNUSED_VAR (clk) `UNUSED_VAR (reset) @@ -28,107 +41,114 @@ module VX_skid_buffer #( assign data_out = data_in; assign ready_in = ready_out; - end else if (NOBACKPRESSURE) begin + end else if (OUT_REG == 0) begin - `RUNTIME_ASSERT(ready_out, ("%t: *** ready_out should always be asserted", $time)) + reg [1:0][DATAW-1:0] shift_reg; + reg valid_out_r, ready_in_r, rd_ptr_r; - wire stall = valid_out && ~ready_out; + wire push = valid_in && ready_in; + wire pop = valid_out_r && ready_out; - VX_pipe_register #( - .DATAW (1 + DATAW), - .RESETW (1) - ) pipe_reg ( - .clk (clk), - .reset (reset), - .enable (!stall), - .data_in ({valid_in, data_in}), - .data_out ({valid_out, data_out}) - ); + always @(posedge clk) begin + if (reset) begin + valid_out_r <= 0; + ready_in_r <= 1; + rd_ptr_r <= 1; + end else begin + if (push) begin + if (!pop) begin + ready_in_r <= rd_ptr_r; + valid_out_r <= 1; + end + end else if (pop) begin + ready_in_r <= 1; + valid_out_r <= rd_ptr_r; + end + rd_ptr_r <= rd_ptr_r ^ (push ^ pop); + end + end + + always @(posedge clk) begin + if (push) begin + shift_reg[1] <= shift_reg[0]; + shift_reg[0] <= data_in; + end + end + + assign ready_in = ready_in_r; + assign valid_out = valid_out_r; + assign data_out = shift_reg[rd_ptr_r]; + + end else if (OUT_REG == 1) begin + + // Full-bandwidth operation: input is consummed every cycle. + // However, data_out register has an additional multiplexer. + + reg [DATAW-1:0] data_out_r; + reg [DATAW-1:0] buffer; + reg valid_out_r; + reg use_buffer; + + wire push = valid_in && ready_in; + wire stall_out = valid_out_r && ~ready_out; + + always @(posedge clk) begin + if (reset) begin + valid_out_r <= 0; + use_buffer <= 0; + end else begin + if (ready_out) begin + use_buffer <= 0; + end else if (valid_in && valid_out) begin + use_buffer <= 1; + end + if (~stall_out) begin + valid_out_r <= valid_in || use_buffer; + end + end + end + + always @(posedge clk) begin + if (push) begin + buffer <= data_in; + end + if (~stall_out) begin + data_out_r <= use_buffer ? buffer : data_in; + end + end + + assign ready_in = ~use_buffer; + assign valid_out = valid_out_r; + assign data_out = data_out_r; - assign ready_in = ~stall; - end else begin - if (OUT_REG) begin + // Half-bandwidth operation: input is consummed every other cycle. + // However, data_out register has no additional multiplexer. - reg [DATAW-1:0] data_out_r; - reg [DATAW-1:0] buffer; - reg valid_out_r; - reg use_buffer; - - wire push = valid_in && ready_in; - wire pop = !valid_out_r || ready_out; - - always @(posedge clk) begin - if (reset) begin - valid_out_r <= 0; - use_buffer <= 0; - end else begin - if (ready_out) begin - use_buffer <= 0; - end else if (valid_in && valid_out_r) begin - use_buffer <= 1; - end - if (pop) begin - valid_out_r <= valid_in || use_buffer; - end - end - end + reg [DATAW-1:0] data_out_r; + reg has_data; - always @(posedge clk) begin - if (push) begin - buffer <= data_in; - end - if (pop && !use_buffer) begin - data_out_r <= data_in; + always @(posedge clk) begin + if (reset) begin + has_data <= 0; + end else begin + if (~has_data) begin + has_data <= valid_in; end else if (ready_out) begin - data_out_r <= buffer; - end + has_data <= 0; + end end - - assign ready_in = !use_buffer; - assign valid_out = valid_out_r; - assign data_out = data_out_r; - - end else begin - - reg [DATAW-1:0] shift_reg [1:0]; - reg valid_out_r, ready_in_r, rd_ptr_r; - - wire push = valid_in && ready_in; - wire pop = valid_out_r && ready_out; - - always @(posedge clk) begin - if (reset) begin - valid_out_r <= 0; - ready_in_r <= 1; - rd_ptr_r <= 1; - end else begin - if (push) begin - if (!pop) begin - ready_in_r <= rd_ptr_r; - valid_out_r <= 1; - end - end else if (pop) begin - ready_in_r <= 1; - valid_out_r <= rd_ptr_r; - end - rd_ptr_r <= rd_ptr_r ^ (push ^ pop); - end + if (~has_data) begin + data_out_r <= data_in; end - - always @(posedge clk) begin - if (push) begin - shift_reg[1] <= shift_reg[0]; - shift_reg[0] <= data_in; - end - end - - assign ready_in = ready_in_r; - assign valid_out = valid_out_r; - assign data_out = shift_reg[rd_ptr_r]; end + + assign ready_in = ~has_data; + assign valid_out = has_data; + assign data_out = data_out_r; + end endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_sp_ram.sv b/hw/rtl/libs/VX_sp_ram.sv index 2ed01d0d..1496d448 100644 --- a/hw/rtl/libs/VX_sp_ram.sv +++ b/hw/rtl/libs/VX_sp_ram.sv @@ -1,252 +1,60 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_platform.vh" `TRACING_OFF module VX_sp_ram #( parameter DATAW = 1, parameter SIZE = 1, - parameter BYTEENW = 1, + parameter WRENW = 1, parameter OUT_REG = 0, parameter NO_RWCHECK = 0, - parameter LUTRAM = 0, - parameter ADDRW = $clog2(SIZE), + parameter LUTRAM = 0, parameter INIT_ENABLE = 0, parameter INIT_FILE = "", - parameter [DATAW-1:0] INIT_VALUE = 0 + parameter [DATAW-1:0] INIT_VALUE = 0, + parameter ADDRW = `LOG2UP(SIZE) ) ( - input wire clk, + input wire clk, + input wire read, + input wire write, + input wire [WRENW-1:0] wren, input wire [ADDRW-1:0] addr, - input wire [BYTEENW-1:0] wren, input wire [DATAW-1:0] wdata, output wire [DATAW-1:0] rdata ); - - `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) - -`define RAM_INITIALIZATION \ - if (INIT_ENABLE) begin \ - if (INIT_FILE != "") begin \ - initial $readmemh(INIT_FILE, ram); \ - end else begin \ - initial \ - for (integer i = 0; i < SIZE; ++i)\ - ram[i] = INIT_VALUE; \ - end \ - end - -`ifdef SYNTHESIS - if (LUTRAM) begin - if (OUT_REG) begin - reg [DATAW-1:0] rdata_r; - - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[addr][i] <= wdata[i * 8 +: 8]; - end - rdata_r <= ram[addr]; - end - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[addr] <= wdata; - rdata_r <= ram[addr]; - end - end - assign rdata = rdata_r; - end else begin - if (BYTEENW > 1) begin - `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[addr][i] <= wdata[i * 8 +: 8]; - end - end - assign rdata = ram[addr]; - end else begin - `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[addr] <= wdata; - end - assign rdata = ram[addr]; - end - end - end else begin - if (OUT_REG) begin - reg [DATAW-1:0] rdata_r; - - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[addr][i] <= wdata[i * 8 +: 8]; - end - rdata_r <= ram[addr]; - end - end else begin - reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[addr] <= wdata; - rdata_r <= ram[addr]; - end - end - assign rdata = rdata_r; - end else begin - if (NO_RWCHECK) begin - if (BYTEENW > 1) begin - `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[addr][i] <= wdata[i * 8 +: 8]; - end - end - assign rdata = ram[addr]; - end else begin - `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[addr] <= wdata; - end - assign rdata = ram[addr]; - end - end else begin - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[addr][i] <= wdata[i * 8 +: 8]; - end - end - assign rdata = ram[addr]; - end else begin - reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[addr] <= wdata; - end - assign rdata = ram[addr]; - end - end - end - end -`else - if (OUT_REG) begin - reg [DATAW-1:0] rdata_r; - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[addr][i] <= wdata[i * 8 +: 8]; - end - rdata_r <= ram[addr]; - end - end else begin - reg [DATAW-1:0] ram [SIZE-1:0]; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[addr] <= wdata; - rdata_r <= ram[addr]; - end - end - assign rdata = rdata_r; - end else begin - if (BYTEENW > 1) begin - reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; - reg [DATAW-1:0] prev_data; - reg [ADDRW-1:0] prev_addr; - reg prev_write; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - for (integer i = 0; i < BYTEENW; i++) begin - if (wren[i]) - ram[addr][i] <= wdata[i * 8 +: 8]; - end - prev_write <= (| wren); - prev_data <= ram[addr]; - prev_addr <= addr; - end - - if (LUTRAM || !NO_RWCHECK) begin - `UNUSED_VAR (prev_write) - `UNUSED_VAR (prev_data) - `UNUSED_VAR (prev_addr) - assign rdata = ram[addr]; - end else begin - assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr]; - end - end else begin - reg [DATAW-1:0] ram [SIZE-1:0]; - reg [DATAW-1:0] prev_data; - reg [ADDRW-1:0] prev_addr; - reg prev_write; - - `RAM_INITIALIZATION - - always @(posedge clk) begin - if (wren) - ram[addr] <= wdata; - prev_write <= wren; - prev_data <= ram[addr]; - prev_addr <= addr; - end - if (LUTRAM || !NO_RWCHECK) begin - `UNUSED_VAR (prev_write) - `UNUSED_VAR (prev_data) - `UNUSED_VAR (prev_addr) - assign rdata = ram[addr]; - end else begin - assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr]; - end - end - end -`endif + VX_dp_ram #( + .DATAW (DATAW), + .SIZE (SIZE), + .WRENW (WRENW), + .OUT_REG (OUT_REG), + .NO_RWCHECK (NO_RWCHECK), + .LUTRAM (LUTRAM), + .INIT_ENABLE (INIT_ENABLE), + .INIT_FILE (INIT_FILE), + .INIT_VALUE (INIT_VALUE), + .ADDRW (ADDRW) + ) dp_ram ( + .clk (clk), + .read (read), + .write (write), + .wren (wren), + .waddr (addr), + .wdata (wdata), + .raddr (addr), + .rdata (rdata) + ); endmodule -`TRACING_ON \ No newline at end of file +`TRACING_ON diff --git a/hw/rtl/libs/VX_stream_arb.sv b/hw/rtl/libs/VX_stream_arb.sv new file mode 100644 index 00000000..58da0b25 --- /dev/null +++ b/hw/rtl/libs/VX_stream_arb.sv @@ -0,0 +1,375 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_arb #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATAW = 1, + parameter `STRING ARBITER = "P", + parameter LOCK_ENABLE = 1, + parameter MAX_FANOUT = `MAX_FANOUT, + parameter OUT_REG = 0 , + parameter NUM_REQS = (NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS, + parameter LOG_NUM_REQS = `CLOG2(NUM_REQS), + parameter NUM_REQS_W = `UP(LOG_NUM_REQS) +) ( + input wire clk, + input wire reset, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + output wire [NUM_OUTPUTS-1:0][NUM_REQS_W-1:0] sel_out, + input wire [NUM_OUTPUTS-1:0] ready_out +); + if (NUM_INPUTS > NUM_OUTPUTS) begin + + if (NUM_OUTPUTS > 1) begin + + // (#inputs > #outputs) and (#outputs > 1) + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + + localparam BATCH_BEGIN = i * NUM_REQS; + localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_INPUTS); + localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN; + + `RESET_RELAY (slice_reset, reset); + + VX_stream_arb #( + .NUM_INPUTS (BATCH_SIZE), + .NUM_OUTPUTS (1), + .DATAW (DATAW), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) arb_slice ( + .clk (clk), + .reset (slice_reset), + .valid_in (valid_in[BATCH_END-1: BATCH_BEGIN]), + .ready_in (ready_in[BATCH_END-1: BATCH_BEGIN]), + .data_in (data_in[BATCH_END-1: BATCH_BEGIN]), + .data_out (data_out[i]), + .sel_out (sel_out[i]), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + end + + end else if (MAX_FANOUT != 0 && (NUM_INPUTS > (MAX_FANOUT + MAX_FANOUT/2))) begin + + // (#inputs > max_fanout) and (#outputs == 1) + + localparam NUM_BATCHES = (NUM_INPUTS + MAX_FANOUT - 1) / MAX_FANOUT; + localparam LOG_NUM_REQS2 = `CLOG2(MAX_FANOUT); + localparam LOG_NUM_REQS3 = `CLOG2(NUM_BATCHES); + + wire [NUM_BATCHES-1:0] valid_tmp; + wire [NUM_BATCHES-1:0][DATAW+LOG_NUM_REQS2-1:0] data_tmp; + wire [NUM_BATCHES-1:0] ready_tmp; + + for (genvar i = 0; i < NUM_BATCHES; ++i) begin + + localparam BATCH_BEGIN = i * MAX_FANOUT; + localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_INPUTS); + localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN; + + wire [DATAW-1:0] data_tmp_u; + wire [`LOG2UP(BATCH_SIZE)-1:0] sel_tmp_u; + + `RESET_RELAY (slice_reset, reset); + + if (MAX_FANOUT != 1) begin + VX_stream_arb #( + .NUM_INPUTS (BATCH_SIZE), + .NUM_OUTPUTS (1), + .DATAW (DATAW), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) fanout_slice_arb ( + .clk (clk), + .reset (slice_reset), + .valid_in (valid_in[BATCH_END-1: BATCH_BEGIN]), + .data_in (data_in[BATCH_END-1: BATCH_BEGIN]), + .ready_in (ready_in[BATCH_END-1: BATCH_BEGIN]), + .valid_out (valid_tmp[i]), + .data_out (data_tmp_u), + .sel_out (sel_tmp_u), + .ready_out (ready_tmp[i]) + ); + end + + assign data_tmp[i] = {data_tmp_u, LOG_NUM_REQS2'(sel_tmp_u)}; + end + + wire [DATAW+LOG_NUM_REQS2-1:0] data_out_u; + wire [LOG_NUM_REQS3-1:0] sel_out_u; + + VX_stream_arb #( + .NUM_INPUTS (NUM_BATCHES), + .NUM_OUTPUTS (1), + .DATAW (DATAW + LOG_NUM_REQS2), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) fanout_join_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_tmp), + .ready_in (ready_tmp), + .data_in (data_tmp), + .data_out (data_out_u), + .sel_out (sel_out_u), + .valid_out (valid_out), + .ready_out (ready_out) + ); + + assign data_out = data_out_u[LOG_NUM_REQS2 +: DATAW]; + assign sel_out = {sel_out_u, data_out_u[0 +: LOG_NUM_REQS2]}; + + end else begin + + // (#inputs <= max_fanout) and (#outputs == 1) + + wire valid_in_r; + wire [DATAW-1:0] data_in_r; + wire ready_in_r; + + wire arb_valid; + wire [NUM_REQS_W-1:0] arb_index; + wire [NUM_REQS-1:0] arb_onehot; + wire arb_unlock; + + VX_generic_arbiter #( + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE), + .TYPE (ARBITER) + ) arbiter ( + .clk (clk), + .reset (reset), + .requests (valid_in), + .unlock (arb_unlock), + .grant_valid (arb_valid), + .grant_index (arb_index), + .grant_onehot (arb_onehot) + ); + + assign valid_in_r = arb_valid; + assign data_in_r = data_in[arb_index]; + assign arb_unlock = | (valid_in_r & ready_in_r); + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign ready_in[i] = ready_in_r & arb_onehot[i]; + end + + VX_elastic_buffer #( + .DATAW (LOG_NUM_REQS + DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_in_r), + .ready_in (ready_in_r), + .data_in ({arb_index, data_in_r}), + .data_out ({sel_out, data_out}), + .valid_out (valid_out), + .ready_out (ready_out) + ); + end + + end else if (NUM_OUTPUTS > NUM_INPUTS) begin + + if (NUM_INPUTS > 1) begin + + // (#inputs > 1) and (#outputs > #inputs) + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + + localparam BATCH_BEGIN = i * NUM_REQS; + localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_OUTPUTS); + localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN; + + `RESET_RELAY (slice_reset, reset); + + VX_stream_arb #( + .NUM_INPUTS (1), + .NUM_OUTPUTS (BATCH_SIZE), + .DATAW (DATAW), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) arb_slice ( + .clk (clk), + .reset (slice_reset), + .valid_in (valid_in[i]), + .ready_in (ready_in[i]), + .data_in (data_in[i]), + .data_out (data_out[BATCH_END-1: BATCH_BEGIN]), + .valid_out (valid_out[BATCH_END-1: BATCH_BEGIN]), + .ready_out (ready_out[BATCH_END-1: BATCH_BEGIN]), + `UNUSED_PIN (sel_out) + ); + + for (genvar j = BATCH_BEGIN; j < BATCH_END; ++j) begin + assign sel_out[j] = i; + end + end + + end else if (MAX_FANOUT != 0 && (NUM_OUTPUTS > (MAX_FANOUT + MAX_FANOUT/2))) begin + + // (#inputs == 1) and (#outputs > max_fanout) + + localparam NUM_BATCHES = (NUM_OUTPUTS + MAX_FANOUT - 1) / MAX_FANOUT; + + wire [NUM_BATCHES-1:0] valid_tmp; + wire [NUM_BATCHES-1:0][DATAW-1:0] data_tmp; + wire [NUM_BATCHES-1:0] ready_tmp; + + VX_stream_arb #( + .NUM_INPUTS (1), + .NUM_OUTPUTS (NUM_BATCHES), + .DATAW (DATAW), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) fanout_fork_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .ready_in (ready_in), + .data_in (data_in), + .data_out (data_tmp), + .valid_out (valid_tmp), + .ready_out (ready_tmp), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_BATCHES; ++i) begin + + localparam BATCH_BEGIN = i * MAX_FANOUT; + localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_OUTPUTS); + localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN; + + `RESET_RELAY (slice_reset, reset); + + VX_stream_arb #( + .NUM_INPUTS (1), + .NUM_OUTPUTS (BATCH_SIZE), + .DATAW (DATAW), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) fanout_slice_arb ( + .clk (clk), + .reset (slice_reset), + .valid_in (valid_tmp[i]), + .ready_in (ready_tmp[i]), + .data_in (data_tmp[i]), + .data_out (data_out[BATCH_END-1: BATCH_BEGIN]), + .valid_out (valid_out[BATCH_END-1: BATCH_BEGIN]), + .ready_out (ready_out[BATCH_END-1: BATCH_BEGIN]), + `UNUSED_PIN (sel_out) + ); + end + + end else begin + + // (#inputs == 1) and (#outputs <= max_fanout) + + wire [NUM_OUTPUTS-1:0] ready_in_r; + + wire [NUM_OUTPUTS-1:0] arb_requests; + wire arb_valid; + wire [NUM_OUTPUTS-1:0] arb_onehot; + wire arb_unlock; + + VX_generic_arbiter #( + .NUM_REQS (NUM_OUTPUTS), + .LOCK_ENABLE (LOCK_ENABLE), + .TYPE (ARBITER) + ) arbiter ( + .clk (clk), + .reset (reset), + .requests (arb_requests), + .unlock (arb_unlock), + .grant_valid (arb_valid), + `UNUSED_PIN (grant_index), + .grant_onehot (arb_onehot) + ); + + assign arb_requests = ready_in_r; + assign arb_unlock = | (valid_in & ready_in); + assign ready_in = arb_valid; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && arb_onehot[i]), + .ready_in (ready_in_r[i]), + .data_in (data_in), + .data_out (data_out[i]), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + end + end + + assign sel_out = 0; + + end else begin + + // #Inputs == #Outputs + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + + `RESET_RELAY_EN (out_buf_reset, reset, (NUM_OUTPUTS > 1)); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (out_buf_reset), + .valid_in (valid_in[i]), + .ready_in (ready_in[i]), + .data_in (data_in[i]), + .data_out (data_out[i]), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + assign sel_out[i] = NUM_REQS_W'(i); + end + end + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_stream_arbiter.sv b/hw/rtl/libs/VX_stream_arbiter.sv deleted file mode 100644 index c4466f39..00000000 --- a/hw/rtl/libs/VX_stream_arbiter.sv +++ /dev/null @@ -1,148 +0,0 @@ -`include "VX_platform.vh" - -module VX_stream_arbiter #( - parameter NUM_REQS = 1, - parameter LANES = 1, - parameter DATAW = 1, - parameter TYPE = "P", - parameter LOCK_ENABLE = 1, - parameter BUFFERED = 0 -) ( - input wire clk, - input wire reset, - - input wire [NUM_REQS-1:0][LANES-1:0] valid_in, - input wire [NUM_REQS-1:0][LANES-1:0][DATAW-1:0] data_in, - output wire [NUM_REQS-1:0][LANES-1:0] ready_in, - - output wire [LANES-1:0] valid_out, - output wire [LANES-1:0][DATAW-1:0] data_out, - input wire [LANES-1:0] ready_out -); - localparam LOG_NUM_REQS = `CLOG2(NUM_REQS); - - if (NUM_REQS > 1) begin - wire sel_valid; - wire sel_ready; - wire [LOG_NUM_REQS-1:0] sel_index; - wire [NUM_REQS-1:0] sel_onehot; - - wire [NUM_REQS-1:0] valid_in_any; - wire [LANES-1:0] ready_in_sel; - - if (LANES > 1) begin - for (genvar i = 0; i < NUM_REQS; i++) begin - assign valid_in_any[i] = (| valid_in[i]); - end - assign sel_ready = (| ready_in_sel); - end else begin - for (genvar i = 0; i < NUM_REQS; i++) begin - assign valid_in_any[i] = valid_in[i]; - end - assign sel_ready = ready_in_sel; - end - - if (TYPE == "P") begin - VX_fixed_arbiter #( - .NUM_REQS (NUM_REQS), - .LOCK_ENABLE (LOCK_ENABLE) - ) sel_arb ( - .clk (clk), - .reset (reset), - .requests (valid_in_any), - .enable (sel_ready), - .grant_valid (sel_valid), - .grant_index (sel_index), - .grant_onehot (sel_onehot) - ); - end else if (TYPE == "R") begin - VX_rr_arbiter #( - .NUM_REQS (NUM_REQS), - .LOCK_ENABLE (LOCK_ENABLE) - ) sel_arb ( - .clk (clk), - .reset (reset), - .requests (valid_in_any), - .enable (sel_ready), - .grant_valid (sel_valid), - .grant_index (sel_index), - .grant_onehot (sel_onehot) - ); - end else if (TYPE == "F") begin - VX_fair_arbiter #( - .NUM_REQS (NUM_REQS), - .LOCK_ENABLE (LOCK_ENABLE) - ) sel_arb ( - .clk (clk), - .reset (reset), - .requests (valid_in_any), - .enable (sel_ready), - .grant_valid (sel_valid), - .grant_index (sel_index), - .grant_onehot (sel_onehot) - ); - end else if (TYPE == "M") begin - VX_matrix_arbiter #( - .NUM_REQS (NUM_REQS), - .LOCK_ENABLE (LOCK_ENABLE) - ) sel_arb ( - .clk (clk), - .reset (reset), - .requests (valid_in_any), - .enable (sel_ready), - .grant_valid (sel_valid), - .grant_index (sel_index), - .grant_onehot (sel_onehot) - ); - end else begin - `ERROR(("invalid parameter")); - end - - wire [LANES-1:0] valid_in_sel; - wire [LANES-1:0][DATAW-1:0] data_in_sel; - - if (LANES > 1) begin - wire [NUM_REQS-1:0][(LANES * (1 + DATAW))-1:0] valid_data_in; - for (genvar i = 0; i < NUM_REQS; i++) begin - assign valid_data_in[i] = {valid_in[i], data_in[i]}; - end - assign {valid_in_sel, data_in_sel} = valid_data_in[sel_index]; - `UNUSED_VAR (sel_valid) - end else begin - assign data_in_sel = data_in[sel_index]; - assign valid_in_sel = sel_valid; - end - - for (genvar i = 0; i < NUM_REQS; i++) begin - assign ready_in[i] = ready_in_sel & {LANES{sel_onehot[i]}}; - end - - for (genvar i = 0; i < LANES; ++i) begin - VX_skid_buffer #( - .DATAW (DATAW), - .PASSTHRU (0 == BUFFERED), - .OUT_REG (2 == BUFFERED) - ) out_buffer ( - .clk (clk), - .reset (reset), - .valid_in (valid_in_sel[i]), - .data_in (data_in_sel[i]), - .ready_in (ready_in_sel[i]), - .valid_out (valid_out[i]), - .data_out (data_out[i]), - .ready_out (ready_out[i]) - ); - end - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - assign valid_out = valid_in; - assign data_out = data_in; - assign ready_in = ready_out; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_stream_demux.sv b/hw/rtl/libs/VX_stream_demux.sv deleted file mode 100644 index 282a2212..00000000 --- a/hw/rtl/libs/VX_stream_demux.sv +++ /dev/null @@ -1,68 +0,0 @@ -`include "VX_platform.vh" - -module VX_stream_demux #( - parameter NUM_REQS = 1, - parameter LANES = 1, - parameter DATAW = 1, - parameter BUFFERED = 0, - parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) -) ( - input wire clk, - input wire reset, - - input wire [LANES-1:0][LOG_NUM_REQS-1:0] sel_in, - - input wire [LANES-1:0] valid_in, - input wire [LANES-1:0][DATAW-1:0] data_in, - output wire [LANES-1:0] ready_in, - - output wire [NUM_REQS-1:0][LANES-1:0] valid_out, - output wire [NUM_REQS-1:0][LANES-1:0][DATAW-1:0] data_out, - input wire [NUM_REQS-1:0][LANES-1:0] ready_out - ); - - if (NUM_REQS > 1) begin - - for (genvar j = 0; j < LANES; ++j) begin - - reg [NUM_REQS-1:0] valid_in_sel; - wire [NUM_REQS-1:0] ready_in_sel; - - always @(*) begin - valid_in_sel = '0; - valid_in_sel[sel_in[j]] = valid_in[j]; - end - - assign ready_in[j] = ready_in_sel[sel_in[j]]; - - for (genvar i = 0; i < NUM_REQS; i++) begin - VX_skid_buffer #( - .DATAW (DATAW), - .PASSTHRU (0 == BUFFERED), - .OUT_REG (2 == BUFFERED) - ) out_buffer ( - .clk (clk), - .reset (reset), - .valid_in (valid_in_sel[i]), - .data_in (data_in[j]), - .ready_in (ready_in_sel[i]), - .valid_out (valid_out[i][j]), - .data_out (data_out[i][j]), - .ready_out (ready_out[i][j]) - ); - end - end - - end else begin - - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - `UNUSED_VAR (sel_in) - - assign valid_out = valid_in; - assign data_out = data_in; - assign ready_in = ready_out; - - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_stream_switch.sv b/hw/rtl/libs/VX_stream_switch.sv new file mode 100644 index 00000000..2361f418 --- /dev/null +++ b/hw/rtl/libs/VX_stream_switch.sv @@ -0,0 +1,164 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_switch #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATAW = 1, + parameter OUT_REG = 0, + parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? ((NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS) : ((NUM_OUTPUTS + NUM_INPUTS - 1) / NUM_INPUTS), + parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS), + parameter LOG_NUM_REQS = `CLOG2(NUM_REQS) +) ( + input wire clk, + input wire reset, + + input wire [SEL_COUNT-1:0][`UP(LOG_NUM_REQS)-1:0] sel_in, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + input wire [NUM_OUTPUTS-1:0] ready_out +); + if (NUM_INPUTS > NUM_OUTPUTS) begin + + wire [NUM_OUTPUTS-1:0][NUM_REQS-1:0] valid_in_r; + wire [NUM_OUTPUTS-1:0][NUM_REQS-1:0][DATAW-1:0] data_in_r; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + for (genvar j = 0; j < NUM_REQS; ++j) begin + localparam ii = i * NUM_REQS + j; + if (ii < NUM_INPUTS) begin + assign valid_in_r[i][j] = valid_in[ii]; + assign data_in_r[i][j] = data_in[ii]; + end else begin + assign valid_in_r[i][j] = 0; + assign data_in_r[i][j] = '0; + end + end + end + + wire [NUM_OUTPUTS-1:0] valid_out_r; + wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_r; + wire [NUM_OUTPUTS-1:0] ready_out_r; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + assign valid_out_r[i] = valid_in_r[i][sel_in[i]]; + assign data_out_r[i] = data_in_r[i][sel_in[i]]; + end + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + for (genvar j = 0; j < NUM_REQS; ++j) begin + localparam ii = i * NUM_REQS + j; + if (ii < NUM_INPUTS) begin + assign ready_in[ii] = ready_out_r[i] & (sel_in[i] == LOG_NUM_REQS'(j)); + end + end + end + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + + `RESET_RELAY_EN (out_buf_reset, reset, (NUM_OUTPUTS > 1)); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (out_buf_reset), + .valid_in (valid_out_r[i]), + .ready_in (ready_out_r[i]), + .data_in (data_out_r[i]), + .data_out (data_out[i]), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + end + + end else if (NUM_OUTPUTS > NUM_INPUTS) begin + + wire [NUM_INPUTS-1:0][NUM_REQS-1:0] valid_out_r; + wire [NUM_INPUTS-1:0][NUM_REQS-1:0] ready_out_r; + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + for (genvar j = 0; j < NUM_REQS; ++j) begin + assign valid_out_r[i][j] = valid_in[i] & (sel_in[i] == LOG_NUM_REQS'(j)); + end + assign ready_in[i] = ready_out_r[i][sel_in[i]]; + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + for (genvar j = 0; j < NUM_REQS; ++j) begin + localparam ii = i * NUM_REQS + j; + if (ii < NUM_OUTPUTS) begin + + `RESET_RELAY (out_buf_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (out_buf_reset), + .valid_in (valid_out_r[i][j]), + .ready_in (ready_out_r[i][j]), + .data_in (data_in[i]), + .data_out (data_out[ii]), + .valid_out (valid_out[ii]), + .ready_out (ready_out[ii]) + ); + end else begin + `UNUSED_VAR (valid_out_r[i][j]) + assign ready_out_r[i][j] = '0; + end + end + end + + end else begin + + // #Inputs == #Outputs + + `UNUSED_VAR (sel_in) + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + + `RESET_RELAY_EN (out_buf_reset, reset, (NUM_OUTPUTS > 1)); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (out_buf_reset), + .valid_in (valid_in[i]), + .ready_in (ready_in[i]), + .data_in (data_in[i]), + .data_out (data_out[i]), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + end + + end + +endmodule +`TRACING_ON diff --git a/hw/rtl/libs/VX_stream_xbar.sv b/hw/rtl/libs/VX_stream_xbar.sv new file mode 100644 index 00000000..db92cfd0 --- /dev/null +++ b/hw/rtl/libs/VX_stream_xbar.sv @@ -0,0 +1,207 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`TRACING_OFF +module VX_stream_xbar #( + parameter NUM_INPUTS = 4, + parameter NUM_OUTPUTS = 4, + parameter DATAW = 4, + parameter IN_WIDTH = `LOG2UP(NUM_INPUTS), + parameter OUT_WIDTH = `LOG2UP(NUM_OUTPUTS), + parameter ARBITER = "P", + parameter LOCK_ENABLE = 0, + parameter OUT_REG = 0, + parameter MAX_FANOUT = `MAX_FANOUT, + parameter PERF_CTR_BITS = `CLOG2(NUM_INPUTS+1) +) ( + input wire clk, + input wire reset, + + output wire [PERF_CTR_BITS-1:0] collisions, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + input wire [NUM_INPUTS-1:0][OUT_WIDTH-1:0] sel_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + output wire [NUM_OUTPUTS-1:0][IN_WIDTH-1:0] sel_out, + input wire [NUM_OUTPUTS-1:0] ready_out +); + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + if (NUM_INPUTS != 1) begin + + if (NUM_OUTPUTS != 1) begin + + // (#inputs > 1) and (#outputs > 1) + + wire [NUM_OUTPUTS-1:0][NUM_INPUTS-1:0] per_output_ready_in; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + + wire [NUM_INPUTS-1:0] valid_in_q; + for (genvar j = 0; j < NUM_INPUTS; ++j) begin + assign valid_in_q[j] = valid_in[j] && (sel_in[j] == i); + end + + `RESET_RELAY (slice_reset, reset); + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (1), + .DATAW (DATAW), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) xbar_arb ( + .clk (clk), + .reset (slice_reset), + .valid_in (valid_in_q), + .data_in (data_in), + .ready_in (per_output_ready_in[i]), + .valid_out (valid_out[i]), + .data_out (data_out[i]), + .sel_out (sel_out[i]), + .ready_out (ready_out[i]) + ); + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + assign ready_in[i] = per_output_ready_in[sel_in[i]][i]; + end + + end else begin + + // (#inputs >= 1) and (#outputs == 1) + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (1), + .DATAW (DATAW), + .ARBITER (ARBITER), + .LOCK_ENABLE (LOCK_ENABLE), + .MAX_FANOUT (MAX_FANOUT), + .OUT_REG (OUT_REG) + ) xbar_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .ready_in (ready_in), + .valid_out (valid_out), + .data_out (data_out), + .sel_out (sel_out), + .ready_out (ready_out) + ); + + `UNUSED_VAR (sel_in) + end + + end else if (NUM_OUTPUTS != 1) begin + + // (#inputs == 1) and (#outputs > 1) + + logic [NUM_OUTPUTS-1:0] valid_out_r, ready_out_r; + logic [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_r; + always @(*) begin + valid_out_r = '0; + valid_out_r[sel_in] = valid_in; + end + assign data_out_r = {NUM_OUTPUTS{data_in}}; + assign ready_in = ready_out_r[sel_in]; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + + `RESET_RELAY (out_buf_reset, reset); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (out_buf_reset), + .valid_in (valid_out_r[i]), + .ready_in (ready_out_r[i]), + .data_in (data_out_r[i]), + .data_out (data_out[i]), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + end + + assign sel_out = 0; + + end else begin + + // (#inputs == 1) and (#outputs == 1) + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)), + .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .ready_in (ready_in), + .data_in (data_in), + .data_out (data_out), + .valid_out (valid_out), + .ready_out (ready_out) + ); + + `UNUSED_VAR (sel_in) + assign sel_out = 0; + + end + + // compute inputs collision + // we have a collision when there exists a valid transfer with mutiple input candicates + // we caount the unique duplicates each cycle. + + reg [PERF_CTR_BITS-1:0] collisions_r; + reg [NUM_INPUTS-1:0] per_cycle_collision; + + always @(*) begin + per_cycle_collision = 0; + for (integer i = 0; i < NUM_INPUTS; ++i) begin + for (integer j = 1; j < (NUM_INPUTS-i); ++j) begin + if (valid_in[i] && valid_in[j+i] && sel_in[i] == sel_in[j+i]) begin + per_cycle_collision[i] |= ready_in[i] | ready_in[j+i]; + end + end + end + end + + wire [`CLOG2(NUM_INPUTS+1)-1:0] collision_count; + `POP_COUNT(collision_count, per_cycle_collision); + + always @(posedge clk) begin + if (reset) begin + collisions_r <= '0; + end else begin + collisions_r <= collisions_r + PERF_CTR_BITS'(collision_count); + end + end + + assign collisions = collisions_r; + +endmodule +`TRACING_ON diff --git a/hw/rtl/mem/VX_gbar_arb.sv b/hw/rtl/mem/VX_gbar_arb.sv new file mode 100644 index 00000000..6aa93510 --- /dev/null +++ b/hw/rtl/mem/VX_gbar_arb.sv @@ -0,0 +1,79 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_gbar_arb #( + parameter NUM_REQS = 1, + parameter OUT_REG = 0, + parameter `STRING ARBITER = "R" +) ( + input wire clk, + input wire reset, + + VX_gbar_bus_if.slave bus_in_if [NUM_REQS], + VX_gbar_bus_if.master bus_out_if +); + + localparam REQ_DATAW = `NB_WIDTH + `NC_WIDTH + `NC_WIDTH; + + // arbitrate request + + wire [NUM_REQS-1:0] req_valid_in; + wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_REQS-1:0] req_ready_in; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign req_valid_in[i] = bus_in_if[i].req_valid; + assign req_data_in[i] = {bus_in_if[i].req_id, bus_in_if[i].req_size_m1, bus_in_if[i].req_core_id}; + assign bus_in_if[i].req_ready = req_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS (1), + .DATAW (REQ_DATAW), + .ARBITER (ARBITER), + .OUT_REG (OUT_REG) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (req_valid_in), + .ready_in (req_ready_in), + .data_in (req_data_in), + .data_out ({bus_out_if.req_id, bus_out_if.req_size_m1, bus_out_if.req_core_id}), + .valid_out (bus_out_if.req_valid), + .ready_out (bus_out_if.req_ready), + `UNUSED_PIN (sel_out) + ); + + // broadcast response + + reg rsp_valid; + reg [`NB_WIDTH-1:0] rsp_id; + + always @(posedge clk) begin + if (reset) begin + rsp_valid <= 0; + end else begin + rsp_valid <= bus_out_if.rsp_valid; + end + rsp_id <= bus_out_if.rsp_id; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign bus_in_if[i].rsp_valid = rsp_valid; + assign bus_in_if[i].rsp_id = rsp_id; + end + +endmodule diff --git a/hw/rtl/mem/VX_gbar_bus_if.sv b/hw/rtl/mem/VX_gbar_bus_if.sv new file mode 100644 index 00000000..235c4c7a --- /dev/null +++ b/hw/rtl/mem/VX_gbar_bus_if.sv @@ -0,0 +1,49 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_gbar_bus_if (); + + wire req_valid; + wire [`NB_WIDTH-1:0] req_id; + wire [`NC_WIDTH-1:0] req_size_m1; + wire [`NC_WIDTH-1:0] req_core_id; + wire req_ready; + + wire rsp_valid; + wire [`NB_WIDTH-1:0] rsp_id; + + modport master ( + output req_valid, + output req_id, + output req_size_m1, + output req_core_id, + input req_ready, + + input rsp_valid, + input rsp_id + ); + + modport slave ( + input req_valid, + input req_id, + input req_size_m1, + input req_core_id, + output req_ready, + + output rsp_valid, + output rsp_id + ); + +endinterface diff --git a/hw/rtl/mem/VX_gbar_unit.sv b/hw/rtl/mem/VX_gbar_unit.sv new file mode 100644 index 00000000..a6e5d9ba --- /dev/null +++ b/hw/rtl/mem/VX_gbar_unit.sv @@ -0,0 +1,72 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_gbar_unit #( + parameter `STRING INSTANCE_ID = "" +) ( + input wire clk, + input wire reset, + + VX_gbar_bus_if.slave gbar_bus_if +); + `UNUSED_SPARAM (INSTANCE_ID) + + reg [`NB_WIDTH-1:0][`NUM_CORES-1:0] barrier_masks; + wire [`CLOG2(`NUM_CORES+1)-1:0] active_barrier_count; + wire [`NUM_CORES-1:0] curr_barrier_mask = barrier_masks[gbar_bus_if.req_id]; + + `POP_COUNT(active_barrier_count, curr_barrier_mask); + `UNUSED_VAR (active_barrier_count) + + reg rsp_valid; + reg [`NB_WIDTH-1:0] rsp_bar_id; + + always @(posedge clk) begin + if (reset) begin + barrier_masks <= '0; + rsp_valid <= 0; + end else begin + if (rsp_valid) begin + rsp_valid <= 0; + end + if (gbar_bus_if.req_valid) begin + if (active_barrier_count[`NC_WIDTH-1:0] == gbar_bus_if.req_size_m1) begin + barrier_masks[gbar_bus_if.req_id] <= '0; + rsp_bar_id <= gbar_bus_if.req_id; + rsp_valid <= 1; + end else begin + barrier_masks[gbar_bus_if.req_id][gbar_bus_if.req_core_id] <= 1; + end + end + end + end + + assign gbar_bus_if.rsp_valid = rsp_valid; + assign gbar_bus_if.rsp_id = rsp_bar_id; + assign gbar_bus_if.req_ready = 1; // global barrier unit is always ready (no dependencies) + +`ifdef DBG_TRACE_GBAR + always @(posedge clk) begin + if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin + `TRACE(1, ("%d: %s-acquire: bar_id=%0d, size=%0d, core_id=%0d\n", + $time, INSTANCE_ID, gbar_bus_if.req_id, gbar_bus_if.req_size_m1, gbar_bus_if.req_core_id)); + end + if (gbar_bus_if.rsp_valid) begin + `TRACE(1, ("%d: %s-release: bar_id=%0d\n", $time, INSTANCE_ID, gbar_bus_if.rsp_id)); + end + end +`endif + +endmodule diff --git a/hw/rtl/mem/VX_mem_arb.sv b/hw/rtl/mem/VX_mem_arb.sv new file mode 100644 index 00000000..939dd6ba --- /dev/null +++ b/hw/rtl/mem/VX_mem_arb.sv @@ -0,0 +1,177 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_mem_arb #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATA_SIZE = 1, + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)), + parameter TAG_WIDTH = 1, + parameter TAG_SEL_IDX = 0, + parameter OUT_REG_REQ = 0, + parameter OUT_REG_RSP = 0, + parameter `STRING ARBITER = "R" +) ( + input wire clk, + input wire reset, + + VX_mem_bus_if.slave bus_in_if [NUM_INPUTS], + VX_mem_bus_if.master bus_out_if [NUM_OUTPUTS] +); + localparam DATA_WIDTH = (8 * DATA_SIZE); + localparam LOG_NUM_REQS = `ARB_SEL_BITS(NUM_INPUTS, NUM_OUTPUTS); + localparam REQ_DATAW = TAG_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH; + localparam RSP_DATAW = TAG_WIDTH + DATA_WIDTH; + + `STATIC_ASSERT ((NUM_INPUTS >= NUM_OUTPUTS), ("invalid parameter")) + + wire [NUM_INPUTS-1:0] req_valid_in; + wire [NUM_INPUTS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_INPUTS-1:0] req_ready_in; + + wire [NUM_OUTPUTS-1:0] req_valid_out; + wire [NUM_OUTPUTS-1:0][REQ_DATAW-1:0] req_data_out; + wire [NUM_OUTPUTS-1:0][`UP(LOG_NUM_REQS)-1:0] req_sel_out; + wire [NUM_OUTPUTS-1:0] req_ready_out; + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + assign req_valid_in[i] = bus_in_if[i].req_valid; + assign req_data_in[i] = {bus_in_if[i].req_data.tag, bus_in_if[i].req_data.addr, bus_in_if[i].req_data.rw, bus_in_if[i].req_data.byteen, bus_in_if[i].req_data.data}; + assign bus_in_if[i].req_ready = req_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_OUTPUTS), + .DATAW (REQ_DATAW), + .ARBITER (ARBITER), + .OUT_REG (OUT_REG_REQ) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (req_valid_in), + .ready_in (req_ready_in), + .data_in (req_data_in), + .data_out (req_data_out), + .sel_out (req_sel_out), + .valid_out (req_valid_out), + .ready_out (req_ready_out) + ); + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + wire [TAG_WIDTH-1:0] req_tag_out; + VX_bits_insert #( + .N (TAG_WIDTH), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_insert ( + .data_in (req_tag_out), + .sel_in (req_sel_out[i]), + .data_out (bus_out_if[i].req_data.tag) + ); + assign bus_out_if[i].req_valid = req_valid_out[i]; + assign {req_tag_out, bus_out_if[i].req_data.addr, bus_out_if[i].req_data.rw, bus_out_if[i].req_data.byteen, bus_out_if[i].req_data.data} = req_data_out[i]; + assign req_ready_out[i] = bus_out_if[i].req_ready; + end + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_INPUTS-1:0] rsp_valid_out; + wire [NUM_INPUTS-1:0][RSP_DATAW-1:0] rsp_data_out; + wire [NUM_INPUTS-1:0] rsp_ready_out; + + wire [NUM_OUTPUTS-1:0] rsp_valid_in; + wire [NUM_OUTPUTS-1:0][RSP_DATAW-1:0] rsp_data_in; + wire [NUM_OUTPUTS-1:0] rsp_ready_in; + + if (NUM_INPUTS > NUM_OUTPUTS) begin + + wire [NUM_OUTPUTS-1:0][LOG_NUM_REQS-1:0] rsp_sel_in; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + wire [TAG_WIDTH-1:0] rsp_tag_out; + VX_bits_remove #( + .N (TAG_WIDTH + LOG_NUM_REQS), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_remove ( + .data_in (bus_out_if[i].rsp_data.tag), + .data_out (rsp_tag_out) + ); + + assign rsp_valid_in[i] = bus_out_if[i].rsp_valid; + assign rsp_data_in[i] = {rsp_tag_out, bus_out_if[i].rsp_data.data}; + assign bus_out_if[i].rsp_ready = rsp_ready_in[i]; + + if (NUM_INPUTS > 1) begin + assign rsp_sel_in[i] = bus_out_if[i].rsp_data.tag[TAG_SEL_IDX +: LOG_NUM_REQS]; + end else begin + assign rsp_sel_in[i] = '0; + end + end + + VX_stream_switch #( + .NUM_INPUTS (NUM_OUTPUTS), + .NUM_OUTPUTS (NUM_INPUTS), + .DATAW (RSP_DATAW), + .OUT_REG (OUT_REG_RSP) + ) rsp_switch ( + .clk (clk), + .reset (reset), + .sel_in (rsp_sel_in), + .valid_in (rsp_valid_in), + .ready_in (rsp_ready_in), + .data_in (rsp_data_in), + .data_out (rsp_data_out), + .valid_out (rsp_valid_out), + .ready_out (rsp_ready_out) + ); + + end else begin + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin + assign rsp_valid_in[i] = bus_out_if[i].rsp_valid; + assign rsp_data_in[i] = {bus_out_if[i].rsp_data.tag, bus_out_if[i].rsp_data.data}; + assign bus_out_if[i].rsp_ready = rsp_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_OUTPUTS), + .NUM_OUTPUTS (NUM_INPUTS), + .DATAW (RSP_DATAW), + .ARBITER (ARBITER), + .OUT_REG (OUT_REG_RSP) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_valid_in), + .ready_in (rsp_ready_in), + .data_in (rsp_data_in), + .data_out (rsp_data_out), + .valid_out (rsp_valid_out), + .ready_out (rsp_ready_out), + `UNUSED_PIN (sel_out) + ); + + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin + assign bus_in_if[i].rsp_valid = rsp_valid_out[i]; + assign {bus_in_if[i].rsp_data.tag, bus_in_if[i].rsp_data.data} = rsp_data_out[i]; + assign rsp_ready_out[i] = bus_in_if[i].rsp_ready; + end + +endmodule diff --git a/hw/rtl/mem/VX_mem_bus_if.sv b/hw/rtl/mem/VX_mem_bus_if.sv new file mode 100644 index 00000000..33c5e6f4 --- /dev/null +++ b/hw/rtl/mem/VX_mem_bus_if.sv @@ -0,0 +1,64 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_mem_bus_if #( + parameter DATA_SIZE = 1, + parameter TAG_WIDTH = 1, + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter ADDR_WIDTH = MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE) +) (); + + typedef struct packed { + logic rw; + logic [DATA_SIZE-1:0] byteen; + logic [ADDR_WIDTH-1:0] addr; + logic [DATA_SIZE*8-1:0] data; + logic [TAG_WIDTH-1:0] tag; + } req_data_t; + + typedef struct packed { + logic [DATA_SIZE*8-1:0] data; + logic [TAG_WIDTH-1:0] tag; + } rsp_data_t; + + logic req_valid; + req_data_t req_data; + logic req_ready; + + logic rsp_valid; + rsp_data_t rsp_data; + logic rsp_ready; + + modport master ( + output req_valid, + output req_data, + input req_ready, + + input rsp_valid, + input rsp_data, + output rsp_ready + ); + + modport slave ( + input req_valid, + input req_data, + output req_ready, + + output rsp_valid, + output rsp_data, + input rsp_ready + ); + +endinterface diff --git a/hw/rtl/mem/VX_mem_perf_if.sv b/hw/rtl/mem/VX_mem_perf_if.sv new file mode 100644 index 00000000..277ebf1f --- /dev/null +++ b/hw/rtl/mem/VX_mem_perf_if.sv @@ -0,0 +1,118 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_mem_perf_if (); + + wire [`PERF_CTR_BITS-1:0] icache_reads; + wire [`PERF_CTR_BITS-1:0] icache_read_misses; + + wire [`PERF_CTR_BITS-1:0] dcache_reads; + wire [`PERF_CTR_BITS-1:0] dcache_writes; + wire [`PERF_CTR_BITS-1:0] dcache_read_misses; + wire [`PERF_CTR_BITS-1:0] dcache_write_misses; + wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls; + wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls; + + wire [`PERF_CTR_BITS-1:0] smem_reads; + wire [`PERF_CTR_BITS-1:0] smem_writes; + wire [`PERF_CTR_BITS-1:0] smem_bank_stalls; + + wire [`PERF_CTR_BITS-1:0] l2cache_reads; + wire [`PERF_CTR_BITS-1:0] l2cache_writes; + wire [`PERF_CTR_BITS-1:0] l2cache_read_misses; + wire [`PERF_CTR_BITS-1:0] l2cache_write_misses; + wire [`PERF_CTR_BITS-1:0] l2cache_bank_stalls; + wire [`PERF_CTR_BITS-1:0] l2cache_mshr_stalls; + + wire [`PERF_CTR_BITS-1:0] l3cache_reads; + wire [`PERF_CTR_BITS-1:0] l3cache_writes; + wire [`PERF_CTR_BITS-1:0] l3cache_read_misses; + wire [`PERF_CTR_BITS-1:0] l3cache_write_misses; + wire [`PERF_CTR_BITS-1:0] l3cache_bank_stalls; + wire [`PERF_CTR_BITS-1:0] l3cache_mshr_stalls; + + wire [`PERF_CTR_BITS-1:0] mem_reads; + wire [`PERF_CTR_BITS-1:0] mem_writes; + wire [`PERF_CTR_BITS-1:0] mem_latency; + + modport master ( + output icache_reads, + output icache_read_misses, + + output dcache_reads, + output dcache_writes, + output dcache_read_misses, + output dcache_write_misses, + output dcache_bank_stalls, + output dcache_mshr_stalls, + + output smem_reads, + output smem_writes, + output smem_bank_stalls, + + output l2cache_reads, + output l2cache_writes, + output l2cache_read_misses, + output l2cache_write_misses, + output l2cache_bank_stalls, + output l2cache_mshr_stalls, + + output l3cache_reads, + output l3cache_writes, + output l3cache_read_misses, + output l3cache_write_misses, + output l3cache_bank_stalls, + output l3cache_mshr_stalls, + + output mem_reads, + output mem_writes, + output mem_latency + ); + + modport slave ( + input icache_reads, + input icache_read_misses, + + input dcache_reads, + input dcache_writes, + input dcache_read_misses, + input dcache_write_misses, + input dcache_bank_stalls, + input dcache_mshr_stalls, + + input smem_reads, + input smem_writes, + input smem_bank_stalls, + + input l2cache_reads, + input l2cache_writes, + input l2cache_read_misses, + input l2cache_write_misses, + input l2cache_bank_stalls, + input l2cache_mshr_stalls, + + input l3cache_reads, + input l3cache_writes, + input l3cache_read_misses, + input l3cache_write_misses, + input l3cache_bank_stalls, + input l3cache_mshr_stalls, + + input mem_reads, + input mem_writes, + input mem_latency + ); + +endinterface diff --git a/hw/rtl/mem/VX_mem_unit.sv b/hw/rtl/mem/VX_mem_unit.sv new file mode 100644 index 00000000..0f293a7e --- /dev/null +++ b/hw/rtl/mem/VX_mem_unit.sv @@ -0,0 +1,209 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`define SMEM_ADDR_STACK_OPT + +module VX_mem_unit import VX_gpu_pkg::*; #( + parameter CLUSTER_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + VX_mem_perf_if.master mem_perf_if, +`endif + + VX_mem_bus_if.slave icache_bus_if [`NUM_SOCKETS], + + VX_mem_bus_if.slave dcache_bus_if [`NUM_SOCKETS * DCACHE_NUM_REQS], + + VX_mem_bus_if.master mem_bus_if +); + +`ifdef PERF_ENABLE + VX_cache_perf_if perf_icache_if(); + VX_cache_perf_if perf_dcache_if(); + VX_cache_perf_if perf_l2cache_if(); +`endif + +/////////////////////////////// I-Cache /////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_LINE_SIZE), + .TAG_WIDTH (ICACHE_MEM_TAG_WIDTH) + ) icache_mem_bus_if(); + + `RESET_RELAY (icache_reset, reset); + + VX_cache_cluster #( + .INSTANCE_ID ($sformatf("cluster%0d-icache", CLUSTER_ID)), + .NUM_UNITS (`NUM_ICACHES), + .NUM_INPUTS (`NUM_SOCKETS), + .TAG_SEL_IDX (0), + .CACHE_SIZE (`ICACHE_SIZE), + .LINE_SIZE (ICACHE_LINE_SIZE), + .NUM_BANKS (1), + .NUM_WAYS (`ICACHE_NUM_WAYS), + .WORD_SIZE (ICACHE_WORD_SIZE), + .NUM_REQS (1), + .CRSQ_SIZE (`ICACHE_CRSQ_SIZE), + .MSHR_SIZE (`ICACHE_MSHR_SIZE), + .MRSQ_SIZE (`ICACHE_MRSQ_SIZE), + .MREQ_SIZE (`ICACHE_MREQ_SIZE), + .TAG_WIDTH (ICACHE_ARB_TAG_WIDTH), + .UUID_WIDTH (`UUID_WIDTH), + .WRITE_ENABLE (0), + .CORE_OUT_REG (2), + .MEM_OUT_REG (2) + ) icache ( + `ifdef PERF_ENABLE + .cache_perf_if (perf_icache_if), + `endif + .clk (clk), + .reset (icache_reset), + .core_bus_if (icache_bus_if), + .mem_bus_if (icache_mem_bus_if) + ); + +/////////////////////////////// D-Cache /////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_LINE_SIZE), + .TAG_WIDTH (DCACHE_MEM_TAG_WIDTH) + ) dcache_mem_bus_if(); + + `RESET_RELAY (dcache_reset, reset); + + VX_cache_cluster #( + .INSTANCE_ID ($sformatf("cluster%0d-dcache", CLUSTER_ID)), + .NUM_UNITS (`NUM_DCACHES), + .NUM_INPUTS (`NUM_SOCKETS), + .TAG_SEL_IDX (1), + .CACHE_SIZE (`DCACHE_SIZE), + .LINE_SIZE (DCACHE_LINE_SIZE), + .NUM_BANKS (`DCACHE_NUM_BANKS), + .NUM_WAYS (`DCACHE_NUM_WAYS), + .WORD_SIZE (DCACHE_WORD_SIZE), + .NUM_REQS (DCACHE_NUM_REQS), + .CRSQ_SIZE (`DCACHE_CRSQ_SIZE), + .MSHR_SIZE (`DCACHE_MSHR_SIZE), + .MRSQ_SIZE (`DCACHE_MRSQ_SIZE), + .MREQ_SIZE (`DCACHE_MREQ_SIZE), + .TAG_WIDTH (DCACHE_ARB_TAG_WIDTH), + .UUID_WIDTH (`UUID_WIDTH), + .WRITE_ENABLE (1), + .NC_ENABLE (1), + .CORE_OUT_REG (`SM_ENABLED ? 2 : 1), + .MEM_OUT_REG (2) + ) dcache ( + `ifdef PERF_ENABLE + .cache_perf_if (perf_dcache_if), + `endif + + .clk (clk), + .reset (dcache_reset), + .core_bus_if (dcache_bus_if), + .mem_bus_if (dcache_mem_bus_if) + ); + +/////////////////////////////// L2-Cache ////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (L2_WORD_SIZE), + .TAG_WIDTH (L2_TAG_WIDTH) + ) l2_mem_bus_if[L2_NUM_REQS](); + + localparam I_MEM_ARB_IDX = 0; + localparam D_MEM_ARB_IDX = I_MEM_ARB_IDX + 1; + + `ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[I_MEM_ARB_IDX], icache_mem_bus_if, L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH); + `ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[D_MEM_ARB_IDX], dcache_mem_bus_if, L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH); + + `RESET_RELAY (l2_reset, reset); + + VX_cache_wrap #( + .INSTANCE_ID ($sformatf("cluster%0d-l2cache", CLUSTER_ID)), + .CACHE_SIZE (`L2_CACHE_SIZE), + .LINE_SIZE (`L2_LINE_SIZE), + .NUM_BANKS (`L2_NUM_BANKS), + .NUM_WAYS (`L2_NUM_WAYS), + .WORD_SIZE (L2_WORD_SIZE), + .NUM_REQS (L2_NUM_REQS), + .CRSQ_SIZE (`L2_CRSQ_SIZE), + .MSHR_SIZE (`L2_MSHR_SIZE), + .MRSQ_SIZE (`L2_MRSQ_SIZE), + .MREQ_SIZE (`L2_MREQ_SIZE), + .TAG_WIDTH (L1_MEM_TAG_WIDTH), + .WRITE_ENABLE (1), + .UUID_WIDTH (`UUID_WIDTH), + .CORE_OUT_REG (2), + .MEM_OUT_REG (2), + .NC_ENABLE (1), + .PASSTHRU (!`L2_ENABLED) + ) l2cache ( + .clk (clk), + .reset (l2_reset), + `ifdef PERF_ENABLE + .cache_perf_if (perf_l2cache_if), + `endif + .core_bus_if (l2_mem_bus_if), + .mem_bus_if (mem_bus_if) + ); + +`ifdef PERF_ENABLE + + `UNUSED_VAR (perf_dcache_if.mem_stalls) + `UNUSED_VAR (perf_dcache_if.crsp_stalls) + + assign mem_perf_if.icache_reads = perf_icache_if.reads; + assign mem_perf_if.icache_read_misses = perf_icache_if.read_misses; + + assign mem_perf_if.dcache_reads = perf_dcache_if.reads; + assign mem_perf_if.dcache_writes = perf_dcache_if.writes; + assign mem_perf_if.dcache_read_misses = perf_dcache_if.read_misses; + assign mem_perf_if.dcache_write_misses= perf_dcache_if.write_misses; + assign mem_perf_if.dcache_bank_stalls = perf_dcache_if.bank_stalls; + assign mem_perf_if.dcache_mshr_stalls = perf_dcache_if.mshr_stalls; + +`ifdef L2_ENABLE + assign mem_perf_if.l2cache_reads = perf_l2cache_if.reads; + assign mem_perf_if.l2cache_writes = perf_l2cache_if.writes; + assign mem_perf_if.l2cache_read_misses = perf_l2cache_if.read_misses; + assign mem_perf_if.l2cache_write_misses= perf_l2cache_if.write_misses; + assign mem_perf_if.l2cache_bank_stalls = perf_l2cache_if.bank_stalls; + assign mem_perf_if.l2cache_mshr_stalls = perf_l2cache_if.mshr_stalls; +`else + assign mem_perf_if.l2cache_reads = '0; + assign mem_perf_if.l2cache_writes = '0; + assign mem_perf_if.l2cache_read_misses = '0; + assign mem_perf_if.l2cache_write_misses= '0; + assign mem_perf_if.l2cache_bank_stalls = '0; + assign mem_perf_if.l2cache_mshr_stalls = '0; +`endif + + assign mem_perf_if.l3cache_reads = '0; + assign mem_perf_if.l3cache_writes = '0; + assign mem_perf_if.l3cache_read_misses = '0; + assign mem_perf_if.l3cache_write_misses= '0; + assign mem_perf_if.l3cache_bank_stalls = '0; + assign mem_perf_if.l3cache_mshr_stalls = '0; + + assign mem_perf_if.mem_reads = '0; + assign mem_perf_if.mem_writes = '0; + assign mem_perf_if.mem_latency = '0; + +`endif + +endmodule diff --git a/hw/rtl/mem/VX_shared_mem.sv b/hw/rtl/mem/VX_shared_mem.sv new file mode 100644 index 00000000..ef19ef1c --- /dev/null +++ b/hw/rtl/mem/VX_shared_mem.sv @@ -0,0 +1,330 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_shared_mem #( + parameter `STRING INSTANCE_ID = "", + + // Size of cache in bytes + parameter SIZE = (1024*16*8), + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + // Number of banks + parameter NUM_BANKS = 4, + + // Address width + parameter ADDR_WIDTH = `CLOG2(SIZE), + // Size of a word in bytes + parameter WORD_SIZE = `XLEN/8, + + // Request debug identifier + parameter UUID_WIDTH = 0, + + // Request tag size + parameter TAG_WIDTH = 16 + ) ( + input wire clk, + input wire reset, + + // PERF +`ifdef PERF_ENABLE + VX_cache_perf_if.master cache_perf_if, +`endif + + // Core request + input wire [NUM_REQS-1:0] req_valid, + input wire [NUM_REQS-1:0] req_rw, + input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr, + input wire [NUM_REQS-1:0][WORD_SIZE-1:0] req_byteen, + input wire [NUM_REQS-1:0][WORD_SIZE*8-1:0] req_data, + input wire [NUM_REQS-1:0][TAG_WIDTH-1:0] req_tag, + output wire [NUM_REQS-1:0] req_ready, + + // Core response + output wire [NUM_REQS-1:0] rsp_valid, + output wire [NUM_REQS-1:0][WORD_SIZE*8-1:0] rsp_data, + output wire [NUM_REQS-1:0][TAG_WIDTH-1:0] rsp_tag, + input wire [NUM_REQS-1:0] rsp_ready +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (UUID_WIDTH) + + localparam REQ_SEL_BITS = `CLOG2(NUM_REQS); + localparam REQ_SEL_WIDTH = `UP(REQ_SEL_BITS); + localparam WORD_WIDTH = WORD_SIZE * 8; + localparam NUM_WORDS = SIZE / WORD_SIZE; + localparam WORDS_PER_BANK = NUM_WORDS / NUM_BANKS; + localparam BANK_ADDR_WIDTH = `CLOG2(WORDS_PER_BANK); + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam REQ_DATAW = 1 + BANK_ADDR_WIDTH + WORD_SIZE + WORD_WIDTH + TAG_WIDTH; + localparam RSP_DATAW = WORD_WIDTH + TAG_WIDTH; + + `STATIC_ASSERT(ADDR_WIDTH == (BANK_ADDR_WIDTH + `CLOG2(NUM_BANKS)), ("invalid parameter")) + + // bank selection + + wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] req_bank_idx; + if (NUM_BANKS > 1) begin + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign req_bank_idx[i] = req_addr[i][0 +: BANK_SEL_BITS]; + end + end else begin + assign req_bank_idx = 0; + end + + // bank addressing + + wire [NUM_REQS-1:0][BANK_ADDR_WIDTH-1:0] req_bank_addr; + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign req_bank_addr[i] = req_addr[i][BANK_SEL_BITS +: BANK_ADDR_WIDTH]; + end + + // bank requests dispatch + + wire [NUM_BANKS-1:0] per_bank_req_valid; + wire [NUM_BANKS-1:0] per_bank_req_rw; + wire [NUM_BANKS-1:0][BANK_ADDR_WIDTH-1:0] per_bank_req_addr; + wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_req_byteen; + wire [NUM_BANKS-1:0][WORD_WIDTH-1:0] per_bank_req_data; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_req_tag; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_req_idx; + wire [NUM_BANKS-1:0] per_bank_req_ready; + + wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_BANKS-1:0][REQ_DATAW-1:0] req_data_out; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign req_data_in[i] = { + req_rw[i], + req_bank_addr[i], + req_byteen[i], + req_data[i], + req_tag[i]}; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS (NUM_BANKS), + .DATAW (REQ_DATAW), + .PERF_CTR_BITS (`PERF_CTR_BITS), + .OUT_REG (3) // output should be registered for the data_store addressing + ) req_xbar ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .collisions (cache_perf_if.bank_stalls), + `else + `UNUSED_PIN (collisions), + `endif + .valid_in (req_valid), + .data_in (req_data_in), + .sel_in (req_bank_idx), + .ready_in (req_ready), + .valid_out (per_bank_req_valid), + .data_out (req_data_out), + .sel_out (per_bank_req_idx), + .ready_out (per_bank_req_ready) + ); + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign { + per_bank_req_rw[i], + per_bank_req_addr[i], + per_bank_req_byteen[i], + per_bank_req_data[i], + per_bank_req_tag[i]} = req_data_out[i]; + end + + // banks access + + wire [NUM_BANKS-1:0] per_bank_rsp_valid; + wire [NUM_BANKS-1:0][WORD_WIDTH-1:0] per_bank_rsp_data; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_rsp_idx; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_rsp_tag; + wire [NUM_BANKS-1:0] per_bank_rsp_ready; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + VX_sp_ram #( + .DATAW (WORD_WIDTH), + .SIZE (WORDS_PER_BANK), + .WRENW (WORD_SIZE) + ) data_store ( + .clk (clk), + .read (1'b1), + .write (per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i]), + .wren (per_bank_req_byteen[i]), + .addr (per_bank_req_addr[i]), + .wdata (per_bank_req_data[i]), + .rdata (per_bank_rsp_data[i]) + ); + + // drop write response + wire per_bank_req_valid_w, per_bank_req_ready_w; + assign per_bank_req_valid_w = per_bank_req_valid[i] && ~per_bank_req_rw[i]; + assign per_bank_req_ready[i] = per_bank_req_ready_w || per_bank_req_rw[i]; + + VX_elastic_buffer #( + .DATAW (REQ_SEL_WIDTH + TAG_WIDTH), + .SIZE (0) + ) bank_buf ( + .clk (clk), + .reset (reset), + .valid_in (per_bank_req_valid_w), + .ready_in (per_bank_req_ready_w), + .data_in ({per_bank_req_idx[i], per_bank_req_tag[i]}), + .data_out ({per_bank_rsp_idx[i], per_bank_rsp_tag[i]}), + .valid_out (per_bank_rsp_valid[i]), + .ready_out (per_bank_rsp_ready[i]) + ); + end + + // bank responses gather + + wire [NUM_BANKS-1:0][RSP_DATAW-1:0] rsp_data_in; + wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + assign rsp_data_in[i] = {per_bank_rsp_data[i], per_bank_rsp_tag[i]}; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_BANKS), + .NUM_OUTPUTS (NUM_REQS), + .DATAW (RSP_DATAW), + .OUT_REG (2) + ) rsp_xbar ( + .clk (clk), + .reset (reset), + `UNUSED_PIN (collisions), + .sel_in (per_bank_rsp_idx), + .valid_in (per_bank_rsp_valid), + .ready_in (per_bank_rsp_ready), + .data_in (rsp_data_in), + .data_out (rsp_data_out), + .valid_out (rsp_valid), + .ready_out (rsp_ready), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign {rsp_data[i], rsp_tag[i]} = rsp_data_out[i]; + end + +`ifdef PERF_ENABLE + // per cycle: reads, writes + wire [`CLOG2(NUM_REQS+1)-1:0] perf_reads_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_writes_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle; + + wire [NUM_REQS-1:0] perf_reads_per_req = req_valid & req_ready & ~req_rw; + wire [NUM_REQS-1:0] perf_writes_per_req = req_valid & req_ready & req_rw; + wire [NUM_REQS-1:0] perf_crsp_stall_per_req = rsp_valid & ~rsp_ready; + + `POP_COUNT(perf_reads_per_cycle, perf_reads_per_req); + `POP_COUNT(perf_writes_per_cycle, perf_writes_per_req); + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req); + + reg [`PERF_CTR_BITS-1:0] perf_reads; + reg [`PERF_CTR_BITS-1:0] perf_writes; + reg [`PERF_CTR_BITS-1:0] perf_crsp_stalls; + + always @(posedge clk) begin + if (reset) begin + perf_reads <= '0; + perf_writes <= '0; + perf_crsp_stalls <= '0; + end else begin + perf_reads <= perf_reads + `PERF_CTR_BITS'(perf_reads_per_cycle); + perf_writes <= perf_writes + `PERF_CTR_BITS'(perf_writes_per_cycle); + perf_crsp_stalls <= perf_crsp_stalls + `PERF_CTR_BITS'(perf_crsp_stall_per_cycle); + end + end + + assign cache_perf_if.reads = perf_reads; + assign cache_perf_if.writes = perf_writes; + assign cache_perf_if.read_misses = '0; + assign cache_perf_if.write_misses = '0; + assign cache_perf_if.mshr_stalls = '0; + assign cache_perf_if.mem_stalls = '0; + assign cache_perf_if.crsp_stalls = perf_crsp_stalls; + +`endif + +`ifdef DBG_TRACE_CACHE_BANK + + wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] req_uuid; + wire [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] rsp_uuid; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + if (UUID_WIDTH != 0) begin + assign req_uuid[i] = req_tag[i][TAG_WIDTH-1 -: UUID_WIDTH]; + assign rsp_uuid[i] = rsp_tag[i][TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin + assign req_uuid[i] = 0; + assign rsp_uuid[i] = 0; + end + end + + wire [NUM_BANKS-1:0][`UP(UUID_WIDTH)-1:0] per_bank_req_uuid; + wire [NUM_BANKS-1:0][`UP(UUID_WIDTH)-1:0] per_bank_rsp_uuid; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin + if (UUID_WIDTH != 0) begin + assign per_bank_req_uuid[i] = per_bank_req_tag[i][TAG_WIDTH-1 -: UUID_WIDTH]; + assign per_bank_rsp_uuid[i] = per_bank_rsp_tag[i][TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin + assign per_bank_req_uuid[i] = 0; + assign per_bank_rsp_uuid[i] = 0; + end + end + + always @(posedge clk) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + if (req_valid[i] && req_ready[i]) begin + if (req_rw[i]) begin + `TRACE(1, ("%d: %s wr-req: req_idx=%0d, addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, req_addr[i], req_tag[i], req_byteen[i], req_data[i], req_uuid[i])); + end else begin + `TRACE(1, ("%d: %s rd-req: req_idx=%0d, addr=0x%0h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, req_addr[i], req_tag[i], req_uuid[i])); + end + end + if (rsp_valid[i] && rsp_ready[i]) begin + `TRACE(1, ("%d: %s rd-rsp: req_idx=%0d, tag=0x%0h, data=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, rsp_tag[i], rsp_data[i], rsp_uuid[i])); + end + end + + for (integer i = 0; i < NUM_BANKS; ++i) begin + if (per_bank_req_valid[i] && per_bank_req_ready[i]) begin + if (per_bank_req_rw[i]) begin + `TRACE(2, ("%d: %s-bank%0d wr-req: addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, per_bank_req_addr[i], per_bank_req_tag[i], per_bank_req_byteen[i], per_bank_req_data[i], per_bank_req_uuid[i])); + end else begin + `TRACE(2, ("%d: %s-bank%0d rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, per_bank_req_addr[i], per_bank_req_tag[i], per_bank_req_uuid[i])); + end + end + if (per_bank_rsp_valid[i] && per_bank_rsp_ready[i]) begin + `TRACE(2, ("%d: %s-bank%0d rd-rsp: tag=0x%0h, data=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, per_bank_rsp_tag[i], per_bank_rsp_data[i], per_bank_rsp_uuid[i])); + end + end + end + +`endif + +endmodule diff --git a/hw/rtl/mem/VX_smem_switch.sv b/hw/rtl/mem/VX_smem_switch.sv new file mode 100644 index 00000000..7dc410a9 --- /dev/null +++ b/hw/rtl/mem/VX_smem_switch.sv @@ -0,0 +1,130 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_smem_switch #( + parameter NUM_REQS = 1, + parameter DATA_SIZE = 1, + parameter TAG_WIDTH = 1, + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter TAG_SEL_IDX = 0, + parameter OUT_REG_REQ = 0, + parameter OUT_REG_RSP = 0, + parameter `STRING ARBITER = "R" +) ( + input wire clk, + input wire reset, + + VX_mem_bus_if.slave bus_in_if, + VX_mem_bus_if.master bus_out_if [NUM_REQS] +); + localparam ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)); + localparam DATA_WIDTH = (8 * DATA_SIZE); + localparam LOG_NUM_REQS = `CLOG2(NUM_REQS); + localparam TAG_OUT_WIDTH = TAG_WIDTH - LOG_NUM_REQS; + localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH; + localparam RSP_DATAW = TAG_OUT_WIDTH + DATA_WIDTH; + + wire [NUM_REQS-1:0] req_valid_out; + wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_out; + wire [NUM_REQS-1:0] req_ready_out; + + wire [REQ_DATAW-1:0] req_data_in; + wire [TAG_OUT_WIDTH-1:0] req_tag_in; + wire [`UP(LOG_NUM_REQS)-1:0] req_sel_in; + + VX_bits_remove #( + .N (TAG_WIDTH), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_remove ( + .data_in (bus_in_if.req_data.tag), + .data_out (req_tag_in) + ); + + if (NUM_REQS > 1) begin + assign req_sel_in = bus_in_if.req_data.tag[TAG_SEL_IDX +: LOG_NUM_REQS]; + end else begin + assign req_sel_in = '0; + end + + assign req_data_in = {req_tag_in, bus_in_if.req_data.addr, bus_in_if.req_data.rw, bus_in_if.req_data.byteen, bus_in_if.req_data.data}; + + VX_stream_switch #( + .NUM_OUTPUTS (NUM_REQS), + .DATAW (REQ_DATAW), + .OUT_REG (OUT_REG_REQ) + ) req_switch ( + .clk (clk), + .reset (reset), + .sel_in (req_sel_in), + .valid_in (bus_in_if.req_valid), + .ready_in (bus_in_if.req_ready), + .data_in (req_data_in), + .data_out (req_data_out), + .valid_out (req_valid_out), + .ready_out (req_ready_out) + ); + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign bus_out_if[i].req_valid = req_valid_out[i]; + assign {bus_out_if[i].req_data.tag, bus_out_if[i].req_data.addr, bus_out_if[i].req_data.rw, bus_out_if[i].req_data.byteen, bus_out_if[i].req_data.data} = req_data_out[i]; + assign req_ready_out[i] = bus_out_if[i].req_ready; + end + + /////////////////////////////////////////////////////////////////////// + + wire [NUM_REQS-1:0] rsp_valid_out; + wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out; + wire [NUM_REQS-1:0] rsp_ready_out; + wire [RSP_DATAW-1:0] rsp_data_in; + wire [TAG_OUT_WIDTH-1:0] rsp_tag_in; + wire [`UP(LOG_NUM_REQS)-1:0] rsp_sel_in; + + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign rsp_valid_out[i] = bus_out_if[i].rsp_valid; + assign rsp_data_out[i] = {bus_out_if[i].rsp_data.tag, bus_out_if[i].rsp_data.data}; + assign bus_out_if[i].rsp_ready = rsp_ready_out[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_REQS), + .DATAW (RSP_DATAW), + .ARBITER (ARBITER), + .OUT_REG (OUT_REG_RSP) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_valid_out), + .ready_in (rsp_ready_out), + .data_in (rsp_data_out), + .data_out (rsp_data_in), + .sel_out (rsp_sel_in), + .valid_out (bus_in_if.rsp_valid), + .ready_out (bus_in_if.rsp_ready) + ); + + VX_bits_insert #( + .N (TAG_OUT_WIDTH), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_insert ( + .data_in (rsp_tag_in), + .sel_in (rsp_sel_in), + .data_out (bus_in_if.rsp_data.tag) + ); + + assign {rsp_tag_in, bus_in_if.rsp_data.data} = rsp_data_in; + +endmodule diff --git a/hw/rtl/tex_unit/VX_tex_addr.sv b/hw/rtl/tex_unit/VX_tex_addr.sv deleted file mode 100644 index 87da9cef..00000000 --- a/hw/rtl/tex_unit/VX_tex_addr.sv +++ /dev/null @@ -1,207 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_addr #( - parameter CORE_ID = 0, - parameter REQ_INFOW = 1, - parameter NUM_REQS = 1 -) ( - input wire clk, - input wire reset, - - // inputs - - input wire req_valid, - input wire [NUM_REQS-1:0] req_tmask, - input wire [1:0][NUM_REQS-1:0][`TEX_FXD_BITS-1:0] req_coords, - input wire [`TEX_FORMAT_BITS-1:0] req_format, - input wire [`TEX_FILTER_BITS-1:0] req_filter, - input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps, - input wire [`TEX_ADDR_BITS-1:0] req_baseaddr, - input wire [NUM_REQS-1:0][`TEX_LOD_BITS-1:0] mip_level, - input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff, - input wire [NUM_REQS-1:0][1:0][`TEX_LOD_BITS-1:0] req_logdims, - input wire [REQ_INFOW-1:0] req_info, - output wire req_ready, - - // outputs - - output wire rsp_valid, - output wire [NUM_REQS-1:0] rsp_tmask, - output wire [`TEX_FILTER_BITS-1:0] rsp_filter, - output wire [`TEX_LGSTRIDE_BITS-1:0] rsp_lgstride, - output wire [NUM_REQS-1:0][31:0] rsp_baseaddr, - output wire [NUM_REQS-1:0][3:0][31:0] rsp_addr, - output wire [NUM_REQS-1:0][1:0][`TEX_BLEND_FRAC-1:0] rsp_blends, - output wire [REQ_INFOW-1:0] rsp_info, - input wire rsp_ready -); - - `UNUSED_PARAM (CORE_ID) - - localparam SHIFT_BITS = $clog2(`TEX_FXD_FRAC+1); - localparam PITCH_BITS = `MAX(`TEX_LOD_BITS, `TEX_LGSTRIDE_BITS) + 1; - localparam SCALED_DIM = `TEX_FXD_FRAC + `TEX_DIM_BITS; - localparam SCALED_X_W = `TEX_DIM_BITS + `TEX_BLEND_FRAC; - localparam OFFSET_U_W = `TEX_DIM_BITS + `TEX_LGSTRIDE_MAX; - localparam OFFSET_V_W = `TEX_DIM_BITS + `TEX_DIM_BITS + `TEX_LGSTRIDE_MAX; - - wire valid_s0; - wire [NUM_REQS-1:0] tmask_s0; - wire [`TEX_FILTER_BITS-1:0] filter_s0; - wire [REQ_INFOW-1:0] req_info_s0; - wire [NUM_REQS-1:0][1:0][`TEX_FXD_FRAC-1:0] clamped_lo, clamped_lo_s0; - wire [NUM_REQS-1:0][1:0][`TEX_FXD_FRAC-1:0] clamped_hi, clamped_hi_s0; - wire [NUM_REQS-1:0][1:0][SHIFT_BITS-1:0] dim_shift, dim_shift_s0; - wire [`TEX_LGSTRIDE_BITS-1:0] log_stride, log_stride_s0; - wire [NUM_REQS-1:0][31:0] mip_addr, mip_addr_s0; - wire [NUM_REQS-1:0][PITCH_BITS-1:0] log_pitch, log_pitch_s0; - wire [NUM_REQS-1:0][PITCH_BITS-1:0] log_pitch, log_pitch_s0; - - wire stall_out; - - // stride - - VX_tex_stride #( - .CORE_ID (CORE_ID) - ) tex_stride ( - .format (req_format), - .log_stride (log_stride) - ); - - // addressing mode - - for (genvar i = 0; i < NUM_REQS; ++i) begin - for (genvar j = 0; j < 2; ++j) begin - wire [`TEX_FXD_FRAC-1:0] delta = `TEX_FXD_FRAC'((SCALED_DIM'(`TEX_FXD_HALF) << mip_level[i]) >> req_logdims[i][j]); - wire [`TEX_FXD_BITS-1:0] coord_lo = req_filter ? (req_coords[j][i] - `TEX_FXD_BITS'(delta)) : req_coords[j][i]; - wire [`TEX_FXD_BITS-1:0] coord_hi = req_filter ? (req_coords[j][i] + `TEX_FXD_BITS'(delta)) : req_coords[j][i]; - - VX_tex_wrap #( - .CORE_ID (CORE_ID) - ) tex_wrap_lo ( - .wrap_i (req_wraps[j]), - .coord_i (coord_lo), - .coord_o (clamped_lo[i][j]) - ); - - VX_tex_wrap #( - .CORE_ID (CORE_ID) - ) tex_wrap_hi ( - .wrap_i (req_wraps[j]), - .coord_i (coord_hi), - .coord_o (clamped_hi[i][j]) - ); - - assign dim_shift[i][j] = (`TEX_FXD_FRAC - `TEX_BLEND_FRAC - (req_logdims[i][j] - mip_level[i])); - end - assign log_pitch[i] = PITCH_BITS'(req_logdims[i][0] - mip_level[i]) + PITCH_BITS'(log_stride); - assign mip_addr[i] = req_baseaddr + `TEX_ADDR_BITS'(req_mipoff[i]); - end - - VX_pipe_register #( - .DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_LGSTRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + 2 * SHIFT_BITS + `TEX_ADDR_BITS + 2 * 2 * `TEX_FXD_FRAC)), - .RESETW (1) - ) pipe_reg0 ( - .clk (clk), - .reset (reset), - .enable (~stall_out), - .data_in ({req_valid, req_tmask, req_filter, log_stride, req_info, log_pitch, dim_shift, mip_addr, clamped_lo, clamped_hi}), - .data_out ({valid_s0, tmask_s0, filter_s0, log_stride_s0, req_info_s0, log_pitch_s0, dim_shift_s0, mip_addr_s0, clamped_lo_s0, clamped_hi_s0}) - ); - - // addresses generation - - wire [NUM_REQS-1:0][1:0][SCALED_X_W-1:0] scaled_lo; - wire [NUM_REQS-1:0][1:0][SCALED_X_W-1:0] scaled_hi; - wire [NUM_REQS-1:0][OFFSET_U_W-1:0] offset_u_lo; - wire [NUM_REQS-1:0][OFFSET_U_W-1:0] offset_u_hi; - wire [NUM_REQS-1:0][OFFSET_V_W-1:0] offset_v_lo; - wire [NUM_REQS-1:0][OFFSET_V_W-1:0] offset_v_hi; - wire [NUM_REQS-1:0][1:0][`TEX_BLEND_FRAC-1:0] blends; - wire [NUM_REQS-1:0][3:0][31:0] addr; - - for (genvar i = 0; i < NUM_REQS; ++i) begin - for (genvar j = 0; j < 2; ++j) begin - assign scaled_lo[i][j] = SCALED_X_W'(clamped_lo_s0[i][j] >> dim_shift_s0[i][j]); - assign scaled_hi[i][j] = SCALED_X_W'(clamped_hi_s0[i][j] >> dim_shift_s0[i][j]); - assign blends[i][j] = filter_s0 ? scaled_lo[i][j][`TEX_BLEND_FRAC-1:0] : `TEX_BLEND_FRAC'(0); - end - end - - for (genvar i = 0; i < NUM_REQS; ++i) begin - assign offset_u_lo[i] = OFFSET_U_W'(scaled_lo[i][0][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_stride_s0; - assign offset_u_hi[i] = OFFSET_U_W'(scaled_hi[i][0][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_stride_s0; - - assign offset_v_lo[i] = OFFSET_V_W'(scaled_lo[i][1][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_pitch_s0[i]; - assign offset_v_hi[i] = OFFSET_V_W'(scaled_hi[i][1][`TEX_BLEND_FRAC +: `TEX_DIM_BITS]) << log_pitch_s0[i]; - - assign addr[i][0] = 32'(offset_v_lo[i]) + 32'(offset_u_lo[i]); - assign addr[i][1] = 32'(offset_v_lo[i]) + 32'(offset_u_hi[i]); - assign addr[i][2] = 32'(offset_v_hi[i]) + 32'(offset_u_lo[i]); - assign addr[i][3] = 32'(offset_v_hi[i]) + 32'(offset_u_hi[i]); - end - - assign stall_out = rsp_valid && ~rsp_ready; - - VX_pipe_register #( - .DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_LGSTRIDE_BITS + (NUM_REQS * 32) + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `TEX_BLEND_FRAC) + REQ_INFOW), - .RESETW (1) - ) pipe_reg1 ( - .clk (clk), - .reset (reset), - .enable (~stall_out), - .data_in ({valid_s0, tmask_s0, filter_s0, log_stride_s0, mip_addr_s0, addr, blends, req_info_s0}), - .data_out ({rsp_valid, rsp_tmask, rsp_filter, rsp_lgstride, rsp_baseaddr, rsp_addr, rsp_blends, rsp_info}) - ); - - assign req_ready = ~stall_out; - -`ifdef DBG_TRACE_TEX - wire [`NW_BITS-1:0] rsp_wid; - wire [31:0] rsp_PC; - - assign {rsp_wid, rsp_PC} = rsp_info[`NW_BITS+32-1:0]; - - always @(posedge clk) begin - if (req_valid && ~stall_out) begin - dpi_trace("%d: *** log_pitch=", $time); - `TRACE_ARRAY1D(log_pitch, NUM_REQS); - dpi_trace(", mip_addr="); - `TRACE_ARRAY1D(mip_addr, NUM_REQS); - dpi_trace(", req_logdims="); - `TRACE_ARRAY2D(req_logdims, 2, NUM_REQS); - dpi_trace(", clamped_lo="); - `TRACE_ARRAY2D(clamped_lo, 2, NUM_REQS); - dpi_trace(", clamped_hi="); - `TRACE_ARRAY2D(clamped_hi, 2, NUM_REQS); - dpi_trace(", mip_addr="); - `TRACE_ARRAY1D(mip_addr, NUM_REQS); - dpi_trace("\n"); - end - - if (valid_s0 && ~stall_out) begin - dpi_trace("%d: *** scaled_lo=", $time); - `TRACE_ARRAY2D(scaled_lo, 2, NUM_REQS); - dpi_trace(", scaled_hi="); - `TRACE_ARRAY2D(scaled_hi, 2, NUM_REQS); - dpi_trace(", offset_u_lo="); - `TRACE_ARRAY1D(offset_u_lo, NUM_REQS); - dpi_trace(", offset_u_hi="); - `TRACE_ARRAY1D(offset_u_hi, NUM_REQS); - dpi_trace(", offset_v_lo="); - `TRACE_ARRAY1D(offset_v_lo, NUM_REQS); - dpi_trace(", offset_v_hi="); - `TRACE_ARRAY1D(offset_v_hi, NUM_REQS); - dpi_trace("\n"); - end - - if (rsp_valid && rsp_ready) begin - dpi_trace("%d: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, req_filter=%0d, lgstride=%0d, addr=", - $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_lgstride); - `TRACE_ARRAY2D(rsp_addr, 4, NUM_REQS); - dpi_trace("\n"); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_define.vh b/hw/rtl/tex_unit/VX_tex_define.vh deleted file mode 100644 index 381069fc..00000000 --- a/hw/rtl/tex_unit/VX_tex_define.vh +++ /dev/null @@ -1,51 +0,0 @@ -`ifndef VX_TEX_DEFINE -`define VX_TEX_DEFINE - -`include "VX_define.vh" - -`define TEX_FXD_INT (`TEX_FXD_BITS - `TEX_FXD_FRAC) -`define TEX_FXD_ONE (2 ** `TEX_FXD_FRAC) -`define TEX_FXD_HALF (`TEX_FXD_ONE >> 1) -`define TEX_FXD_MASK (`TEX_FXD_ONE - 1) - -`define TEX_ADDR_BITS 32 -`define TEX_FORMAT_BITS 3 -`define TEX_WRAP_BITS 2 -`define TEX_FILTER_BITS 1 -`define TEX_MIPOFF_BITS (2*`TEX_DIM_BITS+1) - -`define TEX_LGSTRIDE_MAX 2 -`define TEX_LGSTRIDE_BITS 2 - -`define TEX_WRAP_CLAMP 0 -`define TEX_WRAP_REPEAT 1 -`define TEX_WRAP_MIRROR 2 - -`define TEX_BLEND_FRAC 8 -`define TEX_BLEND_ONE (2 ** `TEX_BLEND_FRAC) - -`define TEX_FORMAT_A8R8G8B8 `TEX_FORMAT_BITS'(0) -`define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1) -`define TEX_FORMAT_A1R5G5B5 `TEX_FORMAT_BITS'(2) -`define TEX_FORMAT_A4R4G4B4 `TEX_FORMAT_BITS'(3) -`define TEX_FORMAT_A8L8 `TEX_FORMAT_BITS'(4) -`define TEX_FORMAT_L8 `TEX_FORMAT_BITS'(5) -`define TEX_FORMAT_A8 `TEX_FORMAT_BITS'(6) - -task trace_tex_state ( - input [`CSR_ADDR_BITS-1:0] state -); - case (state) - `CSR_TEX_ADDR: dpi_trace("ADDR"); - `CSR_TEX_WIDTH: dpi_trace("WIDTH"); - `CSR_TEX_HEIGHT: dpi_trace("HEIGHT"); - `CSR_TEX_FORMAT: dpi_trace("FORMAT"); - `CSR_TEX_FILTER: dpi_trace("FILTER"); - `CSR_TEX_WRAPU: dpi_trace("WRAPU"); - `CSR_TEX_WRAPV: dpi_trace("WRAPV"); - //`CSR_TEX_MIPOFF - default: dpi_trace("MIPOFF"); - endcase -endtask - -`endif \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_format.sv b/hw/rtl/tex_unit/VX_tex_format.sv deleted file mode 100644 index e299ed17..00000000 --- a/hw/rtl/tex_unit/VX_tex_format.sv +++ /dev/null @@ -1,64 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_format #( - parameter CORE_ID = 0 -) ( - input wire [`TEX_FORMAT_BITS-1:0] format, - input wire [31:0] texel_in, - output wire [31:0] texel_out -); - `UNUSED_PARAM (CORE_ID) - - reg [31:0] texel_out_r; - - always @(*) begin - case (format) - `TEX_FORMAT_A8R8G8B8: begin - texel_out_r[07:00] = texel_in[7:0]; - texel_out_r[15:08] = texel_in[15:8]; - texel_out_r[23:16] = texel_in[23:16]; - texel_out_r[31:24] = texel_in[31:24]; - end - `TEX_FORMAT_R5G6B5: begin - texel_out_r[07:00] = {texel_in[4:0], texel_in[4:2]}; - texel_out_r[15:08] = {texel_in[10:5], texel_in[10:9]}; - texel_out_r[23:16] = {texel_in[15:11], texel_in[15:13]}; - texel_out_r[31:24] = 8'hff; - end - `TEX_FORMAT_A1R5G5B5: begin - texel_out_r[07:00] = {texel_in[4:0], texel_in[4:2]}; - texel_out_r[15:08] = {texel_in[9:5], texel_in[9:7]}; - texel_out_r[23:16] = {texel_in[14:10], texel_in[14:12]}; - texel_out_r[31:24] = {8{texel_in[15]}}; - end - `TEX_FORMAT_A4R4G4B4: begin - texel_out_r[07:00] = {2{texel_in[3:0]}}; - texel_out_r[15:08] = {2{texel_in[7:4]}}; - texel_out_r[23:16] = {2{texel_in[11:8]}}; - texel_out_r[31:24] = {2{texel_in[15:12]}}; - end - `TEX_FORMAT_A8L8: begin - texel_out_r[07:00] = texel_in[7:0]; - texel_out_r[15:08] = texel_in[7:0]; - texel_out_r[23:16] = texel_in[7:0]; - texel_out_r[31:24] = texel_in[15:8]; - end - `TEX_FORMAT_L8: begin - texel_out_r[07:00] = texel_in[7:0]; - texel_out_r[15:08] = texel_in[7:0]; - texel_out_r[23:16] = texel_in[7:0]; - texel_out_r[31:24] = 8'hff; - end - //`TEX_FORMAT_A8 - default: begin - texel_out_r[07:00] = 8'hff; - texel_out_r[15:08] = 8'hff; - texel_out_r[23:16] = 8'hff; - texel_out_r[31:24] = texel_in[7:0]; - end - endcase - end - - assign texel_out = texel_out_r; - -endmodule diff --git a/hw/rtl/tex_unit/VX_tex_lerp.sv b/hw/rtl/tex_unit/VX_tex_lerp.sv deleted file mode 100644 index 7f35ac38..00000000 --- a/hw/rtl/tex_unit/VX_tex_lerp.sv +++ /dev/null @@ -1,15 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_lerp ( - input wire [3:0][7:0] in1, - input wire [3:0][7:0] in2, - input wire [7:0] frac, - output wire [3:0][7:0] out -); - for (genvar i = 0; i < 4; ++i) begin - wire [16:0] sum = in1[i] * 8'(8'hff - frac) + in2[i] * frac; - `UNUSED_VAR (sum) - assign out[i] = sum[15:8]; - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_mem.sv b/hw/rtl/tex_unit/VX_tex_mem.sv deleted file mode 100644 index 73f9367c..00000000 --- a/hw/rtl/tex_unit/VX_tex_mem.sv +++ /dev/null @@ -1,317 +0,0 @@ -`include "VX_tex_define.vh" -module VX_tex_mem #( - parameter CORE_ID = 0, - parameter REQ_INFOW = 1, - parameter NUM_REQS = 1 -) ( - input wire clk, - input wire reset, - - // memory interface - VX_dcache_req_if.master dcache_req_if, - VX_dcache_rsp_if.slave dcache_rsp_if, - - // inputs - input wire req_valid, - input wire [NUM_REQS-1:0] req_tmask, - input wire [`TEX_FILTER_BITS-1:0] req_filter, - input wire [`TEX_LGSTRIDE_BITS-1:0] req_lgstride, - input wire [NUM_REQS-1:0][31:0] req_baseaddr, - input wire [NUM_REQS-1:0][3:0][31:0] req_addr, - input wire [REQ_INFOW-1:0] req_info, - output wire req_ready, - - // outputs - output wire rsp_valid, - output wire [NUM_REQS-1:0] rsp_tmask, - output wire [NUM_REQS-1:0][3:0][31:0] rsp_data, - output wire [REQ_INFOW-1:0] rsp_info, - input wire rsp_ready -); - - `UNUSED_PARAM (CORE_ID) - - localparam RSP_CTR_W = $clog2(NUM_REQS * 4 + 1); - - // full address calculation - wire [NUM_REQS-1:0][3:0][31:0] full_addr; - for (genvar i = 0; i < NUM_REQS; ++i) begin - for (genvar j = 0; j < 4; ++j) begin - assign full_addr[i][j] = req_baseaddr[i] + req_addr[i][j]; - end - end - - wire [3:0] dup_reqs; - wire [3:0][NUM_REQS-1:0][29:0] req_addr_w; - wire [3:0][NUM_REQS-1:0][1:0] align_offs; - - // reorder address into quads - - for (genvar i = 0; i < NUM_REQS; ++i) begin - for (genvar j = 0; j < 4; ++j) begin - assign req_addr_w[j][i] = full_addr[i][j][31:2]; - assign align_offs[j][i] = full_addr[i][j][1:0]; - end - end - - // detect duplicate addresses - - for (genvar i = 0; i < 4; ++i) begin - wire [NUM_REQS-2:0] addr_matches; - for (genvar j = 0; j < (NUM_REQS-1); ++j) begin - assign addr_matches[j] = (req_addr_w[i][j+1] == req_addr_w[i][0]) || ~req_tmask[j+1]; - end - assign dup_reqs[i] = req_tmask[0] && (& addr_matches); - end - - // save request addresses into fifo - - wire reqq_push, reqq_pop, reqq_empty, reqq_full; - - wire [3:0][NUM_REQS-1:0][29:0] q_req_addr; - wire [NUM_REQS-1:0] q_req_tmask; - wire [`TEX_FILTER_BITS-1:0] q_req_filter; - wire [REQ_INFOW-1:0] q_req_info; - wire [`TEX_LGSTRIDE_BITS-1:0] q_req_lgstride; - wire [3:0][NUM_REQS-1:0][1:0] q_align_offs; - wire [3:0] q_dup_reqs; - wire [`NW_BITS-1:0] q_req_wid; - wire [31:0] q_req_PC; - wire [`UUID_BITS-1:0] q_req_uuid; - - assign reqq_push = req_valid && req_ready; - - VX_fifo_queue #( - .DATAW ((NUM_REQS * 4 * 30) + NUM_REQS + REQ_INFOW + `TEX_FILTER_BITS + `TEX_LGSTRIDE_BITS + (4 * NUM_REQS * 2) + 4), - .SIZE (`TEXQ_SIZE), - .OUT_REG (1) - ) req_queue ( - .clk (clk), - .reset (reset), - .push (reqq_push), - .pop (reqq_pop), - .data_in ({req_addr_w, req_tmask, req_info, req_filter, req_lgstride, align_offs, dup_reqs}), - .data_out ({q_req_addr, q_req_tmask, q_req_info, q_req_filter, q_req_lgstride, q_align_offs, q_dup_reqs}), - .empty (reqq_empty), - .full (reqq_full), - `UNUSED_PIN (alm_full), - `UNUSED_PIN (alm_empty), - `UNUSED_PIN (size) - ); - - // can take more requests? - assign req_ready = ~reqq_full; - - /////////////////////////////////////////////////////////////////////////// - - wire req_texel_valid; - wire sent_all_ready, last_texel_sent; - wire req_texel_dup; - wire [NUM_REQS-1:0][29:0] req_texel_addr; - reg [1:0] req_texel_idx; - reg req_texels_done; - - always @(posedge clk) begin - if (reset || last_texel_sent) begin - req_texel_idx <= 0; - end else if (req_texel_valid && sent_all_ready) begin - req_texel_idx <= req_texel_idx + 1; - end - end - - always @(posedge clk) begin - if (reset || reqq_pop) begin - req_texels_done <= 0; - end else if (last_texel_sent) begin - req_texels_done <= 1; - end - end - - assign req_texel_valid = ~reqq_empty && ~req_texels_done; - assign req_texel_addr = q_req_addr[req_texel_idx]; - assign req_texel_dup = q_dup_reqs[req_texel_idx]; - - wire is_last_texel = (req_texel_idx == (q_req_filter ? 3 : 0)); - assign last_texel_sent = req_texel_valid && sent_all_ready && is_last_texel; - - // DCache Request - - reg [NUM_REQS-1:0] texel_sent_mask; - - wire [NUM_REQS-1:0] dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready; - - wire dcache_req_fire_any = (| dcache_req_fire); - - assign sent_all_ready = (&(dcache_req_if.ready | texel_sent_mask | ~q_req_tmask)) - || (req_texel_dup & dcache_req_if.ready[0]); - - always @(posedge clk) begin - if (reset || sent_all_ready) begin - texel_sent_mask <= 0; - end else begin - texel_sent_mask <= texel_sent_mask | dcache_req_fire; - end - end - - wire [NUM_REQS-1:0] req_dup_mask = {{(NUM_REQS-1){~req_texel_dup}}, 1'b1}; - - assign {q_req_wid, q_req_PC, q_req_uuid} = q_req_info[`NW_BITS+32+`UUID_BITS-1:0]; - `UNUSED_VAR (q_req_wid) - `UNUSED_VAR (q_req_PC) - - assign dcache_req_if.valid = {NUM_REQS{req_texel_valid}} & q_req_tmask & req_dup_mask & ~texel_sent_mask; - assign dcache_req_if.rw = {NUM_REQS{1'b0}}; - assign dcache_req_if.addr = req_texel_addr; - assign dcache_req_if.byteen = {NUM_REQS{4'b0}}; - assign dcache_req_if.data = 'x; - assign dcache_req_if.tag = {NUM_REQS{q_req_uuid, `LSU_TAG_ID_BITS'(req_texel_idx), `CACHE_ADDR_TYPE_BITS'(0)}}; - - // Dcache Response - - reg [3:0][NUM_REQS-1:0][31:0] rsp_texels, rsp_texels_n; - wire [NUM_REQS-1:0][3:0][31:0] rsp_texels_qual; - reg [NUM_REQS-1:0][31:0] rsp_data_qual; - reg [RSP_CTR_W-1:0] rsp_rem_ctr, rsp_rem_ctr_init; - wire [RSP_CTR_W-1:0] rsp_rem_ctr_n; - wire [NUM_REQS-1:0][1:0] rsp_align_offs; - wire [$clog2(NUM_REQS+1)-1:0] q_req_size; - wire [$clog2(NUM_REQS+1)-1:0] dcache_rsp_size; - wire dcache_rsp_fire; - wire [1:0] rsp_texel_idx; - wire rsp_texel_dup; - - assign rsp_texel_idx = dcache_rsp_if.tag[`CACHE_ADDR_TYPE_BITS +: 2]; - `UNUSED_VAR (dcache_rsp_if.tag) - - assign rsp_texel_dup = q_dup_reqs[rsp_texel_idx]; - assign rsp_align_offs = q_align_offs[rsp_texel_idx]; - - assign dcache_rsp_fire = dcache_rsp_if.valid && dcache_rsp_if.ready; - - for (genvar i = 0; i < NUM_REQS; i++) begin - wire [31:0] src_mask = {32{dcache_rsp_if.tmask[i]}}; - wire [31:0] src_data = ((i == 0 || rsp_texel_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i]) & src_mask; - - reg [31:0] rsp_data_shifted; - always @(*) begin - rsp_data_shifted[31:16] = src_data[31:16]; - rsp_data_shifted[15:0] = rsp_align_offs[i][1] ? src_data[31:16] : src_data[15:0]; - rsp_data_shifted[7:0] = rsp_align_offs[i][0] ? rsp_data_shifted[15:8] : rsp_data_shifted[7:0]; - end - - always @(*) begin - case (q_req_lgstride) - 0: rsp_data_qual[i] = 32'(rsp_data_shifted[7:0]); - 1: rsp_data_qual[i] = 32'(rsp_data_shifted[15:0]); - default: rsp_data_qual[i] = rsp_data_shifted; - endcase - end - end - - always @(*) begin - rsp_texels_n = rsp_texels; - rsp_texels_n[rsp_texel_idx] |= rsp_data_qual; - end - - always @(posedge clk) begin - if (reset || reqq_pop) begin - rsp_texels <= '0; - end else if (dcache_rsp_fire) begin - rsp_texels <= rsp_texels_n; - end - end - - `POP_COUNT(q_req_size, q_req_tmask); - - always @(*) begin - rsp_rem_ctr_init = q_dup_reqs[0] ? RSP_CTR_W'(1) : RSP_CTR_W'(q_req_size); - if (q_req_filter) begin - for (integer i = 1; i < 4; ++i) begin - rsp_rem_ctr_init += q_dup_reqs[i] ? RSP_CTR_W'(1) : RSP_CTR_W'(q_req_size); - end - end - end - - wire [NUM_REQS-1:0] dcache_rsp_tmask = dcache_rsp_if.tmask; - `POP_COUNT(dcache_rsp_size, dcache_rsp_tmask); - - assign rsp_rem_ctr_n = rsp_rem_ctr - RSP_CTR_W'(dcache_rsp_size); - - always @(posedge clk) begin - if (reset) begin - rsp_rem_ctr <= 0; - end else begin - if (dcache_req_fire_any && 0 == rsp_rem_ctr) begin - rsp_rem_ctr <= rsp_rem_ctr_init; - end else if (dcache_rsp_fire) begin - rsp_rem_ctr <= rsp_rem_ctr_n; - end - end - end - - for (genvar i = 0; i < NUM_REQS; ++i) begin - for (genvar j = 0; j < 4; ++j) begin - assign rsp_texels_qual[i][j] = rsp_texels_n[j][i]; - end - end - - wire stall_out = rsp_valid && ~rsp_ready; - - wire is_last_rsp = (rsp_rem_ctr == RSP_CTR_W'(dcache_rsp_size)); - - wire rsp_texels_done = dcache_rsp_fire && is_last_rsp; - - assign reqq_pop = rsp_texels_done && ~stall_out; - - VX_pipe_register #( - .DATAW (1 + NUM_REQS + REQ_INFOW + (4 * NUM_REQS * 32)), - .RESETW (1) - ) rsp_pipe_reg ( - .clk (clk), - .reset (reset), - .enable (~stall_out), - .data_in ({rsp_texels_done, q_req_tmask, q_req_info, rsp_texels_qual}), - .data_out ({rsp_valid, rsp_tmask, rsp_info, rsp_data}) - ); - - // Can accept new cache response? - assign dcache_rsp_if.ready = ~(is_last_rsp && stall_out); - -`ifdef DBG_TRACE_TEX - wire [`NW_BITS-1:0] req_wid, rsp_wid; - wire [31:0] req_PC, rsp_PC; - wire [`UUID_BITS-1:0] req_uuid, rsp_uuid; - assign {req_wid, req_PC, req_uuid} = req_info[`NW_BITS+32+`UUID_BITS-1:0]; - assign {rsp_wid, rsp_PC, rsp_uuid} = rsp_info[`NW_BITS+32+`UUID_BITS-1:0]; - - always @(posedge clk) begin - if (dcache_req_fire_any) begin - dpi_trace("%d: core%0d-tex-cache-req: wid=%0d, PC=%0h, tmask=%b, tag=%0h, addr=", - $time, CORE_ID, q_req_wid, q_req_PC, dcache_req_fire, req_texel_idx); - `TRACE_ARRAY1D(req_texel_addr, NUM_REQS); - dpi_trace(", is_dup=%b (#%0d)\n", req_texel_dup, q_req_uuid); - end - if (dcache_rsp_fire) begin - dpi_trace("%d: core%0d-tex-cache-rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, data=", - $time, CORE_ID, q_req_wid, q_req_PC, dcache_rsp_if.tmask, rsp_texel_idx); - `TRACE_ARRAY1D(dcache_rsp_if.data, NUM_REQS); - dpi_trace(" (#%0d)\n", q_req_uuid); - end - if (req_valid && req_ready) begin - dpi_trace("%d: core%0d-tex-mem-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, lgstride=%0d, baseaddr=", - $time, CORE_ID, req_wid, req_PC, req_tmask, req_filter, req_lgstride); - `TRACE_ARRAY1D(req_baseaddr, NUM_REQS); - dpi_trace(", addr="); - `TRACE_ARRAY2D(req_addr, 4, NUM_REQS); - dpi_trace(" (#%0d)\n", req_uuid); - end - if (rsp_valid && rsp_ready) begin - dpi_trace("%d: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, data=", - $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask); - `TRACE_ARRAY2D(rsp_data, 4, NUM_REQS); - dpi_trace(" (#%0d)\n", rsp_uuid); - end - end -`endif - -endmodule diff --git a/hw/rtl/tex_unit/VX_tex_sampler.sv b/hw/rtl/tex_unit/VX_tex_sampler.sv deleted file mode 100644 index dffc5cf0..00000000 --- a/hw/rtl/tex_unit/VX_tex_sampler.sv +++ /dev/null @@ -1,149 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_sampler #( - parameter CORE_ID = 0, - parameter REQ_INFOW = 1, - parameter NUM_REQS = 1 -) ( - input wire clk, - input wire reset, - - // inputs - input wire req_valid, - input wire [NUM_REQS-1:0] req_tmask, - input wire [`TEX_FORMAT_BITS-1:0] req_format, - input wire [NUM_REQS-1:0][1:0][`TEX_BLEND_FRAC-1:0] req_blends, - input wire [NUM_REQS-1:0][3:0][31:0] req_data, - input wire [REQ_INFOW-1:0] req_info, - output wire req_ready, - - // ouputs - output wire rsp_valid, - output wire [NUM_REQS-1:0] rsp_tmask, - output wire [NUM_REQS-1:0][31:0] rsp_data, - output wire [REQ_INFOW-1:0] rsp_info, - input wire rsp_ready -); - - `UNUSED_PARAM (CORE_ID) - - wire valid_s0, valid_s1; - wire [NUM_REQS-1:0] req_tmask_s0, req_tmask_s1; - wire [REQ_INFOW-1:0] req_info_s0, req_info_s1; - wire [NUM_REQS-1:0][31:0] texel_ul, texel_uh; - wire [NUM_REQS-1:0][31:0] texel_ul_s1, texel_uh_s1; - wire [NUM_REQS-1:0][1:0][`TEX_BLEND_FRAC-1:0] req_blends_s0; - wire [NUM_REQS-1:0][`TEX_BLEND_FRAC-1:0] blend_v, blend_v_s1; - wire [NUM_REQS-1:0][31:0] texel_v; - wire [NUM_REQS-1:0][3:0][31:0] fmt_texels, fmt_texels_s0; - - wire stall_out; - - for (genvar i = 0; i < NUM_REQS; ++i) begin - for (genvar j = 0; j < 4; ++j) begin - VX_tex_format #( - .CORE_ID (CORE_ID) - ) tex_format ( - .format (req_format), - .texel_in (req_data[i][j]), - .texel_out (fmt_texels[i][j]) - ); - end - end - - VX_pipe_register #( - .DATAW (1 + NUM_REQS + REQ_INFOW + (NUM_REQS * 2 * `TEX_BLEND_FRAC) + (NUM_REQS * 4 * 32)), - .RESETW (1) - ) pipe_reg0 ( - .clk (clk), - .reset (reset), - .enable (~stall_out), - .data_in ({req_valid, req_tmask, req_info, req_blends, fmt_texels}), - .data_out ({valid_s0, req_tmask_s0, req_info_s0, req_blends_s0, fmt_texels_s0}) - ); - - for (genvar i = 0; i < NUM_REQS; ++i) begin - VX_tex_lerp #( - ) tex_lerp_ul ( - .in1 (fmt_texels_s0[i][0]), - .in2 (fmt_texels_s0[i][1]), - .frac (req_blends_s0[i][0]), - .out (texel_ul[i]) - ); - - VX_tex_lerp #( - ) tex_lerp_uh ( - .in1 (fmt_texels_s0[i][2]), - .in2 (fmt_texels_s0[i][3]), - .frac (req_blends_s0[i][0]), - .out (texel_uh[i]) - ); - - assign blend_v[i] = req_blends_s0[i][1]; - end - - VX_pipe_register #( - .DATAW (1 + NUM_REQS + REQ_INFOW + (NUM_REQS * `TEX_BLEND_FRAC) + (2 * NUM_REQS * 32)), - .RESETW (1) - ) pipe_reg1 ( - .clk (clk), - .reset (reset), - .enable (~stall_out), - .data_in ({valid_s0, req_tmask_s0, req_info_s0, blend_v, texel_ul, texel_uh}), - .data_out ({valid_s1, req_tmask_s1, req_info_s1, blend_v_s1, texel_ul_s1, texel_uh_s1}) - ); - - for (genvar i = 0; i < NUM_REQS; i++) begin - VX_tex_lerp #( - ) tex_lerp_v ( - .in1 (texel_ul_s1[i]), - .in2 (texel_uh_s1[i]), - .frac (blend_v_s1[i]), - .out (texel_v[i]) - ); - end - - assign stall_out = rsp_valid && ~rsp_ready; - - VX_pipe_register #( - .DATAW (1 + NUM_REQS + REQ_INFOW + (NUM_REQS * 32)), - .RESETW (1) - ) pipe_reg2 ( - .clk (clk), - .reset (reset), - .enable (~stall_out), - .data_in ({valid_s1, req_tmask_s1, req_info_s1, texel_v}), - .data_out ({rsp_valid, rsp_tmask, rsp_info, rsp_data}) - ); - - // can accept new request? - assign req_ready = ~stall_out; - -`ifdef DBG_TRACE_TEX - wire [`NW_BITS-1:0] req_wid, rsp_wid; - wire [31:0] req_PC, rsp_PC; - - assign {req_wid, req_PC} = req_info[`NW_BITS+32-1:0]; - assign {rsp_wid, rsp_PC} = rsp_info[`NW_BITS+32-1:0]; - - always @(posedge clk) begin - if (req_valid && req_ready) begin - dpi_trace("%d: core%0d-tex-sampler-req: wid=%0d, PC=%0h, tmask=%b, format=%0d, data=", - $time, CORE_ID, req_wid, req_PC, req_tmask, req_format); - `TRACE_ARRAY2D(req_data, 4, NUM_REQS); - dpi_trace(", u0="); - `TRACE_ARRAY1D(req_blends[0], NUM_REQS); - dpi_trace(", v0="); - `TRACE_ARRAY1D(req_blends[1], NUM_REQS); - dpi_trace("\n"); - end - if (rsp_valid && rsp_ready) begin - dpi_trace("%d: core%0d-tex-sampler-rsp: wid=%0d, PC=%0h, tmask=%b, data=", - $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask); - `TRACE_ARRAY1D(rsp_data, NUM_REQS); - dpi_trace("\n"); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_sat.sv b/hw/rtl/tex_unit/VX_tex_sat.sv deleted file mode 100644 index f8e20d08..00000000 --- a/hw/rtl/tex_unit/VX_tex_sat.sv +++ /dev/null @@ -1,21 +0,0 @@ -`include "VX_platform.vh" - -module VX_tex_sat #( - parameter IN_W = 1, - parameter OUT_W = 1, - parameter MODEL = 1 -) ( - input wire [IN_W-1:0] data_in, - output wire [OUT_W-1:0] data_out -); - `STATIC_ASSERT(((OUT_W+1) < IN_W), ("invalid parameter")) - - if (MODEL == 1) begin - wire [OUT_W-1:0] underflow_mask = {OUT_W{~data_in[IN_W-1]}}; - wire [OUT_W-1:0] overflow_mask = {OUT_W{(| data_in[IN_W-2:OUT_W])}}; - assign data_out = (data_in[OUT_W-1:0] | overflow_mask) & underflow_mask; - end else begin - assign data_out = data_in[IN_W-1] ? OUT_W'(0) : ((data_in > {OUT_W{1'b1}}) ? {OUT_W{1'b1}} : OUT_W'(data_in)); - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_stride.sv b/hw/rtl/tex_unit/VX_tex_stride.sv deleted file mode 100644 index 3f1427bb..00000000 --- a/hw/rtl/tex_unit/VX_tex_stride.sv +++ /dev/null @@ -1,28 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_stride #( - parameter CORE_ID = 0 -) ( - input wire [`TEX_FORMAT_BITS-1:0] format, - output wire [`TEX_LGSTRIDE_BITS-1:0] log_stride -); - `UNUSED_PARAM (CORE_ID) - - reg [`TEX_LGSTRIDE_BITS-1:0] log_stride_r; - - always @(*) begin - case (format) - `TEX_FORMAT_A8R8G8B8: log_stride_r = 2; - `TEX_FORMAT_R5G6B5, - `TEX_FORMAT_A1R5G5B5, - `TEX_FORMAT_A4R4G4B4, - `TEX_FORMAT_A8L8: log_stride_r = 1; - // `TEX_FORMAT_L8: - // `TEX_FORMAT_A8: - default: log_stride_r = 0; - endcase - end - - assign log_stride = log_stride_r; - -endmodule diff --git a/hw/rtl/tex_unit/VX_tex_unit.sv b/hw/rtl/tex_unit/VX_tex_unit.sv deleted file mode 100644 index 9045c5aa..00000000 --- a/hw/rtl/tex_unit/VX_tex_unit.sv +++ /dev/null @@ -1,266 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_unit #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - - // PERF -`ifdef PERF_ENABLE - VX_perf_tex_if.master perf_tex_if, -`endif - - // Texture unit <-> Memory Unit - VX_dcache_req_if.master dcache_req_if, - VX_dcache_rsp_if.slave dcache_rsp_if, - - // Inputs - VX_tex_req_if.slave tex_req_if, - VX_tex_csr_if.slave tex_csr_if, - - // Outputs - VX_tex_rsp_if.master tex_rsp_if -); - - localparam REQ_INFO_W = `NR_BITS + 1 + `NW_BITS + 32 + `UUID_BITS; - localparam BLEND_FRAC_W = (2 * `NUM_THREADS * `TEX_BLEND_FRAC); - - reg [$clog2(`NUM_TEX_UNITS)-1:0] csr_tex_unit; - reg [`TEX_MIPOFF_BITS-1:0] tex_mipoff [`NUM_TEX_UNITS-1:0][(`TEX_LOD_MAX+1)-1:0]; - reg [1:0][`TEX_LOD_BITS-1:0] tex_logdims [`NUM_TEX_UNITS-1:0]; - reg [1:0][`TEX_WRAP_BITS-1:0] tex_wraps [`NUM_TEX_UNITS-1:0]; - reg [`TEX_ADDR_BITS-1:0] tex_baddr [`NUM_TEX_UNITS-1:0]; - reg [`TEX_FORMAT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1:0]; - reg [`TEX_FILTER_BITS-1:0] tex_filter [`NUM_TEX_UNITS-1:0]; - - // CSRs programming - - always @(posedge clk) begin - if (tex_csr_if.write_enable) begin - case (tex_csr_if.write_addr) - `CSR_TEX_UNIT: begin - csr_tex_unit <= tex_csr_if.write_data[$clog2(`NUM_TEX_UNITS)-1:0]; - end - `CSR_TEX_ADDR: begin - tex_baddr[csr_tex_unit] <= tex_csr_if.write_data[`TEX_ADDR_BITS-1:0]; - end - `CSR_TEX_FORMAT: begin - tex_format[csr_tex_unit] <= tex_csr_if.write_data[`TEX_FORMAT_BITS-1:0]; - end - `CSR_TEX_WRAPU: begin - tex_wraps[csr_tex_unit][0] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0]; - end - `CSR_TEX_WRAPV: begin - tex_wraps[csr_tex_unit][1] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0]; - end - `CSR_TEX_FILTER: begin - tex_filter[csr_tex_unit] <= tex_csr_if.write_data[`TEX_FILTER_BITS-1:0]; - end - `CSR_TEX_WIDTH: begin - tex_logdims[csr_tex_unit][0] <= tex_csr_if.write_data[`TEX_LOD_BITS-1:0]; - end - `CSR_TEX_HEIGHT: begin - tex_logdims[csr_tex_unit][1] <= tex_csr_if.write_data[`TEX_LOD_BITS-1:0]; - end - default: begin - for (integer j = 0; j <= `TEX_LOD_MAX; ++j) begin - `IGNORE_WARNINGS_BEGIN - if (tex_csr_if.write_addr == `CSR_TEX_MIPOFF(j)) begin - `IGNORE_WARNINGS_END - tex_mipoff[csr_tex_unit][j] <= tex_csr_if.write_data[`TEX_MIPOFF_BITS-1:0]; - end - end - end - endcase - end - end - wire [`UUID_BITS-1:0] write_uuid = tex_csr_if.write_uuid; - `UNUSED_VAR (write_uuid); - - // mipmap attributes - - wire [`NUM_THREADS-1:0][`TEX_LOD_BITS-1:0] mip_level; - wire [`NUM_THREADS-1:0][`TEX_MIPOFF_BITS-1:0] sel_mipoff; - wire [`NUM_THREADS-1:0][1:0][`TEX_LOD_BITS-1:0] sel_logdims; - - for (genvar i = 0; i < `NUM_THREADS; ++i) begin - wire [`NTEX_BITS-1:0] unit = tex_req_if.unit[`NTEX_BITS-1:0]; - assign mip_level[i] = tex_req_if.lod[i][`TEX_LOD_BITS-1:0]; - assign sel_mipoff[i] = tex_mipoff[unit][mip_level[i]]; - assign sel_logdims[i][0] = tex_logdims[unit][0]; - assign sel_logdims[i][1] = tex_logdims[unit][1]; - end - - // address generation - - wire mem_req_valid; - wire [`NUM_THREADS-1:0] mem_req_tmask; - wire [`TEX_FILTER_BITS-1:0] mem_req_filter; - wire [`TEX_LGSTRIDE_BITS-1:0] mem_req_lgstride; - wire [`NUM_THREADS-1:0][1:0][`TEX_BLEND_FRAC-1:0] mem_req_blends; - wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr; - wire [`NUM_THREADS-1:0][31:0] mem_req_baseaddr; - wire [(`TEX_FORMAT_BITS + REQ_INFO_W)-1:0] mem_req_info; - wire mem_req_ready; - - VX_tex_addr #( - .CORE_ID (CORE_ID), - .REQ_INFOW (`TEX_FORMAT_BITS + REQ_INFO_W), - .NUM_REQS (`NUM_THREADS) - ) tex_addr ( - .clk (clk), - .reset (reset), - - .req_valid (tex_req_if.valid), - .req_tmask (tex_req_if.tmask), - .req_coords (tex_req_if.coords), - .req_format (tex_format[tex_req_if.unit]), - .req_filter (tex_filter[tex_req_if.unit]), - .req_wraps (tex_wraps[tex_req_if.unit]), - .req_baseaddr(tex_baddr[tex_req_if.unit]), - .mip_level (mip_level), - .req_mipoff (sel_mipoff), - .req_logdims(sel_logdims), - .req_info ({tex_format[tex_req_if.unit], tex_req_if.rd, tex_req_if.wb, tex_req_if.wid, tex_req_if.PC, tex_req_if.uuid}), - .req_ready (tex_req_if.ready), - - .rsp_valid (mem_req_valid), - .rsp_tmask (mem_req_tmask), - .rsp_filter (mem_req_filter), - .rsp_lgstride(mem_req_lgstride), - .rsp_baseaddr(mem_req_baseaddr), - .rsp_addr (mem_req_addr), - .rsp_blends (mem_req_blends), - .rsp_info (mem_req_info), - .rsp_ready (mem_req_ready) - ); - - // retrieve texel values from memory - - wire mem_rsp_valid; - wire [`NUM_THREADS-1:0] mem_rsp_tmask; - wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data; - wire [(BLEND_FRAC_W + `TEX_FORMAT_BITS + REQ_INFO_W)-1:0] mem_rsp_info; - wire mem_rsp_ready; - - VX_tex_mem #( - .CORE_ID (CORE_ID), - .REQ_INFOW (BLEND_FRAC_W + `TEX_FORMAT_BITS + REQ_INFO_W), - .NUM_REQS (`NUM_THREADS) - ) tex_mem ( - .clk (clk), - .reset (reset), - - // memory interface - .dcache_req_if (dcache_req_if), - .dcache_rsp_if (dcache_rsp_if), - - // inputs - .req_valid (mem_req_valid), - .req_tmask (mem_req_tmask), - .req_filter(mem_req_filter), - .req_lgstride(mem_req_lgstride), - .req_baseaddr(mem_req_baseaddr), - .req_addr (mem_req_addr), - .req_info ({mem_req_blends, mem_req_info}), - .req_ready (mem_req_ready), - - // outputs - .rsp_valid (mem_rsp_valid), - .rsp_tmask (mem_rsp_tmask), - .rsp_data (mem_rsp_data), - .rsp_info (mem_rsp_info), - .rsp_ready (mem_rsp_ready) - ); - - // apply sampler - - VX_tex_sampler #( - .CORE_ID (CORE_ID), - .REQ_INFOW (REQ_INFO_W), - .NUM_REQS (`NUM_THREADS) - ) tex_sampler ( - .clk (clk), - .reset (reset), - - // inputs - .req_valid (mem_rsp_valid), - .req_tmask (mem_rsp_tmask), - .req_data (mem_rsp_data), - .req_blends (mem_rsp_info[(REQ_INFO_W+`TEX_FORMAT_BITS) +: BLEND_FRAC_W]), - .req_format (mem_rsp_info[REQ_INFO_W +: `TEX_FORMAT_BITS]), - .req_info (mem_rsp_info[0 +: REQ_INFO_W]), - .req_ready (mem_rsp_ready), - - // outputs - .rsp_valid (tex_rsp_if.valid), - .rsp_tmask (tex_rsp_if.tmask), - .rsp_data (tex_rsp_if.data), - .rsp_info ({tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.wid, tex_rsp_if.PC, tex_rsp_if.uuid}), - .rsp_ready (tex_rsp_if.ready) - ); - -`ifdef PERF_ENABLE - wire [$clog2(`NUM_THREADS+1)-1:0] perf_mem_req_per_cycle; - wire [$clog2(`NUM_THREADS+1)-1:0] perf_mem_rsp_per_cycle; - - wire [`NUM_THREADS-1:0] perf_mem_req_per_mask = dcache_req_if.valid & dcache_req_if.ready; - wire [`NUM_THREADS-1:0] perf_mem_rsp_per_mask = dcache_rsp_if.tmask & {`NUM_THREADS{dcache_rsp_if.valid & dcache_rsp_if.ready}}; - - `POP_COUNT(perf_mem_req_per_cycle, perf_mem_req_per_mask); - `POP_COUNT(perf_mem_rsp_per_cycle, perf_mem_rsp_per_mask); - - reg [`PERF_CTR_BITS-1:0] perf_pending_reads; - wire [$clog2(`NUM_THREADS+1)+1-1:0] perf_pending_reads_cycle = perf_mem_req_per_cycle - perf_mem_rsp_per_cycle; - - always @(posedge clk) begin - if (reset) begin - perf_pending_reads <= 0; - end else begin - perf_pending_reads <= perf_pending_reads + `PERF_CTR_BITS'($signed(perf_pending_reads_cycle)); - end - end - - reg [`PERF_CTR_BITS-1:0] perf_mem_reads; - reg [`PERF_CTR_BITS-1:0] perf_mem_latency; - - always @(posedge clk) begin - if (reset) begin - perf_mem_reads <= 0; - perf_mem_latency <= 0; - end else begin - perf_mem_reads <= perf_mem_reads + `PERF_CTR_BITS'(perf_mem_req_per_cycle); - perf_mem_latency <= perf_mem_latency + `PERF_CTR_BITS'(perf_pending_reads); - end - end - - assign perf_tex_if.mem_reads = perf_mem_reads; - assign perf_tex_if.mem_latency = perf_mem_latency; -`endif - -`ifdef DBG_TRACE_TEX - always @(posedge clk) begin - if (tex_csr_if.write_enable) begin - dpi_trace("%d: core%0d-tex-csr: unit=%0d, state=", $time, CORE_ID, csr_tex_unit); - trace_tex_state(tex_csr_if.write_addr); - dpi_trace(", data=%0h (#%0d)\n", tex_csr_if.write_data, tex_csr_if.write_uuid); - end - if (tex_req_if.valid && tex_req_if.ready) begin - dpi_trace("%d: core%0d-tex-req: wid=%0d, PC=%0h, tmask=%b, unit=%0d, lod=%0h, u=", - $time, CORE_ID, tex_req_if.wid, tex_req_if.PC, tex_req_if.tmask, tex_req_if.unit, tex_req_if.lod); - `TRACE_ARRAY1D(tex_req_if.coords[0], `NUM_THREADS); - dpi_trace(", v="); - `TRACE_ARRAY1D(tex_req_if.coords[1], `NUM_THREADS); - dpi_trace(" (#%0d)\n", tex_req_if.uuid); - end - if (tex_rsp_if.valid && tex_rsp_if.ready) begin - dpi_trace("%d: core%0d-tex-rsp: wid=%0d, PC=%0h, tmask=%b, data=", - $time, CORE_ID, tex_rsp_if.wid, tex_rsp_if.PC, tex_rsp_if.tmask); - `TRACE_ARRAY1D(tex_rsp_if.data, `NUM_THREADS); - dpi_trace(" (#%0d)\n", tex_rsp_if.uuid); - end - end -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_wrap.sv b/hw/rtl/tex_unit/VX_tex_wrap.sv deleted file mode 100644 index fe2110ba..00000000 --- a/hw/rtl/tex_unit/VX_tex_wrap.sv +++ /dev/null @@ -1,38 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_wrap #( - parameter CORE_ID = 0 -) ( - input wire [`TEX_WRAP_BITS-1:0] wrap_i, - input wire [`TEX_FXD_BITS-1:0] coord_i, - output wire [`TEX_FXD_FRAC-1:0] coord_o -); - - `UNUSED_PARAM (CORE_ID) - - reg [`TEX_FXD_FRAC-1:0] coord_r; - - wire [`TEX_FXD_FRAC-1:0] clamp; - - VX_tex_sat #( - .IN_W (`TEX_FXD_BITS), - .OUT_W (`TEX_FXD_FRAC) - ) sat_fx ( - .data_in (coord_i), - .data_out (clamp) - ); - - always @(*) begin - case (wrap_i) - `TEX_WRAP_CLAMP: - coord_r = clamp; - `TEX_WRAP_MIRROR: - coord_r = coord_i[`TEX_FXD_FRAC-1:0] ^ {`TEX_FXD_FRAC{coord_i[`TEX_FXD_FRAC]}}; - default: //`TEX_WRAP_REPEAT - coord_r = coord_i[`TEX_FXD_FRAC-1:0]; - endcase - end - - assign coord_o = coord_r; - -endmodule \ No newline at end of file diff --git a/hw/scripts/gen_config.py b/hw/scripts/gen_config.py index 6753f86e..ef94c710 100755 --- a/hw/scripts/gen_config.py +++ b/hw/scripts/gen_config.py @@ -1,5 +1,18 @@ #!/usr/bin/env python3 -# coding=utf-8 + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + from __future__ import print_function import sys @@ -25,8 +38,7 @@ translation_rules = [ # preprocessor directives (re.compile(r'`include\s+.*$'), r''), (re.compile(r'`ifdef'), r'#ifdef'), - (re.compile(r'`ifndef'), r'#ifndef'), - (re.compile(r'`elif'), r'#elif'), + (re.compile(r'`ifndef'), r'#ifndef'), (re.compile(r'`else'), r'#else'), (re.compile(r'`define'), r'#define'), (re.compile(r'`endif'), r'#endif'), @@ -37,7 +49,8 @@ translation_rules = [ # literals (re.compile(r"\d+'d(\d+)"), r'\1'), (re.compile(r"\d+'b([01]+)"), r'0b\1'), - (re.compile(r"\d+'h([\da-fA-F]+)"), r'0x\1') + (re.compile(r"128'h([\da-fA-F_]+)"), r'"\1"'), + (re.compile(r"\d+'h([\da-fA-F]+)"), r'0x\1') ] with open(args.output, 'w') as f: @@ -45,8 +58,8 @@ with open(args.output, 'w') as f: // auto-generated by gen_config.py. DO NOT EDIT // Generated at {date} -// Translated from VX_config.vh: -'''[1:].format(date=datetime.now()), file=f) +// Translated from {input}: +'''[1:].format(date=datetime.now(), input=args.input), file=f) with open(args.input, 'r') as r: lineno = 0 for line in r: diff --git a/hw/scripts/gen_sources.sh b/hw/scripts/gen_sources.sh new file mode 100755 index 00000000..cfe7780c --- /dev/null +++ b/hw/scripts/gen_sources.sh @@ -0,0 +1,129 @@ +#!/bin/bash + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +defines=() +includes=() +externs=() + +output_file="" +global_file="" +copy_folder="" +prepropressor=0 + +defines_str="" +includes_str="" + +# parse command arguments +while getopts D:I:J:O:G:C:Ph flag +do + case "${flag}" in + D) defines+=( ${OPTARG} ) + defines_str+="-D${OPTARG} " + ;; + I) includes+=( ${OPTARG} ) + includes_str+="-I${OPTARG} " + ;; + J) externs+=( ${OPTARG} ) + includes_str+="-I${OPTARG} " + ;; + O) output_file=( ${OPTARG} );; + G) global_file=( ${OPTARG} );; + C) copy_folder=( ${OPTARG} );; + P) prepropressor=1;; + h) echo "Usage: [-D] [-I] [-J] [-O] [-C: copy to] [-G] [-P: macro prepropressing] [-h help]" + exit 0 + ;; + \?) + echo "Invalid option: -$OPTARG" 1>&2 + exit 1 + ;; + esac +done + +if [ "$global_file" != "" ]; then + directory=$(dirname "$global_file") + mkdir -p "$directory" + { + # dump defines into a global header + for value in ${defines[@]}; do + arrNV=(${value//=/ }) + if (( ${#arrNV[@]} > 1 )); + then + echo "\`define ${arrNV[0]} ${arrNV[1]}" + else + echo "\`define $value" + fi + done + } > $global_file +fi + +if [ "$copy_folder" != "" ]; then + # copy source files + mkdir -p $copy_folder + for dir in ${includes[@]}; do + find "$dir" -maxdepth 1 -type f | while read -r file; do + ext="${file##*.}" + if [ $prepropressor != 0 ] && { [ "$ext" == "v" ] || [ "$ext" == "sv" ]; }; then + verilator $defines_str $includes_str -E -P $file > $copy_folder/$(basename -- $file) + else + cp $file $copy_folder + fi + done + done +fi + +if [ "$output_file" != "" ]; then + { + if [ "$global_file" == "" ]; then + # dump defines + for value in ${defines[@]}; do + echo "+define+$value" + done + fi + + for dir in ${externs[@]}; do + echo "+incdir+$(realpath $dir)" + done + + for dir in ${externs[@]}; do + find "$(realpath $dir)" -maxdepth 1 -type f -name "*_pkg.sv" -print + done + for dir in ${externs[@]}; do + find "$(realpath $dir)" -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" \) ! -name "*_pkg.sv" -print + done + + if [ "$copy_folder" != "" ]; then + # dump include directories + echo "+incdir+$(realpath $copy_folder)" + + # dump source files + find "$(realpath $copy_folder)" -maxdepth 1 -type f -name "*_pkg.sv" -print + find "$(realpath $copy_folder)" -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" \) ! -name "*_pkg.sv" -print + else + # dump include directories + for dir in ${includes[@]}; do + echo "+incdir+$(realpath $dir)" + done + + # dump source files + for dir in ${includes[@]}; do + find "$(realpath $dir)" -maxdepth 1 -type f -name "*_pkg.sv" -print + done + for dir in ${includes[@]}; do + find "$(realpath $dir)" -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" \) ! -name "*_pkg.sv" -print + done + fi + } > $output_file +fi diff --git a/hw/scripts/parse_vcs_list.tcl b/hw/scripts/parse_vcs_list.tcl new file mode 100644 index 00000000..ba11851e --- /dev/null +++ b/hw/scripts/parse_vcs_list.tcl @@ -0,0 +1,46 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +proc parse_vcs_list {flist_path} { + set f [split [string trim [read [open $flist_path r]]] "\n"] + set flist [list ] + set dir_list [list ] + set def_list [list ] + foreach x $f { + if {![string match "" $x]} { + # If the item starts with +incdir+, directory files need to be added + if {[string match "#*" $x]} { + # get rid of comment line + } elseif {[string match "+incdir+*" $x]} { + set trimchars "+incdir+" + set temp [string trimleft $x $trimchars] + set expanded [subst $temp] + lappend dir_list $expanded + } elseif {[string match "+define+*" $x]} { + set trimchars "+define+" + set temp [string trimleft $x $trimchars] + set expanded [subst $temp] + lappend def_list $expanded + } else { + set expanded [subst $x] + lappend flist $expanded + } + } + } + + #puts $flist + #puts $dir_list + #puts $def_list + + return [list $flist $dir_list $def_list] +} diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json deleted file mode 100644 index d6cfd609..00000000 --- a/hw/scripts/scope.json +++ /dev/null @@ -1,224 +0,0 @@ -{ - "version": 1, - "include_paths":[ - "../dpi", - "../rtl", - "../rtl/afu", - "../rtl/cache", - "../rtl/fp_cores", - "../rtl/interfaces", - "../rtl/libs" - ], - "includes":[ - "../rtl/VX_config.vh", - "../rtl/VX_platform.vh", - "../rtl/VX_define.vh", - "../rtl/VX_gpu_types.vh", - "../rtl/fp_cores/VX_fpu_types.vh", - "../rtl/fp_cores/VX_fpu_define.vh", - "../rtl/cache/VX_cache_define.vh" - ], - "modules": { - "afu": { - "submodules": { - "vortex": {"type":"Vortex", "enabled":true} - } - }, - "Vortex": { - "submodules": { - "cluster": {"type":"VX_cluster", "count":"`NUM_CLUSTERS"}, - "l3cache": {"type":"VX_cache", "enabled":"`L3_ENABLE", "params":{"NUM_BANKS":"`L3NUM_BANKS"}} - } - }, - "VX_cluster": { - "submodules": { - "core": {"type":"VX_core", "count":"`NUM_CORES", "enabled":true}, - "l2cache": {"type":"VX_cache", "enabled":"`L2_ENABLE", "params":{"NUM_BANKS":"`L2NUM_BANKS"}} - } - }, - "VX_core": { - "submodules": { - "pipeline": {"type":"VX_pipeline", "enabled":true}, - "mem_unit": {"type":"VX_mem_unit", "enabled":true} - } - }, - "VX_pipeline": { - "submodules": { - "fetch": {"type":"VX_fetch", "enabled":true}, - "decode": {"type":"VX_decode", "enabled":true}, - "issue": {"type":"VX_issue", "enabled":true}, - "execute": {"type":"VX_execute", "enabled":true}, - "commit": {"type":"VX_commit", "enabled":true} - } - }, - "VX_fetch": { - "submodules": { - "warp_sched": {"type":"VX_warp_sched"}, - "icache_stage": {"type":"VX_icache_stage"} - } - }, - "VX_warp_sched": {}, - "VX_icache_stage": {}, - "VX_decode": {}, - "VX_issue": {}, - "VX_execute": { - "submodules": { - "lsu_unit": {"type":"VX_lsu_unit"}, - "gpu_unit": {"type":"VX_gpu_unit"} - } - }, - "VX_commit": {}, - "VX_lsu_unit": {}, - "VX_gpu_unit": {}, - "VX_mem_unit": { - "submodules": { - "dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DCACHE_NUM_BANKS"}}, - "icache": {"type":"VX_cache", "params":{"NUM_BANKS":"1"}} - } - }, - "VX_cache": { - "submodules": { - "bank": {"type":"VX_bank", "count":"NUM_BANKS"} - } - }, - "VX_bank": {} - }, - "taps": { - "afu": { - "!cmd_type":3, - "!state":2, - "?cci_sRxPort_c0_mmioRdValid":1, - "?cci_sRxPort_c0_mmioWrValid":1, - "mmio_hdr_address":16, - "mmio_hdr_length":2, - "cci_sRxPort_c0_hdr_mdata":16, - "?cci_sRxPort_c0_rspValid":1, - "?cci_sRxPort_c1_rspValid":1, - "?cci_sTxPort_c0_valid":1, - "cci_sTxPort_c0_hdr_address":42, - "cci_sTxPort_c0_hdr_mdata":16, - "?cci_sTxPort_c1_valid":1, - "cci_sTxPort_c1_hdr_address":42, - "cci_sTxPort_c2_mmioRdValid":1, - "!cci_sRxPort_c0TxAlmFull":1, - "!cci_sRxPort_c1TxAlmFull":1, - "avs_address":26, - "!avs_waitrequest":1, - "?avs_write_fire":1, - "?avs_read_fire":1, - "avs_byteenable":64, - "avs_burstcount":4, - "avs_readdatavalid":1, - "cci_mem_rd_req_ctr":26, - "cci_mem_wr_req_ctr":26, - "cci_rd_req_ctr":26, - "cci_rd_rsp_ctr":3, - "cci_wr_req_ctr":26, - "?cci_wr_req_fire":1, - "?cci_wr_rsp_fire":1, - "?cci_rd_req_fire":1, - "?cci_rd_rsp_fire":1, - "!cci_pending_reads_full":1, - "!cci_pending_writes_empty":1, - "!cci_pending_writes_full": 1, - "?afu_mem_req_fire": 1, - "afu_mem_req_addr": 26, - "afu_mem_req_tag": "`VX_MEM_TAG_WIDTH+1", - "?afu_mem_rsp_fire": 1, - "afu_mem_rsp_tag": "`VX_MEM_TAG_WIDTH+1" - }, - "afu/vortex": { - "!reset": 1, - "?mem_req_fire": 1, - "mem_req_addr": 32, - "mem_req_rw": 1, - "mem_req_byteen":"`VX_MEM_BYTEEN_WIDTH", - "mem_req_data":"`VX_MEM_DATA_WIDTH", - "mem_req_tag":"`VX_MEM_TAG_WIDTH", - "?mem_rsp_fire": 1, - "mem_rsp_data":"`VX_MEM_DATA_WIDTH", - "mem_rsp_tag":"`VX_MEM_TAG_WIDTH", - "busy": 1 - }, - "afu/vortex/cluster/core/pipeline/fetch/warp_sched": { - "?wsched_scheduled": 1, - "wsched_schedule_uuid": "`UUID_BITS", - "wsched_active_warps": "`NUM_WARPS", - "wsched_stalled_warps": "`NUM_WARPS", - "wsched_schedule_tmask": "`NUM_THREADS", - "wsched_schedule_wid": "`NW_BITS", - "wsched_schedule_pc": 32 - }, - "afu/vortex/cluster/core/pipeline/fetch/icache_stage": { - "?icache_req_fire": 1, - "icache_req_uuid": "`UUID_BITS", - "icache_req_addr": 32, - "icache_req_tag":"`ICACHE_CORE_TAG_ID_BITS", - "?icache_rsp_fire": 1, - "icache_rsp_uuid": "`UUID_BITS", - "icache_rsp_data": 32, - "icache_rsp_tag":"`ICACHE_CORE_TAG_ID_BITS" - }, - "afu/vortex/cluster/core/pipeline/issue": { - "?issue_fire": 1, - "issue_uuid": "`UUID_BITS", - "issue_tmask":"`NUM_THREADS", - "issue_ex_type":"`EX_BITS", - "issue_op_type":"`INST_OP_BITS", - "issue_op_mod":"`INST_MOD_BITS", - "issue_wb": 1, - "issue_rd":"`NR_BITS", - "issue_rs1":"`NR_BITS", - "issue_rs2":"`NR_BITS", - "issue_rs3":"`NR_BITS", - "issue_imm": 32, - "issue_use_pc": 1, - "issue_use_imm": 1, - "gpr_rs1":"`NUM_THREADS * 32", - "gpr_rs2":"`NUM_THREADS * 32", - "gpr_rs3":"`NUM_THREADS * 32", - "?writeback_valid": 1, - "writeback_uuid": "`UUID_BITS", - "writeback_tmask":"`NUM_THREADS", - "writeback_rd":"`NR_BITS", - "writeback_data":"`NUM_THREADS * 32", - "writeback_eop": 1, - "!scoreboard_delay": 1, - "!dispatch_delay": 1 - }, - "afu/vortex/cluster/core/pipeline/execute/lsu_unit": { - "?dcache_req_fire":"`NUM_THREADS", - "dcache_req_uuid": "`UUID_BITS", - "dcache_req_addr":"`NUM_THREADS * 32", - "dcache_req_rw": 1, - "dcache_req_byteen":"`NUM_THREADS * 4", - "dcache_req_data":"`NUM_THREADS * 32", - "dcache_req_tag":"`LSUQ_ADDR_BITS", - "?dcache_rsp_fire":"`NUM_THREADS", - "dcache_rsp_uuid": "`UUID_BITS", - "dcache_rsp_data":"`NUM_THREADS * 32", - "dcache_rsp_tag":"`LSUQ_ADDR_BITS" - }, - "afu/vortex/cluster/core/pipeline/execute/gpu_unit": { - "?gpu_rsp_valid": 1, - "gpu_rsp_uuid": "`UUID_BITS", - "gpu_rsp_tmc": 1, - "gpu_rsp_wspawn": 1, - "gpu_rsp_split": 1, - "gpu_rsp_barrier": 1 - }, - "afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank": { - "?valid_st0": 1, - "?valid_st1": 1, - "addr_st0": 32, - "addr_st1": 32, - "is_fill_st0": 1, - "is_mshr_st0": 1, - "miss_st0": 1, - "?crsq_stall": 1, - "?mreq_alm_full": 1, - "?mshr_alm_full": 1 - } - } - } - \ No newline at end of file diff --git a/hw/scripts/scope.py b/hw/scripts/scope.py index 679209a9..5361e8af 100755 --- a/hw/scripts/scope.py +++ b/hw/scripts/scope.py @@ -1,829 +1,177 @@ #!/usr/bin/env python3 -import os + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import sys +import argparse +import xml.etree.ElementTree as ET import re import json -import argparse -import math -vl_include_re = re.compile(r"^\s*`include\s+\"(.+)\"") -vl_define_re = re.compile(r"^\s*`define\s+(\w+)(\([\w\s,]*\))?(.*)") -vl_ifdef_re = re.compile(r"^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$") -vl_endif_re = re.compile(r"^\s*`(endif|else)\s*$") -vl_expand_re = re.compile(r"`([0-9a-zA-Z_]+)") +vl_int_re = re.compile(r"\d+'s*h([\da-fA-F]+)") -exclude_files = [] -include_dirs = [] -macros = [] -br_stack = [] +def parse_vl_int(text): + str_hex = re.sub(vl_int_re, r'\1', text) + return int(str_hex, 16) -def translate_ternary(text): +def source_loc(xml_doc, xml_loc): + loc = xml_loc.split(",") + file_id = loc[0] + start_line = loc[1] + start_col = loc[2] + end_line = loc[3] + end_col = loc[4] + file = xml_doc.find(".//file/[@id='" + file_id + "']").get("filename") + return file + " (" + start_line + ":" + start_col + "-" + end_line + ":" + end_col + ")" - def skip_space(text, i, ln, step): - while (i >= 0) and (i < ln): - c = text[i] - if not c.isspace(): - break - i += step - return i - - def skip_expr(text, i, ln, step): - paren = 0 - checkparen = True - while (i >= 0) and (i < ln): - c = text[i] - if checkparen and (((step < 0) and (c == ')')) or ((step > 0) and (c == '('))): - paren += 1 - elif checkparen and (((step < 0) and (c == '(')) or ((step > 0) and (c == ')'))): - if (0 == paren): - break - paren -= 1 - if (0 == paren): - i = skip_space(text, i + step, ln, step) - checkparen = False - continue - elif (0 == paren) and not (c.isalnum() or (c == '_')): - break - i += step - return (i - step) - - def parse_ternary(text): - ternary = None - ln = len(text) - for i in range(1, ln): - c = text[i] - if not (c == '?'): - continue - # parse condition expression - i0 = skip_space(text, i - 1, ln, -1) - if (i < 0): - raise Exception("invalid condition expression") - i1 = skip_expr(text, i0, ln, -1) - if (i1 > i0): - raise Exception("invalid condition expression") - # parse true expression - i2 = skip_space(text, i + 1, ln, 1) - if (i2 >= ln): - raise Exception("invalid true expression") - i3 = skip_expr(text, i2, ln, 1) - if (i3 < i2): - raise Exception("invalid true expression") - # parse colon - i4 = skip_space(text, i3 + 1, ln, 1) - if (i4 >= ln): - raise Exception("invalid colon") - if not (text[i4] == ':'): - raise Exception("missing colon") - # parse false expression - i5 = skip_space(text, i4 + 1, ln, 1) - if (i5 >= ln): - raise Exception("invalid false expression") - i6 = skip_expr(text, i5, ln, 1) - if (i6 < i5): - raise Exception("invalid false expression") - ternary = (i0, i1, i2, i3, i5, i6) - break - return ternary - - while True: - pos = parse_ternary(text) - if pos is None: - break - # convert to python ternary - newText = text[:pos[1]] + text[pos[2]:pos[3]+1] + " if " + text[pos[1]:pos[0]+1] + " else " + text[pos[4]:pos[5]+1] + text[pos[5]+1:] - text = newText - - return text - -def parse_func_args(text): - args = [] - arg = '' - l = len(text) - if text[0] != '(': - raise Exception("missing leading parenthesis: " + text) - paren = 1 - for i in range(1, l): - c = text[i] - if c == '(': - paren += 1 - elif c == ')': - if paren == 0: - raise Exception("mismatched parenthesis: (" + i + ") " + text) - paren -= 1 - if paren == 0: - l = i - break - if c == ',' and paren == 1: - if arg.strip(): - args.append(arg) - arg = '' - else: - arg += c - if paren != 0: - raise Exception("missing closing parenthesis: " + text) - if arg.strip(): - args.append(arg) - - return (args, l) - -def load_include_path(dir): - if not dir in include_dirs: - print("*** include path: " + dir) - include_dirs.append(dir) - -def resolve_include_path(filename, parent_dir): - if os.path.basename(filename) in exclude_files: - return None - if os.path.isfile(filename): - return os.path.abspath(filename) - search_dirs = include_dirs - if parent_dir: - search_dirs.append(parent_dir) - for dir in search_dirs: - filepath = os.path.join(dir, filename) - if os.path.isfile(filepath): - return os.path.abspath(filepath) - raise Exception("couldn't find include file: " + filename + " in " + parent_dir) - -def remove_comments(text): - text = re.sub(re.compile("/\*.*?\*/",re.DOTALL ), "", text) # multiline - text = re.sub(re.compile("//.*?\n" ), "\n", text) # singleline - return text - -def add_macro(name, args, value): - macro = (name, args, value) - macros.append(macro) - ''' - if not args is None: - print("*** token: " + name + "(", end='') - for i in range(len(args)): - if i > 0: - print(', ', end='') - print(args[i], end='') - print(")=" + value) +def parse_dtype_width(xml_doc, dtype_id): + xml_type = xml_doc.find(".//typetable/*[@id='" + dtype_id + "']") + if xml_type.tag == "packarraydtype" or xml_type.tag == "unpackarraydtype": + sub_dtype_id = xml_type.get("sub_dtype_id") + base_width = parse_dtype_width(xml_doc, sub_dtype_id) + const = xml_type.iter("const") + left = parse_vl_int(next(const).get("name")) + right = parse_vl_int(next(const).get("name")) + return base_width * (left - right + 1) + elif xml_type.tag == "structdtype": + width = 0 + for member in xml_type.iter("memberdtype"): + sub_dtype_id = member.get("sub_dtype_id") + width = width + parse_dtype_width(xml_doc, sub_dtype_id) + return width + elif xml_type.tag == "uniondtype": + width = 0 + for member in xml_type.iter("memberdtype"): + sub_dtype_id = member.get("sub_dtype_id") + width = max(width, parse_dtype_width(xml_doc, sub_dtype_id)) + return width else: - print("*** token: " + name + "=" + value) - ''' - -def find_macro(name): - for macro in macros: - if macro[0] == name: - return macro - return None - -def expand_text(text, params): - - def re_pattern_args(args): - p = "(? 0: - p += "|" - p += arg - i += 1 - p += ")(?![0-9a-zA-Z_])" - return p - - class DoReplParam(object): - def __init__(self, params): - self.params = params - self.expanded = False - def __call__(self, match): - name = match.group(1) - self.expanded = True - return self.params[name] - - class DoReplMacro(object): - def __init__(self): - self.expanded = False - self.has_func = False - def __call__(self, match): - name = match.group(1) - macro = find_macro(name) - if macro: - if not macro[1] is None: - self.has_func = True - else: - self.expanded = True - return macro[2] - return "`" + name - - def repl_func_macro(text): - expanded = False - match = re.search(vl_expand_re, text) - if match: - name = match.group(1) - macro = find_macro(name) - if macro: - args = macro[1] - value = macro[2] - if not args is None: - str_args = text[match.end():].strip() - f_args = parse_func_args(str_args) - if len(args) == 0: - if len(f_args[0]) != 0: - raise Exception("invalid argments for macro '" + name + "': value=" + text) - else: - if len(args) != len(f_args[0]): - raise Exception("mismatch number of argments for macro '" + name + "': actual=" + len(f_args[0]) + ", expected=" + len(args)) - - pattern = re_pattern_args(args) - params = {} - for i in range(len(args)): - params[args[i]] = f_args[0][i] - dorepl = DoReplParam(params) - value = re.sub(pattern, dorepl, value) - - str_head = text[0:match.start()] - str_tail = text[match.end() + f_args[1]+1:] - text = str_head + value + str_tail - expanded = True - if expanded: - return text - return None - - changed = False - iter = 0 - - while True: - if iter > 65536: - raise Exception("Macro recursion!") - has_func = False - while True: - params_updated = False - if not params is None: - do_repl = DoReplParam(params) - pattern = re_pattern_args(params) - new_text = re.sub(pattern, do_repl, text) - if do_repl.expanded: - text = new_text - params_updated = True - do_repl = DoReplMacro() - new_text = re.sub(vl_expand_re, do_repl, text) - has_func = do_repl.has_func - if not (params_updated or do_repl.expanded): - break - text = new_text - changed = True - if not has_func: - break - expanded = repl_func_macro(text) - if not expanded: - break - text = expanded - changed = True - iter += 1 - - if changed: - return text - return None - -def parse_include(filename, nesting): - print("*** parsing: " + filename + "...") - if nesting > 99: - raise Exception("include recursion!") - #print("*** parsing '" + filename + "'...") - content = None - with open(filename, "r") as f: - content = f.read() - # remove comments - content = remove_comments(content) - # parse content - prev_line = None - for line in content.splitlines(False): - # skip empty lines - if re.match(re.compile(r'^\s*$'), line): - continue - # merge multi-line lines - if line.endswith('\\'): - if prev_line: - prev_line += line[:len(line) - 1] - else: - prev_line = line[:len(line) - 1] - continue - if prev_line: - line = prev_line + line - prev_line = None - # parse ifdef - m = re.match(vl_ifdef_re, line) - if m: - key = m.group(1) - cond = m.group(2) - taken = find_macro(cond) is not None - if key == 'ifndef': - taken = not taken - elif key == '"elsif': - br_stack.pop() - br_stack.append(taken) - #print("*** " + key + "(" + cond + ") => " + str(taken)) - continue - # parse endif - m = re.match(vl_endif_re, line) - if m: - key = m.group(1) - top = br_stack.pop() - if key == 'else': - br_stack.append(not top) - #print("*** " + key) - continue - # skip disabled blocks - if not all(br_stack): - continue + sub_dtype_id = xml_type.get("sub_dtype_id") + if sub_dtype_id != None: + return parse_dtype_width(xml_doc, sub_dtype_id) + left = xml_type.get("left") + right = xml_type.get("right") + if left != None and right != None: + return int(left) - int(right) + 1 + return 1 - # parse include - m = re.match(vl_include_re, line) - if m: - include = m.group(1) - include = resolve_include_path(include, os.path.dirname(filename)) - if include: - parse_include(include, nesting + 1) - continue - # parse define - m = re.match(vl_define_re, line) - if m: - name = m.group(1) - args = m.group(2) - if args: - args = args[1:len(args)-1].strip() - if args != '': - args = args.split(',') - for i in range(len(args)): - args[i] = args[i].strip() - else: - args = [] - value = m.group(3) - add_macro(name, args, value.strip()) +def parse_var_name(xml_doc, xml_node): + if xml_node.tag == "varref": + return xml_node.get("name") + elif xml_node.tag == "varxref": + name = xml_node.get("name") + dotted = xml_node.get("dotted") + return dotted + '.' + name + else: + raise ET.ParseError("invalid probe entry" + source_loc(xml_doc, xml_node.get("loc"))) + return name + +def parse_sel_name(xml_doc, xml_node): + name = parse_var_name(xml_doc, xml_node.find("*")) + const = xml_node.iter("const") + offset = parse_vl_int(next(const).get("name")) + #size = parse_vl_int(next(const).get("name")) + return name + '_' + str(offset) + +def parse_array_name(xml_doc, xml_node): + if xml_node.tag == "arraysel": + name = parse_array_name(xml_doc, xml_node.find("*")) + xml_size = xml_node.find("const").get("name") + array_size = parse_vl_int(xml_size) + name = name + '_' + str(array_size) + else: + name = parse_var_name(xml_doc, xml_node) + return name + +def parse_vl_port(xml_doc, xml_node, signals): + total_width = 0 + if xml_node.tag == "concat": + for xml_child in xml_node.findall("*"): + total_width = total_width + parse_vl_port(xml_doc, xml_child, signals) + elif xml_node.tag == "varref" or xml_node.tag == "varxref": + name = parse_var_name(xml_doc, xml_node) + dtype_id = xml_node.get("dtype_id") + signal_width = parse_dtype_width(xml_doc, dtype_id) + signals.append([name, signal_width]) + total_width = total_width + signal_width + elif xml_node.tag == "sel": + name = parse_sel_name(xml_doc, xml_node) + dtype_id = xml_node.get("dtype_id") + signal_width = parse_dtype_width(xml_doc, dtype_id) + signals.append([name, signal_width]) + total_width = total_width + signal_width + elif xml_node.tag == "arraysel": + name = parse_array_name(xml_doc, xml_node) + dtype_id = xml_node.get("dtype_id") + signal_width = parse_dtype_width(xml_doc, dtype_id) + signals.append([name, signal_width]) + total_width = total_width + signal_width + else: + raise ET.ParseError("invalid probe entry: " + source_loc(xml_doc, xml_node.get("loc"))) + return total_width + +def parse_xml(filename, max_taps): + xml_doc = ET.parse(filename) + modules = {} + xml_modules = xml_doc.findall(".//module/[@origName='VX_scope_tap']") + for xml_module in xml_modules: + scope_id = parse_vl_int(xml_module.find(".//var/[@name='SCOPE_ID']/const").get("name")) + triggerw = parse_vl_int(xml_module.find(".//var/[@name='TRIGGERW']/const").get("name")) + probew = parse_vl_int(xml_module.find(".//var/[@name='PROBEW']/const").get("name")) + module_name = xml_module.get("name") + modules[module_name] = [scope_id, triggerw, probew] + + taps = [] + xml_instances = xml_doc.iter("instance") + for xml_instance in xml_instances: + if (max_taps != -1 and len(taps) >= max_taps): + break + defName = xml_instance.get("defName") + module = modules.get(defName) + if module is None: continue + triggers = [] + probes = [] + w = parse_vl_port(xml_doc, xml_instance.find(".//port/[@name='triggers']/*"), triggers) + if w != module[1]: + raise ET.ParseError("invalid triggers width: actual=" + str(w) + ", expected=" + str(module[1])) + w = parse_vl_port(xml_doc, xml_instance.find(".//port/[@name='probes']/*"), probes) + if w != module[2]: + raise ET.ParseError("invalid probes width: actual=" + str(w) + ", expected=" + str(module[2])) + signals = probes + for trigger in triggers: + signals.append(trigger) + loc = xml_instance.get("loc") + hier = xml_doc.find(".//cell/[@loc='" + loc + "']").get("hier") + path = hier.rsplit(".", 1)[0] + taps.append({"id":module[0], + "width":module[1] + module[2], + "signals":signals, + "path":path}) -def parse_includes(includes): - # change current directory to include directory - old_dir = os.getcwd() - script_dir = os.path.dirname(os.path.realpath(__file__)) - os.chdir(script_dir) - - for include in includes: - parse_include(include, 0) - load_include_path(os.path.dirname(include)) - - # restore current directory - os.chdir(old_dir) - -def load_defines(defines): - for define in defines: - key_value = define.split('=', 2) - name = key_value[0] - value = '' - if len(key_value) == 2: - value = key_value[1] - add_macro(name, None, value) - -def load_config(filename): - with open(filename, "r") as f: - config = json.load(f) - print("condfig=", config) - return config - -def eval_node(text, params): - def clog2(x): - l2 = math.log2(x) - cl = math.ceil(l2) - return int(cl) - - if not type(text) == str: - return text - - expanded = expand_text(text, params) - if expanded: - text = expanded - - try: - __text = text.replace('$clog2', '__clog2') - __text = translate_ternary(__text) - __text = __text.replace('||', 'or') - __text = __text.replace('&&', 'and') - e = eval(__text, {'__clog2': clog2}) - return e - except (NameError, SyntaxError): - return text - -def gen_vl_header(file, modules, taps): - - header = ''' -`ifndef VX_SCOPE_DEFS -`define VX_SCOPE_DEFS -''' - footer = '`endif' - - def signal_size(size, mn): - if type(size) == int: - if (size != mn): - return "[" + str(size-1) + ":0]" - else: - return "" - else: - return "[" + size + "-1:0]" - - def create_signal(key, ports): - if not key in ports: - ports[key] = [] - return ports[key] - - def dic_insert(gdic, ldic, key, value, enabled): - if enabled: - ldic[key] = value - if key in gdic: - return False - if enabled: - gdic[key] = None - return True - - def trigger_name(name, size): - if type(size) == int: - if size != 1: - return "(| " + name + ")" - else: - return name - else: - return "(| " + name + ")" - - def trigger_subscripts(asize): - def Q(arr, ss, asize, idx, N): - a = asize[idx] - if (a != 0): - for i in range(a): - tmp = ss + '[' + str(i) + ']' - if (idx + 1) < N: - Q(arr, tmp, asize, idx + 1, N) - else: - arr.append(tmp) - else: - if (idx + 1) < N: - Q(arr, ss, asize, idx + 1, N) - else: - arr.append(ss) - - if asize is None: - return [""] - ln = len(asize) - if (0 == ln): - return [""] - arr = [] - Q(arr, "", asize, 0, ln) - return arr - - - def visit_path(alltaps, ports, ntype, paths, modules, taps): - curtaps = {} - - if (len(paths) != 0): - spath = paths.pop(0) - snodes = modules[ntype]["submodules"] - if not spath in snodes: - raise Exception("invalid path: " + spath + " in " + ntype) - - snode = snodes[spath] - - stype = snode["type"] - - enabled = True - if "enabled" in snode: - enabled = eval_node(snode["enabled"], None) - - subtaps = visit_path(alltaps, ports, stype, paths, modules, taps) - - scount = 0 - if "count" in snode: - scount = eval_node(snode["count"], None) - - params = None - if "params" in snode: - params = snode["params"] - - new_staps = [] - - nn = "SCOPE_IO_" + ntype - pp = create_signal(nn, ports) - - for key in subtaps: - subtap = subtaps[key] - s = subtap[0] - a = subtap[1] - t = subtap[2] - - aa = [scount] - sa = signal_size(scount, 0) - if a: - for i in a: - x = eval_node(i, params) - aa.append(x) - sa += signal_size(x, 0) - - if dic_insert(alltaps, curtaps, spath + '/' + key, (s, aa, t), enabled): - skey = key.replace('/', '_') - if enabled: - pp.append("\toutput wire" + sa + signal_size(s, 1) + " scope_" + spath + '_' + skey + ',') - new_staps.append(skey) - - ports[nn] = pp - - if (0 == scount): - nn = "SCOPE_BIND_" + ntype + '_' + spath - pp = create_signal(nn, ports) - - for st in new_staps: - if enabled: - pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "),") - else: - pp.append("\t`UNUSED_PIN (scope_" + st + "),") - - ports[nn] = pp - else: - nn = "SCOPE_BIND_" + ntype + '_' + spath + "(__i__)" - pp = create_signal(nn, ports) - - for st in new_staps: - if enabled: - pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "[__i__]),") - else: - pp.append("\t`UNUSED_PIN (scope_" + st + "),") - - ports[nn] = pp - else: - nn = "SCOPE_IO_" + ntype - pp = create_signal(nn, ports) - - for tk in taps: - trigger = 0 - name = tk - size = eval_node(taps[tk], None) - if name[0] == '!': - name = name[1:] - trigger = 1 - elif name[0] == '?': - name = name[1:] - trigger = 2 - if dic_insert(alltaps, curtaps, name, (size, None, trigger), True): - pp.append("\toutput wire" + signal_size(size, 1) + " scope_" + name + ',') - - ports[nn] = pp - - return curtaps - - toptaps = {} - - with open(file, 'w') as f: - - ports = {} - alltaps = {} - - for key in taps: - skey_list = key.split(',') - _taps = taps[key] - for skey in skey_list: - #print('*** processing node: ' + skey + ' ...') - paths = skey.strip().split('/') - ntype = paths.pop(0) - curtaps = visit_path(alltaps, ports, ntype, paths, modules, _taps) - for tk in curtaps: - toptaps[tk] = curtaps[tk] - - print(header, file=f) - - for key in ports: - print("`define " + key + ' \\', file=f) - for port in ports[key]: - print(port + ' \\', file=f) - print("", file=f) - - print("`define SCOPE_DECL_SIGNALS \\", file=f) - i = 0 - for key in toptaps: - tap = toptaps[key] - name = key.replace('/', '_') - size = tap[0] - asize = tap[1] - sa = "" - if asize: - for a in asize: - sa += signal_size(a, 0) - if i > 0: - print(" \\", file=f) - print('\t wire' + sa + signal_size(size, 1) + " scope_" + name + ';', file=f, end='') - i += 1 - print("", file=f) - print("", file=f) - - print("`define SCOPE_DATA_LIST \\", file=f) - i = 0 - for key in toptaps: - tap = toptaps[key] - trigger = tap[2] - if trigger != 0: - continue - name = key.replace('/', '_') - if i > 0: - print(", \\", file=f) - print("\t scope_" + name, file=f, end='') - i += 1 - print("", file=f) - print("", file=f) - - print("`define SCOPE_UPDATE_LIST \\", file=f) - i = 0 - for key in toptaps: - tap = toptaps[key] - trigger = tap[2] - if trigger == 0: - continue - name = key.replace('/', '_') - if i > 0: - print(", \\", file=f) - print("\t scope_" + name, file=f, end='') - i += 1 - print("", file=f) - print("", file=f) - - print("`define SCOPE_TRIGGER \\", file=f) - i = 0 - for key in toptaps: - tap = toptaps[key] - if tap[2] != 2: - continue - size = tap[0] - asize = tap[1] - sus = trigger_subscripts(asize) - for su in sus: - if i > 0: - print(" | \\", file=f) - print("\t(", file=f, end='') - name = trigger_name("scope_" + key.replace('/', '_') + su, size) - print(name, file=f, end='') - print(")", file=f, end='') - i += 1 - print("", file=f) - print("", file=f) - - print(footer, file=f) - - return toptaps - -def gen_cc_header(file, taps): - - header = ''' -#pragma once - -struct scope_module_t { - const char* name; - int index; - int parent; -}; - -struct scope_tap_t { - int width; - const char* name; - int module; -}; -''' - def flatten_path(paths, sizes): - def Q(arr, ss, idx, N, paths, sizes): - size = sizes[idx] - if size != 0: - for i in range(sizes[idx]): - tmp = ss + ('/' if (ss != '') else '') - tmp += paths[idx] + '_' + str(i) - if (idx + 1) < N: - Q(arr, tmp, idx + 1, N, paths, sizes) - else: - arr.append(tmp) - else: - tmp = ss + ('/' if (ss != '') else '') - tmp += paths[idx] - if (idx + 1) < N: - Q(arr, tmp, idx + 1, N, paths, sizes) - else: - arr.append(tmp) - - arr = [] - Q(arr, "", 0, len(asize), paths, asize) - return arr - - # flatten the taps - fdic = {} - for key in taps: - tap = taps[key] - size = str(tap[0]) - trigger = tap[2] - if (trigger != 0): - continue - paths = key.split('/') - if (len(paths) > 1): - name = paths.pop(-1) - asize = tap[1] - for ss in flatten_path(paths, asize): - fdic[ss + '/' + name ] = [size, 0] - else: - fdic[key] = [size, 0] - for key in taps: - tap = taps[key] - size = str(tap[0]) - trigger = tap[2] - if (trigger == 0): - continue - paths = key.split('/') - if (len(paths) > 1): - name = paths.pop(-1) - asize = tap[1] - for ss in flatten_path(paths, asize): - fdic[ss + '/' + name ] = [size, 0] - else: - fdic[key] = [size, 0] - - # generate module dic - mdic = {} - mdic["*"] = ("*", 0, -1) - for key in fdic: - paths = key.split('/') - if len(paths) == 1: - continue - paths.pop(-1) - parent = 0 - mk = "" - for path in paths: - mk += '/' + path - if not mk in mdic: - index = len(mdic) - mdic[mk] = (path, index, parent) - parent = index - else: - parent = mdic[mk][1] - fdic[key][1] = parent - - with open(file, 'w') as f: - print(header, file=f) - - print("static constexpr scope_module_t scope_modules[] = {", file=f) - i = 0 - for key in mdic: - m = mdic[key] - if i > 0: - print(',', file=f) - print("\t{\"" + m[0] + "\", " + str(m[1]) + ", " + str(m[2]) + "}", file=f, end='') - i += 1 - print("", file=f) - print("};", file=f) - - print("", file=f) - print("static constexpr scope_tap_t scope_taps[] = {", file=f) - i = 0 - for key in fdic: - size = fdic[key][0] - parent = fdic[key][1] - paths = key.split('/') - if len(paths) > 1: - name = paths.pop(-1) - else: - name = key - if i > 0: - print(',', file=f) - print("\t{" + size + ", \"" + name + "\", " + str(parent) + "}", file=f, end='') - i += 1 - print("", file=f) - print("};", file=f) + return {"version":"0.1.0", "taps":taps} def main(): parser = argparse.ArgumentParser(description='Scope headers generator.') - parser.add_argument('-vl', nargs='?', default='scope-defs.vh', metavar='file', help='Output Verilog header') - parser.add_argument('-cc', nargs='?', default='scope-defs.h', metavar='file', help='Output C++ header') - parser.add_argument('-D', nargs='?', action='append', metavar='macro[=value]', help='define macro') - parser.add_argument('-I', nargs='?', action='append', metavar='', help='include directory') - parser.add_argument('config', help='Json config file') + parser.add_argument('-o', nargs='?', default='scope.json', metavar='o', help='Output JSON manifest') + parser.add_argument('-n', nargs='?', default=-1, metavar='n', type=int, help='Maximum number of taps to read') + parser.add_argument('xml', help='Design XML descriptor file') args = parser.parse_args() - print("args=", args) - - global exclude_files - global include_dirs - global macros - global br_stack - - if args.I: - for dir in args.I: - load_include_path(dir) - - if args.D: - load_defines(args.D) - - config = load_config(args.config) - - exclude_files.append(os.path.basename(args.vl)) - - if "include_paths" in config: - for path in config["include_paths"]: - load_include_path(path) - - if "includes" in config: - parse_includes(config["includes"]) - - taps = gen_vl_header(args.vl, config["modules"], config["taps"]) - gen_cc_header(args.cc, taps) + #print("args=", args) + scope_taps = parse_xml(args.xml, args.n) + with open(args.o, "w") as f: + json.dump(scope_taps, f, ensure_ascii=False, indent=4) if __name__ == '__main__': - main() \ No newline at end of file + main() diff --git a/hw/syn/yosys/sv2v.sh b/hw/scripts/sv2v.sh similarity index 58% rename from hw/syn/yosys/sv2v.sh rename to hw/scripts/sv2v.sh index cf5abaaf..9ab6799a 100755 --- a/hw/syn/yosys/sv2v.sh +++ b/hw/scripts/sv2v.sh @@ -1,5 +1,18 @@ #!/bin/bash +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + # this script uses sv2v and yosys tools to run. # sv2v: https://github.com/zachjs/sv2v # yosys: http://www.clifford.at/yosys/ @@ -14,8 +27,11 @@ output_file=out.v usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; } [ $# -eq 0 ] && usage -while getopts "o:I:D:h" arg; do +while getopts "t:s:o:I:D:h" arg; do case $arg in + t) # source + top=--top=${OPTARG} + ;; s) # source source=${OPTARG} ;; @@ -54,4 +70,4 @@ do done # system-verilog to verilog conversion -sv2v $macro_args $inc_args $file_args -v -w $output_file \ No newline at end of file +sv2v $top $macro_args $inc_args $file_args -v -w $output_file \ No newline at end of file diff --git a/hw/syn/altera/.gitignore b/hw/syn/altera/.gitignore new file mode 100644 index 00000000..e338f642 --- /dev/null +++ b/hw/syn/altera/.gitignore @@ -0,0 +1 @@ +ip_cache/* \ No newline at end of file diff --git a/hw/syn/altera/NOTEBOOK b/hw/syn/altera/NOTEBOOK new file mode 100644 index 00000000..5a76e235 --- /dev/null +++ b/hw/syn/altera/NOTEBOOK @@ -0,0 +1,106 @@ +## Altera synthesis Notebook + +## To configure quartus and opae. Run this after logging in. +source /export/fpga/bin/setup-fpga-env fpga-pac-a10 + +# Configure a Quartus build area +afu_synth_setup -s sources.txt build_fpga + +# Run Quartus in the vLab batch queue +cd build_fpga && qsub-synth + +# check last 10 lines in build log for possible errors +tail -n 10 ./build_arria10_fpga_1c/build.log + +# Check if the job is submitted to the queue and running. Status should be R +qstat | grep + +# Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C +watch ‘qstat | grep ’ + +# +## Executing on FPGA +# + +# From the build_fpga directory acquire a fpga node +qsub-fpga + +# Go to the directory whree qsub-synth was run above +cd $PBS_O_WORKDIR + +# Load the image onto an FPGA +fpgaconf /synth/vortex_afu.gbs + +# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port +fpgaconf --bus 0xaf /synth/vortex_afu.gbs + +# get portid +fpgainfo port + +# Running the Test case +cd /driver/tests/basic +make run-fpga + +# +## ASE build instructions +# +source /export/fpga/bin/setup-fpga-env fpga-pac-a10 + +# Acquire a sever node for running ASE simulations +qsub-sim + +# build ASE runtime +TARGET=asesim make -C runtime/opae + +# build ASE hw image +PREFIX=build_base CONFIGS="-DEXT_F_DISABLE -DL1_DISABLE -DSM_DISABLE -DNUM_WARPS=2 -DNUM_THREADS=2" TARGET=asesim make +PREFIX=build_gfx CONFIGS="-DEXT_GFX_ENABLE -DTCACHE_DISABLE -DRCACHE_DISABLE -DOCACHE_DISABLE -DEXT_F_DISABLE -DL1_DISABLE -DSM_DISABLE -DNUM_WARPS=2 -DNUM_THREADS=2" TARGET=asesim make + +# ASE test runs +./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n1 -t0 +./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n1 -t1 +./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/basic/basic -n16 +./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/demo/demo -n16 +./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/regression/dogfood/dogfood -n16 +./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/opencl/vecadd/vecadd +./run_ase.sh build_base_arria10_asesim_1c/synth ../../../../tests/opencl/sgemm/sgemm -n4 +./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/tex/tex +./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/rop/rop -w8 -h8 +./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/raster/raster -w8 -h8 +./run_ase.sh build_gfx_arria10_asesim_1c/synth ../../../../tests/regression/draw3d/draw3d -w8 -h8 + +# modify "vsim_run.tcl" to dump VCD trace +vcd file trace.vcd +vcd add -r /*/Vortex/hw/rtl/* +run -all + +# compress FPGA output files +tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)` + +# compress log trace +tar -zcvf run.log.tar.gz run.log +tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log +tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/synth/work/run.log build_arria10_ase_1c/work/trace.vcd + +# decompress log trace +tar -zxvf vortex.vcd.tar.gz +tar -xvf vortex.vcd.tar.bz2 + +# building FPGA images +make all +PREFIX=build_gfx NUM_CORES=2 CONFIGS="-DEXT_GFX_ENABLE" make + +# building gfx test on systems with custom boost directory +LDFLAGS += -L/homes/tinebp/tools/boost/lib + +# running benchmarks on FPGA +fpgaconf --bus 0xaf /synth/vortex_afu.gbs +TARGET=fpga ./ci/blackbox.sh --driver=opae --app=sgemm +TARGET=fpga ./ci/blackbox.sh --driver=opae --app=draw3d --args="-w512 -h512 -tvase.cgltrace" + +# quick off synthesis +make core + +# generate reports +./report_timing.sh +./report_area.sh \ No newline at end of file diff --git a/hw/syn/altera/analyze_timing.sh b/hw/syn/altera/analyze_timing.sh new file mode 100755 index 00000000..81393654 --- /dev/null +++ b/hw/syn/altera/analyze_timing.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +# Timing Analysis +# first argument is the project name + +SCRIPT_DIR="$(dirname "${BASH_SOURCE[0]}")" +SCRIPT_DIR="$(realpath "${SCRIPT_DIR}")" + +PROJECT_DIR=$1 +PROJECT=$2 +MODE=${3-fit} + +echo "Running quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE in $PROJECT_DIR ..." + +pushd $PROJECT_DIR +quartus_sta -t $SCRIPT_DIR/analyze_timing.tcl $PROJECT $MODE +popd \ No newline at end of file diff --git a/hw/syn/altera/analyze_timing.tcl b/hw/syn/altera/analyze_timing.tcl new file mode 100644 index 00000000..8cd1eb29 --- /dev/null +++ b/hw/syn/altera/analyze_timing.tcl @@ -0,0 +1,145 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +set ProjectName [lindex $argv 0] +set SynMode [lindex $argv 1] +if { $SynMode == "map" } { + set FileSuffix "map" +} else { + set FileSuffix "fit" +} + +proc do_timing_checks { ProjectName FileSuffix } { + # Validate timing DRC rules + # REF: http://quartushelp.altera.com/14.0/mergedProjects/tafs/tafs/tcl_pkg_sta_ver_1.0_cmd_check_timing.htm + check_timing -include {no_clock multiple_clock loops latches } -file $ProjectName.$FileSuffix.timing.check_errors.html + # NOTE: metastability requires QSF setting of Synchronizer Identification = Auto + # can also embed in Verilog: (* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *) + report_metastability -nchains 100 -file $ProjectName.$FileSuffix.timing.check_metastability.html +} + +proc do_timing_detailed_slackpaths { ProjectName FileSuffix SynMode } { + # Detailed info for top 100 setup/hold paths + if { $SynMode == "fit" } { + set npaths_detailed 200 + set npaths_pairs 10000 + set npaths_maxslack 0.2 + # Create html reports showing details of each of the top 100 paths (creates html index + subdir with css/images/etc) + set ExtraRTArgs "-show_routing" + report_timing -setup -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.setup.html + report_timing -hold -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.hold.html + report_timing -recovery -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.recovery.html + report_timing -removal -nworst $npaths_detailed -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.removal.html + + # Create txt with (slack,src,dst) for cross-seed comparisons + report_timing -setup -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.setup.txt + report_timing -hold -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.hold.txt + report_timing -recovery -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.recovery.txt + report_timing -removal -nworst $npaths_pairs -less_than_slack $npaths_maxslack -detail summary -pairs_only -file $ProjectName.$FileSuffix.timing_paths.removal.txt + + # Histogram of setup/hold slacks across all clocks + set allclocks [get_clocks] + foreach_in_collection curclk $allclocks { + set clkname [ get_clock_info -name $curclk ] + create_slack_histogram -clock_name $clkname -setup -file $ProjectName.$FileSuffix.timing_histogram.$clkname.setup.html + #create_slack_histogram -clock_name $clkname -hold -file $ProjectName.$FileSuffix.timing_histogram.$clkname.hold.html + } + # Just emit simple setup paths if analyzing MAP netlist + } else { + set ExtraRTArgs "" + report_timing -setup -nworst 100 -detail full_path $ExtraRTArgs -file $ProjectName.$FileSuffix.timing.setup.html + } +} + +proc do_timing_summary { ProjectName FileSuffix } { + # Save summary into to single txt file + create_timing_summary -setup -file $ProjectName.$FileSuffix.timing.summary.txt + create_timing_summary -hold -append -file $ProjectName.$FileSuffix.timing.summary.txt + report_clocks -summary -append -file $ProjectName.$FileSuffix.timing.summary.txt + report_clock_fmax_summary -append -file $ProjectName.$FileSuffix.timing.summary.txt +} + +proc do_timing_detailed_bottleneck_paths { ProjectName FileSuffix } { + # Create bottleneck timing analysis with different metrics to analyze setup paths + #proc custom_metric_fanins {arg} { + # upvar $arg metric + # set rating $metric(num_fanins) + # return $rating + #} + #report_bottleneck -cmetric custom_metric_fanins -file timing.bottlneck.num_fanins.html $tpaths + set tpaths [ get_timing_paths -nworst 1000 -setup ] + set tns_paths [ report_bottleneck -metric tns $tpaths -stdout ] + set np_paths [ report_bottleneck -metric num_paths $tpaths -stdout ] + set nfp_paths [ report_bottleneck -metric num_fpaths $tpaths -stdout ] + set nfo_paths [ report_bottleneck -metric num_fanouts $tpaths -stdout ] + set nfi_paths [ report_bottleneck -metric num_fanins $tpaths -stdout ] + + set fo [ open "$ProjectName.$FileSuffix.timing.setup.bottlenecks.txt" "w" ] + puts $fo "Bottlenecks by TNS" + puts $fo $tns_paths + + puts $fo "Bottlenecks by NumPaths" + puts $fo $np_paths + + puts $fo "Bottlenecks by NumFailingPaths" + puts $fo $nfp_paths + + puts $fo "Bottlenecks by NumFanOuts" + puts $fo $nfo_paths + + puts $fo "Bottlenecks by NumFanIns" + puts $fo $nfi_paths +} + +# Iterate over all known operating conditions +# 3_H2_slow_850mv_100c / 3_H2_slow_850mv_100c / 3_H2_slow_850mv_0c / MIN_fast_850mv_100c / MIN_fast_850mv_0c +#foreach_in_collection oc [get_available_operating_conditions] { +# set_operating_conditions $oc +# post_message "Setting Operating Conditions $oc" +# update_timing_netlist +# report_timing -setup -npaths 100 -file $ProjectName.timing.setup.html +# report_timing -hold -npaths 100 -file $ProjectName.timing.hold.html +#} + +project_open $ProjectName + +# => allows comparison of raw logic vs impact of routing delays +if { $SynMode == "map" } { + create_timing_netlist -post_map + read_sdc + update_timing_netlist + + do_timing_detailed_slackpaths $ProjectName $FileSuffix $SynMode + do_timing_summary $ProjectName $FileSuffix + + delete_timing_netlist + +# normal post-par analysis (includes routing congestion/physical placement constraints) +} else { + create_timing_netlist + read_sdc + update_timing_netlist + + # Iterate over a single worst-case operating condition (grade/speed pre-selected based on netlist) + set_operating_conditions -voltage 900 -temperature 100 + update_timing_netlist + + do_timing_checks $ProjectName $FileSuffix + do_timing_detailed_slackpaths $ProjectName $FileSuffix $SynMode + do_timing_detailed_bottleneck_paths $ProjectName $FileSuffix + do_timing_summary $ProjectName $FileSuffix + + delete_timing_netlist +} + +project_close \ No newline at end of file diff --git a/hw/syn/altera/ip_gen.sh b/hw/syn/altera/ip_gen.sh new file mode 100755 index 00000000..36f3a706 --- /dev/null +++ b/hw/syn/altera/ip_gen.sh @@ -0,0 +1,50 @@ +#!/bin/bash + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +BUILD_DIR=$1 + +EXP_BITS=8 +MAN_BITS=23 +FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" + +CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 + +OPTIONS="-target $DEVICE_FAMILY -noChanValid -enable -enableHardFP 1 -faithfulRounding -speedgrade 2 -frequency 200 -lang verilog -printMachineReadable" + +export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH + +CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" + +mkdir -p $BUILD_DIR +pushd $BUILD_DIR + +echo Generating IP cores for $FBITS +{ + #$CMD -name acl_fadd FPAdd $EXP_BITS $MAN_BITS + #$CMD -name acl_fsub FPSub $EXP_BITS $MAN_BITS + #$CMD -name acl_fmul FPMul $EXP_BITS $MAN_BITS + $CMD -name acl_fmadd FPMultAdd $EXP_BITS $MAN_BITS + $CMD -name acl_fdiv FPDiv $EXP_BITS $MAN_BITS 0 + $CMD -name acl_fsqrt FPSqrt $EXP_BITS $MAN_BITS + #$CMD -name acl_ftoi FPToFXP $EXP_BITS $MAN_BITS 32 0 1 + #$CMD -name acl_ftou FPToFXP $EXP_BITS $MAN_BITS 32 0 0 + #$CMD -name acl_itof FXPToFP 32 0 1 $EXP_BITS $MAN_BITS + #$CMD -name acl_utof FXPToFP 32 0 0 $EXP_BITS $MAN_BITS +} > ip_gen.log 2>&1 + +cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv dspba_delay_ver.sv + +popd \ No newline at end of file diff --git a/hw/syn/altera/opae/.gitignore b/hw/syn/altera/opae/.gitignore new file mode 100644 index 00000000..1929af05 --- /dev/null +++ b/hw/syn/altera/opae/.gitignore @@ -0,0 +1 @@ +build*/* \ No newline at end of file diff --git a/hw/syn/altera/opae/Makefile b/hw/syn/altera/opae/Makefile new file mode 100644 index 00000000..e5594d0b --- /dev/null +++ b/hw/syn/altera/opae/Makefile @@ -0,0 +1,152 @@ +DEVICE_FAMILY ?= arria10 +XLEN ?= 32 +PREFIX ?= build$(XLEN) +TARGET ?= fpga +NUM_CORES ?= 1 + +SCRIPT_DIR = ../../../scripts +RTL_DIR = ../../../rtl +DPI_DIR = ../../../dpi +AFU_DIR = $(RTL_DIR)/afu/opae +THIRD_PARTY_DIR = ../../../../third_party +IP_CACHE_DIR = ../ip_cache/$(DEVICE_FAMILY) + +BUILD_DIR = $(PREFIX)_$(DEVICE_FAMILY)_$(TARGET)_$(NUM_CORES)c + +ifeq ($(shell which qsub-synth),) + RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 & +else + RUN_SYNTH=qsub-synth +endif + +# control RTL debug tracing states +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA +DBG_TRACE_FLAGS += -DDBG_TRACE_AFU +DBG_TRACE_FLAGS += -DDBG_TRACE_TEX +DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER +DBG_TRACE_FLAGS += -DDBG_TRACE_ROP +DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR + +# Control logic analyzer monitors +DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU +DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE +DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH +DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU +DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER +DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED + +ifeq ($(DEVICE_FAMILY), stratix10) + CONFIGS += -DALTERA_S10 +endif +ifeq ($(DEVICE_FAMILY), arria10) + CONFIGS += -DALTERA_A10 +endif + +# cluster configuration +CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1 +CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2 +CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 +CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 +CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS += $(CONFIGS_$(NUM_CORES)c) + +# include paths +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR) +RTL_INCLUDE += $(FPU_INCLUDE) + +# compilation flags +CFLAGS += -DSYNTHESIS -DQUARTUS +CFLAGS += -DXLEN_$(XLEN) +CFLAGS += $(CONFIGS) +CFLAGS += $(RTL_INCLUDE) + +ifneq ($(TARGET), fpga) + CFLAGS += -DSIMULATION +endif + +# Debugigng +ifdef DEBUG + ifeq ($(TARGET), fpga) + CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS) + SCOPE_JSON += $(BUILD_DIR)/scope.json + else + CFLAGS += $(DBG_TRACE_FLAGS) + endif +else + CFLAGS += -DNDEBUG +endif + +# Enable scope analyzer +ifdef SCOPE + CFLAGS += -DSCOPE +endif + +# Enable perf counters +ifdef PERF + CFLAGS += -DPERF_ENABLE +endif + +# ast dump flags +XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DNOPAE + +all: swconfig ip-gen setup build + +ip-gen: $(IP_CACHE_DIR)/ip-gen.log +$(IP_CACHE_DIR)/ip-gen.log: + ../ip_gen.sh $(IP_CACHE_DIR) + +swconfig: vortex_afu.h +vortex_afu.h: vortex_afu.json + afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ + +$(BUILD_DIR)/setup.cfg: + mkdir -p $(BUILD_DIR); cp setup.cfg $(BUILD_DIR)/setup.cfg + +$(BUILD_DIR)/vortex_afu.qsf: + mkdir -p $(BUILD_DIR); cp vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf + +$(BUILD_DIR)/vortex_afu.json: + mkdir -p $(BUILD_DIR); cp vortex_afu.json $(BUILD_DIR)/vortex_afu.json + +gen-sources: $(BUILD_DIR)/sources.txt +$(BUILD_DIR)/sources.txt: + mkdir -p $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -C$(BUILD_DIR)/src -O$(BUILD_DIR)/sources.txt + +setup: $(BUILD_DIR)/synth +$(BUILD_DIR)/synth: $(BUILD_DIR)/sources.txt $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/vortex_afu.qsf $(BUILD_DIR)/vortex_afu.json +ifeq ($(TARGET), asesim) + afu_sim_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth +else + afu_synth_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth +endif + +build: ip-gen setup $(SCOPE_JSON) +ifeq ($(TARGET), asesim) + make -C $(BUILD_DIR)/synth > $(BUILD_DIR)/synth/build.log 2>&1 & +else + cd $(BUILD_DIR)/synth && $(RUN_SYNTH) +endif + +gen-ast: $(BUILD_DIR)/vortex.xml +$(BUILD_DIR)/vortex.xml: setup + verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.sv --xml-output $(BUILD_DIR)/vortex.xml + +scope-json: $(BUILD_DIR)/scope.json +$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml + $(SCRIPT_DIR)/scope.py $(BUILD_DIR)/vortex.xml -o $(BUILD_DIR)/scope.json + +clean: + rm -rf vortex_afu.h $(BUILD_DIR) diff --git a/hw/syn/altera/opae/fpga_prog.sh b/hw/syn/altera/opae/fpga_prog.sh new file mode 100755 index 00000000..fe198b28 --- /dev/null +++ b/hw/syn/altera/opae/fpga_prog.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# FPGA programming +# first argument is the bitstream + +fpgaconf --bus 0xaf $1 diff --git a/hw/syn/opae/run_ase.sh b/hw/syn/altera/opae/run_ase.sh similarity index 52% rename from hw/syn/opae/run_ase.sh rename to hw/syn/altera/opae/run_ase.sh index 86b74121..ba30d209 100755 --- a/hw/syn/opae/run_ase.sh +++ b/hw/syn/altera/opae/run_ase.sh @@ -1,5 +1,18 @@ #!/bin/bash +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" BUILD_DIR=$1 @@ -7,7 +20,7 @@ BUILD_DIR=$1 PROGRAM=$(basename "$2") PROGRAM_DIR=`dirname $2` -VORTEX_DRV_PATH=$SCRIPT_DIR/../../../driver +VORTEX_RT_PATH=$SCRIPT_DIR/../../../../runtime # Export ASE_WORKDIR variable export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work @@ -35,5 +48,5 @@ done # run application pushd $PROGRAM_DIR echo " [DBG] running ./$PROGRAM $*" -ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/asesim:$LD_LIBRARY_PATH ./$PROGRAM $* -popd \ No newline at end of file +ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_RT_PATH/opae:$LD_LIBRARY_PATH ./$PROGRAM $* +popd diff --git a/hw/syn/altera/opae/setup.cfg b/hw/syn/altera/opae/setup.cfg new file mode 100644 index 00000000..96926120 --- /dev/null +++ b/hw/syn/altera/opae/setup.cfg @@ -0,0 +1,4 @@ +vortex_afu.json +QI:vortex_afu.qsf + +C:sources.txt diff --git a/hw/syn/opae/vortex_afu.json b/hw/syn/altera/opae/vortex_afu.json similarity index 80% rename from hw/syn/opae/vortex_afu.json rename to hw/syn/altera/opae/vortex_afu.json index 8f47e292..6a3a597e 100644 --- a/hw/syn/opae/vortex_afu.json +++ b/hw/syn/altera/opae/vortex_afu.json @@ -2,21 +2,24 @@ "version": 1, "afu-image": { "power": 0, - "clock-frequency-high": "auto", - "clock-frequency-low": "auto", + "clock-frequency-high": "auto-200", + "clock-frequency-low": "auto-100", "cmd-mem-read": 1, "cmd-mem-write": 2, "cmd-run": 3, + "cmd-dcr-write": 4, + "cmd-max-value": 4, "mmio-cmd-type": 10, - "mmio-io-addr": 12, - "mmio-mem-addr": 14, - "mmio-data-size": 16, + "mmio-cmd-arg0": 12, + "mmio-cmd-arg1": 14, + "mmio-cmd-arg2": 16, "mmio-status": 18, "mmio-scope-read": 20, "mmio-scope-write": 22, "mmio-dev-caps": 24, + "mmio-isa-caps": 26, "afu-top-interface": { diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/altera/opae/vortex_afu.qsf similarity index 83% rename from hw/syn/opae/vortex_afu.qsf rename to hw/syn/altera/opae/vortex_afu.qsf index 1628f9d8..e951faf6 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/altera/opae/vortex_afu.qsf @@ -4,24 +4,25 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON -set_global_assignment -name VERILOG_MACRO QUARTUS -set_global_assignment -name VERILOG_MACRO SYNTHESIS -set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" + set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON + set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON #set_global_assignment -name USE_HIGH_SPEED_ADDER ON #set_global_assignment -name MUX_RESTRUCTURE ON @@ -30,6 +31,6 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON #set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON #set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name SEED 1 \ No newline at end of file +#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +#set_global_assignment -name SEED 1 diff --git a/hw/syn/altera/power_play.sh b/hw/syn/altera/power_play.sh new file mode 100644 index 00000000..4f41bf01 --- /dev/null +++ b/hw/syn/altera/power_play.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +# Generate Power Report +# first argument is the project name + +quartus_pow --input_vcd=trace.vcd --vcd_filter_glitches=on --default_input_io_toggle_rate=10000transitions/s $1 \ No newline at end of file diff --git a/hw/syn/altera/quartus/.gitignore b/hw/syn/altera/quartus/.gitignore new file mode 100644 index 00000000..35930be0 --- /dev/null +++ b/hw/syn/altera/quartus/.gitignore @@ -0,0 +1,41 @@ +/unittest/* +!/unittest/Makefile + +/smem/* +!/smem/Makefile + +/cache/* +!/cache/Makefile + +/vortex/* +!/vortex/Makefile + +/pipeline/* +!/pipeline/Makefile + +/core/* +!/core/Makefile + +/top/* +!/top/Makefile + +/top-gfx/* +!/top-gfx/Makefile + +/test/* +!/test/Makefile + +/fpu/* +!/fpu/Makefile + +/tex/* +!/tex/Makefile + +/rop/* +!/rop/Makefile + +/raster/* +!/raster/Makefile + +/vortex-gfx/* +!/vortex-gfx/Makefile \ No newline at end of file diff --git a/hw/syn/altera/quartus/Makefile b/hw/syn/altera/quartus/Makefile new file mode 100644 index 00000000..7a81226c --- /dev/null +++ b/hw/syn/altera/quartus/Makefile @@ -0,0 +1,61 @@ +PREFIX ?= build + +BUILD_DIR=$(PREFIX)_$(DEVICE_FAMILY) + +IP_CACHE_DIR=../ip_cache/$(DEVICE_FAMILY) + +.PHONY: dogfood unittest pipeline smem cache fpu core vortex top test + +ip-gen: $(IP_CACHE_DIR)/ip_gen.log +$(IP_CACHE_DIR)/ip_gen.log: + ../ip_gen.sh $(IP_CACHE_DIR) + +dogfood: + mkdir -p dogfood/$(BUILD_DIR) + cp dogfood/Makefile dogfood/$(BUILD_DIR) + $(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 & + +unittest: + mkdir -p unittest/$(BUILD_DIR) + cp unittest/Makefile unittest/$(BUILD_DIR) + $(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 & + +pipeline: + mkdir -p pipeline/$(BUILD_DIR) + cp pipeline/Makefile pipeline/$(BUILD_DIR) + $(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 & + +smem: + mkdir -p smem/$(BUILD_DIR) + cp smem/Makefile smem/$(BUILD_DIR) + $(MAKE) -C smem/$(BUILD_DIR) clean && $(MAKE) -C smem/$(BUILD_DIR) > smem/$(BUILD_DIR)/build.log 2>&1 & + +cache: + mkdir -p cache/$(BUILD_DIR) + cp cache/Makefile cache/$(BUILD_DIR) + $(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 & + +fpu: ip-gen + mkdir -p fpu/$(BUILD_DIR) + cp fpu/Makefile fpu/$(BUILD_DIR) + $(MAKE) -C fpu/$(BUILD_DIR) clean && $(MAKE) -C fpu/$(BUILD_DIR) > fpu/$(BUILD_DIR)/build.log 2>&1 & + +core: + mkdir -p core/$(BUILD_DIR) + cp core/Makefile core/$(BUILD_DIR) + $(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 & + +vortex: ip-gen + mkdir -p vortex/$(BUILD_DIR) + cp vortex/Makefile vortex/$(BUILD_DIR) + $(MAKE) -C vortex/$(BUILD_DIR) clean && $(MAKE) -C vortex/$(BUILD_DIR) > vortex/$(BUILD_DIR)/build.log 2>&1 & + +top: ip-gen + mkdir -p top/$(BUILD_DIR) + cp top/Makefile top/$(BUILD_DIR) + $(MAKE) -C top/$(BUILD_DIR) clean && $(MAKE) -C top/$(BUILD_DIR) > top/$(BUILD_DIR)/build.log 2>&1 & + +test: ip-gen + mkdir -p test/$(BUILD_DIR) + cp test/Makefile test/$(BUILD_DIR) + $(MAKE) -C test/$(BUILD_DIR) clean && $(MAKE) -C test/$(BUILD_DIR) > test/$(BUILD_DIR)/build.log 2>&1 & diff --git a/hw/syn/altera/quartus/cache/Makefile b/hw/syn/altera/quartus/cache/Makefile new file mode 100755 index 00000000..258dc91a --- /dev/null +++ b/hw/syn/altera/quartus/cache/Makefile @@ -0,0 +1,7 @@ +PROJECT = VX_cache_cluster_top +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = VX_cache_cluster.sv + +include ../../common.mk + +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache diff --git a/hw/syn/altera/quartus/common.mk b/hw/syn/altera/quartus/common.mk new file mode 100644 index 00000000..5a9532a4 --- /dev/null +++ b/hw/syn/altera/quartus/common.mk @@ -0,0 +1,99 @@ +RTL_DIR = ../../../../../rtl +AFU_DIR = $(RTL_DIR)/afu/opae +THIRD_PARTY_DIR = ../../../../../../third_party +IP_CACHE_DIR = ../../../ip_cache/$(DEVICE_FAMILY) +SCRIPT_DIR = ../../../../../scripts +THIRD_PARTY_DIR = ../../../../../../third_party + +ifeq ($(DEVICE_FAMILY), stratix10) + FAMILY = "Stratix 10" + DEVICE = 1SX280HN2F43E2VG +endif +ifeq ($(DEVICE_FAMILY), arria10) + FAMILY = "Arria 10" + DEVICE = 10AX115N3F40E2SG +endif + +CONFIGS += -DNDEBUG +CONFIGS += -DQUARTUS +CONFIGS += -DSYNTHESIS +CONFIGS += -DNOGLOBALS + +PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf + +# Executable Configuration +SYN_ARGS = --parallel --read_settings_files=on +FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on +ASM_ARGS = +STA_ARGS = --parallel --do_report_timing +POW_ARGS = --no_input_file --default_input_io_toggle_rate=60% --default_toggle_rate=20% --use_vectorless_estimation=off + +# Build targets +all: gen-sources $(PROJECT).sta.rpt $(PROJECT).pow.rpt + +gen-sources: src +src: + mkdir -p src + $(SCRIPT_DIR)/gen_sources.sh $(CONFIGS) $(RTL_INCLUDE) -P -Csrc + +syn: $(PROJECT).syn.rpt + +fit: $(PROJECT).fit.rpt + +asm: $(PROJECT).asm.rpt + +sta: $(PROJECT).sta.rpt + +pow: $(PROJECT).pow.rpt + +smart: smart.log + +# Target implementations +STAMP = echo done > + +$(PROJECT).syn.rpt: smart.log syn.chg + quartus_syn $(SYN_ARGS) $(PROJECT) + $(STAMP) fit.chg + +$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt + quartus_fit $(FIT_ARGS) $(PROJECT) + $(STAMP) asm.chg + $(STAMP) sta.chg + +$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt + quartus_asm $(ASM_ARGS) $(PROJECT) + $(STAMP) pow.chg + +$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt + quartus_sta $(STA_ARGS) $(PROJECT) + +$(PROJECT).pow.rpt: smart.log pow.chg $(PROJECT).asm.rpt + quartus_pow $(POW_ARGS) $(PROJECT) + +smart.log: $(PROJECT_FILES) + quartus_sh --determine_smart_action $(PROJECT) > smart.log + +# Project initialization +$(PROJECT_FILES): gen-sources + quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "src" + +syn.chg: + $(STAMP) syn.chg + +fit.chg: + $(STAMP) fit.chg + +sta.chg: + $(STAMP) sta.chg + +asm.chg: + $(STAMP) asm.chg + +pow.chg: + $(STAMP) pow.chg + +program: $(PROJECT).sof + quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" + +clean: + rm -rf src bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/altera/quartus/core/Makefile b/hw/syn/altera/quartus/core/Makefile new file mode 100644 index 00000000..f1dc07f3 --- /dev/null +++ b/hw/syn/altera/quartus/core/Makefile @@ -0,0 +1,14 @@ +PROJECT = VX_core_top +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = VX_core.sv + +include ../../common.mk + +#CONFIGS += -DNUM_WARPS=32 +#CONFIGS += -DNUM_THREADS=32 + +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) \ No newline at end of file diff --git a/hw/syn/altera/quartus/fpu/Makefile b/hw/syn/altera/quartus/fpu/Makefile new file mode 100644 index 00000000..b7826dc6 --- /dev/null +++ b/hw/syn/altera/quartus/fpu/Makefile @@ -0,0 +1,11 @@ +PROJECT = VX_fpu_dsp +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = $(PROJECT).sv + +include ../../common.mk + +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR) diff --git a/hw/syn/altera/quartus/project.sdc b/hw/syn/altera/quartus/project.sdc new file mode 100644 index 00000000..6ea50853 --- /dev/null +++ b/hw/syn/altera/quartus/project.sdc @@ -0,0 +1 @@ +create_clock -name {clk} -period "200 MHz" -waveform { 0.000 1.0 } [get_ports {clk}] \ No newline at end of file diff --git a/hw/syn/quartus/project.tcl b/hw/syn/altera/quartus/project.tcl similarity index 73% rename from hw/syn/quartus/project.tcl rename to hw/syn/altera/quartus/project.tcl index 87fb09b7..7e4783a3 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/altera/quartus/project.tcl @@ -1,3 +1,16 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + load_package flow package require cmdline @@ -35,21 +48,11 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON -set_global_assignment -name VERILOG_MACRO QUARTUS -set_global_assignment -name VERILOG_MACRO SYNTHESIS -set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -set_global_assignment -name OPTIMIZATION_TECHNIQUE AREA set_global_assignment -name SEED 1 -# Power estimation -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - switch $opts(family) { "Arria 10" { set_global_assignment -name VERILOG_MACRO ALTERA_A10 @@ -82,11 +85,16 @@ foreach arg $q_args_orig { proc make_all_pins_virtual {} { execute_module -tool map + set excludes { clk } set name_ids [get_names -filter * -node_type pin] foreach_in_collection name_id $name_ids { set pin_name [get_name_info -info full_path $name_id] - post_message "Making VIRTUAL_PIN assignment to $pin_name" - set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON + if { [lsearch -exact -nocase $excludes $pin_name] >= 0 } { + post_message "Skipping VIRTUAL_PIN assignment to $pin_name" + } else { + post_message "Making VIRTUAL_PIN assignment to $pin_name" + set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON + } } export_assignments } diff --git a/hw/syn/altera/quartus/smem/Makefile b/hw/syn/altera/quartus/smem/Makefile new file mode 100755 index 00000000..f7fa73e3 --- /dev/null +++ b/hw/syn/altera/quartus/smem/Makefile @@ -0,0 +1,7 @@ +PROJECT = VX_shared_mem +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = $(PROJECT).sv + +include ../../common.mk + +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem diff --git a/hw/syn/altera/quartus/test/Makefile b/hw/syn/altera/quartus/test/Makefile new file mode 100644 index 00000000..0c4a7ae4 --- /dev/null +++ b/hw/syn/altera/quartus/test/Makefile @@ -0,0 +1,11 @@ +PROJECT = Vortex +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = $(PROJECT).sv + +include ../../common.mk + +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) diff --git a/hw/syn/quartus/timing-html.tcl b/hw/syn/altera/quartus/timing-html.tcl similarity index 62% rename from hw/syn/quartus/timing-html.tcl rename to hw/syn/altera/quartus/timing-html.tcl index 20d3fb52..fcdf5dc9 100644 --- a/hw/syn/quartus/timing-html.tcl +++ b/hw/syn/altera/quartus/timing-html.tcl @@ -1,3 +1,16 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + package require cmdline set options { diff --git a/hw/syn/altera/quartus/top/Makefile b/hw/syn/altera/quartus/top/Makefile new file mode 100644 index 00000000..a47389d7 --- /dev/null +++ b/hw/syn/altera/quartus/top/Makefile @@ -0,0 +1,18 @@ +PROJECT = vortex_afu +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = $(PROJECT).sv + +include ../../common.mk + +CONFIGS += -DNOPAE + +#CONFIGS += -DNUM_CORES=2 +#CONFIGS += -DNUM_WARPS=32 +#CONFIGS += -DNUM_THREADS=32 +#CONFIGS += -DL2_ENABLE + +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) diff --git a/hw/syn/altera/quartus/unittest/Makefile b/hw/syn/altera/quartus/unittest/Makefile new file mode 100644 index 00000000..2bfb18e4 --- /dev/null +++ b/hw/syn/altera/quartus/unittest/Makefile @@ -0,0 +1,11 @@ +PROJECT = Unittest +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = $(PROJECT).sv + +include ../../common.mk + +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) \ No newline at end of file diff --git a/hw/syn/altera/quartus/vortex/Makefile b/hw/syn/altera/quartus/vortex/Makefile new file mode 100644 index 00000000..7429df41 --- /dev/null +++ b/hw/syn/altera/quartus/vortex/Makefile @@ -0,0 +1,16 @@ +PROJECT = Vortex +TOP_LEVEL_ENTITY = $(PROJECT) +SRC_FILE = $(PROJECT).sv + +include ../../common.mk + +#CONFIGS += -DNUM_CORES=2 +#CONFIGS += -DNUM_WARPS=32 +#CONFIGS += -DNUM_THREADS=32 +#CONFIGS += -DL2_ENABLE + +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) diff --git a/hw/syn/altera/report_area.sh b/hw/syn/altera/report_area.sh new file mode 100755 index 00000000..55b2b8e0 --- /dev/null +++ b/hw/syn/altera/report_area.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +# Dump Area Report +# first argument is the project name + +SCRIPT_DIR="$(dirname "${BASH_SOURCE[0]}")" +SCRIPT_DIR="$(realpath "${SCRIPT_DIR}")" + +PROJECT_DIR=$1 +PROJECT=$2 +MODE=${3-fit} + +echo "Running quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE in $PROJECT_DIR ..." + +pushd $PROJECT_DIR +quartus_sh -t $SCRIPT_DIR/report_area.tcl $PROJECT $MODE +popd \ No newline at end of file diff --git a/hw/syn/altera/report_area.tcl b/hw/syn/altera/report_area.tcl new file mode 100644 index 00000000..0d33564d --- /dev/null +++ b/hw/syn/altera/report_area.tcl @@ -0,0 +1,105 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +load_package report + +set ProjectName [lindex $argv 0] +set SynMode [lindex $argv 1] + +proc panel_to_csv { panel_name csv_file } { + set fh [open $csv_file w] + # Its possible for some panels to not exist based on design (ex. if no RAMs ) + set num_rows [get_number_of_rows -name $panel_name] + catch { + for { set i 0 } { $i < $num_rows } { incr i } { + set row_data_raw [get_report_panel_row -name $panel_name -row $i] + set row_data [regsub -all , $row_data_raw ""] + puts $fh [join $row_data ","] + } + } + close $fh +} + +# Dump names of all known panels +proc do_dump_panelnames { } { + set fh [open "panels.txt" w] + set panel_names [get_report_panel_names] + foreach panel_name $panel_names { + puts $fh "$panel_name" + } + close $fh +} + +proc do_map_analysis { ProjectName } { + # Save synthesis results + set RSyn1 "Synthesis||Synthesis Source Files Read" + set RSyn2 "Synthesis||Partition \"root_partition\"||Synthesis Resource Usage Summary for Partition \"root_partition\"" + set RSyn3 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Resource Utilization by Entity" + set RSyn4 "Synthesis||Partition \"root_partition\"||Synthesis RAM Summary for Partition \"root_partition\"" + set RSyn5 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Optimization Results||Register Statistics||Registers Protected by Synthesis" + set RSyn6 "Synthesis||Partition \"root_partition\"||Post-Synthesis Netlist Statistics for Partition \"root_partition\"" + panel_to_csv $RSyn1 "$ProjectName.syn.area.source_files.csv" + panel_to_csv $RSyn2 "$ProjectName.syn.area.resource_summmary.csv" + panel_to_csv $RSyn3 "$ProjectName.syn.area.resource_breakdown.csv" + panel_to_csv $RSyn4 "$ProjectName.syn.area.ram_summary.csv" + panel_to_csv $RSyn5 "$ProjectName.syn.area.regs_removed.csv" + panel_to_csv $RSyn6 "$ProjectName.syn.area.stats.csv" +} + +proc do_fit_analysis { ProjectName } { + # Save par results + set RPar1 "Fitter||Place Stage||Fitter Resource Usage Summary" + set RPar2 "Fitter||Place Stage||Fitter Resource Utilization by Entity" + set RPar3 "Fitter||Place Stage||Fitter Partition Statistics" + set RPar4 "Fitter||Place Stage||Fitter RAM Summary" + set RPar5 "Fitter||Plan Stage||Global & Other Fast Signals Summary" + set RPar6 "Fitter||Place Stage||Non-Global High Fan-Out Signals" + set RPar7 "Fitter||Route Stage||Routing Usage Summary" + panel_to_csv $RPar1 "$ProjectName.fit.area.resource_summary.csv" + panel_to_csv $RPar2 "$ProjectName.fit.area.resource_breakdown.csv" + #panel_to_csv $RPar3 "$ProjectName.fit.area.stats.csv" + panel_to_csv $RPar4 "$ProjectName.fit.area.ram_summary.csv" + panel_to_csv $RPar5 "$ProjectName.fit.area.routing_global.csv" + panel_to_csv $RPar6 "$ProjectName.fit.area.routing_high_fanout.csv" + panel_to_csv $RPar7 "$ProjectName.fit.area.routing_summary.csv" +} + +proc do_fit_analysis_timingsummary { ProjectName } { + # Save timing results + set RT1 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Fmax Summary" + set RT2 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Setup Summary" + set RT3 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Hold Summary" + set RT4 "TimeQuest Timing Analyzer||Multicorner Timing Analysis Summary" + panel_to_csv $RT1 "$ProjectName.fit.timing.summary.fmax.csv" + panel_to_csv $RT2 "$ProjectName.fit.timing.summary.setup.csv" + panel_to_csv $RT3 "$ProjectName.fit.timing.summary.hold.csv" + panel_to_csv $RT4 "$ProjectName.fit.timing.summary.multicorner.csv" +} + +project_open $ProjectName +load_report + +# print available panels +#do_dump_panelnames + +# => allows comparison of raw logic vs impact of routing delays +if { $SynMode == "map" } { + do_map_analysis $ProjectName +# normal post-par analysis (includes routing congestion/physical placement constraints) +} else { + do_fit_analysis $ProjectName + do_fit_analysis_timingsummary $ProjectName +} + +unload_report +project_close \ No newline at end of file diff --git a/hw/syn/modelsim/vortex_dpi.h b/hw/syn/modelsim/vortex_dpi.h index 4a3509d0..165bb0b3 100644 --- a/hw/syn/modelsim/vortex_dpi.h +++ b/hw/syn/modelsim/vortex_dpi.h @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + extern "C" { void load_file (char * filename); diff --git a/hw/syn/modelsim/vortex_tb.v b/hw/syn/modelsim/vortex_tb.v index 38b4acad..6637f96f 100644 --- a/hw/syn/modelsim/vortex_tb.v +++ b/hw/syn/modelsim/vortex_tb.v @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `include "VX_define.vh" //`define NUM_BANKS 8 diff --git a/hw/syn/opae/.gitignore b/hw/syn/opae/.gitignore deleted file mode 100644 index 4ecaff7f..00000000 --- a/hw/syn/opae/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build_*/ \ No newline at end of file diff --git a/hw/syn/opae/Makefile b/hw/syn/opae/Makefile deleted file mode 100644 index 891ca1e4..00000000 --- a/hw/syn/opae/Makefile +++ /dev/null @@ -1,203 +0,0 @@ -DEVICE_FAMILY ?= arria10 -BUILD_DIR ?= build_$(DEVICE_FAMILY) -RTL_DIR=../../rtl - -ifeq ($(shell which qsub-synth),) - RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 & -else - RUN_SYNTH=qsub-synth -endif - -# control RTL debug tracing states -DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE -DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE -DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE -DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM -DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK -DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR -DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG -DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA -DBG_TRACE_FLAGS += -DDBG_TRACE_AFU -DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE -DBG_TRACE_FLAGS += -DDBG_TRACE_TEX - -DBG_FLAGS += $(DBG_TRACE_FLAGS) - -CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) -CONFIG2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) -CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS) -CONFIG8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS) -CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS) -CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS) -CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=524288 $(CONFIGS) - -FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY) -TEX_INCLUDE = -I$(RTL_DIR)/tex_unit -RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/afu $(FPU_INCLUDE) $(TEX_INCLUDE) - -CFLAGS += $(RTL_INCLUDE) - -# Debugigng -ifdef DEBUG - CFLAGS += $(DBG_FLAGS) -else - CFLAGS += -DNDEBUG -endif - -# Enable scope analyzer -ifdef SCOPE - CFLAGS += -DSCOPE -endif - -# Enable perf counters -ifdef PERF - CFLAGS += -DPERF_ENABLE -endif - -all: vortex_afu.h ase-1c - -# AFU info from JSON file, including AFU UUID -vortex_afu.h: vortex_afu.json - afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ - -$(BUILD_DIR)_ase_1c/Makefile: - afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_1c - -$(BUILD_DIR)_ase_2c/Makefile: - afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_2c - -$(BUILD_DIR)_ase_4c/Makefile: - afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_4c - -$(BUILD_DIR)_fpga_1c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_1c - -$(BUILD_DIR)_fpga_2c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_2c - -$(BUILD_DIR)_fpga_4c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_4c - -$(BUILD_DIR)_fpga_8c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_8c - -$(BUILD_DIR)_fpga_16c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_16c - -$(BUILD_DIR)_fpga_32c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_32c - -$(BUILD_DIR)_fpga_64c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(BUILD_DIR)_fpga_64c - -gen-sources-1c: - ./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt - -gen-sources-2c: - ./gen_sources.sh $(CFLAGS) $(CONFIG2) > sources.txt - -gen-sources-4c: - ./gen_sources.sh $(CFLAGS) $(CONFIG4) > sources.txt - -gen-sources-8c: - ./gen_sources.sh $(CFLAGS) $(CONFIG8) > sources.txt - -gen-sources-16c: - ./gen_sources.sh $(CFLAGS) $(CONFIG16) > sources.txt - -gen-sources-32c: - ./gen_sources.sh $(CFLAGS) $(CONFIG32) > sources.txt - -gen-sources-64c: - ./gen_sources.sh $(CFLAGS) $(CONFIG64) > sources.txt - -# setup - -setup-ase-1c: $(BUILD_DIR)_ase_1c/Makefile - -setup-ase-2c: $(BUILD_DIR)_ase_2c/Makefile - -setup-ase-4c: $(BUILD_DIR)_ase_4c/Makefile - -setup-fpga-1c: $(BUILD_DIR)_fpga_1c/build/dcp.qpf - -setup-fpga-2c: $(BUILD_DIR)_fpga_2c/build/dcp.qpf - -setup-fpga-4c: $(BUILD_DIR)_fpga_4c/build/dcp.qpf - -setup-fpga-8c: $(BUILD_DIR)_fpga_8c/build/dcp.qpf - -setup-fpga-16c: $(BUILD_DIR)_fpga_16c/build/dcp.qpf - -setup-fpga-32c: $(BUILD_DIR)_fpga_32c/build/dcp.qpf - -setup-fpga-64c: $(BUILD_DIR)_fpga_64c/build/dcp.qpf - -# build - -ase-1c: gen-sources-1c setup-ase-1c - make -C $(BUILD_DIR)_ase_1c - cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(BUILD_DIR)_ase_1c/work - -ase-2c: gen-sources-2c setup-ase-2c - make -C $(BUILD_DIR)_ase_2c - cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(BUILD_DIR)_ase_2c/work - -ase-4c: gen-sources-4c setup-ase-4c - make -C $(BUILD_DIR)_ase_4c - cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(BUILD_DIR)_ase_4c/work - -fpga-1c: gen-sources-1c setup-fpga-1c - cd $(BUILD_DIR)_fpga_1c && $(RUN_SYNTH) - -fpga-2c: gen-sources-2c setup-fpga-2c - cd $(BUILD_DIR)_fpga_2c && $(RUN_SYNTH) - -fpga-4c: gen-sources-4c setup-fpga-4c - cd $(BUILD_DIR)_fpga_4c && $(RUN_SYNTH) - -fpga-8c: gen-sources-8c setup-fpga-8c - cd $(BUILD_DIR)_fpga_8c && $(RUN_SYNTH) - -fpga-16c: gen-sources-16c setup-fpga-16c - cd $(BUILD_DIR)_fpga_16c && $(RUN_SYNTH) - -fpga-32c: gen-sources-32c setup-fpga-32c - cd $(BUILD_DIR)_fpga_32c && $(RUN_SYNTH) - -fpga-64c: gen-sources-64c setup-fpga-64c - cd $(BUILD_DIR)_fpga_64c && $(RUN_SYNTH) - -# cleanup - -clean-ase-1c: - rm -rf $(BUILD_DIR)_ase_1c sources.txt - -clean-ase-2c: - rm -rf $(BUILD_DIR)_ase_2c sources.txt - -clean-ase-4c: - rm -rf $(BUILD_DIR)_ase_4c sources.txt - -clean-fpga-1c: - rm -rf $(BUILD_DIR)_fpga_1c sources.txt - -clean-fpga-2c: - rm -rf $(BUILD_DIR)_fpga_2c sources.txt - -clean-fpga-4c: - rm -rf $(BUILD_DIR)_fpga_4c sources.txt - -clean-fpga-8c: - rm -rf $(BUILD_DIR)_fpga_8c sources.txt - -clean-fpga-16c: - rm -rf $(BUILD_DIR)_fpga_16c sources.txt - -clean-fpga-32c: - rm -rf $(BUILD_DIR)_fpga_32c sources.txt - -clean-fpga-64c: - rm -rf $(BUILD_DIR)_fpga_64c sources.txt - -clean: vortex_afu.h clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c clean-fpga-8c clean-fpga-16c clean-fpga-32c clean-fpga-64c \ No newline at end of file diff --git a/hw/syn/opae/README b/hw/syn/opae/README deleted file mode 100644 index 1c23b88f..00000000 --- a/hw/syn/opae/README +++ /dev/null @@ -1,92 +0,0 @@ -use the following step to build vortex and run it on fpga on intel cloud server using OPAE. -This script is also present at ~/dev/runVortex - -## To configure quartus and opae. Run this after logging in. -source /export/fpga/bin/setup-fpga-env fpga-pac-a10 -######################### -## Vortex Run commands ## -######################### - -# -## Synthesis -# - -cd /driver/hw/opae - -# Configure a Quartus build area -afu_synth_setup -s sources.txt build_fpga - -# Run Quartus in the vLab batch queue -cd build_fpga && qsub-synth - -# check last 10 lines in build log for possible errors -tail -n 10 ./build_fpga_1c/build.log - -# Check if the job is submitted to the queue and running. Status should be R -qstat | grep - -# Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C -watch ‘qstat | grep ’ - -# -## Executing on FPGA -# - -# From the build_fpga directory acquire a fpga node -qsub-fpga - -# Go to the directory whree qsub-synth was run above -cd $PBS_O_WORKDIR - -# Load the image onto an FPGA -fpgaconf vortex_afu.gbs - -# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port -fpgaconf --bus 0xaf vortex_afu.gbs - -# get portid -fpgainfo port - -# Running the Test case -cd /driver/tests/basic -make run-fpga - -# -## ASE build instructions -# -source /export/fpga/bin/setup-fpga-env fpga-pac-a10 - -# Acquire a sever node for running ASE simulations -qsub-sim - -# build -make ase - -# tests -./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t0 -./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t1 -./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n16 -./run_ase.sh build_arria10_ase_1c ../../../tests/regression/demo/demo -n16 -./run_ase.sh build_arria10_ase_1c ../../../tests/regression/dogfood/dogfood -n16 -./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/vecadd/vecadd -./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/sgemm/sgemm -n4 - -# modify "vsim_run.tcl" to dump VCD trace -vcd file trace.vcd -vcd add -r /*/Vortex/hw/rtl/* -run -all - -# compress FPGA output files -tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)` - -# compress log trace -tar -zcvf run.log.tar.gz run.log -tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log -tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/work/run.log build_arria10_ase_1c/work/trace.vcd - -# decompress log trace -tar -zxvf vortex.vcd.tar.gz -tar -xvf vortex.vcd.tar.bz2 - -# quick off synthesis -make core \ No newline at end of file diff --git a/hw/syn/opae/fpga_prog.sh b/hw/syn/opae/fpga_prog.sh deleted file mode 100755 index 4fc9db22..00000000 --- a/hw/syn/opae/fpga_prog.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/bash - -# FPGA programming -# first argument is the bitstream - -echo "fpgaconf --bus 0xaf $1" -fpgaconf --bus 0xaf $1 \ No newline at end of file diff --git a/hw/syn/opae/gen_sources.sh b/hw/syn/opae/gen_sources.sh deleted file mode 100755 index a320f53a..00000000 --- a/hw/syn/opae/gen_sources.sh +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/bash - -exclude_list="VX_fpu_fpnew.sv" -macros=() -includes=() - -# parse command arguments -while getopts D:I:h flag -do - case "${flag}" in - D) macros+=( ${OPTARG} );; - I) includes+=( ${OPTARG} );; - h) echo "Usage: [-D macro] [-I include] [-h help]" - exit 0 - ;; - \?) - echo "Invalid option: -$OPTARG" 1>&2 - exit 1 - ;; - esac -done - -# dump macros -for value in ${macros[@]}; do - echo "+define+$value" -done - -# dump include directories -for dir in ${includes[@]}; do - echo "+incdir+$dir" -done - -# dump source files -for dir in ${includes[@]}; do - for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do - exclude=0 - for fe in $exclude_list; do - if [[ $file =~ $fe ]]; then - exclude=1 - fi - done - if [[ $exclude == 0 ]]; then - echo $file - fi - done -done \ No newline at end of file diff --git a/hw/syn/opae/setup.cfg b/hw/syn/opae/setup.cfg deleted file mode 100644 index 9bb0b72d..00000000 --- a/hw/syn/opae/setup.cfg +++ /dev/null @@ -1,7 +0,0 @@ -+define+SYNTHESIS -+define+QUARTUS - -vortex_afu.json -QI:vortex_afu.qsf - -C:sources.txt \ No newline at end of file diff --git a/hw/syn/quartus/.gitignore b/hw/syn/quartus/.gitignore deleted file mode 100644 index 4b27eaab..00000000 --- a/hw/syn/quartus/.gitignore +++ /dev/null @@ -1,41 +0,0 @@ -/unittest/* -!/unittest/Makefile - -/smem/* -!/smem/Makefile - -/cache/* -!/cache/Makefile - -/fpu_core/* -!/fpu_core/Makefile - -/vortex/* -!/vortex/Makefile - -/pipeline/* -!/pipeline/Makefile - -/core/* -!/core/Makefile - -/top1/* -!/top1/Makefile - -/top2/* -!/top2/Makefile - -/top4/* -!/top4/Makefile - -/top8/* -!/top8/Makefile - -/top16/* -!/top16/Makefile - -/top32/* -!/top32/Makefile - -/top64/* -!/top64/Makefile \ No newline at end of file diff --git a/hw/syn/quartus/Makefile b/hw/syn/quartus/Makefile deleted file mode 100644 index 1dd63335..00000000 --- a/hw/syn/quartus/Makefile +++ /dev/null @@ -1,83 +0,0 @@ -BUILD_DIR ?= build - -.PHONY: dogfood unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64 texunit - -dogfood: - mkdir -p dogfood/$(BUILD_DIR) - cp dogfood/Makefile dogfood/$(BUILD_DIR) - $(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 & - -unittest: - mkdir -p unittest/$(BUILD_DIR) - cp unittest/Makefile unittest/$(BUILD_DIR) - $(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 & - -pipeline: - mkdir -p pipeline/$(BUILD_DIR) - cp pipeline/Makefile pipeline/$(BUILD_DIR) - $(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 & - -smem: - mkdir -p smem/$(BUILD_DIR) - cp smem/Makefile smem/$(BUILD_DIR) - $(MAKE) -C smem/$(BUILD_DIR) clean && $(MAKE) -C smem/$(BUILD_DIR) > smem/$(BUILD_DIR)/build.log 2>&1 & - -cache: - mkdir -p cache/$(BUILD_DIR) - cp cache/Makefile cache/$(BUILD_DIR) - $(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 & - -fpu_core: - mkdir -p fpu_core/$(BUILD_DIR) - cp fpu_core/Makefile fpu_core/$(BUILD_DIR) - $(MAKE) -C fpu_core/$(BUILD_DIR) clean && $(MAKE) -C fpu_core/$(BUILD_DIR) > fpu_core/$(BUILD_DIR)/build.log 2>&1 & - -core: - mkdir -p core/$(BUILD_DIR) - cp core/Makefile core/$(BUILD_DIR) - $(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 & - -vortex: - mkdir -p vortex/$(BUILD_DIR) - cp vortex/Makefile vortex/$(BUILD_DIR) - $(MAKE) -C vortex/$(BUILD_DIR) clean && $(MAKE) -C vortex/$(BUILD_DIR) > vortex/$(BUILD_DIR)/build.log 2>&1 & - -top1: - mkdir -p top1/$(BUILD_DIR) - cp top1/Makefile top1/$(BUILD_DIR) - $(MAKE) -C top1/$(BUILD_DIR) clean && $(MAKE) -C top1/$(BUILD_DIR) > top1/$(BUILD_DIR)/build.log 2>&1 & - -top2: - mkdir -p top2/$(BUILD_DIR) - cp top2/Makefile top2/$(BUILD_DIR) - $(MAKE) -C top2/$(BUILD_DIR) clean && $(MAKE) -C top2/$(BUILD_DIR) > top2/$(BUILD_DIR)/build.log 2>&1 & - -top4: - mkdir -p top4/$(BUILD_DIR) - cp top4/Makefile top4/$(BUILD_DIR) - $(MAKE) -C top4/$(BUILD_DIR) clean && $(MAKE) -C top4/$(BUILD_DIR) > top4/$(BUILD_DIR)/build.log 2>&1 & - -top8: - mkdir -p top8/$(BUILD_DIR) - cp top8/Makefile top8/$(BUILD_DIR) - $(MAKE) -C top8/$(BUILD_DIR) clean && $(MAKE) -C top8/$(BUILD_DIR) > top8/$(BUILD_DIR)/build.log 2>&1 & - -top16: - mkdir -p top16/$(BUILD_DIR) - cp top16/Makefile top16/$(BUILD_DIR) - $(MAKE) -C top16/$(BUILD_DIR) clean && $(MAKE) -C top16/$(BUILD_DIR) > top16/$(BUILD_DIR)/build.log 2>&1 & - -top32: - mkdir -p top32/$(BUILD_DIR) - cp top32/Makefile top32/$(BUILD_DIR) - $(MAKE) -C top32/$(BUILD_DIR) clean && $(MAKE) -C top32/$(BUILD_DIR) > top32/$(BUILD_DIR)/build.log 2>&1 & - -top64: - mkdir -p top64/$(BUILD_DIR) - cp top64/Makefile top64/$(BUILD_DIR) - $(MAKE) -C top64/$(BUILD_DIR) clean && $(MAKE) -C top64/$(BUILD_DIR) > top64/$(BUILD_DIR)/build.log 2>&1 & - -texunit: - mkdir -p texunit/$(BUILD_DIR) - cp texunit/Makefile texunit/$(BUILD_DIR) - $(MAKE) -C texunit/$(BUILD_DIR) clean && $(MAKE) -C texunit/$(BUILD_DIR) > texunit/$(BUILD_DIR)/build.log 2>&1 & \ No newline at end of file diff --git a/hw/syn/quartus/cache/Makefile b/hw/syn/quartus/cache/Makefile deleted file mode 100755 index d28d9b18..00000000 --- a/hw/syn/quartus/cache/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -PROJECT = VX_cache -TOP_LEVEL_ENTITY = VX_cache -SRC_FILE = VX_cache.v -RTL_DIR = ../../../../rtl - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/core/Makefile b/hw/syn/quartus/core/Makefile deleted file mode 100644 index d209c80d..00000000 --- a/hw/syn/quartus/core/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = Core -TOP_LEVEL_ENTITY = VX_core -SRC_FILE = VX_core.v -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/fpu_core/Makefile b/hw/syn/quartus/fpu_core/Makefile deleted file mode 100644 index 26ca51ac..00000000 --- a/hw/syn/quartus/fpu_core/Makefile +++ /dev/null @@ -1,87 +0,0 @@ -PROJECT = VX_fpu_fpga -TOP_LEVEL_ENTITY = VX_fpu_fpga -SRC_FILE = VX_fpu_fpga.v -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Part, Family -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -# -set "FPU_CVT2" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -timing: $(PROJECT_FILES) - quartus_sh -t ../../timing-html.tcl -project $(PROJECT) - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile deleted file mode 100644 index 665f7829..00000000 --- a/hw/syn/quartus/pipeline/Makefile +++ /dev/null @@ -1,86 +0,0 @@ -PROJECT = VX_pipeline -TOP_LEVEL_ENTITY = VX_pipeline -SRC_FILE = VX_pipeline.v -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -timing: $(PROJECT_FILES) - quartus_sh -t ../../timing-html.tcl -project $(PROJECT) - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/project.sdc b/hw/syn/quartus/project.sdc deleted file mode 100644 index 797606f7..00000000 --- a/hw/syn/quartus/project.sdc +++ /dev/null @@ -1,4 +0,0 @@ -create_clock -name {clk} -period "250 MHz" [get_ports {clk}] - -derive_pll_clocks -create_base_clocks -derive_clock_uncertainty \ No newline at end of file diff --git a/hw/syn/quartus/smem/Makefile b/hw/syn/quartus/smem/Makefile deleted file mode 100755 index 3b0c0872..00000000 --- a/hw/syn/quartus/smem/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -PROJECT = VX_shared_mem -TOP_LEVEL_ENTITY = VX_shared_mem -SRC_FILE = VX_shared_mem.v -RTL_DIR = ../../../../rtl - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/texunit/Makefile b/hw/syn/quartus/texunit/Makefile deleted file mode 100644 index 3ecfa892..00000000 --- a/hw/syn/quartus/texunit/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = Core -TOP_LEVEL_ENTITY = VX_core -SRC_FILE = VX_core.v -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "EXT_TEX_ENABLE=1" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top1/Makefile b/hw/syn/quartus/top1/Makefile deleted file mode 100644 index 9494b2d3..00000000 --- a/hw/syn/quartus/top1/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = vortex_afu -TOP_LEVEL_ENTITY = vortex_afu -SRC_FILE = vortex_afu.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=1" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top16/Makefile b/hw/syn/quartus/top16/Makefile deleted file mode 100644 index 836e3558..00000000 --- a/hw/syn/quartus/top16/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = vortex_afu -TOP_LEVEL_ENTITY = vortex_afu -SRC_FILE = vortex_afu.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=262144" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top2/Makefile b/hw/syn/quartus/top2/Makefile deleted file mode 100644 index d4c6abbc..00000000 --- a/hw/syn/quartus/top2/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = vortex_afu -TOP_LEVEL_ENTITY = vortex_afu -SRC_FILE = vortex_afu.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=2" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top32/Makefile b/hw/syn/quartus/top32/Makefile deleted file mode 100644 index d07a515c..00000000 --- a/hw/syn/quartus/top32/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = vortex_afu -TOP_LEVEL_ENTITY = vortex_afu -SRC_FILE = vortex_afu.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=4" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=262144" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top4/Makefile b/hw/syn/quartus/top4/Makefile deleted file mode 100644 index af33661c..00000000 --- a/hw/syn/quartus/top4/Makefile +++ /dev/null @@ -1,80 +0,0 @@ -PROJECT = vortex_afu -TOP_LEVEL_ENTITY = vortex_afu -SRC_FILE = vortex_afu.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=1" -set "L2_ENABLE=1" -set "L3_ENABLE=0" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L2_CACHE_SIZE=65536" -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top64/Makefile b/hw/syn/quartus/top64/Makefile deleted file mode 100644 index 1d60b214..00000000 --- a/hw/syn/quartus/top64/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = vortex_afu -TOP_LEVEL_ENTITY = vortex_afu -SRC_FILE = vortex_afu.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -#FAMILY = "Arria 10" -#DEVICE = 10AX115N3F40E2SG -#FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10 - -FAMILY = "Stratix 10" -DEVICE = 1SX280HN2F43E2VG -FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8" -set "L2_ENABLE=0" -set "L3_ENABLE=1" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L3_CACHE_SIZE=524288" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top8/Makefile b/hw/syn/quartus/top8/Makefile deleted file mode 100644 index b2efcc6d..00000000 --- a/hw/syn/quartus/top8/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = vortex_afu -TOP_LEVEL_ENTITY = vortex_afu -SRC_FILE = vortex_afu.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=1" -set "L2_ENABLE=1" -set "L3_ENABLE=0" -set "ICACHE_SIZE=8192" -set "DCACHE_SIZE=8192" -set "L2_CACHE_SIZE=131072" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/unittest/Makefile b/hw/syn/quartus/unittest/Makefile deleted file mode 100644 index 975ec0a1..00000000 --- a/hw/syn/quartus/unittest/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = Unittest -TOP_LEVEL_ENTITY = VX_core_req_bank_sel -SRC_FILE = VX_core_req_bank_sel.v -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile deleted file mode 100644 index b2046cf8..00000000 --- a/hw/syn/quartus/vortex/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -PROJECT = Vortex -TOP_LEVEL_ENTITY = Vortex -SRC_FILE = Vortex.sv -RTL_DIR = ../../../../rtl -THIRD_PARTY_DIR = ../../../../../third_party - -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG -FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10 - -#FAMILY = "Stratix 10" -#DEVICE = 1SX280HN2F43E2VG -#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10 - -FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -TEX_INCLUDE = $(RTL_DIR)/tex_unit -RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE) - -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --parallel --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/synopsys/fsyn.tcl b/hw/syn/synopsys/fsyn.tcl index b6c30524..02888dcf 100644 --- a/hw/syn/synopsys/fsyn.tcl +++ b/hw/syn/synopsys/fsyn.tcl @@ -1,3 +1,16 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + set search_path [concat ../../models/memory/cln28hpm/rf2_128x128_wm1 ../../models/memory/cln28hpm/rf2_256x128_wm1 ../../models/memory/cln28hpm/rf2_256_19_wm0 ../../models/memory/cln28hpm/rf2_32x128_wm1 ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache] set link_library [concat NanGate_15nm_OCL.db] set symbol_library {} diff --git a/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp index ac1ac49d..da94f5fb 100644 --- a/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp +++ b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include "Vrf2_32x128_wm1_rtl.h" diff --git a/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v index 8f0132cb..0413ff95 100644 --- a/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v +++ b/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `timescale 1ns/1ps diff --git a/hw/syn/synopsys/models/memory/cln28hpm/convert_lib_to_db.tcl b/hw/syn/synopsys/models/memory/cln28hpm/convert_lib_to_db.tcl index 3b4bddea..47ec9e53 100755 --- a/hw/syn/synopsys/models/memory/cln28hpm/convert_lib_to_db.tcl +++ b/hw/syn/synopsys/models/memory/cln28hpm/convert_lib_to_db.tcl @@ -1,3 +1,16 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + set SOURCE_FILES [glob *.lib] foreach FILE ${SOURCE_FILES} { read_lib $FILE diff --git a/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v index 105cc840..b2c38ea4 100644 --- a/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v +++ b/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `timescale 1ns/1ps diff --git a/hw/syn/synopsys/run_mult_synth.sh b/hw/syn/synopsys/run_mult_synth.sh index 38a32f9a..7ebacbf0 100644 --- a/hw/syn/synopsys/run_mult_synth.sh +++ b/hw/syn/synopsys/run_mult_synth.sh @@ -1,4 +1,18 @@ #!/bin/bash + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + set top_level = Vortex source /tools/synopsys/synthesis/j201409/cshrc.syn diff --git a/hw/syn/synopsys/syn.tcl b/hw/syn/synopsys/syn.tcl index 951adaa8..5726d41c 100755 --- a/hw/syn/synopsys/syn.tcl +++ b/hw/syn/synopsys/syn.tcl @@ -1,3 +1,16 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db] set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb] set symbol_library {} diff --git a/hw/syn/xilinx/NOTEBOOK b/hw/syn/xilinx/NOTEBOOK new file mode 100644 index 00000000..aa854eb8 --- /dev/null +++ b/hw/syn/xilinx/NOTEBOOK @@ -0,0 +1,73 @@ +## Xilinx synthesis Notebook + +# check installed FPGAs +platforminfo -l + +# check FPGA status +xbutil validate --device 0000:09:00.1 --verbose + +# generate FPU IPs +vivado -mode batch -source scripts/gen_ip.tcl -tclargs ip/xilinx_u50_gen3x16_xdma_5_202210_1 + +# build FPGA +PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_1c.log 2>&1 & +PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_base_1c.log 2>&1 & + +PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_1c.log 2>&1 & +PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_1c.log 2>&1 & + +PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_dbg_1c.log 2>&1 & +PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_dbg_1c.log 2>&1 & + +PREFIX=build_base_2c NUM_CORES=2 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_2c.log 2>&1 & +PREFIX=build_base_2c NUM_CORES=2 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_base_2c.log 2>&1 & + +PREFIX=build_gfx_2c NUM_CORES=2 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_emu_gfx_2c.log 2>&1 & +PREFIX=build_gfx_2c NUM_CORES=2 TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u50_hw_gfx_2c.log 2>&1 & + +PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_emu_gfx_dbg_1c.log 2>&1 & +PREFIX=build_gfx_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_gfx_dbg_1c.log 2>&1 & +PREFIX=build_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_emu_dbg_1c.log 2>&1 & +PREFIX=build_dbg_1c DEBUG=3 NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_dbg_1c.log 2>&1 & +PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_emu_base_1c.log 2>&1 & +PREFIX=build_base_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 make > build_u280_hw_base_1c.log 2>&1 & +PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_emu_gfx_1c.log 2>&1 & +PREFIX=build_gfx_1c NUM_CORES=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 CONFIGS="-DEXT_GFX_ENABLE" make > build_u280_hw_gfx_1c.log 2>&1 & + +PREFIX=build TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 make > build_vck5k_hw_emu.log 2>&1 & +PREFIX=build TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 make > build_vck5k_hw.log 2>&1 & + +# debug hw_emu using xsim +xsim --gui xilinx_u50_gen3x16_xdma_5_202210_1-0-vortex_afu.wdb & + +# debug hw using ILA +platforminfo --json="hardwarePlatform.extensions.chipscope_debug" xilinx_u50_gen3x16_xdma_5_202210_1 +ls /dev/xfpga/xvc_pub* +ls /dev/xvc_pub* +debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server +debug_hw --xvc_pcie /dev/xvc_pub.u0 --hw_server +debug_hw --vivado --host localhost --ltx_file ./build_xilinx_u50_gen3x16_xdma_5_202210_1_hw/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx & +make chipscope TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 + +# analyze build report +vitis_analyzer build_xilinx_u50_gen3x16_xdma_5_202210_1_hw_4c/bin/vortex_afu.xclbin.link_summary + +# running test +TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo +TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo +TARGET=hw PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo +TARGET=hw_emu PLATFORM=xilinx_vck5000_gen3x16_xdma_1_202120_1 ./ci/blackbox.sh --driver=xrt --app=demo +FPGA_BIN_DIR= TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo +FPGA_BIN_DIR= TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=demo +FPGA_BIN_DIR= TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png" +FPGA_BIN_DIR= TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png" +FPGA_BIN_DIR= TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=demo +FPGA_BIN_DIR= XRT_DEVICE_INDEX=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=demo +FPGA_BIN_DIR= TARGET=hw_emu PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png" +FPGA_BIN_DIR= XRT_DEVICE_INDEX=1 TARGET=hw PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1 ./ci/blackbox.sh --driver=xrt --app=draw3d --args="-tbox.cgltrace -rbox_ref_128.png" + +# build report logs +/bin/vortex_afu.xclbin.info +/_x/reports/link/link/imp/impl_1_full_util_routed.rpt +/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt # search for keyword "VIOLATED" +/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log diff --git a/hw/syn/xilinx/test/.gitignore b/hw/syn/xilinx/test/.gitignore new file mode 100644 index 00000000..a1a8316c --- /dev/null +++ b/hw/syn/xilinx/test/.gitignore @@ -0,0 +1,2 @@ +/project_1/* +/.Xil/* \ No newline at end of file diff --git a/hw/syn/xilinx/test/Makefile b/hw/syn/xilinx/test/Makefile new file mode 100644 index 00000000..66d9a998 --- /dev/null +++ b/hw/syn/xilinx/test/Makefile @@ -0,0 +1,49 @@ +VIVADO = $(XILINX_VIVADO)/bin/vivado + +RTL_DIR = ../../../rtl +AFU_DIR = $(RTL_DIR)/afu/xrt +SCRIPT_DIR = ../../../scripts +THIRD_PARTY_DIR = ../../../../third_party + +# include paths +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache +RTL_INCLUDE += $(FPU_INCLUDE) +RTL_INCLUDE += -Iproject_1_files + +# compilation flags +CFLAGS += -DNDEBUG -DSYNTHESIS -DVIVADO +CFLAGS += $(CONFIGS) +CFLAGS += $(RTL_INCLUDE) +CFLAGS += -DEXT_F_DISABLE +#CFLAGS += -DNUM_CORES 4 + +# update memory layout for 2MB RAM +CFLAGS += -DSTARTUP_ADDR=32\'h80000 +CFLAGS += -DIO_BASE_ADDR=32\'hFF000 + +COE_FILE := $(realpath project_1_files)/kernel.bin.coe +ESCAPED_COE_FILE := $(shell echo "$(COE_FILE)" | sed -e 's/[\/&]/\\&/g') + +all: build + +gen-sources: project_1/sources.txt +project_1/sources.txt: + mkdir -p project_1 + $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -Cproject_1/src -Oproject_1/sources.txt + +project.tcl: project.tcl.in + sed -e 's/%COE_FILE%/$(ESCAPED_COE_FILE)/g' < $< > $@ + +build: project_1/vortex.xpr +project_1/vortex.xpr: project_1/sources.txt project.tcl + $(VIVADO) -mode batch -source project.tcl -tclargs project_1/sources.txt project_1/src $(SCRIPT_DIR) + +run: project_1/vortex.xpr + $(VIVADO) project_1/vortex.xpr & + +clean: + rm -rf project_1 project.tcl diff --git a/hw/syn/xilinx/test/kernel/Makefile b/hw/syn/xilinx/test/kernel/Makefile new file mode 100644 index 00000000..55c21aa2 --- /dev/null +++ b/hw/syn/xilinx/test/kernel/Makefile @@ -0,0 +1,51 @@ +XLEN ?= 32 + +ifeq ($(XLEN),64) +RISCV_TOOLCHAIN_PATH ?= /opt/riscv64-gnu-toolchain +CFLAGS += -march=rv64imafd -mabi=lp64d +else +RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain +CFLAGS += -march=rv32imaf -mabi=ilp32f +endif + +RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf + +VORTEX_RT_PATH ?= $(realpath ../../../../../kernel) +BIN2COE_PATH ?= ../../../../../../bin2coe + +CC = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc +AR = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc-ar +DP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objdump +CP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objcopy + +CFLAGS += -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections +CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw + +LDFLAGS += -lm -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link$(XLEN).ld,--defsym=STARTUP_ADDR=0x80000000 + +PROJECT = kernel + +SRCS = main.c start.S + +all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dump $(PROJECT).bin.coe + +$(PROJECT).dump: $(PROJECT).elf + $(DP) -D $(PROJECT).elf > $(PROJECT).dump + +$(PROJECT).hex: $(PROJECT).elf + $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex + +$(PROJECT).bin: $(PROJECT).elf + $(CP) -O binary $(PROJECT).elf $(PROJECT).bin + +$(PROJECT).bin.coe: $(PROJECT).bin + $(BIN2COE_PATH)/bin2coe $(PROJECT).bin --out=$(PROJECT).bin.coe --binary=$(PROJECT).bin --data=$(PROJECT).dat --binaddr=8192 --depth=16384 --wordsize=64 + +$(PROJECT).elf: $(SRCS) + $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf + +.depend: $(SRCS) + $(CC) $(CFLAGS) -MM $^ > .depend; + +clean: + rm -rf *.bin *.elf *.hex *.dump *.coe .depend diff --git a/hw/syn/xilinx/test/kernel/kernel.dat b/hw/syn/xilinx/test/kernel/kernel.dat new file mode 100644 index 00000000..6e197b71 --- /dev/null +++ b/hw/syn/xilinx/test/kernel/kernel.dat @@ -0,0 +1,3 @@ +@1 +000000C00000008000000002, +00000003000000020000000100000000, \ No newline at end of file diff --git a/hw/syn/xilinx/test/kernel/main.c b/hw/syn/xilinx/test/kernel/main.c new file mode 100644 index 00000000..e448ce35 --- /dev/null +++ b/hw/syn/xilinx/test/kernel/main.c @@ -0,0 +1,38 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +#define KERNEL_ARG_DEV_MEM_ADDR 0x40 + +typedef struct { + uint32_t count; + uint32_t src_addr; + uint32_t dst_addr; +} kernel_arg_t; + +int main() { + kernel_arg_t* arg = (kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + uint32_t count = arg->count; + int32_t* src_ptr = (int32_t*)arg->src_addr; + int32_t* dst_ptr = (int32_t*)arg->dst_addr; + + uint32_t offset = vx_core_id() * count; + + for (uint32_t i = 0; i < count; ++i) { + dst_ptr[offset + i] = src_ptr[offset + i]; + } + + return 0; +} diff --git a/hw/syn/xilinx/test/kernel/start.S b/hw/syn/xilinx/test/kernel/start.S new file mode 100644 index 00000000..e9295d64 --- /dev/null +++ b/hw/syn/xilinx/test/kernel/start.S @@ -0,0 +1,23 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +.section .init, "ax" +.global _start +.type _start, @function +_start: + # call main routine + call main + + # end execution + .insn r 0x0b, 0, 0, x0, x0, x0 +.size _start, .-_start \ No newline at end of file diff --git a/hw/syn/xilinx/test/project.tcl.in b/hw/syn/xilinx/test/project.tcl.in new file mode 100644 index 00000000..a2692f63 --- /dev/null +++ b/hw/syn/xilinx/test/project.tcl.in @@ -0,0 +1,2228 @@ +if { $::argc != 3 } { + puts "ERROR: Program \"$::argv0\" requires 3 arguments!\n" + puts "Usage: $::argv0 \n" + exit +} + +set vcs_file [lindex $::argv 0] +set files_dir [lindex $::argv 1] +set tool_dir [lindex $::argv 2] + +#puts $vcs_file +#puts $files_dir +#puts $tool_dir + +set origin_dir [file normalize "."] + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set project_name "project_1" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set project_name $::user_project_name +} + +source "${tool_dir}/parse_vcs_list.tcl" +set vlist [parse_vcs_list "${vcs_file}"] + +set vsources_list [lindex $vlist 0] +set vincludes_list [lindex $vlist 1] +set vdefines_list [lindex $vlist 2] + +#puts ${vsources_list} +#puts ${vincludes_list} +#puts ${vdefines_list} + +# Create project +create_project ${project_name} ./${project_name} -force -part xcu280-fsvh2892-2L-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "xilinx.com:au280:part0:1.1" -objects $obj +set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj +set_property -name "compxlib.funcsim" -value "1" -objects $obj +set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj +set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/modelsim" -objects $obj +set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj +set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/questa" -objects $obj +set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/riviera" -objects $obj +set_property -name "compxlib.timesim" -value "1" -objects $obj +set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/vcs" -objects $obj +set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj +set_property -name "corecontainer.enable" -value "0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_optional_runs_sta" -value "0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_interface_inference_priority" -value "" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj +set_property -name "legacy_ip_repo_paths" -value "" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "platform.board_id" -value "au280" -objects $obj +set_property -name "platform.default_output_type" -value "undefined" -objects $obj +set_property -name "platform.design_intent.datacenter" -value "undefined" -objects $obj +set_property -name "platform.design_intent.embedded" -value "undefined" -objects $obj +set_property -name "platform.design_intent.external_host" -value "undefined" -objects $obj +set_property -name "platform.design_intent.server_managed" -value "undefined" -objects $obj +set_property -name "platform.rom.debug_type" -value "0" -objects $obj +set_property -name "platform.rom.prom_type" -value "0" -objects $obj +set_property -name "platform.slrconstraintmode" -value "0" -objects $obj +set_property -name "preferred_sim_model" -value "rtl" -objects $obj +set_property -name "project_type" -value "Default" -objects $obj +set_property -name "pr_flow" -value "0" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${project_name}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj +set_property -name "simulator.activehdl_gcc_install_dir" -value "" -objects $obj +set_property -name "simulator.activehdl_install_dir" -value "" -objects $obj +set_property -name "simulator.ies_gcc_install_dir" -value "" -objects $obj +set_property -name "simulator.ies_install_dir" -value "" -objects $obj +set_property -name "simulator.modelsim_gcc_install_dir" -value "" -objects $obj +set_property -name "simulator.modelsim_install_dir" -value "" -objects $obj +set_property -name "simulator.questa_gcc_install_dir" -value "" -objects $obj +set_property -name "simulator.riviera_gcc_install_dir" -value "" -objects $obj +set_property -name "simulator.riviera_install_dir" -value "" -objects $obj +set_property -name "simulator.vcs_gcc_install_dir" -value "" -objects $obj +set_property -name "simulator.vcs_install_dir" -value "" -objects $obj +set_property -name "simulator.xcelium_gcc_install_dir" -value "" -objects $obj +set_property -name "simulator.xcelium_install_dir" -value "" -objects $obj +set_property -name "simulator_language" -value "Verilog" -objects $obj +set_property -name "source_mgmt_mode" -value "All" -objects $obj +set_property -name "target_language" -value "Verilog" -objects $obj +set_property -name "target_simulator" -value "XSim" -objects $obj +set_property -name "tool_flow" -value "Vivado" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "27" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "27" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "27" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "27" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "27" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "27" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "5" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "27" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "91" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj +set_property -name "xsim.array_display_limit" -value "1024" -objects $obj +set_property -name "xsim.radix" -value "hex" -objects $obj +set_property -name "xsim.time_unit" -value "ns" -objects $obj +set_property -name "xsim.trace_limit" -value "65536" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# add source files +set obj [get_filesets sources_1] +add_files -norecurse -verbose -fileset $obj ${vsources_list} + +# process defines +set obj [get_filesets sources_1] +foreach def $vdefines_list { + set_property -name "verilog_define" -value $def -objects $obj +} + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "design_mode" -value "RTL" -objects $obj +set_property -name "edif_extra_search_paths" -value "" -objects $obj +set_property -name "elab_link_dcps" -value "1" -objects $obj +set_property -name "elab_load_timing_constraints" -value "1" -objects $obj +set_property -name "generic" -value "" -objects $obj +set_property -name "include_dirs" -value "" -objects $obj +set_property -name "lib_map_file" -value "" -objects $obj +set_property -name "loop_count" -value "1000" -objects $obj +set_property -name "name" -value "sources_1" -objects $obj +set_property -name "top" -value "design_1_wrapper" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "verilog_define" -value "" -objects $obj +set_property -name "verilog_uppercase" -value "1" -objects $obj +set_property -name "verilog_version" -value "verilog_2001" -objects $obj +set_property -name "vhdl_version" -value "vhdl_2k" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "constrs_type" -value "XDC" -objects $obj +set_property -name "name" -value "constrs_1" -objects $obj +set_property -name "target_constrs_file" -value "" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Import local files from the original project +set files [list \ + [file normalize "$files_dir/testbench.v" ]\ +] +set imported_files [import_files -fileset sim_1 $files] + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +set file "testbench.v" +set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] +set_property -name "file_type" -value "Verilog" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_simulation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "32bit" -value "0" -objects $obj +set_property -name "force_compile_glbl" -value "0" -objects $obj +set_property -name "generate_scripts_only" -value "0" -objects $obj +set_property -name "generic" -value "" -objects $obj +set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj +set_property -name "include_dirs" -value "" -objects $obj +set_property -name "incremental" -value "1" -objects $obj +set_property -name "name" -value "sim_1" -objects $obj +set_property -name "nl.cell" -value "" -objects $obj +set_property -name "nl.incl_unisim_models" -value "0" -objects $obj +set_property -name "nl.mode" -value "funcsim" -objects $obj +set_property -name "nl.process_corner" -value "slow" -objects $obj +set_property -name "nl.rename_top" -value "" -objects $obj +set_property -name "nl.sdf_anno" -value "1" -objects $obj +set_property -name "nl.write_all_overrides" -value "0" -objects $obj +set_property -name "source_set" -value "sources_1" -objects $obj +set_property -name "systemc_include_dirs" -value "" -objects $obj +set_property -name "top" -value "testbench" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "transport_int_delay" -value "0" -objects $obj +set_property -name "transport_path_delay" -value "0" -objects $obj +set_property -name "unifast" -value "0" -objects $obj +set_property -name "verilog_define" -value "" -objects $obj +set_property -name "verilog_uppercase" -value "0" -objects $obj +set_property -name "xelab.dll" -value "0" -objects $obj +set_property -name "xsim.compile.tcl.pre" -value "" -objects $obj +set_property -name "xsim.compile.xsc.more_options" -value "" -objects $obj +set_property -name "xsim.compile.xvhdl.more_options" -value "" -objects $obj +set_property -name "xsim.compile.xvhdl.nosort" -value "1" -objects $obj +set_property -name "xsim.compile.xvhdl.relax" -value "1" -objects $obj +set_property -name "xsim.compile.xvlog.more_options" -value "" -objects $obj +set_property -name "xsim.compile.xvlog.nosort" -value "1" -objects $obj +set_property -name "xsim.compile.xvlog.relax" -value "1" -objects $obj +set_property -name "xsim.elaborate.debug_level" -value "typical" -objects $obj +set_property -name "xsim.elaborate.load_glbl" -value "1" -objects $obj +set_property -name "xsim.elaborate.mt_level" -value "auto" -objects $obj +set_property -name "xsim.elaborate.rangecheck" -value "0" -objects $obj +set_property -name "xsim.elaborate.relax" -value "1" -objects $obj +set_property -name "xsim.elaborate.sdf_delay" -value "sdfmax" -objects $obj +set_property -name "xsim.elaborate.snapshot" -value "" -objects $obj +set_property -name "xsim.elaborate.xelab.more_options" -value "" -objects $obj +set_property -name "xsim.elaborate.xsc.more_options" -value "" -objects $obj +set_property -name "xsim.simulate.add_positional" -value "0" -objects $obj +set_property -name "xsim.simulate.custom_tcl" -value "" -objects $obj +set_property -name "xsim.simulate.log_all_signals" -value "0" -objects $obj +set_property -name "xsim.simulate.no_quit" -value "0" -objects $obj +set_property -name "xsim.simulate.runtime" -value "4000ns" -objects $obj +set_property -name "xsim.simulate.saif" -value "" -objects $obj +set_property -name "xsim.simulate.saif_all_signals" -value "0" -objects $obj +set_property -name "xsim.simulate.saif_scope" -value "" -objects $obj +set_property -name "xsim.simulate.tcl.post" -value "" -objects $obj +set_property -name "xsim.simulate.wdb" -value "" -objects $obj +set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] +set_property -name "name" -value "utils_1" -objects $obj + +# Proc to create BD design_1 +proc cr_bd_design_1 { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# Vortex_top + +# CHANGE DESIGN NAME HERE +set design_name design_1 + +common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + +create_bd_design $design_name + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:axi_bram_ctrl:4.1\ + xilinx.com:ip:blk_mem_gen:8.4\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + Vortex_top\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +variable script_folder + +if { $parentCell eq "" } { + set parentCell [get_bd_cells /] +} + +# Get object for parentCell +set parentObj [get_bd_cells $parentCell] +if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return +} + +# Make sure parentObj is hier blk +set parentType [get_property TYPE $parentObj] +if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return +} + +# Save current instance; Restore later +set oldCurInst [current_bd_instance .] + +# Set parent object as current +current_bd_instance $parentObj + + +# Create interface ports + +# Create ports +set clk_100MHz [ create_bd_port -dir I -type clk -freq_hz 100000000 clk_100MHz ] +set resetn [ create_bd_port -dir I -type rst resetn ] +set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ +] $resetn +set vx_busy [ create_bd_port -dir O vx_busy ] +set vx_reset [ create_bd_port -dir I -type rst vx_reset ] +set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ +] $vx_reset + +set dcr_wr_valid [ create_bd_port -dir I dcr_wr_valid ] +set dcr_wr_addr [ create_bd_port -dir I -from 11 -to 0 dcr_wr_addr ] +set dcr_wr_data [ create_bd_port -dir I -from 31 -to 0 dcr_wr_data ] + +# Create instance: Vortex_top_0, and set properties +set block_name Vortex_top +set block_cell_name Vortex_top_0 +if { [catch {set Vortex_top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $Vortex_top_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + +# Create instance: axi_bram_ctrl_0, and set properties +set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] +set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ECC_TYPE {0} \ +] $axi_bram_ctrl_0 + +# Create instance: axi_bram_ctrl_0_bram, and set properties +set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] + +set_property -dict [ list \ + CONFIG.Assume_Synchronous_Clk {true} \ + CONFIG.Byte_Size {8} \ + CONFIG.Load_Init_File {true} \ + CONFIG.Coe_File {%COE_FILE%} \ + CONFIG.EN_SAFETY_CKT {true} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Fill_Remaining_Memory_Locations {false} \ + CONFIG.Memory_Type {Simple_Dual_Port_RAM} \ + CONFIG.Operating_Mode_A {NO_CHANGE} \ + CONFIG.Operating_Mode_B {READ_FIRST} \ + CONFIG.Port_B_Write_Rate {0} \ + CONFIG.Read_Width_A {512} \ + CONFIG.Read_Width_B {512} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ + CONFIG.Remaining_Memory_Locations {0} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Use_RSTA_Pin {false} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.Write_Width_A {512} \ + CONFIG.Write_Depth_A {16384} \ + CONFIG.use_bram_block {Stand_Alone} \ +] $axi_bram_ctrl_0_bram + +# Create interface connections +connect_bd_intf_net -intf_net Vortex_top_0_m_axi_mem [get_bd_intf_pins Vortex_top_0/m_axi_mem] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] +connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] +connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTB] + +# Create port connections +connect_bd_net -net Vortex_top_0_busy [get_bd_ports vx_busy] [get_bd_pins Vortex_top_0/busy] +connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins Vortex_top_0/clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] +connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] +connect_bd_net -net vx_reset_1 [get_bd_ports vx_reset] [get_bd_pins Vortex_top_0/reset] +connect_bd_net -net dcr_wr_valid_1 [get_bd_ports dcr_wr_valid] [get_bd_pins Vortex_top_0/dcr_wr_valid] +connect_bd_net -net dcr_wr_addr_1 [get_bd_ports dcr_wr_addr] [get_bd_pins Vortex_top_0/dcr_wr_addr] +connect_bd_net -net dcr_wr_data_1 [get_bd_ports dcr_wr_data] [get_bd_pins Vortex_top_0/dcr_wr_data] + +# Create address segments +assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces Vortex_top_0/m_axi_mem] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + +# Perform GUI Layout +regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-195,-165", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port clk_100MHz -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD +preplace port resetn -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD +preplace port vx_busy -pg 1 -lvl 4 -x 950 -y 220 -defaultsOSRD +preplace port vx_reset -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD +preplace port dcr_wr_valid -pg 1 -lvl 0 -x 0 -y 130 -defaultsOSRD +preplace portBus dcr_wr_addr -pg 1 -lvl 0 -x 0 -y 150 -defaultsOSRD +preplace portBus dcr_wr_data -pg 1 -lvl 0 -x 0 -y 170 -defaultsOSRD +preplace inst Vortex_top_0 -pg 1 -lvl 1 -x 190 -y 130 -defaultsOSRD +preplace inst axi_bram_ctrl_0 -pg 1 -lvl 2 -x 520 -y 140 -defaultsOSRD +preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 3 -x 800 -y 140 -defaultsOSRD +preplace netloc Vortex_top_0_busy 1 1 3 360J 220 NJ 220 NJ +preplace netloc clk_wiz_clk_out1 1 0 2 20 30 370 +preplace netloc resetn_1 1 0 2 NJ 20 380J +preplace netloc vx_reset_1 1 0 1 NJ 110 +preplace netloc dcr_wr_valid_1 1 0 1 NJ 130 +preplace netloc dcr_wr_addr_1 1 0 1 NJ 150 +preplace netloc dcr_wr_data_1 1 0 1 NJ 170 +preplace netloc axi_bram_ctrl_0_BRAM_PORTB 1 2 1 N 150 +preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 2 1 N 130 +preplace netloc Vortex_top_0_m_axi_mem 1 1 1 N 120 +levelinfo -pg 1 0 190 520 800 950 +pagesize -pg 1 -db -bbox -sgen -180 0 1060 240 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_design_1() +cr_bd_design_1 "" +set_property EXCLUDE_DEBUG_LOGIC "0" [get_files design_1.bd ] +set_property GENERATE_SYNTH_CHECKPOINT "1" [get_files design_1.bd ] +set_property IS_ENABLED "1" [get_files design_1.bd ] +set_property IS_GLOBAL_INCLUDE "0" [get_files design_1.bd ] +#set_property IS_LOCKED "0" [get_files design_1.bd ] +set_property LIBRARY "xil_defaultlib" [get_files design_1.bd ] +set_property PATH_MODE "RelativeFirst" [get_files design_1.bd ] +set_property PFM_NAME "" [get_files design_1.bd ] +set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] +set_property USED_IN "synthesis implementation simulation" [get_files design_1.bd ] +set_property USED_IN_IMPLEMENTATION "1" [get_files design_1.bd ] +set_property USED_IN_SIMULATION "1" [get_files design_1.bd ] +set_property USED_IN_SYNTHESIS "1" [get_files design_1.bd ] + +#call make_wrapper to create wrapper files +set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top] +add_files -norecurse -fileset sources_1 $wrapper_path + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xcu280-fsvh2892-2L-e -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2020" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Utilization - Synth Design" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs synth_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "flow" -value "Vivado Synthesis 2020" -objects $obj +set_property -name "name" -value "synth_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "rqs_files" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "write_incremental_synth_checkpoint" -value "0" -objects $obj +set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/project_1.srcs/utils_1/imports/synth_1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj +set_property -name "steps.synth_design.args.flatten_hierarchy" -value "rebuilt" -objects $obj +set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj +set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj +set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj +set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj +set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj +set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj +set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj +set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj +set_property -name "steps.synth_design.args.more options" -value "" -objects $obj + +# Create 'synth_1_copy_1' run (if not found) +if {[string equal [get_runs -quiet synth_1_copy_1] ""]} { + create_run -name synth_1_copy_1 -part xcu280-fsvh2892-2L-e -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1_copy_1] + set_property flow "Vivado Synthesis 2020" [get_runs synth_1_copy_1] +} +set obj [get_runs synth_1_copy_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_copy_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1_copy_1] synth_1_copy_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_copy_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1_copy_1] synth_1_copy_1_synth_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Utilization - Synth Design" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs synth_1_copy_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "flow" -value "Vivado Synthesis 2020" -objects $obj +set_property -name "name" -value "synth_1_copy_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "rqs_files" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "write_incremental_synth_checkpoint" -value "0" -objects $obj +set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/project_1.srcs/utils_1/imports/synth_1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj +set_property -name "steps.synth_design.args.flatten_hierarchy" -value "rebuilt" -objects $obj +set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj +set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj +set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj +set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj +set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj +set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj +set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj +set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj +set_property -name "steps.synth_design.args.more options" -value "" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# preserve signal names +set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xcu280-fsvh2892-2L-e -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2020" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Design Initialization" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "DRC - Opt Design" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Power Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "IO - Place Design" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Utilization - Place Design" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Control Sets - Place Design" -objects $obj +set_property -name "options.verbose" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Place Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Place Power Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Place Phys Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "DRC - Route Design" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Methodology - Route Design" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Power - Route Design" -objects $obj +set_property -name "options.advisory" -value "0" -objects $obj +set_property -name "options.xpe" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Route Status - Route Design" -objects $obj +set_property -name "options.of_objects" -value "" -objects $obj +set_property -name "options.route_type" -value "" -objects $obj +set_property -name "options.list_all_nets" -value "0" -objects $obj +set_property -name "options.show_all" -value "0" -objects $obj +set_property -name "options.has_routing" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Timing Summary - Route Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Route Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Clock Utilization - Route Design" -objects $obj +set_property -name "options.write_xdc" -value "0" -objects $obj +set_property -name "options.clock_roots_only" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Bus Skew - Route Design" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Route Phys Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Bus Skew - Post-Route Phys Opt Design" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Default settings for Implementation." -objects $obj +set_property -name "flow" -value "Vivado Implementation 2020" -objects $obj +set_property -name "name" -value "impl_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "pr_configuration" -value "" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "rqs_files" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/project_1.srcs/utils_1/imports/impl_1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.init_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.init_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj +set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.place_design.tcl.post" -value "" -objects $obj +set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.place_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.route_design.tcl.post" -value "" -objects $obj +set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.route_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj +set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj + +# Create 'impl_1_copy_1' run (if not found) +if {[string equal [get_runs -quiet impl_1_copy_1] ""]} { + create_run -name impl_1_copy_1 -part xcu280-fsvh2892-2L-e -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1_copy_1] + set_property flow "Vivado Implementation 2020" [get_runs impl_1_copy_1] +} +set obj [get_runs impl_1_copy_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_copy_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Design Initialization" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_copy_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "DRC - Opt Design" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Power Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_io_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "IO - Place Design" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Utilization - Place Design" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Control Sets - Place Design" -objects $obj +set_property -name "options.verbose" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Place Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Place Power Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Place Phys Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "DRC - Route Design" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_methodology_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Methodology - Route Design" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_power_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Power - Route Design" -objects $obj +set_property -name "options.advisory" -value "0" -objects $obj +set_property -name "options.xpe" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_route_status_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Route Status - Route Design" -objects $obj +set_property -name "options.of_objects" -value "" -objects $obj +set_property -name "options.route_type" -value "" -objects $obj +set_property -name "options.list_all_nets" -value "0" -objects $obj +set_property -name "options.show_all" -value "0" -objects $obj +set_property -name "options.has_routing" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Timing Summary - Route Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Route Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_clock_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Clock Utilization - Route Design" -objects $obj +set_property -name "options.write_xdc" -value "0" -objects $obj +set_property -name "options.clock_roots_only" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Bus Skew - Route Design" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Route Phys Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_copy_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1_copy_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Bus Skew - Post-Route Phys Opt Design" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs impl_1_copy_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Default settings for Implementation." -objects $obj +set_property -name "flow" -value "Vivado Implementation 2020" -objects $obj +set_property -name "name" -value "impl_1_copy_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "pr_configuration" -value "" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "rqs_files" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/project_1.srcs/utils_1/imports/impl_1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.init_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.init_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj +set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.place_design.tcl.post" -value "" -objects $obj +set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.place_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.route_design.tcl.post" -value "" -objects $obj +set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.route_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj +set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj + +# Create 'impl_1_copy_2' run (if not found) +if {[string equal [get_runs -quiet impl_1_copy_2] ""]} { + create_run -name impl_1_copy_2 -part xcu280-fsvh2892-2L-e -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1_copy_2] + set_property flow "Vivado Implementation 2020" [get_runs impl_1_copy_2] +} +set obj [get_runs impl_1_copy_2] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_copy_2_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Design Initialization" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_copy_2_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_opt_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "DRC - Opt Design" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Power Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_copy_2_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_io_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "IO - Place Design" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_copy_2_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Utilization - Place Design" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_copy_2_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Control Sets - Place Design" -objects $obj +set_property -name "options.verbose" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_copy_2_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_copy_2_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Place Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Place Power Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Place Phys Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "DRC - Route Design" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_methodology_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Methodology - Route Design" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_power_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Power - Route Design" -objects $obj +set_property -name "options.advisory" -value "0" -objects $obj +set_property -name "options.xpe" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_route_status_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Route Status - Route Design" -objects $obj +set_property -name "options.of_objects" -value "" -objects $obj +set_property -name "options.route_type" -value "" -objects $obj +set_property -name "options.list_all_nets" -value "0" -objects $obj +set_property -name "options.show_all" -value "0" -objects $obj +set_property -name "options.has_routing" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Timing Summary - Route Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Incremental Reuse - Route Design" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_clock_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Clock Utilization - Route Design" -objects $obj +set_property -name "options.write_xdc" -value "0" -objects $obj +set_property -name "options.clock_roots_only" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_copy_2_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Bus Skew - Route Design" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_2_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Timing Summary - Post-Route Phys Opt Design" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_copy_2_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_copy_2_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1_copy_2 +} +set obj [get_report_configs -of_objects [get_runs impl_1_copy_2] impl_1_copy_2_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "display_name" -value "Bus Skew - Post-Route Phys Opt Design" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.slack_greater_than" -value "" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs impl_1_copy_2] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Default settings for Implementation." -objects $obj +set_property -name "flow" -value "Vivado Implementation 2020" -objects $obj +set_property -name "name" -value "impl_1_copy_2" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "pr_configuration" -value "" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj +set_property -name "rqs_files" -value "" -objects $obj +set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "gen_full_bitstream" -value "1" -objects $obj +set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/project_1.srcs/utils_1/imports/impl_1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.init_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.init_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj +set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.place_design.tcl.post" -value "" -objects $obj +set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.place_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.route_design.tcl.post" -value "" -objects $obj +set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.route_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj +set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${project_name}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.critical_warning" -value "1" -objects $obj +set_property -name "statistics.error" -value "1" -objects $obj +set_property -name "statistics.info" -value "1" -objects $obj +set_property -name "statistics.warning" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.critical_warning" -value "1" -objects $obj +set_property -name "statistics.error" -value "1" -objects $obj +set_property -name "statistics.info" -value "1" -objects $obj +set_property -name "statistics.warning" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.bram" -value "1" -objects $obj +set_property -name "statistics.clocks" -value "1" -objects $obj +set_property -name "statistics.dsp" -value "1" -objects $obj +set_property -name "statistics.gth" -value "1" -objects $obj +set_property -name "statistics.gtp" -value "1" -objects $obj +set_property -name "statistics.gtx" -value "1" -objects $obj +set_property -name "statistics.gtz" -value "1" -objects $obj +set_property -name "statistics.io" -value "1" -objects $obj +set_property -name "statistics.logic" -value "1" -objects $obj +set_property -name "statistics.mmcm" -value "1" -objects $obj +set_property -name "statistics.pcie" -value "1" -objects $obj +set_property -name "statistics.phaser" -value "1" -objects $obj +set_property -name "statistics.pll" -value "1" -objects $obj +set_property -name "statistics.pl_static" -value "1" -objects $obj +set_property -name "statistics.ps7" -value "1" -objects $obj +set_property -name "statistics.ps" -value "1" -objects $obj +set_property -name "statistics.ps_static" -value "1" -objects $obj +set_property -name "statistics.signals" -value "1" -objects $obj +set_property -name "statistics.total_power" -value "1" -objects $obj +set_property -name "statistics.transceiver" -value "1" -objects $obj +set_property -name "statistics.xadc" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj +set_property -name "run.step" -value "route_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.ths" -value "1" -objects $obj +set_property -name "statistics.tns" -value "1" -objects $obj +set_property -name "statistics.tpws" -value "1" -objects $obj +set_property -name "statistics.whs" -value "1" -objects $obj +set_property -name "statistics.wns" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Table" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj +set_property -name "statistics.bram" -value "1" -objects $obj +set_property -name "statistics.bufg" -value "1" -objects $obj +set_property -name "statistics.dsp" -value "1" -objects $obj +set_property -name "statistics.ff" -value "1" -objects $obj +set_property -name "statistics.gt" -value "1" -objects $obj +set_property -name "statistics.io" -value "1" -objects $obj +set_property -name "statistics.lut" -value "1" -objects $obj +set_property -name "statistics.lutram" -value "1" -objects $obj +set_property -name "statistics.mmcm" -value "1" -objects $obj +set_property -name "statistics.pcie" -value "1" -objects $obj +set_property -name "statistics.pll" -value "1" -objects $obj +set_property -name "statistics.uram" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "active_reports" -value "" -objects $obj +set_property -name "active_reports_invalid" -value "" -objects $obj +set_property -name "active_run" -value "0" -objects $obj +set_property -name "hide_unused_data" -value "1" -objects $obj +set_property -name "incl_new_reports" -value "0" -objects $obj +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj +set_property -name "run.step" -value "place_design" -objects $obj +set_property -name "run.type" -value "implementation" -objects $obj +set_property -name "statistics.bram" -value "1" -objects $obj +set_property -name "statistics.bufg" -value "1" -objects $obj +set_property -name "statistics.dsp" -value "1" -objects $obj +set_property -name "statistics.ff" -value "1" -objects $obj +set_property -name "statistics.gt" -value "1" -objects $obj +set_property -name "statistics.io" -value "1" -objects $obj +set_property -name "statistics.lut" -value "1" -objects $obj +set_property -name "statistics.lutram" -value "1" -objects $obj +set_property -name "statistics.mmcm" -value "1" -objects $obj +set_property -name "statistics.pcie" -value "1" -objects $obj +set_property -name "statistics.pll" -value "1" -objects $obj +set_property -name "statistics.uram" -value "1" -objects $obj +set_property -name "view.orientation" -value "Horizontal" -objects $obj +set_property -name "view.type" -value "Graph" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/hw/syn/xilinx/test/project_1_files/Vortex_top.v b/hw/syn/xilinx/test/project_1_files/Vortex_top.v new file mode 100644 index 00000000..a7adf71b --- /dev/null +++ b/hw/syn/xilinx/test/project_1_files/Vortex_top.v @@ -0,0 +1,208 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module Vortex_top #( + parameter C_M_AXI_GMEM_DATA_WIDTH = 512, + parameter C_M_AXI_GMEM_ADDR_WIDTH = `XLEN, + parameter C_M_AXI_GMEM_ID_WIDTH = 32, + parameter C_M_AXI_MEM_NUM_BANKS = 1 +) ( + input wire clk, + input wire reset, + + // AXI4 memory interface + output wire m_axi_mem_awvalid, + input wire m_axi_mem_awready, + output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr, + output wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_awid, + output wire [7:0] m_axi_mem_awlen, + output wire [2:0] m_axi_mem_awsize, + output wire [1:0] m_axi_mem_awburst, + output wire [1:0] m_axi_mem_awlock, + output wire [3:0] m_axi_mem_awcache, + output wire [2:0] m_axi_mem_awprot, + output wire [3:0] m_axi_mem_awqos, + output wire m_axi_mem_wvalid, + input wire m_axi_mem_wready, + output wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_mem_wdata, + output wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb, + output wire m_axi_mem_wlast, + output wire m_axi_mem_arvalid, + input wire m_axi_mem_arready, + output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_araddr, + output wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_mem_arid, + output wire [7:0] m_axi_mem_arlen, + output wire [2:0] m_axi_mem_arsize, + output wire [1:0] m_axi_mem_arburst, + output wire [1:0] m_axi_mem_arlock, + output wire [3:0] m_axi_mem_arcache, + output wire [2:0] m_axi_mem_arprot, + output wire [3:0] m_axi_mem_arqos, + input wire m_axi_mem_rvalid, + output wire m_axi_mem_rready, + input wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata, + input wire m_axi_mem_rlast, + input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_rid, + input wire [1:0] m_axi_mem_rresp, + input wire m_axi_mem_bvalid, + output wire m_axi_mem_bready, + input wire [1:0] m_axi_mem_bresp, + input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_bid, + + input wire dcr_wr_valid, + input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr, + input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data, + + output wire busy +); + + wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS]; + wire [2:0] m_axi_mem_awsize_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_awburst_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_awlock_a [C_M_AXI_MEM_NUM_BANKS]; + wire [3:0] m_axi_mem_awcache_a [C_M_AXI_MEM_NUM_BANKS]; + wire [2:0] m_axi_mem_awprot_a [C_M_AXI_MEM_NUM_BANKS]; + wire [3:0] m_axi_mem_awqos_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS]; + wire [2:0] m_axi_mem_arsize_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_arburst_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_arlock_a [C_M_AXI_MEM_NUM_BANKS]; + wire [3:0] m_axi_mem_arcache_a [C_M_AXI_MEM_NUM_BANKS]; + wire [2:0] m_axi_mem_arprot_a [C_M_AXI_MEM_NUM_BANKS]; + wire [3:0] m_axi_mem_arqos_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS]; + + assign m_axi_mem_awvalid = m_axi_mem_awvalid_a[0]; + assign m_axi_mem_awready_a[0] = m_axi_mem_awready; + assign m_axi_mem_awaddr = m_axi_mem_awaddr_a[0]; + assign m_axi_mem_awid = m_axi_mem_awid_a[0]; + assign m_axi_mem_awlen = m_axi_mem_awlen_a[0]; + assign m_axi_mem_awsize = m_axi_mem_awsize_a[0]; + assign m_axi_mem_awburst = m_axi_mem_awburst_a[0]; + assign m_axi_mem_awlock = m_axi_mem_awlock_a[0]; + assign m_axi_mem_awcache = m_axi_mem_awcache_a[0]; + assign m_axi_mem_awprot = m_axi_mem_awprot_a[0]; + assign m_axi_mem_awqos = m_axi_mem_awqos_a[0]; + + assign m_axi_mem_wvalid = m_axi_mem_wvalid_a[0]; + assign m_axi_mem_wready_a[0] = m_axi_mem_wready; + assign m_axi_mem_wdata = m_axi_mem_wdata_a[0]; + assign m_axi_mem_wstrb = m_axi_mem_wstrb_a[0]; + assign m_axi_mem_wlast = m_axi_mem_wlast_a[0]; + + assign m_axi_mem_arvalid = m_axi_mem_arvalid_a[0]; + assign m_axi_mem_arready_a[0] = m_axi_mem_arready; + assign m_axi_mem_araddr = m_axi_mem_araddr_a[0]; + assign m_axi_mem_arid = m_axi_mem_arid_a[0]; + assign m_axi_mem_arlen = m_axi_mem_arlen_a[0]; + assign m_axi_mem_arsize = m_axi_mem_arsize_a[0]; + assign m_axi_mem_arburst = m_axi_mem_arburst_a[0]; + assign m_axi_mem_arlock = m_axi_mem_arlock_a[0]; + assign m_axi_mem_arcache = m_axi_mem_arcache_a[0]; + assign m_axi_mem_arprot = m_axi_mem_arprot_a[0]; + assign m_axi_mem_arqos = m_axi_mem_arqos_a[0]; + + assign m_axi_mem_rvalid_a[0] = m_axi_mem_rvalid; + assign m_axi_mem_rready = m_axi_mem_rready_a[0]; + assign m_axi_mem_rdata_a[0] = m_axi_mem_rdata; + assign m_axi_mem_rlast_a[0] = m_axi_mem_rlast; + assign m_axi_mem_rid_a[0] = m_axi_mem_rid; + assign m_axi_mem_rresp_a[0] = m_axi_mem_rresp; + + assign m_axi_mem_bvalid_a[0] = m_axi_mem_bvalid; + assign m_axi_mem_bready = m_axi_mem_bready_a[0]; + assign m_axi_mem_bresp_a[0] = m_axi_mem_bresp; + assign m_axi_mem_bid_a[0] = m_axi_mem_bid; + + Vortex_axi #( + .AXI_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH), + .AXI_ADDR_WIDTH (C_M_AXI_GMEM_ADDR_WIDTH), + .AXI_TID_WIDTH (C_M_AXI_GMEM_ID_WIDTH) + ) inst ( + .clk (clk), + .reset (reset), + + .m_axi_awvalid (m_axi_mem_awvalid_a), + .m_axi_awready (m_axi_mem_awready_a), + .m_axi_awaddr (m_axi_mem_awaddr_a), + .m_axi_awid (m_axi_mem_awid_a), + .m_axi_awlen (m_axi_mem_awlen_a), + .m_axi_awsize (m_axi_mem_awsize_a), + .m_axi_awburst (m_axi_mem_awburst_a), + .m_axi_awlock (m_axi_mem_awlock_a), + .m_axi_awcache (m_axi_mem_awcache_a), + .m_axi_awprot (m_axi_mem_awprot_a), + .m_axi_awqos (m_axi_mem_awqos_a), + + .m_axi_wvalid (m_axi_mem_wvalid_a), + .m_axi_wready (m_axi_mem_wready_a), + .m_axi_wdata (m_axi_mem_wdata_a), + .m_axi_wstrb (m_axi_mem_wstrb_a), + .m_axi_wlast (m_axi_mem_wlast_a), + + .m_axi_bvalid (m_axi_mem_bvalid_a), + .m_axi_bready (m_axi_mem_bready_a), + .m_axi_bid (m_axi_mem_bid_a), + .m_axi_bresp (m_axi_mem_bresp_a), + + .m_axi_arvalid (m_axi_mem_arvalid_a), + .m_axi_arready (m_axi_mem_arready_a), + .m_axi_araddr (m_axi_mem_araddr_a), + .m_axi_arid (m_axi_mem_arid_a), + .m_axi_arlen (m_axi_mem_arlen_a), + .m_axi_arsize (m_axi_mem_arsize_a), + .m_axi_arburst (m_axi_mem_arburst_a), + .m_axi_arlock (m_axi_mem_arlock_a), + .m_axi_arcache (m_axi_mem_arcache_a), + .m_axi_arprot (m_axi_mem_arprot_a), + .m_axi_arqos (m_axi_mem_arqos_a), + + .m_axi_rvalid (m_axi_mem_rvalid_a), + .m_axi_rready (m_axi_mem_rready_a), + .m_axi_rdata (m_axi_mem_rdata_a), + .m_axi_rid (m_axi_mem_rid_a), + .m_axi_rresp (m_axi_mem_rresp_a), + .m_axi_rlast (m_axi_mem_rlast_a), + + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data), + + .busy (busy) + ); + +endmodule diff --git a/hw/syn/xilinx/test/project_1_files/kernel.bin.coe b/hw/syn/xilinx/test/project_1_files/kernel.bin.coe new file mode 100644 index 00000000..a316d82b --- /dev/null +++ b/hw/syn/xilinx/test/project_1_files/kernel.bin.coe @@ -0,0 +1,16386 @@ +MEMORY_INITIALIZATION_RADIX=16; +MEMORY_INITIALIZATION_VECTOR= +0, +000000C00000008000000002, +00000003000000020000000100000000, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, 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+// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`timescale 10ns / 1ns + +`define CYCLE_TIME 4 + +module testbench; + reg clk; + reg resetn; + reg [43:0] cycles; + + reg vx_running; + reg vx_reset_wait; + reg vx_busy_wait; + wire vx_busy; + + reg dcr_wr_valid; + reg [11:0] dcr_wr_addr; + reg [31:0] dcr_wr_data; + + design_1_wrapper UUD( + .clk_100MHz (clk), + .resetn (resetn), + .vx_reset (~resetn || ~vx_running), + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data), + .vx_busy (vx_busy) + ); + + always #(`CYCLE_TIME/2) + clk = ~clk; + + initial begin + clk = 1'b0; + resetn = 1'b0; + #4 resetn = 1'b1; + end + + always @(posedge clk) begin + if (~resetn) begin + cycles <= 0; + end else begin + cycles <= cycles + 1; + end + end + + reg [7:0] vx_reset_ctr; + always @(posedge clk) begin + if (vx_reset_wait) begin + vx_reset_ctr <= vx_reset_ctr + 1; + end else begin + vx_reset_ctr <= 0; + end + end + + always @(posedge clk) begin + if (~resetn) begin + vx_running <= 0; + vx_reset_wait <= 0; + vx_busy_wait <= 0; + dcr_wr_valid <= 0; + dcr_wr_addr <= 0; + dcr_wr_data <= 0; + end else begin + case (cycles) + 1: begin + dcr_wr_valid <= 1; + dcr_wr_addr <= `VX_DCR_BASE_STARTUP_ADDR0; + dcr_wr_data <= `STARTUP_ADDR; + end + 2: begin + dcr_wr_valid <= 0; + dcr_wr_addr <= 0; + dcr_wr_data <= 0; + end + 3: begin + vx_reset_wait <= 1; + end + default:; + endcase + + if (vx_running) begin + if (vx_busy_wait) begin + if (vx_busy) begin + vx_busy_wait <= 0; + end + end else begin + if (~vx_busy) begin + vx_running <= 0; + $display("done!"); + $finish; + end + end + end else begin + if (vx_reset_wait && vx_reset_ctr == (`RESET_DELAY-1)) begin + $display("start!"); + vx_reset_wait <= 0; + vx_running <= 1; + vx_busy_wait <= 1; + end + end + end + end + +endmodule \ No newline at end of file diff --git a/hw/syn/xilinx/xrt/.gitignore b/hw/syn/xilinx/xrt/.gitignore new file mode 100644 index 00000000..7e7b2b15 --- /dev/null +++ b/hw/syn/xilinx/xrt/.gitignore @@ -0,0 +1 @@ +/build*/* \ No newline at end of file diff --git a/hw/syn/xilinx/xrt/Makefile b/hw/syn/xilinx/xrt/Makefile new file mode 100644 index 00000000..bfb0123d --- /dev/null +++ b/hw/syn/xilinx/xrt/Makefile @@ -0,0 +1,200 @@ +ifneq ($(findstring Makefile, $(MAKEFILE_LIST)), Makefile) +help: + $(ECHO) "Makefile Usage:" + $(ECHO) " make all TARGET= PLATFORM=" + $(ECHO) " Command to generate the design for specified Target and Device." + $(ECHO) "" + $(ECHO) " make clean" + $(ECHO) " Command to remove the generated non-hardware files." + $(ECHO) "" +endif + +TARGET ?= hw +PLATFORM ?= +XLEN ?= 32 +NUM_CORES ?= 1 +PREFIX ?= build$(XLEN) +MAX_JOBS ?= 8 + +RTL_DIR = ../../../../rtl +AFU_DIR = $(RTL_DIR)/afu/xrt +DPI_DIR = ../../../../dpi +SCRIPT_DIR = ../../../../scripts +THIRD_PARTY_DIR = ../../../../../third_party + +VIVADO = $(XILINX_VIVADO)/bin/vivado +VPP = $(XILINX_VITIS)/bin/v++ +CP = cp -rf +RMDIR = rm -rf +ECHO = @echo + +NCPUS := $(shell grep -c ^processor /proc/cpuinfo) +JOBS ?= $(shell echo $$(( $(NCPUS) > $(MAX_JOBS) ? $(MAX_JOBS) : $(NCPUS) ))) + +PLATFORM_TO_XSA = $(strip $(patsubst %.xpfm, % , $(shell basename $(PLATFORM)))) +XSA := $(call PLATFORM_TO_XSA, $(PLATFORM)) + +DEV_ARCH := $(shell platforminfo -p $(PLATFORM) | grep 'FPGA Family' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//') +CPU_TYPE := $(shell platforminfo -p $(PLATFORM) | grep 'CPU Type' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//') + +BUILD_DIR = $(PREFIX)_$(XSA)_$(TARGET) +BIN_DIR = $(BUILD_DIR)/bin + +XO_CONTAINER = $(BIN_DIR)/vortex_afu.xo +XCLBIN_CONTAINER = $(BIN_DIR)/vortex_afu.xclbin + +# Control RTL debug tracing states +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA +DBG_TRACE_FLAGS += -DDBG_TRACE_AFU +DBG_TRACE_FLAGS += -DDBG_TRACE_TEX +DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER +DBG_TRACE_FLAGS += -DDBG_TRACE_ROP +DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR + +# Control logic analyzer monitors +DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU +DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE +DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH +DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU +DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER +DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED + +# cluster configuration +CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1 +CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2 +CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 +CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 +CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS += $(CONFIGS_$(NUM_CORES)c) + +# include paths +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) +RTL_INCLUDE += $(FPU_INCLUDE) + +# Kernel compiler global settings +VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache +VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS) + +ifeq ($(DEV_ARCH), zynquplus) +# ztnq +else ifeq ($(DEV_ARCH), versal) +# versal +else +# alveo +VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15] +endif + +VPP_FLAGS += --report_level 2 +VPP_FLAGS += --config ../vitis.ini + +# Enable perf counters +ifdef PERF + CFLAGS += -DPERF_ENABLE +endif + +# Generates profile summary report +ifdef PROFILE + VPP_FLAGS += --profile_kernel data:all:all:all + VPP_FLAGS += --profile_kernel stall:all:all:all +endif + +ifeq ($(TARGET), hw_emu) + CFLAGS += -DSIMULATION +endif + +# Debugigng +ifdef DEBUG + VPP_FLAGS += -g --debug.protocol all + ifeq ($(TARGET), hw) + CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS) + SCOPE_JSON += $(BUILD_DIR)/scope.json + #CFLAGS += -DNDEBUG -DCHIPSCOPE $(DBG_SCOPE_FLAGS) + #VPP_FLAGS += --debug.chipscope vortex_afu_1 + else + VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all + CFLAGS += $(DBG_TRACE_FLAGS) + endif +else + VPP_FLAGS += --optimize 3 + CFLAGS += -DNDEBUG +endif + +# compilation flags +CFLAGS += -DSYNTHESIS -DVIVADO +CFLAGS += -DXLEN_$(XLEN) +CFLAGS += $(CONFIGS) +CFLAGS += $(RTL_INCLUDE) + +# ast dump flags +XML_CFLAGS = $(filter-out -DSYNTHESIS -DVIVADO, $(CFLAGS)) -I$(DPI_DIR) + +# RTL Kernel only supports Hardware and Hardware Emulation. +ifneq ($(TARGET),$(findstring $(TARGET), hw hw_emu)) + $(warning WARNING:Application supports only hw hw_emu TARGET. Please use the target for running the application) +endif + +.PHONY: all clean gen-sources gen-ast emconfig check-devices + +all: check-devices emconfig $(XCLBIN_CONTAINER) report + +gen-sources: $(BUILD_DIR)/sources.txt +$(BUILD_DIR)/sources.txt: + mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt + +gen-ast: $(BUILD_DIR)/vortex.xml +$(BUILD_DIR)/vortex.xml: + mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.v --xml-output vortex.xml + +scope-json: $(BUILD_DIR)/scope.json +$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml + mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/scope.py vortex.xml -o scope.json + +gen-xo: $(XO_CONTAINER) +$(XO_CONTAINER): $(BUILD_DIR)/sources.txt + mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source ../scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR) + +gen-bin: $(XCLBIN_CONTAINER) +$(XCLBIN_CONTAINER): $(XO_CONTAINER) $(SCOPE_JSON) + mkdir -p $(BIN_DIR); cd $(BUILD_DIR); $(VPP) $(VPP_FLAGS) -o ../$(XCLBIN_CONTAINER) ../$(XO_CONTAINER) + +emconfig: $(BIN_DIR)/emconfig.json +$(BIN_DIR)/emconfig.json: + mkdir -p $(BIN_DIR); cd $(BUILD_DIR); emconfigutil --platform $(PLATFORM) --od ../$(BIN_DIR) + +report: $(XCLBIN_CONTAINER) +ifeq ($(TARGET),$(findstring $(TARGET), hw)) + cp $(BUILD_DIR)/_x/logs/link/syn/ulp_vortex_afu_1_0_synth_1_runme.log $(BUILD_DIR)/bin/runme.log + cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_full_util_routed.rpt $(BUILD_DIR)/bin/synthesis.log + cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin/timing.log +endif + +hwserver: + debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server & + +chipscope: + debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx & + +clean: + $(RMDIR) $(BUILD_DIR) + +# Check the devices avaiable +check-devices: +ifndef PLATFORM + $(error PLATFORM not set. Please set the PLATFORM properly and rerun. Run "make help" for more details.) +endif +ifndef XILINX_VITIS + $(error XILINX_VITIS variable is not set, please set correctly and rerun) +endif diff --git a/hw/syn/xilinx/xrt/kill_build.sh b/hw/syn/xilinx/xrt/kill_build.sh new file mode 100755 index 00000000..4e6ae3f7 --- /dev/null +++ b/hw/syn/xilinx/xrt/kill_build.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +ps -A | grep xrcserver | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep loader | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep vpl | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep v++ | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep vivado | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep runme.sh | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep ISEWrap.sh | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep vrs | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep xcd | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep make | awk '{print $1}' | xargs kill -9 $1 diff --git a/hw/syn/xilinx/xrt/kill_hwserver.sh b/hw/syn/xilinx/xrt/kill_hwserver.sh new file mode 100755 index 00000000..6323ae6f --- /dev/null +++ b/hw/syn/xilinx/xrt/kill_hwserver.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +ps -A | grep debug_hw | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep python3 | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep xvc_pcie | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep hw_server | awk '{print $1}' | xargs kill -9 $1 \ No newline at end of file diff --git a/hw/syn/xilinx/xrt/kill_sim.sh b/hw/syn/xilinx/xrt/kill_sim.sh new file mode 100755 index 00000000..8809ad03 --- /dev/null +++ b/hw/syn/xilinx/xrt/kill_sim.sh @@ -0,0 +1,19 @@ +#!/bin/sh + +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +ps -A | grep launch_hw_emu.s | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep simulate.sh | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep xsim | awk '{print $1}' | xargs kill -9 $1 +ps -A | grep xsimk | awk '{print $1}' | xargs kill -9 $1 \ No newline at end of file diff --git a/hw/syn/xilinx/xrt/scripts/gen_ip.tcl b/hw/syn/xilinx/xrt/scripts/gen_ip.tcl new file mode 100644 index 00000000..5aae6db7 --- /dev/null +++ b/hw/syn/xilinx/xrt/scripts/gen_ip.tcl @@ -0,0 +1,40 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +if { $::argc != 1 } { + puts "ERROR: Program \"$::argv0\" requires 1 arguments!\n" + puts "Usage: $::argv0 \n" + exit +} + +set ip_dir [lindex $::argv 0] + +# IP folder does not exist. Create IP folder +file mkdir ${ip_dir} + +# create_ip requires that a project is open in memory. +# Create project but don't do anything with it +create_project -in_memory + +create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fdiv -dir ${ip_dir} +set_property -dict [list CONFIG.Component_Name {xil_fdiv} CONFIG.Operation_Type {Divide} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.C_Has_DIVIDE_BY_ZERO {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fdiv] + +create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fsqrt -dir ${ip_dir} +set_property -dict [list CONFIG.Component_Name {xil_fsqrt} CONFIG.Operation_Type {Square_root} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {No_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {28} CONFIG.C_Rate {1}] [get_ips xil_fsqrt] + +create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name xil_fma -dir ${ip_dir} +set_property -dict [list CONFIG.Component_Name {xil_fma} CONFIG.Operation_Type {FMA} CONFIG.Add_Sub_Value {Add} CONFIG.Flow_Control {NonBlocking} CONFIG.Has_ACLKEN {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.Has_A_TUSER {false} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {Medium_Usage} CONFIG.Has_RESULT_TREADY {false} CONFIG.C_Latency {16} CONFIG.C_Rate {1} CONFIG.A_TUSER_Width {1}] [get_ips xil_fma] + +generate_target all [get_ips] + +close_project -delete diff --git a/hw/syn/xilinx/xrt/scripts/gen_xo.tcl b/hw/syn/xilinx/xrt/scripts/gen_xo.tcl new file mode 100644 index 00000000..0f95f09b --- /dev/null +++ b/hw/syn/xilinx/xrt/scripts/gen_xo.tcl @@ -0,0 +1,40 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +if { $::argc != 5 } { + puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n" + puts "Usage: $::argv0 \n" + exit +} + +set xoname [lindex $::argv 0] +set krnl_name [lindex $::argv 1] +set vcs_file [lindex $::argv 2] +set tool_dir [lindex $::argv 3] +set build_dir [lindex $::argv 4] + +set script_path [ file dirname [ file normalize [ info script ] ] ] + +if {[file exists "${xoname}"]} { + file delete -force "${xoname}" +} + +set argv [list ${build_dir}/ip] +set argc 1 +source ${script_path}/gen_ip.tcl + +set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}] +set argc 4 +source ${script_path}/package_kernel.tcl + +package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel" diff --git a/hw/syn/xilinx/xrt/scripts/package_kernel.tcl b/hw/syn/xilinx/xrt/scripts/package_kernel.tcl new file mode 100644 index 00000000..73476de0 --- /dev/null +++ b/hw/syn/xilinx/xrt/scripts/package_kernel.tcl @@ -0,0 +1,268 @@ +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +if { $::argc != 4 } { + puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n" + puts "Usage: $::argv0 \n" + exit +} + +set krnl_name [lindex $::argv 0] +set vcs_file [lindex $::argv 1] +set tool_dir [lindex $::argv 2] +set build_dir [lindex $::argv 3] + +set path_to_packaged "${build_dir}/xo/packaged_kernel" +set path_to_tmp_project "${build_dir}/xo/project" + +source "${tool_dir}/parse_vcs_list.tcl" +set vlist [parse_vcs_list "${vcs_file}"] + +set vsources_list [lindex $vlist 0] +set vincludes_list [lindex $vlist 1] +set vdefines_list [lindex $vlist 2] + +#puts ${vsources_list} +#puts ${vincludes_list} +#puts ${vdefines_list} + +# find if chipscope is enabled +set chipscope 0 +foreach def $vdefines_list { + set fields [split $def "="] + set name [lindex $fields 0] + if { $name == "CHIPSCOPE" } { + set chipscope 1 + } +} + +create_project -force kernel_pack $path_to_tmp_project + +add_files -norecurse ${vsources_list} + +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${build_dir}/ip/xil_fdiv/xil_fdiv.xci"] \ + [file normalize "${build_dir}/ip/xil_fma/xil_fma.xci"] \ + [file normalize "${build_dir}/ip/xil_fsqrt/xil_fsqrt.xci"] \ +] +add_files -verbose -norecurse -fileset $obj $files + +set_property include_dirs ${vincludes_list} [current_fileset] +#set_property verilog_define ${vdefines_list} [current_fileset] + +set obj [get_filesets sources_1] +set_property -verbose -name "top" -value ${krnl_name} -objects $obj + +if { $chipscope == 1 } { + # hw debugging + create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_afu + set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_DATA_DEPTH {4096} \ + CONFIG.C_NUM_OF_PROBES {2} \ + CONFIG.C_PROBE0_WIDTH {8} \ + CONFIG.C_PROBE1_WIDTH {24} \ + ] [get_ips ila_afu] + generate_target {instantiation_template} [get_files ila_afu.xci] + set_property generate_synth_checkpoint false [get_files ila_afu.xci] + + create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_fetch + set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_DATA_DEPTH {4096} \ + CONFIG.C_NUM_OF_PROBES {3} \ + CONFIG.C_PROBE0_WIDTH {128} \ + CONFIG.C_PROBE1_WIDTH {128} \ + CONFIG.C_PROBE2_WIDTH {128} \ + ] [get_ips ila_fetch] + generate_target {instantiation_template} [get_files ila_fetch.xci] + set_property generate_synth_checkpoint false [get_files ila_fetch.xci] + + create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_issue + set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_DATA_DEPTH {4096} \ + CONFIG.C_NUM_OF_PROBES {2} \ + CONFIG.C_PROBE0_WIDTH {256} \ + CONFIG.C_PROBE1_WIDTH {128} \ + ] [get_ips ila_issue] + generate_target {instantiation_template} [get_files ila_issue.xci] + set_property generate_synth_checkpoint false [get_files ila_issue.xci] + + create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_lsu + set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_DATA_DEPTH {4096} \ + CONFIG.C_NUM_OF_PROBES {4} \ + CONFIG.C_PROBE0_WIDTH {256} \ + CONFIG.C_PROBE1_WIDTH {128} \ + CONFIG.C_PROBE2_WIDTH {288} \ + CONFIG.C_PROBE3_WIDTH {256} \ + ] [get_ips ila_lsu] + generate_target {instantiation_template} [get_files ila_lsu.xci] + set_property generate_synth_checkpoint false [get_files ila_lsu.xci] + + create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_msched + set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_DATA_DEPTH {4096} \ + CONFIG.C_NUM_OF_PROBES {4} \ + CONFIG.C_PROBE0_WIDTH {128} \ + CONFIG.C_PROBE1_WIDTH {128} \ + CONFIG.C_PROBE2_WIDTH {128} \ + CONFIG.C_PROBE3_WIDTH {128} \ + ] [get_ips ila_msched] + generate_target {instantiation_template} [get_files ila_msched.xci] + set_property generate_synth_checkpoint false [get_files ila_msched.xci] + + create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_raster + set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_DATA_DEPTH {4096} \ + CONFIG.C_NUM_OF_PROBES {2} \ + CONFIG.C_PROBE0_WIDTH {128} \ + CONFIG.C_PROBE1_WIDTH {128} \ + ] [get_ips ila_raster] + generate_target {instantiation_template} [get_files ila_raster.xci] + set_property generate_synth_checkpoint false [get_files ila_raster.xci] +} + +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 +ipx::package_project -root_dir $path_to_packaged -vendor xilinx.com -library RTLKernel -taxonomy /KernelIP -import_files -set_current false +ipx::unload_core $path_to_packaged/component.xml +ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $path_to_packaged $path_to_packaged/component.xml + +set core [ipx::current_core] + +set_property core_revision 2 $core +foreach up [ipx::get_user_parameters] { + ipx::remove_user_parameter [get_property NAME $up] $core +} + +ipx::associate_bus_interfaces -busif s_axi_ctrl -clock ap_clk $core + +for {set i 0} {$i < 1} {incr i} { + ipx::associate_bus_interfaces -busif m_axi_mem_$i -clock ap_clk $core +} + +set mem_map [::ipx::add_memory_map -quiet "s_axi_ctrl" $core] +set addr_block [::ipx::add_address_block -quiet "reg0" $mem_map] + +set reg [::ipx::add_register "CTRL" $addr_block] + set_property description "Control signals" $reg + set_property address_offset 0x000 $reg + set_property size 32 $reg + +set field [ipx::add_field AP_START $reg] + set_property ACCESS {read-write} $field + set_property BIT_OFFSET {0} $field + set_property BIT_WIDTH {1} $field + set_property DESCRIPTION {Control signal Register for 'ap_start'.} $field + set_property MODIFIED_WRITE_VALUE {modify} $field + +set field [ipx::add_field AP_DONE $reg] + set_property ACCESS {read-only} $field + set_property BIT_OFFSET {1} $field + set_property BIT_WIDTH {1} $field + set_property DESCRIPTION {Control signal Register for 'ap_done'.} $field + set_property READ_ACTION {modify} $field + +set field [ipx::add_field AP_IDLE $reg] + set_property ACCESS {read-only} $field + set_property BIT_OFFSET {2} $field + set_property BIT_WIDTH {1} $field + set_property DESCRIPTION {Control signal Register for 'ap_idle'.} $field + set_property READ_ACTION {modify} $field + +set field [ipx::add_field AP_READY $reg] + set_property ACCESS {read-only} $field + set_property BIT_OFFSET {3} $field + set_property BIT_WIDTH {1} $field + set_property DESCRIPTION {Control signal Register for 'ap_ready'.} $field + set_property READ_ACTION {modify} $field + +set field [ipx::add_field RESERVED_1 $reg] + set_property ACCESS {read-only} $field + set_property BIT_OFFSET {4} $field + set_property BIT_WIDTH {3} $field + set_property DESCRIPTION {Reserved. 0s on read.} $field + set_property READ_ACTION {modify} $field + +set field [ipx::add_field AUTO_RESTART $reg] + set_property ACCESS {read-write} $field + set_property BIT_OFFSET {7} $field + set_property BIT_WIDTH {1} $field + set_property DESCRIPTION {Control signal Register for 'auto_restart'.} $field + set_property MODIFIED_WRITE_VALUE {modify} $field + +set field [ipx::add_field RESERVED_2 $reg] + set_property ACCESS {read-only} $field + set_property BIT_OFFSET {8} $field + set_property BIT_WIDTH {24} $field + set_property DESCRIPTION {Reserved. 0s on read.} $field + set_property READ_ACTION {modify} $field + +set reg [::ipx::add_register "GIER" $addr_block] + set_property description "Global Interrupt Enable Register" $reg + set_property address_offset 0x004 $reg + set_property size 32 $reg + +set reg [::ipx::add_register "IP_IER" $addr_block] + set_property description "IP Interrupt Enable Register" $reg + set_property address_offset 0x008 $reg + set_property size 32 $reg + +set reg [::ipx::add_register "IP_ISR" $addr_block] + set_property description "IP Interrupt Status Register" $reg + set_property address_offset 0x00C $reg + set_property size 32 $reg + +set reg [::ipx::add_register -quiet "DEV" $addr_block] + set_property address_offset 0x010 $reg + set_property size [expr {8*8}] $reg + +set reg [::ipx::add_register -quiet "ISA" $addr_block] + set_property address_offset 0x01C $reg + set_property size [expr {8*8}] $reg + +set reg [::ipx::add_register -quiet "DCR" $addr_block] + set_property address_offset 0x028 $reg + set_property size [expr {8*8}] $reg + +set reg [::ipx::add_register -quiet "SCP" $addr_block] + set_property address_offset 0x034 $reg + set_property size [expr {8*8}] $reg + +for {set i 0} {$i < 1} {incr i} { + set reg [::ipx::add_register -quiet "MEM_$i" $addr_block] + set_property address_offset [expr {0x040 + $i * 12}] $reg + set_property size [expr {8*8}] $reg + set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg] + set_property value m_axi_mem_$i $regparam +} + +set_property slave_memory_map_ref "s_axi_ctrl" [::ipx::get_bus_interfaces -of $core "s_axi_ctrl"] + +set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core +set_property sdx_kernel true $core +set_property sdx_kernel_type rtl $core +set_property supported_families { } $core +set_property auto_family_support_level level_2 $core + +ipx::create_xgui_files $core +ipx::update_checksums $core +ipx::check_integrity -kernel $core +ipx::save_core $core +close_project -delete diff --git a/hw/syn/xilinx/xrt/scripts/xsim.tcl b/hw/syn/xilinx/xrt/scripts/xsim.tcl new file mode 100644 index 00000000..061bc17a --- /dev/null +++ b/hw/syn/xilinx/xrt/scripts/xsim.tcl @@ -0,0 +1,25 @@ +# +# Copyright 2021 Xilinx, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +#log_wave -r * +#run all +#exit + +open_vcd xsim_dump.vcd +log_vcd /* +run all +close_vcd +exit diff --git a/hw/syn/xilinx/xrt/vitis.ini b/hw/syn/xilinx/xrt/vitis.ini new file mode 100644 index 00000000..e662ff3b --- /dev/null +++ b/hw/syn/xilinx/xrt/vitis.ini @@ -0,0 +1,9 @@ +[connectivity] +#nk=vortex_afu:1 +#sp=vortex_afu_1.m_axi_mem_0:HBM[0:15] + +[vivado] +#prop=fileset.sim_1.xsim.elaborate.debug_level=all + +[advanced] +#param=compiler.userPostDebugProfileOverlayTcl=../scripts/post_dbg_profile_overlay.tcl \ No newline at end of file diff --git a/hw/syn/xilinx/xrt/xrt.ini b/hw/syn/xilinx/xrt/xrt.ini new file mode 100644 index 00000000..09421911 --- /dev/null +++ b/hw/syn/xilinx/xrt/xrt.ini @@ -0,0 +1,11 @@ +[Runtime] +runtime_log=console + +[Emulation] +#debug_mode=batch +#user_pre_sim_script=xsim.tcl + +[Debug] +profile=true +timeline_trace=true +data_transfer_trace=fine \ No newline at end of file diff --git a/hw/syn/yosys/.gitignore b/hw/syn/yosys/.gitignore new file mode 100644 index 00000000..5fea2524 --- /dev/null +++ b/hw/syn/yosys/.gitignore @@ -0,0 +1 @@ +build_*/* \ No newline at end of file diff --git a/hw/syn/yosys/Makefile b/hw/syn/yosys/Makefile index 6ac5f6a0..34f6059f 100644 --- a/hw/syn/yosys/Makefile +++ b/hw/syn/yosys/Makefile @@ -1,20 +1,99 @@ -PROJECT = Vortex -TOP_LEVEL_ENTITY = Vortex -SRC_FILE = Vortex.sv -RTL_DIR = ../../rtl +TOP_LEVEL_ENTITY ?= Vortex +PREFIX ?= build +NUM_CORES ?= 1 +XLEN ?= 32 -DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64 +SCRIPT_DIR = ../../../scripts +RTL_DIR = ../../../rtl +DPI_DIR = ../../../dpi +THIRD_PARTY_DIR = ../../../../third_party -RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache +CP = cp -rf +RMDIR = rm -rf +ECHO = @echo + +BUILD_DIR = $(PREFIX)_$(TOP_LEVEL_ENTITY) +BIN_DIR = $(BUILD_DIR)/bin + +# control RTL debug tracing states +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA +DBG_TRACE_FLAGS += -DDBG_TRACE_AFU +DBG_TRACE_FLAGS += -DDBG_TRACE_TEX +DBG_TRACE_FLAGS += -DDBG_TRACE_RASTER +DBG_TRACE_FLAGS += -DDBG_TRACE_ROP +DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR + +# Control logic analyzer monitors +DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU +DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE +DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH +DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU +DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER +DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED + +# cluster configuration +CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1 +CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2 +CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE +CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE +CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE +CONFIGS += $(CONFIGS_$(NUM_CORES)c) + +# include paths +FPU_INCLUDE = -I$(RTL_DIR)/fpu +ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) + FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src +endif +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache +RTL_INCLUDE += $(FPU_INCLUDE) + +# Debugigng +ifdef DEBUG + CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS) + SCOPE_JSON += $(BUILD_DIR)/scope.json +else + CFLAGS += -DNDEBUG +endif + +# Enable scope analyzer +ifdef SCOPE + CFLAGS += -DSCOPE +endif + +# Enable perf counters +ifdef PERF + CFLAGS += -DPERF_ENABLE +endif + +CFLAGS += -DSYNTHESIS -DYOSYS +CFLAGS += -DXLEN_$(XLEN) +CFLAGS += $(CONFIGS) +CFLAGS += $(RTL_INCLUDE) # Build targets -all: build +all: clean build -output.v: - ./sv2v.sh $(DEFINES) $(RTL_INCLUDE) -ooutput.v +gen-sources: $(BUILD_DIR)/sources.txt +$(BUILD_DIR)/sources.txt: + mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt -build: output.v - ./synth.sh -t$(TOP_LEVEL_ENTITY) -soutput.v +$(BUILD_DIR)/project.v: gen-sources + cd $(BUILD_DIR); $(SCRIPT_DIR)/sv2v.sh -t$(TOP_LEVEL_ENTITY) -Isrc -oproject.v + +build: $(BUILD_DIR)/project.v + cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v + +elaborate: $(BUILD_DIR)/project.v + cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v -P="elaborate" clean: - rm -rf output.v *.ys *.log + $(RMDIR) $(BUILD_DIR) diff --git a/hw/syn/yosys/synth.sh b/hw/syn/yosys/synth.sh index 07528757..79f68aaf 100755 --- a/hw/syn/yosys/synth.sh +++ b/hw/syn/yosys/synth.sh @@ -1,5 +1,18 @@ #!/bin/bash +# Copyright © 2019-2023 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + # this script uses sv2v and yosys tools to run. # sv2v: https://github.com/zachjs/sv2v # yosys: http://www.clifford.at/yosys/ @@ -12,10 +25,48 @@ top_level="" dir_list=() inc_args="" macro_args="" +no_warnings=1 +process="elaborate,netlist,techmap,verilog" + +declare -a excluded_warnings=("Resizing cell port") + +is_excluded_warning() { + local warning_text="$1" + for exclusion in "${excluded_warnings[@]}"; do + if [[ "$warning_text" == *"$exclusion"* ]]; then + return $no_warnings + fi + done + return 1 +} + +checkErrors() +{ + log_file="$1" + if grep -q "Error: " "$log_file"; then + echo "Error: found errors during synthesis!" + exit 1 + fi + + count=0 + while IFS= read -r line; do + if [[ "$line" == *"Warning:"* ]]; then + warning_text="${line#Warning: }" + if ! is_excluded_warning "$warning_text"; then + count=$(expr $count + 1) + fi + fi + done < $log_file + + if [ "$count" -ne 0 ]; then + echo "Error: found $count unexpected warnings during synthesis!" + exit $count + fi +} usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; } [ $# -eq 0 ] && usage -while getopts "s:t:I:D:h" arg; do +while getopts "s:t:I:D:P:Wh" arg; do case $arg in s) # source source=${OPTARG} @@ -30,6 +81,12 @@ while getopts "s:t:I:D:h" arg; do D) # macro definition macro_args="$macro_args -D${OPTARG}" ;; + P) # process + process=${OPTARG} + ;; + W) # allow warnings + no_warnings=0 + ;; h | *) usage exit 0 @@ -43,23 +100,34 @@ done do for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) do - echo "read_verilog $macro_args $inc_args -sv $file" + echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $file" done done if [ -n "$source" ]; then - echo "read_verilog $macro_args $inc_args -sv $source" + echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $source" fi - # generic synthesis - echo "synth -top $top_level" + # elaborate + if echo "$process" | grep -q "elaborate"; then + echo "hierarchy -top $top_level" + fi + + # convert to netlist + if echo "$process" | grep -q "netlist"; then + echo "proc; opt" + fi - # mapping to mycells.lib - echo "dfflibmap -liberty mycells.lib" - echo "abc -liberty mycells.lib" - echo "clean" + # convert to gate logic + if echo "$process" | grep -q "techmap"; then + echo "techmap; opt" + fi # write synthesized design - echo "write_verilog synth.v" + if echo "$process" | grep -q "verilog"; then + echo "write_verilog synth.v" + fi } > synth.ys -yosys -l yosys.log synth.ys \ No newline at end of file +yosys -l yosys.log synth.ys + +checkErrors yosys.log diff --git a/hw/unit_tests/VX_divide_tb.v b/hw/unit_tests/VX_divide_tb.v index a4ba539e..cf4804ba 100644 --- a/hw/unit_tests/VX_divide_tb.v +++ b/hw/unit_tests/VX_divide_tb.v @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `timescale 1ns/1ps module VX_tb_divide(); @@ -17,7 +30,7 @@ module VX_tb_divide(); wire [31:0] o_div[0:7], o_rem[0:7]; - for (genvar i = 0; i < 8; i++) begin + for (genvar i = 0; i < 8; ++i) begin VX_divide#( .WIDTHN(32), .WIDTHD(32), diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile index e23b4898..79c500a1 100644 --- a/hw/unit_tests/cache/Makefile +++ b/hw/unit_tests/cache/Makefile @@ -1,4 +1,6 @@ -PARAMS += -DCACHE_SIZE=4096 -DCACHE_WORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DCACHE_NUM_BANKS=4 -DCACHE_CREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 +PARAMS += -DCACHE_SIZE=4096 -DCACHE_WORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DCACHE_NUM_BANKS=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 + +TOP = VX_cache # control RTL debug tracing states DBG_TRACE_FLAGS = -DDBG_TRACE_CORE_PIPELINE \ @@ -31,7 +33,7 @@ VF += -exe $(SRCS) $(INCLUDE) VF += $(PARAMS) gen: - verilator $(VF) -cc $(TOP).v -CFLAGS '$(CF)' --exe $(SRCS) + verilator $(VF) -cc $(TOP).sv -CFLAGS '$(CF)' --exe $(SRCS) build: gen (cd obj_dir && make -j -f V$(TOP).mk) diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp index 736b5cb2..e7fea67e 100644 --- a/hw/unit_tests/cache/cachesim.cpp +++ b/hw/unit_tests/cache/cachesim.cpp @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include "cachesim.h" #include #include @@ -235,7 +248,7 @@ void CacheSim::eval_mem_bus() { if (cache_->mem_req_valid) { if (cache_->mem_req_rw) { //write = 1 uint64_t byteen = cache_->mem_req_byteen; - unsigned base_addr = (cache_->mem_req_addr * MEM_BLOCK_SIZE); + uint64_t base_addr = (cache_->mem_req_addr * MEM_BLOCK_SIZE); uint8_t* data = (uint8_t*)(cache_->mem_req_data); for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { diff --git a/hw/unit_tests/cache/cachesim.h b/hw/unit_tests/cache/cachesim.h index 72cc44f9..b0fad6fe 100644 --- a/hw/unit_tests/cache/cachesim.h +++ b/hw/unit_tests/cache/cachesim.h @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #pragma once #include "VVX_cache.h" diff --git a/hw/unit_tests/cache/ram.h b/hw/unit_tests/cache/ram.h index 0ddd3e47..d01934a5 100644 --- a/hw/unit_tests/cache/ram.h +++ b/hw/unit_tests/cache/ram.h @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #pragma once #include diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp index 4a38bb7c..64e188e5 100644 --- a/hw/unit_tests/cache/testbench.cpp +++ b/hw/unit_tests/cache/testbench.cpp @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include "cachesim.h" #include #include diff --git a/runtime/.gitignore b/hw/unit_tests/cache2/Makefile similarity index 100% rename from runtime/.gitignore rename to hw/unit_tests/cache2/Makefile diff --git a/hw/unit_tests/tex_unit/tex_sampler/vl_simulator.h b/hw/unit_tests/common/vl_simulator.h similarity index 72% rename from hw/unit_tests/tex_unit/tex_sampler/vl_simulator.h rename to hw/unit_tests/common/vl_simulator.h index 16486adf..9b2d57ad 100644 --- a/hw/unit_tests/tex_unit/tex_sampler/vl_simulator.h +++ b/hw/unit_tests/common/vl_simulator.h @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #pragma once #include diff --git a/hw/unit_tests/generic_queue/main.cpp b/hw/unit_tests/generic_queue/main.cpp index c753a7c8..ba46ebce 100644 --- a/hw/unit_tests/generic_queue/main.cpp +++ b/hw/unit_tests/generic_queue/main.cpp @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include "vl_simulator.h" #include "VVX_fifo_queue.h" #include diff --git a/hw/unit_tests/generic_queue/testbench.v b/hw/unit_tests/generic_queue/testbench.v index 66cafbaf..30b926a5 100644 --- a/hw/unit_tests/generic_queue/testbench.v +++ b/hw/unit_tests/generic_queue/testbench.v @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + `timescale 1ns/1ns `include "VX_fifo_queue.v" @@ -15,8 +28,8 @@ module testbench(); wire empty; VX_fifo_queue #( - .DATAW(4), - .SIZE(4) + .DATAW (4), + .DEPTH (4) ) dut ( .clk(clk), .reset(reset), diff --git a/hw/unit_tests/generic_queue/vl_simulator.h b/hw/unit_tests/generic_queue/vl_simulator.h index 16486adf..9b2d57ad 100644 --- a/hw/unit_tests/generic_queue/vl_simulator.h +++ b/hw/unit_tests/generic_queue/vl_simulator.h @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #pragma once #include diff --git a/hw/unit_tests/mem_streamer/mem_streamer/Makefile b/hw/unit_tests/mem_streamer/mem_streamer/Makefile new file mode 100644 index 00000000..f42c5cb3 --- /dev/null +++ b/hw/unit_tests/mem_streamer/mem_streamer/Makefile @@ -0,0 +1,65 @@ +#--------------------------------------------------------- +# Makefile to compile and test the memory stream unit +#--------------------------------------------------------- + +TOP = VX_mem_scheduler +PARAMS += -GNUM_REQS=4 -GADDRW=8 -GDATAW=8 -GTAGW=8 -GWORD_SIZE=1 -GQUEUE_SIZE=4 + +ifdef RSP_PARTIAL + PARAMS += -GRSP_PARTIAL=$(RSP_PARTIAL) +endif + +ifdef DUPLICATE_ADDR + PARAMS += -GDUPLICATE_ADDR=$(DUPLICATE_ADDR) +endif + +RTL_DIR = ../../../rtl +DPI_DIR = ../../../dpi + +RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(DPI_DIR) + +VERILATOR_ROOT = /opt/verilator +VERILATOR ?= $(VERILATOR_ROOT)/bin/verilator + +VL_FLAGS += --exe --cc $(TOP).sv --top-module $(TOP) +VL_FLAGS += --language 1800-2009 --assert -Wall +VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO +VL_FLAGS += --x-initial unique --x-assign unique +VL_FLAGS += --trace +VL_FLAGS += $(RTL_INCLUDE) +VL_FLAGS += $(PARAMS) + +SRCS += memsim.cpp ram.cpp $(DPI_DIR)/util_dpi.cpp + +CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors -Wno-array-bounds -Wno-maybe-uninitialized +CXXFLAGS += -I../../../../dpi -I../../../../ + +default: run + +gen: $(SRCS) + @echo + @echo "### VERILATE ###" + $(VERILATOR) $(VL_FLAGS) $^ -CFLAGS '$(CXXFLAGS)' + +build: gen + @echo + @echo "### BUILD ###" + $(MAKE) -C obj_dir -j 4 -f V$(TOP).mk + +run: build + @echo + @echo "### RUN ###" + obj_dir/V$(TOP) + +waves: trace.vcd + @echo + @echo "### TRACE ###" + gtkwave -o trace.vcd + +clean: + @echo + @echo "### CLEAN ###" + -rm -rf obj_dir *.vcd *.log + +#--------------------------------------------------------- + diff --git a/hw/unit_tests/mem_streamer/mem_streamer/memsim.cpp b/hw/unit_tests/mem_streamer/mem_streamer/memsim.cpp new file mode 100644 index 00000000..a6958c39 --- /dev/null +++ b/hw/unit_tests/mem_streamer/mem_streamer/memsim.cpp @@ -0,0 +1,176 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "memsim.h" +#include "ram.h" + +static bool trace_enabled = false; +static uint64_t trace_start_time = 0; +static uint64_t trace_stop_time = -1ull; +static uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +bool sim_trace_enabled() { + if (timestamp >= trace_start_time + && timestamp < trace_stop_time) + return true; + return trace_enabled; +} + +void sim_trace_enable (bool enable) { + trace_enabled = enable; +} + +////////////////////////////////////////////////////// + +int generate_rand (int min, int max) { + int range = max - min + 1; + return rand() % range + min; +} + +////////////////////////////////////////////////////// + +int generate_rand_mask (int mask) { + int result = 0; + int m = mask; + for (int i = 0; i < 4; i++) { + int bit = m & 0b1; + int rand_bit = generate_rand (0, bit); + result |= (rand_bit << i); + m = m >> 1; + } + return result; +} + +////////////////////////////////////////////////////// + +MemSim::MemSim() { + msu_ = new VVX_mem_streamer(); + + // Enable tracing + Verilated::traceEverOn(true); + trace_ = new VerilatedVcdC; + msu_->trace(trace_, 99); + trace_->open("trace.vcd"); +} + +////////////////////////////////////////////////////// + +MemSim::~MemSim() { + trace_->close(); + delete msu_; +} + +////////////////////////////////////////////////////// + +void MemSim::eval() { + msu_->eval(); + trace_->dump(timestamp++); +} + +////////////////////////////////////////////////////// + +void MemSim::step() { + msu_->clk = 0; + this->eval(); + + msu_->clk = 1; + this->eval(); +} + +////////////////////////////////////////////////////// + +void MemSim::reset() { + msu_->reset = 1; + this->step(); + + msu_->reset = 0; + this->step(); + +} + +////////////////////////////////////////////////////// + +void MemSim::attach_core() { + if (msu_->req_ready) { + msu_->req_valid = generate_rand(0, 1); + msu_->req_rw = generate_rand(0, 1); + msu_->req_mask = generate_rand(0b0001, 0b1111); + msu_->req_byteen = 0b1; + msu_->req_addr = generate_rand(0, 0x10000000); + msu_->req_data = generate_rand(0x60000000, 0x80000000); + msu_->req_tag = generate_rand(0x00, 0xFF); + } + msu_->rsp_ready = true; +} + +////////////////////////////////////////////////////// + +void MemSim::attach_ram (RAM *ram) { + + req_t req; + req.valid = msu_->mem_req_valid; + req.rw = msu_->mem_req_rw; + req.byteen = msu_->mem_req_byteen; + req.addr = msu_->mem_req_addr; + req.data = msu_->mem_req_data; + req.tag = msu_->mem_req_tag; + msu_->mem_req_ready = ram->is_ready(); + + ram->insert_req(req); + + rsp_t rsp; + rsp = ram->schedule_rsp(); + + msu_->mem_rsp_valid = rsp.valid; + msu_->mem_rsp_mask = rsp.mask; + msu_->mem_rsp_data = rsp.data; + msu_->mem_rsp_tag = rsp.tag; + rsp.ready = msu_->mem_rsp_ready; + std::cout<<"MEMSIM: mem_rsp_ready: "<halt_rsp(rsp); +} + +////////////////////////////////////////////////////// + +void MemSim::run(RAM *ram) { + this->reset(); + + while (sc_time_stamp() < SIM_TIME) { + this->step(); + std::cout<<"========================="<<"\n"; + std::cout<<"Cycle: "<attach_core(); + this->attach_ram(ram); + } +} + +////////////////////////////////////////////////////// + +int main (int argc, char** argv, char** env) { + Verilated::commandArgs(argc, argv); + + MemSim memsim; + RAM ram; + + memsim.run(&ram); + + return 0; +} + +////////////////////////////////////////////////////// \ No newline at end of file diff --git a/hw/unit_tests/mem_streamer/mem_streamer/memsim.h b/hw/unit_tests/mem_streamer/mem_streamer/memsim.h new file mode 100644 index 00000000..1fd09d24 --- /dev/null +++ b/hw/unit_tests/mem_streamer/mem_streamer/memsim.h @@ -0,0 +1,47 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include +#include +#include "VVX_mem_streamer.h" +#include "VVX_mem_streamer__Syms.h" +#include "ram.h" + +#define SIM_TIME 5000 + +int generate_rand (int min, int max); +int generate_rand_mask (int mask); + +class MemSim { + private: + VVX_mem_streamer *msu_; + VerilatedVcdC *trace_; + + void eval(); + void step(); + void reset(); + + void attach_core(); + void attach_ram(RAM *ram); + + public: + MemSim(); + virtual ~MemSim(); + + void run(RAM *ram); +}; diff --git a/hw/unit_tests/mem_streamer/mem_streamer/ram.cpp b/hw/unit_tests/mem_streamer/mem_streamer/ram.cpp new file mode 100644 index 00000000..4a4c4780 --- /dev/null +++ b/hw/unit_tests/mem_streamer/mem_streamer/ram.cpp @@ -0,0 +1,137 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ram.h" +#include "memsim.h" + +RAM::RAM() { + + ram_.clear(); + is_rsp_active_ = false; + is_rsp_stall_ = false; +} + +////////////////////////////////////////////////////// + +bool RAM::check_duplicate_req(req_t req) { + for(int i = 0; i < ram_.size(); i++) { + if (ram_[i].addr == req.addr) { + std::cout<<"RAM: Duplicate entry. Do not insert..."< 0) { + ram_[i].cycles_left -= 1; + } + } + + std::cout<<"RAM: # cycles left: "<check_duplicate_req(req)) && req.valid && !req.rw) { + req_t r; + r.valid = req.valid; + r.rw = req.rw; + r.byteen = req.byteen; + r.addr = req.addr; + r.data = req.data; + r.tag = req.tag & 0b11; + + // Store metadata + r.cycles_left = MEM_LATENCY; + + std::cout<<"RAM: Insert entry... "<simulate_cycle_delay(); + + if (!is_rsp_active_) { + if (dequeue_index != -1) { + + std::cout<<"RAM: Scheduling response... "< +#include + +#define MEM_LATENCY 4 + +typedef struct { + uint8_t valid; + bool rw; + uint8_t byteen; + uint32_t addr; + uint32_t data; + uint8_t tag; + uint8_t ready; + + // Metadata + uint8_t rsp_sent_mask; + double cycles_left; +} req_t; + +typedef struct { + bool valid; + uint8_t mask; + uint32_t data; + uint8_t tag; + bool ready; +} rsp_t; + +class RAM { + + private: + std::vector ram_; + + bool is_rsp_active_; + bool is_rsp_stall_; + + bool check_duplicate_req(req_t req); + int simulate_cycle_delay(); + + public: + RAM(); + + uint8_t is_ready(); + void insert_req(req_t req); + rsp_t schedule_rsp(); + void halt_rsp(rsp_t rsp); + +}; + +////////////////////////////////////////////////////// diff --git a/hw/unit_tests/tex_unit/tex_sampler/Makefile b/hw/unit_tests/tex_unit/tex_sampler/Makefile deleted file mode 100644 index c6de8aa1..00000000 --- a/hw/unit_tests/tex_unit/tex_sampler/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -TOP = VX_tex_sampler - -PARAMS ?= - -INCLUDE = -I../../../rtl/ -I../../../rtl/libs -I../../../rtl/tex_unit - -SRCS = main.cpp - -all: build - -CF += -std=c++11 -fms-extensions -I../.. -VF += $(PARAMS) - -VF += --language 1800-2009 --assert -Wall --trace -VF += -Wno-DECLFILENAME -VF += --x-initial unique -VF += -exe $(SRCS) $(INCLUDE) -VF += $(PARAMS) - -gen: - verilator $(VF) -cc $(TOP).v -CFLAGS '$(CF)' --exe $(SRCS) - -build: gen - (cd obj_dir && make -j -f V$(TOP).mk) - -run: build - (cd obj_dir && ./V$(TOP)) - -clean: - rm -rf obj_dir diff --git a/hw/unit_tests/tex_unit/tex_sampler/main.cpp b/hw/unit_tests/tex_unit/tex_sampler/main.cpp deleted file mode 100644 index a67b38cb..00000000 --- a/hw/unit_tests/tex_unit/tex_sampler/main.cpp +++ /dev/null @@ -1,215 +0,0 @@ -#include "vl_simulator.h" -#include "VVX_tex_sampler.h" -#include -#include - -#define MAX_TICKS 20 -#define MAX_UNIT_CYCLES 5 -#define NUM_THREADS - -#define CHECK(x) \ - do { \ - if (x) \ - break; \ - std::cout << "FAILED: " << #x << std::endl; \ - std::abort(); \ - } while (false) - -uint64_t ticks = 0; - -// using Device = VVX_tex_sampler; - -template -class testbench -{ -private: - vl_simulator sim; - std::map input_map; - std::map output_map; - -public: - - struct UnitTest { - bool use_reset; - unsigned int num_cycles; - bool use_cmodel; - struct Output outputs[MAX_UNIT_CYCLES]; - struct Input inputs[MAX_UNIT_CYCLES]; - unsigned int num_output_check; - unsigned int check_output_cycle[MAX_UNIT_CYCLES]; - } - - struct Input { - bool req_valid; - unsigned int req_wid; - unsigned int req_tmask; - unsigned int req_PC; - unsigned int req_rd; - unsigned int req_wb; - unsigned int req_filter; - unsigned int req_format; - unsigned int req_u[NUM_THREADS]; - unsigned int req_v[NUM_THREADS]; - unsigned int req_texels[NUM_THREADS][4]; - bool rsp_ready; - } - - struct Output { - int output_cycle; - // outputs - bool req_ready; - bool rsp_valid; - unsigned int rsp_wid; - unsigned int rsp_tmask; - unsigned int rsp_PC; - unsigned int rsp_rd; - bool rsp_wb; - unsigned int rsp_data[NUM_THREADS]; - } - - testbench(/* args */){ - - } - - ~testbench(){ - } - - void unittest_Cmodel(struct UnitTest * test){ - int cycles = test->num_cycles; - int num_outputs = test->num_output_check; - - // struct Input* inputs = new (struct Input)[cycles]; - struct Output* outputs = new (struct Output)[num_outputs]; - - // implement c model and assign outputs to struct - - if (test->inputs[0]->req_filter == 0){ - for (int i = 0; i < NUM_THREADS; i++) - outputs[0]->rsp_data[0] = test->inputs->req_texels[i][0]; - } else { - // for (int i = 0; i < NUM_THREADS; i++){ - // uint32_t low[4], high[4]; - // for (int j = 0; j < 4; j++){ - // low[j] = test->inputs->req_texels[i][j] & 0x00ff00ff; - // high[j] = (test->inputs->req_texels[i][j] >> 8) & 0x00ff00ff; - // } - - // } - } - outputs[0]->output_cycle = 1; - test->num_cycles = 1; - test->outputs = &outputs; - - } - - void generate_test_vectors(struct UnitTest * tests, int num_tests, bool is_pipe){ - // for all unit tests create output test vectors (w w/o c-model) - int prev_test_cycle = 0; - - for (int i = 0; i < num_tests; i++) - { - int op_counter = 0; - int ip_counter = 0; - - int test_cycle = 0; - int last_ip_cycle = 0; - - struct UnitTest curr_test = tests[i]; - - if (curr_test->use_cmodel){ - unittest_Cmodel(&curr_test); - } - - for (int j = 0; j < curr_test->num_cycles; j++) - { - if (curr_test->inputs[ip_counter]->input_cycle == test_cycle){ - input_map.insert(std::make_pair(prev_test_cycle + test_cycle, curr_test->inputs[j])); - last_ip_cycle = prev_test_cycle + test_cycle; - ip_counter++; - } - - if (curr_test->outputs[op_counter]->output_cycle == test_cycle){ - output_map.insert(std::make_pair(prev_test_cycle + test_cycle, curr_test->outputs[op_counter])); - op_counter++; - } - - test_cycle++; - } - - if(!is_pipe){ - prev_test_cycle += (test_cycle - 1); - } - else{ - prev_test_cycle = last_ip_cycle + 1; - } - - } - - } - - void run(){ - - ticks = sim.reset(0); - int cycle = 0; - - while (ticks < MAX_TICKS) { - - auto input = input_map.find(cycle); - auto output = output_map.find(cycle); - - if (input != input_map.end()){ - sim->req_valid = input->req_valid; - sim->req_wid = input->req_wid; - sim->req_tmask = input->req_tmask; - sim->req_PC = input->req_PC; - sim->req_rd = input->req_rd; - sim->req_wb = input->req_wb; - sim->req_filter = input->req_filter; - sim->req_format = input->req_format; - // sim->req_u = input->req_u[NUM_THREADS]; - // sim->req_v = input->req_v[NUM_THREADS]; - vl_setw(sim->req_texels, input->req_texels) - // sim->req_texels = input->req_texels[NUM_THREADS][4]; - sim->rsp_ready = input->rsp_ready; - } else{ - std::cout << "Warning! No Input on Cycle " << cycle << std::endl; - } - - if(output != output_map.end()){ - CHECK(sim->req_ready == output->req_ready); - CHECK(sim->rsp_valid == output->rsp_valid); - CHECK(sim->rsp_wid == output->rsp_wid); - CHECK(sim->rsp_tmask == output->rsp_tmask); - CHECK(sim->rsp_PC == output->rsp_PC); - CHECK(sim->rsp_rd == output->rsp_rd); - CHECK(sim->rsp_wb == output->rsp_wb); - CHECK(vl_cmpw(sim->rsp_data, output->rsp_data)); - } - - cycle++; - ticks = sim.step(ticks,2); - } - } - - std::cout << "PASSED!" << std::endl; - std::cout << "Simulation time: " << std::dec << ticks/2 << " cycles" << std::endl; - -}; - - -double sc_time_stamp() { - return ticks; -} - -int main(int argc, char **argv) { - // Initialize Verilators variables - Verilated::commandArgs(argc, argv); - - testbench sampler_testbench; - - sampler_testbench.generate_test_vectors(tests, 1, 0); - sampler_test_bench.run(); - - - return 0; -} \ No newline at end of file diff --git a/kernel/.gitignore b/kernel/.gitignore new file mode 100644 index 00000000..e69de29b diff --git a/kernel/Makefile b/kernel/Makefile new file mode 100644 index 00000000..e4c975dc --- /dev/null +++ b/kernel/Makefile @@ -0,0 +1,66 @@ +XLEN ?= 32 + +ifeq ($(XLEN),64) +RISCV_TOOLCHAIN_PATH ?= /opt/riscv64-gnu-toolchain +CFLAGS += -march=rv64imafd -mabi=lp64d +else +RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain +CFLAGS += -march=rv32imaf -mabi=ilp32f +endif + +RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf +RISCV_SYSROOT ?= $(RISCV_TOOLCHAIN_PATH)/$(RISCV_PREFIX) + +LLVM_VORTEX ?= /opt/llvm-vortex + +LLVM_CFLAGS += --sysroot=$(RISCV_SYSROOT) +LLVM_CFLAGS += --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) +LLVM_CFLAGS += -Xclang -target-feature -Xclang +vortex -mllvm -vortex-branch-divergence=0 +#LLVM_CFLAGS += -I$(RISCV_SYSROOT)/include/c++/9.2.0/$(RISCV_PREFIX) +#LLVM_CFLAGS += -I$(RISCV_SYSROOT)/include/c++/9.2.0 +#LLVM_CFLAGS += -Wl,-L$(RISCV_TOOLCHAIN_PATH)/lib/gcc/$(RISCV_PREFIX)/9.2.0 +#LLVM_CFLAGS += --rtlib=libgcc + +#CC = $(LLVM_VORTEX)/bin/clang $(LLVM_CFLAGS) +#CXX = $(LLVM_VORTEX)/bin/clang++ $(LLVM_CFLAGS) +#DP = $(LLVM_VORTEX)/bin/llvm-objdump +#CP = $(LLVM_VORTEX)/bin/llvm-objcopy + +CC = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc +CXX = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-g++ +AR = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc-ar +DP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objdump +CP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objcopy + +CFLAGS += -O3 -mcmodel=medany -fno-exceptions -nostartfiles -fdata-sections -ffunction-sections +CFLAGS += -I./include -I../hw +CFLAGS += -DXLEN_$(XLEN) + +PROJECT = libvortexrt + +SRCS = ./src/vx_start.S ./src/vx_syscalls.c ./src/vx_print.S ./src/tinyprintf.c ./src/vx_print.c ./src/vx_spawn.c ./src/vx_serial.S ./src/vx_perf.c + +OBJS := $(addsuffix .o, $(notdir $(SRCS))) + +all: $(PROJECT).a $(PROJECT).dump + +$(PROJECT).dump: $(PROJECT).a + $(DP) -D $(PROJECT).a > $(PROJECT).dump + +%.S.o: src/%.S + $(CC) $(CFLAGS) -c $< -o $@ + +%.cpp.o: src/%.cpp + $(CXX) $(CFLAGS) -c $< -o $@ + +%.c.o: src/%.c + $(CC) $(CFLAGS) -c $< -o $@ + +$(PROJECT).a: $(OBJS) + $(AR) rcs $@ $^ + +.depend: $(SRCS) + $(CC) $(CFLAGS) -MM $^ > .depend; + +clean: + rm -rf *.a *.o *.dump .depend diff --git a/kernel/include/vx_intrinsics.h b/kernel/include/vx_intrinsics.h new file mode 100644 index 00000000..1dbf4da0 --- /dev/null +++ b/kernel/include/vx_intrinsics.h @@ -0,0 +1,247 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __VX_INTRINSICS_H__ +#define __VX_INTRINSICS_H__ + +#include +#include + +#if defined(__clang__) +#define __UNIFORM__ __attribute__((annotate("vortex.uniform"))) +#else +#define __UNIFORM__ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#define RISCV_CUSTOM0 0x0B +#define RISCV_CUSTOM1 0x2B +#define RISCV_CUSTOM2 0x5B +#define RISCV_CUSTOM3 0x7B + +#define csr_read(csr) ({ \ + unsigned __r; \ + __asm__ __volatile__ ("csrr %0, %1" : "=r" (__r) : "i" (csr)); \ + __r; \ +}) + +#define csr_write(csr, val) ({ \ + unsigned __v = (unsigned)(val); \ + if (__builtin_constant_p(val) && __v < 32) \ + __asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "i" (__v)); \ + else \ + __asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "r" (__v)); \ +}) + +#define csr_swap(csr, val) ({ \ + unsigned __r; \ + unsigned __v = (unsigned)(val); \ + if (__builtin_constant_p(val) && __v < 32) \ + __asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \ + else \ + __asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \ + __r; \ +}) + +#define csr_read_set(csr, val) ({ \ + unsigned __r; \ + unsigned __v = (unsigned)(val); \ + if (__builtin_constant_p(val) && __v < 32) \ + __asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \ + else \ + __asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \ + __r; \ +}) + +#define csr_set(csr, val) ({ \ + unsigned __v = (unsigned)(val); \ + if (__builtin_constant_p(val) && __v < 32) \ + __asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "i" (__v)); \ + else \ + __asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "r" (__v)); \ +}) + +#define csr_read_clear(csr, val) ({ \ + unsigned __r; \ + unsigned __v = (unsigned)(val); \ + if (__builtin_constant_p(val) && __v < 32) \ + __asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \ + else \ + __asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \ + __r; \ +}) + +#define csr_clear(csr, val) ({ \ + unsigned __v = (unsigned)(val); \ + if (__builtin_constant_p(val) && __v < 32) \ + __asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "i" (__v)); \ + else \ + __asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "r" (__v)); \ +}) + +// Texture load +inline unsigned vx_tex(unsigned stage, unsigned u, unsigned v, unsigned lod) { + unsigned ret; + asm volatile (".insn r4 %1, 0, %2, %0, %3, %4, %5" : "=r"(ret) : "i"(RISCV_CUSTOM1), "i"(stage), "r"(u), "r"(v), "r"(lod)); + return ret; +} + +// Conditional move +inline unsigned vx_cmov(unsigned c, unsigned t, unsigned f) { + unsigned ret; + asm volatile (".insn r4 %1, 1, 0, %0, %2, %3, %4" : "=r"(ret) : "i"(RISCV_CUSTOM1), "r"(c), "r"(t), "r"(f)); + return ret; +} + +// Rop write +inline void vx_rop(unsigned x, unsigned y, unsigned face, unsigned color, unsigned depth) { + unsigned pos_face = (y << 16) | (x << 1) | face; + asm volatile (".insn r4 %0, 1, 1, x0, %1, %2, %3" :: "i"(RISCV_CUSTOM1), "r"(pos_face), "r"(color), "r"(depth)); +} + +// Raster load +inline unsigned vx_rast() { + unsigned ret; + asm volatile (".insn r %1, 0, 1, %0, x0, x0" : "=r"(ret) : "i"(RISCV_CUSTOM0)); + return ret; +} + +// Set thread mask +inline void vx_tmc(unsigned thread_mask) { + asm volatile (".insn r %0, 0, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(thread_mask)); +} + +// disable all threads in the current warp +inline void vx_tmc_zero() { + asm volatile (".insn r %0, 0, 0, x0, x0, x0" :: "i"(RISCV_CUSTOM0)); +} + +// switch execution to single thread zero +inline void vx_tmc_one() { + asm volatile ( + "li a0, 1\n\t" // Load immediate value 1 into a0 (x10) register + ".insn r %0, 0, 0, x0, a0, x0" :: "i"(RISCV_CUSTOM0) + : "a0" // Indicate that a0 (x10) is clobbered + ); +} + +// Set thread predicate +inline void vx_pred(unsigned condition, unsigned thread_mask) { + asm volatile (".insn r %0, 5, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(condition), "r"(thread_mask)); +} + +typedef void (*vx_wspawn_pfn)(); + +// Spawn warps +inline void vx_wspawn(unsigned num_warps, vx_wspawn_pfn func_ptr) { + asm volatile (".insn r %0, 1, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(num_warps), "r"(func_ptr)); +} + +// Split on a predicate +inline unsigned vx_split(unsigned predicate) { + unsigned ret; + asm volatile (".insn r %1, 2, 0, %0, %2, x0" : "=r"(ret) : "i"(RISCV_CUSTOM0), "r"(predicate)); + return ret; +} + +// Join +inline void vx_join(unsigned stack_ptr) { + asm volatile (".insn r %0, 3, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(stack_ptr)); +} + +// Warp Barrier +inline void vx_barrier(unsigned barried_id, unsigned num_warps) { + asm volatile (".insn r %0, 4, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(barried_id), "r"(num_warps)); +} + +// Return current thread identifier +inline int vx_thread_id() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_ID)); + return ret; +} + +// Return current warp identifier +inline int vx_warp_id() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_ID)); + return ret; +} + +// Return current core identifier +inline int vx_core_id() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_CORE_ID)); + return ret; +} + +// Return current thread mask +inline int vx_thread_mask() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_MASK)); + return ret; +} + +// Return number of active warps +inline int vx_active_warps() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_MASK)); + return ret; +} + +// Return the number of threads per warp +inline int vx_num_threads() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_THREADS)); + return ret; +} + +// Return the number of warps per core +inline int vx_num_warps() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_WARPS)); + return ret; +} + +// Return the number of cores per cluster +inline int vx_num_cores() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_CORES)); + return ret; +} + +// Return the hart identifier (thread id accross the processor) +inline int vx_hart_id() { + int ret; + asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_MHARTID)); + return ret; +} + +inline void vx_fence() { + asm volatile ("fence iorw, iorw"); +} + +#ifdef __cplusplus +} +#endif + +#endif // __VX_INTRINSICS_H__ diff --git a/kernel/include/vx_print.h b/kernel/include/vx_print.h new file mode 100644 index 00000000..1dd2a0fa --- /dev/null +++ b/kernel/include/vx_print.h @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __VX_PRINT_H__ +#define __VX_PRINT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int vx_vprintf(const char* format, va_list va); +int vx_printf(const char * format, ...); + +void vx_putchar(int c); +void vx_putint(int value, int base); +void vx_putfloat(float value, int precision); + +#ifdef __cplusplus +} +#endif + +#endif // __VX_PRINT_H__ diff --git a/runtime/include/vx_spawn.h b/kernel/include/vx_spawn.h similarity index 55% rename from runtime/include/vx_spawn.h rename to kernel/include/vx_spawn.h index 905f22a5..2584b997 100644 --- a/runtime/include/vx_spawn.h +++ b/kernel/include/vx_spawn.h @@ -1,5 +1,18 @@ -#ifndef VX_API_H -#define VX_API_H +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __VX_SPAWN_H__ +#define __VX_SPAWN_H__ #include #include @@ -30,6 +43,8 @@ typedef void (*vx_spawn_tasks_cb)(int task_id, void *arg); typedef void (*vx_serial_cb)(void *arg); +void vx_wspawn_wait(); + void vx_spawn_kernel(context_t * ctx, vx_spawn_kernel_cb callback, void * arg); void vx_spawn_tasks(int num_tasks, vx_spawn_tasks_cb callback, void * arg); @@ -40,4 +55,4 @@ void vx_serial(vx_serial_cb callback, void * arg); } #endif -#endif \ No newline at end of file +#endif // __VX_SPAWN_H__ diff --git a/runtime/linker/vx_link32.ld b/kernel/linker/vx_link32.ld similarity index 84% rename from runtime/linker/vx_link32.ld rename to kernel/linker/vx_link32.ld index 7461e516..d8a50026 100644 --- a/runtime/linker/vx_link32.ld +++ b/kernel/linker/vx_link32.ld @@ -1,15 +1,15 @@ -/* ---- Original Script: /opt/riscv32i/riscv32-unknown-elf/lib/ldscripts/elf32lriscv.x ---- */ /* Default linker script, for normal executables */ -/* Copyright (C) 2014-2017 Free Software Foundation, Inc. +/* Copyright (C) 2014-2020 Free Software Foundation, Inc. Copying and distribution of this script, with or without modification, are permitted in any medium without royalty provided the copyright notice and this notice are preserved. */ -OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", + "elf32-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) SECTIONS { - . = 0x80000000; + . = STARTUP_ADDR; .interp : { *(.interp) } .note.gnu.build-id : { *(.note.gnu.build-id) } .hash : { *(.hash) } @@ -19,23 +19,24 @@ SECTIONS .gnu.version : { *(.gnu.version) } .gnu.version_d : { *(.gnu.version_d) } .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : + .rela.init : { *(.rela.init) } + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + .rela.fini : { *(.rela.fini) } + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } + .rela.data.rel.ro : { *(.rela.data.rel.ro .rela.data.rel.ro.* .rela.gnu.linkonce.d.rel.ro.*) } + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } + .rela.ctors : { *(.rela.ctors) } + .rela.dtors : { *(.rela.dtors) } + .rela.got : { *(.rela.got) } + .rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) } + .rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) } + .rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) } + .rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) } + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } + .rela.iplt : { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) PROVIDE_HIDDEN (__rela_iplt_start = .); *(.rela.iplt) PROVIDE_HIDDEN (__rela_iplt_end = .); @@ -56,8 +57,9 @@ SECTIONS *(.text.exit .text.exit.*) *(.text.startup .text.startup.*) *(.text.hot .text.hot.*) + *(SORT(.text.sorted.*)) *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf32.em. */ + /* .gnu.warning sections are handled specially by elf.em. */ *(.gnu.warning) } .fini : @@ -201,23 +203,9 @@ SECTIONS . = ALIGN(32 / 8); __BSS_END__ = .; __global_pointer = MIN(__SDATA_BEGIN__ + 0x800, - MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); + MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); _end = .; PROVIDE (end = .); - . = DATA_SEGMENT_END (.); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } - __stack_usage = SIZEOF(.stack_dummy); - PROVIDE(__stack_top = 0xFF000000); - PROVIDE(__stack_size = 0x400); - PROVIDE(__stack = __stack_top); - ASSERT(__stack_usage <= __stack_size, "stack overflow") - + . = DATA_SEGMENT_END (.); /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } diff --git a/runtime/linker/vx_link64.ld b/kernel/linker/vx_link64.ld similarity index 84% rename from runtime/linker/vx_link64.ld rename to kernel/linker/vx_link64.ld index 18b3669b..072281f7 100644 --- a/runtime/linker/vx_link64.ld +++ b/kernel/linker/vx_link64.ld @@ -1,15 +1,15 @@ -/* ---- Original Script: /opt/riscv32i/riscv32-unknown-elf/lib/ldscripts/elf64lriscv.x ---- */ /* Default linker script, for normal executables */ -/* Copyright (C) 2014-2017 Free Software Foundation, Inc. +/* Copyright (C) 2014-2020 Free Software Foundation, Inc. Copying and distribution of this script, with or without modification, are permitted in any medium without royalty provided the copyright notice and this notice are preserved. */ -OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", + "elf64-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) SECTIONS { - . = 0x80000000; + . = STARTUP_ADDR; .interp : { *(.interp) } .note.gnu.build-id : { *(.note.gnu.build-id) } .hash : { *(.hash) } @@ -19,23 +19,24 @@ SECTIONS .gnu.version : { *(.gnu.version) } .gnu.version_d : { *(.gnu.version_d) } .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : + .rela.init : { *(.rela.init) } + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + .rela.fini : { *(.rela.fini) } + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } + .rela.data.rel.ro : { *(.rela.data.rel.ro .rela.data.rel.ro.* .rela.gnu.linkonce.d.rel.ro.*) } + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } + .rela.ctors : { *(.rela.ctors) } + .rela.dtors : { *(.rela.dtors) } + .rela.got : { *(.rela.got) } + .rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) } + .rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) } + .rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) } + .rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) } + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } + .rela.iplt : { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) PROVIDE_HIDDEN (__rela_iplt_start = .); *(.rela.iplt) PROVIDE_HIDDEN (__rela_iplt_end = .); @@ -56,8 +57,9 @@ SECTIONS *(.text.exit .text.exit.*) *(.text.startup .text.startup.*) *(.text.hot .text.hot.*) + *(SORT(.text.sorted.*)) *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf32.em. */ + /* .gnu.warning sections are handled specially by elf.em. */ *(.gnu.warning) } .fini : @@ -201,23 +203,9 @@ SECTIONS . = ALIGN(64 / 8); __BSS_END__ = .; __global_pointer = MIN(__SDATA_BEGIN__ + 0x800, - MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); + MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); _end = .; PROVIDE (end = .); - . = DATA_SEGMENT_END (.); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } - __stack_usage = SIZEOF(.stack_dummy); - PROVIDE(__stack_top = 0xFF000000); - PROVIDE(__stack_size = 0x400); - PROVIDE(__stack = __stack_top); - ASSERT(__stack_usage <= __stack_size, "stack overflow") - + . = DATA_SEGMENT_END (.); /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } diff --git a/runtime/src/tinyprintf.c b/kernel/src/tinyprintf.c similarity index 99% rename from runtime/src/tinyprintf.c rename to kernel/src/tinyprintf.c index 4c88ef29..c733e082 100644 --- a/runtime/src/tinyprintf.c +++ b/kernel/src/tinyprintf.c @@ -887,4 +887,4 @@ int tiny_vprintf(const char* format, va_list va) { int tiny_vsnprintf(char* buffer, size_t count, const char* format, va_list va) { return _vsnprintf(_out_buffer, buffer, count, format, va); -} \ No newline at end of file +} diff --git a/runtime/src/tinyprintf.h b/kernel/src/tinyprintf.h similarity index 98% rename from runtime/src/tinyprintf.h rename to kernel/src/tinyprintf.h index 9aa79d9a..b142ef16 100644 --- a/runtime/src/tinyprintf.h +++ b/kernel/src/tinyprintf.h @@ -29,8 +29,8 @@ // /////////////////////////////////////////////////////////////////////////////// -#ifndef _TINYPRINTF_H_ -#define _TINYPRINTF_H_ +#ifndef __TINYPRINTF_H__ +#define __TINYPRINTF_H__ #include #include @@ -83,4 +83,4 @@ int tiny_vprintf(const char* format, va_list va); } #endif -#endif // _TINYPRINTF_H_ \ No newline at end of file +#endif // __TINYPRINTF_H__ diff --git a/kernel/src/vx_perf.c b/kernel/src/vx_perf.c new file mode 100644 index 00000000..b88615de --- /dev/null +++ b/kernel/src/vx_perf.c @@ -0,0 +1,49 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include +#include +#include +#include + +#define DUMP_CSR_4(d, s) \ + csr_mem[d + 0] = csr_read(s + 0); \ + csr_mem[d + 1] = csr_read(s + 1); \ + csr_mem[d + 2] = csr_read(s + 2); \ + csr_mem[d + 3] = csr_read(s + 3); + +#define DUMP_CSR_32(d, s) \ + DUMP_CSR_4(d + 0, s + 0) \ + DUMP_CSR_4(d + 4, s + 4) \ + DUMP_CSR_4(d + 8, s + 8) \ + DUMP_CSR_4(d + 12, s + 12) \ + DUMP_CSR_4(d + 16, s + 16) \ + DUMP_CSR_4(d + 20, s + 20) \ + DUMP_CSR_4(d + 24, s + 24) \ + DUMP_CSR_4(d + 28, s + 28) + +#ifdef __cplusplus +extern "C" { +#endif + +void vx_perf_dump() { + int core_id = vx_core_id(); + uint32_t* const csr_mem = (uint32_t*)(IO_CSR_ADDR + 64 * sizeof(uint32_t) * core_id); + DUMP_CSR_32(0, VX_CSR_MPM_BASE) + DUMP_CSR_32(32, VX_CSR_MPM_BASE_H) +} + +#ifdef __cplusplus +} +#endif diff --git a/kernel/src/vx_print.S b/kernel/src/vx_print.S new file mode 100644 index 00000000..7e883df0 --- /dev/null +++ b/kernel/src/vx_print.S @@ -0,0 +1,32 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +.type vx_putchar, @function +.global vx_putchar +vx_putchar: + csrr t0, VX_CSR_MHARTID + andi t0, t0, %lo(IO_COUT_SIZE-1) +#if (XLEN == 64) + li t1, (IO_COUT_ADDR >> 32) + slli t1, t1, 32 + li t2, (IO_COUT_ADDR & 0xffffffff) + or t1, t1, t2 +#else + li t1, IO_COUT_ADDR +#endif + add t0, t0, t1 + sb a0, 0(t0) + ret diff --git a/runtime/src/vx_print.c b/kernel/src/vx_print.c similarity index 75% rename from runtime/src/vx_print.c rename to kernel/src/vx_print.c index e75993e2..488cdd9f 100644 --- a/runtime/src/vx_print.c +++ b/kernel/src/vx_print.c @@ -1,3 +1,16 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include #include #include @@ -91,4 +104,4 @@ int vx_printf(const char * format, ...) { #ifdef __cplusplus } -#endif \ No newline at end of file +#endif diff --git a/kernel/src/vx_serial.S b/kernel/src/vx_serial.S new file mode 100644 index 00000000..eeb1c503 --- /dev/null +++ b/kernel/src/vx_serial.S @@ -0,0 +1,77 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +#define RISCV_CUSTOM0 0x0B + +.type vx_serial, @function +.global vx_serial +vx_serial: +#if (XLEN == 64) + addi sp, sp, -56 + sd ra, 48(sp) + sd s5, 40(sp) + sd s4, 32(sp) + sd s3, 24(sp) + sd s2, 16(sp) + sd s1, 8(sp) + sd s0, 0(sp) +#else + addi sp, sp, -28 + sw ra, 24(sp) + sw s5, 20(sp) + sw s4, 16(sp) + sw s3, 12(sp) + sw s2, 8(sp) + sw s1, 4(sp) + sw s0, 0(sp) +#endif + mv s4, a0 # s4 <- callback + mv s3, a1 # s3 <- arg + csrr s2, VX_CSR_NUM_THREADS # s2 <- NT + csrr s1, VX_CSR_THREAD_ID # s1 <- tid + li s0, 0 # s0 <- index +label_loop: + sub t0, s0, s1 + seqz t1, t0 # (index != tid) + .insn r RISCV_CUSTOM0, 2, 0, s5, t1, x0 # split s5, t0 + bnez t0, label_join + mv a0, s3 # a0 <- arg + jalr s4 # callback(arg) +label_join: + .insn r RISCV_CUSTOM0, 3, 0, x0, s5, x0 # join s5 + addi s0, s0, 1 # index++ + blt s0, s2, label_loop # loop back +#if (XLEN == 64) + ld ra, 48(sp) + ld s5, 40(sp) + ld s4, 32(sp) + ld s3, 24(sp) + ld s2, 16(sp) + ld s1, 8(sp) + ld s0, 0(sp) + addi sp, sp, 56 +#else + lw ra, 24(sp) + lw s5, 20(sp) + lw s4, 16(sp) + lw s3, 12(sp) + lw s2, 8(sp) + lw s1, 4(sp) + lw s0, 0(sp) + addi sp, sp, 28 +#endif + ret + diff --git a/kernel/src/vx_spawn.c b/kernel/src/vx_spawn.c new file mode 100644 index 00000000..14773707 --- /dev/null +++ b/kernel/src/vx_spawn.c @@ -0,0 +1,334 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define NUM_CORES_MAX 1024 + +#ifndef MIN +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +typedef struct { + vx_spawn_tasks_cb callback; + void* arg; + int offset; // task offset + int NWs; // number of NW batches where NW=. + int RWs; // number of remaining warps in the core +} wspawn_tasks_args_t; + +typedef struct { + context_t * ctx; + vx_spawn_kernel_cb callback; + void* arg; + int offset; // task offset + int NWs; // number of NW batches where NW=. + int RWs; // number of remaining warps in the core + char isXYpow2; + char log2XY; + char log2X; +} wspawn_kernel_args_t; + +void* g_wspawn_args[NUM_CORES_MAX]; + +inline char is_log2(int x) { + return ((x & (x-1)) == 0); +} + +inline int fast_log2(int x) { + float f = x; + return (*(int*)(&f)>>23) - 127; +} + +static void __attribute__ ((noinline)) spawn_tasks_all_stub() { + int NT = vx_num_threads(); + int cid = vx_core_id(); + int wid = vx_warp_id(); + int tid = vx_thread_id(); + + wspawn_tasks_args_t* p_wspawn_args = (wspawn_tasks_args_t*)g_wspawn_args[cid]; + + int wK = (p_wspawn_args->NWs * wid) + MIN(p_wspawn_args->RWs, wid); + int tK = p_wspawn_args->NWs + (wid < p_wspawn_args->RWs); + int offset = p_wspawn_args->offset + (wK * NT) + (tid * tK); + + vx_spawn_tasks_cb callback = p_wspawn_args->callback; + void* arg = p_wspawn_args->arg; + for (int task_id = offset, N = task_id + tK; task_id < N; ++task_id) { + callback(task_id, arg); + } +} + +static void __attribute__ ((noinline)) spawn_tasks_rem_stub() { + int cid = vx_core_id(); + int tid = vx_thread_id(); + + wspawn_tasks_args_t* p_wspawn_args = (wspawn_tasks_args_t*)g_wspawn_args[cid]; + int task_id = p_wspawn_args->offset + tid; + (p_wspawn_args->callback)(task_id, p_wspawn_args->arg); +} + +static void __attribute__ ((noinline)) spawn_tasks_all_cb() { + // activate all threads + vx_tmc(-1); + + // call stub routine + spawn_tasks_all_stub(); + + // disable warp + vx_tmc_zero(); +} + +void vx_spawn_tasks(int num_tasks, vx_spawn_tasks_cb callback , void * arg) { + // device specs + int NC = vx_num_cores(); + int NW = vx_num_warps(); + int NT = vx_num_threads(); + + // current core id + int core_id = vx_core_id(); + if (core_id >= NUM_CORES_MAX) + return; + + // calculate necessary active cores + int WT = NW * NT; + int nC = (num_tasks > WT) ? (num_tasks / WT) : 1; + int nc = MIN(nC, NC); + if (core_id >= nc) + return; // terminate extra cores + + // number of tasks per core + int tasks_per_core = num_tasks / nc; + int tasks_per_core_n1 = tasks_per_core; + if (core_id == (nc-1)) { + int rem = num_tasks - (nc * tasks_per_core); + tasks_per_core_n1 += rem; // last core also executes remaining tasks + } + + // number of tasks per warp + int TW = tasks_per_core_n1 / NT; // occupied warps + int rT = tasks_per_core_n1 - TW * NT; // remaining threads + int fW = 1, rW = 0; + if (TW >= NW) { + fW = TW / NW; // full warps iterations + rW = TW - fW * NW; // remaining warps + } + + wspawn_tasks_args_t wspawn_args = { callback, arg, core_id * tasks_per_core, fW, rW }; + g_wspawn_args[core_id] = &wspawn_args; + + if (TW >= 1) { + // execute callback on other warps + int nw = MIN(TW, NW); + vx_wspawn(nw, spawn_tasks_all_cb); + + // activate all threads + vx_tmc(-1); + + // call stub routine + spawn_tasks_all_stub(); + + // back to single-threaded + vx_tmc_one(); + + // wait for spawn warps to terminate + vx_wspawn_wait(); + } + + if (rT != 0) { + // adjust offset + wspawn_args.offset += (tasks_per_core_n1 - rT); + + // activate remaining threads + int tmask = (1 << rT) - 1; + vx_tmc(tmask); + + // call stub routine + spawn_tasks_rem_stub(); + + // back to single-threaded + vx_tmc_one(); + } +} + +/////////////////////////////////////////////////////////////////////////////// + +static void __attribute__ ((noinline)) spawn_kernel_all_stub() { + int NT = vx_num_threads(); + int cid = vx_core_id(); + int wid = vx_warp_id(); + int tid = vx_thread_id(); + + wspawn_kernel_args_t* p_wspawn_args = (wspawn_kernel_args_t*)g_wspawn_args[cid]; + + int wK = (p_wspawn_args->NWs * wid) + MIN(p_wspawn_args->RWs, wid); + int tK = p_wspawn_args->NWs + (wid < p_wspawn_args->RWs); + int offset = p_wspawn_args->offset + (wK * NT) + (tid * tK); + + int X = p_wspawn_args->ctx->num_groups[0]; + int Y = p_wspawn_args->ctx->num_groups[1]; + int XY = X * Y; + + if (p_wspawn_args->isXYpow2) { + for (int wg_id = offset, N = wg_id + tK; wg_id < N; ++wg_id) { + int k = wg_id >> p_wspawn_args->log2XY; + int wg_2d = wg_id - k * XY; + int j = wg_2d >> p_wspawn_args->log2X; + int i = wg_2d - j * X; + (p_wspawn_args->callback)(p_wspawn_args->arg, p_wspawn_args->ctx, i, j, k); + } + } else { + for (int wg_id = offset, N = wg_id + tK; wg_id < N; ++wg_id) { + int k = wg_id / XY; + int wg_2d = wg_id - k * XY; + int j = wg_2d / X; + int i = wg_2d - j * X; + (p_wspawn_args->callback)(p_wspawn_args->arg, p_wspawn_args->ctx, i, j, k); + } + } +} + +static void __attribute__ ((noinline)) spawn_kernel_rem_stub() { + int cid = vx_core_id(); + int tid = vx_thread_id(); + + wspawn_kernel_args_t* p_wspawn_args = (wspawn_kernel_args_t*)g_wspawn_args[cid]; + + int wg_id = p_wspawn_args->offset + tid; + + int X = p_wspawn_args->ctx->num_groups[0]; + int Y = p_wspawn_args->ctx->num_groups[1]; + int XY = X * Y; + + if (p_wspawn_args->isXYpow2) { + int k = wg_id >> p_wspawn_args->log2XY; + int wg_2d = wg_id - k * XY; + int j = wg_2d >> p_wspawn_args->log2X; + int i = wg_2d - j * X; + (p_wspawn_args->callback)(p_wspawn_args->arg, p_wspawn_args->ctx, i, j, k); + } else { + int k = wg_id / XY; + int wg_2d = wg_id - k * XY; + int j = wg_2d / X; + int i = wg_2d - j * X; + (p_wspawn_args->callback)(p_wspawn_args->arg, p_wspawn_args->ctx, i, j, k); + } +} + +static void __attribute__ ((noinline)) spawn_kernel_all_cb() { + // activate all threads + vx_tmc(-1); + + // call stub routine + spawn_kernel_all_stub(); + + // disable warp + vx_tmc_zero(); +} + +void vx_spawn_kernel(context_t * ctx, vx_spawn_kernel_cb callback, void * arg) { + // total number of WGs + int X = ctx->num_groups[0]; + int Y = ctx->num_groups[1]; + int Z = ctx->num_groups[2]; + int XY = X * Y; + int num_tasks = XY * Z; + + // device specs + int NC = vx_num_cores(); + int NW = vx_num_warps(); + int NT = vx_num_threads(); + + // current core id + int core_id = vx_core_id(); + if (core_id >= NUM_CORES_MAX) + return; + + // calculate necessary active cores + int WT = NW * NT; + int nC = (num_tasks > WT) ? (num_tasks / WT) : 1; + int nc = MIN(nC, NC); + if (core_id >= nc) + return; // terminate extra cores + + // number of tasks per core + int tasks_per_core = num_tasks / nc; + int tasks_per_core_n1 = tasks_per_core; + if (core_id == (nc-1)) { + int rem = num_tasks - (nc * tasks_per_core); + tasks_per_core_n1 += rem; // last core also executes remaining WGs + } + + // number of tasks per warp + int TW = tasks_per_core_n1 / NT; // occupied warps + int rT = tasks_per_core_n1 - TW * NT; // remaining threads + int fW = 1, rW = 0; + if (TW >= NW) { + fW = TW / NW; // full warps iterations + rW = TW - fW * NW; // remaining warps + } + + // fast path handling + char isXYpow2 = is_log2(XY); + char log2XY = fast_log2(XY); + char log2X = fast_log2(X); + + wspawn_kernel_args_t wspawn_args = { + ctx, callback, arg, core_id * tasks_per_core, fW, rW, isXYpow2, log2XY, log2X + }; + g_wspawn_args[core_id] = &wspawn_args; + + if (TW >= 1) { + // execute callback on other warps + int nw = MIN(TW, NW); + vx_wspawn(nw, spawn_kernel_all_cb); + + // activate all threads + vx_tmc(-1); + + // call stub routine + asm volatile("" ::: "memory"); + spawn_kernel_all_stub(); + + // back to single-threaded + vx_tmc_one(); + + // wait for spawn warps to terminate + vx_wspawn_wait(); + } + + if (rT != 0) { + // adjust offset + wspawn_args.offset += (tasks_per_core_n1 - rT); + + // activate remaining threads + int tmask = (1 << rT) - 1; + vx_tmc(tmask); + + // call stub routine + spawn_kernel_rem_stub(); + + // back to single-threaded + vx_tmc_one(); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/kernel/src/vx_start.S b/kernel/src/vx_start.S new file mode 100644 index 00000000..b5065c95 --- /dev/null +++ b/kernel/src/vx_start.S @@ -0,0 +1,150 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +#define RISCV_CUSTOM0 0x0B + +.section .init, "ax" +.global _start +.type _start, @function +_start: + + # initialize per-thread registers + csrr t0, VX_CSR_NUM_WARPS # get num warps + la t1, init_regs_all + .insn r RISCV_CUSTOM0, 1, 0, x0, t0, t1 # wspawn t0, t1 + li t0, -1 + .insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0 + jal init_regs + li t0, 1 + .insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0 + + # wait for spawn warps to terminate + jal vx_wspawn_wait + + # initialize TLS for all warps + csrr t0, VX_CSR_NUM_WARPS # get num warps + la t1, init_tls_all + .insn r RISCV_CUSTOM0, 1, 0, x0, t0, t1 # wspawn t0, t1 + li t0, -1 + .insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0 + call __init_tls + li t0, 1 + .insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0 + + # wait for spawn warps to terminate + jal vx_wspawn_wait + + # clear BSS segment + la a0, _edata + la a2, _end + sub a2, a2, a0 + li a1, 0 + call memset + + # initialize trap vector + # la t0, trap_entry + # csrw mtvec, t0 + + # register global termination functions + la a0, __libc_fini_array + call atexit + + # run global initialization functions + call __libc_init_array + + # call main program routine + call main + + # call exit routine + tail exit +.size _start, .-_start + +.section .text +.type _exit, @function +.global _exit +_exit: + mv s0, a0 + call vx_perf_dump + mv gp, s0 + .insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0 # tmc x0 + +.section .text +.type init_regs, @function +.local init_regs +init_regs: + # set global pointer register + .option push + .option norelax + la gp, __global_pointer + .option pop + + # set stack pointer register +#if (XLEN == 64) + li t0, (STACK_BASE_ADDR >> 32) + slli t0, t0, 32 + li sp, (STACK_BASE_ADDR & 0xffffffff) + or sp, sp, t0 +#else + li sp, STACK_BASE_ADDR # load stack base address +#endif + csrr t0, VX_CSR_MHARTID + sll t1, t0, STACK_LOG2_SIZE + sub sp, sp, t1 + + # set thread pointer register + # use address space after BSS region + # ensure cache line alignment + la t1, __tcb_aligned_size + mul t0, t0, t1 + la tp, _end + 63 + add tp, tp, t0 + and tp, tp, -64 + ret + +.section .text +.type init_regs_all, @function +.local init_regs_all +init_regs_all: + li t0, -1 + .insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0 + jal init_regs + .insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0 # tmc x0 + ret + +.section .text +.type init_tls_all, @function +.local init_tls_all +init_tls_all: + li t0, -1 + .insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0 + call __init_tls + .insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0 # tmc x0 + ret + +.section .text +.type vx_wspawn_wait, @function +.global vx_wspawn_wait +vx_wspawn_wait: + csrr t0, VX_CSR_WARP_MASK + li t1, 1 + bne t0, t1, vx_wspawn_wait + ret + +.section .data + .global __dso_handle + .weak __dso_handle +__dso_handle: + .long 0 diff --git a/runtime/src/vx_syscalls.c b/kernel/src/vx_syscalls.c similarity index 76% rename from runtime/src/vx_syscalls.c rename to kernel/src/vx_syscalls.c index fcd8b26f..97e49fb1 100644 --- a/runtime/src/vx_syscalls.c +++ b/kernel/src/vx_syscalls.c @@ -1,9 +1,26 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include #include #include #include #include #include + +#ifdef __cplusplus +extern "C" { +#endif int _close(int file) { return -1; } @@ -33,7 +50,7 @@ int _write(int file, char *ptr, int len) { int _kill(int pid, int sig) { return -1; } int _getpid() { - return vx_warp_gid(); + return vx_hart_id(); } void __init_tls(void) { @@ -42,19 +59,13 @@ void __init_tls(void) { extern char __tdata_size[]; extern char __tbss_size[]; - // activate all threads - vx_tmc(-1); - // TLS memory initialization register char *__thread_self __asm__ ("tp"); memcpy(__thread_self, __tdata_start, (size_t)__tdata_size); memset(__thread_self + (size_t)__tbss_offset, 0, (size_t)__tbss_size); - - // back to single thread execution - vx_tmc(0 == vx_warp_id()); } - #ifdef HAVE_INITFINI_ARRAY +#ifdef HAVE_INITFINI_ARRAY /* These magic symbols are provided by the linker. */ extern void (*__preinit_array_start []) (void) __attribute__((weak)); @@ -106,4 +117,8 @@ void __libc_fini_array (void) { _fini (); #endif } -#endif \ No newline at end of file +#endif + +#ifdef __cplusplus +} +#endif diff --git a/miscs/docker/pocl/Dockerfile b/miscs/docker/pocl/Dockerfile index decad2a1..c259bbfa 100644 --- a/miscs/docker/pocl/Dockerfile +++ b/miscs/docker/pocl/Dockerfile @@ -13,8 +13,8 @@ ARG LLVM_HOME=/opt/llvm-10 ARG POCL_CC_PATH=/opt/pocl_cc ARG POCL_RT_PATH=/opt/pocl_rt ARG VORTEX_HOME=/home/vortex -ARG VORTEX_DRIVER_INC=$VORTEX_HOME/driver/sw/include -ARG VORTEX_DRIVER_LIB=$VORTEX_HOME/driver/sw/stub/libvortex.so +ARG VORTEX_RUNTIME_INC=$VORTEX_HOME/runtime/sw/include +ARG VORTEX_RUNTIME_LIB=$VORTEX_HOME/runtime/sw/stub/libvortex.so ARG VORTEX_RUNTIME_PATH=$VORTEX_HOME/runtime # system update @@ -65,13 +65,13 @@ RUN git clone https://$LOGIN@github.gatech.edu/casl/pocl.git /tmp/pocl RUN cd /tmp/pocl; \ mkdir build_cc RUN cd /tmp/pocl/build_cc; \ - cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_CC_PATH -DOCS_AVAILABLE=ON -DWITH_LLVM_CONFIG=$LLVM_HOME/bin/llvm-config -DENABLE_VORTEX=ON -DVORTEX_RUNTIME_PATH=$VORTEX_RUNTIME_PATH -DVORTEX_DRIVER_INC=$VORTEX_DRIVER_INC -DVORTEX_DRIVER_LIB=$VORTEX_DRIVER_LIB -DBUILD_TESTS=OFF -DPOCL_DEBUG_MESSAGES=ON .. + cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_CC_PATH -DOCS_AVAILABLE=ON -DWITH_LLVM_CONFIG=$LLVM_HOME/bin/llvm-config -DENABLE_VORTEX=ON -DVORTEX_RUNTIME_PATH=$VORTEX_RUNTIME_PATH -DVORTEX_RUNTIME_INC=$VORTEX_RUNTIME_INC -DVORTEX_RUNTIME_LIB=$VORTEX_RUNTIME_LIB -DBUILD_TESTS=OFF -DPOCL_DEBUG_MESSAGES=ON .. RUN cd /tmp/pocl/build_cc; \ cmake --build . --target install RUN cd /tmp/pocl; \ mkdir build_rt RUN cd /tmp/pocl/build_rt; \ - cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_RT_PATH -DOCS_AVAILABLE=OFF -DHOST_DEVICE_BUILD_HASH=riscv32-unknown-unknown-elf -DENABLE_VORTEX=ON -DVORTEX_RUNTIME_PATH=$VORTEX_RUNTIME_PATH -DVORTEX_DRIVER_INC=$VORTEX_DRIVER_INC -DVORTEX_DRIVER_LIB=$VORTEX_DRIVER_LIB -DBUILD_TESTS=OFF -DPOCL_DEBUG_MESSAGES=ON .. + cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_RT_PATH -DOCS_AVAILABLE=OFF -DHOST_DEVICE_BUILD_HASH=riscv32-unknown-unknown-elf -DENABLE_VORTEX=ON -DVORTEX_RUNTIME_PATH=$VORTEX_RUNTIME_PATH -DVORTEX_RUNTIME_INC=$VORTEX_RUNTIME_INC -DVORTEX_RUNTIME_LIB=$VORTEX_RUNTIME_LIB -DBUILD_TESTS=OFF -DPOCL_DEBUG_MESSAGES=ON .. RUN cd /tmp/pocl/build_rt; \ cmake --build . --target install RUN rm -rf /tmp/pocl diff --git a/miscs/rvvector/basic/Makefile b/miscs/rvvector/basic/Makefile deleted file mode 100644 index 66aece0c..00000000 --- a/miscs/rvvector/basic/Makefile +++ /dev/null @@ -1,41 +0,0 @@ - -LIB_PATH = ../../runtime - - -COMP = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-gcc - -CC_FLAGS = -ffreestanding -O0 -Wl,--gc-sections -nostartfiles -nostdlib -nostartfiles -nodefaultlibs -Wl,-Bstatic,-T,$(LIB_PATH)/startup/vx_link.ld -march=rv32imv -mabi=ilp32 - -DMP = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-objdump -CPY = /home/fares/dev/riscv-gnu-toolchain-vector/drops/bin/riscv32-unknown-elf-objcopy - -# VX_STR = ../../startup/vx_start.S - - - -NEWLIB = $(LIB_PATH)/newlib/newlib.c -VX_STR = $(LIB_PATH)/startup/vx_start.S -VX_INT = $(LIB_PATH)/intrinsics/vx_intrinsics.S -VX_IO = $(LIB_PATH)/io/vx_io.S $(LIB_PATH)/io/vx_io.c -VX_API = $(LIB_PATH)/vx_api/vx_api.c -VX_FIO = $(LIB_PATH)/fileio/fileio.S -VX_VEC = vx_vec.s -LIBS = /home/fares/dev/riscv-gnu-toolchain-vector/drops/riscv32-unknown-elf/lib/libc.a /home/fares/dev/riscv-gnu-toolchain-vector/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc - -VX_MAIN = vx_vector_main - -all: HEX DUMP ELF - -DUMP: ELF - $(DMP) -D $(VX_MAIN).elf > $(VX_MAIN).dump - -HEX: ELF - $(CPY) -O ihex $(VX_MAIN).elf $(VX_MAIN).hex - -ELF: - $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf - -run: - ../../simx/obj_dir/Vcache_simX -E -a rv32i --core vx_vector_main.hex -s -b 1> emulator.debug - - diff --git a/miscs/rvvector/basic/_1_vx_vec.s b/miscs/rvvector/basic/_1_vx_vec.s deleted file mode 100644 index 661e6339..00000000 --- a/miscs/rvvector/basic/_1_vx_vec.s +++ /dev/null @@ -1,30 +0,0 @@ - - - -.type vx_vec_test, @function -.global vx_vec_test -vx_vec_test: - li a1, 7 - sw a1, 0(a0) - ret - - - - -# slli a0, a0, 2 -# add a0, a0, a3 -# vmv.v.x vv0, a2 -# # vsplat4 vv0, a2 -# stripmine_loop: -# vlb4 vv1, (a1) -# vcmpez4 vp0, vv1 -# !vp0 vlw4 vv1, (a3) -# !vp0 vlw4 vv2, (a4) -# !vp0 vfma4 vv1, vv0, vv1, vv2 -# !vp0 vsw4 vv1, (a4) -# addi a1, a1, 4 -# addi a3, a3, 16 -# addi a4, a4, 16 -# bleu a3, a0, stripmine_loop - # handle edge cases - # when (n % 4) != 0 ... diff --git a/miscs/rvvector/basic/_1_vx_vector_main.c b/miscs/rvvector/basic/_1_vx_vector_main.c deleted file mode 100644 index fb8cc688..00000000 --- a/miscs/rvvector/basic/_1_vx_vector_main.c +++ /dev/null @@ -1,32 +0,0 @@ - -#include "../../runtime/intrinsics/vx_intrinsics.h" -#include "vx_vec.h" - -int main() -{ - vx_tmc(1); - // int * a = malloc(4); - // int * b = malloc(4); - // int * c = malloc(4); - - - int * a = malloc(4); - *a = 5; - printf("Value of a: %d\n", *a); - - vx_vec_test(a); - - printf("Value of a: %d\n", *a); - - - // for (int i = 0; i < 4; i++) - // { - // if (c[i] != (a[i] + b[i])) - // { - // printf("Fail\n"); - // break; - // } - // } - - vx_tmc(0); -} \ No newline at end of file diff --git a/miscs/rvvector/basic/__vx_vector_main.c b/miscs/rvvector/basic/__vx_vector_main.c deleted file mode 100644 index 5e4724e1..00000000 --- a/miscs/rvvector/basic/__vx_vector_main.c +++ /dev/null @@ -1,91 +0,0 @@ -#include -#include -#include "../../runtime/intrinsics/vx_intrinsics.h" -#include "vx_vec.h" - -int main() -{ - vx_tmc(1); -#if 0 - # vector-vector add routine of 32-bit integers - # void vvaddint32(size_t n, const int*x, const int*y, int*z) - # { for (size_t i=0; i int -VX_VEC3 = vx_vec_sgemm_float.s #float --> int -VX_VEC4 = vx_vec_vsadd.s -VX_VEC5 = vx_vec_memcpy.s -LIBS = /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libc.a /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc - -VX_MAIN = vx_vec_benchmark - -all: HEX DUMP ELF - -DUMP: ELF - $(DMP) -D $(VX_MAIN).elf > $(VX_MAIN).dump - -HEX: ELF - $(CPY) -O ihex $(VX_MAIN).elf $(VX_MAIN).hex - -ELF: - $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC2) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf -# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC3) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf -# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC4) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf -# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC5) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf~ diff --git a/miscs/rvvector/benchmark_temp/TO_DO_LIST b/miscs/rvvector/benchmark_temp/TO_DO_LIST deleted file mode 100644 index 28a9d57b..00000000 --- a/miscs/rvvector/benchmark_temp/TO_DO_LIST +++ /dev/null @@ -1,9 +0,0 @@ -1. add benchmarks under (Vortex/benchmarks/..) - 1.1 bfs --> blas spmv approach - 1.2 kmeans // stage 2 - 1.3 saxpy --> sample - 1.4 sfilter // stage 2 - 1.5 sgemm --> sample modify (float --> int) - 1.6 vecadd --> sample - - diff --git a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.c b/miscs/rvvector/benchmark_temp/vx_vec_benchmark.c deleted file mode 100644 index 90c4f968..00000000 --- a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.c +++ /dev/null @@ -1,177 +0,0 @@ -#include -#include -#include "../../runtime/intrinsics/vx_intrinsics.h" -#include "vx_vec_benchmark.h" - -int main() -{ - vx_tmc(1); - - int n = 5; - int scalar = 10; - - int *a = (int*)malloc(sizeof(int) * n); //{1, 1, 1, 1, 1}; - int *b = (int*)malloc(sizeof(int) * n); //{1, 1, 1, 1, 1}; - int *c = (int*)malloc(sizeof(int) * n); //{1, 1, 1, 1, 1}; - - for (int i = 0; i < n; ++i) { a[i] = 1; b[i] = 2; c[i] = 5; } - -#if 0 -//--------------------------------------------------------------- -/* vvaddint32 - * # vector-vector add routine of 32-bit integers - * # void vvaddint32(size_t n, const int*x, const int*y, int*z) - * # { for (size_t i=0; i failed at ! \n", i); - return 1; - } - } - printf("\nPASSED.......................... \n"); -#endif -#if 0 -//--------------------------------------------------------------- -/* # vector-scalar add - # for (i=0; i failed at ! \n", i); - return 1; - } - } - printf("\nPASSED.......................... \n"); - -#endif -#if 0 -//--------------------------------------------------------------- -/* # memory copy - # void *memcpy(void* dest, const void* src, size_t n) */ - for (int i = 0; i < n; ++i) { a[i] = 1; b[i] = 2;} - printf("memcpy\na[%d]: ", n); - for(int i = 0; i < n; ++i) printf("%d \n", a[i]); - printf("\nb[%d]: ", n); - for(int i = 0; i < n; ++i) printf("%d \n", b[i]); - - vx_vec_memcpy(a, b, n); - - for(int i = 0; i < n; ++i) - { - if(a[i] != b[i]) - { - printf("\n failed at ! \n", i); -<<<<<<< HEAD - return; - } - } - printf("\nPASSED.......................... \n"); -======= - return 1; - } - } - printf("\nPASSED.......................... \n"); -#endif -#if 1 -//--------------------------------------------------------------- -/* # void saxpy(size_t n, const float a, const float *x, float *y) - # ==> convert to int!! - # void saxpy(size_t n, const int a, const int *x, int *y) - # { - # size_t i; - # for (i=0; i failed at ! \n", i); - return; - } - } - printf("\nPASSED.......................... \n"); - - return 1; - } - } - printf("\nPASSED.......................... \n"); -#endif -#if 0 -//--------------------------------------------------------------- -/* # void sgemm_nn(size_t n, size_t m, size_t k, const float*a, // m * k matrix -# size_t lda, const float*b, // k * n matrix -# size_t ldb, float*c, // m * n matrix -# size_t ldc) -# c += a*b (alpha=1, no transpose on input matrices) -# matrices stored in C row-major order */ - - int m = 8; - int k = 8; - int n = 8 - int lda = 4; - int ldb = 4; - int ldc = 4; - - int* a1 = (int*)malloc(sizeof(m * k)); - int* b1 = (int*)malloc(sizeof(k * n)); - int* c1 = (int*)malloc(sizeof(m * n)); - - for(int i = 0; i < (m * k); ++i) a1[i] = 1; - for(int i = 0; i < (k * n); ++i) b1[i] = 1; - for(int i = 0; i < (m * n); ++i) c1[i] = 1; - - printf("sgemm_nn\na[%d]: ", n); - for(int i = 0; i < n; ++i) printf("%d \n", a1[i]); - printf("\nb[%d]: ", n); - for(int i = 0; i < n; ++i) printf("%d \n", b1[i]); - - vx_vec_sgemm_nn(n, m, k, a1, lda, b1, ldb, c1, ldc); - - //for(int i = 0; i < n; ++i) - //{ - // if(b[i] != ((a[i] * scalar) + c[i])) - // { - // printf("\n failed at ! \n", i); - // return; - // } - //} - printf("\nNOT TESTED.......................... \n"); -//--------------------------------------------------------------- -#endif - - vx_tmc(0); - return 0; -} diff --git a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.dump b/miscs/rvvector/benchmark_temp/vx_vec_benchmark.dump deleted file mode 100644 index ead5855f..00000000 --- a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.dump +++ /dev/null @@ -1,87070 +0,0 @@ - -vx_vec_benchmark.elf: file format elf32-littleriscv - - -Disassembly of section .init: - -80000000 <_start>: -80000000: 00000597 auipc a1,0x0 -80000004: 06458593 addi a1,a1,100 # 80000064 -80000008: 02000513 li a0,32 -8000000c: 00b5106b 0xb5106b -80000010: 054000ef jal ra,80000064 -80000014: 00100513 li a0,1 -80000018: 0005006b 0x5006b -8000001c: 1d418513 addi a0,gp,468 # 80016d3c <_edata> -80000020: 21018613 addi a2,gp,528 # 80016d78 <__BSS_END__> -80000024: 40a60633 sub a2,a2,a0 -80000028: 00000593 li a1,0 -8000002c: 490010ef jal ra,800014bc -80000030: 00001517 auipc a0,0x1 -80000034: bbc50513 addi a0,a0,-1092 # 80000bec <__libc_fini_array> -80000038: 371000ef jal ra,80000ba8 -8000003c: 411000ef jal ra,80000c4c <__libc_init_array> -80000040: 015000ef jal ra,80000854
-80000044: 3790006f j 80000bbc - -Disassembly of section .text: - -80000048 : -80000048: 000007b7 lui a5,0x0 -8000004c: 00078793 mv a5,a5 -80000050: 00078863 beqz a5,80000060 -80000054: 80001537 lui a0,0x80001 -80000058: bec50513 addi a0,a0,-1044 # 80000bec <__BSS_END__+0xfffe9e74> -8000005c: 34d0006f j 80000ba8 -80000060: 00008067 ret - -80000064 : -80000064: 02000513 li a0,32 -80000068: 0005006b 0x5006b -8000006c: 00017197 auipc gp,0x17 -80000070: afc18193 addi gp,gp,-1284 # 80016b68 <__global_pointer$> -80000074: 021026f3 csrr a3,0x21 -80000078: 01a69693 slli a3,a3,0x1a -8000007c: 02002673 csrr a2,0x20 -80000080: 00a61593 slli a1,a2,0xa -80000084: 00261613 slli a2,a2,0x2 -80000088: 6ffff137 lui sp,0x6ffff -8000008c: 40b10133 sub sp,sp,a1 -80000090: 40d10133 sub sp,sp,a3 -80000094: 00c10133 add sp,sp,a2 -80000098: 021026f3 csrr a3,0x21 -8000009c: 00068663 beqz a3,800000a8 -800000a0: 00000513 li a0,0 -800000a4: 0005006b 0x5006b - -800000a8 : -800000a8: 00008067 ret - -800000ac : -800000ac: 00857757 vsetvli a4,a0,e32,m1,d1 - -800000b0 : -800000b0: 12066007 vlw.v v0,(a2) -800000b4: 40e50533 sub a0,a0,a4 -800000b8: 00271713 slli a4,a4,0x2 -800000bc: 00e60633 add a2,a2,a4 -800000c0: 1206e087 vlw.v v1,(a3) -800000c4: 9605e057 vmul.vx v0,v0,a1 -800000c8: 020080d7 vadd.vv v1,v0,v1 -800000cc: 0206e0a7 vsw.v v1,(a3) -800000d0: 00e686b3 add a3,a3,a4 -800000d4: fc051ee3 bnez a0,800000b0 -800000d8: 00008067 ret - -800000dc : -800000dc: fd010113 addi sp,sp,-48 # 6fffefd0 <_start-0x10001030> -800000e0: 02812623 sw s0,44(sp) -800000e4: 03010413 addi s0,sp,48 -800000e8: fca42e23 sw a0,-36(s0) -800000ec: fcb42c23 sw a1,-40(s0) -800000f0: fcc42a23 sw a2,-44(s0) -800000f4: fdc42783 lw a5,-36(s0) -800000f8: 0007a783 lw a5,0(a5) # 0 <_start-0x80000000> -800000fc: fef42623 sw a5,-20(s0) -80000100: fd440793 addi a5,s0,-44 -80000104: fef42223 sw a5,-28(s0) -80000108: fe442783 lw a5,-28(s0) -8000010c: 0007c703 lbu a4,0(a5) -80000110: fec42783 lw a5,-20(s0) -80000114: 00e78023 sb a4,0(a5) -80000118: fec42783 lw a5,-20(s0) -8000011c: 00178793 addi a5,a5,1 -80000120: fe442703 lw a4,-28(s0) -80000124: 00174703 lbu a4,1(a4) -80000128: 00e78023 sb a4,0(a5) -8000012c: fec42783 lw a5,-20(s0) -80000130: 00278793 addi a5,a5,2 -80000134: fe442703 lw a4,-28(s0) -80000138: 00274703 lbu a4,2(a4) -8000013c: 00e78023 sb a4,0(a5) -80000140: fec42783 lw a5,-20(s0) -80000144: 00378793 addi a5,a5,3 -80000148: fe442703 lw a4,-28(s0) -8000014c: 00374703 lbu a4,3(a4) -80000150: 00e78023 sb a4,0(a5) -80000154: fec42783 lw a5,-20(s0) -80000158: 00478793 addi a5,a5,4 -8000015c: fef42623 sw a5,-20(s0) -80000160: fe042423 sw zero,-24(s0) -80000164: 0340006f j 80000198 -80000168: fe842783 lw a5,-24(s0) -8000016c: fd842703 lw a4,-40(s0) -80000170: 00f707b3 add a5,a4,a5 -80000174: 0007c703 lbu a4,0(a5) -80000178: fec42783 lw a5,-20(s0) -8000017c: 00e78023 sb a4,0(a5) -80000180: fec42783 lw a5,-20(s0) -80000184: 00178793 addi a5,a5,1 -80000188: fef42623 sw a5,-20(s0) -8000018c: fe842783 lw a5,-24(s0) -80000190: 00178793 addi a5,a5,1 -80000194: fef42423 sw a5,-24(s0) -80000198: fd442783 lw a5,-44(s0) -8000019c: fe842703 lw a4,-24(s0) -800001a0: fcf744e3 blt a4,a5,80000168 -800001a4: fec42783 lw a5,-20(s0) -800001a8: fef42023 sw a5,-32(s0) -800001ac: fe042783 lw a5,-32(s0) -800001b0: 0037f793 andi a5,a5,3 -800001b4: fe042703 lw a4,-32(s0) -800001b8: 00f707b3 add a5,a4,a5 -800001bc: fef42023 sw a5,-32(s0) -800001c0: fe042783 lw a5,-32(s0) -800001c4: fef42623 sw a5,-20(s0) -800001c8: fdc42783 lw a5,-36(s0) -800001cc: fec42703 lw a4,-20(s0) -800001d0: 00e7a023 sw a4,0(a5) -800001d4: 00000013 nop -800001d8: 02c12403 lw s0,44(sp) -800001dc: 03010113 addi sp,sp,48 -800001e0: 00008067 ret - -800001e4 : -800001e4: fc010113 addi sp,sp,-64 -800001e8: 02812e23 sw s0,60(sp) -800001ec: 04010413 addi s0,sp,64 -800001f0: fca42623 sw a0,-52(s0) -800001f4: fcb42423 sw a1,-56(s0) -800001f8: fcc42783 lw a5,-52(s0) -800001fc: 0007a783 lw a5,0(a5) -80000200: fef42623 sw a5,-20(s0) -80000204: fdc40793 addi a5,s0,-36 -80000208: fef42223 sw a5,-28(s0) -8000020c: fec42783 lw a5,-20(s0) -80000210: 0007c703 lbu a4,0(a5) -80000214: fe442783 lw a5,-28(s0) -80000218: 00e78023 sb a4,0(a5) -8000021c: fe442783 lw a5,-28(s0) -80000220: 00178793 addi a5,a5,1 -80000224: fec42703 lw a4,-20(s0) -80000228: 00174703 lbu a4,1(a4) -8000022c: 00e78023 sb a4,0(a5) -80000230: fe442783 lw a5,-28(s0) -80000234: 00278793 addi a5,a5,2 -80000238: fec42703 lw a4,-20(s0) -8000023c: 00274703 lbu a4,2(a4) -80000240: 00e78023 sb a4,0(a5) -80000244: fe442783 lw a5,-28(s0) -80000248: 00378793 addi a5,a5,3 -8000024c: fec42703 lw a4,-20(s0) -80000250: 00374703 lbu a4,3(a4) -80000254: 00e78023 sb a4,0(a5) -80000258: fec42783 lw a5,-20(s0) -8000025c: 00478793 addi a5,a5,4 -80000260: fef42623 sw a5,-20(s0) -80000264: fe042423 sw zero,-24(s0) -80000268: 0340006f j 8000029c -8000026c: fe842783 lw a5,-24(s0) -80000270: fc842703 lw a4,-56(s0) -80000274: 00f707b3 add a5,a4,a5 -80000278: fec42703 lw a4,-20(s0) -8000027c: 00074703 lbu a4,0(a4) -80000280: 00e78023 sb a4,0(a5) -80000284: fec42783 lw a5,-20(s0) -80000288: 00178793 addi a5,a5,1 -8000028c: fef42623 sw a5,-20(s0) -80000290: fe842783 lw a5,-24(s0) -80000294: 00178793 addi a5,a5,1 -80000298: fef42423 sw a5,-24(s0) -8000029c: fdc42783 lw a5,-36(s0) -800002a0: fe842703 lw a4,-24(s0) -800002a4: fcf744e3 blt a4,a5,8000026c -800002a8: fec42783 lw a5,-20(s0) -800002ac: fef42023 sw a5,-32(s0) -800002b0: fe042783 lw a5,-32(s0) -800002b4: 0037f793 andi a5,a5,3 -800002b8: fe042703 lw a4,-32(s0) -800002bc: 00f707b3 add a5,a4,a5 -800002c0: fef42023 sw a5,-32(s0) -800002c4: fe042783 lw a5,-32(s0) -800002c8: fef42623 sw a5,-20(s0) -800002cc: fcc42783 lw a5,-52(s0) -800002d0: fec42703 lw a4,-20(s0) -800002d4: 00e7a023 sw a4,0(a5) -800002d8: 00000013 nop -800002dc: 03c12403 lw s0,60(sp) -800002e0: 04010113 addi sp,sp,64 -800002e4: 00008067 ret - -800002e8 <_close>: -800002e8: ff010113 addi sp,sp,-16 -800002ec: 00812623 sw s0,12(sp) -800002f0: 01010413 addi s0,sp,16 -800002f4: 00000013 nop -800002f8: 00c12403 lw s0,12(sp) -800002fc: 01010113 addi sp,sp,16 -80000300: 00008067 ret - -80000304 <_fstat>: -80000304: fe010113 addi sp,sp,-32 -80000308: 00812e23 sw s0,28(sp) -8000030c: 02010413 addi s0,sp,32 -80000310: fea42623 sw a0,-20(s0) -80000314: feb42423 sw a1,-24(s0) -80000318: fe842783 lw a5,-24(s0) -8000031c: 00002737 lui a4,0x2 -80000320: 00e7a223 sw a4,4(a5) -80000324: 00000793 li a5,0 -80000328: 00078513 mv a0,a5 -8000032c: 01c12403 lw s0,28(sp) -80000330: 02010113 addi sp,sp,32 -80000334: 00008067 ret - -80000338 <_isatty>: -80000338: fe010113 addi sp,sp,-32 -8000033c: 00812e23 sw s0,28(sp) -80000340: 02010413 addi s0,sp,32 -80000344: fea42623 sw a0,-20(s0) -80000348: 00100793 li a5,1 -8000034c: 00078513 mv a0,a5 -80000350: 01c12403 lw s0,28(sp) -80000354: 02010113 addi sp,sp,32 -80000358: 00008067 ret - -8000035c <_lseek>: -8000035c: fd010113 addi sp,sp,-48 -80000360: 02112623 sw ra,44(sp) -80000364: 02812423 sw s0,40(sp) -80000368: 03010413 addi s0,sp,48 -8000036c: fca42e23 sw a0,-36(s0) -80000370: fcb42c23 sw a1,-40(s0) -80000374: fcc42a23 sw a2,-44(s0) -80000378: 710007b7 lui a5,0x71000 -8000037c: fef42623 sw a5,-20(s0) -80000380: 720007b7 lui a5,0x72000 -80000384: fef42423 sw a5,-24(s0) -80000388: 00300793 li a5,3 -8000038c: fef42223 sw a5,-28(s0) -80000390: fe440713 addi a4,s0,-28 -80000394: fec40793 addi a5,s0,-20 -80000398: 00400613 li a2,4 -8000039c: 00070593 mv a1,a4 -800003a0: 00078513 mv a0,a5 -800003a4: d39ff0ef jal ra,800000dc -800003a8: fdc40713 addi a4,s0,-36 -800003ac: fec40793 addi a5,s0,-20 -800003b0: 00400613 li a2,4 -800003b4: 00070593 mv a1,a4 -800003b8: 00078513 mv a0,a5 -800003bc: d21ff0ef jal ra,800000dc -800003c0: fd840713 addi a4,s0,-40 -800003c4: fec40793 addi a5,s0,-20 -800003c8: 00400613 li a2,4 -800003cc: 00070593 mv a1,a4 -800003d0: 00078513 mv a0,a5 -800003d4: d09ff0ef jal ra,800000dc -800003d8: fd440713 addi a4,s0,-44 -800003dc: fec40793 addi a5,s0,-20 -800003e0: 00400613 li a2,4 -800003e4: 00070593 mv a1,a4 -800003e8: 00078513 mv a0,a5 -800003ec: cf1ff0ef jal ra,800000dc -800003f0: 1bc1a783 lw a5,444(gp) # 80016d24 -800003f4: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -800003f8: fe040713 addi a4,s0,-32 -800003fc: fe840793 addi a5,s0,-24 -80000400: 00070593 mv a1,a4 -80000404: 00078513 mv a0,a5 -80000408: dddff0ef jal ra,800001e4 -8000040c: fe042783 lw a5,-32(s0) -80000410: 00078513 mv a0,a5 -80000414: 02c12083 lw ra,44(sp) -80000418: 02812403 lw s0,40(sp) -8000041c: 03010113 addi sp,sp,48 -80000420: 00008067 ret - -80000424 <_read>: -80000424: fd010113 addi sp,sp,-48 -80000428: 02112623 sw ra,44(sp) -8000042c: 02812423 sw s0,40(sp) -80000430: 03010413 addi s0,sp,48 -80000434: fca42e23 sw a0,-36(s0) -80000438: fcb42c23 sw a1,-40(s0) -8000043c: fcc42a23 sw a2,-44(s0) -80000440: 710007b7 lui a5,0x71000 -80000444: fef42423 sw a5,-24(s0) -80000448: 720007b7 lui a5,0x72000 -8000044c: fef42623 sw a5,-20(s0) -80000450: 00400793 li a5,4 -80000454: fef42223 sw a5,-28(s0) -80000458: fe440713 addi a4,s0,-28 -8000045c: fe840793 addi a5,s0,-24 -80000460: 00400613 li a2,4 -80000464: 00070593 mv a1,a4 -80000468: 00078513 mv a0,a5 -8000046c: c71ff0ef jal ra,800000dc -80000470: fdc40713 addi a4,s0,-36 -80000474: fe840793 addi a5,s0,-24 -80000478: 00400613 li a2,4 -8000047c: 00070593 mv a1,a4 -80000480: 00078513 mv a0,a5 -80000484: c59ff0ef jal ra,800000dc -80000488: fd840713 addi a4,s0,-40 -8000048c: fe840793 addi a5,s0,-24 -80000490: 00400613 li a2,4 -80000494: 00070593 mv a1,a4 -80000498: 00078513 mv a0,a5 -8000049c: c41ff0ef jal ra,800000dc -800004a0: fd440713 addi a4,s0,-44 -800004a4: fe840793 addi a5,s0,-24 -800004a8: 00400613 li a2,4 -800004ac: 00070593 mv a1,a4 -800004b0: 00078513 mv a0,a5 -800004b4: c29ff0ef jal ra,800000dc -800004b8: 1bc1a783 lw a5,444(gp) # 80016d24 -800004bc: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -800004c0: fd442783 lw a5,-44(s0) -800004c4: 00078513 mv a0,a5 -800004c8: 02c12083 lw ra,44(sp) -800004cc: 02812403 lw s0,40(sp) -800004d0: 03010113 addi sp,sp,48 -800004d4: 00008067 ret - -800004d8 <_write>: -800004d8: fd010113 addi sp,sp,-48 -800004dc: 02112623 sw ra,44(sp) -800004e0: 02812423 sw s0,40(sp) -800004e4: 03010413 addi s0,sp,48 -800004e8: fca42e23 sw a0,-36(s0) -800004ec: fcb42c23 sw a1,-40(s0) -800004f0: fcc42a23 sw a2,-44(s0) -800004f4: 710007b7 lui a5,0x71000 -800004f8: fef42623 sw a5,-20(s0) -800004fc: 00500793 li a5,5 -80000500: fef42423 sw a5,-24(s0) -80000504: fe840713 addi a4,s0,-24 -80000508: fec40793 addi a5,s0,-20 -8000050c: 00400613 li a2,4 -80000510: 00070593 mv a1,a4 -80000514: 00078513 mv a0,a5 -80000518: bc5ff0ef jal ra,800000dc -8000051c: fdc40713 addi a4,s0,-36 -80000520: fec40793 addi a5,s0,-20 -80000524: 00400613 li a2,4 -80000528: 00070593 mv a1,a4 -8000052c: 00078513 mv a0,a5 -80000530: badff0ef jal ra,800000dc -80000534: fec40793 addi a5,s0,-20 -80000538: fd442603 lw a2,-44(s0) -8000053c: fd842583 lw a1,-40(s0) -80000540: 00078513 mv a0,a5 -80000544: b99ff0ef jal ra,800000dc -80000548: 1bc1a783 lw a5,444(gp) # 80016d24 -8000054c: 000780e7 jalr a5 # 71000000 <_start-0xf000000> -80000550: fd442783 lw a5,-44(s0) -80000554: 00078513 mv a0,a5 -80000558: 02c12083 lw ra,44(sp) -8000055c: 02812403 lw s0,40(sp) -80000560: 03010113 addi sp,sp,48 -80000564: 00008067 ret - -80000568 <_sbrk>: -80000568: fd010113 addi sp,sp,-48 -8000056c: 02812623 sw s0,44(sp) -80000570: 03010413 addi s0,sp,48 -80000574: fca42e23 sw a0,-36(s0) -80000578: fdc42783 lw a5,-36(s0) -8000057c: 0007d863 bgez a5,8000058c <_sbrk+0x24> -80000580: fdc42783 lw a5,-36(s0) -80000584: 40f007b3 neg a5,a5 -80000588: fcf42e23 sw a5,-36(s0) -8000058c: 1c01a783 lw a5,448(gp) # 80016d28 -80000590: fef42623 sw a5,-20(s0) -80000594: 1c01a703 lw a4,448(gp) # 80016d28 -80000598: fdc42783 lw a5,-36(s0) -8000059c: 00f70733 add a4,a4,a5 -800005a0: 1ce1a023 sw a4,448(gp) # 80016d28 -800005a4: fec42783 lw a5,-20(s0) -800005a8: 00078513 mv a0,a5 -800005ac: 02c12403 lw s0,44(sp) -800005b0: 03010113 addi sp,sp,48 -800005b4: 00008067 ret - -800005b8 <_exit>: -800005b8: fe010113 addi sp,sp,-32 -800005bc: 00112e23 sw ra,28(sp) -800005c0: 00812c23 sw s0,24(sp) -800005c4: 02010413 addi s0,sp,32 -800005c8: fea42623 sw a0,-20(s0) -800005cc: 00000513 li a0,0 -800005d0: 1c8000ef jal ra,80000798 -800005d4: 00000013 nop -800005d8: 01c12083 lw ra,28(sp) -800005dc: 01812403 lw s0,24(sp) -800005e0: 02010113 addi sp,sp,32 -800005e4: 00008067 ret - -800005e8 <_open>: -800005e8: fd010113 addi sp,sp,-48 -800005ec: 02112623 sw ra,44(sp) -800005f0: 02812423 sw s0,40(sp) -800005f4: 03010413 addi s0,sp,48 -800005f8: fca42e23 sw a0,-36(s0) -800005fc: fcb42c23 sw a1,-40(s0) -80000600: fcc42a23 sw a2,-44(s0) -80000604: 710007b7 lui a5,0x71000 -80000608: fef42623 sw a5,-20(s0) -8000060c: 720007b7 lui a5,0x72000 -80000610: fef42423 sw a5,-24(s0) -80000614: 00700793 li a5,7 -80000618: fef42223 sw a5,-28(s0) -8000061c: fe440713 addi a4,s0,-28 -80000620: fec40793 addi a5,s0,-20 -80000624: 00400613 li a2,4 -80000628: 00070593 mv a1,a4 -8000062c: 00078513 mv a0,a5 -80000630: aadff0ef jal ra,800000dc -80000634: fdc40713 addi a4,s0,-36 -80000638: fec40793 addi a5,s0,-20 -8000063c: 00400613 li a2,4 -80000640: 00070593 mv a1,a4 -80000644: 00078513 mv a0,a5 -80000648: a95ff0ef jal ra,800000dc -8000064c: fd840713 addi a4,s0,-40 -80000650: fec40793 addi a5,s0,-20 -80000654: 00400613 li a2,4 -80000658: 00070593 mv a1,a4 -8000065c: 00078513 mv a0,a5 -80000660: a7dff0ef jal ra,800000dc -80000664: fd440713 addi a4,s0,-44 -80000668: fec40793 addi a5,s0,-20 -8000066c: 00400613 li a2,4 -80000670: 00070593 mv a1,a4 -80000674: 00078513 mv a0,a5 -80000678: a65ff0ef jal ra,800000dc -8000067c: 1bc1a783 lw a5,444(gp) # 80016d24 -80000680: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -80000684: fe040713 addi a4,s0,-32 -80000688: fe840793 addi a5,s0,-24 -8000068c: 00070593 mv a1,a4 -80000690: 00078513 mv a0,a5 -80000694: b51ff0ef jal ra,800001e4 -80000698: fe042783 lw a5,-32(s0) -8000069c: 00078513 mv a0,a5 -800006a0: 02c12083 lw ra,44(sp) -800006a4: 02812403 lw s0,40(sp) -800006a8: 03010113 addi sp,sp,48 -800006ac: 00008067 ret - -800006b0 <_kill>: -800006b0: ff010113 addi sp,sp,-16 -800006b4: 00112623 sw ra,12(sp) -800006b8: 00812423 sw s0,8(sp) -800006bc: 01010413 addi s0,sp,16 -800006c0: 00000513 li a0,0 -800006c4: 0d4000ef jal ra,80000798 -800006c8: 00000013 nop -800006cc: 00c12083 lw ra,12(sp) -800006d0: 00812403 lw s0,8(sp) -800006d4: 01010113 addi sp,sp,16 -800006d8: 00008067 ret - -800006dc <_getpid>: -800006dc: ff010113 addi sp,sp,-16 -800006e0: 00112623 sw ra,12(sp) -800006e4: 00812423 sw s0,8(sp) -800006e8: 01010413 addi s0,sp,16 -800006ec: 0d4000ef jal ra,800007c0 -800006f0: 00050793 mv a5,a0 -800006f4: 00078513 mv a0,a5 -800006f8: 00c12083 lw ra,12(sp) -800006fc: 00812403 lw s0,8(sp) -80000700: 01010113 addi sp,sp,16 -80000704: 00008067 ret - -80000708 <_unlink>: -80000708: ff010113 addi sp,sp,-16 -8000070c: 00112623 sw ra,12(sp) -80000710: 00812423 sw s0,8(sp) -80000714: 01010413 addi s0,sp,16 -80000718: 800147b7 lui a5,0x80014 -8000071c: 58878513 addi a0,a5,1416 # 80014588 <__BSS_END__+0xffffd810> -80000720: 0f8000ef jal ra,80000818 -80000724: 00000013 nop -80000728: 00c12083 lw ra,12(sp) -8000072c: 00812403 lw s0,8(sp) -80000730: 01010113 addi sp,sp,16 -80000734: 00008067 ret - -80000738 <_gettimeofday>: -80000738: ff010113 addi sp,sp,-16 -8000073c: 00812623 sw s0,12(sp) -80000740: 01010413 addi s0,sp,16 -80000744: 1e01a783 lw a5,480(gp) # 80016d48 -80000748: 00178693 addi a3,a5,1 -8000074c: 1ed1a023 sw a3,480(gp) # 80016d48 -80000750: 00078513 mv a0,a5 -80000754: 00c12403 lw s0,12(sp) -80000758: 01010113 addi sp,sp,16 -8000075c: 00008067 ret - -80000760 <_link>: -80000760: ff010113 addi sp,sp,-16 -80000764: 00112623 sw ra,12(sp) -80000768: 00812423 sw s0,8(sp) -8000076c: 01010413 addi s0,sp,16 -80000770: 800147b7 lui a5,0x80014 -80000774: 5ac78513 addi a0,a5,1452 # 800145ac <__BSS_END__+0xffffd834> -80000778: 0a0000ef jal ra,80000818 -8000077c: 00000013 nop -80000780: 00c12083 lw ra,12(sp) -80000784: 00812403 lw s0,8(sp) -80000788: 01010113 addi sp,sp,16 -8000078c: 00008067 ret - -80000790 : -80000790: 00b5106b 0xb5106b -80000794: 00008067 ret - -80000798 : -80000798: 0005006b 0x5006b -8000079c: 00008067 ret - -800007a0 : -800007a0: 00b5406b 0xb5406b -800007a4: 00008067 ret - -800007a8 : -800007a8: 0005206b 0x5206b -800007ac: 00008067 ret - -800007b0 : -800007b0: 0000306b 0x306b -800007b4: 00008067 ret - -800007b8 : -800007b8: 02102573 csrr a0,0x21 -800007bc: 00008067 ret - -800007c0 : -800007c0: 02002573 csrr a0,0x20 -800007c4: 00008067 ret - -800007c8 : -800007c8: 02602573 csrr a0,0x26 -800007cc: 00008067 ret - -800007d0 : -800007d0: 02502573 csrr a0,0x25 -800007d4: 00008067 ret - -800007d8 : -800007d8: 00400513 li a0,4 -800007dc: 0005006b 0x5006b -800007e0: 021026f3 csrr a3,0x21 -800007e4: 00f69693 slli a3,a3,0xf -800007e8: 02002673 csrr a2,0x20 -800007ec: 00a61593 slli a1,a2,0xa -800007f0: 00261613 slli a2,a2,0x2 -800007f4: 6ffff137 lui sp,0x6ffff -800007f8: 40b10133 sub sp,sp,a1 -800007fc: 40d10133 sub sp,sp,a3 -80000800: 00c10133 add sp,sp,a2 -80000804: 021026f3 csrr a3,0x21 -80000808: 00068663 beqz a3,80000814 -8000080c: 00000513 li a0,0 -80000810: 0005006b 0x5006b - -80000814 : -80000814: 00008067 ret - -80000818 : -80000818: ff410113 addi sp,sp,-12 # 6fffeff4 <_start-0x1000100c> -8000081c: 00112023 sw ra,0(sp) -80000820: 00b12223 sw a1,4(sp) - -80000824 : -80000824: 00054583 lbu a1,0(a0) -80000828: 00058863 beqz a1,80000838 -8000082c: 01c000ef jal ra,80000848 -80000830: 00150513 addi a0,a0,1 -80000834: ff1ff06f j 80000824 - -80000838 : -80000838: 00012083 lw ra,0(sp) -8000083c: 00412583 lw a1,4(sp) -80000840: 00c10113 addi sp,sp,12 -80000844: 00008067 ret - -80000848 : -80000848: 000102b7 lui t0,0x10 -8000084c: 00b2a023 sw a1,0(t0) # 10000 <_start-0x7fff0000> -80000850: 00008067 ret - -80000854
: -80000854: fc010113 addi sp,sp,-64 -80000858: 02112e23 sw ra,60(sp) -8000085c: 02812c23 sw s0,56(sp) -80000860: 04010413 addi s0,sp,64 -80000864: 00100513 li a0,1 -80000868: f31ff0ef jal ra,80000798 -8000086c: 00500793 li a5,5 -80000870: fcf42823 sw a5,-48(s0) -80000874: 00a00793 li a5,10 -80000878: fcf42623 sw a5,-52(s0) -8000087c: fd042783 lw a5,-48(s0) -80000880: 00279793 slli a5,a5,0x2 -80000884: 00078513 mv a0,a5 -80000888: 460000ef jal ra,80000ce8 -8000088c: 00050793 mv a5,a0 -80000890: fcf42423 sw a5,-56(s0) -80000894: fd042783 lw a5,-48(s0) -80000898: 00279793 slli a5,a5,0x2 -8000089c: 00078513 mv a0,a5 -800008a0: 448000ef jal ra,80000ce8 -800008a4: 00050793 mv a5,a0 -800008a8: fcf42223 sw a5,-60(s0) -800008ac: fd042783 lw a5,-48(s0) -800008b0: 00279793 slli a5,a5,0x2 -800008b4: 00078513 mv a0,a5 -800008b8: 430000ef jal ra,80000ce8 -800008bc: 00050793 mv a5,a0 -800008c0: fcf42023 sw a5,-64(s0) -800008c4: fe042623 sw zero,-20(s0) -800008c8: 0580006f j 80000920 -800008cc: fec42783 lw a5,-20(s0) -800008d0: 00279793 slli a5,a5,0x2 -800008d4: fc842703 lw a4,-56(s0) -800008d8: 00f707b3 add a5,a4,a5 -800008dc: 00100713 li a4,1 -800008e0: 00e7a023 sw a4,0(a5) -800008e4: fec42783 lw a5,-20(s0) -800008e8: 00279793 slli a5,a5,0x2 -800008ec: fc442703 lw a4,-60(s0) -800008f0: 00f707b3 add a5,a4,a5 -800008f4: 00200713 li a4,2 -800008f8: 00e7a023 sw a4,0(a5) -800008fc: fec42783 lw a5,-20(s0) -80000900: 00279793 slli a5,a5,0x2 -80000904: fc042703 lw a4,-64(s0) -80000908: 00f707b3 add a5,a4,a5 -8000090c: 00500713 li a4,5 -80000910: 00e7a023 sw a4,0(a5) -80000914: fec42783 lw a5,-20(s0) -80000918: 00178793 addi a5,a5,1 -8000091c: fef42623 sw a5,-20(s0) -80000920: fec42703 lw a4,-20(s0) -80000924: fd042783 lw a5,-48(s0) -80000928: faf742e3 blt a4,a5,800008cc -8000092c: fe042423 sw zero,-24(s0) -80000930: 0580006f j 80000988 -80000934: fe842783 lw a5,-24(s0) -80000938: 00279793 slli a5,a5,0x2 -8000093c: fc842703 lw a4,-56(s0) -80000940: 00f707b3 add a5,a4,a5 -80000944: 00100713 li a4,1 -80000948: 00e7a023 sw a4,0(a5) -8000094c: fe842783 lw a5,-24(s0) -80000950: 00279793 slli a5,a5,0x2 -80000954: fc442703 lw a4,-60(s0) -80000958: 00f707b3 add a5,a4,a5 -8000095c: 00200713 li a4,2 -80000960: 00e7a023 sw a4,0(a5) -80000964: fe842783 lw a5,-24(s0) -80000968: 00279793 slli a5,a5,0x2 -8000096c: fc042703 lw a4,-64(s0) -80000970: 00f707b3 add a5,a4,a5 -80000974: 00200713 li a4,2 -80000978: 00e7a023 sw a4,0(a5) -8000097c: fe842783 lw a5,-24(s0) -80000980: 00178793 addi a5,a5,1 -80000984: fef42423 sw a5,-24(s0) -80000988: fe842703 lw a4,-24(s0) -8000098c: fd042783 lw a5,-48(s0) -80000990: faf742e3 blt a4,a5,80000934 -80000994: fd042583 lw a1,-48(s0) -80000998: 800147b7 lui a5,0x80014 -8000099c: 5d078513 addi a0,a5,1488 # 800145d0 <__BSS_END__+0xffffd858> -800009a0: 445000ef jal ra,800015e4 -800009a4: fe042223 sw zero,-28(s0) -800009a8: 0340006f j 800009dc -800009ac: fe442783 lw a5,-28(s0) -800009b0: 00279793 slli a5,a5,0x2 -800009b4: fc842703 lw a4,-56(s0) -800009b8: 00f707b3 add a5,a4,a5 -800009bc: 0007a783 lw a5,0(a5) -800009c0: 00078593 mv a1,a5 -800009c4: 800147b7 lui a5,0x80014 -800009c8: 5e078513 addi a0,a5,1504 # 800145e0 <__BSS_END__+0xffffd868> -800009cc: 419000ef jal ra,800015e4 -800009d0: fe442783 lw a5,-28(s0) -800009d4: 00178793 addi a5,a5,1 -800009d8: fef42223 sw a5,-28(s0) -800009dc: fe442703 lw a4,-28(s0) -800009e0: fd042783 lw a5,-48(s0) -800009e4: fcf744e3 blt a4,a5,800009ac -800009e8: fd042583 lw a1,-48(s0) -800009ec: 800147b7 lui a5,0x80014 -800009f0: 5e878513 addi a0,a5,1512 # 800145e8 <__BSS_END__+0xffffd870> -800009f4: 3f1000ef jal ra,800015e4 -800009f8: fe042023 sw zero,-32(s0) -800009fc: 0340006f j 80000a30 -80000a00: fe042783 lw a5,-32(s0) -80000a04: 00279793 slli a5,a5,0x2 -80000a08: fc442703 lw a4,-60(s0) -80000a0c: 00f707b3 add a5,a4,a5 -80000a10: 0007a783 lw a5,0(a5) -80000a14: 00078593 mv a1,a5 -80000a18: 800147b7 lui a5,0x80014 -80000a1c: 5e078513 addi a0,a5,1504 # 800145e0 <__BSS_END__+0xffffd868> -80000a20: 3c5000ef jal ra,800015e4 -80000a24: fe042783 lw a5,-32(s0) -80000a28: 00178793 addi a5,a5,1 -80000a2c: fef42023 sw a5,-32(s0) -80000a30: fe042703 lw a4,-32(s0) -80000a34: fd042783 lw a5,-48(s0) -80000a38: fcf744e3 blt a4,a5,80000a00 -80000a3c: fc442683 lw a3,-60(s0) -80000a40: fc842603 lw a2,-56(s0) -80000a44: fcc42583 lw a1,-52(s0) -80000a48: fd042503 lw a0,-48(s0) -80000a4c: e60ff0ef jal ra,800000ac -80000a50: fd042583 lw a1,-48(s0) -80000a54: 800147b7 lui a5,0x80014 -80000a58: 5d078513 addi a0,a5,1488 # 800145d0 <__BSS_END__+0xffffd858> -80000a5c: 389000ef jal ra,800015e4 -80000a60: fc042e23 sw zero,-36(s0) -80000a64: 0340006f j 80000a98 -80000a68: fdc42783 lw a5,-36(s0) -80000a6c: 00279793 slli a5,a5,0x2 -80000a70: fc842703 lw a4,-56(s0) -80000a74: 00f707b3 add a5,a4,a5 -80000a78: 0007a783 lw a5,0(a5) -80000a7c: 00078593 mv a1,a5 -80000a80: 800147b7 lui a5,0x80014 -80000a84: 5e078513 addi a0,a5,1504 # 800145e0 <__BSS_END__+0xffffd868> -80000a88: 35d000ef jal ra,800015e4 -80000a8c: fdc42783 lw a5,-36(s0) -80000a90: 00178793 addi a5,a5,1 -80000a94: fcf42e23 sw a5,-36(s0) -80000a98: fdc42703 lw a4,-36(s0) -80000a9c: fd042783 lw a5,-48(s0) -80000aa0: fcf744e3 blt a4,a5,80000a68 -80000aa4: fd042583 lw a1,-48(s0) -80000aa8: 800147b7 lui a5,0x80014 -80000aac: 5e878513 addi a0,a5,1512 # 800145e8 <__BSS_END__+0xffffd870> -80000ab0: 335000ef jal ra,800015e4 -80000ab4: fc042c23 sw zero,-40(s0) -80000ab8: 0340006f j 80000aec -80000abc: fd842783 lw a5,-40(s0) -80000ac0: 00279793 slli a5,a5,0x2 -80000ac4: fc442703 lw a4,-60(s0) -80000ac8: 00f707b3 add a5,a4,a5 -80000acc: 0007a783 lw a5,0(a5) -80000ad0: 00078593 mv a1,a5 -80000ad4: 800147b7 lui a5,0x80014 -80000ad8: 5e078513 addi a0,a5,1504 # 800145e0 <__BSS_END__+0xffffd868> -80000adc: 309000ef jal ra,800015e4 -80000ae0: fd842783 lw a5,-40(s0) -80000ae4: 00178793 addi a5,a5,1 -80000ae8: fcf42c23 sw a5,-40(s0) -80000aec: fd842703 lw a4,-40(s0) -80000af0: fd042783 lw a5,-48(s0) -80000af4: fcf744e3 blt a4,a5,80000abc -80000af8: fc042a23 sw zero,-44(s0) -80000afc: 0740006f j 80000b70 -80000b00: fd442783 lw a5,-44(s0) -80000b04: 00279793 slli a5,a5,0x2 -80000b08: fc442703 lw a4,-60(s0) -80000b0c: 00f707b3 add a5,a4,a5 -80000b10: 0007a703 lw a4,0(a5) -80000b14: fd442783 lw a5,-44(s0) -80000b18: 00279793 slli a5,a5,0x2 -80000b1c: fc842683 lw a3,-56(s0) -80000b20: 00f687b3 add a5,a3,a5 -80000b24: 0007a683 lw a3,0(a5) -80000b28: fcc42783 lw a5,-52(s0) -80000b2c: 02f686b3 mul a3,a3,a5 -80000b30: fd442783 lw a5,-44(s0) -80000b34: 00279793 slli a5,a5,0x2 -80000b38: fc042603 lw a2,-64(s0) -80000b3c: 00f607b3 add a5,a2,a5 -80000b40: 0007a783 lw a5,0(a5) -80000b44: 00f687b3 add a5,a3,a5 -80000b48: 00f70e63 beq a4,a5,80000b64 -80000b4c: fd442583 lw a1,-44(s0) -80000b50: 800147b7 lui a5,0x80014 -80000b54: 5f478513 addi a0,a5,1524 # 800145f4 <__BSS_END__+0xffffd87c> -80000b58: 28d000ef jal ra,800015e4 -80000b5c: 00100793 li a5,1 -80000b60: 0340006f j 80000b94 -80000b64: fd442783 lw a5,-44(s0) -80000b68: 00178793 addi a5,a5,1 -80000b6c: fcf42a23 sw a5,-44(s0) -80000b70: fd442703 lw a4,-44(s0) -80000b74: fd042783 lw a5,-48(s0) -80000b78: f8f744e3 blt a4,a5,80000b00 -80000b7c: 800147b7 lui a5,0x80014 -80000b80: 61878513 addi a0,a5,1560 # 80014618 <__BSS_END__+0xffffd8a0> -80000b84: 261000ef jal ra,800015e4 -80000b88: 00000513 li a0,0 -80000b8c: c0dff0ef jal ra,80000798 -80000b90: 00000793 li a5,0 -80000b94: 00078513 mv a0,a5 -80000b98: 03c12083 lw ra,60(sp) -80000b9c: 03812403 lw s0,56(sp) -80000ba0: 04010113 addi sp,sp,64 -80000ba4: 00008067 ret - -80000ba8 : -80000ba8: 00050593 mv a1,a0 -80000bac: 00000693 li a3,0 -80000bb0: 00000613 li a2,0 -80000bb4: 00000513 li a0,0 -80000bb8: 0690306f j 80004420 <__register_exitproc> - -80000bbc : -80000bbc: ff010113 addi sp,sp,-16 -80000bc0: 00000593 li a1,0 -80000bc4: 00812423 sw s0,8(sp) -80000bc8: 00112623 sw ra,12(sp) -80000bcc: 00050413 mv s0,a0 -80000bd0: 0e9030ef jal ra,800044b8 <__call_exitprocs> -80000bd4: 1b81a503 lw a0,440(gp) # 80016d20 <_global_impure_ptr> -80000bd8: 03c52783 lw a5,60(a0) -80000bdc: 00078463 beqz a5,80000be4 -80000be0: 000780e7 jalr a5 -80000be4: 00040513 mv a0,s0 -80000be8: 9d1ff0ef jal ra,800005b8 <_exit> - -80000bec <__libc_fini_array>: -80000bec: ff010113 addi sp,sp,-16 -80000bf0: 00812423 sw s0,8(sp) -80000bf4: 00912223 sw s1,4(sp) -80000bf8: 80016437 lui s0,0x80016 -80000bfc: 800164b7 lui s1,0x80016 -80000c00: 36448793 addi a5,s1,868 # 80016364 <__BSS_END__+0xfffff5ec> -80000c04: 36440413 addi s0,s0,868 # 80016364 <__BSS_END__+0xfffff5ec> -80000c08: 40f40433 sub s0,s0,a5 -80000c0c: 00112623 sw ra,12(sp) -80000c10: 40245413 srai s0,s0,0x2 -80000c14: 02040263 beqz s0,80000c38 <__libc_fini_array+0x4c> -80000c18: 00241493 slli s1,s0,0x2 -80000c1c: ffc48493 addi s1,s1,-4 -80000c20: 00f484b3 add s1,s1,a5 -80000c24: 0004a783 lw a5,0(s1) -80000c28: fff40413 addi s0,s0,-1 -80000c2c: ffc48493 addi s1,s1,-4 -80000c30: 000780e7 jalr a5 -80000c34: fe0418e3 bnez s0,80000c24 <__libc_fini_array+0x38> -80000c38: 00c12083 lw ra,12(sp) -80000c3c: 00812403 lw s0,8(sp) -80000c40: 00412483 lw s1,4(sp) -80000c44: 01010113 addi sp,sp,16 -80000c48: 00008067 ret - -80000c4c <__libc_init_array>: -80000c4c: ff010113 addi sp,sp,-16 -80000c50: 00812423 sw s0,8(sp) -80000c54: 01212023 sw s2,0(sp) -80000c58: 80016437 lui s0,0x80016 -80000c5c: 80016937 lui s2,0x80016 -80000c60: 36040793 addi a5,s0,864 # 80016360 <__BSS_END__+0xfffff5e8> -80000c64: 36090913 addi s2,s2,864 # 80016360 <__BSS_END__+0xfffff5e8> -80000c68: 40f90933 sub s2,s2,a5 -80000c6c: 00112623 sw ra,12(sp) -80000c70: 00912223 sw s1,4(sp) -80000c74: 40295913 srai s2,s2,0x2 -80000c78: 02090063 beqz s2,80000c98 <__libc_init_array+0x4c> -80000c7c: 36040413 addi s0,s0,864 -80000c80: 00000493 li s1,0 -80000c84: 00042783 lw a5,0(s0) -80000c88: 00148493 addi s1,s1,1 -80000c8c: 00440413 addi s0,s0,4 -80000c90: 000780e7 jalr a5 -80000c94: fe9918e3 bne s2,s1,80000c84 <__libc_init_array+0x38> -80000c98: 80016437 lui s0,0x80016 -80000c9c: 80016937 lui s2,0x80016 -80000ca0: 36040793 addi a5,s0,864 # 80016360 <__BSS_END__+0xfffff5e8> -80000ca4: 36490913 addi s2,s2,868 # 80016364 <__BSS_END__+0xfffff5ec> -80000ca8: 40f90933 sub s2,s2,a5 -80000cac: 40295913 srai s2,s2,0x2 -80000cb0: 02090063 beqz s2,80000cd0 <__libc_init_array+0x84> -80000cb4: 36040413 addi s0,s0,864 -80000cb8: 00000493 li s1,0 -80000cbc: 00042783 lw a5,0(s0) -80000cc0: 00148493 addi s1,s1,1 -80000cc4: 00440413 addi s0,s0,4 -80000cc8: 000780e7 jalr a5 -80000ccc: fe9918e3 bne s2,s1,80000cbc <__libc_init_array+0x70> -80000cd0: 00c12083 lw ra,12(sp) -80000cd4: 00812403 lw s0,8(sp) -80000cd8: 00412483 lw s1,4(sp) -80000cdc: 00012903 lw s2,0(sp) -80000ce0: 01010113 addi sp,sp,16 -80000ce4: 00008067 ret - -80000ce8 : -80000ce8: 00050593 mv a1,a0 -80000cec: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -80000cf0: 0100006f j 80000d00 <_malloc_r> - -80000cf4 : -80000cf4: 00050593 mv a1,a0 -80000cf8: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -80000cfc: 02c0406f j 80004d28 <_free_r> - -80000d00 <_malloc_r>: -80000d00: fd010113 addi sp,sp,-48 -80000d04: 02912223 sw s1,36(sp) -80000d08: 01312e23 sw s3,28(sp) -80000d0c: 02112623 sw ra,44(sp) -80000d10: 02812423 sw s0,40(sp) -80000d14: 03212023 sw s2,32(sp) -80000d18: 01412c23 sw s4,24(sp) -80000d1c: 01512a23 sw s5,20(sp) -80000d20: 01612823 sw s6,16(sp) -80000d24: 01712623 sw s7,12(sp) -80000d28: 01812423 sw s8,8(sp) -80000d2c: 01912223 sw s9,4(sp) -80000d30: 00b58493 addi s1,a1,11 -80000d34: 01600793 li a5,22 -80000d38: 00050993 mv s3,a0 -80000d3c: 0697e463 bltu a5,s1,80000da4 <_malloc_r+0xa4> -80000d40: 01000793 li a5,16 -80000d44: 20b7ec63 bltu a5,a1,80000f5c <_malloc_r+0x25c> -80000d48: 051000ef jal ra,80001598 <__malloc_lock> -80000d4c: 01000493 li s1,16 -80000d50: 01800793 li a5,24 -80000d54: 00200613 li a2,2 -80000d58: c2818913 addi s2,gp,-984 # 80016790 <__malloc_av_> -80000d5c: 00f907b3 add a5,s2,a5 -80000d60: 0047a403 lw s0,4(a5) -80000d64: ff878713 addi a4,a5,-8 -80000d68: 24e40263 beq s0,a4,80000fac <_malloc_r+0x2ac> -80000d6c: 00442783 lw a5,4(s0) -80000d70: 00c42683 lw a3,12(s0) -80000d74: 00842603 lw a2,8(s0) -80000d78: ffc7f793 andi a5,a5,-4 -80000d7c: 00f407b3 add a5,s0,a5 -80000d80: 0047a703 lw a4,4(a5) -80000d84: 00d62623 sw a3,12(a2) -80000d88: 00c6a423 sw a2,8(a3) -80000d8c: 00176713 ori a4,a4,1 -80000d90: 00098513 mv a0,s3 -80000d94: 00e7a223 sw a4,4(a5) -80000d98: 005000ef jal ra,8000159c <__malloc_unlock> -80000d9c: 00840513 addi a0,s0,8 -80000da0: 1c80006f j 80000f68 <_malloc_r+0x268> -80000da4: ff84f493 andi s1,s1,-8 -80000da8: 1a04ca63 bltz s1,80000f5c <_malloc_r+0x25c> -80000dac: 1ab4e863 bltu s1,a1,80000f5c <_malloc_r+0x25c> -80000db0: 7e8000ef jal ra,80001598 <__malloc_lock> -80000db4: 1f700793 li a5,503 -80000db8: 4697f863 bgeu a5,s1,80001228 <_malloc_r+0x528> -80000dbc: 0094d793 srli a5,s1,0x9 -80000dc0: 1c078e63 beqz a5,80000f9c <_malloc_r+0x29c> -80000dc4: 00400713 li a4,4 -80000dc8: 3ef76c63 bltu a4,a5,800011c0 <_malloc_r+0x4c0> -80000dcc: 0064d793 srli a5,s1,0x6 -80000dd0: 03978613 addi a2,a5,57 -80000dd4: 03878513 addi a0,a5,56 -80000dd8: 00361693 slli a3,a2,0x3 -80000ddc: c2818913 addi s2,gp,-984 # 80016790 <__malloc_av_> -80000de0: 00d906b3 add a3,s2,a3 -80000de4: 0046a403 lw s0,4(a3) -80000de8: ff868693 addi a3,a3,-8 -80000dec: 02868c63 beq a3,s0,80000e24 <_malloc_r+0x124> -80000df0: 00442783 lw a5,4(s0) -80000df4: 00f00593 li a1,15 -80000df8: ffc7f793 andi a5,a5,-4 -80000dfc: 40978733 sub a4,a5,s1 -80000e00: 02e5c063 blt a1,a4,80000e20 <_malloc_r+0x120> -80000e04: 34075863 bgez a4,80001154 <_malloc_r+0x454> -80000e08: 00c42403 lw s0,12(s0) -80000e0c: 00868c63 beq a3,s0,80000e24 <_malloc_r+0x124> -80000e10: 00442783 lw a5,4(s0) -80000e14: ffc7f793 andi a5,a5,-4 -80000e18: 40978733 sub a4,a5,s1 -80000e1c: fee5d4e3 bge a1,a4,80000e04 <_malloc_r+0x104> -80000e20: 00050613 mv a2,a0 -80000e24: 01092403 lw s0,16(s2) -80000e28: 00890813 addi a6,s2,8 -80000e2c: 19040c63 beq s0,a6,80000fc4 <_malloc_r+0x2c4> -80000e30: 00442583 lw a1,4(s0) -80000e34: 00f00713 li a4,15 -80000e38: ffc5f593 andi a1,a1,-4 -80000e3c: 409587b3 sub a5,a1,s1 -80000e40: 40f74a63 blt a4,a5,80001254 <_malloc_r+0x554> -80000e44: 01092a23 sw a6,20(s2) -80000e48: 01092823 sw a6,16(s2) -80000e4c: 3e07d463 bgez a5,80001234 <_malloc_r+0x534> -80000e50: 1ff00793 li a5,511 -80000e54: 30b7e663 bltu a5,a1,80001160 <_malloc_r+0x460> -80000e58: 0035d593 srli a1,a1,0x3 -80000e5c: 00158793 addi a5,a1,1 -80000e60: 00379793 slli a5,a5,0x3 -80000e64: 00492503 lw a0,4(s2) -80000e68: 00f907b3 add a5,s2,a5 -80000e6c: 0007a683 lw a3,0(a5) -80000e70: 4025d593 srai a1,a1,0x2 -80000e74: 00100713 li a4,1 -80000e78: 00b71733 sll a4,a4,a1 -80000e7c: 00a76733 or a4,a4,a0 -80000e80: ff878593 addi a1,a5,-8 -80000e84: 00b42623 sw a1,12(s0) -80000e88: 00d42423 sw a3,8(s0) -80000e8c: 00e92223 sw a4,4(s2) -80000e90: 0087a023 sw s0,0(a5) -80000e94: 0086a623 sw s0,12(a3) -80000e98: 40265793 srai a5,a2,0x2 -80000e9c: 00100693 li a3,1 -80000ea0: 00f696b3 sll a3,a3,a5 -80000ea4: 12d76a63 bltu a4,a3,80000fd8 <_malloc_r+0x2d8> -80000ea8: 00e6f7b3 and a5,a3,a4 -80000eac: 02079463 bnez a5,80000ed4 <_malloc_r+0x1d4> -80000eb0: 00169693 slli a3,a3,0x1 -80000eb4: ffc67613 andi a2,a2,-4 -80000eb8: 00e6f7b3 and a5,a3,a4 -80000ebc: 00460613 addi a2,a2,4 -80000ec0: 00079a63 bnez a5,80000ed4 <_malloc_r+0x1d4> -80000ec4: 00169693 slli a3,a3,0x1 -80000ec8: 00e6f7b3 and a5,a3,a4 -80000ecc: 00460613 addi a2,a2,4 -80000ed0: fe078ae3 beqz a5,80000ec4 <_malloc_r+0x1c4> -80000ed4: 00f00513 li a0,15 -80000ed8: 00361893 slli a7,a2,0x3 -80000edc: 011908b3 add a7,s2,a7 -80000ee0: 00088593 mv a1,a7 -80000ee4: 00060313 mv t1,a2 -80000ee8: 00c5a403 lw s0,12(a1) -80000eec: 00859a63 bne a1,s0,80000f00 <_malloc_r+0x200> -80000ef0: 2f40006f j 800011e4 <_malloc_r+0x4e4> -80000ef4: 30075263 bgez a4,800011f8 <_malloc_r+0x4f8> -80000ef8: 00c42403 lw s0,12(s0) -80000efc: 2e858463 beq a1,s0,800011e4 <_malloc_r+0x4e4> -80000f00: 00442783 lw a5,4(s0) -80000f04: ffc7f793 andi a5,a5,-4 -80000f08: 40978733 sub a4,a5,s1 -80000f0c: fee554e3 bge a0,a4,80000ef4 <_malloc_r+0x1f4> -80000f10: 00c42683 lw a3,12(s0) -80000f14: 00842603 lw a2,8(s0) -80000f18: 0014e593 ori a1,s1,1 -80000f1c: 00b42223 sw a1,4(s0) -80000f20: 00d62623 sw a3,12(a2) -80000f24: 00c6a423 sw a2,8(a3) -80000f28: 009404b3 add s1,s0,s1 -80000f2c: 00992a23 sw s1,20(s2) -80000f30: 00992823 sw s1,16(s2) -80000f34: 00176693 ori a3,a4,1 -80000f38: 0104a623 sw a6,12(s1) -80000f3c: 0104a423 sw a6,8(s1) -80000f40: 00d4a223 sw a3,4(s1) -80000f44: 00f407b3 add a5,s0,a5 -80000f48: 00098513 mv a0,s3 -80000f4c: 00e7a023 sw a4,0(a5) -80000f50: 64c000ef jal ra,8000159c <__malloc_unlock> -80000f54: 00840513 addi a0,s0,8 -80000f58: 0100006f j 80000f68 <_malloc_r+0x268> -80000f5c: 00c00793 li a5,12 -80000f60: 00f9a023 sw a5,0(s3) -80000f64: 00000513 li a0,0 -80000f68: 02c12083 lw ra,44(sp) -80000f6c: 02812403 lw s0,40(sp) -80000f70: 02412483 lw s1,36(sp) -80000f74: 02012903 lw s2,32(sp) -80000f78: 01c12983 lw s3,28(sp) -80000f7c: 01812a03 lw s4,24(sp) -80000f80: 01412a83 lw s5,20(sp) -80000f84: 01012b03 lw s6,16(sp) -80000f88: 00c12b83 lw s7,12(sp) -80000f8c: 00812c03 lw s8,8(sp) -80000f90: 00412c83 lw s9,4(sp) -80000f94: 03010113 addi sp,sp,48 -80000f98: 00008067 ret -80000f9c: 20000693 li a3,512 -80000fa0: 04000613 li a2,64 -80000fa4: 03f00513 li a0,63 -80000fa8: e35ff06f j 80000ddc <_malloc_r+0xdc> -80000fac: 00c7a403 lw s0,12(a5) -80000fb0: 00260613 addi a2,a2,2 -80000fb4: da879ce3 bne a5,s0,80000d6c <_malloc_r+0x6c> -80000fb8: 01092403 lw s0,16(s2) -80000fbc: 00890813 addi a6,s2,8 -80000fc0: e70418e3 bne s0,a6,80000e30 <_malloc_r+0x130> -80000fc4: 00492703 lw a4,4(s2) -80000fc8: 40265793 srai a5,a2,0x2 -80000fcc: 00100693 li a3,1 -80000fd0: 00f696b3 sll a3,a3,a5 -80000fd4: ecd77ae3 bgeu a4,a3,80000ea8 <_malloc_r+0x1a8> -80000fd8: 00892403 lw s0,8(s2) -80000fdc: 00442a83 lw s5,4(s0) -80000fe0: ffcafc13 andi s8,s5,-4 -80000fe4: 009c6863 bltu s8,s1,80000ff4 <_malloc_r+0x2f4> -80000fe8: 409c07b3 sub a5,s8,s1 -80000fec: 00f00713 li a4,15 -80000ff0: 12f74e63 blt a4,a5,8000112c <_malloc_r+0x42c> -80000ff4: 1dc1aa83 lw s5,476(gp) # 80016d44 <__malloc_top_pad> -80000ff8: 1cc1a703 lw a4,460(gp) # 80016d34 <__malloc_sbrk_base> -80000ffc: fff00793 li a5,-1 -80001000: 01840a33 add s4,s0,s8 -80001004: 01548ab3 add s5,s1,s5 -80001008: 32f70863 beq a4,a5,80001338 <_malloc_r+0x638> -8000100c: 000017b7 lui a5,0x1 -80001010: 00f78793 addi a5,a5,15 # 100f <_start-0x7fffeff1> -80001014: 00fa8ab3 add s5,s5,a5 -80001018: fffff7b7 lui a5,0xfffff -8000101c: 00fafab3 and s5,s5,a5 -80001020: 000a8593 mv a1,s5 -80001024: 00098513 mv a0,s3 -80001028: 60c000ef jal ra,80001634 <_sbrk_r> -8000102c: fff00793 li a5,-1 -80001030: 00050b13 mv s6,a0 -80001034: 26f50a63 beq a0,a5,800012a8 <_malloc_r+0x5a8> -80001038: 27456663 bltu a0,s4,800012a4 <_malloc_r+0x5a4> -8000103c: 1e418b93 addi s7,gp,484 # 80016d4c <__malloc_current_mallinfo> -80001040: 000ba783 lw a5,0(s7) -80001044: 00fa87b3 add a5,s5,a5 -80001048: 00fba023 sw a5,0(s7) -8000104c: 00078713 mv a4,a5 -80001050: 38aa0663 beq s4,a0,800013dc <_malloc_r+0x6dc> -80001054: 1cc1a683 lw a3,460(gp) # 80016d34 <__malloc_sbrk_base> -80001058: fff00793 li a5,-1 -8000105c: 38f68e63 beq a3,a5,800013f8 <_malloc_r+0x6f8> -80001060: 414b0a33 sub s4,s6,s4 -80001064: 00ea0733 add a4,s4,a4 -80001068: 00eba023 sw a4,0(s7) -8000106c: 007b7c93 andi s9,s6,7 -80001070: 2e0c8663 beqz s9,8000135c <_malloc_r+0x65c> -80001074: 419b0b33 sub s6,s6,s9 -80001078: 000017b7 lui a5,0x1 -8000107c: 008b0b13 addi s6,s6,8 -80001080: fff78a13 addi s4,a5,-1 # fff <_start-0x7ffff001> -80001084: 015b0ab3 add s5,s6,s5 -80001088: 00878793 addi a5,a5,8 -8000108c: 014af733 and a4,s5,s4 -80001090: 419787b3 sub a5,a5,s9 -80001094: 40e787b3 sub a5,a5,a4 -80001098: 0147fa33 and s4,a5,s4 -8000109c: 000a0593 mv a1,s4 -800010a0: 00098513 mv a0,s3 -800010a4: 590000ef jal ra,80001634 <_sbrk_r> -800010a8: fff00793 li a5,-1 -800010ac: 3af50063 beq a0,a5,8000144c <_malloc_r+0x74c> -800010b0: 41650533 sub a0,a0,s6 -800010b4: 01450ab3 add s5,a0,s4 -800010b8: 000ba783 lw a5,0(s7) -800010bc: 01692423 sw s6,8(s2) -800010c0: 001aea93 ori s5,s5,1 -800010c4: 00fa07b3 add a5,s4,a5 -800010c8: 00fba023 sw a5,0(s7) -800010cc: 015b2223 sw s5,4(s6) -800010d0: 33240863 beq s0,s2,80001400 <_malloc_r+0x700> -800010d4: 00f00613 li a2,15 -800010d8: 33867863 bgeu a2,s8,80001408 <_malloc_r+0x708> -800010dc: 00442683 lw a3,4(s0) -800010e0: ff4c0713 addi a4,s8,-12 -800010e4: ff877713 andi a4,a4,-8 -800010e8: 0016f693 andi a3,a3,1 -800010ec: 00e6e6b3 or a3,a3,a4 -800010f0: 00d42223 sw a3,4(s0) -800010f4: 00500593 li a1,5 -800010f8: 00e406b3 add a3,s0,a4 -800010fc: 00b6a223 sw a1,4(a3) -80001100: 00b6a423 sw a1,8(a3) -80001104: 34e66e63 bltu a2,a4,80001460 <_malloc_r+0x760> -80001108: 004b2a83 lw s5,4(s6) -8000110c: 000b0413 mv s0,s6 -80001110: 1d81a683 lw a3,472(gp) # 80016d40 <__malloc_max_sbrked_mem> -80001114: 00f6f463 bgeu a3,a5,8000111c <_malloc_r+0x41c> -80001118: 1cf1ac23 sw a5,472(gp) # 80016d40 <__malloc_max_sbrked_mem> -8000111c: 1d41a683 lw a3,468(gp) # 80016d3c <_edata> -80001120: 18f6f863 bgeu a3,a5,800012b0 <_malloc_r+0x5b0> -80001124: 1cf1aa23 sw a5,468(gp) # 80016d3c <_edata> -80001128: 1880006f j 800012b0 <_malloc_r+0x5b0> -8000112c: 0014e713 ori a4,s1,1 -80001130: 00e42223 sw a4,4(s0) -80001134: 009404b3 add s1,s0,s1 -80001138: 00992423 sw s1,8(s2) -8000113c: 0017e793 ori a5,a5,1 -80001140: 00098513 mv a0,s3 -80001144: 00f4a223 sw a5,4(s1) -80001148: 454000ef jal ra,8000159c <__malloc_unlock> -8000114c: 00840513 addi a0,s0,8 -80001150: e19ff06f j 80000f68 <_malloc_r+0x268> -80001154: 00c42683 lw a3,12(s0) -80001158: 00842603 lw a2,8(s0) -8000115c: c21ff06f j 80000d7c <_malloc_r+0x7c> -80001160: 0095d793 srli a5,a1,0x9 -80001164: 00400713 li a4,4 -80001168: 12f77463 bgeu a4,a5,80001290 <_malloc_r+0x590> -8000116c: 01400713 li a4,20 -80001170: 22f76063 bltu a4,a5,80001390 <_malloc_r+0x690> -80001174: 05c78693 addi a3,a5,92 -80001178: 05b78713 addi a4,a5,91 -8000117c: 00369693 slli a3,a3,0x3 -80001180: 00d906b3 add a3,s2,a3 -80001184: 0006a783 lw a5,0(a3) -80001188: ff868693 addi a3,a3,-8 -8000118c: 1af68a63 beq a3,a5,80001340 <_malloc_r+0x640> -80001190: 0047a703 lw a4,4(a5) -80001194: ffc77713 andi a4,a4,-4 -80001198: 00e5f663 bgeu a1,a4,800011a4 <_malloc_r+0x4a4> -8000119c: 0087a783 lw a5,8(a5) -800011a0: fef698e3 bne a3,a5,80001190 <_malloc_r+0x490> -800011a4: 00c7a683 lw a3,12(a5) -800011a8: 00492703 lw a4,4(s2) -800011ac: 00d42623 sw a3,12(s0) -800011b0: 00f42423 sw a5,8(s0) -800011b4: 0086a423 sw s0,8(a3) -800011b8: 0087a623 sw s0,12(a5) -800011bc: cddff06f j 80000e98 <_malloc_r+0x198> -800011c0: 01400713 li a4,20 -800011c4: 10f77863 bgeu a4,a5,800012d4 <_malloc_r+0x5d4> -800011c8: 05400713 li a4,84 -800011cc: 1ef76063 bltu a4,a5,800013ac <_malloc_r+0x6ac> -800011d0: 00c4d793 srli a5,s1,0xc -800011d4: 06f78613 addi a2,a5,111 -800011d8: 06e78513 addi a0,a5,110 -800011dc: 00361693 slli a3,a2,0x3 -800011e0: bfdff06f j 80000ddc <_malloc_r+0xdc> -800011e4: 00130313 addi t1,t1,1 -800011e8: 00337793 andi a5,t1,3 -800011ec: 00858593 addi a1,a1,8 -800011f0: ce079ce3 bnez a5,80000ee8 <_malloc_r+0x1e8> -800011f4: 0fc0006f j 800012f0 <_malloc_r+0x5f0> -800011f8: 00f407b3 add a5,s0,a5 -800011fc: 0047a703 lw a4,4(a5) -80001200: 00c42683 lw a3,12(s0) -80001204: 00842603 lw a2,8(s0) -80001208: 00176713 ori a4,a4,1 -8000120c: 00e7a223 sw a4,4(a5) -80001210: 00d62623 sw a3,12(a2) -80001214: 00098513 mv a0,s3 -80001218: 00c6a423 sw a2,8(a3) -8000121c: 380000ef jal ra,8000159c <__malloc_unlock> -80001220: 00840513 addi a0,s0,8 -80001224: d45ff06f j 80000f68 <_malloc_r+0x268> -80001228: 0034d613 srli a2,s1,0x3 -8000122c: 00848793 addi a5,s1,8 -80001230: b29ff06f j 80000d58 <_malloc_r+0x58> -80001234: 00b405b3 add a1,s0,a1 -80001238: 0045a783 lw a5,4(a1) -8000123c: 00098513 mv a0,s3 -80001240: 0017e793 ori a5,a5,1 -80001244: 00f5a223 sw a5,4(a1) -80001248: 354000ef jal ra,8000159c <__malloc_unlock> -8000124c: 00840513 addi a0,s0,8 -80001250: d19ff06f j 80000f68 <_malloc_r+0x268> -80001254: 0014e713 ori a4,s1,1 -80001258: 00e42223 sw a4,4(s0) -8000125c: 009404b3 add s1,s0,s1 -80001260: 00992a23 sw s1,20(s2) -80001264: 00992823 sw s1,16(s2) -80001268: 0017e713 ori a4,a5,1 -8000126c: 0104a623 sw a6,12(s1) -80001270: 0104a423 sw a6,8(s1) -80001274: 00e4a223 sw a4,4(s1) -80001278: 00b405b3 add a1,s0,a1 -8000127c: 00098513 mv a0,s3 -80001280: 00f5a023 sw a5,0(a1) -80001284: 318000ef jal ra,8000159c <__malloc_unlock> -80001288: 00840513 addi a0,s0,8 -8000128c: cddff06f j 80000f68 <_malloc_r+0x268> -80001290: 0065d793 srli a5,a1,0x6 -80001294: 03978693 addi a3,a5,57 -80001298: 03878713 addi a4,a5,56 -8000129c: 00369693 slli a3,a3,0x3 -800012a0: ee1ff06f j 80001180 <_malloc_r+0x480> -800012a4: 13240263 beq s0,s2,800013c8 <_malloc_r+0x6c8> -800012a8: 00892403 lw s0,8(s2) -800012ac: 00442a83 lw s5,4(s0) -800012b0: ffcafa93 andi s5,s5,-4 -800012b4: 409a87b3 sub a5,s5,s1 -800012b8: 009ae663 bltu s5,s1,800012c4 <_malloc_r+0x5c4> -800012bc: 00f00713 li a4,15 -800012c0: e6f746e3 blt a4,a5,8000112c <_malloc_r+0x42c> -800012c4: 00098513 mv a0,s3 -800012c8: 2d4000ef jal ra,8000159c <__malloc_unlock> -800012cc: 00000513 li a0,0 -800012d0: c99ff06f j 80000f68 <_malloc_r+0x268> -800012d4: 05c78613 addi a2,a5,92 -800012d8: 05b78513 addi a0,a5,91 -800012dc: 00361693 slli a3,a2,0x3 -800012e0: afdff06f j 80000ddc <_malloc_r+0xdc> -800012e4: 0088a783 lw a5,8(a7) -800012e8: fff60613 addi a2,a2,-1 -800012ec: 1d179463 bne a5,a7,800014b4 <_malloc_r+0x7b4> -800012f0: 00367793 andi a5,a2,3 -800012f4: ff888893 addi a7,a7,-8 -800012f8: fe0796e3 bnez a5,800012e4 <_malloc_r+0x5e4> -800012fc: 00492703 lw a4,4(s2) -80001300: fff6c793 not a5,a3 -80001304: 00e7f7b3 and a5,a5,a4 -80001308: 00f92223 sw a5,4(s2) -8000130c: 00169693 slli a3,a3,0x1 -80001310: ccd7e4e3 bltu a5,a3,80000fd8 <_malloc_r+0x2d8> -80001314: cc0682e3 beqz a3,80000fd8 <_malloc_r+0x2d8> -80001318: 00f6f733 and a4,a3,a5 -8000131c: 00071a63 bnez a4,80001330 <_malloc_r+0x630> -80001320: 00169693 slli a3,a3,0x1 -80001324: 00f6f733 and a4,a3,a5 -80001328: 00430313 addi t1,t1,4 -8000132c: fe070ae3 beqz a4,80001320 <_malloc_r+0x620> -80001330: 00030613 mv a2,t1 -80001334: ba5ff06f j 80000ed8 <_malloc_r+0x1d8> -80001338: 010a8a93 addi s5,s5,16 -8000133c: ce5ff06f j 80001020 <_malloc_r+0x320> -80001340: 00492503 lw a0,4(s2) -80001344: 40275593 srai a1,a4,0x2 -80001348: 00100713 li a4,1 -8000134c: 00b71733 sll a4,a4,a1 -80001350: 00a76733 or a4,a4,a0 -80001354: 00e92223 sw a4,4(s2) -80001358: e55ff06f j 800011ac <_malloc_r+0x4ac> -8000135c: 000017b7 lui a5,0x1 -80001360: fff78713 addi a4,a5,-1 # fff <_start-0x7ffff001> -80001364: 015b0a33 add s4,s6,s5 -80001368: 00ea7a33 and s4,s4,a4 -8000136c: 414787b3 sub a5,a5,s4 -80001370: 00e7fa33 and s4,a5,a4 -80001374: 000a0593 mv a1,s4 -80001378: 00098513 mv a0,s3 -8000137c: 2b8000ef jal ra,80001634 <_sbrk_r> -80001380: fff00793 li a5,-1 -80001384: d2f516e3 bne a0,a5,800010b0 <_malloc_r+0x3b0> -80001388: 00000a13 li s4,0 -8000138c: d2dff06f j 800010b8 <_malloc_r+0x3b8> -80001390: 05400713 li a4,84 -80001394: 08f76063 bltu a4,a5,80001414 <_malloc_r+0x714> -80001398: 00c5d793 srli a5,a1,0xc -8000139c: 06f78693 addi a3,a5,111 -800013a0: 06e78713 addi a4,a5,110 -800013a4: 00369693 slli a3,a3,0x3 -800013a8: dd9ff06f j 80001180 <_malloc_r+0x480> -800013ac: 15400713 li a4,340 -800013b0: 08f76063 bltu a4,a5,80001430 <_malloc_r+0x730> -800013b4: 00f4d793 srli a5,s1,0xf -800013b8: 07878613 addi a2,a5,120 -800013bc: 07778513 addi a0,a5,119 -800013c0: 00361693 slli a3,a2,0x3 -800013c4: a19ff06f j 80000ddc <_malloc_r+0xdc> -800013c8: 1e418b93 addi s7,gp,484 # 80016d4c <__malloc_current_mallinfo> -800013cc: 000ba703 lw a4,0(s7) -800013d0: 00ea8733 add a4,s5,a4 -800013d4: 00eba023 sw a4,0(s7) -800013d8: c7dff06f j 80001054 <_malloc_r+0x354> -800013dc: 014a1693 slli a3,s4,0x14 -800013e0: c6069ae3 bnez a3,80001054 <_malloc_r+0x354> -800013e4: 00892403 lw s0,8(s2) -800013e8: 015c0ab3 add s5,s8,s5 -800013ec: 001aea93 ori s5,s5,1 -800013f0: 01542223 sw s5,4(s0) -800013f4: d1dff06f j 80001110 <_malloc_r+0x410> -800013f8: 1d61a623 sw s6,460(gp) # 80016d34 <__malloc_sbrk_base> -800013fc: c71ff06f j 8000106c <_malloc_r+0x36c> -80001400: 000b0413 mv s0,s6 -80001404: d0dff06f j 80001110 <_malloc_r+0x410> -80001408: 00100793 li a5,1 -8000140c: 00fb2223 sw a5,4(s6) -80001410: eb5ff06f j 800012c4 <_malloc_r+0x5c4> -80001414: 15400713 li a4,340 -80001418: 06f76263 bltu a4,a5,8000147c <_malloc_r+0x77c> -8000141c: 00f5d793 srli a5,a1,0xf -80001420: 07878693 addi a3,a5,120 -80001424: 07778713 addi a4,a5,119 -80001428: 00369693 slli a3,a3,0x3 -8000142c: d55ff06f j 80001180 <_malloc_r+0x480> -80001430: 55400713 li a4,1364 -80001434: 06f76263 bltu a4,a5,80001498 <_malloc_r+0x798> -80001438: 0124d793 srli a5,s1,0x12 -8000143c: 07d78613 addi a2,a5,125 -80001440: 07c78513 addi a0,a5,124 -80001444: 00361693 slli a3,a2,0x3 -80001448: 995ff06f j 80000ddc <_malloc_r+0xdc> -8000144c: ff8c8c93 addi s9,s9,-8 -80001450: 019a8ab3 add s5,s5,s9 -80001454: 416a8ab3 sub s5,s5,s6 -80001458: 00000a13 li s4,0 -8000145c: c5dff06f j 800010b8 <_malloc_r+0x3b8> -80001460: 00840593 addi a1,s0,8 -80001464: 00098513 mv a0,s3 -80001468: 0c1030ef jal ra,80004d28 <_free_r> -8000146c: 00892403 lw s0,8(s2) -80001470: 000ba783 lw a5,0(s7) -80001474: 00442a83 lw s5,4(s0) -80001478: c99ff06f j 80001110 <_malloc_r+0x410> -8000147c: 55400713 li a4,1364 -80001480: 02f76463 bltu a4,a5,800014a8 <_malloc_r+0x7a8> -80001484: 0125d793 srli a5,a1,0x12 -80001488: 07d78693 addi a3,a5,125 -8000148c: 07c78713 addi a4,a5,124 -80001490: 00369693 slli a3,a3,0x3 -80001494: cedff06f j 80001180 <_malloc_r+0x480> -80001498: 3f800693 li a3,1016 -8000149c: 07f00613 li a2,127 -800014a0: 07e00513 li a0,126 -800014a4: 939ff06f j 80000ddc <_malloc_r+0xdc> -800014a8: 3f800693 li a3,1016 -800014ac: 07e00713 li a4,126 -800014b0: cd1ff06f j 80001180 <_malloc_r+0x480> -800014b4: 00492783 lw a5,4(s2) -800014b8: e55ff06f j 8000130c <_malloc_r+0x60c> - -800014bc : -800014bc: 00f00313 li t1,15 -800014c0: 00050713 mv a4,a0 -800014c4: 02c37e63 bgeu t1,a2,80001500 -800014c8: 00f77793 andi a5,a4,15 -800014cc: 0a079063 bnez a5,8000156c -800014d0: 08059263 bnez a1,80001554 -800014d4: ff067693 andi a3,a2,-16 -800014d8: 00f67613 andi a2,a2,15 -800014dc: 00e686b3 add a3,a3,a4 -800014e0: 00b72023 sw a1,0(a4) # 2000 <_start-0x7fffe000> -800014e4: 00b72223 sw a1,4(a4) -800014e8: 00b72423 sw a1,8(a4) -800014ec: 00b72623 sw a1,12(a4) -800014f0: 01070713 addi a4,a4,16 -800014f4: fed766e3 bltu a4,a3,800014e0 -800014f8: 00061463 bnez a2,80001500 -800014fc: 00008067 ret -80001500: 40c306b3 sub a3,t1,a2 -80001504: 00269693 slli a3,a3,0x2 -80001508: 00000297 auipc t0,0x0 -8000150c: 005686b3 add a3,a3,t0 -80001510: 00c68067 jr 12(a3) -80001514: 00b70723 sb a1,14(a4) -80001518: 00b706a3 sb a1,13(a4) -8000151c: 00b70623 sb a1,12(a4) -80001520: 00b705a3 sb a1,11(a4) -80001524: 00b70523 sb a1,10(a4) -80001528: 00b704a3 sb a1,9(a4) -8000152c: 00b70423 sb a1,8(a4) -80001530: 00b703a3 sb a1,7(a4) -80001534: 00b70323 sb a1,6(a4) -80001538: 00b702a3 sb a1,5(a4) -8000153c: 00b70223 sb a1,4(a4) -80001540: 00b701a3 sb a1,3(a4) -80001544: 00b70123 sb a1,2(a4) -80001548: 00b700a3 sb a1,1(a4) -8000154c: 00b70023 sb a1,0(a4) -80001550: 00008067 ret -80001554: 0ff5f593 andi a1,a1,255 -80001558: 00859693 slli a3,a1,0x8 -8000155c: 00d5e5b3 or a1,a1,a3 -80001560: 01059693 slli a3,a1,0x10 -80001564: 00d5e5b3 or a1,a1,a3 -80001568: f6dff06f j 800014d4 -8000156c: 00279693 slli a3,a5,0x2 -80001570: 00000297 auipc t0,0x0 -80001574: 005686b3 add a3,a3,t0 -80001578: 00008293 mv t0,ra -8000157c: fa0680e7 jalr -96(a3) -80001580: 00028093 mv ra,t0 -80001584: ff078793 addi a5,a5,-16 -80001588: 40f70733 sub a4,a4,a5 -8000158c: 00f60633 add a2,a2,a5 -80001590: f6c378e3 bgeu t1,a2,80001500 -80001594: f3dff06f j 800014d0 - -80001598 <__malloc_lock>: -80001598: 00008067 ret - -8000159c <__malloc_unlock>: -8000159c: 00008067 ret - -800015a0 <_printf_r>: -800015a0: fc010113 addi sp,sp,-64 -800015a4: 02c12423 sw a2,40(sp) -800015a8: 02d12623 sw a3,44(sp) -800015ac: 02f12a23 sw a5,52(sp) -800015b0: 02e12823 sw a4,48(sp) -800015b4: 03012c23 sw a6,56(sp) -800015b8: 03112e23 sw a7,60(sp) -800015bc: 00058613 mv a2,a1 -800015c0: 00852583 lw a1,8(a0) -800015c4: 02810793 addi a5,sp,40 -800015c8: 00078693 mv a3,a5 -800015cc: 00112e23 sw ra,28(sp) -800015d0: 00f12623 sw a5,12(sp) -800015d4: 0bc000ef jal ra,80001690 <_vfprintf_r> -800015d8: 01c12083 lw ra,28(sp) -800015dc: 04010113 addi sp,sp,64 -800015e0: 00008067 ret - -800015e4 : -800015e4: 1c81a303 lw t1,456(gp) # 80016d30 <_impure_ptr> -800015e8: fc010113 addi sp,sp,-64 -800015ec: 02c12423 sw a2,40(sp) -800015f0: 02d12623 sw a3,44(sp) -800015f4: 02f12a23 sw a5,52(sp) -800015f8: 02b12223 sw a1,36(sp) -800015fc: 02e12823 sw a4,48(sp) -80001600: 03012c23 sw a6,56(sp) -80001604: 03112e23 sw a7,60(sp) -80001608: 00832583 lw a1,8(t1) -8000160c: 02410793 addi a5,sp,36 -80001610: 00050613 mv a2,a0 -80001614: 00078693 mv a3,a5 -80001618: 00030513 mv a0,t1 -8000161c: 00112e23 sw ra,28(sp) -80001620: 00f12623 sw a5,12(sp) -80001624: 06c000ef jal ra,80001690 <_vfprintf_r> -80001628: 01c12083 lw ra,28(sp) -8000162c: 04010113 addi sp,sp,64 -80001630: 00008067 ret - -80001634 <_sbrk_r>: -80001634: ff010113 addi sp,sp,-16 -80001638: 00812423 sw s0,8(sp) -8000163c: 00912223 sw s1,4(sp) -80001640: 00050493 mv s1,a0 -80001644: 00058513 mv a0,a1 -80001648: 00112623 sw ra,12(sp) -8000164c: 2001a623 sw zero,524(gp) # 80016d74 -80001650: f19fe0ef jal ra,80000568 <_sbrk> -80001654: fff00793 li a5,-1 -80001658: 00f50c63 beq a0,a5,80001670 <_sbrk_r+0x3c> -8000165c: 00c12083 lw ra,12(sp) -80001660: 00812403 lw s0,8(sp) -80001664: 00412483 lw s1,4(sp) -80001668: 01010113 addi sp,sp,16 -8000166c: 00008067 ret -80001670: 20c1a783 lw a5,524(gp) # 80016d74 -80001674: fe0784e3 beqz a5,8000165c <_sbrk_r+0x28> -80001678: 00c12083 lw ra,12(sp) -8000167c: 00812403 lw s0,8(sp) -80001680: 00f4a023 sw a5,0(s1) -80001684: 00412483 lw s1,4(sp) -80001688: 01010113 addi sp,sp,16 -8000168c: 00008067 ret - -80001690 <_vfprintf_r>: -80001690: e1010113 addi sp,sp,-496 -80001694: 1e112623 sw ra,492(sp) -80001698: 1e812423 sw s0,488(sp) -8000169c: 1d712623 sw s7,460(sp) -800016a0: 00b12223 sw a1,4(sp) -800016a4: 00060b93 mv s7,a2 -800016a8: 00d12823 sw a3,16(sp) -800016ac: 1e912223 sw s1,484(sp) -800016b0: 1f212023 sw s2,480(sp) -800016b4: 1d312e23 sw s3,476(sp) -800016b8: 1d412c23 sw s4,472(sp) -800016bc: 1d512a23 sw s5,468(sp) -800016c0: 1d612823 sw s6,464(sp) -800016c4: 1d812423 sw s8,456(sp) -800016c8: 1d912223 sw s9,452(sp) -800016cc: 1da12023 sw s10,448(sp) -800016d0: 1bb12e23 sw s11,444(sp) -800016d4: 00050413 mv s0,a0 -800016d8: 02a12023 sw a0,32(sp) -800016dc: 64c060ef jal ra,80007d28 <_localeconv_r> -800016e0: 00052783 lw a5,0(a0) -800016e4: 00078513 mv a0,a5 -800016e8: 02f12a23 sw a5,52(sp) -800016ec: 731070ef jal ra,8000961c -800016f0: 02a12623 sw a0,44(sp) -800016f4: 0e012823 sw zero,240(sp) -800016f8: 0e012a23 sw zero,244(sp) -800016fc: 0e012c23 sw zero,248(sp) -80001700: 0e012e23 sw zero,252(sp) -80001704: 00040663 beqz s0,80001710 <_vfprintf_r+0x80> -80001708: 03842783 lw a5,56(s0) -8000170c: 540780e3 beqz a5,8000244c <_vfprintf_r+0xdbc> -80001710: 00412603 lw a2,4(sp) -80001714: 00c61703 lh a4,12(a2) -80001718: 01071793 slli a5,a4,0x10 -8000171c: 0107d793 srli a5,a5,0x10 -80001720: 01279693 slli a3,a5,0x12 -80001724: 0206c663 bltz a3,80001750 <_vfprintf_r+0xc0> -80001728: 06462683 lw a3,100(a2) -8000172c: 000027b7 lui a5,0x2 -80001730: 00f767b3 or a5,a4,a5 -80001734: ffffe737 lui a4,0xffffe -80001738: fff70713 addi a4,a4,-1 # ffffdfff <__BSS_END__+0x7ffe7287> -8000173c: 00e6f733 and a4,a3,a4 -80001740: 00f61623 sh a5,12(a2) -80001744: 01079793 slli a5,a5,0x10 -80001748: 06e62223 sw a4,100(a2) -8000174c: 0107d793 srli a5,a5,0x10 -80001750: 0087f713 andi a4,a5,8 -80001754: 16070e63 beqz a4,800018d0 <_vfprintf_r+0x240> -80001758: 00412703 lw a4,4(sp) -8000175c: 01072703 lw a4,16(a4) -80001760: 16070863 beqz a4,800018d0 <_vfprintf_r+0x240> -80001764: 01a7f793 andi a5,a5,26 -80001768: 00a00713 li a4,10 -8000176c: 18e78663 beq a5,a4,800018f8 <_vfprintf_r+0x268> -80001770: 10c10793 addi a5,sp,268 -80001774: 000b8c93 mv s9,s7 -80001778: 00078893 mv a7,a5 -8000177c: 0ef12223 sw a5,228(sp) -80001780: 000cc703 lbu a4,0(s9) -80001784: 800147b7 lui a5,0x80014 -80001788: 64478793 addi a5,a5,1604 # 80014644 <__BSS_END__+0xffffd8cc> -8000178c: 00f12623 sw a5,12(sp) -80001790: 0e012623 sw zero,236(sp) -80001794: 800147b7 lui a5,0x80014 -80001798: 0e012423 sw zero,232(sp) -8000179c: 00012e23 sw zero,28(sp) -800017a0: 02012823 sw zero,48(sp) -800017a4: 02012c23 sw zero,56(sp) -800017a8: 04012023 sw zero,64(sp) -800017ac: 04012423 sw zero,72(sp) -800017b0: 02012e23 sw zero,60(sp) -800017b4: 00012423 sw zero,8(sp) -800017b8: 7c078c13 addi s8,a5,1984 # 800147c0 <__BSS_END__+0xffffda48> -800017bc: 00088d13 mv s10,a7 -800017c0: 02012a03 lw s4,32(sp) -800017c4: 3e070863 beqz a4,80001bb4 <_vfprintf_r+0x524> -800017c8: 02500693 li a3,37 -800017cc: 00d71463 bne a4,a3,800017d4 <_vfprintf_r+0x144> -800017d0: 7780106f j 80002f48 <_vfprintf_r+0x18b8> -800017d4: 000c8413 mv s0,s9 -800017d8: 00c0006f j 800017e4 <_vfprintf_r+0x154> -800017dc: 14d78263 beq a5,a3,80001920 <_vfprintf_r+0x290> -800017e0: 00090413 mv s0,s2 -800017e4: 00144783 lbu a5,1(s0) -800017e8: 00140913 addi s2,s0,1 -800017ec: fe0798e3 bnez a5,800017dc <_vfprintf_r+0x14c> -800017f0: 419904b3 sub s1,s2,s9 -800017f4: 3c048063 beqz s1,80001bb4 <_vfprintf_r+0x524> -800017f8: 0ec12683 lw a3,236(sp) -800017fc: 0e812703 lw a4,232(sp) -80001800: 019d2023 sw s9,0(s10) -80001804: 009686b3 add a3,a3,s1 -80001808: 00170713 addi a4,a4,1 -8000180c: 009d2223 sw s1,4(s10) -80001810: 0ed12623 sw a3,236(sp) -80001814: 0ee12423 sw a4,232(sp) -80001818: 00700693 li a3,7 -8000181c: 008d0d13 addi s10,s10,8 -80001820: 10e6c663 blt a3,a4,8000192c <_vfprintf_r+0x29c> -80001824: 00812783 lw a5,8(sp) -80001828: 00144703 lbu a4,1(s0) -8000182c: 009787b3 add a5,a5,s1 -80001830: 00f12423 sw a5,8(sp) -80001834: 38070063 beqz a4,80001bb4 <_vfprintf_r+0x524> -80001838: fff00313 li t1,-1 -8000183c: 00190493 addi s1,s2,1 -80001840: 00194e03 lbu t3,1(s2) -80001844: 0c0103a3 sb zero,199(sp) -80001848: 00000413 li s0,0 -8000184c: 00000913 li s2,0 -80001850: 05a00993 li s3,90 -80001854: 00900b13 li s6,9 -80001858: 02a00b93 li s7,42 -8000185c: 00030d93 mv s11,t1 -80001860: 00148493 addi s1,s1,1 -80001864: 000e0a93 mv s5,t3 -80001868: fe0a8793 addi a5,s5,-32 -8000186c: 22f9ea63 bltu s3,a5,80001aa0 <_vfprintf_r+0x410> -80001870: 00c12703 lw a4,12(sp) -80001874: 00279793 slli a5,a5,0x2 -80001878: 00e787b3 add a5,a5,a4 -8000187c: 0007a783 lw a5,0(a5) -80001880: 00078067 jr a5 -80001884: 000a0513 mv a0,s4 -80001888: 4a0060ef jal ra,80007d28 <_localeconv_r> -8000188c: 00452783 lw a5,4(a0) -80001890: 00078513 mv a0,a5 -80001894: 02f12e23 sw a5,60(sp) -80001898: 585070ef jal ra,8000961c -8000189c: 04a12423 sw a0,72(sp) -800018a0: 00050a93 mv s5,a0 -800018a4: 000a0513 mv a0,s4 -800018a8: 480060ef jal ra,80007d28 <_localeconv_r> -800018ac: 00852783 lw a5,8(a0) -800018b0: 04f12023 sw a5,64(sp) -800018b4: 000a8463 beqz s5,800018bc <_vfprintf_r+0x22c> -800018b8: 4a80106f j 80002d60 <_vfprintf_r+0x16d0> -800018bc: 0004ce03 lbu t3,0(s1) -800018c0: fa1ff06f j 80001860 <_vfprintf_r+0x1d0> -800018c4: 02096913 ori s2,s2,32 -800018c8: 0004ce03 lbu t3,0(s1) -800018cc: f95ff06f j 80001860 <_vfprintf_r+0x1d0> -800018d0: 00412583 lw a1,4(sp) -800018d4: 02012503 lw a0,32(sp) -800018d8: 1e5020ef jal ra,800042bc <__swsetup_r> -800018dc: 00050463 beqz a0,800018e4 <_vfprintf_r+0x254> -800018e0: 4f00206f j 80003dd0 <_vfprintf_r+0x2740> -800018e4: 00412783 lw a5,4(sp) -800018e8: 00a00713 li a4,10 -800018ec: 00c7d783 lhu a5,12(a5) -800018f0: 01a7f793 andi a5,a5,26 -800018f4: e6e79ee3 bne a5,a4,80001770 <_vfprintf_r+0xe0> -800018f8: 00412783 lw a5,4(sp) -800018fc: 00e79783 lh a5,14(a5) -80001900: e607c8e3 bltz a5,80001770 <_vfprintf_r+0xe0> -80001904: 01012683 lw a3,16(sp) -80001908: 00412583 lw a1,4(sp) -8000190c: 02012503 lw a0,32(sp) -80001910: 000b8613 mv a2,s7 -80001914: 0e9020ef jal ra,800041fc <__sbprintf> -80001918: 00a12423 sw a0,8(sp) -8000191c: 0680006f j 80001984 <_vfprintf_r+0x2f4> -80001920: 419904b3 sub s1,s2,s9 -80001924: f0048ae3 beqz s1,80001838 <_vfprintf_r+0x1a8> -80001928: ed1ff06f j 800017f8 <_vfprintf_r+0x168> -8000192c: 00412583 lw a1,4(sp) -80001930: 0e410613 addi a2,sp,228 -80001934: 000a0513 mv a0,s4 -80001938: 2310a0ef jal ra,8000c368 <__sprint_r> -8000193c: 02051a63 bnez a0,80001970 <_vfprintf_r+0x2e0> -80001940: 10c10d13 addi s10,sp,268 -80001944: ee1ff06f j 80001824 <_vfprintf_r+0x194> -80001948: 00412583 lw a1,4(sp) -8000194c: 0e410613 addi a2,sp,228 -80001950: 000a0513 mv a0,s4 -80001954: 2150a0ef jal ra,8000c368 <__sprint_r> -80001958: 52050e63 beqz a0,80001e94 <_vfprintf_r+0x804> -8000195c: 01412783 lw a5,20(sp) -80001960: 00078863 beqz a5,80001970 <_vfprintf_r+0x2e0> -80001964: 02012503 lw a0,32(sp) -80001968: 00078593 mv a1,a5 -8000196c: 3bc030ef jal ra,80004d28 <_free_r> -80001970: 00412783 lw a5,4(sp) -80001974: 00c7d783 lhu a5,12(a5) -80001978: 0407f793 andi a5,a5,64 -8000197c: 00078463 beqz a5,80001984 <_vfprintf_r+0x2f4> -80001980: 4500206f j 80003dd0 <_vfprintf_r+0x2740> -80001984: 1ec12083 lw ra,492(sp) -80001988: 1e812403 lw s0,488(sp) -8000198c: 00812503 lw a0,8(sp) -80001990: 1e412483 lw s1,484(sp) -80001994: 1e012903 lw s2,480(sp) -80001998: 1dc12983 lw s3,476(sp) -8000199c: 1d812a03 lw s4,472(sp) -800019a0: 1d412a83 lw s5,468(sp) -800019a4: 1d012b03 lw s6,464(sp) -800019a8: 1cc12b83 lw s7,460(sp) -800019ac: 1c812c03 lw s8,456(sp) -800019b0: 1c412c83 lw s9,452(sp) -800019b4: 1c012d03 lw s10,448(sp) -800019b8: 1bc12d83 lw s11,444(sp) -800019bc: 1f010113 addi sp,sp,496 -800019c0: 00008067 ret -800019c4: 800147b7 lui a5,0x80014 -800019c8: 7e078793 addi a5,a5,2016 # 800147e0 <__BSS_END__+0xffffda68> -800019cc: 02f12823 sw a5,48(sp) -800019d0: 02097793 andi a5,s2,32 -800019d4: 000d8313 mv t1,s11 -800019d8: 0e078e63 beqz a5,80001ad4 <_vfprintf_r+0x444> -800019dc: 01012783 lw a5,16(sp) -800019e0: 00778793 addi a5,a5,7 -800019e4: ff87f793 andi a5,a5,-8 -800019e8: 0007ab83 lw s7,0(a5) -800019ec: 0047ad83 lw s11,4(a5) -800019f0: 00878713 addi a4,a5,8 -800019f4: 00e12823 sw a4,16(sp) -800019f8: 00197793 andi a5,s2,1 -800019fc: 00078863 beqz a5,80001a0c <_vfprintf_r+0x37c> -80001a00: 01bbe7b3 or a5,s7,s11 -80001a04: 00078463 beqz a5,80001a0c <_vfprintf_r+0x37c> -80001a08: 3ec0106f j 80002df4 <_vfprintf_r+0x1764> -80001a0c: bff97993 andi s3,s2,-1025 -80001a10: 00200793 li a5,2 -80001a14: 0c0103a3 sb zero,199(sp) -80001a18: fff00713 li a4,-1 -80001a1c: 0ae302e3 beq t1,a4,800022c0 <_vfprintf_r+0xc30> -80001a20: 01bbe733 or a4,s7,s11 -80001a24: f7f9f913 andi s2,s3,-129 -80001a28: 7a071ce3 bnez a4,800029e0 <_vfprintf_r+0x1350> -80001a2c: 2c0316e3 bnez t1,800024f8 <_vfprintf_r+0xe68> -80001a30: 22079a63 bnez a5,80001c64 <_vfprintf_r+0x5d4> -80001a34: 0019fb13 andi s6,s3,1 -80001a38: 1b010c93 addi s9,sp,432 -80001a3c: 000b0463 beqz s6,80001a44 <_vfprintf_r+0x3b4> -80001a40: 3000106f j 80002d40 <_vfprintf_r+0x16b0> -80001a44: 000b0993 mv s3,s6 -80001a48: 006b5463 bge s6,t1,80001a50 <_vfprintf_r+0x3c0> -80001a4c: 00030993 mv s3,t1 -80001a50: 0c714703 lbu a4,199(sp) -80001a54: 00012a23 sw zero,20(sp) -80001a58: 02012423 sw zero,40(sp) -80001a5c: 02012223 sw zero,36(sp) -80001a60: 00012c23 sw zero,24(sp) -80001a64: 32070e63 beqz a4,80001da0 <_vfprintf_r+0x710> -80001a68: 00198993 addi s3,s3,1 -80001a6c: 3340006f j 80001da0 <_vfprintf_r+0x710> -80001a70: 00000413 li s0,0 -80001a74: fd0a8713 addi a4,s5,-48 -80001a78: 00148493 addi s1,s1,1 -80001a7c: 00241793 slli a5,s0,0x2 -80001a80: fff4ca83 lbu s5,-1(s1) -80001a84: 008787b3 add a5,a5,s0 -80001a88: 00179793 slli a5,a5,0x1 -80001a8c: 00f70433 add s0,a4,a5 -80001a90: fd0a8713 addi a4,s5,-48 -80001a94: feeb72e3 bgeu s6,a4,80001a78 <_vfprintf_r+0x3e8> -80001a98: fe0a8793 addi a5,s5,-32 -80001a9c: dcf9fae3 bgeu s3,a5,80001870 <_vfprintf_r+0x1e0> -80001aa0: 100a8a63 beqz s5,80001bb4 <_vfprintf_r+0x524> -80001aa4: 15510623 sb s5,332(sp) -80001aa8: 0c0103a3 sb zero,199(sp) -80001aac: 00100993 li s3,1 -80001ab0: 00100b13 li s6,1 -80001ab4: 14c10c93 addi s9,sp,332 -80001ab8: 2d40006f j 80001d8c <_vfprintf_r+0x6fc> -80001abc: 800147b7 lui a5,0x80014 -80001ac0: 7f478793 addi a5,a5,2036 # 800147f4 <__BSS_END__+0xffffda7c> -80001ac4: 02f12823 sw a5,48(sp) -80001ac8: 02097793 andi a5,s2,32 -80001acc: 000d8313 mv t1,s11 -80001ad0: f00796e3 bnez a5,800019dc <_vfprintf_r+0x34c> -80001ad4: 01012703 lw a4,16(sp) -80001ad8: 01097793 andi a5,s2,16 -80001adc: 00072b83 lw s7,0(a4) -80001ae0: 00470713 addi a4,a4,4 -80001ae4: 00e12823 sw a4,16(sp) -80001ae8: 00078463 beqz a5,80001af0 <_vfprintf_r+0x460> -80001aec: 26c0106f j 80002d58 <_vfprintf_r+0x16c8> -80001af0: 04097793 andi a5,s2,64 -80001af4: 00079463 bnez a5,80001afc <_vfprintf_r+0x46c> -80001af8: 2580106f j 80002d50 <_vfprintf_r+0x16c0> -80001afc: 010b9b93 slli s7,s7,0x10 -80001b00: 010bdb93 srli s7,s7,0x10 -80001b04: 00000d93 li s11,0 -80001b08: ef1ff06f j 800019f8 <_vfprintf_r+0x368> -80001b0c: 0004ce03 lbu t3,0(s1) -80001b10: 00496913 ori s2,s2,4 -80001b14: d4dff06f j 80001860 <_vfprintf_r+0x1d0> -80001b18: 0004ca83 lbu s5,0(s1) -80001b1c: 00148793 addi a5,s1,1 -80001b20: 017a9463 bne s5,s7,80001b28 <_vfprintf_r+0x498> -80001b24: 6680206f j 8000418c <_vfprintf_r+0x2afc> -80001b28: fd0a8713 addi a4,s5,-48 -80001b2c: 00078493 mv s1,a5 -80001b30: 00000d93 li s11,0 -80001b34: d2eb6ae3 bltu s6,a4,80001868 <_vfprintf_r+0x1d8> -80001b38: 00148493 addi s1,s1,1 -80001b3c: 002d9793 slli a5,s11,0x2 -80001b40: fff4ca83 lbu s5,-1(s1) -80001b44: 01b787b3 add a5,a5,s11 -80001b48: 00179793 slli a5,a5,0x1 -80001b4c: 00e78db3 add s11,a5,a4 -80001b50: fd0a8713 addi a4,s5,-48 -80001b54: feeb72e3 bgeu s6,a4,80001b38 <_vfprintf_r+0x4a8> -80001b58: d11ff06f j 80001868 <_vfprintf_r+0x1d8> -80001b5c: 01012683 lw a3,16(sp) -80001b60: 02097793 andi a5,s2,32 -80001b64: 00468713 addi a4,a3,4 -80001b68: 00078463 beqz a5,80001b70 <_vfprintf_r+0x4e0> -80001b6c: 2680106f j 80002dd4 <_vfprintf_r+0x1744> -80001b70: 01097793 andi a5,s2,16 -80001b74: 00078463 beqz a5,80001b7c <_vfprintf_r+0x4ec> -80001b78: 6540106f j 800031cc <_vfprintf_r+0x1b3c> -80001b7c: 04097793 andi a5,s2,64 -80001b80: 00078463 beqz a5,80001b88 <_vfprintf_r+0x4f8> -80001b84: 2250106f j 800035a8 <_vfprintf_r+0x1f18> -80001b88: 20097913 andi s2,s2,512 -80001b8c: 00091463 bnez s2,80001b94 <_vfprintf_r+0x504> -80001b90: 63c0106f j 800031cc <_vfprintf_r+0x1b3c> -80001b94: 01012783 lw a5,16(sp) -80001b98: 00e12823 sw a4,16(sp) -80001b9c: 00812703 lw a4,8(sp) -80001ba0: 0007a783 lw a5,0(a5) -80001ba4: 00048c93 mv s9,s1 -80001ba8: 00e78023 sb a4,0(a5) -80001bac: 000cc703 lbu a4,0(s9) -80001bb0: c0071ce3 bnez a4,800017c8 <_vfprintf_r+0x138> -80001bb4: 0ec12783 lw a5,236(sp) -80001bb8: da078ce3 beqz a5,80001970 <_vfprintf_r+0x2e0> -80001bbc: 00412583 lw a1,4(sp) -80001bc0: 02012503 lw a0,32(sp) -80001bc4: 0e410613 addi a2,sp,228 -80001bc8: 7a00a0ef jal ra,8000c368 <__sprint_r> -80001bcc: da5ff06f j 80001970 <_vfprintf_r+0x2e0> -80001bd0: 0004ce03 lbu t3,0(s1) -80001bd4: 06c00793 li a5,108 -80001bd8: 00fe1463 bne t3,a5,80001be0 <_vfprintf_r+0x550> -80001bdc: 2c00106f j 80002e9c <_vfprintf_r+0x180c> -80001be0: 01096913 ori s2,s2,16 -80001be4: c7dff06f j 80001860 <_vfprintf_r+0x1d0> -80001be8: 0004ce03 lbu t3,0(s1) -80001bec: 06800793 li a5,104 -80001bf0: 00fe1463 bne t3,a5,80001bf8 <_vfprintf_r+0x568> -80001bf4: 2b80106f j 80002eac <_vfprintf_r+0x181c> -80001bf8: 04096913 ori s2,s2,64 -80001bfc: c65ff06f j 80001860 <_vfprintf_r+0x1d0> -80001c00: 02097793 andi a5,s2,32 -80001c04: 000d8313 mv t1,s11 -80001c08: 040798e3 bnez a5,80002458 <_vfprintf_r+0xdc8> -80001c0c: 01012783 lw a5,16(sp) -80001c10: 01097713 andi a4,s2,16 -80001c14: 00478793 addi a5,a5,4 -80001c18: 00070463 beqz a4,80001c20 <_vfprintf_r+0x590> -80001c1c: 5940206f j 800041b0 <_vfprintf_r+0x2b20> -80001c20: 04097713 andi a4,s2,64 -80001c24: 00071463 bnez a4,80001c2c <_vfprintf_r+0x59c> -80001c28: 6700106f j 80003298 <_vfprintf_r+0x1c08> -80001c2c: 01012703 lw a4,16(sp) -80001c30: 00090993 mv s3,s2 -80001c34: 00f12823 sw a5,16(sp) -80001c38: 00071b83 lh s7,0(a4) -80001c3c: 41fbdd93 srai s11,s7,0x1f -80001c40: 000d8713 mv a4,s11 -80001c44: 64074c63 bltz a4,8000229c <_vfprintf_r+0xc0c> -80001c48: fff00793 li a5,-1 -80001c4c: 08f304e3 beq t1,a5,800024d4 <_vfprintf_r+0xe44> -80001c50: 01bbe7b3 or a5,s7,s11 -80001c54: f7f9f913 andi s2,s3,-129 -80001c58: 06079ce3 bnez a5,800024d0 <_vfprintf_r+0xe40> -80001c5c: 00030463 beqz t1,80001c64 <_vfprintf_r+0x5d4> -80001c60: 5b50106f j 80003a14 <_vfprintf_r+0x2384> -80001c64: 00000313 li t1,0 -80001c68: 00000b13 li s6,0 -80001c6c: 1b010c93 addi s9,sp,432 -80001c70: dd5ff06f j 80001a44 <_vfprintf_r+0x3b4> -80001c74: 08096913 ori s2,s2,128 -80001c78: 0004ce03 lbu t3,0(s1) -80001c7c: be5ff06f j 80001860 <_vfprintf_r+0x1d0> -80001c80: 02097793 andi a5,s2,32 -80001c84: 000d8313 mv t1,s11 -80001c88: 01096993 ori s3,s2,16 -80001c8c: 7e079c63 bnez a5,80002484 <_vfprintf_r+0xdf4> -80001c90: 01012783 lw a5,16(sp) -80001c94: 00478793 addi a5,a5,4 -80001c98: 01012703 lw a4,16(sp) -80001c9c: 00000d93 li s11,0 -80001ca0: 00f12823 sw a5,16(sp) -80001ca4: 00072b83 lw s7,0(a4) -80001ca8: 00100793 li a5,1 -80001cac: d69ff06f j 80001a14 <_vfprintf_r+0x384> -80001cb0: 01012783 lw a5,16(sp) -80001cb4: 0c0103a3 sb zero,199(sp) -80001cb8: 0007ac83 lw s9,0(a5) -80001cbc: 00478b93 addi s7,a5,4 -80001cc0: 000c9463 bnez s9,80001cc8 <_vfprintf_r+0x638> -80001cc4: 1f80106f j 80002ebc <_vfprintf_r+0x182c> -80001cc8: fff00713 li a4,-1 -80001ccc: 00ed9463 bne s11,a4,80001cd4 <_vfprintf_r+0x644> -80001cd0: 5180106f j 800031e8 <_vfprintf_r+0x1b58> -80001cd4: 000d8613 mv a2,s11 -80001cd8: 00000593 li a1,0 -80001cdc: 000c8513 mv a0,s9 -80001ce0: 01b12823 sw s11,16(sp) -80001ce4: 348060ef jal ra,8000802c -80001ce8: 00a12a23 sw a0,20(sp) -80001cec: 01012303 lw t1,16(sp) -80001cf0: 00051463 bnez a0,80001cf8 <_vfprintf_r+0x668> -80001cf4: 7fd0106f j 80003cf0 <_vfprintf_r+0x2660> -80001cf8: 01412783 lw a5,20(sp) -80001cfc: 41978b33 sub s6,a5,s9 -80001d00: 0c714703 lbu a4,199(sp) -80001d04: fffb4993 not s3,s6 -80001d08: 41f9d993 srai s3,s3,0x1f -80001d0c: 01712823 sw s7,16(sp) -80001d10: 00012a23 sw zero,20(sp) -80001d14: 02012423 sw zero,40(sp) -80001d18: 02012223 sw zero,36(sp) -80001d1c: 00012c23 sw zero,24(sp) -80001d20: 013b79b3 and s3,s6,s3 -80001d24: 00000313 li t1,0 -80001d28: d40710e3 bnez a4,80001a68 <_vfprintf_r+0x3d8> -80001d2c: 0740006f j 80001da0 <_vfprintf_r+0x710> -80001d30: 02097793 andi a5,s2,32 -80001d34: 000d8313 mv t1,s11 -80001d38: 01096913 ori s2,s2,16 -80001d3c: 76079663 bnez a5,800024a8 <_vfprintf_r+0xe18> -80001d40: 01012783 lw a5,16(sp) -80001d44: 00478793 addi a5,a5,4 -80001d48: 01012703 lw a4,16(sp) -80001d4c: 00000d93 li s11,0 -80001d50: 00f12823 sw a5,16(sp) -80001d54: 00072b83 lw s7,0(a4) -80001d58: 76c0006f j 800024c4 <_vfprintf_r+0xe34> -80001d5c: 00896913 ori s2,s2,8 -80001d60: 0004ce03 lbu t3,0(s1) -80001d64: afdff06f j 80001860 <_vfprintf_r+0x1d0> -80001d68: 01012703 lw a4,16(sp) -80001d6c: 0c0103a3 sb zero,199(sp) -80001d70: 00100993 li s3,1 -80001d74: 00072783 lw a5,0(a4) -80001d78: 00470713 addi a4,a4,4 -80001d7c: 00e12823 sw a4,16(sp) -80001d80: 14f10623 sb a5,332(sp) -80001d84: 00100b13 li s6,1 -80001d88: 14c10c93 addi s9,sp,332 -80001d8c: 00012a23 sw zero,20(sp) -80001d90: 00000313 li t1,0 -80001d94: 02012423 sw zero,40(sp) -80001d98: 02012223 sw zero,36(sp) -80001d9c: 00012c23 sw zero,24(sp) -80001da0: 00297293 andi t0,s2,2 -80001da4: 00028463 beqz t0,80001dac <_vfprintf_r+0x71c> -80001da8: 00298993 addi s3,s3,2 -80001dac: 08497b93 andi s7,s2,132 -80001db0: 0ec12703 lw a4,236(sp) -80001db4: 000b9663 bnez s7,80001dc0 <_vfprintf_r+0x730> -80001db8: 41340833 sub a6,s0,s3 -80001dbc: 430046e3 bgtz a6,800029e8 <_vfprintf_r+0x1358> -80001dc0: 0c714683 lbu a3,199(sp) -80001dc4: 02068a63 beqz a3,80001df8 <_vfprintf_r+0x768> -80001dc8: 0e812683 lw a3,232(sp) -80001dcc: 0c710613 addi a2,sp,199 -80001dd0: 00cd2023 sw a2,0(s10) -80001dd4: 00170713 addi a4,a4,1 -80001dd8: 00100613 li a2,1 -80001ddc: 00168693 addi a3,a3,1 -80001de0: 00cd2223 sw a2,4(s10) -80001de4: 0ee12623 sw a4,236(sp) -80001de8: 0ed12423 sw a3,232(sp) -80001dec: 00700613 li a2,7 -80001df0: 008d0d13 addi s10,s10,8 -80001df4: 0cd64263 blt a2,a3,80001eb8 <_vfprintf_r+0x828> -80001df8: 02028a63 beqz t0,80001e2c <_vfprintf_r+0x79c> -80001dfc: 0e812683 lw a3,232(sp) -80001e00: 0c810613 addi a2,sp,200 -80001e04: 00cd2023 sw a2,0(s10) -80001e08: 00270713 addi a4,a4,2 -80001e0c: 00200613 li a2,2 -80001e10: 00168693 addi a3,a3,1 -80001e14: 00cd2223 sw a2,4(s10) -80001e18: 0ee12623 sw a4,236(sp) -80001e1c: 0ed12423 sw a3,232(sp) -80001e20: 00700613 li a2,7 -80001e24: 008d0d13 addi s10,s10,8 -80001e28: 4ed648e3 blt a2,a3,80002b18 <_vfprintf_r+0x1488> -80001e2c: 08000693 li a3,128 -80001e30: 06db86e3 beq s7,a3,8000269c <_vfprintf_r+0x100c> -80001e34: 41630db3 sub s11,t1,s6 -80001e38: 17b044e3 bgtz s11,800027a0 <_vfprintf_r+0x1110> -80001e3c: 10097693 andi a3,s2,256 -80001e40: 70069a63 bnez a3,80002554 <_vfprintf_r+0xec4> -80001e44: 0e812783 lw a5,232(sp) -80001e48: 01670733 add a4,a4,s6 -80001e4c: 019d2023 sw s9,0(s10) -80001e50: 00178793 addi a5,a5,1 -80001e54: 016d2223 sw s6,4(s10) -80001e58: 0ee12623 sw a4,236(sp) -80001e5c: 0ef12423 sw a5,232(sp) -80001e60: 00700693 li a3,7 -80001e64: 008d0d13 addi s10,s10,8 -80001e68: 24f6cee3 blt a3,a5,800028c4 <_vfprintf_r+0x1234> -80001e6c: 00497913 andi s2,s2,4 -80001e70: 00090663 beqz s2,80001e7c <_vfprintf_r+0x7ec> -80001e74: 41340933 sub s2,s0,s3 -80001e78: 07204863 bgtz s2,80001ee8 <_vfprintf_r+0x858> -80001e7c: 01345463 bge s0,s3,80001e84 <_vfprintf_r+0x7f4> -80001e80: 00098413 mv s0,s3 -80001e84: 00812783 lw a5,8(sp) -80001e88: 008787b3 add a5,a5,s0 -80001e8c: 00f12423 sw a5,8(sp) -80001e90: aa071ce3 bnez a4,80001948 <_vfprintf_r+0x2b8> -80001e94: 01412783 lw a5,20(sp) -80001e98: 0e012423 sw zero,232(sp) -80001e9c: 00078863 beqz a5,80001eac <_vfprintf_r+0x81c> -80001ea0: 01412583 lw a1,20(sp) -80001ea4: 000a0513 mv a0,s4 -80001ea8: 681020ef jal ra,80004d28 <_free_r> -80001eac: 10c10d13 addi s10,sp,268 -80001eb0: 00048c93 mv s9,s1 -80001eb4: cf9ff06f j 80001bac <_vfprintf_r+0x51c> -80001eb8: 00412583 lw a1,4(sp) -80001ebc: 0e410613 addi a2,sp,228 -80001ec0: 000a0513 mv a0,s4 -80001ec4: 04612623 sw t1,76(sp) -80001ec8: 04512223 sw t0,68(sp) -80001ecc: 49c0a0ef jal ra,8000c368 <__sprint_r> -80001ed0: a80516e3 bnez a0,8000195c <_vfprintf_r+0x2cc> -80001ed4: 0ec12703 lw a4,236(sp) -80001ed8: 10c10d13 addi s10,sp,268 -80001edc: 04c12303 lw t1,76(sp) -80001ee0: 04412283 lw t0,68(sp) -80001ee4: f15ff06f j 80001df8 <_vfprintf_r+0x768> -80001ee8: 01000693 li a3,16 -80001eec: 0e812783 lw a5,232(sp) -80001ef0: 0126c463 blt a3,s2,80001ef8 <_vfprintf_r+0x868> -80001ef4: 6d10106f j 80003dc4 <_vfprintf_r+0x2734> -80001ef8: 800146b7 lui a3,0x80014 -80001efc: 7b068d93 addi s11,a3,1968 # 800147b0 <__BSS_END__+0xffffda38> -80001f00: 01000b13 li s6,16 -80001f04: 00700b93 li s7,7 -80001f08: 00412a83 lw s5,4(sp) -80001f0c: 00c0006f j 80001f18 <_vfprintf_r+0x888> -80001f10: ff090913 addi s2,s2,-16 -80001f14: 052b5663 bge s6,s2,80001f60 <_vfprintf_r+0x8d0> -80001f18: 01070713 addi a4,a4,16 -80001f1c: 00178793 addi a5,a5,1 -80001f20: 01bd2023 sw s11,0(s10) -80001f24: 016d2223 sw s6,4(s10) -80001f28: 0ee12623 sw a4,236(sp) -80001f2c: 0ef12423 sw a5,232(sp) -80001f30: 008d0d13 addi s10,s10,8 -80001f34: fcfbdee3 bge s7,a5,80001f10 <_vfprintf_r+0x880> -80001f38: 0e410613 addi a2,sp,228 -80001f3c: 000a8593 mv a1,s5 -80001f40: 000a0513 mv a0,s4 -80001f44: 4240a0ef jal ra,8000c368 <__sprint_r> -80001f48: a0051ae3 bnez a0,8000195c <_vfprintf_r+0x2cc> -80001f4c: ff090913 addi s2,s2,-16 -80001f50: 0ec12703 lw a4,236(sp) -80001f54: 0e812783 lw a5,232(sp) -80001f58: 10c10d13 addi s10,sp,268 -80001f5c: fb2b4ee3 blt s6,s2,80001f18 <_vfprintf_r+0x888> -80001f60: 01270733 add a4,a4,s2 -80001f64: 00178793 addi a5,a5,1 -80001f68: 01bd2023 sw s11,0(s10) -80001f6c: 012d2223 sw s2,4(s10) -80001f70: 0ee12623 sw a4,236(sp) -80001f74: 0ef12423 sw a5,232(sp) -80001f78: 00700693 li a3,7 -80001f7c: f0f6d0e3 bge a3,a5,80001e7c <_vfprintf_r+0x7ec> -80001f80: 00412583 lw a1,4(sp) -80001f84: 0e410613 addi a2,sp,228 -80001f88: 000a0513 mv a0,s4 -80001f8c: 3dc0a0ef jal ra,8000c368 <__sprint_r> -80001f90: 9c0516e3 bnez a0,8000195c <_vfprintf_r+0x2cc> -80001f94: 0ec12703 lw a4,236(sp) -80001f98: ee5ff06f j 80001e7c <_vfprintf_r+0x7ec> -80001f9c: 00897713 andi a4,s2,8 -80001fa0: 000d8313 mv t1,s11 -80001fa4: 5e0700e3 beqz a4,80002d84 <_vfprintf_r+0x16f4> -80001fa8: 01012783 lw a5,16(sp) -80001fac: 0007a703 lw a4,0(a5) -80001fb0: 00478793 addi a5,a5,4 -80001fb4: 00f12823 sw a5,16(sp) -80001fb8: 00072583 lw a1,0(a4) -80001fbc: 00472603 lw a2,4(a4) -80001fc0: 00872683 lw a3,8(a4) -80001fc4: 00c72703 lw a4,12(a4) -80001fc8: 0eb12823 sw a1,240(sp) -80001fcc: 0ec12a23 sw a2,244(sp) -80001fd0: 0ed12c23 sw a3,248(sp) -80001fd4: 0ee12e23 sw a4,252(sp) -80001fd8: 0f010513 addi a0,sp,240 -80001fdc: 00612a23 sw t1,20(sp) -80001fe0: 4dd050ef jal ra,80007cbc <_ldcheck> -80001fe4: 0ca12623 sw a0,204(sp) -80001fe8: 00200713 li a4,2 -80001fec: 01412303 lw t1,20(sp) -80001ff0: 00e51463 bne a0,a4,80001ff8 <_vfprintf_r+0x968> -80001ff4: 1580106f j 8000314c <_vfprintf_r+0x1abc> -80001ff8: 00100713 li a4,1 -80001ffc: 00e51463 bne a0,a4,80002004 <_vfprintf_r+0x974> -80002000: 2f40106f j 800032f4 <_vfprintf_r+0x1c64> -80002004: 06100713 li a4,97 -80002008: 00ea9463 bne s5,a4,80002010 <_vfprintf_r+0x980> -8000200c: 7110106f j 80003f1c <_vfprintf_r+0x288c> -80002010: 04100713 li a4,65 -80002014: 00ea9463 bne s5,a4,8000201c <_vfprintf_r+0x98c> -80002018: 62c0106f j 80003644 <_vfprintf_r+0x1fb4> -8000201c: fdfaf793 andi a5,s5,-33 -80002020: fff00713 li a4,-1 -80002024: 04f12623 sw a5,76(sp) -80002028: 00e31463 bne t1,a4,80002030 <_vfprintf_r+0x9a0> -8000202c: 71d0106f j 80003f48 <_vfprintf_r+0x28b8> -80002030: 04700713 li a4,71 -80002034: 00e79463 bne a5,a4,8000203c <_vfprintf_r+0x9ac> -80002038: 7010106f j 80003f38 <_vfprintf_r+0x28a8> -8000203c: 0fc12e83 lw t4,252(sp) -80002040: 05212c23 sw s2,88(sp) -80002044: 10096713 ori a4,s2,256 -80002048: 0f012283 lw t0,240(sp) -8000204c: 0f412f03 lw t5,244(sp) -80002050: 0f812f83 lw t6,248(sp) -80002054: 000ed463 bgez t4,8000205c <_vfprintf_r+0x9cc> -80002058: 27d0106f j 80003ad4 <_vfprintf_r+0x2444> -8000205c: 04012e23 sw zero,92(sp) -80002060: 00070913 mv s2,a4 -80002064: 00012a23 sw zero,20(sp) -80002068: 04c12703 lw a4,76(sp) -8000206c: 04600793 li a5,70 -80002070: 00f71463 bne a4,a5,80002078 <_vfprintf_r+0x9e8> -80002074: 3050106f j 80003b78 <_vfprintf_r+0x24e8> -80002078: 04500793 li a5,69 -8000207c: 00f71463 bne a4,a5,80002084 <_vfprintf_r+0x9f4> -80002080: 6090106f j 80003e88 <_vfprintf_r+0x27f8> -80002084: 0b010993 addi s3,sp,176 -80002088: 0d010793 addi a5,sp,208 -8000208c: 0cc10713 addi a4,sp,204 -80002090: 00030693 mv a3,t1 -80002094: 0dc10813 addi a6,sp,220 -80002098: 00200613 li a2,2 -8000209c: 00098593 mv a1,s3 -800020a0: 000a0513 mv a0,s4 -800020a4: 04612223 sw t1,68(sp) -800020a8: 0a512823 sw t0,176(sp) -800020ac: 02512423 sw t0,40(sp) -800020b0: 0be12a23 sw t5,180(sp) -800020b4: 03e12223 sw t5,36(sp) -800020b8: 0bf12c23 sw t6,184(sp) -800020bc: 01f12e23 sw t6,28(sp) -800020c0: 0bd12e23 sw t4,188(sp) -800020c4: 01d12c23 sw t4,24(sp) -800020c8: 0e1040ef jal ra,800069a8 <_ldtoa_r> -800020cc: 04c12783 lw a5,76(sp) -800020d0: 04700713 li a4,71 -800020d4: 00050c93 mv s9,a0 -800020d8: 01812e83 lw t4,24(sp) -800020dc: 01c12f83 lw t6,28(sp) -800020e0: 02412f03 lw t5,36(sp) -800020e4: 02812283 lw t0,40(sp) -800020e8: 04412303 lw t1,68(sp) -800020ec: 00e78463 beq a5,a4,800020f4 <_vfprintf_r+0xa64> -800020f0: 0dc0206f j 800041cc <_vfprintf_r+0x2b3c> -800020f4: 05812783 lw a5,88(sp) -800020f8: 0017f713 andi a4,a5,1 -800020fc: 00070463 beqz a4,80002104 <_vfprintf_r+0xa74> -80002100: 62d0106f j 80003f2c <_vfprintf_r+0x289c> -80002104: 0dc12703 lw a4,220(sp) -80002108: 419707b3 sub a5,a4,s9 -8000210c: 00f12e23 sw a5,28(sp) -80002110: 0cc12783 lw a5,204(sp) -80002114: 04700713 li a4,71 -80002118: 00f12c23 sw a5,24(sp) -8000211c: 04c12783 lw a5,76(sp) -80002120: 00e79463 bne a5,a4,80002128 <_vfprintf_r+0xa98> -80002124: 1290106f j 80003a4c <_vfprintf_r+0x23bc> -80002128: 04c12783 lw a5,76(sp) -8000212c: 04600713 li a4,70 -80002130: 00e79463 bne a5,a4,80002138 <_vfprintf_r+0xaa8> -80002134: 3e90106f j 80003d1c <_vfprintf_r+0x268c> -80002138: 01812783 lw a5,24(sp) -8000213c: 04100593 li a1,65 -80002140: 0ffaf693 andi a3,s5,255 -80002144: fff78713 addi a4,a5,-1 -80002148: 04c12783 lw a5,76(sp) -8000214c: 0ce12623 sw a4,204(sp) -80002150: 00000613 li a2,0 -80002154: 00b79863 bne a5,a1,80002164 <_vfprintf_r+0xad4> -80002158: 00f68693 addi a3,a3,15 -8000215c: 0ff6f693 andi a3,a3,255 -80002160: 00100613 li a2,1 -80002164: 0cd10a23 sb a3,212(sp) -80002168: 00075463 bgez a4,80002170 <_vfprintf_r+0xae0> -8000216c: 7b90106f j 80004124 <_vfprintf_r+0x2a94> -80002170: 02b00693 li a3,43 -80002174: 0cd10aa3 sb a3,213(sp) -80002178: 00900693 li a3,9 -8000217c: 00e6c463 blt a3,a4,80002184 <_vfprintf_r+0xaf4> -80002180: 66d0106f j 80003fec <_vfprintf_r+0x295c> -80002184: 0e310813 addi a6,sp,227 -80002188: 00080613 mv a2,a6 -8000218c: 00a00513 li a0,10 -80002190: 06300313 li t1,99 -80002194: 00c0006f j 800021a0 <_vfprintf_r+0xb10> -80002198: 00058613 mv a2,a1 -8000219c: 00068713 mv a4,a3 -800021a0: 02a767b3 rem a5,a4,a0 -800021a4: fff60593 addi a1,a2,-1 -800021a8: 03078793 addi a5,a5,48 -800021ac: fef60fa3 sb a5,-1(a2) -800021b0: 02a746b3 div a3,a4,a0 -800021b4: fee342e3 blt t1,a4,80002198 <_vfprintf_r+0xb08> -800021b8: 03068713 addi a4,a3,48 -800021bc: 0ff77713 andi a4,a4,255 -800021c0: ffe60693 addi a3,a2,-2 -800021c4: fee58fa3 sb a4,-1(a1) -800021c8: 0106e463 bltu a3,a6,800021d0 <_vfprintf_r+0xb40> -800021cc: 7f50106f j 800041c0 <_vfprintf_r+0x2b30> -800021d0: 0d610593 addi a1,sp,214 -800021d4: 0080006f j 800021dc <_vfprintf_r+0xb4c> -800021d8: 0006c703 lbu a4,0(a3) -800021dc: 00158593 addi a1,a1,1 -800021e0: 00168693 addi a3,a3,1 -800021e4: fee58fa3 sb a4,-1(a1) -800021e8: ff0698e3 bne a3,a6,800021d8 <_vfprintf_r+0xb48> -800021ec: 0e510713 addi a4,sp,229 -800021f0: 0d610793 addi a5,sp,214 -800021f4: 40c70733 sub a4,a4,a2 -800021f8: 00e78733 add a4,a5,a4 -800021fc: 0d410693 addi a3,sp,212 -80002200: 40d707b3 sub a5,a4,a3 -80002204: 02f12c23 sw a5,56(sp) -80002208: 01c12783 lw a5,28(sp) -8000220c: 03812683 lw a3,56(sp) -80002210: 00100713 li a4,1 -80002214: 00d78b33 add s6,a5,a3 -80002218: 00f74463 blt a4,a5,80002220 <_vfprintf_r+0xb90> -8000221c: 7210106f j 8000413c <_vfprintf_r+0x2aac> -80002220: 02c12783 lw a5,44(sp) -80002224: 00fb0b33 add s6,s6,a5 -80002228: 05812783 lw a5,88(sp) -8000222c: fffb4993 not s3,s6 -80002230: 41f9d993 srai s3,s3,0x1f -80002234: bff7f913 andi s2,a5,-1025 -80002238: 10096913 ori s2,s2,256 -8000223c: 013b79b3 and s3,s6,s3 -80002240: 02012423 sw zero,40(sp) -80002244: 02012223 sw zero,36(sp) -80002248: 00012c23 sw zero,24(sp) -8000224c: 05c12783 lw a5,92(sp) -80002250: 00079463 bnez a5,80002258 <_vfprintf_r+0xbc8> -80002254: 06d0106f j 80003ac0 <_vfprintf_r+0x2430> -80002258: 02d00713 li a4,45 -8000225c: 0ce103a3 sb a4,199(sp) -80002260: 00000313 li t1,0 -80002264: 00198993 addi s3,s3,1 -80002268: b39ff06f j 80001da0 <_vfprintf_r+0x710> -8000226c: 02097793 andi a5,s2,32 -80002270: 000d8313 mv t1,s11 -80002274: 01096993 ori s3,s2,16 -80002278: 1e079263 bnez a5,8000245c <_vfprintf_r+0xdcc> -8000227c: 01012783 lw a5,16(sp) -80002280: 00478793 addi a5,a5,4 -80002284: 01012703 lw a4,16(sp) -80002288: 00f12823 sw a5,16(sp) -8000228c: 00072b83 lw s7,0(a4) -80002290: 41fbdd93 srai s11,s7,0x1f -80002294: 000d8713 mv a4,s11 -80002298: 9a0758e3 bgez a4,80001c48 <_vfprintf_r+0x5b8> -8000229c: 41700bb3 neg s7,s7 -800022a0: 017037b3 snez a5,s7 -800022a4: 41b00db3 neg s11,s11 -800022a8: 40fd8db3 sub s11,s11,a5 -800022ac: 02d00793 li a5,45 -800022b0: 0cf103a3 sb a5,199(sp) -800022b4: fff00713 li a4,-1 -800022b8: 00100793 li a5,1 -800022bc: f6e31263 bne t1,a4,80001a20 <_vfprintf_r+0x390> -800022c0: 00100713 li a4,1 -800022c4: 20e78863 beq a5,a4,800024d4 <_vfprintf_r+0xe44> -800022c8: 00200713 li a4,2 -800022cc: 24e78263 beq a5,a4,80002510 <_vfprintf_r+0xe80> -800022d0: 1b010693 addi a3,sp,432 -800022d4: 0080006f j 800022dc <_vfprintf_r+0xc4c> -800022d8: 000c8693 mv a3,s9 -800022dc: 01dd9793 slli a5,s11,0x1d -800022e0: 007bf713 andi a4,s7,7 -800022e4: 003bdb93 srli s7,s7,0x3 -800022e8: 03070713 addi a4,a4,48 -800022ec: 0177ebb3 or s7,a5,s7 -800022f0: 003ddd93 srli s11,s11,0x3 -800022f4: fee68fa3 sb a4,-1(a3) -800022f8: 01bbe7b3 or a5,s7,s11 -800022fc: fff68c93 addi s9,a3,-1 -80002300: fc079ce3 bnez a5,800022d8 <_vfprintf_r+0xc48> -80002304: 0019f613 andi a2,s3,1 -80002308: 22060e63 beqz a2,80002544 <_vfprintf_r+0xeb4> -8000230c: 03000613 li a2,48 -80002310: 22c70a63 beq a4,a2,80002544 <_vfprintf_r+0xeb4> -80002314: ffe68693 addi a3,a3,-2 -80002318: 1b010793 addi a5,sp,432 -8000231c: fecc8fa3 sb a2,-1(s9) -80002320: 40d78b33 sub s6,a5,a3 -80002324: 00098913 mv s2,s3 -80002328: 00068c93 mv s9,a3 -8000232c: f18ff06f j 80001a44 <_vfprintf_r+0x3b4> -80002330: 01012703 lw a4,16(sp) -80002334: ffff87b7 lui a5,0xffff8 -80002338: 8307c793 xori a5,a5,-2000 -8000233c: 0cf11423 sh a5,200(sp) -80002340: 00470793 addi a5,a4,4 -80002344: 00f12823 sw a5,16(sp) -80002348: 800147b7 lui a5,0x80014 -8000234c: 7e078793 addi a5,a5,2016 # 800147e0 <__BSS_END__+0xffffda68> -80002350: 000d8313 mv t1,s11 -80002354: 02f12823 sw a5,48(sp) -80002358: 00072b83 lw s7,0(a4) -8000235c: 00000d93 li s11,0 -80002360: 00296993 ori s3,s2,2 -80002364: 00200793 li a5,2 -80002368: 07800a93 li s5,120 -8000236c: ea8ff06f j 80001a14 <_vfprintf_r+0x384> -80002370: 0c714783 lbu a5,199(sp) -80002374: 0004ce03 lbu t3,0(s1) -80002378: ce079463 bnez a5,80001860 <_vfprintf_r+0x1d0> -8000237c: 02000793 li a5,32 -80002380: 0cf103a3 sb a5,199(sp) -80002384: cdcff06f j 80001860 <_vfprintf_r+0x1d0> -80002388: 02b00793 li a5,43 -8000238c: 0cf103a3 sb a5,199(sp) -80002390: 0004ce03 lbu t3,0(s1) -80002394: cccff06f j 80001860 <_vfprintf_r+0x1d0> -80002398: 01012783 lw a5,16(sp) -8000239c: 0004ce03 lbu t3,0(s1) -800023a0: 0007a403 lw s0,0(a5) -800023a4: 00478793 addi a5,a5,4 -800023a8: 00f12823 sw a5,16(sp) -800023ac: ca045a63 bgez s0,80001860 <_vfprintf_r+0x1d0> -800023b0: 40800433 neg s0,s0 -800023b4: 00496913 ori s2,s2,4 -800023b8: ca8ff06f j 80001860 <_vfprintf_r+0x1d0> -800023bc: 00196913 ori s2,s2,1 -800023c0: 0004ce03 lbu t3,0(s1) -800023c4: c9cff06f j 80001860 <_vfprintf_r+0x1d0> -800023c8: 02097793 andi a5,s2,32 -800023cc: 000d8313 mv t1,s11 -800023d0: 0c079c63 bnez a5,800024a8 <_vfprintf_r+0xe18> -800023d4: 01012683 lw a3,16(sp) -800023d8: 01097713 andi a4,s2,16 -800023dc: 00468793 addi a5,a3,4 -800023e0: 0006ab83 lw s7,0(a3) -800023e4: 960712e3 bnez a4,80001d48 <_vfprintf_r+0x6b8> -800023e8: 04097713 andi a4,s2,64 -800023ec: 6c0708e3 beqz a4,800032bc <_vfprintf_r+0x1c2c> -800023f0: 010b9b93 slli s7,s7,0x10 -800023f4: 010bdb93 srli s7,s7,0x10 -800023f8: 00000d93 li s11,0 -800023fc: 00f12823 sw a5,16(sp) -80002400: 0c40006f j 800024c4 <_vfprintf_r+0xe34> -80002404: 02097793 andi a5,s2,32 -80002408: 000d8313 mv t1,s11 -8000240c: 06079a63 bnez a5,80002480 <_vfprintf_r+0xdf0> -80002410: 01012683 lw a3,16(sp) -80002414: 01097713 andi a4,s2,16 -80002418: 00468793 addi a5,a3,4 -8000241c: 0006ab83 lw s7,0(a3) -80002420: 00070463 beqz a4,80002428 <_vfprintf_r+0xd98> -80002424: 5950106f j 800041b8 <_vfprintf_r+0x2b28> -80002428: 04097713 andi a4,s2,64 -8000242c: 6a0704e3 beqz a4,800032d4 <_vfprintf_r+0x1c44> -80002430: 010b9b93 slli s7,s7,0x10 -80002434: 00f12823 sw a5,16(sp) -80002438: 010bdb93 srli s7,s7,0x10 -8000243c: 00000d93 li s11,0 -80002440: 00090993 mv s3,s2 -80002444: 00100793 li a5,1 -80002448: dccff06f j 80001a14 <_vfprintf_r+0x384> -8000244c: 02012503 lw a0,32(sp) -80002450: 778020ef jal ra,80004bc8 <__sinit> -80002454: abcff06f j 80001710 <_vfprintf_r+0x80> -80002458: 00090993 mv s3,s2 -8000245c: 01012783 lw a5,16(sp) -80002460: 00778793 addi a5,a5,7 -80002464: ff87f793 andi a5,a5,-8 -80002468: 0047a703 lw a4,4(a5) -8000246c: 00878693 addi a3,a5,8 -80002470: 00d12823 sw a3,16(sp) -80002474: 0007ab83 lw s7,0(a5) -80002478: 00070d93 mv s11,a4 -8000247c: fc8ff06f j 80001c44 <_vfprintf_r+0x5b4> -80002480: 00090993 mv s3,s2 -80002484: 01012783 lw a5,16(sp) -80002488: 00778793 addi a5,a5,7 -8000248c: ff87f793 andi a5,a5,-8 -80002490: 00878713 addi a4,a5,8 -80002494: 0007ab83 lw s7,0(a5) -80002498: 0047ad83 lw s11,4(a5) -8000249c: 00e12823 sw a4,16(sp) -800024a0: 00100793 li a5,1 -800024a4: d70ff06f j 80001a14 <_vfprintf_r+0x384> -800024a8: 01012783 lw a5,16(sp) -800024ac: 00778793 addi a5,a5,7 -800024b0: ff87f793 andi a5,a5,-8 -800024b4: 0007ab83 lw s7,0(a5) -800024b8: 0047ad83 lw s11,4(a5) -800024bc: 00878713 addi a4,a5,8 -800024c0: 00e12823 sw a4,16(sp) -800024c4: bff97993 andi s3,s2,-1025 -800024c8: 00000793 li a5,0 -800024cc: d48ff06f j 80001a14 <_vfprintf_r+0x384> -800024d0: 00090993 mv s3,s2 -800024d4: 360d9ce3 bnez s11,8000304c <_vfprintf_r+0x19bc> -800024d8: 00900793 li a5,9 -800024dc: 3777e8e3 bltu a5,s7,8000304c <_vfprintf_r+0x19bc> -800024e0: 030b8b93 addi s7,s7,48 -800024e4: 1b7107a3 sb s7,431(sp) -800024e8: 00098913 mv s2,s3 -800024ec: 00100b13 li s6,1 -800024f0: 1af10c93 addi s9,sp,431 -800024f4: d50ff06f j 80001a44 <_vfprintf_r+0x3b4> -800024f8: 00100713 li a4,1 -800024fc: 00e79463 bne a5,a4,80002504 <_vfprintf_r+0xe74> -80002500: 5140106f j 80003a14 <_vfprintf_r+0x2384> -80002504: 00200713 li a4,2 -80002508: 00090993 mv s3,s2 -8000250c: dce792e3 bne a5,a4,800022d0 <_vfprintf_r+0xc40> -80002510: 03012683 lw a3,48(sp) -80002514: 1b010c93 addi s9,sp,432 -80002518: 00fbf793 andi a5,s7,15 -8000251c: 00f687b3 add a5,a3,a5 -80002520: 0007c783 lbu a5,0(a5) -80002524: 01cd9713 slli a4,s11,0x1c -80002528: 004bdb93 srli s7,s7,0x4 -8000252c: fffc8c93 addi s9,s9,-1 -80002530: 01776bb3 or s7,a4,s7 -80002534: 004ddd93 srli s11,s11,0x4 -80002538: 00fc8023 sb a5,0(s9) -8000253c: 01bbe7b3 or a5,s7,s11 -80002540: fc079ce3 bnez a5,80002518 <_vfprintf_r+0xe88> -80002544: 1b010793 addi a5,sp,432 -80002548: 41978b33 sub s6,a5,s9 -8000254c: 00098913 mv s2,s3 -80002550: cf4ff06f j 80001a44 <_vfprintf_r+0x3b4> -80002554: 06500693 li a3,101 -80002558: 3956d663 bge a3,s5,800028e4 <_vfprintf_r+0x1254> -8000255c: 0f012683 lw a3,240(sp) -80002560: 0a010593 addi a1,sp,160 -80002564: 0b010513 addi a0,sp,176 -80002568: 0ad12823 sw a3,176(sp) -8000256c: 0f412683 lw a3,244(sp) -80002570: 04e12223 sw a4,68(sp) -80002574: 0a012023 sw zero,160(sp) -80002578: 0ad12a23 sw a3,180(sp) -8000257c: 0f812683 lw a3,248(sp) -80002580: 0a012223 sw zero,164(sp) -80002584: 0a012423 sw zero,168(sp) -80002588: 0ad12c23 sw a3,184(sp) -8000258c: 0fc12683 lw a3,252(sp) -80002590: 0a012623 sw zero,172(sp) -80002594: 0ad12e23 sw a3,188(sp) -80002598: 6d10e0ef jal ra,80011468 <__eqtf2> -8000259c: 04412703 lw a4,68(sp) -800025a0: 5a051263 bnez a0,80002b44 <_vfprintf_r+0x14b4> -800025a4: 0e812783 lw a5,232(sp) -800025a8: 800156b7 lui a3,0x80015 -800025ac: 81068693 addi a3,a3,-2032 # 80014810 <__BSS_END__+0xffffda98> -800025b0: 00170713 addi a4,a4,1 -800025b4: 00dd2023 sw a3,0(s10) -800025b8: 00178793 addi a5,a5,1 -800025bc: 00100693 li a3,1 -800025c0: 00dd2223 sw a3,4(s10) -800025c4: 0ee12623 sw a4,236(sp) -800025c8: 0ef12423 sw a5,232(sp) -800025cc: 00700713 li a4,7 -800025d0: 008d0d13 addi s10,s10,8 -800025d4: 34f744e3 blt a4,a5,8000311c <_vfprintf_r+0x1a8c> -800025d8: 0cc12783 lw a5,204(sp) -800025dc: 01c12703 lw a4,28(sp) -800025e0: 00e7ca63 blt a5,a4,800025f4 <_vfprintf_r+0xf64> -800025e4: 00197793 andi a5,s2,1 -800025e8: 00079663 bnez a5,800025f4 <_vfprintf_r+0xf64> -800025ec: 0ec12703 lw a4,236(sp) -800025f0: 87dff06f j 80001e6c <_vfprintf_r+0x7dc> -800025f4: 03412783 lw a5,52(sp) -800025f8: 02c12683 lw a3,44(sp) -800025fc: 0ec12703 lw a4,236(sp) -80002600: 00fd2023 sw a5,0(s10) -80002604: 0e812783 lw a5,232(sp) -80002608: 00e68733 add a4,a3,a4 -8000260c: 00dd2223 sw a3,4(s10) -80002610: 00178793 addi a5,a5,1 -80002614: 0ee12623 sw a4,236(sp) -80002618: 0ef12423 sw a5,232(sp) -8000261c: 00700693 li a3,7 -80002620: 008d0d13 addi s10,s10,8 -80002624: 04f6cae3 blt a3,a5,80002e78 <_vfprintf_r+0x17e8> -80002628: 01c12783 lw a5,28(sp) -8000262c: fff78b13 addi s6,a5,-1 -80002630: 83605ee3 blez s6,80001e6c <_vfprintf_r+0x7dc> -80002634: 01000693 li a3,16 -80002638: 0e812783 lw a5,232(sp) -8000263c: 3166d0e3 bge a3,s6,8000313c <_vfprintf_r+0x1aac> -80002640: 01000b93 li s7,16 -80002644: 00700a93 li s5,7 -80002648: 00412c83 lw s9,4(sp) -8000264c: 00c0006f j 80002658 <_vfprintf_r+0xfc8> -80002650: ff0b0b13 addi s6,s6,-16 -80002654: 2f6bd4e3 bge s7,s6,8000313c <_vfprintf_r+0x1aac> -80002658: 01070713 addi a4,a4,16 -8000265c: 00178793 addi a5,a5,1 -80002660: 018d2023 sw s8,0(s10) -80002664: 017d2223 sw s7,4(s10) -80002668: 0ee12623 sw a4,236(sp) -8000266c: 0ef12423 sw a5,232(sp) -80002670: 008d0d13 addi s10,s10,8 -80002674: fcfadee3 bge s5,a5,80002650 <_vfprintf_r+0xfc0> -80002678: 0e410613 addi a2,sp,228 -8000267c: 000c8593 mv a1,s9 -80002680: 000a0513 mv a0,s4 -80002684: 4e5090ef jal ra,8000c368 <__sprint_r> -80002688: ac051a63 bnez a0,8000195c <_vfprintf_r+0x2cc> -8000268c: 0ec12703 lw a4,236(sp) -80002690: 0e812783 lw a5,232(sp) -80002694: 10c10d13 addi s10,sp,268 -80002698: fb9ff06f j 80002650 <_vfprintf_r+0xfc0> -8000269c: 41340bb3 sub s7,s0,s3 -800026a0: f9705a63 blez s7,80001e34 <_vfprintf_r+0x7a4> -800026a4: 01000613 li a2,16 -800026a8: 0e812683 lw a3,232(sp) -800026ac: 0b765463 bge a2,s7,80002754 <_vfprintf_r+0x10c4> -800026b0: 04912223 sw s1,68(sp) -800026b4: 000d0793 mv a5,s10 -800026b8: 000b8493 mv s1,s7 -800026bc: 000c8d13 mv s10,s9 -800026c0: 00098b93 mv s7,s3 -800026c4: 000b0c93 mv s9,s6 -800026c8: 00040993 mv s3,s0 -800026cc: 01000e93 li t4,16 -800026d0: 00700d93 li s11,7 -800026d4: 00412403 lw s0,4(sp) -800026d8: 00030b13 mv s6,t1 -800026dc: 00c0006f j 800026e8 <_vfprintf_r+0x1058> -800026e0: ff048493 addi s1,s1,-16 -800026e4: 049ed863 bge t4,s1,80002734 <_vfprintf_r+0x10a4> -800026e8: 01070713 addi a4,a4,16 -800026ec: 00168693 addi a3,a3,1 -800026f0: 0187a023 sw s8,0(a5) -800026f4: 01d7a223 sw t4,4(a5) -800026f8: 0ee12623 sw a4,236(sp) -800026fc: 0ed12423 sw a3,232(sp) -80002700: 00878793 addi a5,a5,8 -80002704: fcdddee3 bge s11,a3,800026e0 <_vfprintf_r+0x1050> -80002708: 0e410613 addi a2,sp,228 -8000270c: 00040593 mv a1,s0 -80002710: 000a0513 mv a0,s4 -80002714: 455090ef jal ra,8000c368 <__sprint_r> -80002718: a4051263 bnez a0,8000195c <_vfprintf_r+0x2cc> -8000271c: 01000e93 li t4,16 -80002720: ff048493 addi s1,s1,-16 -80002724: 0ec12703 lw a4,236(sp) -80002728: 0e812683 lw a3,232(sp) -8000272c: 10c10793 addi a5,sp,268 -80002730: fa9ecce3 blt t4,s1,800026e8 <_vfprintf_r+0x1058> -80002734: 00098413 mv s0,s3 -80002738: 000b8993 mv s3,s7 -8000273c: 00048b93 mv s7,s1 -80002740: 04412483 lw s1,68(sp) -80002744: 000b0313 mv t1,s6 -80002748: 000c8b13 mv s6,s9 -8000274c: 000d0c93 mv s9,s10 -80002750: 00078d13 mv s10,a5 -80002754: 01770733 add a4,a4,s7 -80002758: 00168693 addi a3,a3,1 -8000275c: 018d2023 sw s8,0(s10) -80002760: 017d2223 sw s7,4(s10) -80002764: 0ee12623 sw a4,236(sp) -80002768: 0ed12423 sw a3,232(sp) -8000276c: 00700613 li a2,7 -80002770: 008d0d13 addi s10,s10,8 -80002774: ecd65063 bge a2,a3,80001e34 <_vfprintf_r+0x7a4> -80002778: 00412583 lw a1,4(sp) -8000277c: 0e410613 addi a2,sp,228 -80002780: 000a0513 mv a0,s4 -80002784: 04612223 sw t1,68(sp) -80002788: 3e1090ef jal ra,8000c368 <__sprint_r> -8000278c: 9c051863 bnez a0,8000195c <_vfprintf_r+0x2cc> -80002790: 0ec12703 lw a4,236(sp) -80002794: 10c10d13 addi s10,sp,268 -80002798: 04412303 lw t1,68(sp) -8000279c: e98ff06f j 80001e34 <_vfprintf_r+0x7a4> -800027a0: 01000613 li a2,16 -800027a4: 0e812683 lw a3,232(sp) -800027a8: 09b65863 bge a2,s11,80002838 <_vfprintf_r+0x11a8> -800027ac: 000d0793 mv a5,s10 -800027b0: 01000813 li a6,16 -800027b4: 000c8d13 mv s10,s9 -800027b8: 00700b93 li s7,7 -800027bc: 000b0c93 mv s9,s6 -800027c0: 00098b13 mv s6,s3 -800027c4: 00040993 mv s3,s0 -800027c8: 00412403 lw s0,4(sp) -800027cc: 00c0006f j 800027d8 <_vfprintf_r+0x1148> -800027d0: ff0d8d93 addi s11,s11,-16 -800027d4: 05b85863 bge a6,s11,80002824 <_vfprintf_r+0x1194> -800027d8: 01070713 addi a4,a4,16 -800027dc: 00168693 addi a3,a3,1 -800027e0: 0187a023 sw s8,0(a5) -800027e4: 0107a223 sw a6,4(a5) -800027e8: 0ee12623 sw a4,236(sp) -800027ec: 0ed12423 sw a3,232(sp) -800027f0: 00878793 addi a5,a5,8 -800027f4: fcdbdee3 bge s7,a3,800027d0 <_vfprintf_r+0x1140> -800027f8: 0e410613 addi a2,sp,228 -800027fc: 00040593 mv a1,s0 -80002800: 000a0513 mv a0,s4 -80002804: 365090ef jal ra,8000c368 <__sprint_r> -80002808: 94051a63 bnez a0,8000195c <_vfprintf_r+0x2cc> -8000280c: 01000813 li a6,16 -80002810: ff0d8d93 addi s11,s11,-16 -80002814: 0ec12703 lw a4,236(sp) -80002818: 0e812683 lw a3,232(sp) -8000281c: 10c10793 addi a5,sp,268 -80002820: fbb84ce3 blt a6,s11,800027d8 <_vfprintf_r+0x1148> -80002824: 00098413 mv s0,s3 -80002828: 000b0993 mv s3,s6 -8000282c: 000c8b13 mv s6,s9 -80002830: 000d0c93 mv s9,s10 -80002834: 00078d13 mv s10,a5 -80002838: 01b70733 add a4,a4,s11 -8000283c: 00168693 addi a3,a3,1 -80002840: 018d2023 sw s8,0(s10) -80002844: 01bd2223 sw s11,4(s10) -80002848: 0ee12623 sw a4,236(sp) -8000284c: 0ed12423 sw a3,232(sp) -80002850: 00700613 li a2,7 -80002854: 008d0d13 addi s10,s10,8 -80002858: ded65263 bge a2,a3,80001e3c <_vfprintf_r+0x7ac> -8000285c: 00412583 lw a1,4(sp) -80002860: 0e410613 addi a2,sp,228 -80002864: 000a0513 mv a0,s4 -80002868: 301090ef jal ra,8000c368 <__sprint_r> -8000286c: 8e051863 bnez a0,8000195c <_vfprintf_r+0x2cc> -80002870: 0ec12703 lw a4,236(sp) -80002874: 10c10d13 addi s10,sp,268 -80002878: dc4ff06f j 80001e3c <_vfprintf_r+0x7ac> -8000287c: 00197593 andi a1,s2,1 -80002880: 08059263 bnez a1,80002904 <_vfprintf_r+0x1274> -80002884: 00dd2223 sw a3,4(s10) -80002888: 0fb12623 sw s11,236(sp) -8000288c: 0f612423 sw s6,232(sp) -80002890: 00700793 li a5,7 -80002894: 5b67ca63 blt a5,s6,80002e48 <_vfprintf_r+0x17b8> -80002898: 00260a93 addi s5,a2,2 -8000289c: 010d0d13 addi s10,s10,16 -800028a0: 03812683 lw a3,56(sp) -800028a4: 0d410793 addi a5,sp,212 -800028a8: 00fba023 sw a5,0(s7) -800028ac: 01b68733 add a4,a3,s11 -800028b0: 00dba223 sw a3,4(s7) -800028b4: 0ee12623 sw a4,236(sp) -800028b8: 0f512423 sw s5,232(sp) -800028bc: 00700793 li a5,7 -800028c0: db57d663 bge a5,s5,80001e6c <_vfprintf_r+0x7dc> -800028c4: 00412583 lw a1,4(sp) -800028c8: 0e410613 addi a2,sp,228 -800028cc: 000a0513 mv a0,s4 -800028d0: 299090ef jal ra,8000c368 <__sprint_r> -800028d4: 88051463 bnez a0,8000195c <_vfprintf_r+0x2cc> -800028d8: 0ec12703 lw a4,236(sp) -800028dc: 10c10d13 addi s10,sp,268 -800028e0: d8cff06f j 80001e6c <_vfprintf_r+0x7dc> -800028e4: 0e812603 lw a2,232(sp) -800028e8: 01c12783 lw a5,28(sp) -800028ec: 00100693 li a3,1 -800028f0: 019d2023 sw s9,0(s10) -800028f4: 00170d93 addi s11,a4,1 -800028f8: 00160b13 addi s6,a2,1 -800028fc: 008d0b93 addi s7,s10,8 -80002900: f6f6dee3 bge a3,a5,8000287c <_vfprintf_r+0x11ec> -80002904: 00100693 li a3,1 -80002908: 00dd2223 sw a3,4(s10) -8000290c: 0fb12623 sw s11,236(sp) -80002910: 0f612423 sw s6,232(sp) -80002914: 00700693 li a3,7 -80002918: 6366cc63 blt a3,s6,80002f50 <_vfprintf_r+0x18c0> -8000291c: 02c12783 lw a5,44(sp) -80002920: 03412703 lw a4,52(sp) -80002924: 001b0b13 addi s6,s6,1 -80002928: 00fd8db3 add s11,s11,a5 -8000292c: 00eba023 sw a4,0(s7) -80002930: 00fba223 sw a5,4(s7) -80002934: 0fb12623 sw s11,236(sp) -80002938: 0f612423 sw s6,232(sp) -8000293c: 00700693 li a3,7 -80002940: 008b8b93 addi s7,s7,8 -80002944: 6366ca63 blt a3,s6,80002f78 <_vfprintf_r+0x18e8> -80002948: 0f012683 lw a3,240(sp) -8000294c: 01c12783 lw a5,28(sp) -80002950: 001b0813 addi a6,s6,1 -80002954: 0ad12823 sw a3,176(sp) -80002958: 0f412683 lw a3,244(sp) -8000295c: 0a010593 addi a1,sp,160 -80002960: 0b010513 addi a0,sp,176 -80002964: 0ad12a23 sw a3,180(sp) -80002968: 0f812683 lw a3,248(sp) -8000296c: 00080a93 mv s5,a6 -80002970: 03012223 sw a6,36(sp) -80002974: 0ad12c23 sw a3,184(sp) -80002978: 0fc12683 lw a3,252(sp) -8000297c: 0a012023 sw zero,160(sp) -80002980: 0a012223 sw zero,164(sp) -80002984: 0ad12e23 sw a3,188(sp) -80002988: fff78693 addi a3,a5,-1 -8000298c: 00d12c23 sw a3,24(sp) -80002990: 0a012423 sw zero,168(sp) -80002994: 0a012623 sw zero,172(sp) -80002998: 2d10e0ef jal ra,80011468 <__eqtf2> -8000299c: 008b8d13 addi s10,s7,8 -800029a0: 01812683 lw a3,24(sp) -800029a4: 02412803 lw a6,36(sp) -800029a8: 30050e63 beqz a0,80002cc4 <_vfprintf_r+0x1634> -800029ac: 001c8793 addi a5,s9,1 -800029b0: 00dd8db3 add s11,s11,a3 -800029b4: 00fba023 sw a5,0(s7) -800029b8: 00dba223 sw a3,4(s7) -800029bc: 0fb12623 sw s11,236(sp) -800029c0: 0f512423 sw s5,232(sp) -800029c4: 00700793 li a5,7 -800029c8: 4957c063 blt a5,s5,80002e48 <_vfprintf_r+0x17b8> -800029cc: 010b8793 addi a5,s7,16 -800029d0: 002b0a93 addi s5,s6,2 -800029d4: 000d0b93 mv s7,s10 -800029d8: 00078d13 mv s10,a5 -800029dc: ec5ff06f j 800028a0 <_vfprintf_r+0x1210> -800029e0: 00090993 mv s3,s2 -800029e4: 8ddff06f j 800022c0 <_vfprintf_r+0xc30> -800029e8: 800147b7 lui a5,0x80014 -800029ec: 01000613 li a2,16 -800029f0: 0e812683 lw a3,232(sp) -800029f4: 7b078d93 addi s11,a5,1968 # 800147b0 <__BSS_END__+0xffffda38> -800029f8: 0d065463 bge a2,a6,80002ac0 <_vfprintf_r+0x1430> -800029fc: 04912623 sw s1,76(sp) -80002a00: 05212823 sw s2,80(sp) -80002a04: 000d0793 mv a5,s10 -80002a08: 000d8913 mv s2,s11 -80002a0c: 000b0d13 mv s10,s6 -80002a10: 000c8d93 mv s11,s9 -80002a14: 01000f13 li t5,16 -80002a18: 00098c93 mv s9,s3 -80002a1c: 00700393 li t2,7 -80002a20: 00040993 mv s3,s0 -80002a24: 04512223 sw t0,68(sp) -80002a28: 00030b13 mv s6,t1 -80002a2c: 00412483 lw s1,4(sp) -80002a30: 00080413 mv s0,a6 -80002a34: 00c0006f j 80002a40 <_vfprintf_r+0x13b0> -80002a38: ff040413 addi s0,s0,-16 -80002a3c: 048f5c63 bge t5,s0,80002a94 <_vfprintf_r+0x1404> -80002a40: 01070713 addi a4,a4,16 -80002a44: 00168693 addi a3,a3,1 -80002a48: 0127a023 sw s2,0(a5) -80002a4c: 01e7a223 sw t5,4(a5) -80002a50: 0ee12623 sw a4,236(sp) -80002a54: 0ed12423 sw a3,232(sp) -80002a58: 00878793 addi a5,a5,8 -80002a5c: fcd3dee3 bge t2,a3,80002a38 <_vfprintf_r+0x13a8> -80002a60: 0e410613 addi a2,sp,228 -80002a64: 00048593 mv a1,s1 -80002a68: 000a0513 mv a0,s4 -80002a6c: 0fd090ef jal ra,8000c368 <__sprint_r> -80002a70: 00050463 beqz a0,80002a78 <_vfprintf_r+0x13e8> -80002a74: ee9fe06f j 8000195c <_vfprintf_r+0x2cc> -80002a78: 01000f13 li t5,16 -80002a7c: ff040413 addi s0,s0,-16 -80002a80: 0ec12703 lw a4,236(sp) -80002a84: 0e812683 lw a3,232(sp) -80002a88: 10c10793 addi a5,sp,268 -80002a8c: 00700393 li t2,7 -80002a90: fa8f48e3 blt t5,s0,80002a40 <_vfprintf_r+0x13b0> -80002a94: 00040813 mv a6,s0 -80002a98: 04412283 lw t0,68(sp) -80002a9c: 00098413 mv s0,s3 -80002aa0: 04c12483 lw s1,76(sp) -80002aa4: 000c8993 mv s3,s9 -80002aa8: 000d8c93 mv s9,s11 -80002aac: 00090d93 mv s11,s2 -80002ab0: 05012903 lw s2,80(sp) -80002ab4: 000b0313 mv t1,s6 -80002ab8: 000d0b13 mv s6,s10 -80002abc: 00078d13 mv s10,a5 -80002ac0: 01070733 add a4,a4,a6 -80002ac4: 00168693 addi a3,a3,1 -80002ac8: 01bd2023 sw s11,0(s10) -80002acc: 010d2223 sw a6,4(s10) -80002ad0: 0ee12623 sw a4,236(sp) -80002ad4: 0ed12423 sw a3,232(sp) -80002ad8: 00700613 li a2,7 -80002adc: 008d0d13 addi s10,s10,8 -80002ae0: aed65063 bge a2,a3,80001dc0 <_vfprintf_r+0x730> -80002ae4: 00412583 lw a1,4(sp) -80002ae8: 0e410613 addi a2,sp,228 -80002aec: 000a0513 mv a0,s4 -80002af0: 04612623 sw t1,76(sp) -80002af4: 04512223 sw t0,68(sp) -80002af8: 071090ef jal ra,8000c368 <__sprint_r> -80002afc: 00050463 beqz a0,80002b04 <_vfprintf_r+0x1474> -80002b00: e5dfe06f j 8000195c <_vfprintf_r+0x2cc> -80002b04: 0ec12703 lw a4,236(sp) -80002b08: 10c10d13 addi s10,sp,268 -80002b0c: 04c12303 lw t1,76(sp) -80002b10: 04412283 lw t0,68(sp) -80002b14: aacff06f j 80001dc0 <_vfprintf_r+0x730> -80002b18: 00412583 lw a1,4(sp) -80002b1c: 0e410613 addi a2,sp,228 -80002b20: 000a0513 mv a0,s4 -80002b24: 04612223 sw t1,68(sp) -80002b28: 041090ef jal ra,8000c368 <__sprint_r> -80002b2c: 00050463 beqz a0,80002b34 <_vfprintf_r+0x14a4> -80002b30: e2dfe06f j 8000195c <_vfprintf_r+0x2cc> -80002b34: 0ec12703 lw a4,236(sp) -80002b38: 10c10d13 addi s10,sp,268 -80002b3c: 04412303 lw t1,68(sp) -80002b40: aecff06f j 80001e2c <_vfprintf_r+0x79c> -80002b44: 0cc12603 lw a2,204(sp) -80002b48: 44c05c63 blez a2,80002fa0 <_vfprintf_r+0x1910> -80002b4c: 01812783 lw a5,24(sp) -80002b50: 01c12683 lw a3,28(sp) -80002b54: 00078b13 mv s6,a5 -80002b58: 2af6cc63 blt a3,a5,80002e10 <_vfprintf_r+0x1780> -80002b5c: 03605663 blez s6,80002b88 <_vfprintf_r+0x14f8> -80002b60: 0e812683 lw a3,232(sp) -80002b64: 01670733 add a4,a4,s6 -80002b68: 019d2023 sw s9,0(s10) -80002b6c: 00168693 addi a3,a3,1 -80002b70: 016d2223 sw s6,4(s10) -80002b74: 0ee12623 sw a4,236(sp) -80002b78: 0ed12423 sw a3,232(sp) -80002b7c: 00700613 li a2,7 -80002b80: 008d0d13 addi s10,s10,8 -80002b84: 1cd64ee3 blt a2,a3,80003560 <_vfprintf_r+0x1ed0> -80002b88: fffb4693 not a3,s6 -80002b8c: 01812783 lw a5,24(sp) -80002b90: 41f6d693 srai a3,a3,0x1f -80002b94: 00db7b33 and s6,s6,a3 -80002b98: 41678b33 sub s6,a5,s6 -80002b9c: 35604063 bgtz s6,80002edc <_vfprintf_r+0x184c> -80002ba0: 01812783 lw a5,24(sp) -80002ba4: 40097693 andi a3,s2,1024 -80002ba8: 00fc8ab3 add s5,s9,a5 -80002bac: 7a069c63 bnez a3,80003364 <_vfprintf_r+0x1cd4> -80002bb0: 0cc12b03 lw s6,204(sp) -80002bb4: 01c12783 lw a5,28(sp) -80002bb8: 00fb4663 blt s6,a5,80002bc4 <_vfprintf_r+0x1534> -80002bbc: 00197693 andi a3,s2,1 -80002bc0: 1c0686e3 beqz a3,8000358c <_vfprintf_r+0x1efc> -80002bc4: 03412683 lw a3,52(sp) -80002bc8: 02c12783 lw a5,44(sp) -80002bcc: 00700613 li a2,7 -80002bd0: 00dd2023 sw a3,0(s10) -80002bd4: 0e812683 lw a3,232(sp) -80002bd8: 00f70733 add a4,a4,a5 -80002bdc: 00fd2223 sw a5,4(s10) -80002be0: 00168693 addi a3,a3,1 -80002be4: 0ee12623 sw a4,236(sp) -80002be8: 0ed12423 sw a3,232(sp) -80002bec: 008d0d13 addi s10,s10,8 -80002bf0: 00d65463 bge a2,a3,80002bf8 <_vfprintf_r+0x1568> -80002bf4: 0d40106f j 80003cc8 <_vfprintf_r+0x2638> -80002bf8: 01c12683 lw a3,28(sp) -80002bfc: 00dc87b3 add a5,s9,a3 -80002c00: 41668b33 sub s6,a3,s6 -80002c04: 415787b3 sub a5,a5,s5 -80002c08: 000b0b93 mv s7,s6 -80002c0c: 0167d463 bge a5,s6,80002c14 <_vfprintf_r+0x1584> -80002c10: 00078b93 mv s7,a5 -80002c14: 03705863 blez s7,80002c44 <_vfprintf_r+0x15b4> -80002c18: 0e812783 lw a5,232(sp) -80002c1c: 01770733 add a4,a4,s7 -80002c20: 015d2023 sw s5,0(s10) -80002c24: 00178793 addi a5,a5,1 -80002c28: 017d2223 sw s7,4(s10) -80002c2c: 0ee12623 sw a4,236(sp) -80002c30: 0ef12423 sw a5,232(sp) -80002c34: 00700693 li a3,7 -80002c38: 008d0d13 addi s10,s10,8 -80002c3c: 00f6d463 bge a3,a5,80002c44 <_vfprintf_r+0x15b4> -80002c40: 1480106f j 80003d88 <_vfprintf_r+0x26f8> -80002c44: fffbc793 not a5,s7 -80002c48: 41f7d793 srai a5,a5,0x1f -80002c4c: 00fbfbb3 and s7,s7,a5 -80002c50: 417b0b33 sub s6,s6,s7 -80002c54: a1605c63 blez s6,80001e6c <_vfprintf_r+0x7dc> -80002c58: 01000693 li a3,16 -80002c5c: 0e812783 lw a5,232(sp) -80002c60: 4d66de63 bge a3,s6,8000313c <_vfprintf_r+0x1aac> -80002c64: 01000b93 li s7,16 -80002c68: 00700a93 li s5,7 -80002c6c: 00412c83 lw s9,4(sp) -80002c70: 00c0006f j 80002c7c <_vfprintf_r+0x15ec> -80002c74: ff0b0b13 addi s6,s6,-16 -80002c78: 4d6bd263 bge s7,s6,8000313c <_vfprintf_r+0x1aac> -80002c7c: 01070713 addi a4,a4,16 -80002c80: 00178793 addi a5,a5,1 -80002c84: 018d2023 sw s8,0(s10) -80002c88: 017d2223 sw s7,4(s10) -80002c8c: 0ee12623 sw a4,236(sp) -80002c90: 0ef12423 sw a5,232(sp) -80002c94: 008d0d13 addi s10,s10,8 -80002c98: fcfadee3 bge s5,a5,80002c74 <_vfprintf_r+0x15e4> -80002c9c: 0e410613 addi a2,sp,228 -80002ca0: 000c8593 mv a1,s9 -80002ca4: 000a0513 mv a0,s4 -80002ca8: 6c0090ef jal ra,8000c368 <__sprint_r> -80002cac: 00050463 beqz a0,80002cb4 <_vfprintf_r+0x1624> -80002cb0: cadfe06f j 8000195c <_vfprintf_r+0x2cc> -80002cb4: 0ec12703 lw a4,236(sp) -80002cb8: 0e812783 lw a5,232(sp) -80002cbc: 10c10d13 addi s10,sp,268 -80002cc0: fb5ff06f j 80002c74 <_vfprintf_r+0x15e4> -80002cc4: bcd05ee3 blez a3,800028a0 <_vfprintf_r+0x1210> -80002cc8: 01000793 li a5,16 -80002ccc: 00d7c463 blt a5,a3,80002cd4 <_vfprintf_r+0x1644> -80002cd0: 4b40106f j 80004184 <_vfprintf_r+0x2af4> -80002cd4: 00812c23 sw s0,24(sp) -80002cd8: 01000c93 li s9,16 -80002cdc: 00700a93 li s5,7 -80002ce0: 00068413 mv s0,a3 -80002ce4: 00412d03 lw s10,4(sp) -80002ce8: 00080b13 mv s6,a6 -80002cec: 0100006f j 80002cfc <_vfprintf_r+0x166c> -80002cf0: ff040413 addi s0,s0,-16 -80002cf4: 128cd463 bge s9,s0,80002e1c <_vfprintf_r+0x178c> -80002cf8: 001b0b13 addi s6,s6,1 -80002cfc: 010d8d93 addi s11,s11,16 -80002d00: 018ba023 sw s8,0(s7) -80002d04: 019ba223 sw s9,4(s7) -80002d08: 0fb12623 sw s11,236(sp) -80002d0c: 0f612423 sw s6,232(sp) -80002d10: 008b8b93 addi s7,s7,8 -80002d14: fd6adee3 bge s5,s6,80002cf0 <_vfprintf_r+0x1660> -80002d18: 0e410613 addi a2,sp,228 -80002d1c: 000d0593 mv a1,s10 -80002d20: 000a0513 mv a0,s4 -80002d24: 644090ef jal ra,8000c368 <__sprint_r> -80002d28: 00050463 beqz a0,80002d30 <_vfprintf_r+0x16a0> -80002d2c: c31fe06f j 8000195c <_vfprintf_r+0x2cc> -80002d30: 0ec12d83 lw s11,236(sp) -80002d34: 0e812b03 lw s6,232(sp) -80002d38: 10c10b93 addi s7,sp,268 -80002d3c: fb5ff06f j 80002cf0 <_vfprintf_r+0x1660> -80002d40: 03000793 li a5,48 -80002d44: 1af107a3 sb a5,431(sp) -80002d48: 1af10c93 addi s9,sp,431 -80002d4c: cf9fe06f j 80001a44 <_vfprintf_r+0x3b4> -80002d50: 20097793 andi a5,s2,512 -80002d54: 060798e3 bnez a5,800035c4 <_vfprintf_r+0x1f34> -80002d58: 00000d93 li s11,0 -80002d5c: c9dfe06f j 800019f8 <_vfprintf_r+0x368> -80002d60: 04012783 lw a5,64(sp) -80002d64: 0004ce03 lbu t3,0(s1) -80002d68: 00079463 bnez a5,80002d70 <_vfprintf_r+0x16e0> -80002d6c: af5fe06f j 80001860 <_vfprintf_r+0x1d0> -80002d70: 0007c783 lbu a5,0(a5) -80002d74: 00079463 bnez a5,80002d7c <_vfprintf_r+0x16ec> -80002d78: ae9fe06f j 80001860 <_vfprintf_r+0x1d0> -80002d7c: 40096913 ori s2,s2,1024 -80002d80: ae1fe06f j 80001860 <_vfprintf_r+0x1d0> -80002d84: 01012783 lw a5,16(sp) -80002d88: 0b010513 addi a0,sp,176 -80002d8c: 01b12a23 sw s11,20(sp) -80002d90: 00778793 addi a5,a5,7 -80002d94: ff87f793 andi a5,a5,-8 -80002d98: 0007a583 lw a1,0(a5) -80002d9c: 0047a603 lw a2,4(a5) -80002da0: 00878793 addi a5,a5,8 -80002da4: 00f12823 sw a5,16(sp) -80002da8: 214110ef jal ra,80013fbc <__extenddftf2> -80002dac: 0b012703 lw a4,176(sp) -80002db0: 01412303 lw t1,20(sp) -80002db4: 0ee12823 sw a4,240(sp) -80002db8: 0b412703 lw a4,180(sp) -80002dbc: 0ee12a23 sw a4,244(sp) -80002dc0: 0b812703 lw a4,184(sp) -80002dc4: 0ee12c23 sw a4,248(sp) -80002dc8: 0bc12703 lw a4,188(sp) -80002dcc: 0ee12e23 sw a4,252(sp) -80002dd0: a08ff06f j 80001fd8 <_vfprintf_r+0x948> -80002dd4: 00812603 lw a2,8(sp) -80002dd8: 0006a783 lw a5,0(a3) -80002ddc: 00e12823 sw a4,16(sp) -80002de0: 41f65693 srai a3,a2,0x1f -80002de4: 00c7a023 sw a2,0(a5) -80002de8: 00d7a223 sw a3,4(a5) -80002dec: 00048c93 mv s9,s1 -80002df0: dbdfe06f j 80001bac <_vfprintf_r+0x51c> -80002df4: 03000793 li a5,48 -80002df8: 00296913 ori s2,s2,2 -80002dfc: 0cf10423 sb a5,200(sp) -80002e00: 0d5104a3 sb s5,201(sp) -80002e04: bff97993 andi s3,s2,-1025 -80002e08: 00200793 li a5,2 -80002e0c: c09fe06f j 80001a14 <_vfprintf_r+0x384> -80002e10: 00068b13 mv s6,a3 -80002e14: d56046e3 bgtz s6,80002b60 <_vfprintf_r+0x14d0> -80002e18: d71ff06f j 80002b88 <_vfprintf_r+0x14f8> -80002e1c: 00040693 mv a3,s0 -80002e20: 01812403 lw s0,24(sp) -80002e24: 001b0a93 addi s5,s6,1 -80002e28: 008b8793 addi a5,s7,8 -80002e2c: 00dd8db3 add s11,s11,a3 -80002e30: 00dba223 sw a3,4(s7) -80002e34: 018ba023 sw s8,0(s7) -80002e38: 0fb12623 sw s11,236(sp) -80002e3c: 0f512423 sw s5,232(sp) -80002e40: 00700693 li a3,7 -80002e44: 6d56dc63 bge a3,s5,8000351c <_vfprintf_r+0x1e8c> -80002e48: 00412583 lw a1,4(sp) -80002e4c: 0e410613 addi a2,sp,228 -80002e50: 000a0513 mv a0,s4 -80002e54: 514090ef jal ra,8000c368 <__sprint_r> -80002e58: 00050463 beqz a0,80002e60 <_vfprintf_r+0x17d0> -80002e5c: b01fe06f j 8000195c <_vfprintf_r+0x2cc> -80002e60: 0e812603 lw a2,232(sp) -80002e64: 0ec12d83 lw s11,236(sp) -80002e68: 11410d13 addi s10,sp,276 -80002e6c: 00160a93 addi s5,a2,1 -80002e70: 10c10b93 addi s7,sp,268 -80002e74: a2dff06f j 800028a0 <_vfprintf_r+0x1210> -80002e78: 00412583 lw a1,4(sp) -80002e7c: 0e410613 addi a2,sp,228 -80002e80: 000a0513 mv a0,s4 -80002e84: 4e4090ef jal ra,8000c368 <__sprint_r> -80002e88: 00050463 beqz a0,80002e90 <_vfprintf_r+0x1800> -80002e8c: ad1fe06f j 8000195c <_vfprintf_r+0x2cc> -80002e90: 0ec12703 lw a4,236(sp) -80002e94: 10c10d13 addi s10,sp,268 -80002e98: f90ff06f j 80002628 <_vfprintf_r+0xf98> -80002e9c: 0014ce03 lbu t3,1(s1) -80002ea0: 02096913 ori s2,s2,32 -80002ea4: 00148493 addi s1,s1,1 -80002ea8: 9b9fe06f j 80001860 <_vfprintf_r+0x1d0> -80002eac: 0014ce03 lbu t3,1(s1) -80002eb0: 20096913 ori s2,s2,512 -80002eb4: 00148493 addi s1,s1,1 -80002eb8: 9a9fe06f j 80001860 <_vfprintf_r+0x1d0> -80002ebc: 00600793 li a5,6 -80002ec0: 000d8b13 mv s6,s11 -80002ec4: 6db7e063 bltu a5,s11,80003584 <_vfprintf_r+0x1ef4> -80002ec8: 800157b7 lui a5,0x80015 -80002ecc: 000b0993 mv s3,s6 -80002ed0: 01712823 sw s7,16(sp) -80002ed4: 80878c93 addi s9,a5,-2040 # 80014808 <__BSS_END__+0xffffda90> -80002ed8: eb5fe06f j 80001d8c <_vfprintf_r+0x6fc> -80002edc: 01000613 li a2,16 -80002ee0: 0e812683 lw a3,232(sp) -80002ee4: 43665c63 bge a2,s6,8000331c <_vfprintf_r+0x1c8c> -80002ee8: 01000d93 li s11,16 -80002eec: 00700a93 li s5,7 -80002ef0: 00412b83 lw s7,4(sp) -80002ef4: 00c0006f j 80002f00 <_vfprintf_r+0x1870> -80002ef8: ff0b0b13 addi s6,s6,-16 -80002efc: 436dd063 bge s11,s6,8000331c <_vfprintf_r+0x1c8c> -80002f00: 01070713 addi a4,a4,16 -80002f04: 00168693 addi a3,a3,1 -80002f08: 018d2023 sw s8,0(s10) -80002f0c: 01bd2223 sw s11,4(s10) -80002f10: 0ee12623 sw a4,236(sp) -80002f14: 0ed12423 sw a3,232(sp) -80002f18: 008d0d13 addi s10,s10,8 -80002f1c: fcdadee3 bge s5,a3,80002ef8 <_vfprintf_r+0x1868> -80002f20: 0e410613 addi a2,sp,228 -80002f24: 000b8593 mv a1,s7 -80002f28: 000a0513 mv a0,s4 -80002f2c: 43c090ef jal ra,8000c368 <__sprint_r> -80002f30: 00050463 beqz a0,80002f38 <_vfprintf_r+0x18a8> -80002f34: a29fe06f j 8000195c <_vfprintf_r+0x2cc> -80002f38: 0ec12703 lw a4,236(sp) -80002f3c: 0e812683 lw a3,232(sp) -80002f40: 10c10d13 addi s10,sp,268 -80002f44: fb5ff06f j 80002ef8 <_vfprintf_r+0x1868> -80002f48: 000c8913 mv s2,s9 -80002f4c: 8edfe06f j 80001838 <_vfprintf_r+0x1a8> -80002f50: 00412583 lw a1,4(sp) -80002f54: 0e410613 addi a2,sp,228 -80002f58: 000a0513 mv a0,s4 -80002f5c: 40c090ef jal ra,8000c368 <__sprint_r> -80002f60: 00050463 beqz a0,80002f68 <_vfprintf_r+0x18d8> -80002f64: 9f9fe06f j 8000195c <_vfprintf_r+0x2cc> -80002f68: 0ec12d83 lw s11,236(sp) -80002f6c: 0e812b03 lw s6,232(sp) -80002f70: 10c10b93 addi s7,sp,268 -80002f74: 9a9ff06f j 8000291c <_vfprintf_r+0x128c> -80002f78: 00412583 lw a1,4(sp) -80002f7c: 0e410613 addi a2,sp,228 -80002f80: 000a0513 mv a0,s4 -80002f84: 3e4090ef jal ra,8000c368 <__sprint_r> -80002f88: 00050463 beqz a0,80002f90 <_vfprintf_r+0x1900> -80002f8c: 9d1fe06f j 8000195c <_vfprintf_r+0x2cc> -80002f90: 0ec12d83 lw s11,236(sp) -80002f94: 0e812b03 lw s6,232(sp) -80002f98: 10c10b93 addi s7,sp,268 -80002f9c: 9adff06f j 80002948 <_vfprintf_r+0x12b8> -80002fa0: 0e812683 lw a3,232(sp) -80002fa4: 800155b7 lui a1,0x80015 -80002fa8: 81058593 addi a1,a1,-2032 # 80014810 <__BSS_END__+0xffffda98> -80002fac: 00bd2023 sw a1,0(s10) -80002fb0: 00170713 addi a4,a4,1 -80002fb4: 00100593 li a1,1 -80002fb8: 00168693 addi a3,a3,1 -80002fbc: 00bd2223 sw a1,4(s10) -80002fc0: 0ee12623 sw a4,236(sp) -80002fc4: 0ed12423 sw a3,232(sp) -80002fc8: 00700593 li a1,7 -80002fcc: 008d0d13 addi s10,s10,8 -80002fd0: 54d5ce63 blt a1,a3,8000352c <_vfprintf_r+0x1e9c> -80002fd4: 22061263 bnez a2,800031f8 <_vfprintf_r+0x1b68> -80002fd8: 01c12783 lw a5,28(sp) -80002fdc: 00197693 andi a3,s2,1 -80002fe0: 00f6e6b3 or a3,a3,a5 -80002fe4: 00069463 bnez a3,80002fec <_vfprintf_r+0x195c> -80002fe8: e85fe06f j 80001e6c <_vfprintf_r+0x7dc> -80002fec: 03412683 lw a3,52(sp) -80002ff0: 02c12783 lw a5,44(sp) -80002ff4: 00700613 li a2,7 -80002ff8: 00dd2023 sw a3,0(s10) -80002ffc: 0e812683 lw a3,232(sp) -80003000: 00f70733 add a4,a4,a5 -80003004: 00fd2223 sw a5,4(s10) -80003008: 00168693 addi a3,a3,1 -8000300c: 0ee12623 sw a4,236(sp) -80003010: 0ed12423 sw a3,232(sp) -80003014: 008d0893 addi a7,s10,8 -80003018: 5ed64e63 blt a2,a3,80003614 <_vfprintf_r+0x1f84> -8000301c: 01c12783 lw a5,28(sp) -80003020: 00168693 addi a3,a3,1 -80003024: 0198a023 sw s9,0(a7) -80003028: 00e78733 add a4,a5,a4 -8000302c: 00f8a223 sw a5,4(a7) -80003030: 0ee12623 sw a4,236(sp) -80003034: 0ed12423 sw a3,232(sp) -80003038: 00700793 li a5,7 -8000303c: 00888d13 addi s10,a7,8 -80003040: 00d7c463 blt a5,a3,80003048 <_vfprintf_r+0x19b8> -80003044: e29fe06f j 80001e6c <_vfprintf_r+0x7dc> -80003048: 87dff06f j 800028c4 <_vfprintf_r+0x1234> -8000304c: 1b010c93 addi s9,sp,432 -80003050: 00000793 li a5,0 -80003054: 4009f913 andi s2,s3,1024 -80003058: 00912a23 sw s1,20(sp) -8000305c: 01312c23 sw s3,24(sp) -80003060: 0ff00b13 li s6,255 -80003064: 000c8993 mv s3,s9 -80003068: 02612223 sw t1,36(sp) -8000306c: 000a0c93 mv s9,s4 -80003070: 04012483 lw s1,64(sp) -80003074: 000d8a13 mv s4,s11 -80003078: 000d0d93 mv s11,s10 -8000307c: 00040d13 mv s10,s0 -80003080: 00078413 mv s0,a5 -80003084: 0240006f j 800030a8 <_vfprintf_r+0x1a18> -80003088: 00a00613 li a2,10 -8000308c: 00000693 li a3,0 -80003090: 000b8513 mv a0,s7 -80003094: 000a0593 mv a1,s4 -80003098: 70d0c0ef jal ra,8000ffa4 <__udivdi3> -8000309c: 2c0a00e3 beqz s4,80003b5c <_vfprintf_r+0x24cc> -800030a0: 00050b93 mv s7,a0 -800030a4: 00058a13 mv s4,a1 -800030a8: 00a00613 li a2,10 -800030ac: 00000693 li a3,0 -800030b0: 000b8513 mv a0,s7 -800030b4: 000a0593 mv a1,s4 -800030b8: 3200d0ef jal ra,800103d8 <__umoddi3> -800030bc: 03050513 addi a0,a0,48 -800030c0: fea98fa3 sb a0,-1(s3) -800030c4: 00140413 addi s0,s0,1 -800030c8: fff98993 addi s3,s3,-1 -800030cc: fa090ee3 beqz s2,80003088 <_vfprintf_r+0x19f8> -800030d0: 0004c683 lbu a3,0(s1) -800030d4: fad41ae3 bne s0,a3,80003088 <_vfprintf_r+0x19f8> -800030d8: fb6408e3 beq s0,s6,80003088 <_vfprintf_r+0x19f8> -800030dc: 240a10e3 bnez s4,80003b1c <_vfprintf_r+0x248c> -800030e0: 00900793 li a5,9 -800030e4: 2377ece3 bltu a5,s7,80003b1c <_vfprintf_r+0x248c> -800030e8: 000c8a13 mv s4,s9 -800030ec: 00098c93 mv s9,s3 -800030f0: 01812983 lw s3,24(sp) -800030f4: 1b010793 addi a5,sp,432 -800030f8: 00812e23 sw s0,28(sp) -800030fc: 04912023 sw s1,64(sp) -80003100: 000d0413 mv s0,s10 -80003104: 02412303 lw t1,36(sp) -80003108: 01412483 lw s1,20(sp) -8000310c: 000d8d13 mv s10,s11 -80003110: 41978b33 sub s6,a5,s9 -80003114: 00098913 mv s2,s3 -80003118: 92dfe06f j 80001a44 <_vfprintf_r+0x3b4> -8000311c: 00412583 lw a1,4(sp) -80003120: 0e410613 addi a2,sp,228 -80003124: 000a0513 mv a0,s4 -80003128: 240090ef jal ra,8000c368 <__sprint_r> -8000312c: 00050463 beqz a0,80003134 <_vfprintf_r+0x1aa4> -80003130: 82dfe06f j 8000195c <_vfprintf_r+0x2cc> -80003134: 10c10d13 addi s10,sp,268 -80003138: ca0ff06f j 800025d8 <_vfprintf_r+0xf48> -8000313c: 01670733 add a4,a4,s6 -80003140: 00178793 addi a5,a5,1 -80003144: 018d2023 sw s8,0(s10) -80003148: d0dfe06f j 80001e54 <_vfprintf_r+0x7c4> -8000314c: 0f012783 lw a5,240(sp) -80003150: 0a010593 addi a1,sp,160 -80003154: 0b010513 addi a0,sp,176 -80003158: 0af12823 sw a5,176(sp) -8000315c: 0f412783 lw a5,244(sp) -80003160: 0a012023 sw zero,160(sp) -80003164: 0a012223 sw zero,164(sp) -80003168: 0af12a23 sw a5,180(sp) -8000316c: 0f812783 lw a5,248(sp) -80003170: 0a012423 sw zero,168(sp) -80003174: 0a012623 sw zero,172(sp) -80003178: 0af12c23 sw a5,184(sp) -8000317c: 0fc12783 lw a5,252(sp) -80003180: 0af12e23 sw a5,188(sp) -80003184: 4f40e0ef jal ra,80011678 <__letf2> -80003188: 1e0540e3 bltz a0,80003b68 <_vfprintf_r+0x24d8> -8000318c: 0c714703 lbu a4,199(sp) -80003190: 04700793 li a5,71 -80003194: 3d57d063 bge a5,s5,80003554 <_vfprintf_r+0x1ec4> -80003198: 800147b7 lui a5,0x80014 -8000319c: 7d478c93 addi s9,a5,2004 # 800147d4 <__BSS_END__+0xffffda5c> -800031a0: 00012a23 sw zero,20(sp) -800031a4: 02012423 sw zero,40(sp) -800031a8: 02012223 sw zero,36(sp) -800031ac: 00012c23 sw zero,24(sp) -800031b0: f7f97913 andi s2,s2,-129 -800031b4: 00300993 li s3,3 -800031b8: 00300b13 li s6,3 -800031bc: 00000313 li t1,0 -800031c0: 00070463 beqz a4,800031c8 <_vfprintf_r+0x1b38> -800031c4: 8a5fe06f j 80001a68 <_vfprintf_r+0x3d8> -800031c8: bd9fe06f j 80001da0 <_vfprintf_r+0x710> -800031cc: 01012783 lw a5,16(sp) -800031d0: 00048c93 mv s9,s1 -800031d4: 0007a783 lw a5,0(a5) -800031d8: 00e12823 sw a4,16(sp) -800031dc: 00812703 lw a4,8(sp) -800031e0: 00e7a023 sw a4,0(a5) -800031e4: 9c9fe06f j 80001bac <_vfprintf_r+0x51c> -800031e8: 000c8513 mv a0,s9 -800031ec: 430060ef jal ra,8000961c -800031f0: 00050b13 mv s6,a0 -800031f4: b0dfe06f j 80001d00 <_vfprintf_r+0x670> -800031f8: 03412683 lw a3,52(sp) -800031fc: 02c12783 lw a5,44(sp) -80003200: 00700593 li a1,7 -80003204: 00dd2023 sw a3,0(s10) -80003208: 0e812683 lw a3,232(sp) -8000320c: 00f70733 add a4,a4,a5 -80003210: 00fd2223 sw a5,4(s10) -80003214: 00168693 addi a3,a3,1 -80003218: 0ee12623 sw a4,236(sp) -8000321c: 0ed12423 sw a3,232(sp) -80003220: 008d0893 addi a7,s10,8 -80003224: 3ed5c863 blt a1,a3,80003614 <_vfprintf_r+0x1f84> -80003228: de065ae3 bgez a2,8000301c <_vfprintf_r+0x198c> -8000322c: ff000593 li a1,-16 -80003230: 40c00b33 neg s6,a2 -80003234: 3ab654e3 bge a2,a1,80003ddc <_vfprintf_r+0x274c> -80003238: 01000b93 li s7,16 -8000323c: 00700a93 li s5,7 -80003240: 00412d03 lw s10,4(sp) -80003244: 00c0006f j 80003250 <_vfprintf_r+0x1bc0> -80003248: ff0b0b13 addi s6,s6,-16 -8000324c: 396bd8e3 bge s7,s6,80003ddc <_vfprintf_r+0x274c> -80003250: 01070713 addi a4,a4,16 -80003254: 00168693 addi a3,a3,1 -80003258: 0188a023 sw s8,0(a7) -8000325c: 0178a223 sw s7,4(a7) -80003260: 0ee12623 sw a4,236(sp) -80003264: 0ed12423 sw a3,232(sp) -80003268: 00888893 addi a7,a7,8 -8000326c: fcdadee3 bge s5,a3,80003248 <_vfprintf_r+0x1bb8> -80003270: 0e410613 addi a2,sp,228 -80003274: 000d0593 mv a1,s10 -80003278: 000a0513 mv a0,s4 -8000327c: 0ec090ef jal ra,8000c368 <__sprint_r> -80003280: 00050463 beqz a0,80003288 <_vfprintf_r+0x1bf8> -80003284: ed8fe06f j 8000195c <_vfprintf_r+0x2cc> -80003288: 0ec12703 lw a4,236(sp) -8000328c: 0e812683 lw a3,232(sp) -80003290: 10c10893 addi a7,sp,268 -80003294: fb5ff06f j 80003248 <_vfprintf_r+0x1bb8> -80003298: 20097713 andi a4,s2,512 -8000329c: 34070a63 beqz a4,800035f0 <_vfprintf_r+0x1f60> -800032a0: 01012703 lw a4,16(sp) -800032a4: 00090993 mv s3,s2 -800032a8: 00f12823 sw a5,16(sp) -800032ac: 00070b83 lb s7,0(a4) -800032b0: 41fbdd93 srai s11,s7,0x1f -800032b4: 000d8713 mv a4,s11 -800032b8: 98dfe06f j 80001c44 <_vfprintf_r+0x5b4> -800032bc: 20097713 andi a4,s2,512 -800032c0: 32070263 beqz a4,800035e4 <_vfprintf_r+0x1f54> -800032c4: 0ffbfb93 andi s7,s7,255 -800032c8: 00000d93 li s11,0 -800032cc: 00f12823 sw a5,16(sp) -800032d0: 9f4ff06f j 800024c4 <_vfprintf_r+0xe34> -800032d4: 20097713 andi a4,s2,512 -800032d8: 2e070c63 beqz a4,800035d0 <_vfprintf_r+0x1f40> -800032dc: 00f12823 sw a5,16(sp) -800032e0: 0ffbfb93 andi s7,s7,255 -800032e4: 00000d93 li s11,0 -800032e8: 00090993 mv s3,s2 -800032ec: 00100793 li a5,1 -800032f0: f24fe06f j 80001a14 <_vfprintf_r+0x384> -800032f4: 0fc12783 lw a5,252(sp) -800032f8: 3007da63 bgez a5,8000360c <_vfprintf_r+0x1f7c> -800032fc: 02d00793 li a5,45 -80003300: 0cf103a3 sb a5,199(sp) -80003304: 02d00713 li a4,45 -80003308: 04700793 li a5,71 -8000330c: 2b57d6e3 bge a5,s5,80003db8 <_vfprintf_r+0x2728> -80003310: 800147b7 lui a5,0x80014 -80003314: 7dc78c93 addi s9,a5,2012 # 800147dc <__BSS_END__+0xffffda64> -80003318: e89ff06f j 800031a0 <_vfprintf_r+0x1b10> -8000331c: 01670733 add a4,a4,s6 -80003320: 00168693 addi a3,a3,1 -80003324: 018d2023 sw s8,0(s10) -80003328: 016d2223 sw s6,4(s10) -8000332c: 0ee12623 sw a4,236(sp) -80003330: 0ed12423 sw a3,232(sp) -80003334: 00700613 li a2,7 -80003338: 008d0d13 addi s10,s10,8 -8000333c: 86d652e3 bge a2,a3,80002ba0 <_vfprintf_r+0x1510> -80003340: 00412583 lw a1,4(sp) -80003344: 0e410613 addi a2,sp,228 -80003348: 000a0513 mv a0,s4 -8000334c: 01c090ef jal ra,8000c368 <__sprint_r> -80003350: 00050463 beqz a0,80003358 <_vfprintf_r+0x1cc8> -80003354: e08fe06f j 8000195c <_vfprintf_r+0x2cc> -80003358: 0ec12703 lw a4,236(sp) -8000335c: 10c10d13 addi s10,sp,268 -80003360: 841ff06f j 80002ba0 <_vfprintf_r+0x1510> -80003364: 01c12783 lw a5,28(sp) -80003368: 02412b83 lw s7,36(sp) -8000336c: 00912c23 sw s1,24(sp) -80003370: 00fc87b3 add a5,s9,a5 -80003374: 05212223 sw s2,68(sp) -80003378: 04812623 sw s0,76(sp) -8000337c: 02812483 lw s1,40(sp) -80003380: 03312223 sw s3,36(sp) -80003384: 03912423 sw s9,40(sp) -80003388: 000d0693 mv a3,s10 -8000338c: 00700b13 li s6,7 -80003390: 01000d93 li s11,16 -80003394: 04812903 lw s2,72(sp) -80003398: 04012403 lw s0,64(sp) -8000339c: 00412983 lw s3,4(sp) -800033a0: 00078d13 mv s10,a5 -800033a4: 080b8a63 beqz s7,80003438 <_vfprintf_r+0x1da8> -800033a8: 08049a63 bnez s1,8000343c <_vfprintf_r+0x1dac> -800033ac: fff40413 addi s0,s0,-1 -800033b0: fffb8b93 addi s7,s7,-1 -800033b4: 03c12783 lw a5,60(sp) -800033b8: 01270733 add a4,a4,s2 -800033bc: 0126a223 sw s2,4(a3) -800033c0: 00f6a023 sw a5,0(a3) -800033c4: 0e812783 lw a5,232(sp) -800033c8: 0ee12623 sw a4,236(sp) -800033cc: 00868693 addi a3,a3,8 -800033d0: 00178793 addi a5,a5,1 -800033d4: 0ef12423 sw a5,232(sp) -800033d8: 0efb4c63 blt s6,a5,800034d0 <_vfprintf_r+0x1e40> -800033dc: 00044603 lbu a2,0(s0) -800033e0: 415d05b3 sub a1,s10,s5 -800033e4: 00060c93 mv s9,a2 -800033e8: 00c5d463 bge a1,a2,800033f0 <_vfprintf_r+0x1d60> -800033ec: 00058c93 mv s9,a1 -800033f0: 03905663 blez s9,8000341c <_vfprintf_r+0x1d8c> -800033f4: 0e812603 lw a2,232(sp) -800033f8: 01970733 add a4,a4,s9 -800033fc: 0156a023 sw s5,0(a3) -80003400: 00160613 addi a2,a2,1 -80003404: 0196a223 sw s9,4(a3) -80003408: 0ee12623 sw a4,236(sp) -8000340c: 0ec12423 sw a2,232(sp) -80003410: 0ecb4263 blt s6,a2,800034f4 <_vfprintf_r+0x1e64> -80003414: 00044603 lbu a2,0(s0) -80003418: 00868693 addi a3,a3,8 -8000341c: fffcc593 not a1,s9 -80003420: 41f5d593 srai a1,a1,0x1f -80003424: 00bcf7b3 and a5,s9,a1 -80003428: 40f60cb3 sub s9,a2,a5 -8000342c: 01904c63 bgtz s9,80003444 <_vfprintf_r+0x1db4> -80003430: 00ca8ab3 add s5,s5,a2 -80003434: f60b9ae3 bnez s7,800033a8 <_vfprintf_r+0x1d18> -80003438: 5e048263 beqz s1,80003a1c <_vfprintf_r+0x238c> -8000343c: fff48493 addi s1,s1,-1 -80003440: f75ff06f j 800033b4 <_vfprintf_r+0x1d24> -80003444: 0e812603 lw a2,232(sp) -80003448: 019dc863 blt s11,s9,80003458 <_vfprintf_r+0x1dc8> -8000344c: 0580006f j 800034a4 <_vfprintf_r+0x1e14> -80003450: ff0c8c93 addi s9,s9,-16 -80003454: 059dd863 bge s11,s9,800034a4 <_vfprintf_r+0x1e14> -80003458: 01070713 addi a4,a4,16 -8000345c: 00160613 addi a2,a2,1 -80003460: 0186a023 sw s8,0(a3) -80003464: 01b6a223 sw s11,4(a3) -80003468: 0ee12623 sw a4,236(sp) -8000346c: 0ec12423 sw a2,232(sp) -80003470: 00868693 addi a3,a3,8 -80003474: fccb5ee3 bge s6,a2,80003450 <_vfprintf_r+0x1dc0> -80003478: 0e410613 addi a2,sp,228 -8000347c: 00098593 mv a1,s3 -80003480: 000a0513 mv a0,s4 -80003484: 6e5080ef jal ra,8000c368 <__sprint_r> -80003488: 00050463 beqz a0,80003490 <_vfprintf_r+0x1e00> -8000348c: cd0fe06f j 8000195c <_vfprintf_r+0x2cc> -80003490: ff0c8c93 addi s9,s9,-16 -80003494: 0ec12703 lw a4,236(sp) -80003498: 0e812603 lw a2,232(sp) -8000349c: 10c10693 addi a3,sp,268 -800034a0: fb9dcce3 blt s11,s9,80003458 <_vfprintf_r+0x1dc8> -800034a4: 01970733 add a4,a4,s9 -800034a8: 00160613 addi a2,a2,1 -800034ac: 0186a023 sw s8,0(a3) -800034b0: 0196a223 sw s9,4(a3) -800034b4: 0ee12623 sw a4,236(sp) -800034b8: 0ec12423 sw a2,232(sp) -800034bc: 62cb4a63 blt s6,a2,80003af0 <_vfprintf_r+0x2460> -800034c0: 00044603 lbu a2,0(s0) -800034c4: 00868693 addi a3,a3,8 -800034c8: 00ca8ab3 add s5,s5,a2 -800034cc: f69ff06f j 80003434 <_vfprintf_r+0x1da4> -800034d0: 0e410613 addi a2,sp,228 -800034d4: 00098593 mv a1,s3 -800034d8: 000a0513 mv a0,s4 -800034dc: 68d080ef jal ra,8000c368 <__sprint_r> -800034e0: 00050463 beqz a0,800034e8 <_vfprintf_r+0x1e58> -800034e4: c78fe06f j 8000195c <_vfprintf_r+0x2cc> -800034e8: 0ec12703 lw a4,236(sp) -800034ec: 10c10693 addi a3,sp,268 -800034f0: eedff06f j 800033dc <_vfprintf_r+0x1d4c> -800034f4: 0e410613 addi a2,sp,228 -800034f8: 00098593 mv a1,s3 -800034fc: 000a0513 mv a0,s4 -80003500: 669080ef jal ra,8000c368 <__sprint_r> -80003504: 00050463 beqz a0,8000350c <_vfprintf_r+0x1e7c> -80003508: c54fe06f j 8000195c <_vfprintf_r+0x2cc> -8000350c: 00044603 lbu a2,0(s0) -80003510: 0ec12703 lw a4,236(sp) -80003514: 10c10693 addi a3,sp,268 -80003518: f05ff06f j 8000341c <_vfprintf_r+0x1d8c> -8000351c: 001a8a93 addi s5,s5,1 -80003520: 00878d13 addi s10,a5,8 -80003524: 00078b93 mv s7,a5 -80003528: b78ff06f j 800028a0 <_vfprintf_r+0x1210> -8000352c: 00412583 lw a1,4(sp) -80003530: 0e410613 addi a2,sp,228 -80003534: 000a0513 mv a0,s4 -80003538: 631080ef jal ra,8000c368 <__sprint_r> -8000353c: 00050463 beqz a0,80003544 <_vfprintf_r+0x1eb4> -80003540: c1cfe06f j 8000195c <_vfprintf_r+0x2cc> -80003544: 0cc12603 lw a2,204(sp) -80003548: 0ec12703 lw a4,236(sp) -8000354c: 10c10d13 addi s10,sp,268 -80003550: a85ff06f j 80002fd4 <_vfprintf_r+0x1944> -80003554: 800147b7 lui a5,0x80014 -80003558: 7d078c93 addi s9,a5,2000 # 800147d0 <__BSS_END__+0xffffda58> -8000355c: c45ff06f j 800031a0 <_vfprintf_r+0x1b10> -80003560: 00412583 lw a1,4(sp) -80003564: 0e410613 addi a2,sp,228 -80003568: 000a0513 mv a0,s4 -8000356c: 5fd080ef jal ra,8000c368 <__sprint_r> -80003570: 00050463 beqz a0,80003578 <_vfprintf_r+0x1ee8> -80003574: be8fe06f j 8000195c <_vfprintf_r+0x2cc> -80003578: 0ec12703 lw a4,236(sp) -8000357c: 10c10d13 addi s10,sp,268 -80003580: e08ff06f j 80002b88 <_vfprintf_r+0x14f8> -80003584: 00600b13 li s6,6 -80003588: 941ff06f j 80002ec8 <_vfprintf_r+0x1838> -8000358c: 01c12683 lw a3,28(sp) -80003590: 00dc87b3 add a5,s9,a3 -80003594: 41668b33 sub s6,a3,s6 -80003598: 41578bb3 sub s7,a5,s5 -8000359c: eb7b5463 bge s6,s7,80002c44 <_vfprintf_r+0x15b4> -800035a0: 000b0b93 mv s7,s6 -800035a4: ea0ff06f j 80002c44 <_vfprintf_r+0x15b4> -800035a8: 01012783 lw a5,16(sp) -800035ac: 00e12823 sw a4,16(sp) -800035b0: 00812703 lw a4,8(sp) -800035b4: 0007a783 lw a5,0(a5) -800035b8: 00048c93 mv s9,s1 -800035bc: 00e79023 sh a4,0(a5) -800035c0: decfe06f j 80001bac <_vfprintf_r+0x51c> -800035c4: 0ffbfb93 andi s7,s7,255 -800035c8: 00000d93 li s11,0 -800035cc: c2cfe06f j 800019f8 <_vfprintf_r+0x368> -800035d0: 00f12823 sw a5,16(sp) -800035d4: 00000d93 li s11,0 -800035d8: 00090993 mv s3,s2 -800035dc: 00100793 li a5,1 -800035e0: c34fe06f j 80001a14 <_vfprintf_r+0x384> -800035e4: 00000d93 li s11,0 -800035e8: 00f12823 sw a5,16(sp) -800035ec: ed9fe06f j 800024c4 <_vfprintf_r+0xe34> -800035f0: 01012703 lw a4,16(sp) -800035f4: 00090993 mv s3,s2 -800035f8: 00f12823 sw a5,16(sp) -800035fc: 00072b83 lw s7,0(a4) -80003600: 41fbdd93 srai s11,s7,0x1f -80003604: 000d8713 mv a4,s11 -80003608: e3cfe06f j 80001c44 <_vfprintf_r+0x5b4> -8000360c: 0c714703 lbu a4,199(sp) -80003610: cf9ff06f j 80003308 <_vfprintf_r+0x1c78> -80003614: 00412583 lw a1,4(sp) -80003618: 0e410613 addi a2,sp,228 -8000361c: 000a0513 mv a0,s4 -80003620: 549080ef jal ra,8000c368 <__sprint_r> -80003624: 00050463 beqz a0,8000362c <_vfprintf_r+0x1f9c> -80003628: b34fe06f j 8000195c <_vfprintf_r+0x2cc> -8000362c: 0cc12603 lw a2,204(sp) -80003630: 0ec12703 lw a4,236(sp) -80003634: 0e812683 lw a3,232(sp) -80003638: 10c10893 addi a7,sp,268 -8000363c: 9e0650e3 bgez a2,8000301c <_vfprintf_r+0x198c> -80003640: bedff06f j 8000322c <_vfprintf_r+0x1b9c> -80003644: 03000793 li a5,48 -80003648: 0cf10423 sb a5,200(sp) -8000364c: 05800793 li a5,88 -80003650: 0cf104a3 sb a5,201(sp) -80003654: 00296793 ori a5,s2,2 -80003658: 06300713 li a4,99 -8000365c: 04f12c23 sw a5,88(sp) -80003660: 00012a23 sw zero,20(sp) -80003664: 14c10c93 addi s9,sp,332 -80003668: 086748e3 blt a4,t1,80003ef8 <_vfprintf_r+0x2868> -8000366c: 0fc12e83 lw t4,252(sp) -80003670: fdfaf793 andi a5,s5,-33 -80003674: 04f12623 sw a5,76(sp) -80003678: 04012e23 sw zero,92(sp) -8000367c: 10296913 ori s2,s2,258 -80003680: 0f012283 lw t0,240(sp) -80003684: 0f412f03 lw t5,244(sp) -80003688: 0f812f83 lw t6,248(sp) -8000368c: 440ec863 bltz t4,80003adc <_vfprintf_r+0x244c> -80003690: 06100713 li a4,97 -80003694: 18ea84e3 beq s5,a4,8000401c <_vfprintf_r+0x298c> -80003698: 04100713 li a4,65 -8000369c: 00ea8463 beq s5,a4,800036a4 <_vfprintf_r+0x2014> -800036a0: 9c9fe06f j 80002068 <_vfprintf_r+0x9d8> -800036a4: 0b010993 addi s3,sp,176 -800036a8: 00098513 mv a0,s3 -800036ac: 04612a23 sw t1,84(sp) -800036b0: 0a512823 sw t0,176(sp) -800036b4: 0be12a23 sw t5,180(sp) -800036b8: 0bf12c23 sw t6,184(sp) -800036bc: 0bd12e23 sw t4,188(sp) -800036c0: 309100ef jal ra,800141c8 <__trunctfdf2> -800036c4: 0cc10613 addi a2,sp,204 -800036c8: 23d050ef jal ra,80009104 -800036cc: 00058613 mv a2,a1 -800036d0: 00050593 mv a1,a0 -800036d4: 00098513 mv a0,s3 -800036d8: 0e5100ef jal ra,80013fbc <__extenddftf2> -800036dc: 0b012703 lw a4,176(sp) -800036e0: 09010793 addi a5,sp,144 -800036e4: 0a010b93 addi s7,sp,160 -800036e8: 08e12823 sw a4,144(sp) -800036ec: 0b412703 lw a4,180(sp) -800036f0: 08010613 addi a2,sp,128 -800036f4: 00078593 mv a1,a5 -800036f8: 08e12a23 sw a4,148(sp) -800036fc: 0b812703 lw a4,184(sp) -80003700: 000b8513 mv a0,s7 -80003704: 00f12e23 sw a5,28(sp) -80003708: 08e12c23 sw a4,152(sp) -8000370c: 0bc12703 lw a4,188(sp) -80003710: 04c12823 sw a2,80(sp) -80003714: 08012023 sw zero,128(sp) -80003718: 08e12e23 sw a4,156(sp) -8000371c: 3ffc0737 lui a4,0x3ffc0 -80003720: 08e12623 sw a4,140(sp) -80003724: 08012223 sw zero,132(sp) -80003728: 08012423 sw zero,136(sp) -8000372c: 0900e0ef jal ra,800117bc <__multf3> -80003730: 0a012783 lw a5,160(sp) -80003734: 0a412803 lw a6,164(sp) -80003738: 0a812e83 lw t4,168(sp) -8000373c: 0ac12f03 lw t5,172(sp) -80003740: 000b8593 mv a1,s7 -80003744: 00098513 mv a0,s3 -80003748: 0af12823 sw a5,176(sp) -8000374c: 04f12223 sw a5,68(sp) -80003750: 0b012a23 sw a6,180(sp) -80003754: 03012423 sw a6,40(sp) -80003758: 0bd12c23 sw t4,184(sp) -8000375c: 03d12223 sw t4,36(sp) -80003760: 0be12e23 sw t5,188(sp) -80003764: 01e12c23 sw t5,24(sp) -80003768: 0a012023 sw zero,160(sp) -8000376c: 0a012223 sw zero,164(sp) -80003770: 0a012423 sw zero,168(sp) -80003774: 0a012623 sw zero,172(sp) -80003778: 4f10d0ef jal ra,80011468 <__eqtf2> -8000377c: 01812f03 lw t5,24(sp) -80003780: 02412e83 lw t4,36(sp) -80003784: 02812803 lw a6,40(sp) -80003788: 04412783 lw a5,68(sp) -8000378c: 05412303 lw t1,84(sp) -80003790: 00051663 bnez a0,8000379c <_vfprintf_r+0x210c> -80003794: 00100713 li a4,1 -80003798: 0ce12623 sw a4,204(sp) -8000379c: 80014737 lui a4,0x80014 -800037a0: 7f470713 addi a4,a4,2036 # 800147f4 <__BSS_END__+0xffffda7c> -800037a4: 04e12223 sw a4,68(sp) -800037a8: fff30b13 addi s6,t1,-1 -800037ac: 01912c23 sw s9,24(sp) -800037b0: 06912023 sw s1,96(sp) -800037b4: 07512223 sw s5,100(sp) -800037b8: 07a12a23 sw s10,116(sp) -800037bc: 07412c23 sw s4,120(sp) -800037c0: 07912e23 sw s9,124(sp) -800037c4: 07212423 sw s2,104(sp) -800037c8: 06812623 sw s0,108(sp) -800037cc: 06612823 sw t1,112(sp) -800037d0: 000b0c93 mv s9,s6 -800037d4: 00078d13 mv s10,a5 -800037d8: 00080d93 mv s11,a6 -800037dc: 000e8a13 mv s4,t4 -800037e0: 000f0a93 mv s5,t5 -800037e4: 01c12483 lw s1,28(sp) -800037e8: 0540006f j 8000383c <_vfprintf_r+0x21ac> -800037ec: 000b8593 mv a1,s7 -800037f0: 00098513 mv a0,s3 -800037f4: 02c12423 sw a2,40(sp) -800037f8: 03f12223 sw t6,36(sp) -800037fc: 00512e23 sw t0,28(sp) -80003800: 0a512a23 sw t0,180(sp) -80003804: 0bf12c23 sw t6,184(sp) -80003808: 0ac12e23 sw a2,188(sp) -8000380c: 0b212823 sw s2,176(sp) -80003810: 0a012023 sw zero,160(sp) -80003814: 0a012223 sw zero,164(sp) -80003818: 0a012423 sw zero,168(sp) -8000381c: 0a012623 sw zero,172(sp) -80003820: 4490d0ef jal ra,80011468 <__eqtf2> -80003824: fffc8c93 addi s9,s9,-1 -80003828: 01c12283 lw t0,28(sp) -8000382c: 02412f83 lw t6,36(sp) -80003830: 02812603 lw a2,40(sp) -80003834: 0e050463 beqz a0,8000391c <_vfprintf_r+0x228c> -80003838: 01612c23 sw s6,24(sp) -8000383c: 400307b7 lui a5,0x40030 -80003840: 00048613 mv a2,s1 -80003844: 000b8593 mv a1,s7 -80003848: 00098513 mv a0,s3 -8000384c: 08f12e23 sw a5,156(sp) -80003850: 0ba12023 sw s10,160(sp) -80003854: 0bb12223 sw s11,164(sp) -80003858: 0b412423 sw s4,168(sp) -8000385c: 0b512623 sw s5,172(sp) -80003860: 08012823 sw zero,144(sp) -80003864: 08012a23 sw zero,148(sp) -80003868: 08012c23 sw zero,152(sp) -8000386c: 7510d0ef jal ra,800117bc <__multf3> -80003870: 00098513 mv a0,s3 -80003874: 470100ef jal ra,80013ce4 <__fixtfsi> -80003878: 00050593 mv a1,a0 -8000387c: 00050413 mv s0,a0 -80003880: 00098513 mv a0,s3 -80003884: 0bc12b03 lw s6,188(sp) -80003888: 0b012a83 lw s5,176(sp) -8000388c: 0b412a03 lw s4,180(sp) -80003890: 0b812903 lw s2,184(sp) -80003894: 5a0100ef jal ra,80013e34 <__floatsitf> -80003898: 0b012783 lw a5,176(sp) -8000389c: 05012603 lw a2,80(sp) -800038a0: 00048593 mv a1,s1 -800038a4: 08f12023 sw a5,128(sp) -800038a8: 0b412783 lw a5,180(sp) -800038ac: 000b8513 mv a0,s7 -800038b0: 09612e23 sw s6,156(sp) -800038b4: 08f12223 sw a5,132(sp) -800038b8: 0b812783 lw a5,184(sp) -800038bc: 09512823 sw s5,144(sp) -800038c0: 09412a23 sw s4,148(sp) -800038c4: 08f12423 sw a5,136(sp) -800038c8: 0bc12783 lw a5,188(sp) -800038cc: 09212c23 sw s2,152(sp) -800038d0: 08f12623 sw a5,140(sp) -800038d4: 6f10e0ef jal ra,800127c4 <__subtf3> -800038d8: 04412783 lw a5,68(sp) -800038dc: 01812703 lw a4,24(sp) -800038e0: 0a012903 lw s2,160(sp) -800038e4: 008787b3 add a5,a5,s0 -800038e8: 0007c783 lbu a5,0(a5) # 40030000 <_start-0x3ffd0000> -800038ec: 0a412283 lw t0,164(sp) -800038f0: 0a812f83 lw t6,168(sp) -800038f4: 0ac12603 lw a2,172(sp) -800038f8: 00170b13 addi s6,a4,1 -800038fc: fefb0fa3 sb a5,-1(s6) -80003900: 05912a23 sw s9,84(sp) -80003904: fff00793 li a5,-1 -80003908: 00090d13 mv s10,s2 -8000390c: 00028d93 mv s11,t0 -80003910: 000f8a13 mv s4,t6 -80003914: 00060a93 mv s5,a2 -80003918: ecfc9ae3 bne s9,a5,800037ec <_vfprintf_r+0x215c> -8000391c: 07012303 lw t1,112(sp) -80003920: 00090393 mv t2,s2 -80003924: 3ffe06b7 lui a3,0x3ffe0 -80003928: 000b8593 mv a1,s7 -8000392c: 00098513 mv a0,s3 -80003930: 02612223 sw t1,36(sp) -80003934: 00812e23 sw s0,28(sp) -80003938: 06012483 lw s1,96(sp) -8000393c: 06412a83 lw s5,100(sp) -80003940: 0a712823 sw t2,176(sp) -80003944: 06712223 sw t2,100(sp) -80003948: 0a512a23 sw t0,180(sp) -8000394c: 06512023 sw t0,96(sp) -80003950: 0bf12c23 sw t6,184(sp) -80003954: 05f12823 sw t6,80(sp) -80003958: 0ac12e23 sw a2,188(sp) -8000395c: 02c12423 sw a2,40(sp) -80003960: 0a012023 sw zero,160(sp) -80003964: 0a012223 sw zero,164(sp) -80003968: 0a012423 sw zero,168(sp) -8000396c: 0ad12623 sw a3,172(sp) -80003970: 3c50d0ef jal ra,80011534 <__getf2> -80003974: 07412d03 lw s10,116(sp) -80003978: 06c12403 lw s0,108(sp) -8000397c: 000b0d93 mv s11,s6 -80003980: 07812a03 lw s4,120(sp) -80003984: 07c12c83 lw s9,124(sp) -80003988: 06812903 lw s2,104(sp) -8000398c: 02412303 lw t1,36(sp) -80003990: 48a04c63 bgtz a0,80003e28 <_vfprintf_r+0x2798> -80003994: 06412383 lw t2,100(sp) -80003998: 06012283 lw t0,96(sp) -8000399c: 05012f83 lw t6,80(sp) -800039a0: 02812603 lw a2,40(sp) -800039a4: 3ffe06b7 lui a3,0x3ffe0 -800039a8: 000b8593 mv a1,s7 -800039ac: 00098513 mv a0,s3 -800039b0: 0a712823 sw t2,176(sp) -800039b4: 0a512a23 sw t0,180(sp) -800039b8: 0bf12c23 sw t6,184(sp) -800039bc: 0ac12e23 sw a2,188(sp) -800039c0: 0a012023 sw zero,160(sp) -800039c4: 0a012223 sw zero,164(sp) -800039c8: 0a012423 sw zero,168(sp) -800039cc: 0ad12623 sw a3,172(sp) -800039d0: 2990d0ef jal ra,80011468 <__eqtf2> -800039d4: 02412303 lw t1,36(sp) -800039d8: 00051863 bnez a0,800039e8 <_vfprintf_r+0x2358> -800039dc: 01c12783 lw a5,28(sp) -800039e0: 0017fb13 andi s6,a5,1 -800039e4: 440b1263 bnez s6,80003e28 <_vfprintf_r+0x2798> -800039e8: 05412783 lw a5,84(sp) -800039ec: 03000613 li a2,48 -800039f0: 00178693 addi a3,a5,1 -800039f4: 00dd86b3 add a3,s11,a3 -800039f8: 0007c863 bltz a5,80003a08 <_vfprintf_r+0x2378> -800039fc: 001d8d93 addi s11,s11,1 -80003a00: fecd8fa3 sb a2,-1(s11) -80003a04: ffb69ce3 bne a3,s11,800039fc <_vfprintf_r+0x236c> -80003a08: 419d87b3 sub a5,s11,s9 -80003a0c: 00f12e23 sw a5,28(sp) -80003a10: f00fe06f j 80002110 <_vfprintf_r+0xa80> -80003a14: 00090993 mv s3,s2 -80003a18: ac9fe06f j 800024e0 <_vfprintf_r+0xe50> -80003a1c: 02812c83 lw s9,40(sp) -80003a20: 01c12783 lw a5,28(sp) -80003a24: 04812023 sw s0,64(sp) -80003a28: 00068d13 mv s10,a3 -80003a2c: 00fc86b3 add a3,s9,a5 -80003a30: 01812483 lw s1,24(sp) -80003a34: 04412903 lw s2,68(sp) -80003a38: 04c12403 lw s0,76(sp) -80003a3c: 02412983 lw s3,36(sp) -80003a40: 9756f863 bgeu a3,s5,80002bb0 <_vfprintf_r+0x1520> -80003a44: 00068a93 mv s5,a3 -80003a48: 968ff06f j 80002bb0 <_vfprintf_r+0x1520> -80003a4c: 01812783 lw a5,24(sp) -80003a50: ffd00713 li a4,-3 -80003a54: 00e7c463 blt a5,a4,80003a5c <_vfprintf_r+0x23cc> -80003a58: 00f35a63 bge t1,a5,80003a6c <_vfprintf_r+0x23dc> -80003a5c: ffea8a93 addi s5,s5,-2 -80003a60: fdfaf793 andi a5,s5,-33 -80003a64: 04f12623 sw a5,76(sp) -80003a68: ed0fe06f j 80002138 <_vfprintf_r+0xaa8> -80003a6c: 01c12703 lw a4,28(sp) -80003a70: 01812783 lw a5,24(sp) -80003a74: 2ee7c263 blt a5,a4,80003d58 <_vfprintf_r+0x26c8> -80003a78: 05812703 lw a4,88(sp) -80003a7c: 00078b13 mv s6,a5 -80003a80: 00177713 andi a4,a4,1 -80003a84: 00070663 beqz a4,80003a90 <_vfprintf_r+0x2400> -80003a88: 02c12703 lw a4,44(sp) -80003a8c: 00e78b33 add s6,a5,a4 -80003a90: 05812783 lw a5,88(sp) -80003a94: 4007f713 andi a4,a5,1024 -80003a98: 00070663 beqz a4,80003aa4 <_vfprintf_r+0x2414> -80003a9c: 01812783 lw a5,24(sp) -80003aa0: 4af04863 bgtz a5,80003f50 <_vfprintf_r+0x28c0> -80003aa4: fffb4993 not s3,s6 -80003aa8: 41f9d993 srai s3,s3,0x1f -80003aac: 013b79b3 and s3,s6,s3 -80003ab0: 06700a93 li s5,103 -80003ab4: 02012423 sw zero,40(sp) -80003ab8: 02012223 sw zero,36(sp) -80003abc: f90fe06f j 8000224c <_vfprintf_r+0xbbc> -80003ac0: 0c714703 lbu a4,199(sp) -80003ac4: 00000313 li t1,0 -80003ac8: 00070463 beqz a4,80003ad0 <_vfprintf_r+0x2440> -80003acc: f9dfd06f j 80001a68 <_vfprintf_r+0x3d8> -80003ad0: ad0fe06f j 80001da0 <_vfprintf_r+0x710> -80003ad4: 00012a23 sw zero,20(sp) -80003ad8: 00070913 mv s2,a4 -80003adc: 80000737 lui a4,0x80000 -80003ae0: 02d00793 li a5,45 -80003ae4: 01d74eb3 xor t4,a4,t4 -80003ae8: 04f12e23 sw a5,92(sp) -80003aec: ba5ff06f j 80003690 <_vfprintf_r+0x2000> -80003af0: 0e410613 addi a2,sp,228 -80003af4: 00098593 mv a1,s3 -80003af8: 000a0513 mv a0,s4 -80003afc: 06d080ef jal ra,8000c368 <__sprint_r> -80003b00: 00050463 beqz a0,80003b08 <_vfprintf_r+0x2478> -80003b04: e59fd06f j 8000195c <_vfprintf_r+0x2cc> -80003b08: 00044603 lbu a2,0(s0) -80003b0c: 0ec12703 lw a4,236(sp) -80003b10: 10c10693 addi a3,sp,268 -80003b14: 00ca8ab3 add s5,s5,a2 -80003b18: 91dff06f j 80003434 <_vfprintf_r+0x1da4> -80003b1c: 04812783 lw a5,72(sp) -80003b20: 03c12583 lw a1,60(sp) -80003b24: 00000413 li s0,0 -80003b28: 40f989b3 sub s3,s3,a5 -80003b2c: 00078613 mv a2,a5 -80003b30: 00098513 mv a0,s3 -80003b34: 375050ef jal ra,800096a8 -80003b38: 0014c803 lbu a6,1(s1) -80003b3c: 00a00613 li a2,10 -80003b40: 00000693 li a3,0 -80003b44: 01003833 snez a6,a6 -80003b48: 000b8513 mv a0,s7 -80003b4c: 000a0593 mv a1,s4 -80003b50: 010484b3 add s1,s1,a6 -80003b54: 4500c0ef jal ra,8000ffa4 <__udivdi3> -80003b58: d48ff06f j 800030a0 <_vfprintf_r+0x1a10> -80003b5c: 00900793 li a5,9 -80003b60: d577e063 bltu a5,s7,800030a0 <_vfprintf_r+0x1a10> -80003b64: d84ff06f j 800030e8 <_vfprintf_r+0x1a58> -80003b68: 02d00793 li a5,45 -80003b6c: 0cf103a3 sb a5,199(sp) -80003b70: 02d00713 li a4,45 -80003b74: e1cff06f j 80003190 <_vfprintf_r+0x1b00> -80003b78: 0b010993 addi s3,sp,176 -80003b7c: 00030693 mv a3,t1 -80003b80: 0cc10713 addi a4,sp,204 -80003b84: 0dc10813 addi a6,sp,220 -80003b88: 0d010793 addi a5,sp,208 -80003b8c: 00300613 li a2,3 -80003b90: 00098593 mv a1,s3 -80003b94: 000a0513 mv a0,s4 -80003b98: 04612223 sw t1,68(sp) -80003b9c: 0a512823 sw t0,176(sp) -80003ba0: 02512423 sw t0,40(sp) -80003ba4: 0be12a23 sw t5,180(sp) -80003ba8: 03e12223 sw t5,36(sp) -80003bac: 0bf12c23 sw t6,184(sp) -80003bb0: 01f12e23 sw t6,28(sp) -80003bb4: 0bd12e23 sw t4,188(sp) -80003bb8: 01d12c23 sw t4,24(sp) -80003bbc: 5ed020ef jal ra,800069a8 <_ldtoa_r> -80003bc0: 00054683 lbu a3,0(a0) -80003bc4: 03000713 li a4,48 -80003bc8: 00050c93 mv s9,a0 -80003bcc: 01812e83 lw t4,24(sp) -80003bd0: 01c12f83 lw t6,28(sp) -80003bd4: 02412f03 lw t5,36(sp) -80003bd8: 02812283 lw t0,40(sp) -80003bdc: 04412303 lw t1,68(sp) -80003be0: 0a010b93 addi s7,sp,160 -80003be4: 06e68c63 beq a3,a4,80003c5c <_vfprintf_r+0x25cc> -80003be8: 0cc12703 lw a4,204(sp) -80003bec: 00670b33 add s6,a4,t1 -80003bf0: 016c8b33 add s6,s9,s6 -80003bf4: 000b8593 mv a1,s7 -80003bf8: 00098513 mv a0,s3 -80003bfc: 00612c23 sw t1,24(sp) -80003c00: 0a512823 sw t0,176(sp) -80003c04: 0be12a23 sw t5,180(sp) -80003c08: 0bf12c23 sw t6,184(sp) -80003c0c: 0bd12e23 sw t4,188(sp) -80003c10: 0a012023 sw zero,160(sp) -80003c14: 0a012223 sw zero,164(sp) -80003c18: 0a012423 sw zero,168(sp) -80003c1c: 0a012623 sw zero,172(sp) -80003c20: 0490d0ef jal ra,80011468 <__eqtf2> -80003c24: 000b0713 mv a4,s6 -80003c28: 01812303 lw t1,24(sp) -80003c2c: 00051463 bnez a0,80003c34 <_vfprintf_r+0x25a4> -80003c30: cd8fe06f j 80002108 <_vfprintf_r+0xa78> -80003c34: 0dc12703 lw a4,220(sp) -80003c38: 03000613 li a2,48 -80003c3c: 01676463 bltu a4,s6,80003c44 <_vfprintf_r+0x25b4> -80003c40: cc8fe06f j 80002108 <_vfprintf_r+0xa78> -80003c44: 00170793 addi a5,a4,1 # 80000001 <__BSS_END__+0xfffe9289> -80003c48: 0cf12e23 sw a5,220(sp) -80003c4c: 00c70023 sb a2,0(a4) -80003c50: 0dc12703 lw a4,220(sp) -80003c54: ff6768e3 bltu a4,s6,80003c44 <_vfprintf_r+0x25b4> -80003c58: cb0fe06f j 80002108 <_vfprintf_r+0xa78> -80003c5c: 0a010b93 addi s7,sp,160 -80003c60: 000b8593 mv a1,s7 -80003c64: 00098513 mv a0,s3 -80003c68: 04612223 sw t1,68(sp) -80003c6c: 0a512823 sw t0,176(sp) -80003c70: 02512423 sw t0,40(sp) -80003c74: 0be12a23 sw t5,180(sp) -80003c78: 03e12223 sw t5,36(sp) -80003c7c: 0bf12c23 sw t6,184(sp) -80003c80: 01f12e23 sw t6,28(sp) -80003c84: 0bd12e23 sw t4,188(sp) -80003c88: 01d12c23 sw t4,24(sp) -80003c8c: 0a012023 sw zero,160(sp) -80003c90: 0a012223 sw zero,164(sp) -80003c94: 0a012423 sw zero,168(sp) -80003c98: 0a012623 sw zero,172(sp) -80003c9c: 7cc0d0ef jal ra,80011468 <__eqtf2> -80003ca0: 01812e83 lw t4,24(sp) -80003ca4: 01c12f83 lw t6,28(sp) -80003ca8: 02412f03 lw t5,36(sp) -80003cac: 02812283 lw t0,40(sp) -80003cb0: 04412303 lw t1,68(sp) -80003cb4: f2050ae3 beqz a0,80003be8 <_vfprintf_r+0x2558> -80003cb8: 00100713 li a4,1 -80003cbc: 40670733 sub a4,a4,t1 -80003cc0: 0ce12623 sw a4,204(sp) -80003cc4: f29ff06f j 80003bec <_vfprintf_r+0x255c> -80003cc8: 00412583 lw a1,4(sp) -80003ccc: 0e410613 addi a2,sp,228 -80003cd0: 000a0513 mv a0,s4 -80003cd4: 694080ef jal ra,8000c368 <__sprint_r> -80003cd8: 00050463 beqz a0,80003ce0 <_vfprintf_r+0x2650> -80003cdc: c81fd06f j 8000195c <_vfprintf_r+0x2cc> -80003ce0: 0cc12b03 lw s6,204(sp) -80003ce4: 0ec12703 lw a4,236(sp) -80003ce8: 10c10d13 addi s10,sp,268 -80003cec: f0dfe06f j 80002bf8 <_vfprintf_r+0x1568> -80003cf0: 0c714703 lbu a4,199(sp) -80003cf4: 01712823 sw s7,16(sp) -80003cf8: 02012423 sw zero,40(sp) -80003cfc: 02012223 sw zero,36(sp) -80003d00: 00012c23 sw zero,24(sp) -80003d04: 00030993 mv s3,t1 -80003d08: 00030b13 mv s6,t1 -80003d0c: 00000313 li t1,0 -80003d10: 00070463 beqz a4,80003d18 <_vfprintf_r+0x2688> -80003d14: d55fd06f j 80001a68 <_vfprintf_r+0x3d8> -80003d18: 888fe06f j 80001da0 <_vfprintf_r+0x710> -80003d1c: 05812783 lw a5,88(sp) -80003d20: 0017f713 andi a4,a5,1 -80003d24: 01812783 lw a5,24(sp) -80003d28: 00676733 or a4,a4,t1 -80003d2c: 42f05263 blez a5,80004150 <_vfprintf_r+0x2ac0> -80003d30: 2a071463 bnez a4,80003fd8 <_vfprintf_r+0x2948> -80003d34: 01812b03 lw s6,24(sp) -80003d38: 06600a93 li s5,102 -80003d3c: 05812783 lw a5,88(sp) -80003d40: 4007f713 andi a4,a5,1024 -80003d44: 20071863 bnez a4,80003f54 <_vfprintf_r+0x28c4> -80003d48: fffb4993 not s3,s6 -80003d4c: 41f9d993 srai s3,s3,0x1f -80003d50: 013b79b3 and s3,s6,s3 -80003d54: d61ff06f j 80003ab4 <_vfprintf_r+0x2424> -80003d58: 01c12783 lw a5,28(sp) -80003d5c: 02c12703 lw a4,44(sp) -80003d60: 06700a93 li s5,103 -80003d64: 00e78b33 add s6,a5,a4 -80003d68: 01812783 lw a5,24(sp) -80003d6c: fcf048e3 bgtz a5,80003d3c <_vfprintf_r+0x26ac> -80003d70: 40fb0b33 sub s6,s6,a5 -80003d74: 001b0b13 addi s6,s6,1 -80003d78: fffb4993 not s3,s6 -80003d7c: 41f9d993 srai s3,s3,0x1f -80003d80: 013b79b3 and s3,s6,s3 -80003d84: d31ff06f j 80003ab4 <_vfprintf_r+0x2424> -80003d88: 00412583 lw a1,4(sp) -80003d8c: 0e410613 addi a2,sp,228 -80003d90: 000a0513 mv a0,s4 -80003d94: 5d4080ef jal ra,8000c368 <__sprint_r> -80003d98: 00050463 beqz a0,80003da0 <_vfprintf_r+0x2710> -80003d9c: bc1fd06f j 8000195c <_vfprintf_r+0x2cc> -80003da0: 0cc12b03 lw s6,204(sp) -80003da4: 01c12783 lw a5,28(sp) -80003da8: 0ec12703 lw a4,236(sp) -80003dac: 10c10d13 addi s10,sp,268 -80003db0: 41678b33 sub s6,a5,s6 -80003db4: e91fe06f j 80002c44 <_vfprintf_r+0x15b4> -80003db8: 800147b7 lui a5,0x80014 -80003dbc: 7d878c93 addi s9,a5,2008 # 800147d8 <__BSS_END__+0xffffda60> -80003dc0: be0ff06f j 800031a0 <_vfprintf_r+0x1b10> -80003dc4: 800146b7 lui a3,0x80014 -80003dc8: 7b068d93 addi s11,a3,1968 # 800147b0 <__BSS_END__+0xffffda38> -80003dcc: 994fe06f j 80001f60 <_vfprintf_r+0x8d0> -80003dd0: fff00793 li a5,-1 -80003dd4: 00f12423 sw a5,8(sp) -80003dd8: badfd06f j 80001984 <_vfprintf_r+0x2f4> -80003ddc: 01670733 add a4,a4,s6 -80003de0: 00168693 addi a3,a3,1 -80003de4: 0188a023 sw s8,0(a7) -80003de8: 0168a223 sw s6,4(a7) -80003dec: 0ee12623 sw a4,236(sp) -80003df0: 0ed12423 sw a3,232(sp) -80003df4: 00700613 li a2,7 -80003df8: 00888893 addi a7,a7,8 -80003dfc: a2d65063 bge a2,a3,8000301c <_vfprintf_r+0x198c> -80003e00: 00412583 lw a1,4(sp) -80003e04: 0e410613 addi a2,sp,228 -80003e08: 000a0513 mv a0,s4 -80003e0c: 55c080ef jal ra,8000c368 <__sprint_r> -80003e10: 00050463 beqz a0,80003e18 <_vfprintf_r+0x2788> -80003e14: b49fd06f j 8000195c <_vfprintf_r+0x2cc> -80003e18: 0ec12703 lw a4,236(sp) -80003e1c: 0e812683 lw a3,232(sp) -80003e20: 10c10893 addi a7,sp,268 -80003e24: 9f8ff06f j 8000301c <_vfprintf_r+0x198c> -80003e28: 01812783 lw a5,24(sp) -80003e2c: 000d8693 mv a3,s11 -80003e30: 0cf12e23 sw a5,220(sp) -80003e34: 04412783 lw a5,68(sp) -80003e38: fffdc603 lbu a2,-1(s11) -80003e3c: 00f7c583 lbu a1,15(a5) -80003e40: 02b61063 bne a2,a1,80003e60 <_vfprintf_r+0x27d0> -80003e44: 03000513 li a0,48 -80003e48: fea68fa3 sb a0,-1(a3) -80003e4c: 0dc12683 lw a3,220(sp) -80003e50: fff68793 addi a5,a3,-1 -80003e54: 0cf12e23 sw a5,220(sp) -80003e58: fff6c603 lbu a2,-1(a3) -80003e5c: fec586e3 beq a1,a2,80003e48 <_vfprintf_r+0x27b8> -80003e60: 00160593 addi a1,a2,1 -80003e64: 03900513 li a0,57 -80003e68: 0ff5f593 andi a1,a1,255 -80003e6c: 00a60663 beq a2,a0,80003e78 <_vfprintf_r+0x27e8> -80003e70: feb68fa3 sb a1,-1(a3) -80003e74: b95ff06f j 80003a08 <_vfprintf_r+0x2378> -80003e78: 04412783 lw a5,68(sp) -80003e7c: 00a7c583 lbu a1,10(a5) -80003e80: feb68fa3 sb a1,-1(a3) -80003e84: b85ff06f j 80003a08 <_vfprintf_r+0x2378> -80003e88: 00130b13 addi s6,t1,1 -80003e8c: 0b010993 addi s3,sp,176 -80003e90: 0dc10813 addi a6,sp,220 -80003e94: 0d010793 addi a5,sp,208 -80003e98: 0cc10713 addi a4,sp,204 -80003e9c: 000b0693 mv a3,s6 -80003ea0: 00200613 li a2,2 -80003ea4: 00098593 mv a1,s3 -80003ea8: 000a0513 mv a0,s4 -80003eac: 04612223 sw t1,68(sp) -80003eb0: 0a512823 sw t0,176(sp) -80003eb4: 02512423 sw t0,40(sp) -80003eb8: 0be12a23 sw t5,180(sp) -80003ebc: 03e12223 sw t5,36(sp) -80003ec0: 0bf12c23 sw t6,184(sp) -80003ec4: 01f12e23 sw t6,28(sp) -80003ec8: 0bd12e23 sw t4,188(sp) -80003ecc: 01d12c23 sw t4,24(sp) -80003ed0: 2d9020ef jal ra,800069a8 <_ldtoa_r> -80003ed4: 01812e83 lw t4,24(sp) -80003ed8: 01c12f83 lw t6,28(sp) -80003edc: 02412f03 lw t5,36(sp) -80003ee0: 02812283 lw t0,40(sp) -80003ee4: 04412303 lw t1,68(sp) -80003ee8: 00050c93 mv s9,a0 -80003eec: 016c8b33 add s6,s9,s6 -80003ef0: 0a010b93 addi s7,sp,160 -80003ef4: d01ff06f j 80003bf4 <_vfprintf_r+0x2564> -80003ef8: 00130593 addi a1,t1,1 -80003efc: 000a0513 mv a0,s4 -80003f00: 00612a23 sw t1,20(sp) -80003f04: dfdfc0ef jal ra,80000d00 <_malloc_r> -80003f08: 00050c93 mv s9,a0 -80003f0c: 01412303 lw t1,20(sp) -80003f10: 2c050263 beqz a0,800041d4 <_vfprintf_r+0x2b44> -80003f14: 00a12a23 sw a0,20(sp) -80003f18: f54ff06f j 8000366c <_vfprintf_r+0x1fdc> -80003f1c: 03000793 li a5,48 -80003f20: 0cf10423 sb a5,200(sp) -80003f24: 07800793 li a5,120 -80003f28: f28ff06f j 80003650 <_vfprintf_r+0x1fc0> -80003f2c: 006c8b33 add s6,s9,t1 -80003f30: 0a010b93 addi s7,sp,160 -80003f34: cc1ff06f j 80003bf4 <_vfprintf_r+0x2564> -80003f38: 00030463 beqz t1,80003f40 <_vfprintf_r+0x28b0> -80003f3c: 900fe06f j 8000203c <_vfprintf_r+0x9ac> -80003f40: 00100313 li t1,1 -80003f44: 8f8fe06f j 8000203c <_vfprintf_r+0x9ac> -80003f48: 00600313 li t1,6 -80003f4c: 8f0fe06f j 8000203c <_vfprintf_r+0x9ac> -80003f50: 06700a93 li s5,103 -80003f54: 04012583 lw a1,64(sp) -80003f58: 01812783 lw a5,24(sp) -80003f5c: 02012423 sw zero,40(sp) -80003f60: 0005c703 lbu a4,0(a1) -80003f64: 02012223 sw zero,36(sp) -80003f68: 0ff00613 li a2,255 -80003f6c: 02c70e63 beq a4,a2,80003fa8 <_vfprintf_r+0x2918> -80003f70: 02f75c63 bge a4,a5,80003fa8 <_vfprintf_r+0x2918> -80003f74: 0015c683 lbu a3,1(a1) -80003f78: 40e787b3 sub a5,a5,a4 -80003f7c: 00068e63 beqz a3,80003f98 <_vfprintf_r+0x2908> -80003f80: 02412703 lw a4,36(sp) -80003f84: 00158593 addi a1,a1,1 -80003f88: 00170713 addi a4,a4,1 -80003f8c: 02e12223 sw a4,36(sp) -80003f90: 00068713 mv a4,a3 -80003f94: fd9ff06f j 80003f6c <_vfprintf_r+0x28dc> -80003f98: 02812683 lw a3,40(sp) -80003f9c: 00168693 addi a3,a3,1 -80003fa0: 02d12423 sw a3,40(sp) -80003fa4: fc9ff06f j 80003f6c <_vfprintf_r+0x28dc> -80003fa8: 00f12c23 sw a5,24(sp) -80003fac: 02812703 lw a4,40(sp) -80003fb0: 02412783 lw a5,36(sp) -80003fb4: 04b12023 sw a1,64(sp) -80003fb8: 00e78733 add a4,a5,a4 -80003fbc: 04812783 lw a5,72(sp) -80003fc0: 02f70733 mul a4,a4,a5 -80003fc4: 01670b33 add s6,a4,s6 -80003fc8: fffb4993 not s3,s6 -80003fcc: 41f9d993 srai s3,s3,0x1f -80003fd0: 013b79b3 and s3,s6,s3 -80003fd4: a78fe06f j 8000224c <_vfprintf_r+0xbbc> -80003fd8: 02c12703 lw a4,44(sp) -80003fdc: 06600a93 li s5,102 -80003fe0: 00e78b33 add s6,a5,a4 -80003fe4: 006b0b33 add s6,s6,t1 -80003fe8: d55ff06f j 80003d3c <_vfprintf_r+0x26ac> -80003fec: 0d610693 addi a3,sp,214 -80003ff0: 00061863 bnez a2,80004000 <_vfprintf_r+0x2970> -80003ff4: 03000693 li a3,48 -80003ff8: 0cd10b23 sb a3,214(sp) -80003ffc: 0d710693 addi a3,sp,215 -80004000: 1b010793 addi a5,sp,432 -80004004: 40f68633 sub a2,a3,a5 -80004008: 03070713 addi a4,a4,48 -8000400c: 0dd60793 addi a5,a2,221 -80004010: 00e68023 sb a4,0(a3) -80004014: 02f12c23 sw a5,56(sp) -80004018: 9f0fe06f j 80002208 <_vfprintf_r+0xb78> -8000401c: 0b010993 addi s3,sp,176 -80004020: 00098513 mv a0,s3 -80004024: 04612a23 sw t1,84(sp) -80004028: 0a512823 sw t0,176(sp) -8000402c: 0be12a23 sw t5,180(sp) -80004030: 0bf12c23 sw t6,184(sp) -80004034: 0bd12e23 sw t4,188(sp) -80004038: 190100ef jal ra,800141c8 <__trunctfdf2> -8000403c: 0cc10613 addi a2,sp,204 -80004040: 0c4050ef jal ra,80009104 -80004044: 00058613 mv a2,a1 -80004048: 00050593 mv a1,a0 -8000404c: 00098513 mv a0,s3 -80004050: 76d0f0ef jal ra,80013fbc <__extenddftf2> -80004054: 0b012703 lw a4,176(sp) -80004058: 09010793 addi a5,sp,144 -8000405c: 0a010b93 addi s7,sp,160 -80004060: 08e12823 sw a4,144(sp) -80004064: 0b412703 lw a4,180(sp) -80004068: 08010613 addi a2,sp,128 -8000406c: 00078593 mv a1,a5 -80004070: 08e12a23 sw a4,148(sp) -80004074: 0b812703 lw a4,184(sp) -80004078: 000b8513 mv a0,s7 -8000407c: 00f12e23 sw a5,28(sp) -80004080: 08e12c23 sw a4,152(sp) -80004084: 0bc12703 lw a4,188(sp) -80004088: 04c12823 sw a2,80(sp) -8000408c: 08012023 sw zero,128(sp) -80004090: 08e12e23 sw a4,156(sp) -80004094: 3ffc0737 lui a4,0x3ffc0 -80004098: 08e12623 sw a4,140(sp) -8000409c: 08012223 sw zero,132(sp) -800040a0: 08012423 sw zero,136(sp) -800040a4: 7180d0ef jal ra,800117bc <__multf3> -800040a8: 0a012783 lw a5,160(sp) -800040ac: 0a412803 lw a6,164(sp) -800040b0: 0a812e83 lw t4,168(sp) -800040b4: 0ac12f03 lw t5,172(sp) -800040b8: 000b8593 mv a1,s7 -800040bc: 00098513 mv a0,s3 -800040c0: 0af12823 sw a5,176(sp) -800040c4: 04f12223 sw a5,68(sp) -800040c8: 0b012a23 sw a6,180(sp) -800040cc: 03012423 sw a6,40(sp) -800040d0: 0bd12c23 sw t4,184(sp) -800040d4: 03d12223 sw t4,36(sp) -800040d8: 0be12e23 sw t5,188(sp) -800040dc: 01e12c23 sw t5,24(sp) -800040e0: 0a012023 sw zero,160(sp) -800040e4: 0a012223 sw zero,164(sp) -800040e8: 0a012423 sw zero,168(sp) -800040ec: 0a012623 sw zero,172(sp) -800040f0: 3780d0ef jal ra,80011468 <__eqtf2> -800040f4: 01812f03 lw t5,24(sp) -800040f8: 02412e83 lw t4,36(sp) -800040fc: 02812803 lw a6,40(sp) -80004100: 04412783 lw a5,68(sp) -80004104: 05412303 lw t1,84(sp) -80004108: 00051663 bnez a0,80004114 <_vfprintf_r+0x2a84> -8000410c: 00100713 li a4,1 -80004110: 0ce12623 sw a4,204(sp) -80004114: 80014737 lui a4,0x80014 -80004118: 7e070713 addi a4,a4,2016 # 800147e0 <__BSS_END__+0xffffda68> -8000411c: 04e12223 sw a4,68(sp) -80004120: e88ff06f j 800037a8 <_vfprintf_r+0x2118> -80004124: 01812783 lw a5,24(sp) -80004128: 00100713 li a4,1 -8000412c: 02d00693 li a3,45 -80004130: 40f70733 sub a4,a4,a5 -80004134: 0cd10aa3 sb a3,213(sp) -80004138: 840fe06f j 80002178 <_vfprintf_r+0xae8> -8000413c: 05812783 lw a5,88(sp) -80004140: 0017f713 andi a4,a5,1 -80004144: 00071463 bnez a4,8000414c <_vfprintf_r+0x2abc> -80004148: 8e0fe06f j 80002228 <_vfprintf_r+0xb98> -8000414c: 8d4fe06f j 80002220 <_vfprintf_r+0xb90> -80004150: 00071a63 bnez a4,80004164 <_vfprintf_r+0x2ad4> -80004154: 00100993 li s3,1 -80004158: 06600a93 li s5,102 -8000415c: 00100b13 li s6,1 -80004160: 955ff06f j 80003ab4 <_vfprintf_r+0x2424> -80004164: 02c12783 lw a5,44(sp) -80004168: 06600a93 li s5,102 -8000416c: 00178b13 addi s6,a5,1 -80004170: 006b0b33 add s6,s6,t1 -80004174: fffb4993 not s3,s6 -80004178: 41f9d993 srai s3,s3,0x1f -8000417c: 013b79b3 and s3,s6,s3 -80004180: 935ff06f j 80003ab4 <_vfprintf_r+0x2424> -80004184: 000d0793 mv a5,s10 -80004188: ca5fe06f j 80002e2c <_vfprintf_r+0x179c> -8000418c: 01012703 lw a4,16(sp) -80004190: 00072d83 lw s11,0(a4) -80004194: 00470713 addi a4,a4,4 -80004198: 000dd463 bgez s11,800041a0 <_vfprintf_r+0x2b10> -8000419c: fff00d93 li s11,-1 -800041a0: 0014ce03 lbu t3,1(s1) -800041a4: 00e12823 sw a4,16(sp) -800041a8: 00078493 mv s1,a5 -800041ac: eb4fd06f j 80001860 <_vfprintf_r+0x1d0> -800041b0: 00090993 mv s3,s2 -800041b4: 8d0fe06f j 80002284 <_vfprintf_r+0xbf4> -800041b8: 00090993 mv s3,s2 -800041bc: addfd06f j 80001c98 <_vfprintf_r+0x608> -800041c0: 00200793 li a5,2 -800041c4: 02f12c23 sw a5,56(sp) -800041c8: 840fe06f j 80002208 <_vfprintf_r+0xb78> -800041cc: 00030b13 mv s6,t1 -800041d0: d1dff06f j 80003eec <_vfprintf_r+0x285c> -800041d4: 00412703 lw a4,4(sp) -800041d8: 00c75783 lhu a5,12(a4) -800041dc: 0407e793 ori a5,a5,64 -800041e0: 00f71623 sh a5,12(a4) -800041e4: f8cfd06f j 80001970 <_vfprintf_r+0x2e0> - -800041e8 : -800041e8: 00060693 mv a3,a2 -800041ec: 00058613 mv a2,a1 -800041f0: 00050593 mv a1,a0 -800041f4: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -800041f8: c98fd06f j 80001690 <_vfprintf_r> - -800041fc <__sbprintf>: -800041fc: 00c5d783 lhu a5,12(a1) -80004200: 0645ae03 lw t3,100(a1) -80004204: 00e5d303 lhu t1,14(a1) -80004208: 01c5a883 lw a7,28(a1) -8000420c: 0245a803 lw a6,36(a1) -80004210: b8010113 addi sp,sp,-1152 -80004214: ffd7f793 andi a5,a5,-3 -80004218: 40000713 li a4,1024 -8000421c: 46812c23 sw s0,1144(sp) -80004220: 00f11a23 sh a5,20(sp) -80004224: 00058413 mv s0,a1 -80004228: 07010793 addi a5,sp,112 -8000422c: 00810593 addi a1,sp,8 -80004230: 46912a23 sw s1,1140(sp) -80004234: 47212823 sw s2,1136(sp) -80004238: 46112e23 sw ra,1148(sp) -8000423c: 00050913 mv s2,a0 -80004240: 07c12623 sw t3,108(sp) -80004244: 00611b23 sh t1,22(sp) -80004248: 03112223 sw a7,36(sp) -8000424c: 03012623 sw a6,44(sp) -80004250: 00f12423 sw a5,8(sp) -80004254: 00f12c23 sw a5,24(sp) -80004258: 00e12823 sw a4,16(sp) -8000425c: 00e12e23 sw a4,28(sp) -80004260: 02012023 sw zero,32(sp) -80004264: c2cfd0ef jal ra,80001690 <_vfprintf_r> -80004268: 00050493 mv s1,a0 -8000426c: 02055c63 bgez a0,800042a4 <__sbprintf+0xa8> -80004270: 01415783 lhu a5,20(sp) -80004274: 0407f793 andi a5,a5,64 -80004278: 00078863 beqz a5,80004288 <__sbprintf+0x8c> -8000427c: 00c45783 lhu a5,12(s0) -80004280: 0407e793 ori a5,a5,64 -80004284: 00f41623 sh a5,12(s0) -80004288: 47c12083 lw ra,1148(sp) -8000428c: 47812403 lw s0,1144(sp) -80004290: 00048513 mv a0,s1 -80004294: 47012903 lw s2,1136(sp) -80004298: 47412483 lw s1,1140(sp) -8000429c: 48010113 addi sp,sp,1152 -800042a0: 00008067 ret -800042a4: 00810593 addi a1,sp,8 -800042a8: 00090513 mv a0,s2 -800042ac: 580000ef jal ra,8000482c <_fflush_r> -800042b0: fc0500e3 beqz a0,80004270 <__sbprintf+0x74> -800042b4: fff00493 li s1,-1 -800042b8: fb9ff06f j 80004270 <__sbprintf+0x74> - -800042bc <__swsetup_r>: -800042bc: 1c81a783 lw a5,456(gp) # 80016d30 <_impure_ptr> -800042c0: ff010113 addi sp,sp,-16 -800042c4: 00812423 sw s0,8(sp) -800042c8: 00912223 sw s1,4(sp) -800042cc: 00112623 sw ra,12(sp) -800042d0: 00050493 mv s1,a0 -800042d4: 00058413 mv s0,a1 -800042d8: 00078663 beqz a5,800042e4 <__swsetup_r+0x28> -800042dc: 0387a703 lw a4,56(a5) -800042e0: 08070663 beqz a4,8000436c <__swsetup_r+0xb0> -800042e4: 00c41703 lh a4,12(s0) -800042e8: 01071793 slli a5,a4,0x10 -800042ec: 0107d793 srli a5,a5,0x10 -800042f0: 0087f693 andi a3,a5,8 -800042f4: 08068a63 beqz a3,80004388 <__swsetup_r+0xcc> -800042f8: 01042683 lw a3,16(s0) -800042fc: 0a068a63 beqz a3,800043b0 <__swsetup_r+0xf4> -80004300: 0017f713 andi a4,a5,1 -80004304: 02070863 beqz a4,80004334 <__swsetup_r+0x78> -80004308: 01442783 lw a5,20(s0) -8000430c: 00042423 sw zero,8(s0) -80004310: 00000513 li a0,0 -80004314: 40f007b3 neg a5,a5 -80004318: 00f42c23 sw a5,24(s0) -8000431c: 02068a63 beqz a3,80004350 <__swsetup_r+0x94> -80004320: 00c12083 lw ra,12(sp) -80004324: 00812403 lw s0,8(sp) -80004328: 00412483 lw s1,4(sp) -8000432c: 01010113 addi sp,sp,16 -80004330: 00008067 ret -80004334: 0027f793 andi a5,a5,2 -80004338: 00000713 li a4,0 -8000433c: 00079463 bnez a5,80004344 <__swsetup_r+0x88> -80004340: 01442703 lw a4,20(s0) -80004344: 00e42423 sw a4,8(s0) -80004348: 00000513 li a0,0 -8000434c: fc069ae3 bnez a3,80004320 <__swsetup_r+0x64> -80004350: 00c41783 lh a5,12(s0) -80004354: 0807f713 andi a4,a5,128 -80004358: fc0704e3 beqz a4,80004320 <__swsetup_r+0x64> -8000435c: 0407e793 ori a5,a5,64 -80004360: 00f41623 sh a5,12(s0) -80004364: fff00513 li a0,-1 -80004368: fb9ff06f j 80004320 <__swsetup_r+0x64> -8000436c: 00078513 mv a0,a5 -80004370: 059000ef jal ra,80004bc8 <__sinit> -80004374: 00c41703 lh a4,12(s0) -80004378: 01071793 slli a5,a4,0x10 -8000437c: 0107d793 srli a5,a5,0x10 -80004380: 0087f693 andi a3,a5,8 -80004384: f6069ae3 bnez a3,800042f8 <__swsetup_r+0x3c> -80004388: 0107f693 andi a3,a5,16 -8000438c: 06068e63 beqz a3,80004408 <__swsetup_r+0x14c> -80004390: 0047f793 andi a5,a5,4 -80004394: 04079063 bnez a5,800043d4 <__swsetup_r+0x118> -80004398: 01042683 lw a3,16(s0) -8000439c: 00876793 ori a5,a4,8 -800043a0: 00f41623 sh a5,12(s0) -800043a4: 01079793 slli a5,a5,0x10 -800043a8: 0107d793 srli a5,a5,0x10 -800043ac: f4069ae3 bnez a3,80004300 <__swsetup_r+0x44> -800043b0: 2807f713 andi a4,a5,640 -800043b4: 20000613 li a2,512 -800043b8: f4c704e3 beq a4,a2,80004300 <__swsetup_r+0x44> -800043bc: 00040593 mv a1,s0 -800043c0: 00048513 mv a0,s1 -800043c4: 2d9030ef jal ra,80007e9c <__smakebuf_r> -800043c8: 00c45783 lhu a5,12(s0) -800043cc: 01042683 lw a3,16(s0) -800043d0: f31ff06f j 80004300 <__swsetup_r+0x44> -800043d4: 03042583 lw a1,48(s0) -800043d8: 00058e63 beqz a1,800043f4 <__swsetup_r+0x138> -800043dc: 04040793 addi a5,s0,64 -800043e0: 00f58863 beq a1,a5,800043f0 <__swsetup_r+0x134> -800043e4: 00048513 mv a0,s1 -800043e8: 141000ef jal ra,80004d28 <_free_r> -800043ec: 00c41703 lh a4,12(s0) -800043f0: 02042823 sw zero,48(s0) -800043f4: 01042683 lw a3,16(s0) -800043f8: fdb77713 andi a4,a4,-37 -800043fc: 00042223 sw zero,4(s0) -80004400: 00d42023 sw a3,0(s0) -80004404: f99ff06f j 8000439c <__swsetup_r+0xe0> -80004408: 00900793 li a5,9 -8000440c: 00f4a023 sw a5,0(s1) -80004410: 04076713 ori a4,a4,64 -80004414: 00e41623 sh a4,12(s0) -80004418: fff00513 li a0,-1 -8000441c: f05ff06f j 80004320 <__swsetup_r+0x64> - -80004420 <__register_exitproc>: -80004420: 1b81a703 lw a4,440(gp) # 80016d20 <_global_impure_ptr> -80004424: 14872783 lw a5,328(a4) -80004428: 04078c63 beqz a5,80004480 <__register_exitproc+0x60> -8000442c: 0047a703 lw a4,4(a5) -80004430: 01f00813 li a6,31 -80004434: 06e84e63 blt a6,a4,800044b0 <__register_exitproc+0x90> -80004438: 00271813 slli a6,a4,0x2 -8000443c: 02050663 beqz a0,80004468 <__register_exitproc+0x48> -80004440: 01078333 add t1,a5,a6 -80004444: 08c32423 sw a2,136(t1) -80004448: 1887a883 lw a7,392(a5) -8000444c: 00100613 li a2,1 -80004450: 00e61633 sll a2,a2,a4 -80004454: 00c8e8b3 or a7,a7,a2 -80004458: 1917a423 sw a7,392(a5) -8000445c: 10d32423 sw a3,264(t1) -80004460: 00200693 li a3,2 -80004464: 02d50463 beq a0,a3,8000448c <__register_exitproc+0x6c> -80004468: 00170713 addi a4,a4,1 -8000446c: 00e7a223 sw a4,4(a5) -80004470: 010787b3 add a5,a5,a6 -80004474: 00b7a423 sw a1,8(a5) -80004478: 00000513 li a0,0 -8000447c: 00008067 ret -80004480: 14c70793 addi a5,a4,332 -80004484: 14f72423 sw a5,328(a4) -80004488: fa5ff06f j 8000442c <__register_exitproc+0xc> -8000448c: 18c7a683 lw a3,396(a5) -80004490: 00170713 addi a4,a4,1 -80004494: 00e7a223 sw a4,4(a5) -80004498: 00c6e633 or a2,a3,a2 -8000449c: 18c7a623 sw a2,396(a5) -800044a0: 010787b3 add a5,a5,a6 -800044a4: 00b7a423 sw a1,8(a5) -800044a8: 00000513 li a0,0 -800044ac: 00008067 ret -800044b0: fff00513 li a0,-1 -800044b4: 00008067 ret - -800044b8 <__call_exitprocs>: -800044b8: fd010113 addi sp,sp,-48 -800044bc: 01812423 sw s8,8(sp) -800044c0: 1b81ac03 lw s8,440(gp) # 80016d20 <_global_impure_ptr> -800044c4: 01312e23 sw s3,28(sp) -800044c8: 01412c23 sw s4,24(sp) -800044cc: 01512a23 sw s5,20(sp) -800044d0: 01612823 sw s6,16(sp) -800044d4: 02112623 sw ra,44(sp) -800044d8: 02812423 sw s0,40(sp) -800044dc: 02912223 sw s1,36(sp) -800044e0: 03212023 sw s2,32(sp) -800044e4: 01712623 sw s7,12(sp) -800044e8: 00050a93 mv s5,a0 -800044ec: 00058b13 mv s6,a1 -800044f0: 00100a13 li s4,1 -800044f4: fff00993 li s3,-1 -800044f8: 148c2903 lw s2,328(s8) -800044fc: 02090863 beqz s2,8000452c <__call_exitprocs+0x74> -80004500: 00492483 lw s1,4(s2) -80004504: fff48413 addi s0,s1,-1 -80004508: 02044263 bltz s0,8000452c <__call_exitprocs+0x74> -8000450c: 00249493 slli s1,s1,0x2 -80004510: 009904b3 add s1,s2,s1 -80004514: 040b0463 beqz s6,8000455c <__call_exitprocs+0xa4> -80004518: 1044a783 lw a5,260(s1) -8000451c: 05678063 beq a5,s6,8000455c <__call_exitprocs+0xa4> -80004520: fff40413 addi s0,s0,-1 -80004524: ffc48493 addi s1,s1,-4 -80004528: ff3416e3 bne s0,s3,80004514 <__call_exitprocs+0x5c> -8000452c: 02c12083 lw ra,44(sp) -80004530: 02812403 lw s0,40(sp) -80004534: 02412483 lw s1,36(sp) -80004538: 02012903 lw s2,32(sp) -8000453c: 01c12983 lw s3,28(sp) -80004540: 01812a03 lw s4,24(sp) -80004544: 01412a83 lw s5,20(sp) -80004548: 01012b03 lw s6,16(sp) -8000454c: 00c12b83 lw s7,12(sp) -80004550: 00812c03 lw s8,8(sp) -80004554: 03010113 addi sp,sp,48 -80004558: 00008067 ret -8000455c: 00492783 lw a5,4(s2) -80004560: 0044a683 lw a3,4(s1) -80004564: fff78793 addi a5,a5,-1 -80004568: 04878a63 beq a5,s0,800045bc <__call_exitprocs+0x104> -8000456c: 0004a223 sw zero,4(s1) -80004570: fa0688e3 beqz a3,80004520 <__call_exitprocs+0x68> -80004574: 18892783 lw a5,392(s2) -80004578: 008a1733 sll a4,s4,s0 -8000457c: 00492b83 lw s7,4(s2) -80004580: 00f777b3 and a5,a4,a5 -80004584: 00079e63 bnez a5,800045a0 <__call_exitprocs+0xe8> -80004588: 000680e7 jalr a3 -8000458c: 00492783 lw a5,4(s2) -80004590: f77794e3 bne a5,s7,800044f8 <__call_exitprocs+0x40> -80004594: 148c2783 lw a5,328(s8) -80004598: f92784e3 beq a5,s2,80004520 <__call_exitprocs+0x68> -8000459c: f5dff06f j 800044f8 <__call_exitprocs+0x40> -800045a0: 18c92783 lw a5,396(s2) -800045a4: 0844a583 lw a1,132(s1) -800045a8: 00f77733 and a4,a4,a5 -800045ac: 00071c63 bnez a4,800045c4 <__call_exitprocs+0x10c> -800045b0: 000a8513 mv a0,s5 -800045b4: 000680e7 jalr a3 -800045b8: fd5ff06f j 8000458c <__call_exitprocs+0xd4> -800045bc: 00892223 sw s0,4(s2) -800045c0: fb1ff06f j 80004570 <__call_exitprocs+0xb8> -800045c4: 00058513 mv a0,a1 -800045c8: 000680e7 jalr a3 -800045cc: fc1ff06f j 8000458c <__call_exitprocs+0xd4> - -800045d0 <__sflush_r>: -800045d0: 00c59783 lh a5,12(a1) -800045d4: fe010113 addi sp,sp,-32 -800045d8: 00812c23 sw s0,24(sp) -800045dc: 01079713 slli a4,a5,0x10 -800045e0: 01075713 srli a4,a4,0x10 -800045e4: 01312623 sw s3,12(sp) -800045e8: 00112e23 sw ra,28(sp) -800045ec: 00912a23 sw s1,20(sp) -800045f0: 01212823 sw s2,16(sp) -800045f4: 00877693 andi a3,a4,8 -800045f8: 00058413 mv s0,a1 -800045fc: 00050993 mv s3,a0 -80004600: 10069a63 bnez a3,80004714 <__sflush_r+0x144> -80004604: 00001737 lui a4,0x1 -80004608: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> -8000460c: 0045a683 lw a3,4(a1) -80004610: 00e7e7b3 or a5,a5,a4 -80004614: 00f59623 sh a5,12(a1) -80004618: 18d05063 blez a3,80004798 <__sflush_r+0x1c8> -8000461c: 02842703 lw a4,40(s0) -80004620: 0c070a63 beqz a4,800046f4 <__sflush_r+0x124> -80004624: 01079793 slli a5,a5,0x10 -80004628: 0107d793 srli a5,a5,0x10 -8000462c: 0009a483 lw s1,0(s3) -80004630: 01379693 slli a3,a5,0x13 -80004634: 0009a023 sw zero,0(s3) -80004638: 01c42583 lw a1,28(s0) -8000463c: 1606c463 bltz a3,800047a4 <__sflush_r+0x1d4> -80004640: 00100693 li a3,1 -80004644: 00000613 li a2,0 -80004648: 00098513 mv a0,s3 -8000464c: 000700e7 jalr a4 -80004650: fff00793 li a5,-1 -80004654: 18f50863 beq a0,a5,800047e4 <__sflush_r+0x214> -80004658: 00c45783 lhu a5,12(s0) -8000465c: 02842703 lw a4,40(s0) -80004660: 01c42583 lw a1,28(s0) -80004664: 0047f793 andi a5,a5,4 -80004668: 00078e63 beqz a5,80004684 <__sflush_r+0xb4> -8000466c: 00442683 lw a3,4(s0) -80004670: 03042783 lw a5,48(s0) -80004674: 40d50533 sub a0,a0,a3 -80004678: 00078663 beqz a5,80004684 <__sflush_r+0xb4> -8000467c: 03c42783 lw a5,60(s0) -80004680: 40f50533 sub a0,a0,a5 -80004684: 00050613 mv a2,a0 -80004688: 00000693 li a3,0 -8000468c: 00098513 mv a0,s3 -80004690: 000700e7 jalr a4 -80004694: fff00793 li a5,-1 -80004698: 10f51a63 bne a0,a5,800047ac <__sflush_r+0x1dc> -8000469c: 0009a703 lw a4,0(s3) -800046a0: 00c41783 lh a5,12(s0) -800046a4: 16070463 beqz a4,8000480c <__sflush_r+0x23c> -800046a8: 01d00693 li a3,29 -800046ac: 00d70663 beq a4,a3,800046b8 <__sflush_r+0xe8> -800046b0: 01600693 li a3,22 -800046b4: 0cd71063 bne a4,a3,80004774 <__sflush_r+0x1a4> -800046b8: 01042683 lw a3,16(s0) -800046bc: fffff737 lui a4,0xfffff -800046c0: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8a87> -800046c4: 00e7f7b3 and a5,a5,a4 -800046c8: 00f41623 sh a5,12(s0) -800046cc: 00042223 sw zero,4(s0) -800046d0: 00d42023 sw a3,0(s0) -800046d4: 03042583 lw a1,48(s0) -800046d8: 0099a023 sw s1,0(s3) -800046dc: 00058c63 beqz a1,800046f4 <__sflush_r+0x124> -800046e0: 04040793 addi a5,s0,64 -800046e4: 00f58663 beq a1,a5,800046f0 <__sflush_r+0x120> -800046e8: 00098513 mv a0,s3 -800046ec: 63c000ef jal ra,80004d28 <_free_r> -800046f0: 02042823 sw zero,48(s0) -800046f4: 00000513 li a0,0 -800046f8: 01c12083 lw ra,28(sp) -800046fc: 01812403 lw s0,24(sp) -80004700: 01412483 lw s1,20(sp) -80004704: 01012903 lw s2,16(sp) -80004708: 00c12983 lw s3,12(sp) -8000470c: 02010113 addi sp,sp,32 -80004710: 00008067 ret -80004714: 0105a903 lw s2,16(a1) -80004718: fc090ee3 beqz s2,800046f4 <__sflush_r+0x124> -8000471c: 0005a483 lw s1,0(a1) -80004720: 00377713 andi a4,a4,3 -80004724: 0125a023 sw s2,0(a1) -80004728: 412484b3 sub s1,s1,s2 -8000472c: 00000793 li a5,0 -80004730: 00071463 bnez a4,80004738 <__sflush_r+0x168> -80004734: 0145a783 lw a5,20(a1) -80004738: 00f42423 sw a5,8(s0) -8000473c: 00904863 bgtz s1,8000474c <__sflush_r+0x17c> -80004740: fb5ff06f j 800046f4 <__sflush_r+0x124> -80004744: 00a90933 add s2,s2,a0 -80004748: fa9056e3 blez s1,800046f4 <__sflush_r+0x124> -8000474c: 02442783 lw a5,36(s0) -80004750: 01c42583 lw a1,28(s0) -80004754: 00048693 mv a3,s1 -80004758: 00090613 mv a2,s2 -8000475c: 00098513 mv a0,s3 -80004760: 000780e7 jalr a5 -80004764: 40a484b3 sub s1,s1,a0 -80004768: fca04ee3 bgtz a0,80004744 <__sflush_r+0x174> -8000476c: 00c45783 lhu a5,12(s0) -80004770: fff00513 li a0,-1 -80004774: 0407e793 ori a5,a5,64 -80004778: 00f41623 sh a5,12(s0) -8000477c: 01c12083 lw ra,28(sp) -80004780: 01812403 lw s0,24(sp) -80004784: 01412483 lw s1,20(sp) -80004788: 01012903 lw s2,16(sp) -8000478c: 00c12983 lw s3,12(sp) -80004790: 02010113 addi sp,sp,32 -80004794: 00008067 ret -80004798: 03c5a703 lw a4,60(a1) -8000479c: e8e040e3 bgtz a4,8000461c <__sflush_r+0x4c> -800047a0: f55ff06f j 800046f4 <__sflush_r+0x124> -800047a4: 05042503 lw a0,80(s0) -800047a8: ebdff06f j 80004664 <__sflush_r+0x94> -800047ac: 00c45783 lhu a5,12(s0) -800047b0: fffff737 lui a4,0xfffff -800047b4: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8a87> -800047b8: 00e7f7b3 and a5,a5,a4 -800047bc: 01042683 lw a3,16(s0) -800047c0: 01079793 slli a5,a5,0x10 -800047c4: 4107d793 srai a5,a5,0x10 -800047c8: 00f41623 sh a5,12(s0) -800047cc: 00042223 sw zero,4(s0) -800047d0: 00d42023 sw a3,0(s0) -800047d4: 01379713 slli a4,a5,0x13 -800047d8: ee075ee3 bgez a4,800046d4 <__sflush_r+0x104> -800047dc: 04a42823 sw a0,80(s0) -800047e0: ef5ff06f j 800046d4 <__sflush_r+0x104> -800047e4: 0009a783 lw a5,0(s3) -800047e8: e60788e3 beqz a5,80004658 <__sflush_r+0x88> -800047ec: 01d00713 li a4,29 -800047f0: 02e78863 beq a5,a4,80004820 <__sflush_r+0x250> -800047f4: 01600713 li a4,22 -800047f8: 02e78463 beq a5,a4,80004820 <__sflush_r+0x250> -800047fc: 00c45783 lhu a5,12(s0) -80004800: 0407e793 ori a5,a5,64 -80004804: 00f41623 sh a5,12(s0) -80004808: ef1ff06f j 800046f8 <__sflush_r+0x128> -8000480c: fffff737 lui a4,0xfffff -80004810: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8a87> -80004814: 01042683 lw a3,16(s0) -80004818: 00e7f7b3 and a5,a5,a4 -8000481c: fadff06f j 800047c8 <__sflush_r+0x1f8> -80004820: 0099a023 sw s1,0(s3) -80004824: 00000513 li a0,0 -80004828: ed1ff06f j 800046f8 <__sflush_r+0x128> - -8000482c <_fflush_r>: -8000482c: fe010113 addi sp,sp,-32 -80004830: 00812c23 sw s0,24(sp) -80004834: 00112e23 sw ra,28(sp) -80004838: 00050413 mv s0,a0 -8000483c: 00050663 beqz a0,80004848 <_fflush_r+0x1c> -80004840: 03852783 lw a5,56(a0) -80004844: 02078063 beqz a5,80004864 <_fflush_r+0x38> -80004848: 00c59783 lh a5,12(a1) -8000484c: 02079663 bnez a5,80004878 <_fflush_r+0x4c> -80004850: 01c12083 lw ra,28(sp) -80004854: 01812403 lw s0,24(sp) -80004858: 00000513 li a0,0 -8000485c: 02010113 addi sp,sp,32 -80004860: 00008067 ret -80004864: 00b12623 sw a1,12(sp) -80004868: 360000ef jal ra,80004bc8 <__sinit> -8000486c: 00c12583 lw a1,12(sp) -80004870: 00c59783 lh a5,12(a1) -80004874: fc078ee3 beqz a5,80004850 <_fflush_r+0x24> -80004878: 00040513 mv a0,s0 -8000487c: 01812403 lw s0,24(sp) -80004880: 01c12083 lw ra,28(sp) -80004884: 02010113 addi sp,sp,32 -80004888: d49ff06f j 800045d0 <__sflush_r> - -8000488c : -8000488c: 00050593 mv a1,a0 -80004890: 00050663 beqz a0,8000489c -80004894: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -80004898: f95ff06f j 8000482c <_fflush_r> -8000489c: 1b81a503 lw a0,440(gp) # 80016d20 <_global_impure_ptr> -800048a0: 800055b7 lui a1,0x80005 -800048a4: 82c58593 addi a1,a1,-2004 # 8000482c <__BSS_END__+0xfffedab4> -800048a8: 0210006f j 800050c8 <_fwalk_reent> - -800048ac <__fp_lock>: -800048ac: 00000513 li a0,0 -800048b0: 00008067 ret - -800048b4 <_cleanup_r>: -800048b4: 8000e5b7 lui a1,0x8000e -800048b8: 8b858593 addi a1,a1,-1864 # 8000d8b8 <__BSS_END__+0xffff6b40> -800048bc: 00d0006f j 800050c8 <_fwalk_reent> - -800048c0 <__sinit.part.0>: -800048c0: fe010113 addi sp,sp,-32 -800048c4: 800057b7 lui a5,0x80005 -800048c8: 00112e23 sw ra,28(sp) -800048cc: 00812c23 sw s0,24(sp) -800048d0: 00912a23 sw s1,20(sp) -800048d4: 01212823 sw s2,16(sp) -800048d8: 01312623 sw s3,12(sp) -800048dc: 01412423 sw s4,8(sp) -800048e0: 01512223 sw s5,4(sp) -800048e4: 01612023 sw s6,0(sp) -800048e8: 00452403 lw s0,4(a0) -800048ec: 8b478793 addi a5,a5,-1868 # 800048b4 <__BSS_END__+0xfffedb3c> -800048f0: 02f52e23 sw a5,60(a0) -800048f4: 2ec50713 addi a4,a0,748 -800048f8: 00300793 li a5,3 -800048fc: 2ee52423 sw a4,744(a0) -80004900: 2ef52223 sw a5,740(a0) -80004904: 2e052023 sw zero,736(a0) -80004908: 00400793 li a5,4 -8000490c: 00050913 mv s2,a0 -80004910: 00f42623 sw a5,12(s0) -80004914: 00800613 li a2,8 -80004918: 00000593 li a1,0 -8000491c: 06042223 sw zero,100(s0) -80004920: 00042023 sw zero,0(s0) -80004924: 00042223 sw zero,4(s0) -80004928: 00042423 sw zero,8(s0) -8000492c: 00042823 sw zero,16(s0) -80004930: 00042a23 sw zero,20(s0) -80004934: 00042c23 sw zero,24(s0) -80004938: 05c40513 addi a0,s0,92 -8000493c: b81fc0ef jal ra,800014bc -80004940: 80009b37 lui s6,0x80009 -80004944: 00892483 lw s1,8(s2) -80004948: 80009ab7 lui s5,0x80009 -8000494c: 80009a37 lui s4,0x80009 -80004950: 800099b7 lui s3,0x80009 -80004954: 294b0b13 addi s6,s6,660 # 80009294 <__BSS_END__+0xffff251c> -80004958: 2f8a8a93 addi s5,s5,760 # 800092f8 <__BSS_END__+0xffff2580> -8000495c: 380a0a13 addi s4,s4,896 # 80009380 <__BSS_END__+0xffff2608> -80004960: 3e898993 addi s3,s3,1000 # 800093e8 <__BSS_END__+0xffff2670> -80004964: 000107b7 lui a5,0x10 -80004968: 03642023 sw s6,32(s0) -8000496c: 03542223 sw s5,36(s0) -80004970: 03442423 sw s4,40(s0) -80004974: 03342623 sw s3,44(s0) -80004978: 00842e23 sw s0,28(s0) -8000497c: 00978793 addi a5,a5,9 # 10009 <_start-0x7ffefff7> -80004980: 00f4a623 sw a5,12(s1) -80004984: 00800613 li a2,8 -80004988: 00000593 li a1,0 -8000498c: 0604a223 sw zero,100(s1) -80004990: 0004a023 sw zero,0(s1) -80004994: 0004a223 sw zero,4(s1) -80004998: 0004a423 sw zero,8(s1) -8000499c: 0004a823 sw zero,16(s1) -800049a0: 0004aa23 sw zero,20(s1) -800049a4: 0004ac23 sw zero,24(s1) -800049a8: 05c48513 addi a0,s1,92 -800049ac: b11fc0ef jal ra,800014bc -800049b0: 00c92403 lw s0,12(s2) -800049b4: 000207b7 lui a5,0x20 -800049b8: 0364a023 sw s6,32(s1) -800049bc: 0354a223 sw s5,36(s1) -800049c0: 0344a423 sw s4,40(s1) -800049c4: 0334a623 sw s3,44(s1) -800049c8: 0094ae23 sw s1,28(s1) -800049cc: 01278793 addi a5,a5,18 # 20012 <_start-0x7ffdffee> -800049d0: 00f42623 sw a5,12(s0) -800049d4: 06042223 sw zero,100(s0) -800049d8: 00042023 sw zero,0(s0) -800049dc: 00042223 sw zero,4(s0) -800049e0: 00042423 sw zero,8(s0) -800049e4: 00042823 sw zero,16(s0) -800049e8: 00042a23 sw zero,20(s0) -800049ec: 00042c23 sw zero,24(s0) -800049f0: 05c40513 addi a0,s0,92 -800049f4: 00800613 li a2,8 -800049f8: 00000593 li a1,0 -800049fc: ac1fc0ef jal ra,800014bc -80004a00: 01c12083 lw ra,28(sp) -80004a04: 03642023 sw s6,32(s0) -80004a08: 03542223 sw s5,36(s0) -80004a0c: 03442423 sw s4,40(s0) -80004a10: 03342623 sw s3,44(s0) -80004a14: 00842e23 sw s0,28(s0) -80004a18: 01812403 lw s0,24(sp) -80004a1c: 00100793 li a5,1 -80004a20: 02f92c23 sw a5,56(s2) -80004a24: 01412483 lw s1,20(sp) -80004a28: 01012903 lw s2,16(sp) -80004a2c: 00c12983 lw s3,12(sp) -80004a30: 00812a03 lw s4,8(sp) -80004a34: 00412a83 lw s5,4(sp) -80004a38: 00012b03 lw s6,0(sp) -80004a3c: 02010113 addi sp,sp,32 -80004a40: 00008067 ret - -80004a44 <__fp_unlock>: -80004a44: 00000513 li a0,0 -80004a48: 00008067 ret - -80004a4c <__sfmoreglue>: -80004a4c: ff010113 addi sp,sp,-16 -80004a50: 00912223 sw s1,4(sp) -80004a54: 06800613 li a2,104 -80004a58: fff58493 addi s1,a1,-1 -80004a5c: 02c484b3 mul s1,s1,a2 -80004a60: 01212023 sw s2,0(sp) -80004a64: 00058913 mv s2,a1 -80004a68: 00812423 sw s0,8(sp) -80004a6c: 00112623 sw ra,12(sp) -80004a70: 07448593 addi a1,s1,116 -80004a74: a8cfc0ef jal ra,80000d00 <_malloc_r> -80004a78: 00050413 mv s0,a0 -80004a7c: 02050063 beqz a0,80004a9c <__sfmoreglue+0x50> -80004a80: 00c50513 addi a0,a0,12 -80004a84: 00042023 sw zero,0(s0) -80004a88: 01242223 sw s2,4(s0) -80004a8c: 00a42423 sw a0,8(s0) -80004a90: 06848613 addi a2,s1,104 -80004a94: 00000593 li a1,0 -80004a98: a25fc0ef jal ra,800014bc -80004a9c: 00040513 mv a0,s0 -80004aa0: 00c12083 lw ra,12(sp) -80004aa4: 00812403 lw s0,8(sp) -80004aa8: 00412483 lw s1,4(sp) -80004aac: 00012903 lw s2,0(sp) -80004ab0: 01010113 addi sp,sp,16 -80004ab4: 00008067 ret - -80004ab8 <__sfp>: -80004ab8: fe010113 addi sp,sp,-32 -80004abc: 01212823 sw s2,16(sp) -80004ac0: 1b81a903 lw s2,440(gp) # 80016d20 <_global_impure_ptr> -80004ac4: 01312623 sw s3,12(sp) -80004ac8: 00112e23 sw ra,28(sp) -80004acc: 03892783 lw a5,56(s2) -80004ad0: 00812c23 sw s0,24(sp) -80004ad4: 00912a23 sw s1,20(sp) -80004ad8: 00050993 mv s3,a0 -80004adc: 0a078663 beqz a5,80004b88 <__sfp+0xd0> -80004ae0: 2e090913 addi s2,s2,736 -80004ae4: fff00493 li s1,-1 -80004ae8: 00492783 lw a5,4(s2) -80004aec: 00892403 lw s0,8(s2) -80004af0: fff78793 addi a5,a5,-1 -80004af4: 0007da63 bgez a5,80004b08 <__sfp+0x50> -80004af8: 0800006f j 80004b78 <__sfp+0xc0> -80004afc: fff78793 addi a5,a5,-1 -80004b00: 06840413 addi s0,s0,104 -80004b04: 06978a63 beq a5,s1,80004b78 <__sfp+0xc0> -80004b08: 00c41703 lh a4,12(s0) -80004b0c: fe0718e3 bnez a4,80004afc <__sfp+0x44> -80004b10: ffff07b7 lui a5,0xffff0 -80004b14: 00178793 addi a5,a5,1 # ffff0001 <__BSS_END__+0x7ffd9289> -80004b18: 06042223 sw zero,100(s0) -80004b1c: 00042023 sw zero,0(s0) -80004b20: 00042223 sw zero,4(s0) -80004b24: 00042423 sw zero,8(s0) -80004b28: 00f42623 sw a5,12(s0) -80004b2c: 00042823 sw zero,16(s0) -80004b30: 00042a23 sw zero,20(s0) -80004b34: 00042c23 sw zero,24(s0) -80004b38: 00800613 li a2,8 -80004b3c: 00000593 li a1,0 -80004b40: 05c40513 addi a0,s0,92 -80004b44: 979fc0ef jal ra,800014bc -80004b48: 02042823 sw zero,48(s0) -80004b4c: 02042a23 sw zero,52(s0) -80004b50: 04042223 sw zero,68(s0) -80004b54: 04042423 sw zero,72(s0) -80004b58: 00040513 mv a0,s0 -80004b5c: 01c12083 lw ra,28(sp) -80004b60: 01812403 lw s0,24(sp) -80004b64: 01412483 lw s1,20(sp) -80004b68: 01012903 lw s2,16(sp) -80004b6c: 00c12983 lw s3,12(sp) -80004b70: 02010113 addi sp,sp,32 -80004b74: 00008067 ret -80004b78: 00092403 lw s0,0(s2) -80004b7c: 00040c63 beqz s0,80004b94 <__sfp+0xdc> -80004b80: 00040913 mv s2,s0 -80004b84: f65ff06f j 80004ae8 <__sfp+0x30> -80004b88: 00090513 mv a0,s2 -80004b8c: d35ff0ef jal ra,800048c0 <__sinit.part.0> -80004b90: f51ff06f j 80004ae0 <__sfp+0x28> -80004b94: 00400593 li a1,4 -80004b98: 00098513 mv a0,s3 -80004b9c: eb1ff0ef jal ra,80004a4c <__sfmoreglue> -80004ba0: 00a92023 sw a0,0(s2) -80004ba4: 00050413 mv s0,a0 -80004ba8: fc051ce3 bnez a0,80004b80 <__sfp+0xc8> -80004bac: 00c00793 li a5,12 -80004bb0: 00f9a023 sw a5,0(s3) -80004bb4: fa5ff06f j 80004b58 <__sfp+0xa0> - -80004bb8 <_cleanup>: -80004bb8: 1b81a503 lw a0,440(gp) # 80016d20 <_global_impure_ptr> -80004bbc: 8000e5b7 lui a1,0x8000e -80004bc0: 8b858593 addi a1,a1,-1864 # 8000d8b8 <__BSS_END__+0xffff6b40> -80004bc4: 5040006f j 800050c8 <_fwalk_reent> - -80004bc8 <__sinit>: -80004bc8: 03852783 lw a5,56(a0) -80004bcc: 00078463 beqz a5,80004bd4 <__sinit+0xc> -80004bd0: 00008067 ret -80004bd4: cedff06f j 800048c0 <__sinit.part.0> - -80004bd8 <__sfp_lock_acquire>: -80004bd8: 00008067 ret - -80004bdc <__sfp_lock_release>: -80004bdc: 00008067 ret - -80004be0 <__sinit_lock_acquire>: -80004be0: 00008067 ret - -80004be4 <__sinit_lock_release>: -80004be4: 00008067 ret - -80004be8 <__fp_lock_all>: -80004be8: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -80004bec: 800055b7 lui a1,0x80005 -80004bf0: 8ac58593 addi a1,a1,-1876 # 800048ac <__BSS_END__+0xfffedb34> -80004bf4: 4240006f j 80005018 <_fwalk> - -80004bf8 <__fp_unlock_all>: -80004bf8: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -80004bfc: 800055b7 lui a1,0x80005 -80004c00: a4458593 addi a1,a1,-1468 # 80004a44 <__BSS_END__+0xfffedccc> -80004c04: 4140006f j 80005018 <_fwalk> - -80004c08 <_malloc_trim_r>: -80004c08: fe010113 addi sp,sp,-32 -80004c0c: 01212823 sw s2,16(sp) -80004c10: 00812c23 sw s0,24(sp) -80004c14: 00912a23 sw s1,20(sp) -80004c18: 01312623 sw s3,12(sp) -80004c1c: 00058413 mv s0,a1 -80004c20: 00112e23 sw ra,28(sp) -80004c24: 00050993 mv s3,a0 -80004c28: c2818913 addi s2,gp,-984 # 80016790 <__malloc_av_> -80004c2c: 96dfc0ef jal ra,80001598 <__malloc_lock> -80004c30: 00892683 lw a3,8(s2) -80004c34: 00001737 lui a4,0x1 -80004c38: fef70793 addi a5,a4,-17 # fef <_start-0x7ffff011> -80004c3c: 0046a483 lw s1,4(a3) -80004c40: 40878433 sub s0,a5,s0 -80004c44: ffc4f493 andi s1,s1,-4 -80004c48: 00940433 add s0,s0,s1 -80004c4c: 00c45413 srli s0,s0,0xc -80004c50: fff40413 addi s0,s0,-1 -80004c54: 00c41413 slli s0,s0,0xc -80004c58: 00e44e63 blt s0,a4,80004c74 <_malloc_trim_r+0x6c> -80004c5c: 00000593 li a1,0 -80004c60: 00098513 mv a0,s3 -80004c64: 9d1fc0ef jal ra,80001634 <_sbrk_r> -80004c68: 00892783 lw a5,8(s2) -80004c6c: 009787b3 add a5,a5,s1 -80004c70: 02f50663 beq a0,a5,80004c9c <_malloc_trim_r+0x94> -80004c74: 00098513 mv a0,s3 -80004c78: 925fc0ef jal ra,8000159c <__malloc_unlock> -80004c7c: 01c12083 lw ra,28(sp) -80004c80: 01812403 lw s0,24(sp) -80004c84: 01412483 lw s1,20(sp) -80004c88: 01012903 lw s2,16(sp) -80004c8c: 00c12983 lw s3,12(sp) -80004c90: 00000513 li a0,0 -80004c94: 02010113 addi sp,sp,32 -80004c98: 00008067 ret -80004c9c: 408005b3 neg a1,s0 -80004ca0: 00098513 mv a0,s3 -80004ca4: 991fc0ef jal ra,80001634 <_sbrk_r> -80004ca8: fff00793 li a5,-1 -80004cac: 04f50463 beq a0,a5,80004cf4 <_malloc_trim_r+0xec> -80004cb0: 1e41a783 lw a5,484(gp) # 80016d4c <__malloc_current_mallinfo> -80004cb4: 00892683 lw a3,8(s2) -80004cb8: 408484b3 sub s1,s1,s0 -80004cbc: 0014e493 ori s1,s1,1 -80004cc0: 40878433 sub s0,a5,s0 -80004cc4: 00098513 mv a0,s3 -80004cc8: 0096a223 sw s1,4(a3) -80004ccc: 1e81a223 sw s0,484(gp) # 80016d4c <__malloc_current_mallinfo> -80004cd0: 8cdfc0ef jal ra,8000159c <__malloc_unlock> -80004cd4: 01c12083 lw ra,28(sp) -80004cd8: 01812403 lw s0,24(sp) -80004cdc: 01412483 lw s1,20(sp) -80004ce0: 01012903 lw s2,16(sp) -80004ce4: 00c12983 lw s3,12(sp) -80004ce8: 00100513 li a0,1 -80004cec: 02010113 addi sp,sp,32 -80004cf0: 00008067 ret -80004cf4: 00000593 li a1,0 -80004cf8: 00098513 mv a0,s3 -80004cfc: 939fc0ef jal ra,80001634 <_sbrk_r> -80004d00: 00892703 lw a4,8(s2) -80004d04: 00f00693 li a3,15 -80004d08: 40e507b3 sub a5,a0,a4 -80004d0c: f6f6d4e3 bge a3,a5,80004c74 <_malloc_trim_r+0x6c> -80004d10: 1cc1a683 lw a3,460(gp) # 80016d34 <__malloc_sbrk_base> -80004d14: 0017e793 ori a5,a5,1 -80004d18: 00f72223 sw a5,4(a4) -80004d1c: 40d50533 sub a0,a0,a3 -80004d20: 1ea1a223 sw a0,484(gp) # 80016d4c <__malloc_current_mallinfo> -80004d24: f51ff06f j 80004c74 <_malloc_trim_r+0x6c> - -80004d28 <_free_r>: -80004d28: 12058663 beqz a1,80004e54 <_free_r+0x12c> -80004d2c: ff010113 addi sp,sp,-16 -80004d30: 00812423 sw s0,8(sp) -80004d34: 00912223 sw s1,4(sp) -80004d38: 00058413 mv s0,a1 -80004d3c: 00050493 mv s1,a0 -80004d40: 00112623 sw ra,12(sp) -80004d44: 855fc0ef jal ra,80001598 <__malloc_lock> -80004d48: ffc42503 lw a0,-4(s0) -80004d4c: ff840713 addi a4,s0,-8 -80004d50: ffe57793 andi a5,a0,-2 -80004d54: 00f70633 add a2,a4,a5 -80004d58: c2818593 addi a1,gp,-984 # 80016790 <__malloc_av_> -80004d5c: 00462683 lw a3,4(a2) -80004d60: 0085a803 lw a6,8(a1) -80004d64: ffc6f693 andi a3,a3,-4 -80004d68: 18c80e63 beq a6,a2,80004f04 <_free_r+0x1dc> -80004d6c: 00d62223 sw a3,4(a2) -80004d70: 00157513 andi a0,a0,1 -80004d74: 00d60833 add a6,a2,a3 -80004d78: 0a051063 bnez a0,80004e18 <_free_r+0xf0> -80004d7c: ff842303 lw t1,-8(s0) -80004d80: 00482803 lw a6,4(a6) -80004d84: 40670733 sub a4,a4,t1 -80004d88: 00872883 lw a7,8(a4) -80004d8c: c3018513 addi a0,gp,-976 # 80016798 <__malloc_av_+0x8> -80004d90: 006787b3 add a5,a5,t1 -80004d94: 00187813 andi a6,a6,1 -80004d98: 14a88063 beq a7,a0,80004ed8 <_free_r+0x1b0> -80004d9c: 00c72303 lw t1,12(a4) -80004da0: 0068a623 sw t1,12(a7) -80004da4: 01132423 sw a7,8(t1) -80004da8: 1c080663 beqz a6,80004f74 <_free_r+0x24c> -80004dac: 0017e693 ori a3,a5,1 -80004db0: 00d72223 sw a3,4(a4) -80004db4: 00f62023 sw a5,0(a2) -80004db8: 1ff00693 li a3,511 -80004dbc: 0af6e863 bltu a3,a5,80004e6c <_free_r+0x144> -80004dc0: 0037d793 srli a5,a5,0x3 -80004dc4: 00178693 addi a3,a5,1 -80004dc8: 00369693 slli a3,a3,0x3 -80004dcc: 0045a803 lw a6,4(a1) -80004dd0: 00d586b3 add a3,a1,a3 -80004dd4: 0006a503 lw a0,0(a3) -80004dd8: 4027d613 srai a2,a5,0x2 -80004ddc: 00100793 li a5,1 -80004de0: 00c797b3 sll a5,a5,a2 -80004de4: 0107e7b3 or a5,a5,a6 -80004de8: ff868613 addi a2,a3,-8 -80004dec: 00c72623 sw a2,12(a4) -80004df0: 00a72423 sw a0,8(a4) -80004df4: 00f5a223 sw a5,4(a1) -80004df8: 00e6a023 sw a4,0(a3) -80004dfc: 00e52623 sw a4,12(a0) -80004e00: 00812403 lw s0,8(sp) -80004e04: 00c12083 lw ra,12(sp) -80004e08: 00048513 mv a0,s1 -80004e0c: 00412483 lw s1,4(sp) -80004e10: 01010113 addi sp,sp,16 -80004e14: f88fc06f j 8000159c <__malloc_unlock> -80004e18: 00482503 lw a0,4(a6) -80004e1c: 00157513 andi a0,a0,1 -80004e20: 02051c63 bnez a0,80004e58 <_free_r+0x130> -80004e24: 00d787b3 add a5,a5,a3 -80004e28: c3018513 addi a0,gp,-976 # 80016798 <__malloc_av_+0x8> -80004e2c: 00862683 lw a3,8(a2) -80004e30: 0017e893 ori a7,a5,1 -80004e34: 00f70833 add a6,a4,a5 -80004e38: 14a68a63 beq a3,a0,80004f8c <_free_r+0x264> -80004e3c: 00c62603 lw a2,12(a2) -80004e40: 00c6a623 sw a2,12(a3) -80004e44: 00d62423 sw a3,8(a2) -80004e48: 01172223 sw a7,4(a4) -80004e4c: 00f82023 sw a5,0(a6) -80004e50: f69ff06f j 80004db8 <_free_r+0x90> -80004e54: 00008067 ret -80004e58: 0017e693 ori a3,a5,1 -80004e5c: fed42e23 sw a3,-4(s0) -80004e60: 00f62023 sw a5,0(a2) -80004e64: 1ff00693 li a3,511 -80004e68: f4f6fce3 bgeu a3,a5,80004dc0 <_free_r+0x98> -80004e6c: 0097d693 srli a3,a5,0x9 -80004e70: 00400613 li a2,4 -80004e74: 0cd66e63 bltu a2,a3,80004f50 <_free_r+0x228> -80004e78: 0067d693 srli a3,a5,0x6 -80004e7c: 03968513 addi a0,a3,57 -80004e80: 03868613 addi a2,a3,56 -80004e84: 00351513 slli a0,a0,0x3 -80004e88: 00a58533 add a0,a1,a0 -80004e8c: 00052683 lw a3,0(a0) -80004e90: ff850513 addi a0,a0,-8 -80004e94: 10d50a63 beq a0,a3,80004fa8 <_free_r+0x280> -80004e98: 0046a603 lw a2,4(a3) -80004e9c: ffc67613 andi a2,a2,-4 -80004ea0: 00c7f663 bgeu a5,a2,80004eac <_free_r+0x184> -80004ea4: 0086a683 lw a3,8(a3) -80004ea8: fed518e3 bne a0,a3,80004e98 <_free_r+0x170> -80004eac: 00c6a503 lw a0,12(a3) -80004eb0: 00a72623 sw a0,12(a4) -80004eb4: 00d72423 sw a3,8(a4) -80004eb8: 00812403 lw s0,8(sp) -80004ebc: 00e52423 sw a4,8(a0) -80004ec0: 00c12083 lw ra,12(sp) -80004ec4: 00048513 mv a0,s1 -80004ec8: 00412483 lw s1,4(sp) -80004ecc: 00e6a623 sw a4,12(a3) -80004ed0: 01010113 addi sp,sp,16 -80004ed4: ec8fc06f j 8000159c <__malloc_unlock> -80004ed8: 12081863 bnez a6,80005008 <_free_r+0x2e0> -80004edc: 00862583 lw a1,8(a2) -80004ee0: 00c62603 lw a2,12(a2) -80004ee4: 00f687b3 add a5,a3,a5 -80004ee8: 0017e693 ori a3,a5,1 -80004eec: 00c5a623 sw a2,12(a1) -80004ef0: 00b62423 sw a1,8(a2) -80004ef4: 00d72223 sw a3,4(a4) -80004ef8: 00f70733 add a4,a4,a5 -80004efc: 00f72023 sw a5,0(a4) -80004f00: f01ff06f j 80004e00 <_free_r+0xd8> -80004f04: 00157513 andi a0,a0,1 -80004f08: 00d787b3 add a5,a5,a3 -80004f0c: 02051063 bnez a0,80004f2c <_free_r+0x204> -80004f10: ff842503 lw a0,-8(s0) -80004f14: 40a70733 sub a4,a4,a0 -80004f18: 00c72683 lw a3,12(a4) -80004f1c: 00872603 lw a2,8(a4) -80004f20: 00a787b3 add a5,a5,a0 -80004f24: 00d62623 sw a3,12(a2) -80004f28: 00c6a423 sw a2,8(a3) -80004f2c: 0017e613 ori a2,a5,1 -80004f30: 1d01a683 lw a3,464(gp) # 80016d38 <__malloc_trim_threshold> -80004f34: 00c72223 sw a2,4(a4) -80004f38: 00e5a423 sw a4,8(a1) -80004f3c: ecd7e2e3 bltu a5,a3,80004e00 <_free_r+0xd8> -80004f40: 1dc1a583 lw a1,476(gp) # 80016d44 <__malloc_top_pad> -80004f44: 00048513 mv a0,s1 -80004f48: cc1ff0ef jal ra,80004c08 <_malloc_trim_r> -80004f4c: eb5ff06f j 80004e00 <_free_r+0xd8> -80004f50: 01400613 li a2,20 -80004f54: 02d67463 bgeu a2,a3,80004f7c <_free_r+0x254> -80004f58: 05400613 li a2,84 -80004f5c: 06d66463 bltu a2,a3,80004fc4 <_free_r+0x29c> -80004f60: 00c7d693 srli a3,a5,0xc -80004f64: 06f68513 addi a0,a3,111 -80004f68: 06e68613 addi a2,a3,110 -80004f6c: 00351513 slli a0,a0,0x3 -80004f70: f19ff06f j 80004e88 <_free_r+0x160> -80004f74: 00d787b3 add a5,a5,a3 -80004f78: eb5ff06f j 80004e2c <_free_r+0x104> -80004f7c: 05c68513 addi a0,a3,92 -80004f80: 05b68613 addi a2,a3,91 -80004f84: 00351513 slli a0,a0,0x3 -80004f88: f01ff06f j 80004e88 <_free_r+0x160> -80004f8c: 00e5aa23 sw a4,20(a1) -80004f90: 00e5a823 sw a4,16(a1) -80004f94: 00a72623 sw a0,12(a4) -80004f98: 00a72423 sw a0,8(a4) -80004f9c: 01172223 sw a7,4(a4) -80004fa0: 00f82023 sw a5,0(a6) -80004fa4: e5dff06f j 80004e00 <_free_r+0xd8> -80004fa8: 0045a803 lw a6,4(a1) -80004fac: 40265613 srai a2,a2,0x2 -80004fb0: 00100793 li a5,1 -80004fb4: 00c79633 sll a2,a5,a2 -80004fb8: 01066633 or a2,a2,a6 -80004fbc: 00c5a223 sw a2,4(a1) -80004fc0: ef1ff06f j 80004eb0 <_free_r+0x188> -80004fc4: 15400613 li a2,340 -80004fc8: 00d66c63 bltu a2,a3,80004fe0 <_free_r+0x2b8> -80004fcc: 00f7d693 srli a3,a5,0xf -80004fd0: 07868513 addi a0,a3,120 -80004fd4: 07768613 addi a2,a3,119 -80004fd8: 00351513 slli a0,a0,0x3 -80004fdc: eadff06f j 80004e88 <_free_r+0x160> -80004fe0: 55400613 li a2,1364 -80004fe4: 00d66c63 bltu a2,a3,80004ffc <_free_r+0x2d4> -80004fe8: 0127d693 srli a3,a5,0x12 -80004fec: 07d68513 addi a0,a3,125 -80004ff0: 07c68613 addi a2,a3,124 -80004ff4: 00351513 slli a0,a0,0x3 -80004ff8: e91ff06f j 80004e88 <_free_r+0x160> -80004ffc: 3f800513 li a0,1016 -80005000: 07e00613 li a2,126 -80005004: e85ff06f j 80004e88 <_free_r+0x160> -80005008: 0017e693 ori a3,a5,1 -8000500c: 00d72223 sw a3,4(a4) -80005010: 00f62023 sw a5,0(a2) -80005014: dedff06f j 80004e00 <_free_r+0xd8> - -80005018 <_fwalk>: -80005018: fe010113 addi sp,sp,-32 -8000501c: 01512223 sw s5,4(sp) -80005020: 00112e23 sw ra,28(sp) -80005024: 00812c23 sw s0,24(sp) -80005028: 00912a23 sw s1,20(sp) -8000502c: 01212823 sw s2,16(sp) -80005030: 01312623 sw s3,12(sp) -80005034: 01412423 sw s4,8(sp) -80005038: 01612023 sw s6,0(sp) -8000503c: 2e050a93 addi s5,a0,736 -80005040: 080a8063 beqz s5,800050c0 <_fwalk+0xa8> -80005044: 00058b13 mv s6,a1 -80005048: 00000a13 li s4,0 -8000504c: 00100993 li s3,1 -80005050: fff00913 li s2,-1 -80005054: 004aa483 lw s1,4(s5) -80005058: 008aa403 lw s0,8(s5) -8000505c: fff48493 addi s1,s1,-1 -80005060: 0204c663 bltz s1,8000508c <_fwalk+0x74> -80005064: 00c45783 lhu a5,12(s0) -80005068: fff48493 addi s1,s1,-1 -8000506c: 00f9fc63 bgeu s3,a5,80005084 <_fwalk+0x6c> -80005070: 00e41783 lh a5,14(s0) -80005074: 00040513 mv a0,s0 -80005078: 01278663 beq a5,s2,80005084 <_fwalk+0x6c> -8000507c: 000b00e7 jalr s6 -80005080: 00aa6a33 or s4,s4,a0 -80005084: 06840413 addi s0,s0,104 -80005088: fd249ee3 bne s1,s2,80005064 <_fwalk+0x4c> -8000508c: 000aaa83 lw s5,0(s5) -80005090: fc0a92e3 bnez s5,80005054 <_fwalk+0x3c> -80005094: 01c12083 lw ra,28(sp) -80005098: 01812403 lw s0,24(sp) -8000509c: 000a0513 mv a0,s4 -800050a0: 01412483 lw s1,20(sp) -800050a4: 01012903 lw s2,16(sp) -800050a8: 00c12983 lw s3,12(sp) -800050ac: 00812a03 lw s4,8(sp) -800050b0: 00412a83 lw s5,4(sp) -800050b4: 00012b03 lw s6,0(sp) -800050b8: 02010113 addi sp,sp,32 -800050bc: 00008067 ret -800050c0: 00000a13 li s4,0 -800050c4: fd1ff06f j 80005094 <_fwalk+0x7c> - -800050c8 <_fwalk_reent>: -800050c8: fd010113 addi sp,sp,-48 -800050cc: 01512a23 sw s5,20(sp) -800050d0: 02112623 sw ra,44(sp) -800050d4: 02812423 sw s0,40(sp) -800050d8: 02912223 sw s1,36(sp) -800050dc: 03212023 sw s2,32(sp) -800050e0: 01312e23 sw s3,28(sp) -800050e4: 01412c23 sw s4,24(sp) -800050e8: 01612823 sw s6,16(sp) -800050ec: 01712623 sw s7,12(sp) -800050f0: 2e050a93 addi s5,a0,736 -800050f4: 080a8663 beqz s5,80005180 <_fwalk_reent+0xb8> -800050f8: 00058b93 mv s7,a1 -800050fc: 00050b13 mv s6,a0 -80005100: 00000a13 li s4,0 -80005104: 00100993 li s3,1 -80005108: fff00913 li s2,-1 -8000510c: 004aa483 lw s1,4(s5) -80005110: 008aa403 lw s0,8(s5) -80005114: fff48493 addi s1,s1,-1 -80005118: 0204c863 bltz s1,80005148 <_fwalk_reent+0x80> -8000511c: 00c45783 lhu a5,12(s0) -80005120: fff48493 addi s1,s1,-1 -80005124: 00f9fe63 bgeu s3,a5,80005140 <_fwalk_reent+0x78> -80005128: 00e41783 lh a5,14(s0) -8000512c: 00040593 mv a1,s0 -80005130: 000b0513 mv a0,s6 -80005134: 01278663 beq a5,s2,80005140 <_fwalk_reent+0x78> -80005138: 000b80e7 jalr s7 -8000513c: 00aa6a33 or s4,s4,a0 -80005140: 06840413 addi s0,s0,104 -80005144: fd249ce3 bne s1,s2,8000511c <_fwalk_reent+0x54> -80005148: 000aaa83 lw s5,0(s5) -8000514c: fc0a90e3 bnez s5,8000510c <_fwalk_reent+0x44> -80005150: 02c12083 lw ra,44(sp) -80005154: 02812403 lw s0,40(sp) -80005158: 000a0513 mv a0,s4 -8000515c: 02412483 lw s1,36(sp) -80005160: 02012903 lw s2,32(sp) -80005164: 01c12983 lw s3,28(sp) -80005168: 01812a03 lw s4,24(sp) -8000516c: 01412a83 lw s5,20(sp) -80005170: 01012b03 lw s6,16(sp) -80005174: 00c12b83 lw s7,12(sp) -80005178: 03010113 addi sp,sp,48 -8000517c: 00008067 ret -80005180: 00000a13 li s4,0 -80005184: fcdff06f j 80005150 <_fwalk_reent+0x88> - -80005188 : -80005188: 00450693 addi a3,a0,4 -8000518c: 00000793 li a5,0 -80005190: 01a50513 addi a0,a0,26 -80005194: ffff8837 lui a6,0xffff8 -80005198: 01c0006f j 800051b4 -8000519c: 00179793 slli a5,a5,0x1 -800051a0: 00e69023 sh a4,0(a3) -800051a4: 01079793 slli a5,a5,0x10 -800051a8: 00268693 addi a3,a3,2 -800051ac: 0107d793 srli a5,a5,0x10 -800051b0: 02d50e63 beq a0,a3,800051ec -800051b4: 0006d703 lhu a4,0(a3) -800051b8: 00177613 andi a2,a4,1 -800051bc: 00060463 beqz a2,800051c4 -800051c0: 0017e793 ori a5,a5,1 -800051c4: 00175713 srli a4,a4,0x1 -800051c8: 0027f613 andi a2,a5,2 -800051cc: 010765b3 or a1,a4,a6 -800051d0: fc0606e3 beqz a2,8000519c -800051d4: 00179793 slli a5,a5,0x1 -800051d8: 00b69023 sh a1,0(a3) -800051dc: 01079793 slli a5,a5,0x10 -800051e0: 00268693 addi a3,a3,2 -800051e4: 0107d793 srli a5,a5,0x10 -800051e8: fcd516e3 bne a0,a3,800051b4 -800051ec: 00008067 ret - -800051f0 : -800051f0: 01850693 addi a3,a0,24 -800051f4: 00000713 li a4,0 -800051f8: 00250513 addi a0,a0,2 -800051fc: 01c0006f j 80005218 -80005200: 00171713 slli a4,a4,0x1 -80005204: 00f69023 sh a5,0(a3) -80005208: 01071713 slli a4,a4,0x10 -8000520c: ffe68693 addi a3,a3,-2 -80005210: 01075713 srli a4,a4,0x10 -80005214: 04d50463 beq a0,a3,8000525c -80005218: 0006d783 lhu a5,0(a3) -8000521c: 01079613 slli a2,a5,0x10 -80005220: 41065613 srai a2,a2,0x10 -80005224: 00179793 slli a5,a5,0x1 -80005228: 00065463 bgez a2,80005230 -8000522c: 00176713 ori a4,a4,1 -80005230: 01079793 slli a5,a5,0x10 -80005234: 0107d793 srli a5,a5,0x10 -80005238: 00277613 andi a2,a4,2 -8000523c: 0017e593 ori a1,a5,1 -80005240: fc0600e3 beqz a2,80005200 -80005244: 00171713 slli a4,a4,0x1 -80005248: 00b69023 sh a1,0(a3) -8000524c: 01071713 slli a4,a4,0x10 -80005250: ffe68693 addi a3,a3,-2 -80005254: 01075713 srli a4,a4,0x10 -80005258: fcd510e3 bne a0,a3,80005218 -8000525c: 00008067 ret - -80005260 : -80005260: fe010113 addi sp,sp,-32 -80005264: 00010e37 lui t3,0x10 -80005268: 00011d23 sh zero,26(sp) -8000526c: 00011e23 sh zero,28(sp) -80005270: 01858593 addi a1,a1,24 -80005274: 01c10793 addi a5,sp,28 -80005278: 00810813 addi a6,sp,8 -8000527c: fffe0e13 addi t3,t3,-1 # ffff <_start-0x7fff0001> -80005280: 0005d703 lhu a4,0(a1) -80005284: ffe78793 addi a5,a5,-2 -80005288: ffe58593 addi a1,a1,-2 -8000528c: 02071863 bnez a4,800052bc -80005290: fe079f23 sh zero,-2(a5) -80005294: ff0796e3 bne a5,a6,80005280 -80005298: 00460613 addi a2,a2,4 -8000529c: 01e10693 addi a3,sp,30 -800052a0: 0007d703 lhu a4,0(a5) -800052a4: 00260613 addi a2,a2,2 -800052a8: 00278793 addi a5,a5,2 -800052ac: fee61f23 sh a4,-2(a2) -800052b0: fed798e3 bne a5,a3,800052a0 -800052b4: 02010113 addi sp,sp,32 -800052b8: 00008067 ret -800052bc: 02a70733 mul a4,a4,a0 -800052c0: 0027d883 lhu a7,2(a5) -800052c4: 0007d303 lhu t1,0(a5) -800052c8: 01c776b3 and a3,a4,t3 -800052cc: 011686b3 add a3,a3,a7 -800052d0: 01075713 srli a4,a4,0x10 -800052d4: 0106d893 srli a7,a3,0x10 -800052d8: 00670733 add a4,a4,t1 -800052dc: 01170733 add a4,a4,a7 -800052e0: 01075893 srli a7,a4,0x10 -800052e4: 00d79123 sh a3,2(a5) -800052e8: 00e79023 sh a4,0(a5) -800052ec: ff179f23 sh a7,-2(a5) -800052f0: f90798e3 bne a5,a6,80005280 -800052f4: fa5ff06f j 80005298 - -800052f8 : -800052f8: 01250713 addi a4,a0,18 -800052fc: 00250513 addi a0,a0,2 -80005300: ffe55783 lhu a5,-2(a0) -80005304: 00079863 bnez a5,80005314 -80005308: fea71ae3 bne a4,a0,800052fc -8000530c: 00000513 li a0,0 -80005310: 00008067 ret -80005314: 00100513 li a0,1 -80005318: 00008067 ret - -8000531c : -8000531c: ff010113 addi sp,sp,-16 -80005320: 00812423 sw s0,8(sp) -80005324: 01255403 lhu s0,18(a0) -80005328: 00912223 sw s1,4(sp) -8000532c: 00112623 sw ra,12(sp) -80005330: fff44793 not a5,s0 -80005334: 01179713 slli a4,a5,0x11 -80005338: 00050493 mv s1,a0 -8000533c: 00071663 bnez a4,80005348 -80005340: fb9ff0ef jal ra,800052f8 -80005344: 00051863 bnez a0,80005354 -80005348: ffff87b7 lui a5,0xffff8 -8000534c: 00f44433 xor s0,s0,a5 -80005350: 00849923 sh s0,18(s1) -80005354: 00c12083 lw ra,12(sp) -80005358: 00812403 lw s0,8(sp) -8000535c: 00412483 lw s1,4(sp) -80005360: 01010113 addi sp,sp,16 -80005364: 00008067 ret - -80005368 : -80005368: ff010113 addi sp,sp,-16 -8000536c: 00812423 sw s0,8(sp) -80005370: 01255403 lhu s0,18(a0) -80005374: 00112623 sw ra,12(sp) -80005378: fff44793 not a5,s0 -8000537c: 01179713 slli a4,a5,0x11 -80005380: 00071863 bnez a4,80005390 -80005384: f75ff0ef jal ra,800052f8 -80005388: 00000793 li a5,0 -8000538c: 00051463 bnez a0,80005394 -80005390: 00f45793 srli a5,s0,0xf -80005394: 00c12083 lw ra,12(sp) -80005398: 00812403 lw s0,8(sp) -8000539c: 00078513 mv a0,a5 -800053a0: 01010113 addi sp,sp,16 -800053a4: 00008067 ret - -800053a8 : -800053a8: 01251783 lh a5,18(a0) -800053ac: ff010113 addi sp,sp,-16 -800053b0: 00112623 sw ra,12(sp) -800053b4: 00812423 sw s0,8(sp) -800053b8: 00912223 sw s1,4(sp) -800053bc: 01212023 sw s2,0(sp) -800053c0: 0607c063 bltz a5,80005420 -800053c4: 00059023 sh zero,0(a1) -800053c8: 01255783 lhu a5,18(a0) -800053cc: 00008737 lui a4,0x8 -800053d0: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -800053d4: 00f777b3 and a5,a4,a5 -800053d8: 00f59123 sh a5,2(a1) -800053dc: 01050413 addi s0,a0,16 -800053e0: 06e78263 beq a5,a4,80005444 -800053e4: 00658793 addi a5,a1,6 -800053e8: 00059223 sh zero,4(a1) -800053ec: ffe50513 addi a0,a0,-2 -800053f0: ffe40413 addi s0,s0,-2 -800053f4: 00245703 lhu a4,2(s0) -800053f8: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe128a> -800053fc: fee79f23 sh a4,-2(a5) -80005400: fe8518e3 bne a0,s0,800053f0 -80005404: 00059c23 sh zero,24(a1) -80005408: 00c12083 lw ra,12(sp) -8000540c: 00812403 lw s0,8(sp) -80005410: 00412483 lw s1,4(sp) -80005414: 00012903 lw s2,0(sp) -80005418: 01010113 addi sp,sp,16 -8000541c: 00008067 ret -80005420: fff00793 li a5,-1 -80005424: 00f59023 sh a5,0(a1) -80005428: 01255783 lhu a5,18(a0) -8000542c: 00008737 lui a4,0x8 -80005430: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005434: 00f777b3 and a5,a4,a5 -80005438: 00f59123 sh a5,2(a1) -8000543c: 01050413 addi s0,a0,16 -80005440: fae792e3 bne a5,a4,800053e4 -80005444: 01255703 lhu a4,18(a0) -80005448: 00058913 mv s2,a1 -8000544c: 00050493 mv s1,a0 -80005450: 00e7f733 and a4,a5,a4 -80005454: 02f71863 bne a4,a5,80005484 -80005458: ea1ff0ef jal ra,800052f8 -8000545c: 02050463 beqz a0,80005484 -80005460: 00690713 addi a4,s2,6 -80005464: 00091223 sh zero,4(s2) -80005468: ffc48793 addi a5,s1,-4 -8000546c: ffe40413 addi s0,s0,-2 -80005470: 00245683 lhu a3,2(s0) -80005474: 00270713 addi a4,a4,2 -80005478: fed71f23 sh a3,-2(a4) -8000547c: fe8798e3 bne a5,s0,8000546c -80005480: f89ff06f j 80005408 -80005484: 00490793 addi a5,s2,4 -80005488: 01a90593 addi a1,s2,26 -8000548c: 00278793 addi a5,a5,2 -80005490: fe079f23 sh zero,-2(a5) -80005494: fef59ce3 bne a1,a5,8000548c -80005498: 00c12083 lw ra,12(sp) -8000549c: 00812403 lw s0,8(sp) -800054a0: 00412483 lw s1,4(sp) -800054a4: 00012903 lw s2,0(sp) -800054a8: 01010113 addi sp,sp,16 -800054ac: 00008067 ret - -800054b0 : -800054b0: 01255783 lhu a5,18(a0) -800054b4: fb010113 addi sp,sp,-80 -800054b8: 04812423 sw s0,72(sp) -800054bc: fff7c793 not a5,a5 -800054c0: 04912223 sw s1,68(sp) -800054c4: 04112623 sw ra,76(sp) -800054c8: 01179713 slli a4,a5,0x11 -800054cc: 00050493 mv s1,a0 -800054d0: 00058413 mv s0,a1 -800054d4: 00071663 bnez a4,800054e0 -800054d8: e21ff0ef jal ra,800052f8 -800054dc: 08051263 bnez a0,80005560 -800054e0: 01245783 lhu a5,18(s0) -800054e4: fff7c793 not a5,a5 -800054e8: 01179713 slli a4,a5,0x11 -800054ec: 06070463 beqz a4,80005554 -800054f0: 00810593 addi a1,sp,8 -800054f4: 00048513 mv a0,s1 -800054f8: eb1ff0ef jal ra,800053a8 -800054fc: 02410593 addi a1,sp,36 -80005500: 00040513 mv a0,s0 -80005504: ea5ff0ef jal ra,800053a8 -80005508: 00815583 lhu a1,8(sp) -8000550c: 02415783 lhu a5,36(sp) -80005510: 04b78c63 beq a5,a1,80005568 -80005514: 00a10793 addi a5,sp,10 -80005518: 02610713 addi a4,sp,38 -8000551c: 02010613 addi a2,sp,32 -80005520: 0007d683 lhu a3,0(a5) -80005524: 00278793 addi a5,a5,2 -80005528: 08069663 bnez a3,800055b4 -8000552c: 00075683 lhu a3,0(a4) -80005530: 00270713 addi a4,a4,2 -80005534: 08069063 bnez a3,800055b4 -80005538: fec794e3 bne a5,a2,80005520 -8000553c: 00000513 li a0,0 -80005540: 04c12083 lw ra,76(sp) -80005544: 04812403 lw s0,72(sp) -80005548: 04412483 lw s1,68(sp) -8000554c: 05010113 addi sp,sp,80 -80005550: 00008067 ret -80005554: 00040513 mv a0,s0 -80005558: da1ff0ef jal ra,800052f8 -8000555c: f8050ae3 beqz a0,800054f0 -80005560: ffe00513 li a0,-2 -80005564: fddff06f j 80005540 -80005568: 00100513 li a0,1 -8000556c: 04079c63 bnez a5,800055c4 -80005570: 00a10713 addi a4,sp,10 -80005574: 02610793 addi a5,sp,38 -80005578: 00278793 addi a5,a5,2 -8000557c: 00270713 addi a4,a4,2 -80005580: ffe75603 lhu a2,-2(a4) -80005584: ffe7d683 lhu a3,-2(a5) -80005588: 03c10593 addi a1,sp,60 -8000558c: 00d61e63 bne a2,a3,800055a8 -80005590: fab786e3 beq a5,a1,8000553c -80005594: 00278793 addi a5,a5,2 -80005598: 00270713 addi a4,a4,2 -8000559c: ffe75603 lhu a2,-2(a4) -800055a0: ffe7d683 lhu a3,-2(a5) -800055a4: fed606e3 beq a2,a3,80005590 -800055a8: f8c6ece3 bltu a3,a2,80005540 -800055ac: 40a00533 neg a0,a0 -800055b0: f91ff06f j 80005540 -800055b4: 00100513 li a0,1 -800055b8: f80584e3 beqz a1,80005540 -800055bc: fff00513 li a0,-1 -800055c0: f81ff06f j 80005540 -800055c4: fff00513 li a0,-1 -800055c8: fa9ff06f j 80005570 - -800055cc : -800055cc: ff010113 addi sp,sp,-16 -800055d0: 00112623 sw ra,12(sp) -800055d4: d25ff0ef jal ra,800052f8 -800055d8: 00c12083 lw ra,12(sp) -800055dc: 00153513 seqz a0,a0 -800055e0: 01010113 addi sp,sp,16 -800055e4: 00008067 ret - -800055e8 : -800055e8: ff010113 addi sp,sp,-16 -800055ec: 00812423 sw s0,8(sp) -800055f0: 01212023 sw s2,0(sp) -800055f4: 00112623 sw ra,12(sp) -800055f8: 00912223 sw s1,4(sp) -800055fc: 00058913 mv s2,a1 -80005600: 00050413 mv s0,a0 -80005604: 0a05c263 bltz a1,800056a8 -80005608: 00f00793 li a5,15 -8000560c: 00058613 mv a2,a1 -80005610: 00450513 addi a0,a0,4 -80005614: 01840693 addi a3,s0,24 -80005618: 00f00593 li a1,15 -8000561c: 0327d463 bge a5,s2,80005644 -80005620: 00050793 mv a5,a0 -80005624: 00278793 addi a5,a5,2 -80005628: 0007d703 lhu a4,0(a5) -8000562c: fee79f23 sh a4,-2(a5) -80005630: fed79ae3 bne a5,a3,80005624 -80005634: 00041c23 sh zero,24(s0) -80005638: ff060613 addi a2,a2,-16 -8000563c: fec5c2e3 blt a1,a2,80005620 -80005640: 00f97913 andi s2,s2,15 -80005644: 00700793 li a5,7 -80005648: 0327d863 bge a5,s2,80005678 -8000564c: 01840793 addi a5,s0,24 -80005650: 00240593 addi a1,s0,2 -80005654: 00000713 li a4,0 -80005658: 0007d683 lhu a3,0(a5) -8000565c: ffe78793 addi a5,a5,-2 -80005660: 00869613 slli a2,a3,0x8 -80005664: 00c76733 or a4,a4,a2 -80005668: 00e79123 sh a4,2(a5) -8000566c: 0086d713 srli a4,a3,0x8 -80005670: feb794e3 bne a5,a1,80005658 -80005674: ff890913 addi s2,s2,-8 -80005678: 00090a63 beqz s2,8000568c -8000567c: fff90913 addi s2,s2,-1 -80005680: 00040513 mv a0,s0 -80005684: b6dff0ef jal ra,800051f0 -80005688: fe091ae3 bnez s2,8000567c -8000568c: 00c12083 lw ra,12(sp) -80005690: 00812403 lw s0,8(sp) -80005694: 00412483 lw s1,4(sp) -80005698: 00012903 lw s2,0(sp) -8000569c: 00000513 li a0,0 -800056a0: 01010113 addi sp,sp,16 -800056a4: 00008067 ret -800056a8: ff100793 li a5,-15 -800056ac: 40b004b3 neg s1,a1 -800056b0: 0cf5d463 bge a1,a5,80005778 -800056b4: 01850593 addi a1,a0,24 -800056b8: 00000913 li s2,0 -800056bc: 00450693 addi a3,a0,4 -800056c0: 00f00613 li a2,15 -800056c4: 01845703 lhu a4,24(s0) -800056c8: 00058793 mv a5,a1 -800056cc: 00e96933 or s2,s2,a4 -800056d0: ffe78793 addi a5,a5,-2 -800056d4: 0007d703 lhu a4,0(a5) -800056d8: 00e79123 sh a4,2(a5) -800056dc: fed79ae3 bne a5,a3,800056d0 -800056e0: 00041223 sh zero,4(s0) -800056e4: ff048493 addi s1,s1,-16 -800056e8: fc964ee3 blt a2,s1,800056c4 -800056ec: 00700793 li a5,7 -800056f0: 0497d663 bge a5,s1,8000573c -800056f4: 01091913 slli s2,s2,0x10 -800056f8: 41095913 srai s2,s2,0x10 -800056fc: 01844783 lbu a5,24(s0) -80005700: 01a40593 addi a1,s0,26 -80005704: 00000713 li a4,0 -80005708: 00f96933 or s2,s2,a5 -8000570c: 01091913 slli s2,s2,0x10 -80005710: 01095913 srli s2,s2,0x10 -80005714: 0006d783 lhu a5,0(a3) -80005718: 00268693 addi a3,a3,2 -8000571c: 0087d613 srli a2,a5,0x8 -80005720: 00c76733 or a4,a4,a2 -80005724: 00879793 slli a5,a5,0x8 -80005728: fee69f23 sh a4,-2(a3) -8000572c: 01079713 slli a4,a5,0x10 -80005730: 01075713 srli a4,a4,0x10 -80005734: feb690e3 bne a3,a1,80005714 -80005738: ff848493 addi s1,s1,-8 -8000573c: 02048063 beqz s1,8000575c -80005740: 01845783 lhu a5,24(s0) -80005744: fff48493 addi s1,s1,-1 -80005748: 00040513 mv a0,s0 -8000574c: 0017f793 andi a5,a5,1 -80005750: 0127e933 or s2,a5,s2 -80005754: a35ff0ef jal ra,80005188 -80005758: fe0494e3 bnez s1,80005740 -8000575c: 00c12083 lw ra,12(sp) -80005760: 00812403 lw s0,8(sp) -80005764: 01203533 snez a0,s2 -80005768: 00412483 lw s1,4(sp) -8000576c: 00012903 lw s2,0(sp) -80005770: 01010113 addi sp,sp,16 -80005774: 00008067 ret -80005778: ff900793 li a5,-7 -8000577c: 00f5c663 blt a1,a5,80005788 -80005780: 00000913 li s2,0 -80005784: fbdff06f j 80005740 -80005788: 00000913 li s2,0 -8000578c: 00440693 addi a3,s0,4 -80005790: f6dff06f j 800056fc - -80005794 : -80005794: 00455783 lhu a5,4(a0) -80005798: ff010113 addi sp,sp,-16 -8000579c: 00912223 sw s1,4(sp) -800057a0: 00112623 sw ra,12(sp) -800057a4: 00812423 sw s0,8(sp) -800057a8: 01212023 sw s2,0(sp) -800057ac: 00050493 mv s1,a0 -800057b0: 0c079c63 bnez a5,80005888 -800057b4: 00655703 lhu a4,6(a0) -800057b8: 00000413 li s0,0 -800057bc: 01071793 slli a5,a4,0x10 -800057c0: 4107d793 srai a5,a5,0x10 -800057c4: 0a07c463 bltz a5,8000586c -800057c8: 01a50693 addi a3,a0,26 -800057cc: 0a000613 li a2,160 -800057d0: 02071863 bnez a4,80005800 -800057d4: 00648793 addi a5,s1,6 -800057d8: 0080006f j 800057e0 -800057dc: 0007d703 lhu a4,0(a5) -800057e0: 00278793 addi a5,a5,2 -800057e4: fee79e23 sh a4,-4(a5) -800057e8: fef69ae3 bne a3,a5,800057dc -800057ec: 00049c23 sh zero,24(s1) -800057f0: 01040413 addi s0,s0,16 -800057f4: 06c40c63 beq s0,a2,8000586c -800057f8: 0064d703 lhu a4,6(s1) -800057fc: fc070ce3 beqz a4,800057d4 -80005800: f0077793 andi a5,a4,-256 -80005804: 04079063 bnez a5,80005844 -80005808: 01848513 addi a0,s1,24 -8000580c: 00248593 addi a1,s1,2 -80005810: 00000713 li a4,0 -80005814: 00050793 mv a5,a0 -80005818: 0007d683 lhu a3,0(a5) -8000581c: ffe78793 addi a5,a5,-2 -80005820: 00869613 slli a2,a3,0x8 -80005824: 00c76733 or a4,a4,a2 -80005828: 00e79123 sh a4,2(a5) -8000582c: 0086d713 srli a4,a3,0x8 -80005830: fef594e3 bne a1,a5,80005818 -80005834: 0064d703 lhu a4,6(s1) -80005838: 00840413 addi s0,s0,8 -8000583c: f0077793 andi a5,a4,-256 -80005840: fc0788e3 beqz a5,80005810 -80005844: 0a000913 li s2,160 -80005848: 0140006f j 8000585c -8000584c: 00140413 addi s0,s0,1 -80005850: 9a1ff0ef jal ra,800051f0 -80005854: 00894c63 blt s2,s0,8000586c -80005858: 0064d703 lhu a4,6(s1) -8000585c: 01071713 slli a4,a4,0x10 -80005860: 41075713 srai a4,a4,0x10 -80005864: 00048513 mv a0,s1 -80005868: fe0752e3 bgez a4,8000584c -8000586c: 00040513 mv a0,s0 -80005870: 00c12083 lw ra,12(sp) -80005874: 00812403 lw s0,8(sp) -80005878: 00412483 lw s1,4(sp) -8000587c: 00012903 lw s2,0(sp) -80005880: 01010113 addi sp,sp,16 -80005884: 00008067 ret -80005888: f007f713 andi a4,a5,-256 -8000588c: 00000413 li s0,0 -80005890: 04071063 bnez a4,800058d0 -80005894: f6f00913 li s2,-145 -80005898: 0140006f j 800058ac -8000589c: fff40413 addi s0,s0,-1 -800058a0: 8e9ff0ef jal ra,80005188 -800058a4: fd2404e3 beq s0,s2,8000586c -800058a8: 0044d783 lhu a5,4(s1) -800058ac: 00048513 mv a0,s1 -800058b0: fe0796e3 bnez a5,8000589c -800058b4: 00040513 mv a0,s0 -800058b8: 00c12083 lw ra,12(sp) -800058bc: 00812403 lw s0,8(sp) -800058c0: 00412483 lw s1,4(sp) -800058c4: 00012903 lw s2,0(sp) -800058c8: 01010113 addi sp,sp,16 -800058cc: 00008067 ret -800058d0: 00450693 addi a3,a0,4 -800058d4: 01a50593 addi a1,a0,26 -800058d8: 00000713 li a4,0 -800058dc: 0080006f j 800058e4 -800058e0: 0006d783 lhu a5,0(a3) -800058e4: 0087d613 srli a2,a5,0x8 -800058e8: 00c76733 or a4,a4,a2 -800058ec: 00879793 slli a5,a5,0x8 -800058f0: 00e69023 sh a4,0(a3) -800058f4: 01079713 slli a4,a5,0x10 -800058f8: 00268693 addi a3,a3,2 -800058fc: 01075713 srli a4,a4,0x10 -80005900: feb690e3 bne a3,a1,800058e0 -80005904: 0044d783 lhu a5,4(s1) -80005908: ff800413 li s0,-8 -8000590c: f89ff06f j 80005894 - -80005910 : -80005910: fe010113 addi sp,sp,-32 -80005914: 00812c23 sw s0,24(sp) -80005918: 00912a23 sw s1,20(sp) -8000591c: 01212823 sw s2,16(sp) -80005920: 01312623 sw s3,12(sp) -80005924: 01412423 sw s4,8(sp) -80005928: 01512223 sw s5,4(sp) -8000592c: 00068913 mv s2,a3 -80005930: 00078493 mv s1,a5 -80005934: 00112e23 sw ra,28(sp) -80005938: 00050413 mv s0,a0 -8000593c: 00058993 mv s3,a1 -80005940: 00060a13 mv s4,a2 -80005944: 00070a93 mv s5,a4 -80005948: e4dff0ef jal ra,80005794 -8000594c: 09000793 li a5,144 -80005950: 40a90933 sub s2,s2,a0 -80005954: 06a7de63 bge a5,a0,800059d0 -80005958: 000087b7 lui a5,0x8 -8000595c: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -80005960: 2127de63 bge a5,s2,80005b7c -80005964: 1e0a8863 beqz s5,80005b54 -80005968: 0044a503 lw a0,4(s1) -8000596c: 0004a783 lw a5,0(s1) -80005970: 0ea78e63 beq a5,a0,80005a6c -80005974: 01a48713 addi a4,s1,26 -80005978: 03448793 addi a5,s1,52 -8000597c: 00270713 addi a4,a4,2 -80005980: fe071f23 sh zero,-2(a4) -80005984: fef71ce3 bne a4,a5,8000597c -80005988: 03800793 li a5,56 -8000598c: 36f50463 beq a0,a5,80005cf4 -80005990: 06a7d263 bge a5,a0,800059f4 -80005994: 04000793 li a5,64 -80005998: 2ef50e63 beq a0,a5,80005c94 -8000599c: 07100793 li a5,113 -800059a0: 32f51063 bne a0,a5,80005cc0 -800059a4: 400087b7 lui a5,0x40008 -800059a8: fff78793 addi a5,a5,-1 # 40007fff <_start-0x3fff8001> -800059ac: 00a00713 li a4,10 -800059b0: 00f4aa23 sw a5,20(s1) -800059b4: ffff87b7 lui a5,0xffff8 -800059b8: 00e4a423 sw a4,8(s1) -800059bc: 00f49c23 sh a5,24(s1) -800059c0: 00e4a623 sw a4,12(s1) -800059c4: 00a00793 li a5,10 -800059c8: 00008737 lui a4,0x8 -800059cc: 0680006f j 80005a34 -800059d0: 1e095663 bgez s2,80005bbc -800059d4: f7000793 li a5,-144 -800059d8: 1af95e63 bge s2,a5,80005b94 -800059dc: 00240793 addi a5,s0,2 -800059e0: 01a40413 addi s0,s0,26 -800059e4: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe128a> -800059e8: fe079f23 sh zero,-2(a5) -800059ec: fe879ce3 bne a5,s0,800059e4 -800059f0: 1400006f j 80005b30 -800059f4: 01800793 li a5,24 -800059f8: 26f50863 beq a0,a5,80005c68 -800059fc: 03500793 li a5,53 -80005a00: 2cf51063 bne a0,a5,80005cc0 -80005a04: 040007b7 lui a5,0x4000 -80005a08: 7ff78793 addi a5,a5,2047 # 40007ff <_start-0x7bfff801> -80005a0c: 00600713 li a4,6 -80005a10: 00f4aa23 sw a5,20(s1) -80005a14: 000017b7 lui a5,0x1 -80005a18: 80078793 addi a5,a5,-2048 # 800 <_start-0x7ffff800> -80005a1c: 00e4a423 sw a4,8(s1) -80005a20: 00e4a623 sw a4,12(s1) -80005a24: 00001737 lui a4,0x1 -80005a28: 00f49c23 sh a5,24(s1) -80005a2c: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> -80005a30: 00600793 li a5,6 -80005a34: 00878793 addi a5,a5,8 -80005a38: 00179793 slli a5,a5,0x1 -80005a3c: 00f487b3 add a5,s1,a5 -80005a40: 00e79523 sh a4,10(a5) -80005a44: 00a4a023 sw a0,0(s1) -80005a48: 03204263 bgtz s2,80005a6c -80005a4c: 09000793 li a5,144 -80005a50: 1ef50863 beq a0,a5,80005c40 -80005a54: 01845783 lhu a5,24(s0) -80005a58: 00040513 mv a0,s0 -80005a5c: 0017f793 andi a5,a5,1 -80005a60: 00f9e9b3 or s3,s3,a5 -80005a64: f24ff0ef jal ra,80005188 -80005a68: 0044a503 lw a0,4(s1) -80005a6c: 0084a583 lw a1,8(s1) -80005a70: 0144d783 lhu a5,20(s1) -80005a74: 08f00813 li a6,143 -80005a78: 00159613 slli a2,a1,0x1 -80005a7c: 00c40633 add a2,s0,a2 -80005a80: 00065703 lhu a4,0(a2) -80005a84: 00f776b3 and a3,a4,a5 -80005a88: 02a84a63 blt a6,a0,80005abc -80005a8c: 00b00813 li a6,11 -80005a90: 02b84663 blt a6,a1,80005abc -80005a94: 00060713 mv a4,a2 -80005a98: 01840593 addi a1,s0,24 -80005a9c: 00275783 lhu a5,2(a4) -80005aa0: 00078463 beqz a5,80005aa8 -80005aa4: 0016e693 ori a3,a3,1 -80005aa8: 00071123 sh zero,2(a4) -80005aac: 00270713 addi a4,a4,2 -80005ab0: fee596e3 bne a1,a4,80005a9c -80005ab4: 00065703 lhu a4,0(a2) -80005ab8: 0144d783 lhu a5,20(s1) -80005abc: fff7c793 not a5,a5 -80005ac0: 00e7f7b3 and a5,a5,a4 -80005ac4: 00f61023 sh a5,0(a2) -80005ac8: 0164d783 lhu a5,22(s1) -80005acc: 00d7f733 and a4,a5,a3 -80005ad0: 04070063 beqz a4,80005b10 -80005ad4: 12d78263 beq a5,a3,80005bf8 -80005ad8: 03248613 addi a2,s1,50 -80005adc: 01840713 addi a4,s0,24 -80005ae0: 01c48493 addi s1,s1,28 -80005ae4: 00000693 li a3,0 -80005ae8: 00065783 lhu a5,0(a2) -80005aec: 00075583 lhu a1,0(a4) -80005af0: ffe70713 addi a4,a4,-2 -80005af4: ffe60613 addi a2,a2,-2 -80005af8: 00b787b3 add a5,a5,a1 -80005afc: 00d787b3 add a5,a5,a3 -80005b00: 00f71123 sh a5,2(a4) -80005b04: 0107d793 srli a5,a5,0x10 -80005b08: 0017f693 andi a3,a5,1 -80005b0c: fc961ee3 bne a2,s1,80005ae8 -80005b10: 11205663 blez s2,80005c1c -80005b14: 00445783 lhu a5,4(s0) -80005b18: 0a079c63 bnez a5,80005bd0 -80005b1c: 000087b7 lui a5,0x8 -80005b20: 00041c23 sh zero,24(s0) -80005b24: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -80005b28: 0327c863 blt a5,s2,80005b58 -80005b2c: 01241123 sh s2,2(s0) -80005b30: 01c12083 lw ra,28(sp) -80005b34: 01812403 lw s0,24(sp) -80005b38: 01412483 lw s1,20(sp) -80005b3c: 01012903 lw s2,16(sp) -80005b40: 00c12983 lw s3,12(sp) -80005b44: 00812a03 lw s4,8(sp) -80005b48: 00412a83 lw s5,4(sp) -80005b4c: 02010113 addi sp,sp,32 -80005b50: 00008067 ret -80005b54: 00041c23 sh zero,24(s0) -80005b58: ffff87b7 lui a5,0xffff8 -80005b5c: fff7c793 not a5,a5 -80005b60: 00f41123 sh a5,2(s0) -80005b64: 00440793 addi a5,s0,4 -80005b68: 01840413 addi s0,s0,24 -80005b6c: 00079023 sh zero,0(a5) # ffff8000 <__BSS_END__+0x7ffe1288> -80005b70: 00278793 addi a5,a5,2 -80005b74: fef41ce3 bne s0,a5,80005b6c -80005b78: fb9ff06f j 80005b30 -80005b7c: 00240793 addi a5,s0,2 -80005b80: 01a40413 addi s0,s0,26 -80005b84: 00278793 addi a5,a5,2 -80005b88: fe079f23 sh zero,-2(a5) -80005b8c: fe879ce3 bne a5,s0,80005b84 -80005b90: fa1ff06f j 80005b30 -80005b94: 00090593 mv a1,s2 -80005b98: 00040513 mv a0,s0 -80005b9c: a4dff0ef jal ra,800055e8 -80005ba0: 00050463 beqz a0,80005ba8 -80005ba4: 00100993 li s3,1 -80005ba8: 0a0a8a63 beqz s5,80005c5c -80005bac: 0044a503 lw a0,4(s1) -80005bb0: 0004a783 lw a5,0(s1) -80005bb4: dca790e3 bne a5,a0,80005974 -80005bb8: e95ff06f j 80005a4c -80005bbc: f60a80e3 beqz s5,80005b1c -80005bc0: 0044a503 lw a0,4(s1) -80005bc4: 0004a783 lw a5,0(s1) -80005bc8: daf516e3 bne a0,a5,80005974 -80005bcc: e7dff06f j 80005a48 -80005bd0: 00040513 mv a0,s0 -80005bd4: db4ff0ef jal ra,80005188 -80005bd8: 000087b7 lui a5,0x8 -80005bdc: 00190913 addi s2,s2,1 -80005be0: 00041c23 sh zero,24(s0) -80005be4: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -80005be8: f727c8e3 blt a5,s2,80005b58 -80005bec: f40950e3 bgez s2,80005b2c -80005bf0: 00041123 sh zero,2(s0) -80005bf4: f3dff06f j 80005b30 -80005bf8: 0e099a63 bnez s3,80005cec -80005bfc: 00c4a783 lw a5,12(s1) -80005c00: 0184d703 lhu a4,24(s1) -80005c04: 00179793 slli a5,a5,0x1 -80005c08: 00f407b3 add a5,s0,a5 -80005c0c: 0007d783 lhu a5,0(a5) -80005c10: 00e7f7b3 and a5,a5,a4 -80005c14: ec0792e3 bnez a5,80005ad8 -80005c18: ef204ee3 bgtz s2,80005b14 -80005c1c: 09000793 li a5,144 -80005c20: 00f50663 beq a0,a5,80005c2c -80005c24: 00040513 mv a0,s0 -80005c28: dc8ff0ef jal ra,800051f0 -80005c2c: 00445783 lhu a5,4(s0) -80005c30: fa0790e3 bnez a5,80005bd0 -80005c34: 00041c23 sh zero,24(s0) -80005c38: fa094ce3 bltz s2,80005bf0 -80005c3c: ef1ff06f j 80005b2c -80005c40: 0084a603 lw a2,8(s1) -80005c44: 0144d783 lhu a5,20(s1) -80005c48: 00161613 slli a2,a2,0x1 -80005c4c: 00c40633 add a2,s0,a2 -80005c50: 00065703 lhu a4,0(a2) -80005c54: 00e7f6b3 and a3,a5,a4 -80005c58: e65ff06f j 80005abc -80005c5c: 00041c23 sh zero,24(s0) -80005c60: 00041123 sh zero,2(s0) -80005c64: ecdff06f j 80005b30 -80005c68: 008007b7 lui a5,0x800 -80005c6c: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> -80005c70: 00400713 li a4,4 -80005c74: 00f4aa23 sw a5,20(s1) -80005c78: 10000793 li a5,256 -80005c7c: 00e4a423 sw a4,8(s1) -80005c80: 00f49c23 sh a5,24(s1) -80005c84: 00e4a623 sw a4,12(s1) -80005c88: 00400793 li a5,4 -80005c8c: 10000713 li a4,256 -80005c90: da5ff06f j 80005a34 -80005c94: 00700793 li a5,7 -80005c98: 00f4a423 sw a5,8(s1) -80005c9c: 800107b7 lui a5,0x80010 -80005ca0: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff9287> -80005ca4: 00f4aa23 sw a5,20(s1) -80005ca8: 00100793 li a5,1 -80005cac: 00f49c23 sh a5,24(s1) -80005cb0: 00600793 li a5,6 -80005cb4: 00f4a623 sw a5,12(s1) -80005cb8: 00100713 li a4,1 -80005cbc: d79ff06f j 80005a34 -80005cc0: 00c00793 li a5,12 -80005cc4: 00f4a423 sw a5,8(s1) -80005cc8: 800107b7 lui a5,0x80010 -80005ccc: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff9287> -80005cd0: 00f4aa23 sw a5,20(s1) -80005cd4: 00100793 li a5,1 -80005cd8: 00f49c23 sh a5,24(s1) -80005cdc: 00b00793 li a5,11 -80005ce0: 00f4a623 sw a5,12(s1) -80005ce4: 00100713 li a4,1 -80005ce8: d4dff06f j 80005a34 -80005cec: de0a06e3 beqz s4,80005ad8 -80005cf0: e21ff06f j 80005b10 -80005cf4: 008007b7 lui a5,0x800 -80005cf8: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> -80005cfc: 00600713 li a4,6 -80005d00: 00f4aa23 sw a5,20(s1) -80005d04: 10000793 li a5,256 -80005d08: 00e4a423 sw a4,8(s1) -80005d0c: 00f49c23 sh a5,24(s1) -80005d10: 00e4a623 sw a4,12(s1) -80005d14: 00600793 li a5,6 -80005d18: 10000713 li a4,256 -80005d1c: d19ff06f j 80005a34 - -80005d20 : -80005d20: fd010113 addi sp,sp,-48 -80005d24: 01312e23 sw s3,28(sp) -80005d28: 00255983 lhu s3,2(a0) -80005d2c: 02912223 sw s1,36(sp) -80005d30: 00058493 mv s1,a1 -80005d34: 02112623 sw ra,44(sp) -80005d38: 02812423 sw s0,40(sp) -80005d3c: 03212023 sw s2,32(sp) -80005d40: 01412c23 sw s4,24(sp) -80005d44: 00060913 mv s2,a2 -80005d48: 01512a23 sw s5,20(sp) -80005d4c: 01612823 sw s6,16(sp) -80005d50: 01712623 sw s7,12(sp) -80005d54: 01812423 sw s8,8(sp) -80005d58: 01912223 sw s9,4(sp) -80005d5c: 01a12023 sw s10,0(sp) -80005d60: 00050a13 mv s4,a0 -80005d64: a31ff0ef jal ra,80005794 -80005d68: 0024d403 lhu s0,2(s1) -80005d6c: 40a989b3 sub s3,s3,a0 -80005d70: 00048513 mv a0,s1 -80005d74: a21ff0ef jal ra,80005794 -80005d78: 03490a93 addi s5,s2,52 -80005d7c: 40a40433 sub s0,s0,a0 -80005d80: 04e90713 addi a4,s2,78 -80005d84: 000a8793 mv a5,s5 -80005d88: 00278793 addi a5,a5,2 -80005d8c: fe079f23 sh zero,-2(a5) -80005d90: fee79ce3 bne a5,a4,80005d88 -80005d94: 09344a63 blt s0,s3,80005e28 -80005d98: 004a0b93 addi s7,s4,4 -80005d9c: 00448b13 addi s6,s1,4 -80005da0: fff98993 addi s3,s3,-1 -80005da4: 01aa0c93 addi s9,s4,26 -80005da8: 00248c13 addi s8,s1,2 -80005dac: 000b0713 mv a4,s6 -80005db0: 000b8793 mv a5,s7 -80005db4: 00278793 addi a5,a5,2 -80005db8: 00270713 addi a4,a4,2 -80005dbc: ffe7d603 lhu a2,-2(a5) -80005dc0: ffe75683 lhu a3,-2(a4) -80005dc4: 0ad61a63 bne a2,a3,80005e78 -80005dc8: ff9796e3 bne a5,s9,80005db4 -80005dcc: 018a0693 addi a3,s4,24 -80005dd0: 01848713 addi a4,s1,24 -80005dd4: 00000613 li a2,0 -80005dd8: 00075783 lhu a5,0(a4) -80005ddc: 0006d583 lhu a1,0(a3) -80005de0: ffe70713 addi a4,a4,-2 -80005de4: 40c787b3 sub a5,a5,a2 -80005de8: 40b787b3 sub a5,a5,a1 -80005dec: 00f71123 sh a5,2(a4) -80005df0: 0107d793 srli a5,a5,0x10 -80005df4: ffe68693 addi a3,a3,-2 -80005df8: 0017f613 andi a2,a5,1 -80005dfc: fcec1ee3 bne s8,a4,80005dd8 -80005e00: 00100d13 li s10,1 -80005e04: 000a8513 mv a0,s5 -80005e08: be8ff0ef jal ra,800051f0 -80005e0c: 04c95783 lhu a5,76(s2) -80005e10: fff40413 addi s0,s0,-1 -80005e14: 00048513 mv a0,s1 -80005e18: 00fd6d33 or s10,s10,a5 -80005e1c: 05a91623 sh s10,76(s2) -80005e20: bd0ff0ef jal ra,800051f0 -80005e24: f93414e3 bne s0,s3,80005dac -80005e28: 00040693 mv a3,s0 -80005e2c: 02812403 lw s0,40(sp) -80005e30: 02c12083 lw ra,44(sp) -80005e34: 01c12983 lw s3,28(sp) -80005e38: 01812a03 lw s4,24(sp) -80005e3c: 01412a83 lw s5,20(sp) -80005e40: 01012b03 lw s6,16(sp) -80005e44: 00c12b83 lw s7,12(sp) -80005e48: 00812c03 lw s8,8(sp) -80005e4c: 00412c83 lw s9,4(sp) -80005e50: 00012d03 lw s10,0(sp) -80005e54: 00090793 mv a5,s2 -80005e58: 00048513 mv a0,s1 -80005e5c: 02012903 lw s2,32(sp) -80005e60: 02412483 lw s1,36(sp) -80005e64: 00000713 li a4,0 -80005e68: 00000613 li a2,0 -80005e6c: 00000593 li a1,0 -80005e70: 03010113 addi sp,sp,48 -80005e74: a9dff06f j 80005910 -80005e78: 00000d13 li s10,0 -80005e7c: f8c6e4e3 bltu a3,a2,80005e04 -80005e80: f4dff06f j 80005dcc - -80005e84 : -80005e84: 00055703 lhu a4,0(a0) -80005e88: 00255783 lhu a5,2(a0) -80005e8c: 04070263 beqz a4,80005ed0 -80005e90: ffff8737 lui a4,0xffff8 -80005e94: 00e7e7b3 or a5,a5,a4 -80005e98: 00f59923 sh a5,18(a1) -80005e9c: 00255703 lhu a4,2(a0) -80005ea0: 000087b7 lui a5,0x8 -80005ea4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005ea8: 02f70e63 beq a4,a5,80005ee4 -80005eac: 00650793 addi a5,a0,6 -80005eb0: 01058593 addi a1,a1,16 -80005eb4: 01850513 addi a0,a0,24 -80005eb8: 00278793 addi a5,a5,2 -80005ebc: ffe7d703 lhu a4,-2(a5) -80005ec0: ffe58593 addi a1,a1,-2 -80005ec4: 00e59123 sh a4,2(a1) -80005ec8: fea798e3 bne a5,a0,80005eb8 -80005ecc: 00008067 ret -80005ed0: 00f59923 sh a5,18(a1) -80005ed4: 00255703 lhu a4,2(a0) -80005ed8: 000087b7 lui a5,0x8 -80005edc: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005ee0: fcf716e3 bne a4,a5,80005eac -80005ee4: 00650793 addi a5,a0,6 -80005ee8: 01a50513 addi a0,a0,26 -80005eec: 0007d703 lhu a4,0(a5) -80005ef0: 00278793 addi a5,a5,2 -80005ef4: 02071a63 bnez a4,80005f28 -80005ef8: fea79ae3 bne a5,a0,80005eec -80005efc: 01258713 addi a4,a1,18 -80005f00: 00058793 mv a5,a1 -80005f04: 00278793 addi a5,a5,2 -80005f08: fe079f23 sh zero,-2(a5) -80005f0c: fef71ce3 bne a4,a5,80005f04 -80005f10: 0125d783 lhu a5,18(a1) -80005f14: 00008737 lui a4,0x8 -80005f18: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005f1c: 00e7e7b3 or a5,a5,a4 -80005f20: 00f59923 sh a5,18(a1) -80005f24: 00008067 ret -80005f28: 01058713 addi a4,a1,16 -80005f2c: 00058793 mv a5,a1 -80005f30: 00278793 addi a5,a5,2 -80005f34: fe079f23 sh zero,-2(a5) -80005f38: fee79ce3 bne a5,a4,80005f30 -80005f3c: 7fffc7b7 lui a5,0x7fffc -80005f40: 00f5a823 sw a5,16(a1) -80005f44: 00008067 ret - -80005f48 : -80005f48: f7010113 addi sp,sp,-144 -80005f4c: 07512a23 sw s5,116(sp) -80005f50: 01255a83 lhu s5,18(a0) -80005f54: 000087b7 lui a5,0x8 -80005f58: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005f5c: 08812423 sw s0,136(sp) -80005f60: 08912223 sw s1,132(sp) -80005f64: 09212023 sw s2,128(sp) -80005f68: 07312e23 sw s3,124(sp) -80005f6c: 07612823 sw s6,112(sp) -80005f70: 08112623 sw ra,140(sp) -80005f74: 07412c23 sw s4,120(sp) -80005f78: 07712623 sw s7,108(sp) -80005f7c: 07812423 sw s8,104(sp) -80005f80: 07912223 sw s9,100(sp) -80005f84: 0157fb33 and s6,a5,s5 -80005f88: 00050493 mv s1,a0 -80005f8c: 00058913 mv s2,a1 -80005f90: 00060413 mv s0,a2 -80005f94: 00068993 mv s3,a3 -80005f98: 0afb1863 bne s6,a5,80006048 -80005f9c: b5cff0ef jal ra,800052f8 -80005fa0: 20051a63 bnez a0,800061b4 -80005fa4: 01295a03 lhu s4,18(s2) -80005fa8: 014b77b3 and a5,s6,s4 -80005fac: 23679263 bne a5,s6,800061d0 -80005fb0: 00090513 mv a0,s2 -80005fb4: b44ff0ef jal ra,800052f8 -80005fb8: 0a051463 bnez a0,80006060 -80005fbc: 00048513 mv a0,s1 -80005fc0: e0cff0ef jal ra,800055cc -80005fc4: 20051c63 bnez a0,800061dc -80005fc8: 000087b7 lui a5,0x8 -80005fcc: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005fd0: 0147fa33 and s4,a5,s4 -80005fd4: 010a1a13 slli s4,s4,0x10 -80005fd8: 010a5a13 srli s4,s4,0x10 -80005fdc: 2cfa1263 bne s4,a5,800062a0 -80005fe0: 00090513 mv a0,s2 -80005fe4: de8ff0ef jal ra,800055cc -80005fe8: 30051e63 bnez a0,80006304 -80005fec: 0124d783 lhu a5,18(s1) -80005ff0: 00fa77b3 and a5,s4,a5 -80005ff4: 21478263 beq a5,s4,800061f8 -80005ff8: 00048513 mv a0,s1 -80005ffc: 00c10593 addi a1,sp,12 -80006000: ba8ff0ef jal ra,800053a8 -80006004: 00090513 mv a0,s2 -80006008: 02810593 addi a1,sp,40 -8000600c: b9cff0ef jal ra,800053a8 -80006010: 00e15483 lhu s1,14(sp) -80006014: 02a15903 lhu s2,42(sp) -80006018: 08049a63 bnez s1,800060ac -8000601c: 01010793 addi a5,sp,16 -80006020: 02410693 addi a3,sp,36 -80006024: 2af68c63 beq a3,a5,800062dc -80006028: 00278793 addi a5,a5,2 -8000602c: ffe7d703 lhu a4,-2(a5) -80006030: fe070ae3 beqz a4,80006024 -80006034: 00c10513 addi a0,sp,12 -80006038: f5cff0ef jal ra,80005794 -8000603c: 40a004b3 neg s1,a0 -80006040: 02a15703 lhu a4,42(sp) -80006044: 06c0006f j 800060b0 -80006048: 0125da03 lhu s4,18(a1) -8000604c: 0147f733 and a4,a5,s4 -80006050: faf714e3 bne a4,a5,80005ff8 -80006054: 00058513 mv a0,a1 -80006058: aa0ff0ef jal ra,800052f8 -8000605c: f60506e3 beqz a0,80005fc8 -80006060: 01490713 addi a4,s2,20 -80006064: 00290913 addi s2,s2,2 -80006068: ffe95783 lhu a5,-2(s2) -8000606c: 00240413 addi s0,s0,2 -80006070: fef41f23 sh a5,-2(s0) -80006074: ff2718e3 bne a4,s2,80006064 -80006078: 08c12083 lw ra,140(sp) -8000607c: 08812403 lw s0,136(sp) -80006080: 08412483 lw s1,132(sp) -80006084: 08012903 lw s2,128(sp) -80006088: 07c12983 lw s3,124(sp) -8000608c: 07812a03 lw s4,120(sp) -80006090: 07412a83 lw s5,116(sp) -80006094: 07012b03 lw s6,112(sp) -80006098: 06c12b83 lw s7,108(sp) -8000609c: 06812c03 lw s8,104(sp) -800060a0: 06412c83 lw s9,100(sp) -800060a4: 09010113 addi sp,sp,144 -800060a8: 00008067 ret -800060ac: 00090713 mv a4,s2 -800060b0: 00090b13 mv s6,s2 -800060b4: 02c10793 addi a5,sp,44 -800060b8: 04010693 addi a3,sp,64 -800060bc: 02071263 bnez a4,800060e0 -800060c0: 22f68863 beq a3,a5,800062f0 -800060c4: 00278793 addi a5,a5,2 -800060c8: ffe7d703 lhu a4,-2(a5) -800060cc: fe070ae3 beqz a4,800060c0 -800060d0: 02810513 addi a0,sp,40 -800060d4: ec0ff0ef jal ra,80005794 -800060d8: 02a15703 lhu a4,42(sp) -800060dc: 40a90b33 sub s6,s2,a0 -800060e0: 02815783 lhu a5,40(sp) -800060e4: 03898a93 addi s5,s3,56 -800060e8: 02e99b23 sh a4,54(s3) -800060ec: 02f99a23 sh a5,52(s3) -800060f0: 04e98713 addi a4,s3,78 -800060f4: 000a8793 mv a5,s5 -800060f8: 00079023 sh zero,0(a5) -800060fc: 00278793 addi a5,a5,2 -80006100: fef71ce3 bne a4,a5,800060f8 -80006104: 04c98b93 addi s7,s3,76 -80006108: 00000a13 li s4,0 -8000610c: 02410913 addi s2,sp,36 -80006110: 01010c93 addi s9,sp,16 -80006114: 04610c13 addi s8,sp,70 -80006118: 00095503 lhu a0,0(s2) -8000611c: ffe90913 addi s2,s2,-2 -80006120: 12051e63 bnez a0,8000625c -80006124: 04c9d703 lhu a4,76(s3) -80006128: 000b8793 mv a5,s7 -8000612c: 00ea6a33 or s4,s4,a4 -80006130: ffe78793 addi a5,a5,-2 -80006134: 0007d703 lhu a4,0(a5) -80006138: 00e79123 sh a4,2(a5) -8000613c: ff579ae3 bne a5,s5,80006130 -80006140: 02099c23 sh zero,56(s3) -80006144: fd991ae3 bne s2,s9,80006118 -80006148: 03498713 addi a4,s3,52 -8000614c: 02810793 addi a5,sp,40 -80006150: 04210693 addi a3,sp,66 -80006154: 00075603 lhu a2,0(a4) -80006158: 00278793 addi a5,a5,2 -8000615c: 00270713 addi a4,a4,2 -80006160: fec79f23 sh a2,-2(a5) -80006164: fef698e3 bne a3,a5,80006154 -80006168: ffffc6b7 lui a3,0xffffc -8000616c: 016484b3 add s1,s1,s6 -80006170: 00268693 addi a3,a3,2 # ffffc002 <__BSS_END__+0x7ffe528a> -80006174: 00098793 mv a5,s3 -80006178: 04000713 li a4,64 -8000617c: 00d486b3 add a3,s1,a3 -80006180: 00000613 li a2,0 -80006184: 000a0593 mv a1,s4 -80006188: 02810513 addi a0,sp,40 -8000618c: f84ff0ef jal ra,80005910 -80006190: 00c15703 lhu a4,12(sp) -80006194: 02815783 lhu a5,40(sp) -80006198: 1af70c63 beq a4,a5,80006350 -8000619c: fff00793 li a5,-1 -800061a0: 02f11423 sh a5,40(sp) -800061a4: 00040593 mv a1,s0 -800061a8: 02810513 addi a0,sp,40 -800061ac: cd9ff0ef jal ra,80005e84 -800061b0: ec9ff06f j 80006078 -800061b4: 01448713 addi a4,s1,20 -800061b8: 00248493 addi s1,s1,2 -800061bc: ffe4d783 lhu a5,-2(s1) -800061c0: 00240413 addi s0,s0,2 -800061c4: fef41f23 sh a5,-2(s0) -800061c8: fee498e3 bne s1,a4,800061b8 -800061cc: eadff06f j 80006078 -800061d0: 00048513 mv a0,s1 -800061d4: bf8ff0ef jal ra,800055cc -800061d8: 0c050663 beqz a0,800062a4 -800061dc: 800155b7 lui a1,0x80015 -800061e0: 81458593 addi a1,a1,-2028 # 80014814 <__BSS_END__+0xffffda9c> -800061e4: 00090513 mv a0,s2 -800061e8: ac8ff0ef jal ra,800054b0 -800061ec: 12050e63 beqz a0,80006328 -800061f0: 01295a03 lhu s4,18(s2) -800061f4: dd5ff06f j 80005fc8 -800061f8: 00048513 mv a0,s1 -800061fc: bd0ff0ef jal ra,800055cc -80006200: 00051863 bnez a0,80006210 -80006204: 00090513 mv a0,s2 -80006208: bc4ff0ef jal ra,800055cc -8000620c: de0506e3 beqz a0,80005ff8 -80006210: 00048513 mv a0,s1 -80006214: 954ff0ef jal ra,80005368 -80006218: 00050493 mv s1,a0 -8000621c: 00090513 mv a0,s2 -80006220: 948ff0ef jal ra,80005368 -80006224: 12a48263 beq s1,a0,80006348 -80006228: ffff87b7 lui a5,0xffff8 -8000622c: 00f41923 sh a5,18(s0) -80006230: 01240713 addi a4,s0,18 -80006234: 00040793 mv a5,s0 -80006238: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe128a> -8000623c: fe079f23 sh zero,-2(a5) -80006240: fee79ce3 bne a5,a4,80006238 -80006244: 01245783 lhu a5,18(s0) -80006248: 00008737 lui a4,0x8 -8000624c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80006250: 00e7e7b3 or a5,a5,a4 -80006254: 00f41923 sh a5,18(s0) -80006258: e21ff06f j 80006078 -8000625c: 04410613 addi a2,sp,68 -80006260: 02810593 addi a1,sp,40 -80006264: ffdfe0ef jal ra,80005260 -80006268: 000b8613 mv a2,s7 -8000626c: 00000593 li a1,0 -80006270: 05c10713 addi a4,sp,92 -80006274: 00065503 lhu a0,0(a2) -80006278: 00075783 lhu a5,0(a4) -8000627c: ffe60613 addi a2,a2,-2 -80006280: ffe70713 addi a4,a4,-2 -80006284: 00a787b3 add a5,a5,a0 -80006288: 00b787b3 add a5,a5,a1 -8000628c: 00f61123 sh a5,2(a2) -80006290: 0107d793 srli a5,a5,0x10 -80006294: 0017f593 andi a1,a5,1 -80006298: fd871ee3 bne a4,s8,80006274 -8000629c: e89ff06f j 80006124 -800062a0: 0124da83 lhu s5,18(s1) -800062a4: 000087b7 lui a5,0x8 -800062a8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800062ac: 0157fab3 and s5,a5,s5 -800062b0: 010a9a93 slli s5,s5,0x10 -800062b4: 010ada93 srli s5,s5,0x10 -800062b8: d4fa90e3 bne s5,a5,80005ff8 -800062bc: 00048513 mv a0,s1 -800062c0: b0cff0ef jal ra,800055cc -800062c4: f40516e3 bnez a0,80006210 -800062c8: 01295783 lhu a5,18(s2) -800062cc: fff7c793 not a5,a5 -800062d0: 01179713 slli a4,a5,0x11 -800062d4: d20712e3 bnez a4,80005ff8 -800062d8: f2dff06f j 80006204 -800062dc: 01440793 addi a5,s0,20 -800062e0: 00240413 addi s0,s0,2 -800062e4: fe041f23 sh zero,-2(s0) -800062e8: fe879ce3 bne a5,s0,800062e0 -800062ec: d8dff06f j 80006078 -800062f0: 01440793 addi a5,s0,20 -800062f4: 00240413 addi s0,s0,2 -800062f8: fe041f23 sh zero,-2(s0) -800062fc: fef41ce3 bne s0,a5,800062f4 -80006300: d79ff06f j 80006078 -80006304: 800155b7 lui a1,0x80015 -80006308: 81458593 addi a1,a1,-2028 # 80014814 <__BSS_END__+0xffffda9c> -8000630c: 00048513 mv a0,s1 -80006310: 9a0ff0ef jal ra,800054b0 -80006314: 00050a63 beqz a0,80006328 -80006318: 0124d783 lhu a5,18(s1) -8000631c: 00fa77b3 and a5,s4,a5 -80006320: f9478ee3 beq a5,s4,800062bc -80006324: fa5ff06f j 800062c8 -80006328: 01040713 addi a4,s0,16 -8000632c: 00040793 mv a5,s0 -80006330: 00278793 addi a5,a5,2 -80006334: fe079f23 sh zero,-2(a5) -80006338: fee79ce3 bne a5,a4,80006330 -8000633c: 7fffc7b7 lui a5,0x7fffc -80006340: 00f42823 sw a5,16(s0) -80006344: d35ff06f j 80006078 -80006348: 00041923 sh zero,18(s0) -8000634c: ee5ff06f j 80006230 -80006350: 02011423 sh zero,40(sp) -80006354: e51ff06f j 800061a4 - -80006358 : -80006358: 01255783 lhu a5,18(a0) -8000635c: f5010113 addi sp,sp,-176 -80006360: 0a812423 sw s0,168(sp) -80006364: fff7c793 not a5,a5 -80006368: 0a912223 sw s1,164(sp) -8000636c: 0b212023 sw s2,160(sp) -80006370: 09612823 sw s6,144(sp) -80006374: 0a112623 sw ra,172(sp) -80006378: 09312e23 sw s3,156(sp) -8000637c: 09412c23 sw s4,152(sp) -80006380: 09512a23 sw s5,148(sp) -80006384: 09712623 sw s7,140(sp) -80006388: 09812423 sw s8,136(sp) -8000638c: 09912223 sw s9,132(sp) -80006390: 09a12023 sw s10,128(sp) -80006394: 07b12e23 sw s11,124(sp) -80006398: 01179713 slli a4,a5,0x11 -8000639c: 00050493 mv s1,a0 -800063a0: 00058913 mv s2,a1 -800063a4: 00060413 mv s0,a2 -800063a8: 00068b13 mv s6,a3 -800063ac: 00071663 bnez a4,800063b8 -800063b0: f49fe0ef jal ra,800052f8 -800063b4: 36051a63 bnez a0,80006728 -800063b8: 01295783 lhu a5,18(s2) -800063bc: fff7c793 not a5,a5 -800063c0: 01179713 slli a4,a5,0x11 -800063c4: 08070e63 beqz a4,80006460 -800063c8: 800159b7 lui s3,0x80015 -800063cc: 81498593 addi a1,s3,-2028 # 80014814 <__BSS_END__+0xffffda9c> -800063d0: 00048513 mv a0,s1 -800063d4: 8dcff0ef jal ra,800054b0 -800063d8: 10050463 beqz a0,800064e0 -800063dc: 0124d983 lhu s3,18(s1) -800063e0: 01295703 lhu a4,18(s2) -800063e4: 000087b7 lui a5,0x8 -800063e8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800063ec: 0137f9b3 and s3,a5,s3 -800063f0: 00e7fa33 and s4,a5,a4 -800063f4: 08f99a63 bne s3,a5,80006488 -800063f8: 00048513 mv a0,s1 -800063fc: 9d0ff0ef jal ra,800055cc -80006400: 10050863 beqz a0,80006510 -80006404: 013a1863 bne s4,s3,80006414 -80006408: 00090513 mv a0,s2 -8000640c: 9c0ff0ef jal ra,800055cc -80006410: 0e051063 bnez a0,800064f0 -80006414: 01440793 addi a5,s0,20 -80006418: 00240413 addi s0,s0,2 -8000641c: fe041f23 sh zero,-2(s0) -80006420: fef41ce3 bne s0,a5,80006418 -80006424: 0ac12083 lw ra,172(sp) -80006428: 0a812403 lw s0,168(sp) -8000642c: 0a412483 lw s1,164(sp) -80006430: 0a012903 lw s2,160(sp) -80006434: 09c12983 lw s3,156(sp) -80006438: 09812a03 lw s4,152(sp) -8000643c: 09412a83 lw s5,148(sp) -80006440: 09012b03 lw s6,144(sp) -80006444: 08c12b83 lw s7,140(sp) -80006448: 08812c03 lw s8,136(sp) -8000644c: 08412c83 lw s9,132(sp) -80006450: 08012d03 lw s10,128(sp) -80006454: 07c12d83 lw s11,124(sp) -80006458: 0b010113 addi sp,sp,176 -8000645c: 00008067 ret -80006460: 00090513 mv a0,s2 -80006464: e95fe0ef jal ra,800052f8 -80006468: f60500e3 beqz a0,800063c8 -8000646c: 01490713 addi a4,s2,20 -80006470: 00290913 addi s2,s2,2 -80006474: ffe95783 lhu a5,-2(s2) -80006478: 00240413 addi s0,s0,2 -8000647c: fef41f23 sh a5,-2(s0) -80006480: ff2718e3 bne a4,s2,80006470 -80006484: fa1ff06f j 80006424 -80006488: 08fa0663 beq s4,a5,80006514 -8000648c: 00048513 mv a0,s1 -80006490: 01c10593 addi a1,sp,28 -80006494: f15fe0ef jal ra,800053a8 -80006498: 03810593 addi a1,sp,56 -8000649c: 00090513 mv a0,s2 -800064a0: f09fe0ef jal ra,800053a8 -800064a4: 03a15b83 lhu s7,58(sp) -800064a8: 01e15483 lhu s1,30(sp) -800064ac: 0c0b9063 bnez s7,8000656c -800064b0: 03c10793 addi a5,sp,60 -800064b4: 05010b93 addi s7,sp,80 -800064b8: 34fb8063 beq s7,a5,800067f8 -800064bc: 00278793 addi a5,a5,2 -800064c0: ffe7d683 lhu a3,-2(a5) -800064c4: fe068ae3 beqz a3,800064b8 -800064c8: 03810513 addi a0,sp,56 -800064cc: ac8ff0ef jal ra,80005794 -800064d0: 40a007b3 neg a5,a0 -800064d4: 00f12623 sw a5,12(sp) -800064d8: 01e15703 lhu a4,30(sp) -800064dc: 0980006f j 80006574 -800064e0: 81498593 addi a1,s3,-2028 -800064e4: 00090513 mv a0,s2 -800064e8: fc9fe0ef jal ra,800054b0 -800064ec: ee0518e3 bnez a0,800063dc -800064f0: 01040713 addi a4,s0,16 -800064f4: 00040793 mv a5,s0 -800064f8: 00278793 addi a5,a5,2 -800064fc: fe079f23 sh zero,-2(a5) -80006500: fee79ce3 bne a5,a4,800064f8 -80006504: 7fffc7b7 lui a5,0x7fffc -80006508: 00f42823 sw a5,16(s0) -8000650c: f19ff06f j 80006424 -80006510: f73a1ee3 bne s4,s3,8000648c -80006514: 00090513 mv a0,s2 -80006518: 8b4ff0ef jal ra,800055cc -8000651c: f60508e3 beqz a0,8000648c -80006520: 00048513 mv a0,s1 -80006524: e45fe0ef jal ra,80005368 -80006528: 00050493 mv s1,a0 -8000652c: 00090513 mv a0,s2 -80006530: e39fe0ef jal ra,80005368 -80006534: 32a48463 beq s1,a0,8000685c -80006538: ffff87b7 lui a5,0xffff8 -8000653c: 00f41923 sh a5,18(s0) -80006540: 01240713 addi a4,s0,18 -80006544: 00040793 mv a5,s0 -80006548: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe128a> -8000654c: fe079f23 sh zero,-2(a5) -80006550: fee79ce3 bne a5,a4,80006548 -80006554: 01245783 lhu a5,18(s0) -80006558: 00008737 lui a4,0x8 -8000655c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80006560: 00e7e7b3 or a5,a5,a4 -80006564: 00f41923 sh a5,18(s0) -80006568: ebdff06f j 80006424 -8000656c: 01712623 sw s7,12(sp) -80006570: 00048713 mv a4,s1 -80006574: 00912423 sw s1,8(sp) -80006578: 02010793 addi a5,sp,32 -8000657c: 03410693 addi a3,sp,52 -80006580: 02071263 bnez a4,800065a4 -80006584: 28f68463 beq a3,a5,8000680c -80006588: 00278793 addi a5,a5,2 -8000658c: ffe7d703 lhu a4,-2(a5) -80006590: fe070ae3 beqz a4,80006584 -80006594: 01c10513 addi a0,sp,28 -80006598: 9fcff0ef jal ra,80005794 -8000659c: 40a487b3 sub a5,s1,a0 -800065a0: 00f12423 sw a5,8(sp) -800065a4: 03812703 lw a4,56(sp) -800065a8: 038b0d13 addi s10,s6,56 -800065ac: 000d0793 mv a5,s10 -800065b0: 02eb2a23 sw a4,52(s6) -800065b4: 04eb0493 addi s1,s6,78 -800065b8: 00278793 addi a5,a5,2 -800065bc: fe079f23 sh zero,-2(a5) -800065c0: fe979ce3 bne a5,s1,800065b8 -800065c4: 03810513 addi a0,sp,56 -800065c8: bc1fe0ef jal ra,80005188 -800065cc: 02215c03 lhu s8,34(sp) -800065d0: 000109b7 lui s3,0x10 -800065d4: 05010b93 addi s7,sp,80 -800065d8: 010c1a13 slli s4,s8,0x10 -800065dc: 418a0a33 sub s4,s4,s8 -800065e0: 03a10a93 addi s5,sp,58 -800065e4: fff98993 addi s3,s3,-1 # ffff <_start-0x7fff0001> -800065e8: 06e10c93 addi s9,sp,110 -800065ec: 05610913 addi s2,sp,86 -800065f0: 03c15503 lhu a0,60(sp) -800065f4: 03e15783 lhu a5,62(sp) -800065f8: 00098d93 mv s11,s3 -800065fc: 01051513 slli a0,a0,0x10 -80006600: 00f50533 add a0,a0,a5 -80006604: 00aa6863 bltu s4,a0,80006614 -80006608: 03855533 divu a0,a0,s8 -8000660c: 01051d93 slli s11,a0,0x10 -80006610: 010ddd93 srli s11,s11,0x10 -80006614: 05410613 addi a2,sp,84 -80006618: 01c10593 addi a1,sp,28 -8000661c: 000d8513 mv a0,s11 -80006620: c41fe0ef jal ra,80005260 -80006624: 03c10613 addi a2,sp,60 -80006628: 05810793 addi a5,sp,88 -8000662c: 00278793 addi a5,a5,2 -80006630: 00260613 addi a2,a2,2 -80006634: ffe7d503 lhu a0,-2(a5) -80006638: ffe65583 lhu a1,-2(a2) -8000663c: 10b51463 bne a0,a1,80006744 -80006640: ff9796e3 bne a5,s9,8000662c -80006644: 00000513 li a0,0 -80006648: 06c10593 addi a1,sp,108 -8000664c: 000b8613 mv a2,s7 -80006650: 00065783 lhu a5,0(a2) -80006654: 0005d803 lhu a6,0(a1) -80006658: ffe60613 addi a2,a2,-2 -8000665c: 40a787b3 sub a5,a5,a0 -80006660: 410787b3 sub a5,a5,a6 -80006664: 00f61123 sh a5,2(a2) -80006668: 0107d793 srli a5,a5,0x10 -8000666c: ffe58593 addi a1,a1,-2 -80006670: 0017f513 andi a0,a5,1 -80006674: fd561ee3 bne a2,s5,80006650 -80006678: 01bd1023 sh s11,0(s10) -8000667c: 03c10793 addi a5,sp,60 -80006680: 00278793 addi a5,a5,2 -80006684: 0007d603 lhu a2,0(a5) -80006688: fec79f23 sh a2,-2(a5) -8000668c: ff779ae3 bne a5,s7,80006680 -80006690: 04011823 sh zero,80(sp) -80006694: 002d0d13 addi s10,s10,2 -80006698: f5a49ce3 bne s1,s10,800065f0 -8000669c: 00000593 li a1,0 -800066a0: 03c10793 addi a5,sp,60 -800066a4: 05210693 addi a3,sp,82 -800066a8: 00278793 addi a5,a5,2 -800066ac: ffe7d703 lhu a4,-2(a5) -800066b0: 00e5e5b3 or a1,a1,a4 -800066b4: fed79ae3 bne a5,a3,800066a8 -800066b8: 00b035b3 snez a1,a1 -800066bc: 034b0713 addi a4,s6,52 -800066c0: 03810793 addi a5,sp,56 -800066c4: 00075603 lhu a2,0(a4) -800066c8: 00278793 addi a5,a5,2 -800066cc: 00270713 addi a4,a4,2 -800066d0: fec79f23 sh a2,-2(a5) -800066d4: fef698e3 bne a3,a5,800066c4 -800066d8: 00c12783 lw a5,12(sp) -800066dc: 00812703 lw a4,8(sp) -800066e0: 000046b7 lui a3,0x4 -800066e4: fff68693 addi a3,a3,-1 # 3fff <_start-0x7fffc001> -800066e8: 40e78bb3 sub s7,a5,a4 -800066ec: 00db86b3 add a3,s7,a3 -800066f0: 000b0793 mv a5,s6 -800066f4: 04000713 li a4,64 -800066f8: 00000613 li a2,0 -800066fc: 03810513 addi a0,sp,56 -80006700: a10ff0ef jal ra,80005910 -80006704: 01c15703 lhu a4,28(sp) -80006708: 03815783 lhu a5,56(sp) -8000670c: 14f70063 beq a4,a5,8000684c -80006710: fff00793 li a5,-1 -80006714: 02f11c23 sh a5,56(sp) -80006718: 00040593 mv a1,s0 -8000671c: 03810513 addi a0,sp,56 -80006720: f64ff0ef jal ra,80005e84 -80006724: d01ff06f j 80006424 -80006728: 01448713 addi a4,s1,20 -8000672c: 00248493 addi s1,s1,2 -80006730: ffe4d783 lhu a5,-2(s1) -80006734: 00240413 addi s0,s0,2 -80006738: fef41f23 sh a5,-2(s0) -8000673c: fee498e3 bne s1,a4,8000672c -80006740: ce5ff06f j 80006424 -80006744: f0a5f0e3 bgeu a1,a0,80006644 -80006748: fffd8793 addi a5,s11,-1 -8000674c: 01079893 slli a7,a5,0x10 -80006750: 0108d893 srli a7,a7,0x10 -80006754: 00000513 li a0,0 -80006758: 03410593 addi a1,sp,52 -8000675c: 06c10613 addi a2,sp,108 -80006760: 00065783 lhu a5,0(a2) -80006764: 0005d803 lhu a6,0(a1) -80006768: ffe60613 addi a2,a2,-2 -8000676c: 40a787b3 sub a5,a5,a0 -80006770: 410787b3 sub a5,a5,a6 -80006774: 00f61123 sh a5,2(a2) -80006778: 0107d793 srli a5,a5,0x10 -8000677c: ffe58593 addi a1,a1,-2 -80006780: 0017f513 andi a0,a5,1 -80006784: fd261ee3 bne a2,s2,80006760 -80006788: 03c10613 addi a2,sp,60 -8000678c: 05810793 addi a5,sp,88 -80006790: 00278793 addi a5,a5,2 -80006794: 00260613 addi a2,a2,2 -80006798: ffe7d503 lhu a0,-2(a5) -8000679c: ffe65583 lhu a1,-2(a2) -800067a0: 00b51863 bne a0,a1,800067b0 -800067a4: ff9796e3 bne a5,s9,80006790 -800067a8: 00088d93 mv s11,a7 -800067ac: e99ff06f j 80006644 -800067b0: fea5fce3 bgeu a1,a0,800067a8 -800067b4: ffed8d93 addi s11,s11,-2 -800067b8: 010d9d93 slli s11,s11,0x10 -800067bc: 010ddd93 srli s11,s11,0x10 -800067c0: 00000513 li a0,0 -800067c4: 03410593 addi a1,sp,52 -800067c8: 06c10613 addi a2,sp,108 -800067cc: 00065783 lhu a5,0(a2) -800067d0: 0005d803 lhu a6,0(a1) -800067d4: ffe60613 addi a2,a2,-2 -800067d8: 40a787b3 sub a5,a5,a0 -800067dc: 410787b3 sub a5,a5,a6 -800067e0: 00f61123 sh a5,2(a2) -800067e4: 0107d793 srli a5,a5,0x10 -800067e8: ffe58593 addi a1,a1,-2 -800067ec: 0017f513 andi a0,a5,1 -800067f0: fd261ee3 bne a2,s2,800067cc -800067f4: e51ff06f j 80006644 -800067f8: 01440793 addi a5,s0,20 -800067fc: 00240413 addi s0,s0,2 -80006800: fe041f23 sh zero,-2(s0) -80006804: fe879ce3 bne a5,s0,800067fc -80006808: c1dff06f j 80006424 -8000680c: 01c15703 lhu a4,28(sp) -80006810: 03815783 lhu a5,56(sp) -80006814: 04f70063 beq a4,a5,80006854 -80006818: ffff87b7 lui a5,0xffff8 -8000681c: 00f41923 sh a5,18(s0) -80006820: 01240713 addi a4,s0,18 -80006824: 00040793 mv a5,s0 -80006828: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe128a> -8000682c: fe079f23 sh zero,-2(a5) -80006830: fee79ce3 bne a5,a4,80006828 -80006834: 01245783 lhu a5,18(s0) -80006838: 00008737 lui a4,0x8 -8000683c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80006840: 00e7e7b3 or a5,a5,a4 -80006844: 00f41923 sh a5,18(s0) -80006848: bddff06f j 80006424 -8000684c: 02011c23 sh zero,56(sp) -80006850: ec9ff06f j 80006718 -80006854: 00041923 sh zero,18(s0) -80006858: fc9ff06f j 80006820 -8000685c: 00041923 sh zero,18(s0) -80006860: ce1ff06f j 80006540 - -80006864 : -80006864: fd010113 addi sp,sp,-48 -80006868: 02812423 sw s0,40(sp) -8000686c: 02112623 sw ra,44(sp) -80006870: 00058413 mv s0,a1 -80006874: 00410793 addi a5,sp,4 -80006878: 01e10713 addi a4,sp,30 -8000687c: 00278793 addi a5,a5,2 -80006880: fe079f23 sh zero,-2(a5) -80006884: fee79ce3 bne a5,a4,8000687c -80006888: 00e55603 lhu a2,14(a0) -8000688c: 01061793 slli a5,a2,0x10 -80006890: 4107d793 srai a5,a5,0x10 -80006894: 0607ca63 bltz a5,80006908 -80006898: 000087b7 lui a5,0x8 -8000689c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800068a0: 00011223 sh zero,4(sp) -800068a4: 00f67633 and a2,a2,a5 -800068a8: 06f60c63 beq a2,a5,80006920 -800068ac: 00e50793 addi a5,a0,14 -800068b0: 00c11323 sh a2,6(sp) -800068b4: 00a10713 addi a4,sp,10 -800068b8: ffe78793 addi a5,a5,-2 -800068bc: 0007d683 lhu a3,0(a5) -800068c0: 00270713 addi a4,a4,2 -800068c4: fed71f23 sh a3,-2(a4) -800068c8: fef518e3 bne a0,a5,800068b8 -800068cc: 02061263 bnez a2,800068f0 -800068d0: 00011423 sh zero,8(sp) -800068d4: 00040593 mv a1,s0 -800068d8: 00410513 addi a0,sp,4 -800068dc: da8ff0ef jal ra,80005e84 -800068e0: 02c12083 lw ra,44(sp) -800068e4: 02812403 lw s0,40(sp) -800068e8: 03010113 addi sp,sp,48 -800068ec: 00008067 ret -800068f0: 00100793 li a5,1 -800068f4: fff00593 li a1,-1 -800068f8: 00410513 addi a0,sp,4 -800068fc: 00f11423 sh a5,8(sp) -80006900: ce9fe0ef jal ra,800055e8 -80006904: fd1ff06f j 800068d4 -80006908: fff00793 li a5,-1 -8000690c: 00f11223 sh a5,4(sp) -80006910: 000087b7 lui a5,0x8 -80006914: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80006918: 00f67633 and a2,a2,a5 -8000691c: f8f618e3 bne a2,a5,800068ac -80006920: 00050793 mv a5,a0 -80006924: 00e50693 addi a3,a0,14 -80006928: 0007d703 lhu a4,0(a5) -8000692c: 00278793 addi a5,a5,2 -80006930: 04071c63 bnez a4,80006988 -80006934: fef69ae3 bne a3,a5,80006928 -80006938: 01440713 addi a4,s0,20 -8000693c: 00040793 mv a5,s0 -80006940: 00278793 addi a5,a5,2 -80006944: fe079f23 sh zero,-2(a5) -80006948: fee79ce3 bne a5,a4,80006940 -8000694c: 01240713 addi a4,s0,18 -80006950: 00040793 mv a5,s0 -80006954: 00278793 addi a5,a5,2 -80006958: fe079f23 sh zero,-2(a5) -8000695c: fee79ce3 bne a5,a4,80006954 -80006960: 01245783 lhu a5,18(s0) -80006964: 00008737 lui a4,0x8 -80006968: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -8000696c: 00e7e7b3 or a5,a5,a4 -80006970: 00f41923 sh a5,18(s0) -80006974: 00e51783 lh a5,14(a0) -80006978: f607d4e3 bgez a5,800068e0 -8000697c: 00040513 mv a0,s0 -80006980: 99dfe0ef jal ra,8000531c -80006984: f5dff06f j 800068e0 -80006988: 01040713 addi a4,s0,16 -8000698c: 00040793 mv a5,s0 -80006990: 00278793 addi a5,a5,2 -80006994: fe079f23 sh zero,-2(a5) -80006998: fee79ce3 bne a5,a4,80006990 -8000699c: 7fffc7b7 lui a5,0x7fffc -800069a0: 00f42823 sw a5,16(s0) -800069a4: f3dff06f j 800068e0 - -800069a8 <_ldtoa_r>: -800069a8: 0005ae83 lw t4,0(a1) -800069ac: 0045ae03 lw t3,4(a1) -800069b0: 0085a303 lw t1,8(a1) -800069b4: 00c5a583 lw a1,12(a1) -800069b8: e1010113 addi sp,sp,-496 -800069bc: 04052883 lw a7,64(a0) -800069c0: 02b12e23 sw a1,60(sp) -800069c4: fff00593 li a1,-1 -800069c8: 16b12023 sw a1,352(sp) -800069cc: 09000593 li a1,144 -800069d0: 1e812423 sw s0,488(sp) -800069d4: 1d712623 sw s7,460(sp) -800069d8: 1e112623 sw ra,492(sp) -800069dc: 1e912223 sw s1,484(sp) -800069e0: 1f212023 sw s2,480(sp) -800069e4: 1d312e23 sw s3,476(sp) -800069e8: 1d412c23 sw s4,472(sp) -800069ec: 1d512a23 sw s5,468(sp) -800069f0: 1d612823 sw s6,464(sp) -800069f4: 1d812423 sw s8,456(sp) -800069f8: 1d912223 sw s9,452(sp) -800069fc: 1da12023 sw s10,448(sp) -80006a00: 1bb12e23 sw s11,444(sp) -80006a04: 03d12823 sw t4,48(sp) -80006a08: 03c12a23 sw t3,52(sp) -80006a0c: 02612c23 sw t1,56(sp) -80006a10: 16b12223 sw a1,356(sp) -80006a14: 00c12023 sw a2,0(sp) -80006a18: 00d12423 sw a3,8(sp) -80006a1c: 00e12623 sw a4,12(sp) -80006a20: 01012c23 sw a6,24(sp) -80006a24: 00050b93 mv s7,a0 -80006a28: 00078413 mv s0,a5 -80006a2c: 02088263 beqz a7,80006a50 <_ldtoa_r+0xa8> -80006a30: 04452703 lw a4,68(a0) -80006a34: 00100793 li a5,1 -80006a38: 00088593 mv a1,a7 -80006a3c: 00e797b3 sll a5,a5,a4 -80006a40: 00e8a223 sw a4,4(a7) -80006a44: 00f8a423 sw a5,8(a7) -80006a48: 768010ef jal ra,800081b0 <_Bfree> -80006a4c: 040ba023 sw zero,64(s7) -80006a50: 06010a13 addi s4,sp,96 -80006a54: 03010513 addi a0,sp,48 -80006a58: 000a0593 mv a1,s4 -80006a5c: e09ff0ef jal ra,80006864 -80006a60: 000a0513 mv a0,s4 -80006a64: 905fe0ef jal ra,80005368 -80006a68: 20050c63 beqz a0,80006c80 <_ldtoa_r+0x2d8> -80006a6c: 00012703 lw a4,0(sp) -80006a70: 00100793 li a5,1 -80006a74: 00f42023 sw a5,0(s0) -80006a78: 00300793 li a5,3 -80006a7c: 20f70a63 beq a4,a5,80006c90 <_ldtoa_r+0x2e8> -80006a80: 01400793 li a5,20 -80006a84: 00f12223 sw a5,4(sp) -80006a88: 60071ee3 bnez a4,800078a4 <_ldtoa_r+0xefc> -80006a8c: 07215783 lhu a5,114(sp) -80006a90: 16412703 lw a4,356(sp) -80006a94: fff7c793 not a5,a5 -80006a98: 00e12a23 sw a4,20(sp) -80006a9c: 01179713 slli a4,a5,0x11 -80006aa0: 00071863 bnez a4,80006ab0 <_ldtoa_r+0x108> -80006aa4: 000a0513 mv a0,s4 -80006aa8: 851fe0ef jal ra,800052f8 -80006aac: 440512e3 bnez a0,800076f0 <_ldtoa_r+0xd48> -80006ab0: 09000793 li a5,144 -80006ab4: 16f12223 sw a5,356(sp) -80006ab8: 07c10713 addi a4,sp,124 -80006abc: 000a0793 mv a5,s4 -80006ac0: 07410613 addi a2,sp,116 -80006ac4: 00278793 addi a5,a5,2 # 7fffc002 <_start-0x3ffe> -80006ac8: ffe7d683 lhu a3,-2(a5) -80006acc: 00270713 addi a4,a4,2 -80006ad0: fed71f23 sh a3,-2(a4) -80006ad4: fec798e3 bne a5,a2,80006ac4 <_ldtoa_r+0x11c> -80006ad8: 08e15603 lhu a2,142(sp) -80006adc: 00012823 sw zero,16(sp) -80006ae0: 01061793 slli a5,a2,0x10 -80006ae4: 4107d793 srai a5,a5,0x10 -80006ae8: 0007de63 bgez a5,80006b04 <_ldtoa_r+0x15c> -80006aec: 01161613 slli a2,a2,0x11 -80006af0: 000107b7 lui a5,0x10 -80006af4: 01165613 srli a2,a2,0x11 -80006af8: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -80006afc: 08c11723 sh a2,142(sp) -80006b00: 00f12823 sw a5,16(sp) -80006b04: 80015b37 lui s6,0x80015 -80006b08: 814b0d13 addi s10,s6,-2028 # 80014814 <__BSS_END__+0xffffda9c> -80006b0c: 014d0d93 addi s11,s10,20 -80006b10: 00000693 li a3,0 -80006b14: 09810793 addi a5,sp,152 -80006b18: 000d8713 mv a4,s11 -80006b1c: 0ac10c93 addi s9,sp,172 -80006b20: 0080006f j 80006b28 <_ldtoa_r+0x180> -80006b24: 00075683 lhu a3,0(a4) -80006b28: 00278793 addi a5,a5,2 -80006b2c: fed79f23 sh a3,-2(a5) -80006b30: 00270713 addi a4,a4,2 -80006b34: ff9798e3 bne a5,s9,80006b24 <_ldtoa_r+0x17c> -80006b38: 16060863 beqz a2,80006ca8 <_ldtoa_r+0x300> -80006b3c: 000087b7 lui a5,0x8 -80006b40: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80006b44: 58f60ce3 beq a2,a5,800078dc <_ldtoa_r+0xf34> -80006b48: 08c11783 lh a5,140(sp) -80006b4c: 6207d2e3 bgez a5,80007970 <_ldtoa_r+0xfc8> -80006b50: 07c10593 addi a1,sp,124 -80006b54: 000d8513 mv a0,s11 -80006b58: 959fe0ef jal ra,800054b0 -80006b5c: 16050263 beqz a0,80006cc0 <_ldtoa_r+0x318> -80006b60: 100548e3 bltz a0,80007470 <_ldtoa_r+0xac8> -80006b64: 08e15783 lhu a5,142(sp) -80006b68: 68079ee3 bnez a5,80007a04 <_ldtoa_r+0x105c> -80006b6c: 08c11783 lh a5,140(sp) -80006b70: 00000493 li s1,0 -80006b74: 16010993 addi s3,sp,352 -80006b78: 0207c463 bltz a5,80006ba0 <_ldtoa_r+0x1f8> -80006b7c: 118d0413 addi s0,s10,280 -80006b80: 07c10613 addi a2,sp,124 -80006b84: 00098693 mv a3,s3 -80006b88: 00060593 mv a1,a2 -80006b8c: 00040513 mv a0,s0 -80006b90: bb8ff0ef jal ra,80005f48 -80006b94: 08c11783 lh a5,140(sp) -80006b98: fff48493 addi s1,s1,-1 -80006b9c: fe07d2e3 bgez a5,80006b80 <_ldtoa_r+0x1d8> -80006ba0: 0d010413 addi s0,sp,208 -80006ba4: 0e810c13 addi s8,sp,232 -80006ba8: 00040713 mv a4,s0 -80006bac: 07c10793 addi a5,sp,124 -80006bb0: 09010613 addi a2,sp,144 -80006bb4: 00278793 addi a5,a5,2 -80006bb8: ffe7d683 lhu a3,-2(a5) -80006bbc: 00270713 addi a4,a4,2 -80006bc0: fed71f23 sh a3,-2(a4) -80006bc4: fec798e3 bne a5,a2,80006bb4 <_ldtoa_r+0x20c> -80006bc8: 00000693 li a3,0 -80006bcc: 09810793 addi a5,sp,152 -80006bd0: 000d8713 mv a4,s11 -80006bd4: 0080006f j 80006bdc <_ldtoa_r+0x234> -80006bd8: 00075683 lhu a3,0(a4) -80006bdc: 00278793 addi a5,a5,2 -80006be0: fed79f23 sh a3,-2(a5) -80006be4: 00270713 addi a4,a4,2 -80006be8: ff9798e3 bne a5,s9,80006bd8 <_ldtoa_r+0x230> -80006bec: 028d0a93 addi s5,s10,40 -80006bf0: 12cd0c93 addi s9,s10,300 -80006bf4: fffff937 lui s2,0xfffff -80006bf8: 118d0d13 addi s10,s10,280 -80006bfc: 00c0006f j 80006c08 <_ldtoa_r+0x260> -80006c00: 014c8c93 addi s9,s9,20 -80006c04: 014a8a93 addi s5,s5,20 -80006c08: 00040593 mv a1,s0 -80006c0c: 000d8513 mv a0,s11 -80006c10: 8a1fe0ef jal ra,800054b0 -80006c14: 00040593 mv a1,s0 -80006c18: 04a05663 blez a0,80006c64 <_ldtoa_r+0x2bc> -80006c1c: 000c8513 mv a0,s9 -80006c20: 891fe0ef jal ra,800054b0 -80006c24: 00098693 mv a3,s3 -80006c28: 00040613 mv a2,s0 -80006c2c: 00040593 mv a1,s0 -80006c30: 02054263 bltz a0,80006c54 <_ldtoa_r+0x2ac> -80006c34: 000a8513 mv a0,s5 -80006c38: b10ff0ef jal ra,80005f48 -80006c3c: 09810613 addi a2,sp,152 -80006c40: 00098693 mv a3,s3 -80006c44: 00060593 mv a1,a2 -80006c48: 000a8513 mv a0,s5 -80006c4c: afcff0ef jal ra,80005f48 -80006c50: 012484b3 add s1,s1,s2 -80006c54: 01f95793 srli a5,s2,0x1f -80006c58: 012787b3 add a5,a5,s2 -80006c5c: 4017d913 srai s2,a5,0x1 -80006c60: fbaa90e3 bne s5,s10,80006c00 <_ldtoa_r+0x258> -80006c64: 09810613 addi a2,sp,152 -80006c68: 00098693 mv a3,s3 -80006c6c: 000d8593 mv a1,s11 -80006c70: 00060513 mv a0,a2 -80006c74: ee4ff0ef jal ra,80006358 -80006c78: 12410913 addi s2,sp,292 -80006c7c: 0580006f j 80006cd4 <_ldtoa_r+0x32c> -80006c80: 00012703 lw a4,0(sp) -80006c84: 00042023 sw zero,0(s0) -80006c88: 00300793 li a5,3 -80006c8c: def71ae3 bne a4,a5,80006a80 <_ldtoa_r+0xd8> -80006c90: 00812483 lw s1,8(sp) -80006c94: 00912223 sw s1,4(sp) -80006c98: 02a00793 li a5,42 -80006c9c: de97d8e3 bge a5,s1,80006a8c <_ldtoa_r+0xe4> -80006ca0: 00f12223 sw a5,4(sp) -80006ca4: de9ff06f j 80006a8c <_ldtoa_r+0xe4> -80006ca8: 07c10793 addi a5,sp,124 -80006cac: 08e10693 addi a3,sp,142 -80006cb0: 0007d703 lhu a4,0(a5) -80006cb4: 00278793 addi a5,a5,2 -80006cb8: e8071ce3 bnez a4,80006b50 <_ldtoa_r+0x1a8> -80006cbc: fef69ae3 bne a3,a5,80006cb0 <_ldtoa_r+0x308> -80006cc0: 00000493 li s1,0 -80006cc4: 12410913 addi s2,sp,292 -80006cc8: 16010993 addi s3,sp,352 -80006ccc: 0d010413 addi s0,sp,208 -80006cd0: 0e810c13 addi s8,sp,232 -80006cd4: 00040593 mv a1,s0 -80006cd8: 09810513 addi a0,sp,152 -80006cdc: eccfe0ef jal ra,800053a8 -80006ce0: 09810713 addi a4,sp,152 -80006ce4: 00040793 mv a5,s0 -80006ce8: 00278793 addi a5,a5,2 -80006cec: ffe7d683 lhu a3,-2(a5) -80006cf0: 00270713 addi a4,a4,2 -80006cf4: fed71f23 sh a3,-2(a4) -80006cf8: ff8798e3 bne a5,s8,80006ce8 <_ldtoa_r+0x340> -80006cfc: 00040593 mv a1,s0 -80006d00: 07c10513 addi a0,sp,124 -80006d04: 0a011823 sh zero,176(sp) -80006d08: ea0fe0ef jal ra,800053a8 -80006d0c: 07c10793 addi a5,sp,124 -80006d10: 00240413 addi s0,s0,2 -80006d14: ffe45703 lhu a4,-2(s0) -80006d18: 00278793 addi a5,a5,2 -80006d1c: fee79f23 sh a4,-2(a5) -80006d20: ff8418e3 bne s0,s8,80006d10 <_ldtoa_r+0x368> -80006d24: 09810513 addi a0,sp,152 -80006d28: 00098613 mv a2,s3 -80006d2c: 07c10593 addi a1,sp,124 -80006d30: 08011a23 sh zero,148(sp) -80006d34: fedfe0ef jal ra,80005d20 -80006d38: 1ac15503 lhu a0,428(sp) -80006d3c: 1c051463 bnez a0,80006f04 <_ldtoa_r+0x55c> -80006d40: 09410c93 addi s9,sp,148 -80006d44: 07e10413 addi s0,sp,126 -80006d48: 0b610a93 addi s5,sp,182 -80006d4c: 814b0593 addi a1,s6,-2028 -80006d50: 07c10513 addi a0,sp,124 -80006d54: f5cfe0ef jal ra,800054b0 -80006d58: 1a050663 beqz a0,80006f04 <_ldtoa_r+0x55c> -80006d5c: 00000713 li a4,0 -80006d60: 000c8693 mv a3,s9 -80006d64: 01c0006f j 80006d80 <_ldtoa_r+0x3d8> -80006d68: 00171713 slli a4,a4,0x1 -80006d6c: 00f69023 sh a5,0(a3) -80006d70: 01071713 slli a4,a4,0x10 -80006d74: ffe68693 addi a3,a3,-2 -80006d78: 01075713 srli a4,a4,0x10 -80006d7c: 04868463 beq a3,s0,80006dc4 <_ldtoa_r+0x41c> -80006d80: 0006d783 lhu a5,0(a3) -80006d84: 01079613 slli a2,a5,0x10 -80006d88: 41065613 srai a2,a2,0x10 -80006d8c: 00179793 slli a5,a5,0x1 -80006d90: 00065463 bgez a2,80006d98 <_ldtoa_r+0x3f0> -80006d94: 00176713 ori a4,a4,1 -80006d98: 01079793 slli a5,a5,0x10 -80006d9c: 0107d793 srli a5,a5,0x10 -80006da0: 00277613 andi a2,a4,2 -80006da4: 0017e593 ori a1,a5,1 -80006da8: fc0600e3 beqz a2,80006d68 <_ldtoa_r+0x3c0> -80006dac: 00171713 slli a4,a4,0x1 -80006db0: 00b69023 sh a1,0(a3) -80006db4: 01071713 slli a4,a4,0x10 -80006db8: ffe68693 addi a3,a3,-2 -80006dbc: 01075713 srli a4,a4,0x10 -80006dc0: fc8690e3 bne a3,s0,80006d80 <_ldtoa_r+0x3d8> -80006dc4: 0b410713 addi a4,sp,180 -80006dc8: 07c10793 addi a5,sp,124 -80006dcc: 00278793 addi a5,a5,2 -80006dd0: ffe7d683 lhu a3,-2(a5) -80006dd4: 00270713 addi a4,a4,2 -80006dd8: fed71f23 sh a3,-2(a4) -80006ddc: ff9798e3 bne a5,s9,80006dcc <_ldtoa_r+0x424> -80006de0: 0c011623 sh zero,204(sp) -80006de4: 00000713 li a4,0 -80006de8: 0cc10693 addi a3,sp,204 -80006dec: 01c0006f j 80006e08 <_ldtoa_r+0x460> -80006df0: 00171713 slli a4,a4,0x1 -80006df4: 00f69023 sh a5,0(a3) -80006df8: 01071713 slli a4,a4,0x10 -80006dfc: ffe68693 addi a3,a3,-2 -80006e00: 01075713 srli a4,a4,0x10 -80006e04: 05568463 beq a3,s5,80006e4c <_ldtoa_r+0x4a4> -80006e08: 0006d783 lhu a5,0(a3) -80006e0c: 01079613 slli a2,a5,0x10 -80006e10: 41065613 srai a2,a2,0x10 -80006e14: 00179793 slli a5,a5,0x1 -80006e18: 00065463 bgez a2,80006e20 <_ldtoa_r+0x478> -80006e1c: 00176713 ori a4,a4,1 -80006e20: 01079793 slli a5,a5,0x10 -80006e24: 0107d793 srli a5,a5,0x10 -80006e28: 00277613 andi a2,a4,2 -80006e2c: 0017e593 ori a1,a5,1 -80006e30: fc0600e3 beqz a2,80006df0 <_ldtoa_r+0x448> -80006e34: 00171713 slli a4,a4,0x1 -80006e38: 00b69023 sh a1,0(a3) -80006e3c: 01071713 slli a4,a4,0x10 -80006e40: ffe68693 addi a3,a3,-2 -80006e44: 01075713 srli a4,a4,0x10 -80006e48: fd5690e3 bne a3,s5,80006e08 <_ldtoa_r+0x460> -80006e4c: 00000713 li a4,0 -80006e50: 0cc10693 addi a3,sp,204 -80006e54: 01c0006f j 80006e70 <_ldtoa_r+0x4c8> -80006e58: 00171713 slli a4,a4,0x1 -80006e5c: 00f69023 sh a5,0(a3) -80006e60: 01071713 slli a4,a4,0x10 -80006e64: ffe68693 addi a3,a3,-2 -80006e68: 01075713 srli a4,a4,0x10 -80006e6c: 05568463 beq a3,s5,80006eb4 <_ldtoa_r+0x50c> -80006e70: 0006d783 lhu a5,0(a3) -80006e74: 01079613 slli a2,a5,0x10 -80006e78: 41065613 srai a2,a2,0x10 -80006e7c: 00179793 slli a5,a5,0x1 -80006e80: 00065463 bgez a2,80006e88 <_ldtoa_r+0x4e0> -80006e84: 00176713 ori a4,a4,1 -80006e88: 01079793 slli a5,a5,0x10 -80006e8c: 0107d793 srli a5,a5,0x10 -80006e90: 00277613 andi a2,a4,2 -80006e94: 0017e593 ori a1,a5,1 -80006e98: fc0600e3 beqz a2,80006e58 <_ldtoa_r+0x4b0> -80006e9c: 00171713 slli a4,a4,0x1 -80006ea0: 00b69023 sh a1,0(a3) -80006ea4: 01071713 slli a4,a4,0x10 -80006ea8: ffe68693 addi a3,a3,-2 -80006eac: 01075713 srli a4,a4,0x10 -80006eb0: fd5690e3 bne a3,s5,80006e70 <_ldtoa_r+0x4c8> -80006eb4: 00000613 li a2,0 -80006eb8: 000c8693 mv a3,s9 -80006ebc: 0cc10713 addi a4,sp,204 -80006ec0: 0006d583 lhu a1,0(a3) -80006ec4: 00075783 lhu a5,0(a4) -80006ec8: ffe68693 addi a3,a3,-2 -80006ecc: ffe70713 addi a4,a4,-2 -80006ed0: 00b787b3 add a5,a5,a1 -80006ed4: 00c787b3 add a5,a5,a2 -80006ed8: 00f69123 sh a5,2(a3) -80006edc: 0107d793 srli a5,a5,0x10 -80006ee0: 0017f613 andi a2,a5,1 -80006ee4: fd571ee3 bne a4,s5,80006ec0 <_ldtoa_r+0x518> -80006ee8: 09810513 addi a0,sp,152 -80006eec: 00098613 mv a2,s3 -80006ef0: 07c10593 addi a1,sp,124 -80006ef4: e2dfe0ef jal ra,80005d20 -80006ef8: 1ac15503 lhu a0,428(sp) -80006efc: fff48493 addi s1,s1,-1 -80006f00: e40506e3 beqz a0,80006d4c <_ldtoa_r+0x3a4> -80006f04: 01012783 lw a5,16(sp) -80006f08: 04078263 beqz a5,80006f4c <_ldtoa_r+0x5a4> -80006f0c: 00012703 lw a4,0(sp) -80006f10: 02d00793 li a5,45 -80006f14: 12f10223 sb a5,292(sp) -80006f18: 00300793 li a5,3 -80006f1c: 00412403 lw s0,4(sp) -80006f20: 04f70263 beq a4,a5,80006f64 <_ldtoa_r+0x5bc> -80006f24: 00a00793 li a5,10 -80006f28: 20f504e3 beq a0,a5,80007930 <_ldtoa_r+0xf88> -80006f2c: 03050513 addi a0,a0,48 -80006f30: 02e00793 li a5,46 -80006f34: 12a102a3 sb a0,293(sp) -80006f38: 12f10323 sb a5,294(sp) -80006f3c: 7a044263 bltz s0,800076e0 <_ldtoa_r+0xd38> -80006f40: 12710793 addi a5,sp,295 -80006f44: 00f12823 sw a5,16(sp) -80006f48: 04c0006f j 80006f94 <_ldtoa_r+0x5ec> -80006f4c: 00012703 lw a4,0(sp) -80006f50: 02000793 li a5,32 -80006f54: 12f10223 sb a5,292(sp) -80006f58: 00300793 li a5,3 -80006f5c: 00412403 lw s0,4(sp) -80006f60: fcf712e3 bne a4,a5,80006f24 <_ldtoa_r+0x57c> -80006f64: 00940433 add s0,s0,s1 -80006f68: 02a00793 li a5,42 -80006f6c: fa87dce3 bge a5,s0,80006f24 <_ldtoa_r+0x57c> -80006f70: 00a00793 li a5,10 -80006f74: 18f508e3 beq a0,a5,80007904 <_ldtoa_r+0xf5c> -80006f78: 02e00793 li a5,46 -80006f7c: 03050513 addi a0,a0,48 -80006f80: 12f10323 sb a5,294(sp) -80006f84: 12710793 addi a5,sp,295 -80006f88: 12a102a3 sb a0,293(sp) -80006f8c: 02a00413 li s0,42 -80006f90: 00f12823 sw a5,16(sp) -80006f94: 00000c93 li s9,0 -80006f98: 0b410a93 addi s5,sp,180 -80006f9c: 00912e23 sw s1,28(sp) -80006fa0: 000c8493 mv s1,s9 -80006fa4: 000a8c93 mv s9,s5 -80006fa8: 00098a93 mv s5,s3 -80006fac: 01012983 lw s3,16(sp) -80006fb0: 09410d93 addi s11,sp,148 -80006fb4: 07e10c13 addi s8,sp,126 -80006fb8: 0b610d13 addi s10,sp,182 -80006fbc: 00000693 li a3,0 -80006fc0: 000d8613 mv a2,s11 -80006fc4: 01c0006f j 80006fe0 <_ldtoa_r+0x638> -80006fc8: 00169693 slli a3,a3,0x1 -80006fcc: 00f61023 sh a5,0(a2) -80006fd0: 01069693 slli a3,a3,0x10 -80006fd4: ffe60613 addi a2,a2,-2 -80006fd8: 0106d693 srli a3,a3,0x10 -80006fdc: 05860463 beq a2,s8,80007024 <_ldtoa_r+0x67c> -80006fe0: 00065783 lhu a5,0(a2) -80006fe4: 01079593 slli a1,a5,0x10 -80006fe8: 4105d593 srai a1,a1,0x10 -80006fec: 00179793 slli a5,a5,0x1 -80006ff0: 0005d463 bgez a1,80006ff8 <_ldtoa_r+0x650> -80006ff4: 0016e693 ori a3,a3,1 -80006ff8: 01079793 slli a5,a5,0x10 -80006ffc: 0107d793 srli a5,a5,0x10 -80007000: 0026f593 andi a1,a3,2 -80007004: 0017e513 ori a0,a5,1 -80007008: fc0580e3 beqz a1,80006fc8 <_ldtoa_r+0x620> -8000700c: 00169693 slli a3,a3,0x1 -80007010: 00a61023 sh a0,0(a2) -80007014: 01069693 slli a3,a3,0x10 -80007018: ffe60613 addi a2,a2,-2 -8000701c: 0106d693 srli a3,a3,0x10 -80007020: fd8610e3 bne a2,s8,80006fe0 <_ldtoa_r+0x638> -80007024: 000c8693 mv a3,s9 -80007028: 07c10793 addi a5,sp,124 -8000702c: 00278793 addi a5,a5,2 -80007030: ffe7d603 lhu a2,-2(a5) -80007034: 00268693 addi a3,a3,2 -80007038: fec69f23 sh a2,-2(a3) -8000703c: ffb798e3 bne a5,s11,8000702c <_ldtoa_r+0x684> -80007040: 0c011623 sh zero,204(sp) -80007044: 00000693 li a3,0 -80007048: 0cc10613 addi a2,sp,204 -8000704c: 01c0006f j 80007068 <_ldtoa_r+0x6c0> -80007050: 00169693 slli a3,a3,0x1 -80007054: 00f61023 sh a5,0(a2) -80007058: 01069693 slli a3,a3,0x10 -8000705c: ffe60613 addi a2,a2,-2 -80007060: 0106d693 srli a3,a3,0x10 -80007064: 05a60463 beq a2,s10,800070ac <_ldtoa_r+0x704> -80007068: 00065783 lhu a5,0(a2) -8000706c: 01079593 slli a1,a5,0x10 -80007070: 4105d593 srai a1,a1,0x10 -80007074: 00179793 slli a5,a5,0x1 -80007078: 0005d463 bgez a1,80007080 <_ldtoa_r+0x6d8> -8000707c: 0016e693 ori a3,a3,1 -80007080: 01079793 slli a5,a5,0x10 -80007084: 0107d793 srli a5,a5,0x10 -80007088: 0026f593 andi a1,a3,2 -8000708c: 0017e513 ori a0,a5,1 -80007090: fc0580e3 beqz a1,80007050 <_ldtoa_r+0x6a8> -80007094: 00169693 slli a3,a3,0x1 -80007098: 00a61023 sh a0,0(a2) -8000709c: 01069693 slli a3,a3,0x10 -800070a0: ffe60613 addi a2,a2,-2 -800070a4: 0106d693 srli a3,a3,0x10 -800070a8: fda610e3 bne a2,s10,80007068 <_ldtoa_r+0x6c0> -800070ac: 00000693 li a3,0 -800070b0: 0cc10613 addi a2,sp,204 -800070b4: 01c0006f j 800070d0 <_ldtoa_r+0x728> -800070b8: 00169693 slli a3,a3,0x1 -800070bc: 00f61023 sh a5,0(a2) -800070c0: 01069693 slli a3,a3,0x10 -800070c4: ffe60613 addi a2,a2,-2 -800070c8: 0106d693 srli a3,a3,0x10 -800070cc: 05a60463 beq a2,s10,80007114 <_ldtoa_r+0x76c> -800070d0: 00065783 lhu a5,0(a2) -800070d4: 01079593 slli a1,a5,0x10 -800070d8: 4105d593 srai a1,a1,0x10 -800070dc: 00179793 slli a5,a5,0x1 -800070e0: 0005d463 bgez a1,800070e8 <_ldtoa_r+0x740> -800070e4: 0016e693 ori a3,a3,1 -800070e8: 01079793 slli a5,a5,0x10 -800070ec: 0107d793 srli a5,a5,0x10 -800070f0: 0026f593 andi a1,a3,2 -800070f4: 0017e513 ori a0,a5,1 -800070f8: fc0580e3 beqz a1,800070b8 <_ldtoa_r+0x710> -800070fc: 00169693 slli a3,a3,0x1 -80007100: 00a61023 sh a0,0(a2) -80007104: 01069693 slli a3,a3,0x10 -80007108: ffe60613 addi a2,a2,-2 -8000710c: 0106d693 srli a3,a3,0x10 -80007110: fda610e3 bne a2,s10,800070d0 <_ldtoa_r+0x728> -80007114: 00000593 li a1,0 -80007118: 000d8613 mv a2,s11 -8000711c: 0cc10693 addi a3,sp,204 -80007120: 00065503 lhu a0,0(a2) -80007124: 0006d783 lhu a5,0(a3) -80007128: ffe60613 addi a2,a2,-2 -8000712c: ffe68693 addi a3,a3,-2 -80007130: 00a787b3 add a5,a5,a0 -80007134: 00b787b3 add a5,a5,a1 -80007138: 00f61123 sh a5,2(a2) -8000713c: 0107d793 srli a5,a5,0x10 -80007140: 0017f593 andi a1,a5,1 -80007144: fda69ee3 bne a3,s10,80007120 <_ldtoa_r+0x778> -80007148: 000a8613 mv a2,s5 -8000714c: 07c10593 addi a1,sp,124 -80007150: 09810513 addi a0,sp,152 -80007154: bcdfe0ef jal ra,80005d20 -80007158: 1ac15783 lhu a5,428(sp) -8000715c: 009986b3 add a3,s3,s1 -80007160: 00148493 addi s1,s1,1 -80007164: 03078613 addi a2,a5,48 -80007168: 00c68023 sb a2,0(a3) -8000716c: e49458e3 bge s0,s1,80006fbc <_ldtoa_r+0x614> -80007170: 01012703 lw a4,16(sp) -80007174: 01c12483 lw s1,28(sp) -80007178: 00140993 addi s3,s0,1 -8000717c: 013709b3 add s3,a4,s3 -80007180: 00870cb3 add s9,a4,s0 -80007184: 00400713 li a4,4 -80007188: 06f75e63 bge a4,a5,80007204 <_ldtoa_r+0x85c> -8000718c: 00500713 li a4,5 -80007190: 00e780e3 beq a5,a4,80007990 <_ldtoa_r+0xfe8> -80007194: ffe9c783 lbu a5,-2(s3) -80007198: ffe98713 addi a4,s3,-2 -8000719c: 07f7f793 andi a5,a5,127 -800071a0: 7c044063 bltz s0,80007960 <_ldtoa_r+0xfb8> -800071a4: 02e00693 li a3,46 -800071a8: 04d78263 beq a5,a3,800071ec <_ldtoa_r+0x844> -800071ac: 00178693 addi a3,a5,1 -800071b0: 00d70023 sb a3,0(a4) -800071b4: 03800693 li a3,56 -800071b8: 03000593 li a1,48 -800071bc: 02e00613 li a2,46 -800071c0: 03800513 li a0,56 -800071c4: 00f6c863 blt a3,a5,800071d4 <_ldtoa_r+0x82c> -800071c8: 03c0006f j 80007204 <_ldtoa_r+0x85c> -800071cc: 00d70023 sb a3,0(a4) -800071d0: 02f57a63 bgeu a0,a5,80007204 <_ldtoa_r+0x85c> -800071d4: 00b70023 sb a1,0(a4) -800071d8: fff70713 addi a4,a4,-1 -800071dc: 00074783 lbu a5,0(a4) -800071e0: 07f7f793 andi a5,a5,127 -800071e4: 00178693 addi a3,a5,1 -800071e8: fec792e3 bne a5,a2,800071cc <_ldtoa_r+0x824> -800071ec: fff74783 lbu a5,-1(a4) -800071f0: 03800693 li a3,56 -800071f4: 00f6f2e3 bgeu a3,a5,800079f8 <_ldtoa_r+0x1050> -800071f8: 03100793 li a5,49 -800071fc: 00148493 addi s1,s1,1 -80007200: fef70fa3 sb a5,-1(a4) -80007204: 800155b7 lui a1,0x80015 -80007208: 00048613 mv a2,s1 -8000720c: a8c58593 addi a1,a1,-1396 # 80014a8c <__BSS_END__+0xffffdd14> -80007210: 000c8513 mv a0,s9 -80007214: 008020ef jal ra,8000921c -80007218: 07215783 lhu a5,114(sp) -8000721c: 01412703 lw a4,20(sp) -80007220: 16912823 sw s1,368(sp) -80007224: fff7c793 not a5,a5 -80007228: 16e12223 sw a4,356(sp) -8000722c: 01179713 slli a4,a5,0x11 -80007230: 00071e63 bnez a4,8000724c <_ldtoa_r+0x8a4> -80007234: 000a0513 mv a0,s4 -80007238: b94fe0ef jal ra,800055cc -8000723c: 22051063 bnez a0,8000745c <_ldtoa_r+0xab4> -80007240: 000a0513 mv a0,s4 -80007244: 8b4fe0ef jal ra,800052f8 -80007248: 20051a63 bnez a0,8000745c <_ldtoa_r+0xab4> -8000724c: 00c12683 lw a3,12(sp) -80007250: 12414783 lbu a5,292(sp) -80007254: 00148713 addi a4,s1,1 -80007258: 00e6a023 sw a4,0(a3) -8000725c: 0c0780e3 beqz a5,80007b1c <_ldtoa_r+0x1174> -80007260: 02e00713 li a4,46 -80007264: 06e78063 beq a5,a4,800072c4 <_ldtoa_r+0x91c> -80007268: 00090793 mv a5,s2 -8000726c: 02e00693 li a3,46 -80007270: 0080006f j 80007278 <_ldtoa_r+0x8d0> -80007274: 04d70a63 beq a4,a3,800072c8 <_ldtoa_r+0x920> -80007278: 00178793 addi a5,a5,1 -8000727c: 0007c703 lbu a4,0(a5) -80007280: fe071ae3 bnez a4,80007274 <_ldtoa_r+0x8cc> -80007284: 04500693 li a3,69 -80007288: 00f96663 bltu s2,a5,80007294 <_ldtoa_r+0x8ec> -8000728c: 0140006f j 800072a0 <_ldtoa_r+0x8f8> -80007290: 01278863 beq a5,s2,800072a0 <_ldtoa_r+0x8f8> -80007294: fff78793 addi a5,a5,-1 -80007298: 0007c703 lbu a4,0(a5) -8000729c: fed71ae3 bne a4,a3,80007290 <_ldtoa_r+0x8e8> -800072a0: 00078023 sb zero,0(a5) -800072a4: 00090793 mv a5,s2 -800072a8: 02000693 li a3,32 -800072ac: 02d00613 li a2,45 -800072b0: 0007c703 lbu a4,0(a5) -800072b4: 00d70463 beq a4,a3,800072bc <_ldtoa_r+0x914> -800072b8: 02c71a63 bne a4,a2,800072ec <_ldtoa_r+0x944> -800072bc: 00178793 addi a5,a5,1 -800072c0: ff1ff06f j 800072b0 <_ldtoa_r+0x908> -800072c4: 00090793 mv a5,s2 -800072c8: 0017c703 lbu a4,1(a5) -800072cc: 00178793 addi a5,a5,1 -800072d0: fee78fa3 sb a4,-1(a5) -800072d4: fa0708e3 beqz a4,80007284 <_ldtoa_r+0x8dc> -800072d8: 0017c703 lbu a4,1(a5) -800072dc: 00178793 addi a5,a5,1 -800072e0: fee78fa3 sb a4,-1(a5) -800072e4: fe0712e3 bnez a4,800072c8 <_ldtoa_r+0x920> -800072e8: f9dff06f j 80007284 <_ldtoa_r+0x8dc> -800072ec: 00090413 mv s0,s2 -800072f0: 00c0006f j 800072fc <_ldtoa_r+0x954> -800072f4: 0007c703 lbu a4,0(a5) -800072f8: 00068413 mv s0,a3 -800072fc: 00e40023 sb a4,0(s0) -80007300: 00140693 addi a3,s0,1 -80007304: 00178793 addi a5,a5,1 -80007308: fe0716e3 bnez a4,800072f4 <_ldtoa_r+0x94c> -8000730c: 00012683 lw a3,0(sp) -80007310: 00200793 li a5,2 -80007314: fff44703 lbu a4,-1(s0) -80007318: 12f68663 beq a3,a5,80007444 <_ldtoa_r+0xa9c> -8000731c: 00412783 lw a5,4(sp) -80007320: 00078693 mv a3,a5 -80007324: 0097d463 bge a5,s1,8000732c <_ldtoa_r+0x984> -80007328: 00048693 mv a3,s1 -8000732c: 03000793 li a5,48 -80007330: 02f71663 bne a4,a5,8000735c <_ldtoa_r+0x9b4> -80007334: 412407b3 sub a5,s0,s2 -80007338: 02f6d263 bge a3,a5,8000735c <_ldtoa_r+0x9b4> -8000733c: 03000613 li a2,48 -80007340: 0080006f j 80007348 <_ldtoa_r+0x9a0> -80007344: 00e6dc63 bge a3,a4,8000735c <_ldtoa_r+0x9b4> -80007348: fff40413 addi s0,s0,-1 -8000734c: fff44783 lbu a5,-1(s0) -80007350: 00040023 sb zero,0(s0) -80007354: 41240733 sub a4,s0,s2 -80007358: fec786e3 beq a5,a2,80007344 <_ldtoa_r+0x99c> -8000735c: 00012703 lw a4,0(sp) -80007360: 00300793 li a5,3 -80007364: 0af70263 beq a4,a5,80007408 <_ldtoa_r+0xa60> -80007368: 00812783 lw a5,8(sp) -8000736c: 040ba223 sw zero,68(s7) -80007370: 00978613 addi a2,a5,9 -80007374: 01700793 li a5,23 -80007378: 0cc7f263 bgeu a5,a2,8000743c <_ldtoa_r+0xa94> -8000737c: 00100713 li a4,1 -80007380: 00400793 li a5,4 -80007384: 00179793 slli a5,a5,0x1 -80007388: 01478693 addi a3,a5,20 -8000738c: 00070593 mv a1,a4 -80007390: 00170713 addi a4,a4,1 -80007394: fed678e3 bgeu a2,a3,80007384 <_ldtoa_r+0x9dc> -80007398: 04bba223 sw a1,68(s7) -8000739c: 000b8513 mv a0,s7 -800073a0: 569000ef jal ra,80008108 <_Balloc> -800073a4: 04aba023 sw a0,64(s7) -800073a8: 00090593 mv a1,s2 -800073ac: 00050493 mv s1,a0 -800073b0: 1bc020ef jal ra,8000956c -800073b4: 01812783 lw a5,24(sp) -800073b8: 00078863 beqz a5,800073c8 <_ldtoa_r+0xa20> -800073bc: 41240433 sub s0,s0,s2 -800073c0: 00848433 add s0,s1,s0 -800073c4: 0087a023 sw s0,0(a5) -800073c8: 1ec12083 lw ra,492(sp) -800073cc: 1e812403 lw s0,488(sp) -800073d0: 00048513 mv a0,s1 -800073d4: 1e012903 lw s2,480(sp) -800073d8: 1e412483 lw s1,484(sp) -800073dc: 1dc12983 lw s3,476(sp) -800073e0: 1d812a03 lw s4,472(sp) -800073e4: 1d412a83 lw s5,468(sp) -800073e8: 1d012b03 lw s6,464(sp) -800073ec: 1cc12b83 lw s7,460(sp) -800073f0: 1c812c03 lw s8,456(sp) -800073f4: 1c412c83 lw s9,452(sp) -800073f8: 1c012d03 lw s10,448(sp) -800073fc: 1bc12d83 lw s11,444(sp) -80007400: 1f010113 addi sp,sp,496 -80007404: 00008067 ret -80007408: 00412783 lw a5,4(sp) -8000740c: 009784b3 add s1,a5,s1 -80007410: 4a04c063 bltz s1,800078b0 <_ldtoa_r+0xf08> -80007414: 00c12783 lw a5,12(sp) -80007418: 00812703 lw a4,8(sp) -8000741c: 0007a783 lw a5,0(a5) -80007420: 00f707b3 add a5,a4,a5 -80007424: 00f12423 sw a5,8(sp) -80007428: 00812783 lw a5,8(sp) -8000742c: 040ba223 sw zero,68(s7) -80007430: 00378613 addi a2,a5,3 -80007434: 01700793 li a5,23 -80007438: f4c7e2e3 bltu a5,a2,8000737c <_ldtoa_r+0x9d4> -8000743c: 00000593 li a1,0 -80007440: f5dff06f j 8000739c <_ldtoa_r+0x9f4> -80007444: 03000793 li a5,48 -80007448: f2f710e3 bne a4,a5,80007368 <_ldtoa_r+0x9c0> -8000744c: 412407b3 sub a5,s0,s2 -80007450: 00100693 li a3,1 -80007454: eef6c4e3 blt a3,a5,8000733c <_ldtoa_r+0x994> -80007458: f11ff06f j 80007368 <_ldtoa_r+0x9c0> -8000745c: 00c12703 lw a4,12(sp) -80007460: 000027b7 lui a5,0x2 -80007464: 70f78793 addi a5,a5,1807 # 270f <_start-0x7fffd8f1> -80007468: 00f72023 sw a5,0(a4) -8000746c: e39ff06f j 800072a4 <_ldtoa_r+0x8fc> -80007470: 0b410a93 addi s5,sp,180 -80007474: 000a8713 mv a4,s5 -80007478: 07c10793 addi a5,sp,124 -8000747c: 09010613 addi a2,sp,144 -80007480: 00278793 addi a5,a5,2 -80007484: ffe7d683 lhu a3,-2(a5) -80007488: 00270713 addi a4,a4,2 -8000748c: fed71f23 sh a3,-2(a4) -80007490: fec798e3 bne a5,a2,80007480 <_ldtoa_r+0xad8> -80007494: 000047b7 lui a5,0x4 -80007498: 08e78793 addi a5,a5,142 # 408e <_start-0x7fffbf72> -8000749c: 0cf11323 sh a5,198(sp) -800074a0: 000087b7 lui a5,0x8 -800074a4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800074a8: 00f12e23 sw a5,28(sp) -800074ac: ffffc7b7 lui a5,0xffffc -800074b0: 12410913 addi s2,sp,292 -800074b4: 0d010413 addi s0,sp,208 -800074b8: 01000e13 li t3,16 -800074bc: 0c8d0313 addi t1,s10,200 -800074c0: 00278793 addi a5,a5,2 # ffffc002 <__BSS_END__+0x7ffe528a> -800074c4: 03712423 sw s7,40(sp) -800074c8: 03212223 sw s2,36(sp) -800074cc: 00000493 li s1,0 -800074d0: 00040913 mv s2,s0 -800074d4: 16010993 addi s3,sp,352 -800074d8: 0aa10c13 addi s8,sp,170 -800074dc: 02f12023 sw a5,32(sp) -800074e0: 000e0b93 mv s7,t3 -800074e4: 00030413 mv s0,t1 -800074e8: 00098693 mv a3,s3 -800074ec: 09810613 addi a2,sp,152 -800074f0: 000a8593 mv a1,s5 -800074f4: 00040513 mv a0,s0 -800074f8: e61fe0ef jal ra,80006358 -800074fc: 04c10713 addi a4,sp,76 -80007500: 09810793 addi a5,sp,152 -80007504: 00278793 addi a5,a5,2 -80007508: ffe7d683 lhu a3,-2(a5) -8000750c: 00270713 addi a4,a4,2 -80007510: fed71f23 sh a3,-2(a4) -80007514: ff9798e3 bne a5,s9,80007504 <_ldtoa_r+0xb5c> -80007518: 01c12783 lw a5,28(sp) -8000751c: 05e15583 lhu a1,94(sp) -80007520: 00f5f633 and a2,a1,a5 -80007524: 02012783 lw a5,32(sp) -80007528: 00f60533 add a0,a2,a5 -8000752c: 38a05c63 blez a0,800078c4 <_ldtoa_r+0xf1c> -80007530: 09000613 li a2,144 -80007534: 40a60633 sub a2,a2,a0 -80007538: 00090713 mv a4,s2 -8000753c: 04c10793 addi a5,sp,76 -80007540: 00278793 addi a5,a5,2 -80007544: ffe7d683 lhu a3,-2(a5) -80007548: 00270713 addi a4,a4,2 -8000754c: fed71f23 sh a3,-2(a4) -80007550: ff4798e3 bne a5,s4,80007540 <_ldtoa_r+0xb98> -80007554: 06c05463 blez a2,800075bc <_ldtoa_r+0xc14> -80007558: 00f00793 li a5,15 -8000755c: 00090713 mv a4,s2 -80007560: 02c7dc63 bge a5,a2,80007598 <_ldtoa_r+0xbf0> -80007564: ff060613 addi a2,a2,-16 -80007568: 00465693 srli a3,a2,0x4 -8000756c: 00168713 addi a4,a3,1 -80007570: 00171713 slli a4,a4,0x1 -80007574: 00e90733 add a4,s2,a4 -80007578: 00090793 mv a5,s2 -8000757c: 00278793 addi a5,a5,2 -80007580: fe079f23 sh zero,-2(a5) -80007584: fee79ce3 bne a5,a4,8000757c <_ldtoa_r+0xbd4> -80007588: 08000613 li a2,128 -8000758c: 40a60633 sub a2,a2,a0 -80007590: 00469693 slli a3,a3,0x4 -80007594: 40d60633 sub a2,a2,a3 -80007598: 00161613 slli a2,a2,0x1 -8000759c: 00cd0633 add a2,s10,a2 -800075a0: 00075783 lhu a5,0(a4) -800075a4: 23065683 lhu a3,560(a2) -800075a8: 00d7f7b3 and a5,a5,a3 -800075ac: 00f71023 sh a5,0(a4) -800075b0: 01059593 slli a1,a1,0x10 -800075b4: 4105d593 srai a1,a1,0x10 -800075b8: 1405cc63 bltz a1,80007710 <_ldtoa_r+0xd68> -800075bc: 09810793 addi a5,sp,152 -800075c0: 00090713 mv a4,s2 -800075c4: 0007d603 lhu a2,0(a5) -800075c8: 00075683 lhu a3,0(a4) -800075cc: 00278793 addi a5,a5,2 -800075d0: 00270713 addi a4,a4,2 -800075d4: 02d61463 bne a2,a3,800075fc <_ldtoa_r+0xc54> -800075d8: fefc16e3 bne s8,a5,800075c4 <_ldtoa_r+0xc1c> -800075dc: 000a8713 mv a4,s5 -800075e0: 09810793 addi a5,sp,152 -800075e4: 00278793 addi a5,a5,2 -800075e8: ffe7d683 lhu a3,-2(a5) -800075ec: 00270713 addi a4,a4,2 -800075f0: fed71f23 sh a3,-2(a4) -800075f4: ff9798e3 bne a5,s9,800075e4 <_ldtoa_r+0xc3c> -800075f8: 017484b3 add s1,s1,s7 -800075fc: 01440413 addi s0,s0,20 -80007600: 12cd0793 addi a5,s10,300 -80007604: 001bdb93 srli s7,s7,0x1 -80007608: eef410e3 bne s0,a5,800074e8 <_ldtoa_r+0xb40> -8000760c: 0c615783 lhu a5,198(sp) -80007610: 08e15703 lhu a4,142(sp) -80007614: 00090413 mv s0,s2 -80007618: 02812b83 lw s7,40(sp) -8000761c: 00e787b3 add a5,a5,a4 -80007620: ffffc737 lui a4,0xffffc -80007624: f7270713 addi a4,a4,-142 # ffffbf72 <__BSS_END__+0x7ffe51fa> -80007628: 02412903 lw s2,36(sp) -8000762c: 00e787b3 add a5,a5,a4 -80007630: 0cf11323 sh a5,198(sp) -80007634: 07c10713 addi a4,sp,124 -80007638: 000a8793 mv a5,s5 -8000763c: 0c810613 addi a2,sp,200 -80007640: 00278793 addi a5,a5,2 -80007644: ffe7d683 lhu a3,-2(a5) -80007648: 00270713 addi a4,a4,2 -8000764c: fed71f23 sh a3,-2(a4) -80007650: fec798e3 bne a5,a2,80007640 <_ldtoa_r+0xc98> -80007654: 00000713 li a4,0 -80007658: 09810793 addi a5,sp,152 -8000765c: 0080006f j 80007664 <_ldtoa_r+0xcbc> -80007660: 000dd703 lhu a4,0(s11) -80007664: 00278793 addi a5,a5,2 -80007668: fee79f23 sh a4,-2(a5) -8000766c: 002d8d93 addi s11,s11,2 -80007670: ff9798e3 bne a5,s9,80007660 <_ldtoa_r+0xcb8> -80007674: 028d0c93 addi s9,s10,40 -80007678: 00001c37 lui s8,0x1 -8000767c: 118d0d13 addi s10,s10,280 -80007680: 0100006f j 80007690 <_ldtoa_r+0xce8> -80007684: 001c5c13 srli s8,s8,0x1 -80007688: 2dac8863 beq s9,s10,80007958 <_ldtoa_r+0xfb0> -8000768c: 014c8c93 addi s9,s9,20 -80007690: 000a8593 mv a1,s5 -80007694: 000d0513 mv a0,s10 -80007698: e19fd0ef jal ra,800054b0 -8000769c: 000a8593 mv a1,s5 -800076a0: 2aa04c63 bgtz a0,80007958 <_ldtoa_r+0xfb0> -800076a4: 000c8513 mv a0,s9 -800076a8: e09fd0ef jal ra,800054b0 -800076ac: fca04ce3 bgtz a0,80007684 <_ldtoa_r+0xcdc> -800076b0: 00098693 mv a3,s3 -800076b4: 000a8613 mv a2,s5 -800076b8: 000a8593 mv a1,s5 -800076bc: 000c8513 mv a0,s9 -800076c0: c99fe0ef jal ra,80006358 -800076c4: 09810613 addi a2,sp,152 -800076c8: 00098693 mv a3,s3 -800076cc: 00060593 mv a1,a2 -800076d0: 000c8513 mv a0,s9 -800076d4: 875fe0ef jal ra,80005f48 -800076d8: 018484b3 add s1,s1,s8 -800076dc: fa9ff06f j 80007684 <_ldtoa_r+0xcdc> -800076e0: 1ac15783 lhu a5,428(sp) -800076e4: 12610c93 addi s9,sp,294 -800076e8: 12710993 addi s3,sp,295 -800076ec: a99ff06f j 80007184 <_ldtoa_r+0x7dc> -800076f0: 12410913 addi s2,sp,292 -800076f4: 800155b7 lui a1,0x80015 -800076f8: a6858593 addi a1,a1,-1432 # 80014a68 <__BSS_END__+0xffffdcf0> -800076fc: 00090513 mv a0,s2 -80007700: 000024b7 lui s1,0x2 -80007704: 319010ef jal ra,8000921c -80007708: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -8000770c: b0dff06f j 80007218 <_ldtoa_r+0x870> -80007710: 04c10793 addi a5,sp,76 -80007714: 00090713 mv a4,s2 -80007718: 00c0006f j 80007724 <_ldtoa_r+0xd7c> -8000771c: 05e10693 addi a3,sp,94 -80007720: e8f68ee3 beq a3,a5,800075bc <_ldtoa_r+0xc14> -80007724: 0007d603 lhu a2,0(a5) -80007728: 00075683 lhu a3,0(a4) -8000772c: 00278793 addi a5,a5,2 -80007730: 00270713 addi a4,a4,2 -80007734: fed604e3 beq a2,a3,8000771c <_ldtoa_r+0xd74> -80007738: 0e215783 lhu a5,226(sp) -8000773c: 01c12703 lw a4,28(sp) -80007740: 00f777b3 and a5,a4,a5 -80007744: 00e79e63 bne a5,a4,80007760 <_ldtoa_r+0xdb8> -80007748: 00090513 mv a0,s2 -8000774c: badfd0ef jal ra,800052f8 -80007750: e60516e3 bnez a0,800075bc <_ldtoa_r+0xc14> -80007754: 00090513 mv a0,s2 -80007758: e75fd0ef jal ra,800055cc -8000775c: e60510e3 bnez a0,800075bc <_ldtoa_r+0xc14> -80007760: 0ec10593 addi a1,sp,236 -80007764: 000d8513 mv a0,s11 -80007768: c41fd0ef jal ra,800053a8 -8000776c: 10810593 addi a1,sp,264 -80007770: 00090513 mv a0,s2 -80007774: c35fd0ef jal ra,800053a8 -80007778: 0ec15603 lhu a2,236(sp) -8000777c: 10a15503 lhu a0,266(sp) -80007780: 0ee15883 lhu a7,238(sp) -80007784: fff64613 not a2,a2 -80007788: 01061613 slli a2,a2,0x10 -8000778c: 01065613 srli a2,a2,0x10 -80007790: 0ec11623 sh a2,236(sp) -80007794: 40a885b3 sub a1,a7,a0 -80007798: 00050693 mv a3,a0 -8000779c: 06b05e63 blez a1,80007818 <_ldtoa_r+0xe70> -800077a0: 02412683 lw a3,36(sp) -800077a4: 10810713 addi a4,sp,264 -800077a8: 12010793 addi a5,sp,288 -800077ac: 00270713 addi a4,a4,2 -800077b0: ffe75583 lhu a1,-2(a4) -800077b4: 00268693 addi a3,a3,2 -800077b8: feb69f23 sh a1,-2(a3) -800077bc: fef718e3 bne a4,a5,800077ac <_ldtoa_r+0xe04> -800077c0: 12011e23 sh zero,316(sp) -800077c4: 10810713 addi a4,sp,264 -800077c8: 0ec10693 addi a3,sp,236 -800077cc: 0080006f j 800077d4 <_ldtoa_r+0xe2c> -800077d0: 0006d603 lhu a2,0(a3) -800077d4: 00270713 addi a4,a4,2 -800077d8: fec71f23 sh a2,-2(a4) -800077dc: 00268693 addi a3,a3,2 -800077e0: fef718e3 bne a4,a5,800077d0 <_ldtoa_r+0xe28> -800077e4: 02412783 lw a5,36(sp) -800077e8: 12011023 sh zero,288(sp) -800077ec: 0ec10713 addi a4,sp,236 -800077f0: 13c10613 addi a2,sp,316 -800077f4: 00278793 addi a5,a5,2 -800077f8: ffe7d683 lhu a3,-2(a5) -800077fc: 00270713 addi a4,a4,2 -80007800: fed71f23 sh a3,-2(a4) -80007804: fec798e3 bne a5,a2,800077f4 <_ldtoa_r+0xe4c> -80007808: 10a15683 lhu a3,266(sp) -8000780c: 411505b3 sub a1,a0,a7 -80007810: 10011223 sh zero,260(sp) -80007814: 00068513 mv a0,a3 -80007818: 30058a63 beqz a1,80007b2c <_ldtoa_r+0x1184> -8000781c: 02d12623 sw a3,44(sp) -80007820: f6f00793 li a5,-145 -80007824: 06f5c863 blt a1,a5,80007894 <_ldtoa_r+0xeec> -80007828: 0ec10513 addi a0,sp,236 -8000782c: dbdfd0ef jal ra,800055e8 -80007830: 02c12683 lw a3,44(sp) -80007834: 00050593 mv a1,a0 -80007838: 12010793 addi a5,sp,288 -8000783c: 10410513 addi a0,sp,260 -80007840: 0ec15603 lhu a2,236(sp) -80007844: 10815703 lhu a4,264(sp) -80007848: 32e60e63 beq a2,a4,80007b84 <_ldtoa_r+0x11dc> -8000784c: 00000713 li a4,0 -80007850: 00070613 mv a2,a4 -80007854: 0007d703 lhu a4,0(a5) -80007858: 00055803 lhu a6,0(a0) -8000785c: ffe78793 addi a5,a5,-2 -80007860: 40c70733 sub a4,a4,a2 -80007864: 41070733 sub a4,a4,a6 -80007868: 00e79123 sh a4,2(a5) -8000786c: 01075713 srli a4,a4,0x10 -80007870: 00177613 andi a2,a4,1 -80007874: 10a10713 addi a4,sp,266 -80007878: ffe50513 addi a0,a0,-2 -8000787c: fce79ce3 bne a5,a4,80007854 <_ldtoa_r+0xeac> -80007880: 00100613 li a2,1 -80007884: 00098793 mv a5,s3 -80007888: 04000713 li a4,64 -8000788c: 10810513 addi a0,sp,264 -80007890: 880fe0ef jal ra,80005910 -80007894: 00090593 mv a1,s2 -80007898: 10810513 addi a0,sp,264 -8000789c: de8fe0ef jal ra,80005e84 -800078a0: d1dff06f j 800075bc <_ldtoa_r+0xc14> -800078a4: 00812783 lw a5,8(sp) -800078a8: fff78493 addi s1,a5,-1 -800078ac: be8ff06f j 80006c94 <_ldtoa_r+0x2ec> -800078b0: 00c12783 lw a5,12(sp) -800078b4: 12010223 sb zero,292(sp) -800078b8: 00090413 mv s0,s2 -800078bc: 0007a023 sw zero,0(a5) -800078c0: b69ff06f j 80007428 <_ldtoa_r+0xa80> -800078c4: 00090793 mv a5,s2 -800078c8: 0e410713 addi a4,sp,228 -800078cc: 00278793 addi a5,a5,2 -800078d0: fe079f23 sh zero,-2(a5) -800078d4: fee79ce3 bne a5,a4,800078cc <_ldtoa_r+0xf24> -800078d8: cd9ff06f j 800075b0 <_ldtoa_r+0xc08> -800078dc: 01012783 lw a5,16(sp) -800078e0: 12410913 addi s2,sp,292 -800078e4: 0e078c63 beqz a5,800079dc <_ldtoa_r+0x1034> -800078e8: 800155b7 lui a1,0x80015 -800078ec: a7058593 addi a1,a1,-1424 # 80014a70 <__BSS_END__+0xffffdcf8> -800078f0: 00090513 mv a0,s2 -800078f4: 000024b7 lui s1,0x2 -800078f8: 125010ef jal ra,8000921c -800078fc: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -80007900: 919ff06f j 80007218 <_ldtoa_r+0x870> -80007904: 03100793 li a5,49 -80007908: 12f102a3 sb a5,293(sp) -8000790c: 02e00793 li a5,46 -80007910: 12f10323 sb a5,294(sp) -80007914: 00148493 addi s1,s1,1 -80007918: 02900413 li s0,41 -8000791c: 03000793 li a5,48 -80007920: 12f103a3 sb a5,295(sp) -80007924: 12810793 addi a5,sp,296 -80007928: 00f12823 sw a5,16(sp) -8000792c: e68ff06f j 80006f94 <_ldtoa_r+0x5ec> -80007930: 03100793 li a5,49 -80007934: 12f102a3 sb a5,293(sp) -80007938: 02e00793 li a5,46 -8000793c: 12f10323 sb a5,294(sp) -80007940: 00148493 addi s1,s1,1 -80007944: 1e804063 bgtz s0,80007b24 <_ldtoa_r+0x117c> -80007948: 12710c93 addi s9,sp,295 -8000794c: 8a041ce3 bnez s0,80007204 <_ldtoa_r+0x85c> -80007950: 01912823 sw s9,16(sp) -80007954: e40ff06f j 80006f94 <_ldtoa_r+0x5ec> -80007958: 0e810c13 addi s8,sp,232 -8000795c: b78ff06f j 80006cd4 <_ldtoa_r+0x32c> -80007960: 03100793 li a5,49 -80007964: fef98f23 sb a5,-2(s3) -80007968: 00148493 addi s1,s1,1 -8000796c: 899ff06f j 80007204 <_ldtoa_r+0x85c> -80007970: 12410913 addi s2,sp,292 -80007974: 800155b7 lui a1,0x80015 -80007978: a8858593 addi a1,a1,-1400 # 80014a88 <__BSS_END__+0xffffdd10> -8000797c: 00090513 mv a0,s2 -80007980: 000024b7 lui s1,0x2 -80007984: 099010ef jal ra,8000921c -80007988: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -8000798c: 88dff06f j 80007218 <_ldtoa_r+0x870> -80007990: 09810593 addi a1,sp,152 -80007994: 07c10513 addi a0,sp,124 -80007998: cecfe0ef jal ra,80005e84 -8000799c: 814b0593 addi a1,s6,-2028 -800079a0: 09810513 addi a0,sp,152 -800079a4: b0dfd0ef jal ra,800054b0 -800079a8: fe051663 bnez a0,80007194 <_ldtoa_r+0x7ec> -800079ac: 84044ce3 bltz s0,80007204 <_ldtoa_r+0x85c> -800079b0: ffe9c783 lbu a5,-2(s3) -800079b4: fd278713 addi a4,a5,-46 -800079b8: 00173713 seqz a4,a4 -800079bc: fff74713 not a4,a4 -800079c0: 00ec8733 add a4,s9,a4 -800079c4: 00074703 lbu a4,0(a4) -800079c8: 00177713 andi a4,a4,1 -800079cc: 82070ce3 beqz a4,80007204 <_ldtoa_r+0x85c> -800079d0: ffe98713 addi a4,s3,-2 -800079d4: 07f7f793 andi a5,a5,127 -800079d8: fccff06f j 800071a4 <_ldtoa_r+0x7fc> -800079dc: 800155b7 lui a1,0x80015 -800079e0: a7c58593 addi a1,a1,-1412 # 80014a7c <__BSS_END__+0xffffdd04> -800079e4: 00090513 mv a0,s2 -800079e8: 000024b7 lui s1,0x2 -800079ec: 031010ef jal ra,8000921c -800079f0: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -800079f4: 825ff06f j 80007218 <_ldtoa_r+0x870> -800079f8: 00178793 addi a5,a5,1 -800079fc: fef70fa3 sb a5,-1(a4) -80007a00: 805ff06f j 80007204 <_ldtoa_r+0x85c> -80007a04: 0d010413 addi s0,sp,208 -80007a08: 00040593 mv a1,s0 -80007a0c: 07c10513 addi a0,sp,124 -80007a10: 00004ab7 lui s5,0x4 -80007a14: 995fd0ef jal ra,800053a8 -80007a18: 00000493 li s1,0 -80007a1c: 0e810c13 addi s8,sp,232 -80007a20: 0cc10913 addi s2,sp,204 -80007a24: 0d210993 addi s3,sp,210 -80007a28: ffea8a93 addi s5,s5,-2 # 3ffe <_start-0x7fffc002> -80007a2c: 0e815783 lhu a5,232(sp) -80007a30: 0077f793 andi a5,a5,7 -80007a34: 0c079a63 bnez a5,80007b08 <_ldtoa_r+0x1160> -80007a38: 0b410713 addi a4,sp,180 -80007a3c: 00040793 mv a5,s0 -80007a40: 00278793 addi a5,a5,2 -80007a44: ffe7d683 lhu a3,-2(a5) -80007a48: 00270713 addi a4,a4,2 -80007a4c: fed71f23 sh a3,-2(a4) -80007a50: ff8798e3 bne a5,s8,80007a40 <_ldtoa_r+0x1098> -80007a54: 0b410513 addi a0,sp,180 -80007a58: 0c011623 sh zero,204(sp) -80007a5c: f2cfd0ef jal ra,80005188 -80007a60: 0b410513 addi a0,sp,180 -80007a64: f24fd0ef jal ra,80005188 -80007a68: 00000613 li a2,0 -80007a6c: 00090693 mv a3,s2 -80007a70: 000c0713 mv a4,s8 -80007a74: 0006d583 lhu a1,0(a3) -80007a78: 00075783 lhu a5,0(a4) -80007a7c: ffe68693 addi a3,a3,-2 -80007a80: ffe70713 addi a4,a4,-2 -80007a84: 00b787b3 add a5,a5,a1 -80007a88: 00c787b3 add a5,a5,a2 -80007a8c: 00f69123 sh a5,2(a3) -80007a90: 0107d793 srli a5,a5,0x10 -80007a94: 0017f613 andi a2,a5,1 -80007a98: fd371ee3 bne a4,s3,80007a74 <_ldtoa_r+0x10cc> -80007a9c: 0b615783 lhu a5,182(sp) -80007aa0: 0b815703 lhu a4,184(sp) -80007aa4: 00378793 addi a5,a5,3 -80007aa8: 0af11b23 sh a5,182(sp) -80007aac: 02070063 beqz a4,80007acc <_ldtoa_r+0x1124> -80007ab0: 0b410513 addi a0,sp,180 -80007ab4: ed4fd0ef jal ra,80005188 -80007ab8: 0b615783 lhu a5,182(sp) -80007abc: 0b815703 lhu a4,184(sp) -80007ac0: 00178793 addi a5,a5,1 -80007ac4: 0af11b23 sh a5,182(sp) -80007ac8: fe0714e3 bnez a4,80007ab0 <_ldtoa_r+0x1108> -80007acc: 0cc15783 lhu a5,204(sp) -80007ad0: 02079c63 bnez a5,80007b08 <_ldtoa_r+0x1160> -80007ad4: 0b615783 lhu a5,182(sp) -80007ad8: 02fae863 bltu s5,a5,80007b08 <_ldtoa_r+0x1160> -80007adc: 00040713 mv a4,s0 -80007ae0: 0b410793 addi a5,sp,180 -80007ae4: 00278793 addi a5,a5,2 -80007ae8: ffe7d683 lhu a3,-2(a5) -80007aec: 00270713 addi a4,a4,2 -80007af0: fed71f23 sh a3,-2(a4) -80007af4: ff2798e3 bne a5,s2,80007ae4 <_ldtoa_r+0x113c> -80007af8: 0e011423 sh zero,232(sp) -80007afc: fff48493 addi s1,s1,-1 -80007b00: fd500793 li a5,-43 -80007b04: f2f494e3 bne s1,a5,80007a2c <_ldtoa_r+0x1084> -80007b08: 07c10593 addi a1,sp,124 -80007b0c: 00040513 mv a0,s0 -80007b10: b74fe0ef jal ra,80005e84 -80007b14: 16010993 addi s3,sp,352 -80007b18: 890ff06f j 80006ba8 <_ldtoa_r+0x200> -80007b1c: 00090793 mv a5,s2 -80007b20: f80ff06f j 800072a0 <_ldtoa_r+0x8f8> -80007b24: fff40413 addi s0,s0,-1 -80007b28: df5ff06f j 8000791c <_ldtoa_r+0xf74> -80007b2c: 10c10713 addi a4,sp,268 -80007b30: 0f010793 addi a5,sp,240 -80007b34: 00278793 addi a5,a5,2 -80007b38: 00270713 addi a4,a4,2 -80007b3c: ffe7d883 lhu a7,-2(a5) -80007b40: ffe75603 lhu a2,-2(a4) -80007b44: 02c89863 bne a7,a2,80007b74 <_ldtoa_r+0x11cc> -80007b48: 10610613 addi a2,sp,262 -80007b4c: fec794e3 bne a5,a2,80007b34 <_ldtoa_r+0x118c> -80007b50: 0ec15703 lhu a4,236(sp) -80007b54: 10815783 lhu a5,264(sp) -80007b58: 06f70263 beq a4,a5,80007bbc <_ldtoa_r+0x1214> -80007b5c: 00090793 mv a5,s2 -80007b60: 0e410713 addi a4,sp,228 -80007b64: 00278793 addi a5,a5,2 -80007b68: fe079f23 sh zero,-2(a5) -80007b6c: fee79ce3 bne a5,a4,80007b64 <_ldtoa_r+0x11bc> -80007b70: a4dff06f j 800075bc <_ldtoa_r+0xc14> -80007b74: 0d166663 bltu a2,a7,80007c40 <_ldtoa_r+0x1298> -80007b78: 12010793 addi a5,sp,288 -80007b7c: 10410513 addi a0,sp,260 -80007b80: cc1ff06f j 80007840 <_ldtoa_r+0xe98> -80007b84: 00000713 li a4,0 -80007b88: 0ee10313 addi t1,sp,238 -80007b8c: 0007d803 lhu a6,0(a5) -80007b90: 00055603 lhu a2,0(a0) -80007b94: ffe78793 addi a5,a5,-2 -80007b98: ffe50513 addi a0,a0,-2 -80007b9c: 01060633 add a2,a2,a6 -80007ba0: 00e60733 add a4,a2,a4 -80007ba4: 00e79123 sh a4,2(a5) -80007ba8: 01075713 srli a4,a4,0x10 -80007bac: 00177713 andi a4,a4,1 -80007bb0: fc651ee3 bne a0,t1,80007b8c <_ldtoa_r+0x11e4> -80007bb4: 00000613 li a2,0 -80007bb8: ccdff06f j 80007884 <_ldtoa_r+0xedc> -80007bbc: 00068713 mv a4,a3 -80007bc0: 06069263 bnez a3,80007c24 <_ldtoa_r+0x127c> -80007bc4: 10e11783 lh a5,270(sp) -80007bc8: 0407ce63 bltz a5,80007c24 <_ldtoa_r+0x127c> -80007bcc: 12010693 addi a3,sp,288 -80007bd0: 0200006f j 80007bf0 <_ldtoa_r+0x1248> -80007bd4: 00f69023 sh a5,0(a3) -80007bd8: 00171713 slli a4,a4,0x1 -80007bdc: 01071713 slli a4,a4,0x10 -80007be0: ffe68693 addi a3,a3,-2 -80007be4: 10a10793 addi a5,sp,266 -80007be8: 01075713 srli a4,a4,0x10 -80007bec: caf684e3 beq a3,a5,80007894 <_ldtoa_r+0xeec> -80007bf0: 0006d783 lhu a5,0(a3) -80007bf4: 01079613 slli a2,a5,0x10 -80007bf8: 41065613 srai a2,a2,0x10 -80007bfc: 00179793 slli a5,a5,0x1 -80007c00: 00065463 bgez a2,80007c08 <_ldtoa_r+0x1260> -80007c04: 00176713 ori a4,a4,1 -80007c08: 01079793 slli a5,a5,0x10 -80007c0c: 0107d793 srli a5,a5,0x10 -80007c10: 00277613 andi a2,a4,2 -80007c14: 0017e593 ori a1,a5,1 -80007c18: fa060ee3 beqz a2,80007bd4 <_ldtoa_r+0x122c> -80007c1c: 00b69023 sh a1,0(a3) -80007c20: fb9ff06f j 80007bd8 <_ldtoa_r+0x1230> -80007c24: 10c10613 addi a2,sp,268 -80007c28: 12010793 addi a5,sp,288 -80007c2c: 08071263 bnez a4,80007cb0 <_ldtoa_r+0x1308> -80007c30: 08c78263 beq a5,a2,80007cb4 <_ldtoa_r+0x130c> -80007c34: 00065703 lhu a4,0(a2) -80007c38: 00260613 addi a2,a2,2 -80007c3c: ff1ff06f j 80007c2c <_ldtoa_r+0x1284> -80007c40: 02412603 lw a2,36(sp) -80007c44: 10810713 addi a4,sp,264 -80007c48: 12010793 addi a5,sp,288 -80007c4c: 00270713 addi a4,a4,2 -80007c50: ffe75503 lhu a0,-2(a4) -80007c54: 00260613 addi a2,a2,2 -80007c58: fea61f23 sh a0,-2(a2) -80007c5c: fef718e3 bne a4,a5,80007c4c <_ldtoa_r+0x12a4> -80007c60: 12011e23 sh zero,316(sp) -80007c64: 10810613 addi a2,sp,264 -80007c68: 0ec10713 addi a4,sp,236 -80007c6c: 10410513 addi a0,sp,260 -80007c70: 00270713 addi a4,a4,2 -80007c74: ffe75803 lhu a6,-2(a4) -80007c78: 00260613 addi a2,a2,2 -80007c7c: ff061f23 sh a6,-2(a2) -80007c80: fea718e3 bne a4,a0,80007c70 <_ldtoa_r+0x12c8> -80007c84: 02412703 lw a4,36(sp) -80007c88: 12011023 sh zero,288(sp) -80007c8c: 0ec10893 addi a7,sp,236 -80007c90: 13c10613 addi a2,sp,316 -80007c94: 00270713 addi a4,a4,2 -80007c98: ffe75803 lhu a6,-2(a4) -80007c9c: 00288893 addi a7,a7,2 -80007ca0: ff089f23 sh a6,-2(a7) -80007ca4: fec718e3 bne a4,a2,80007c94 <_ldtoa_r+0x12ec> -80007ca8: 10011223 sh zero,260(sp) -80007cac: b95ff06f j 80007840 <_ldtoa_r+0xe98> -80007cb0: 00168513 addi a0,a3,1 -80007cb4: 10a11523 sh a0,266(sp) -80007cb8: bddff06f j 80007894 <_ldtoa_r+0xeec> - -80007cbc <_ldcheck>: -80007cbc: 00852703 lw a4,8(a0) -80007cc0: 00c52783 lw a5,12(a0) -80007cc4: 00052603 lw a2,0(a0) -80007cc8: 00452683 lw a3,4(a0) -80007ccc: fc010113 addi sp,sp,-64 -80007cd0: 00010513 mv a0,sp -80007cd4: 01410593 addi a1,sp,20 -80007cd8: 00e12423 sw a4,8(sp) -80007cdc: 00f12623 sw a5,12(sp) -80007ce0: 02112e23 sw ra,60(sp) -80007ce4: 00c12023 sw a2,0(sp) -80007ce8: 00d12223 sw a3,4(sp) -80007cec: b79fe0ef jal ra,80006864 -80007cf0: 02615783 lhu a5,38(sp) -80007cf4: 00000513 li a0,0 -80007cf8: fff7c793 not a5,a5 -80007cfc: 01179713 slli a4,a5,0x11 -80007d00: 00071a63 bnez a4,80007d14 <_ldcheck+0x58> -80007d04: 01410513 addi a0,sp,20 -80007d08: df0fd0ef jal ra,800052f8 -80007d0c: 00153513 seqz a0,a0 -80007d10: 00150513 addi a0,a0,1 -80007d14: 03c12083 lw ra,60(sp) -80007d18: 04010113 addi sp,sp,64 -80007d1c: 00008067 ret - -80007d20 <__localeconv_l>: -80007d20: 0f050513 addi a0,a0,240 -80007d24: 00008067 ret - -80007d28 <_localeconv_r>: -80007d28: 12018513 addi a0,gp,288 # 80016c88 <__global_locale+0xf0> -80007d2c: 00008067 ret - -80007d30 : -80007d30: 12018513 addi a0,gp,288 # 80016c88 <__global_locale+0xf0> -80007d34: 00008067 ret - -80007d38 <_setlocale_r>: -80007d38: ff010113 addi sp,sp,-16 -80007d3c: 00112623 sw ra,12(sp) -80007d40: 00812423 sw s0,8(sp) -80007d44: 00912223 sw s1,4(sp) -80007d48: 02060c63 beqz a2,80007d80 <_setlocale_r+0x48> -80007d4c: 800155b7 lui a1,0x80015 -80007d50: a9458593 addi a1,a1,-1388 # 80014a94 <__BSS_END__+0xffffdd1c> -80007d54: 00060513 mv a0,a2 -80007d58: 00060493 mv s1,a2 -80007d5c: 694010ef jal ra,800093f0 -80007d60: 80015437 lui s0,0x80015 -80007d64: 02051263 bnez a0,80007d88 <_setlocale_r+0x50> -80007d68: a9040513 addi a0,s0,-1392 # 80014a90 <__BSS_END__+0xffffdd18> -80007d6c: 00c12083 lw ra,12(sp) -80007d70: 00812403 lw s0,8(sp) -80007d74: 00412483 lw s1,4(sp) -80007d78: 01010113 addi sp,sp,16 -80007d7c: 00008067 ret -80007d80: 80015437 lui s0,0x80015 -80007d84: fe5ff06f j 80007d68 <_setlocale_r+0x30> -80007d88: a9040593 addi a1,s0,-1392 # 80014a90 <__BSS_END__+0xffffdd18> -80007d8c: 00048513 mv a0,s1 -80007d90: 660010ef jal ra,800093f0 -80007d94: fc050ae3 beqz a0,80007d68 <_setlocale_r+0x30> -80007d98: 800155b7 lui a1,0x80015 -80007d9c: 80458593 addi a1,a1,-2044 # 80014804 <__BSS_END__+0xffffda8c> -80007da0: 00048513 mv a0,s1 -80007da4: 64c010ef jal ra,800093f0 -80007da8: fc0500e3 beqz a0,80007d68 <_setlocale_r+0x30> -80007dac: 00000513 li a0,0 -80007db0: fbdff06f j 80007d6c <_setlocale_r+0x34> - -80007db4 <__locale_mb_cur_max>: -80007db4: 1581c503 lbu a0,344(gp) # 80016cc0 <__global_locale+0x128> -80007db8: 00008067 ret - -80007dbc : -80007dbc: 00058613 mv a2,a1 -80007dc0: 00050593 mv a1,a0 -80007dc4: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -80007dc8: f71ff06f j 80007d38 <_setlocale_r> - -80007dcc <__swhatbuf_r>: -80007dcc: f9010113 addi sp,sp,-112 -80007dd0: 06812423 sw s0,104(sp) -80007dd4: 00058413 mv s0,a1 -80007dd8: 00e59583 lh a1,14(a1) -80007ddc: 06912223 sw s1,100(sp) -80007de0: 07212023 sw s2,96(sp) -80007de4: 06112623 sw ra,108(sp) -80007de8: 00060493 mv s1,a2 -80007dec: 00068913 mv s2,a3 -80007df0: 0405ca63 bltz a1,80007e44 <__swhatbuf_r+0x78> -80007df4: 00810613 addi a2,sp,8 -80007df8: 5b5050ef jal ra,8000dbac <_fstat_r> -80007dfc: 04054463 bltz a0,80007e44 <__swhatbuf_r+0x78> -80007e00: 00c12703 lw a4,12(sp) -80007e04: 0000f7b7 lui a5,0xf -80007e08: 06c12083 lw ra,108(sp) -80007e0c: 00e7f7b3 and a5,a5,a4 -80007e10: ffffe737 lui a4,0xffffe -80007e14: 00e787b3 add a5,a5,a4 -80007e18: 0017b793 seqz a5,a5 -80007e1c: 06812403 lw s0,104(sp) -80007e20: 00f92023 sw a5,0(s2) # fffff000 <__BSS_END__+0x7ffe8288> -80007e24: 40000793 li a5,1024 -80007e28: 00f4a023 sw a5,0(s1) -80007e2c: 00001537 lui a0,0x1 -80007e30: 06412483 lw s1,100(sp) -80007e34: 06012903 lw s2,96(sp) -80007e38: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800> -80007e3c: 07010113 addi sp,sp,112 -80007e40: 00008067 ret -80007e44: 00c45783 lhu a5,12(s0) -80007e48: 00092023 sw zero,0(s2) -80007e4c: 0807f793 andi a5,a5,128 -80007e50: 02078463 beqz a5,80007e78 <__swhatbuf_r+0xac> -80007e54: 06c12083 lw ra,108(sp) -80007e58: 06812403 lw s0,104(sp) -80007e5c: 04000793 li a5,64 -80007e60: 00f4a023 sw a5,0(s1) -80007e64: 06012903 lw s2,96(sp) -80007e68: 06412483 lw s1,100(sp) -80007e6c: 00000513 li a0,0 -80007e70: 07010113 addi sp,sp,112 -80007e74: 00008067 ret -80007e78: 06c12083 lw ra,108(sp) -80007e7c: 06812403 lw s0,104(sp) -80007e80: 40000793 li a5,1024 -80007e84: 00f4a023 sw a5,0(s1) -80007e88: 06012903 lw s2,96(sp) -80007e8c: 06412483 lw s1,100(sp) -80007e90: 00000513 li a0,0 -80007e94: 07010113 addi sp,sp,112 -80007e98: 00008067 ret - -80007e9c <__smakebuf_r>: -80007e9c: 00c5d703 lhu a4,12(a1) -80007ea0: fe010113 addi sp,sp,-32 -80007ea4: 00812c23 sw s0,24(sp) -80007ea8: 00112e23 sw ra,28(sp) -80007eac: 00912a23 sw s1,20(sp) -80007eb0: 01212823 sw s2,16(sp) -80007eb4: 00277713 andi a4,a4,2 -80007eb8: 00058413 mv s0,a1 -80007ebc: 02070863 beqz a4,80007eec <__smakebuf_r+0x50> -80007ec0: 04358713 addi a4,a1,67 -80007ec4: 00e5a023 sw a4,0(a1) -80007ec8: 00e5a823 sw a4,16(a1) -80007ecc: 00100713 li a4,1 -80007ed0: 00e5aa23 sw a4,20(a1) -80007ed4: 01c12083 lw ra,28(sp) -80007ed8: 01812403 lw s0,24(sp) -80007edc: 01412483 lw s1,20(sp) -80007ee0: 01012903 lw s2,16(sp) -80007ee4: 02010113 addi sp,sp,32 -80007ee8: 00008067 ret -80007eec: 00c10693 addi a3,sp,12 -80007ef0: 00810613 addi a2,sp,8 -80007ef4: 00050493 mv s1,a0 -80007ef8: ed5ff0ef jal ra,80007dcc <__swhatbuf_r> -80007efc: 00812583 lw a1,8(sp) -80007f00: 00050913 mv s2,a0 -80007f04: 00048513 mv a0,s1 -80007f08: df9f80ef jal ra,80000d00 <_malloc_r> -80007f0c: 00c41783 lh a5,12(s0) -80007f10: 04050863 beqz a0,80007f60 <__smakebuf_r+0xc4> -80007f14: 80005737 lui a4,0x80005 -80007f18: 8b470713 addi a4,a4,-1868 # 800048b4 <__BSS_END__+0xfffedb3c> -80007f1c: 02e4ae23 sw a4,60(s1) -80007f20: 00812703 lw a4,8(sp) -80007f24: 00c12683 lw a3,12(sp) -80007f28: 0807e793 ori a5,a5,128 -80007f2c: 00f41623 sh a5,12(s0) -80007f30: 00a42023 sw a0,0(s0) -80007f34: 00a42823 sw a0,16(s0) -80007f38: 00e42a23 sw a4,20(s0) -80007f3c: 04069863 bnez a3,80007f8c <__smakebuf_r+0xf0> -80007f40: 0127e7b3 or a5,a5,s2 -80007f44: 00f41623 sh a5,12(s0) -80007f48: 01c12083 lw ra,28(sp) -80007f4c: 01812403 lw s0,24(sp) -80007f50: 01412483 lw s1,20(sp) -80007f54: 01012903 lw s2,16(sp) -80007f58: 02010113 addi sp,sp,32 -80007f5c: 00008067 ret -80007f60: 2007f713 andi a4,a5,512 -80007f64: f60718e3 bnez a4,80007ed4 <__smakebuf_r+0x38> -80007f68: ffc7f793 andi a5,a5,-4 -80007f6c: 0027e793 ori a5,a5,2 -80007f70: 04340713 addi a4,s0,67 -80007f74: 00f41623 sh a5,12(s0) -80007f78: 00100793 li a5,1 -80007f7c: 00e42023 sw a4,0(s0) -80007f80: 00e42823 sw a4,16(s0) -80007f84: 00f42a23 sw a5,20(s0) -80007f88: f4dff06f j 80007ed4 <__smakebuf_r+0x38> -80007f8c: 00e41583 lh a1,14(s0) -80007f90: 00048513 mv a0,s1 -80007f94: 12c060ef jal ra,8000e0c0 <_isatty_r> -80007f98: 00051663 bnez a0,80007fa4 <__smakebuf_r+0x108> -80007f9c: 00c41783 lh a5,12(s0) -80007fa0: fa1ff06f j 80007f40 <__smakebuf_r+0xa4> -80007fa4: 00c45783 lhu a5,12(s0) -80007fa8: ffc7f793 andi a5,a5,-4 -80007fac: 0017e793 ori a5,a5,1 -80007fb0: 01079793 slli a5,a5,0x10 -80007fb4: 4107d793 srai a5,a5,0x10 -80007fb8: f89ff06f j 80007f40 <__smakebuf_r+0xa4> - -80007fbc <_mbtowc_r>: -80007fbc: 1141a303 lw t1,276(gp) # 80016c7c <__global_locale+0xe4> -80007fc0: 00030067 jr t1 - -80007fc4 <__ascii_mbtowc>: -80007fc4: 02058063 beqz a1,80007fe4 <__ascii_mbtowc+0x20> -80007fc8: 04060263 beqz a2,8000800c <__ascii_mbtowc+0x48> -80007fcc: 04068863 beqz a3,8000801c <__ascii_mbtowc+0x58> -80007fd0: 00064783 lbu a5,0(a2) -80007fd4: 00f5a023 sw a5,0(a1) -80007fd8: 00064503 lbu a0,0(a2) -80007fdc: 00a03533 snez a0,a0 -80007fe0: 00008067 ret -80007fe4: ff010113 addi sp,sp,-16 -80007fe8: 00c10593 addi a1,sp,12 -80007fec: 02060463 beqz a2,80008014 <__ascii_mbtowc+0x50> -80007ff0: 02068a63 beqz a3,80008024 <__ascii_mbtowc+0x60> -80007ff4: 00064783 lbu a5,0(a2) -80007ff8: 00f5a023 sw a5,0(a1) -80007ffc: 00064503 lbu a0,0(a2) -80008000: 00a03533 snez a0,a0 -80008004: 01010113 addi sp,sp,16 -80008008: 00008067 ret -8000800c: 00000513 li a0,0 -80008010: 00008067 ret -80008014: 00000513 li a0,0 -80008018: fedff06f j 80008004 <__ascii_mbtowc+0x40> -8000801c: ffe00513 li a0,-2 -80008020: 00008067 ret -80008024: ffe00513 li a0,-2 -80008028: fddff06f j 80008004 <__ascii_mbtowc+0x40> - -8000802c : -8000802c: 00357793 andi a5,a0,3 -80008030: 0ff5f813 andi a6,a1,255 -80008034: 0c078663 beqz a5,80008100 -80008038: fff60793 addi a5,a2,-1 -8000803c: 04060e63 beqz a2,80008098 -80008040: 00054703 lbu a4,0(a0) -80008044: 05070c63 beq a4,a6,8000809c -80008048: fff00693 li a3,-1 -8000804c: 0140006f j 80008060 -80008050: fff78793 addi a5,a5,-1 # efff <_start-0x7fff1001> -80008054: 04d78263 beq a5,a3,80008098 -80008058: 00054703 lbu a4,0(a0) -8000805c: 05070063 beq a4,a6,8000809c -80008060: 00150513 addi a0,a0,1 -80008064: 00357713 andi a4,a0,3 -80008068: fe0714e3 bnez a4,80008050 -8000806c: 00300713 li a4,3 -80008070: 02f76863 bltu a4,a5,800080a0 -80008074: 02078263 beqz a5,80008098 -80008078: 00054703 lbu a4,0(a0) -8000807c: 03070063 beq a4,a6,8000809c -80008080: 00f507b3 add a5,a0,a5 -80008084: 00c0006f j 80008090 -80008088: 00054703 lbu a4,0(a0) -8000808c: 01070863 beq a4,a6,8000809c -80008090: 00150513 addi a0,a0,1 -80008094: fea79ae3 bne a5,a0,80008088 -80008098: 00000513 li a0,0 -8000809c: 00008067 ret -800080a0: 00010737 lui a4,0x10 -800080a4: 00859893 slli a7,a1,0x8 -800080a8: fff70713 addi a4,a4,-1 # ffff <_start-0x7fff0001> -800080ac: 00e8f8b3 and a7,a7,a4 -800080b0: 0ff5f593 andi a1,a1,255 -800080b4: 00b8e5b3 or a1,a7,a1 -800080b8: 01059893 slli a7,a1,0x10 -800080bc: 00b8e8b3 or a7,a7,a1 -800080c0: 80808637 lui a2,0x80808 -800080c4: feff05b7 lui a1,0xfeff0 -800080c8: eff58593 addi a1,a1,-257 # fefefeff <__BSS_END__+0x7efd9187> -800080cc: 08060613 addi a2,a2,128 # 80808080 <__BSS_END__+0x7f1308> -800080d0: 00300313 li t1,3 -800080d4: 00052703 lw a4,0(a0) -800080d8: 00e8c733 xor a4,a7,a4 -800080dc: 00b706b3 add a3,a4,a1 -800080e0: fff74713 not a4,a4 -800080e4: 00e6f733 and a4,a3,a4 -800080e8: 00c77733 and a4,a4,a2 -800080ec: f80716e3 bnez a4,80008078 -800080f0: ffc78793 addi a5,a5,-4 -800080f4: 00450513 addi a0,a0,4 -800080f8: fcf36ee3 bltu t1,a5,800080d4 -800080fc: f79ff06f j 80008074 -80008100: 00060793 mv a5,a2 -80008104: f69ff06f j 8000806c - -80008108 <_Balloc>: -80008108: 04c52783 lw a5,76(a0) -8000810c: ff010113 addi sp,sp,-16 -80008110: 00812423 sw s0,8(sp) -80008114: 00912223 sw s1,4(sp) -80008118: 00112623 sw ra,12(sp) -8000811c: 01212023 sw s2,0(sp) -80008120: 00050413 mv s0,a0 -80008124: 00058493 mv s1,a1 -80008128: 02078e63 beqz a5,80008164 <_Balloc+0x5c> -8000812c: 00249713 slli a4,s1,0x2 -80008130: 00e787b3 add a5,a5,a4 -80008134: 0007a503 lw a0,0(a5) -80008138: 04050663 beqz a0,80008184 <_Balloc+0x7c> -8000813c: 00052703 lw a4,0(a0) -80008140: 00e7a023 sw a4,0(a5) -80008144: 00052823 sw zero,16(a0) -80008148: 00052623 sw zero,12(a0) -8000814c: 00c12083 lw ra,12(sp) -80008150: 00812403 lw s0,8(sp) -80008154: 00412483 lw s1,4(sp) -80008158: 00012903 lw s2,0(sp) -8000815c: 01010113 addi sp,sp,16 -80008160: 00008067 ret -80008164: 02100613 li a2,33 -80008168: 00400593 li a1,4 -8000816c: 640050ef jal ra,8000d7ac <_calloc_r> -80008170: 04a42623 sw a0,76(s0) -80008174: 00050793 mv a5,a0 -80008178: fa051ae3 bnez a0,8000812c <_Balloc+0x24> -8000817c: 00000513 li a0,0 -80008180: fcdff06f j 8000814c <_Balloc+0x44> -80008184: 00100913 li s2,1 -80008188: 00991933 sll s2,s2,s1 -8000818c: 00590613 addi a2,s2,5 -80008190: 00261613 slli a2,a2,0x2 -80008194: 00100593 li a1,1 -80008198: 00040513 mv a0,s0 -8000819c: 610050ef jal ra,8000d7ac <_calloc_r> -800081a0: fc050ee3 beqz a0,8000817c <_Balloc+0x74> -800081a4: 00952223 sw s1,4(a0) -800081a8: 01252423 sw s2,8(a0) -800081ac: f99ff06f j 80008144 <_Balloc+0x3c> - -800081b0 <_Bfree>: -800081b0: 02058063 beqz a1,800081d0 <_Bfree+0x20> -800081b4: 0045a703 lw a4,4(a1) -800081b8: 04c52783 lw a5,76(a0) -800081bc: 00271713 slli a4,a4,0x2 -800081c0: 00e787b3 add a5,a5,a4 -800081c4: 0007a703 lw a4,0(a5) -800081c8: 00e5a023 sw a4,0(a1) -800081cc: 00b7a023 sw a1,0(a5) -800081d0: 00008067 ret - -800081d4 <__multadd>: -800081d4: fd010113 addi sp,sp,-48 -800081d8: 00010837 lui a6,0x10 -800081dc: 02812423 sw s0,40(sp) -800081e0: 02912223 sw s1,36(sp) -800081e4: 03212023 sw s2,32(sp) -800081e8: 00058493 mv s1,a1 -800081ec: 0105a403 lw s0,16(a1) -800081f0: 00050913 mv s2,a0 -800081f4: 02112623 sw ra,44(sp) -800081f8: 01312e23 sw s3,28(sp) -800081fc: 01458593 addi a1,a1,20 -80008200: 00000513 li a0,0 -80008204: fff80813 addi a6,a6,-1 # ffff <_start-0x7fff0001> -80008208: 0005a783 lw a5,0(a1) -8000820c: 00458593 addi a1,a1,4 -80008210: 00150513 addi a0,a0,1 -80008214: 0107f733 and a4,a5,a6 -80008218: 02c70733 mul a4,a4,a2 -8000821c: 0107d793 srli a5,a5,0x10 -80008220: 02c787b3 mul a5,a5,a2 -80008224: 00d706b3 add a3,a4,a3 -80008228: 0106d893 srli a7,a3,0x10 -8000822c: 0106f733 and a4,a3,a6 -80008230: 011786b3 add a3,a5,a7 -80008234: 01069793 slli a5,a3,0x10 -80008238: 00e78733 add a4,a5,a4 -8000823c: fee5ae23 sw a4,-4(a1) -80008240: 0106d693 srli a3,a3,0x10 -80008244: fc8542e3 blt a0,s0,80008208 <__multadd+0x34> -80008248: 02068263 beqz a3,8000826c <__multadd+0x98> -8000824c: 0084a783 lw a5,8(s1) -80008250: 02f45e63 bge s0,a5,8000828c <__multadd+0xb8> -80008254: 00440793 addi a5,s0,4 -80008258: 00279793 slli a5,a5,0x2 -8000825c: 00f487b3 add a5,s1,a5 -80008260: 00d7a223 sw a3,4(a5) -80008264: 00140413 addi s0,s0,1 -80008268: 0084a823 sw s0,16(s1) -8000826c: 02c12083 lw ra,44(sp) -80008270: 02812403 lw s0,40(sp) -80008274: 00048513 mv a0,s1 -80008278: 02012903 lw s2,32(sp) -8000827c: 02412483 lw s1,36(sp) -80008280: 01c12983 lw s3,28(sp) -80008284: 03010113 addi sp,sp,48 -80008288: 00008067 ret -8000828c: 0044a583 lw a1,4(s1) -80008290: 00090513 mv a0,s2 -80008294: 00d12623 sw a3,12(sp) -80008298: 00158593 addi a1,a1,1 -8000829c: e6dff0ef jal ra,80008108 <_Balloc> -800082a0: 0104a603 lw a2,16(s1) -800082a4: 00050993 mv s3,a0 -800082a8: 00c48593 addi a1,s1,12 -800082ac: 00260613 addi a2,a2,2 -800082b0: 00c50513 addi a0,a0,12 -800082b4: 00261613 slli a2,a2,0x2 -800082b8: 6cd050ef jal ra,8000e184 -800082bc: 0044a703 lw a4,4(s1) -800082c0: 04c92783 lw a5,76(s2) -800082c4: 00c12683 lw a3,12(sp) -800082c8: 00271713 slli a4,a4,0x2 -800082cc: 00e787b3 add a5,a5,a4 -800082d0: 0007a703 lw a4,0(a5) -800082d4: 00e4a023 sw a4,0(s1) -800082d8: 0097a023 sw s1,0(a5) -800082dc: 00440793 addi a5,s0,4 -800082e0: 00098493 mv s1,s3 -800082e4: 00279793 slli a5,a5,0x2 -800082e8: 00f487b3 add a5,s1,a5 -800082ec: 00d7a223 sw a3,4(a5) -800082f0: 00140413 addi s0,s0,1 -800082f4: 0084a823 sw s0,16(s1) -800082f8: f75ff06f j 8000826c <__multadd+0x98> - -800082fc <__s2b>: -800082fc: fe010113 addi sp,sp,-32 -80008300: 00812c23 sw s0,24(sp) -80008304: 00912a23 sw s1,20(sp) -80008308: 01212823 sw s2,16(sp) -8000830c: 01312623 sw s3,12(sp) -80008310: 01412423 sw s4,8(sp) -80008314: 00068913 mv s2,a3 -80008318: 00900793 li a5,9 -8000831c: 00868693 addi a3,a3,8 -80008320: 00112e23 sw ra,28(sp) -80008324: 01512223 sw s5,4(sp) -80008328: 00050993 mv s3,a0 -8000832c: 00058413 mv s0,a1 -80008330: 00060a13 mv s4,a2 -80008334: 00070493 mv s1,a4 -80008338: 02f6c6b3 div a3,a3,a5 -8000833c: 0d27d263 bge a5,s2,80008400 <__s2b+0x104> -80008340: 00100793 li a5,1 -80008344: 00000593 li a1,0 -80008348: 00179793 slli a5,a5,0x1 -8000834c: 00158593 addi a1,a1,1 -80008350: fed7cce3 blt a5,a3,80008348 <__s2b+0x4c> -80008354: 00098513 mv a0,s3 -80008358: db1ff0ef jal ra,80008108 <_Balloc> -8000835c: 00100793 li a5,1 -80008360: 00f52823 sw a5,16(a0) -80008364: 00952a23 sw s1,20(a0) -80008368: 00900793 li a5,9 -8000836c: 0947d463 bge a5,s4,800083f4 <__s2b+0xf8> -80008370: 00940a93 addi s5,s0,9 -80008374: 000a8493 mv s1,s5 -80008378: 01440433 add s0,s0,s4 -8000837c: 00148493 addi s1,s1,1 -80008380: fff4c683 lbu a3,-1(s1) -80008384: 00050593 mv a1,a0 -80008388: 00a00613 li a2,10 -8000838c: fd068693 addi a3,a3,-48 -80008390: 00098513 mv a0,s3 -80008394: e41ff0ef jal ra,800081d4 <__multadd> -80008398: fe9412e3 bne s0,s1,8000837c <__s2b+0x80> -8000839c: ff8a0413 addi s0,s4,-8 -800083a0: 008a8433 add s0,s5,s0 -800083a4: 032a5663 bge s4,s2,800083d0 <__s2b+0xd4> -800083a8: 414904b3 sub s1,s2,s4 -800083ac: 009404b3 add s1,s0,s1 -800083b0: 00140413 addi s0,s0,1 -800083b4: fff44683 lbu a3,-1(s0) -800083b8: 00050593 mv a1,a0 -800083bc: 00a00613 li a2,10 -800083c0: fd068693 addi a3,a3,-48 -800083c4: 00098513 mv a0,s3 -800083c8: e0dff0ef jal ra,800081d4 <__multadd> -800083cc: fe8492e3 bne s1,s0,800083b0 <__s2b+0xb4> -800083d0: 01c12083 lw ra,28(sp) -800083d4: 01812403 lw s0,24(sp) -800083d8: 01412483 lw s1,20(sp) -800083dc: 01012903 lw s2,16(sp) -800083e0: 00c12983 lw s3,12(sp) -800083e4: 00812a03 lw s4,8(sp) -800083e8: 00412a83 lw s5,4(sp) -800083ec: 02010113 addi sp,sp,32 -800083f0: 00008067 ret -800083f4: 00a40413 addi s0,s0,10 -800083f8: 00900a13 li s4,9 -800083fc: fa9ff06f j 800083a4 <__s2b+0xa8> -80008400: 00000593 li a1,0 -80008404: f51ff06f j 80008354 <__s2b+0x58> - -80008408 <__hi0bits>: -80008408: ffff0737 lui a4,0xffff0 -8000840c: 00e57733 and a4,a0,a4 -80008410: 00050793 mv a5,a0 -80008414: 00000513 li a0,0 -80008418: 00071663 bnez a4,80008424 <__hi0bits+0x1c> -8000841c: 01079793 slli a5,a5,0x10 -80008420: 01000513 li a0,16 -80008424: ff000737 lui a4,0xff000 -80008428: 00e7f733 and a4,a5,a4 -8000842c: 00071663 bnez a4,80008438 <__hi0bits+0x30> -80008430: 00850513 addi a0,a0,8 -80008434: 00879793 slli a5,a5,0x8 -80008438: f0000737 lui a4,0xf0000 -8000843c: 00e7f733 and a4,a5,a4 -80008440: 00071663 bnez a4,8000844c <__hi0bits+0x44> -80008444: 00450513 addi a0,a0,4 -80008448: 00479793 slli a5,a5,0x4 -8000844c: c0000737 lui a4,0xc0000 -80008450: 00e7f733 and a4,a5,a4 -80008454: 00071663 bnez a4,80008460 <__hi0bits+0x58> -80008458: 00250513 addi a0,a0,2 -8000845c: 00279793 slli a5,a5,0x2 -80008460: 0007c863 bltz a5,80008470 <__hi0bits+0x68> -80008464: 00179713 slli a4,a5,0x1 -80008468: 00150513 addi a0,a0,1 -8000846c: 00075463 bgez a4,80008474 <__hi0bits+0x6c> -80008470: 00008067 ret -80008474: 02000513 li a0,32 -80008478: 00008067 ret - -8000847c <__lo0bits>: -8000847c: 00052783 lw a5,0(a0) -80008480: 0077f713 andi a4,a5,7 -80008484: 02070663 beqz a4,800084b0 <__lo0bits+0x34> -80008488: 0017f693 andi a3,a5,1 -8000848c: 00000713 li a4,0 -80008490: 00069c63 bnez a3,800084a8 <__lo0bits+0x2c> -80008494: 0027f713 andi a4,a5,2 -80008498: 08070463 beqz a4,80008520 <__lo0bits+0xa4> -8000849c: 0017d793 srli a5,a5,0x1 -800084a0: 00f52023 sw a5,0(a0) -800084a4: 00100713 li a4,1 -800084a8: 00070513 mv a0,a4 -800084ac: 00008067 ret -800084b0: 01079693 slli a3,a5,0x10 -800084b4: 0106d693 srli a3,a3,0x10 -800084b8: 00000713 li a4,0 -800084bc: 00069663 bnez a3,800084c8 <__lo0bits+0x4c> -800084c0: 0107d793 srli a5,a5,0x10 -800084c4: 01000713 li a4,16 -800084c8: 0ff7f693 andi a3,a5,255 -800084cc: 00069663 bnez a3,800084d8 <__lo0bits+0x5c> -800084d0: 00870713 addi a4,a4,8 # c0000008 <__BSS_END__+0x3ffe9290> -800084d4: 0087d793 srli a5,a5,0x8 -800084d8: 00f7f693 andi a3,a5,15 -800084dc: 00069663 bnez a3,800084e8 <__lo0bits+0x6c> -800084e0: 00470713 addi a4,a4,4 -800084e4: 0047d793 srli a5,a5,0x4 -800084e8: 0037f693 andi a3,a5,3 -800084ec: 00069663 bnez a3,800084f8 <__lo0bits+0x7c> -800084f0: 00270713 addi a4,a4,2 -800084f4: 0027d793 srli a5,a5,0x2 -800084f8: 0017f693 andi a3,a5,1 -800084fc: 00069863 bnez a3,8000850c <__lo0bits+0x90> -80008500: 0017d793 srli a5,a5,0x1 -80008504: 00170713 addi a4,a4,1 -80008508: 00078863 beqz a5,80008518 <__lo0bits+0x9c> -8000850c: 00f52023 sw a5,0(a0) -80008510: 00070513 mv a0,a4 -80008514: 00008067 ret -80008518: 02000713 li a4,32 -8000851c: f8dff06f j 800084a8 <__lo0bits+0x2c> -80008520: 0027d793 srli a5,a5,0x2 -80008524: 00200713 li a4,2 -80008528: 00f52023 sw a5,0(a0) -8000852c: 00070513 mv a0,a4 -80008530: 00008067 ret - -80008534 <__i2b>: -80008534: ff010113 addi sp,sp,-16 -80008538: 00812423 sw s0,8(sp) -8000853c: 00058413 mv s0,a1 -80008540: 00100593 li a1,1 -80008544: 00112623 sw ra,12(sp) -80008548: bc1ff0ef jal ra,80008108 <_Balloc> -8000854c: 00852a23 sw s0,20(a0) -80008550: 00c12083 lw ra,12(sp) -80008554: 00812403 lw s0,8(sp) -80008558: 00100713 li a4,1 -8000855c: 00e52823 sw a4,16(a0) -80008560: 01010113 addi sp,sp,16 -80008564: 00008067 ret - -80008568 <__multiply>: -80008568: fe010113 addi sp,sp,-32 -8000856c: 01312623 sw s3,12(sp) -80008570: 01412423 sw s4,8(sp) -80008574: 0105a983 lw s3,16(a1) -80008578: 01062a03 lw s4,16(a2) -8000857c: 00912a23 sw s1,20(sp) -80008580: 01212823 sw s2,16(sp) -80008584: 00112e23 sw ra,28(sp) -80008588: 00812c23 sw s0,24(sp) -8000858c: 00058493 mv s1,a1 -80008590: 00060913 mv s2,a2 -80008594: 0149cc63 blt s3,s4,800085ac <__multiply+0x44> -80008598: 000a0713 mv a4,s4 -8000859c: 00058913 mv s2,a1 -800085a0: 00098a13 mv s4,s3 -800085a4: 00060493 mv s1,a2 -800085a8: 00070993 mv s3,a4 -800085ac: 00892783 lw a5,8(s2) -800085b0: 00492583 lw a1,4(s2) -800085b4: 013a0433 add s0,s4,s3 -800085b8: 0087a7b3 slt a5,a5,s0 -800085bc: 00f585b3 add a1,a1,a5 -800085c0: b49ff0ef jal ra,80008108 <_Balloc> -800085c4: 01450e13 addi t3,a0,20 -800085c8: 00241313 slli t1,s0,0x2 -800085cc: 006e0333 add t1,t3,t1 -800085d0: 000e0793 mv a5,t3 -800085d4: 006e7863 bgeu t3,t1,800085e4 <__multiply+0x7c> -800085d8: 0007a023 sw zero,0(a5) -800085dc: 00478793 addi a5,a5,4 -800085e0: fe67ece3 bltu a5,t1,800085d8 <__multiply+0x70> -800085e4: 01448593 addi a1,s1,20 -800085e8: 00299e93 slli t4,s3,0x2 -800085ec: 01490613 addi a2,s2,20 -800085f0: 002a1893 slli a7,s4,0x2 -800085f4: 00010837 lui a6,0x10 -800085f8: 01d58eb3 add t4,a1,t4 -800085fc: 011608b3 add a7,a2,a7 -80008600: fff80813 addi a6,a6,-1 # ffff <_start-0x7fff0001> -80008604: 01d5ee63 bltu a1,t4,80008620 <__multiply+0xb8> -80008608: 10c0006f j 80008714 <__multiply+0x1ac> -8000860c: 010fdf93 srli t6,t6,0x10 -80008610: 080f9663 bnez t6,8000869c <__multiply+0x134> -80008614: 00458593 addi a1,a1,4 -80008618: 004e0e13 addi t3,t3,4 -8000861c: 0fd5fc63 bgeu a1,t4,80008714 <__multiply+0x1ac> -80008620: 0005af83 lw t6,0(a1) -80008624: 010ff3b3 and t2,t6,a6 -80008628: fe0382e3 beqz t2,8000860c <__multiply+0xa4> -8000862c: 000e0f93 mv t6,t3 -80008630: 00060293 mv t0,a2 -80008634: 00000493 li s1,0 -80008638: 0002a703 lw a4,0(t0) # 80001570 -8000863c: 000faf03 lw t5,0(t6) -80008640: 004f8f93 addi t6,t6,4 -80008644: 010776b3 and a3,a4,a6 -80008648: 027686b3 mul a3,a3,t2 -8000864c: 01075793 srli a5,a4,0x10 -80008650: 010f7733 and a4,t5,a6 -80008654: 010f5f13 srli t5,t5,0x10 -80008658: 00428293 addi t0,t0,4 -8000865c: 027787b3 mul a5,a5,t2 -80008660: 00e686b3 add a3,a3,a4 -80008664: 009686b3 add a3,a3,s1 -80008668: 0106d713 srli a4,a3,0x10 -8000866c: 0106f6b3 and a3,a3,a6 -80008670: 01e787b3 add a5,a5,t5 -80008674: 00e787b3 add a5,a5,a4 -80008678: 01079713 slli a4,a5,0x10 -8000867c: 00d766b3 or a3,a4,a3 -80008680: fedfae23 sw a3,-4(t6) -80008684: 0107d493 srli s1,a5,0x10 -80008688: fb12e8e3 bltu t0,a7,80008638 <__multiply+0xd0> -8000868c: 009fa023 sw s1,0(t6) -80008690: 0005af83 lw t6,0(a1) -80008694: 010fdf93 srli t6,t6,0x10 -80008698: f60f8ee3 beqz t6,80008614 <__multiply+0xac> -8000869c: 000e2703 lw a4,0(t3) -800086a0: 000e0f13 mv t5,t3 -800086a4: 00060693 mv a3,a2 -800086a8: 00070393 mv t2,a4 -800086ac: 00000293 li t0,0 -800086b0: 0006a783 lw a5,0(a3) -800086b4: 0103d913 srli s2,t2,0x10 -800086b8: 01077733 and a4,a4,a6 -800086bc: 0107f7b3 and a5,a5,a6 -800086c0: 03f787b3 mul a5,a5,t6 -800086c4: 004f0f13 addi t5,t5,4 -800086c8: 00468693 addi a3,a3,4 -800086cc: 000f2383 lw t2,0(t5) -800086d0: 0103f4b3 and s1,t2,a6 -800086d4: 012787b3 add a5,a5,s2 -800086d8: 005787b3 add a5,a5,t0 -800086dc: 01079293 slli t0,a5,0x10 -800086e0: 00e2e733 or a4,t0,a4 -800086e4: feef2e23 sw a4,-4(t5) -800086e8: ffe6d703 lhu a4,-2(a3) -800086ec: 0107d793 srli a5,a5,0x10 -800086f0: 03f70733 mul a4,a4,t6 -800086f4: 00970733 add a4,a4,s1 -800086f8: 00f70733 add a4,a4,a5 -800086fc: 01075293 srli t0,a4,0x10 -80008700: fb16e8e3 bltu a3,a7,800086b0 <__multiply+0x148> -80008704: 00ef2023 sw a4,0(t5) -80008708: 00458593 addi a1,a1,4 -8000870c: 004e0e13 addi t3,t3,4 -80008710: f1d5e8e3 bltu a1,t4,80008620 <__multiply+0xb8> -80008714: 02805463 blez s0,8000873c <__multiply+0x1d4> -80008718: ffc32783 lw a5,-4(t1) -8000871c: ffc30313 addi t1,t1,-4 -80008720: 00078863 beqz a5,80008730 <__multiply+0x1c8> -80008724: 0180006f j 8000873c <__multiply+0x1d4> -80008728: 00032783 lw a5,0(t1) -8000872c: 00079863 bnez a5,8000873c <__multiply+0x1d4> -80008730: fff40413 addi s0,s0,-1 -80008734: ffc30313 addi t1,t1,-4 -80008738: fe0418e3 bnez s0,80008728 <__multiply+0x1c0> -8000873c: 00852823 sw s0,16(a0) -80008740: 01c12083 lw ra,28(sp) -80008744: 01812403 lw s0,24(sp) -80008748: 01412483 lw s1,20(sp) -8000874c: 01012903 lw s2,16(sp) -80008750: 00c12983 lw s3,12(sp) -80008754: 00812a03 lw s4,8(sp) -80008758: 02010113 addi sp,sp,32 -8000875c: 00008067 ret - -80008760 <__pow5mult>: -80008760: fe010113 addi sp,sp,-32 -80008764: 00812c23 sw s0,24(sp) -80008768: 01312623 sw s3,12(sp) -8000876c: 01412423 sw s4,8(sp) -80008770: 00112e23 sw ra,28(sp) -80008774: 00912a23 sw s1,20(sp) -80008778: 01212823 sw s2,16(sp) -8000877c: 00367793 andi a5,a2,3 -80008780: 00060413 mv s0,a2 -80008784: 00050993 mv s3,a0 -80008788: 00058a13 mv s4,a1 -8000878c: 0c079463 bnez a5,80008854 <__pow5mult+0xf4> -80008790: 40245413 srai s0,s0,0x2 -80008794: 000a0913 mv s2,s4 -80008798: 06040863 beqz s0,80008808 <__pow5mult+0xa8> -8000879c: 0489a483 lw s1,72(s3) -800087a0: 0c048e63 beqz s1,8000887c <__pow5mult+0x11c> -800087a4: 00147793 andi a5,s0,1 -800087a8: 000a0913 mv s2,s4 -800087ac: 02079063 bnez a5,800087cc <__pow5mult+0x6c> -800087b0: 40145413 srai s0,s0,0x1 -800087b4: 04040a63 beqz s0,80008808 <__pow5mult+0xa8> -800087b8: 0004a503 lw a0,0(s1) -800087bc: 06050863 beqz a0,8000882c <__pow5mult+0xcc> -800087c0: 00050493 mv s1,a0 -800087c4: 00147793 andi a5,s0,1 -800087c8: fe0784e3 beqz a5,800087b0 <__pow5mult+0x50> -800087cc: 00048613 mv a2,s1 -800087d0: 00090593 mv a1,s2 -800087d4: 00098513 mv a0,s3 -800087d8: d91ff0ef jal ra,80008568 <__multiply> -800087dc: 06090863 beqz s2,8000884c <__pow5mult+0xec> -800087e0: 00492703 lw a4,4(s2) -800087e4: 04c9a783 lw a5,76(s3) -800087e8: 40145413 srai s0,s0,0x1 -800087ec: 00271713 slli a4,a4,0x2 -800087f0: 00e787b3 add a5,a5,a4 -800087f4: 0007a703 lw a4,0(a5) -800087f8: 00e92023 sw a4,0(s2) -800087fc: 0127a023 sw s2,0(a5) -80008800: 00050913 mv s2,a0 -80008804: fa041ae3 bnez s0,800087b8 <__pow5mult+0x58> -80008808: 01c12083 lw ra,28(sp) -8000880c: 01812403 lw s0,24(sp) -80008810: 00090513 mv a0,s2 -80008814: 01412483 lw s1,20(sp) -80008818: 01012903 lw s2,16(sp) -8000881c: 00c12983 lw s3,12(sp) -80008820: 00812a03 lw s4,8(sp) -80008824: 02010113 addi sp,sp,32 -80008828: 00008067 ret -8000882c: 00048613 mv a2,s1 -80008830: 00048593 mv a1,s1 -80008834: 00098513 mv a0,s3 -80008838: d31ff0ef jal ra,80008568 <__multiply> -8000883c: 00a4a023 sw a0,0(s1) -80008840: 00052023 sw zero,0(a0) -80008844: 00050493 mv s1,a0 -80008848: f7dff06f j 800087c4 <__pow5mult+0x64> -8000884c: 00050913 mv s2,a0 -80008850: f61ff06f j 800087b0 <__pow5mult+0x50> -80008854: fff78793 addi a5,a5,-1 -80008858: 80015737 lui a4,0x80015 -8000885c: aa070713 addi a4,a4,-1376 # 80014aa0 <__BSS_END__+0xffffdd28> -80008860: 00279793 slli a5,a5,0x2 -80008864: 00f707b3 add a5,a4,a5 -80008868: 0007a603 lw a2,0(a5) -8000886c: 00000693 li a3,0 -80008870: 965ff0ef jal ra,800081d4 <__multadd> -80008874: 00050a13 mv s4,a0 -80008878: f19ff06f j 80008790 <__pow5mult+0x30> -8000887c: 00100593 li a1,1 -80008880: 00098513 mv a0,s3 -80008884: 885ff0ef jal ra,80008108 <_Balloc> -80008888: 27100793 li a5,625 -8000888c: 00f52a23 sw a5,20(a0) -80008890: 00100793 li a5,1 -80008894: 00f52823 sw a5,16(a0) -80008898: 04a9a423 sw a0,72(s3) -8000889c: 00050493 mv s1,a0 -800088a0: 00052023 sw zero,0(a0) -800088a4: f01ff06f j 800087a4 <__pow5mult+0x44> - -800088a8 <__lshift>: -800088a8: fe010113 addi sp,sp,-32 -800088ac: 01412423 sw s4,8(sp) -800088b0: 0105aa03 lw s4,16(a1) -800088b4: 00912a23 sw s1,20(sp) -800088b8: 0085a783 lw a5,8(a1) -800088bc: 40565493 srai s1,a2,0x5 -800088c0: 01448a33 add s4,s1,s4 -800088c4: 00812c23 sw s0,24(sp) -800088c8: 01212823 sw s2,16(sp) -800088cc: 01312623 sw s3,12(sp) -800088d0: 01512223 sw s5,4(sp) -800088d4: 00112e23 sw ra,28(sp) -800088d8: 001a0413 addi s0,s4,1 -800088dc: 00058993 mv s3,a1 -800088e0: 00060913 mv s2,a2 -800088e4: 00050a93 mv s5,a0 -800088e8: 0045a583 lw a1,4(a1) -800088ec: 0087d863 bge a5,s0,800088fc <__lshift+0x54> -800088f0: 00179793 slli a5,a5,0x1 -800088f4: 00158593 addi a1,a1,1 -800088f8: fe87cce3 blt a5,s0,800088f0 <__lshift+0x48> -800088fc: 000a8513 mv a0,s5 -80008900: 809ff0ef jal ra,80008108 <_Balloc> -80008904: 01450713 addi a4,a0,20 -80008908: 02905463 blez s1,80008930 <__lshift+0x88> -8000890c: 00548493 addi s1,s1,5 -80008910: 00249493 slli s1,s1,0x2 -80008914: 009506b3 add a3,a0,s1 -80008918: 00070793 mv a5,a4 -8000891c: 00478793 addi a5,a5,4 -80008920: fe07ae23 sw zero,-4(a5) -80008924: fef69ce3 bne a3,a5,8000891c <__lshift+0x74> -80008928: fec48493 addi s1,s1,-20 -8000892c: 00970733 add a4,a4,s1 -80008930: 0109a803 lw a6,16(s3) -80008934: 01498793 addi a5,s3,20 -80008938: 01f97613 andi a2,s2,31 -8000893c: 00281813 slli a6,a6,0x2 -80008940: 01078833 add a6,a5,a6 -80008944: 08060263 beqz a2,800089c8 <__lshift+0x120> -80008948: 02000893 li a7,32 -8000894c: 40c888b3 sub a7,a7,a2 -80008950: 00000593 li a1,0 -80008954: 0007a683 lw a3,0(a5) -80008958: 00470713 addi a4,a4,4 -8000895c: 00478793 addi a5,a5,4 -80008960: 00c696b3 sll a3,a3,a2 -80008964: 00b6e6b3 or a3,a3,a1 -80008968: fed72e23 sw a3,-4(a4) -8000896c: ffc7a683 lw a3,-4(a5) -80008970: 0116d5b3 srl a1,a3,a7 -80008974: ff07e0e3 bltu a5,a6,80008954 <__lshift+0xac> -80008978: 00b72023 sw a1,0(a4) -8000897c: 00058463 beqz a1,80008984 <__lshift+0xdc> -80008980: 00040a13 mv s4,s0 -80008984: 0049a703 lw a4,4(s3) -80008988: 04caa783 lw a5,76(s5) -8000898c: 01c12083 lw ra,28(sp) -80008990: 00271713 slli a4,a4,0x2 -80008994: 00e787b3 add a5,a5,a4 -80008998: 0007a703 lw a4,0(a5) -8000899c: 01452823 sw s4,16(a0) -800089a0: 01812403 lw s0,24(sp) -800089a4: 00e9a023 sw a4,0(s3) -800089a8: 0137a023 sw s3,0(a5) -800089ac: 01412483 lw s1,20(sp) -800089b0: 01012903 lw s2,16(sp) -800089b4: 00c12983 lw s3,12(sp) -800089b8: 00812a03 lw s4,8(sp) -800089bc: 00412a83 lw s5,4(sp) -800089c0: 02010113 addi sp,sp,32 -800089c4: 00008067 ret -800089c8: 00478793 addi a5,a5,4 -800089cc: ffc7a683 lw a3,-4(a5) -800089d0: 00470713 addi a4,a4,4 -800089d4: fed72e23 sw a3,-4(a4) -800089d8: fb07f6e3 bgeu a5,a6,80008984 <__lshift+0xdc> -800089dc: 00478793 addi a5,a5,4 -800089e0: ffc7a683 lw a3,-4(a5) -800089e4: 00470713 addi a4,a4,4 -800089e8: fed72e23 sw a3,-4(a4) -800089ec: fd07eee3 bltu a5,a6,800089c8 <__lshift+0x120> -800089f0: f95ff06f j 80008984 <__lshift+0xdc> - -800089f4 <__mcmp>: -800089f4: 00050613 mv a2,a0 -800089f8: 0105a783 lw a5,16(a1) -800089fc: 01052503 lw a0,16(a0) -80008a00: 40f50533 sub a0,a0,a5 -80008a04: 02051e63 bnez a0,80008a40 <__mcmp+0x4c> -80008a08: 00279713 slli a4,a5,0x2 -80008a0c: 01460613 addi a2,a2,20 -80008a10: 01458593 addi a1,a1,20 -80008a14: 00e607b3 add a5,a2,a4 -80008a18: 00e585b3 add a1,a1,a4 -80008a1c: 0080006f j 80008a24 <__mcmp+0x30> -80008a20: 02f67063 bgeu a2,a5,80008a40 <__mcmp+0x4c> -80008a24: ffc78793 addi a5,a5,-4 -80008a28: ffc58593 addi a1,a1,-4 -80008a2c: 0007a683 lw a3,0(a5) -80008a30: 0005a703 lw a4,0(a1) -80008a34: fee686e3 beq a3,a4,80008a20 <__mcmp+0x2c> -80008a38: fff00513 li a0,-1 -80008a3c: 00e6f463 bgeu a3,a4,80008a44 <__mcmp+0x50> -80008a40: 00008067 ret -80008a44: 00100513 li a0,1 -80008a48: 00008067 ret - -80008a4c <__mdiff>: -80008a4c: fe010113 addi sp,sp,-32 -80008a50: 01212823 sw s2,16(sp) -80008a54: 01062703 lw a4,16(a2) -80008a58: 0105a903 lw s2,16(a1) -80008a5c: 00812c23 sw s0,24(sp) -80008a60: 00912a23 sw s1,20(sp) -80008a64: 01312623 sw s3,12(sp) -80008a68: 01412423 sw s4,8(sp) -80008a6c: 00112e23 sw ra,28(sp) -80008a70: 40e90933 sub s2,s2,a4 -80008a74: 00058993 mv s3,a1 -80008a78: 00060a13 mv s4,a2 -80008a7c: 01458413 addi s0,a1,20 -80008a80: 01460493 addi s1,a2,20 -80008a84: 04091863 bnez s2,80008ad4 <__mdiff+0x88> -80008a88: 00271713 slli a4,a4,0x2 -80008a8c: 00e407b3 add a5,s0,a4 -80008a90: 00e48733 add a4,s1,a4 -80008a94: 0080006f j 80008a9c <__mdiff+0x50> -80008a98: 16f47263 bgeu s0,a5,80008bfc <__mdiff+0x1b0> -80008a9c: ffc78793 addi a5,a5,-4 -80008aa0: ffc70713 addi a4,a4,-4 -80008aa4: 0007a583 lw a1,0(a5) -80008aa8: 00072683 lw a3,0(a4) -80008aac: fed586e3 beq a1,a3,80008a98 <__mdiff+0x4c> -80008ab0: 02d5f663 bgeu a1,a3,80008adc <__mdiff+0x90> -80008ab4: 00040713 mv a4,s0 -80008ab8: 00098793 mv a5,s3 -80008abc: 00048413 mv s0,s1 -80008ac0: 000a0993 mv s3,s4 -80008ac4: 00070493 mv s1,a4 -80008ac8: 00078a13 mv s4,a5 -80008acc: 00100913 li s2,1 -80008ad0: 00c0006f j 80008adc <__mdiff+0x90> -80008ad4: fe0940e3 bltz s2,80008ab4 <__mdiff+0x68> -80008ad8: 00000913 li s2,0 -80008adc: 0049a583 lw a1,4(s3) -80008ae0: e28ff0ef jal ra,80008108 <_Balloc> -80008ae4: 0109a303 lw t1,16(s3) -80008ae8: 010a2e83 lw t4,16(s4) -80008aec: 00010637 lui a2,0x10 -80008af0: 00231e13 slli t3,t1,0x2 -80008af4: 002e9e93 slli t4,t4,0x2 -80008af8: 01252623 sw s2,12(a0) -80008afc: 01c40e33 add t3,s0,t3 -80008b00: 01d48eb3 add t4,s1,t4 -80008b04: 01450813 addi a6,a0,20 -80008b08: 00000793 li a5,0 -80008b0c: fff60613 addi a2,a2,-1 # ffff <_start-0x7fff0001> -80008b10: 0080006f j 80008b18 <__mdiff+0xcc> -80008b14: 00088813 mv a6,a7 -80008b18: 00042703 lw a4,0(s0) -80008b1c: 0004a583 lw a1,0(s1) -80008b20: 00480893 addi a7,a6,4 -80008b24: 00c776b3 and a3,a4,a2 -80008b28: 00f686b3 add a3,a3,a5 -80008b2c: 00c5f7b3 and a5,a1,a2 -80008b30: 40f686b3 sub a3,a3,a5 -80008b34: 0105d593 srli a1,a1,0x10 -80008b38: 01075793 srli a5,a4,0x10 -80008b3c: 40b787b3 sub a5,a5,a1 -80008b40: 4106d713 srai a4,a3,0x10 -80008b44: 00e787b3 add a5,a5,a4 -80008b48: 01079713 slli a4,a5,0x10 -80008b4c: 00c6f6b3 and a3,a3,a2 -80008b50: 00d766b3 or a3,a4,a3 -80008b54: 00448493 addi s1,s1,4 -80008b58: fed8ae23 sw a3,-4(a7) -80008b5c: 00440413 addi s0,s0,4 -80008b60: 4107d793 srai a5,a5,0x10 -80008b64: fbd4e8e3 bltu s1,t4,80008b14 <__mdiff+0xc8> -80008b68: 05c47e63 bgeu s0,t3,80008bc4 <__mdiff+0x178> -80008b6c: 00010eb7 lui t4,0x10 -80008b70: 00088813 mv a6,a7 -80008b74: 00040593 mv a1,s0 -80008b78: fffe8e93 addi t4,t4,-1 # ffff <_start-0x7fff0001> -80008b7c: 0005a703 lw a4,0(a1) -80008b80: 00480813 addi a6,a6,4 -80008b84: 00458593 addi a1,a1,4 -80008b88: 01d77633 and a2,a4,t4 -80008b8c: 00f60633 add a2,a2,a5 -80008b90: 41065693 srai a3,a2,0x10 -80008b94: 01075793 srli a5,a4,0x10 -80008b98: 00d787b3 add a5,a5,a3 -80008b9c: 01079693 slli a3,a5,0x10 -80008ba0: 01d67633 and a2,a2,t4 -80008ba4: 00c6e6b3 or a3,a3,a2 -80008ba8: fed82e23 sw a3,-4(a6) -80008bac: 4107d793 srai a5,a5,0x10 -80008bb0: fdc5e6e3 bltu a1,t3,80008b7c <__mdiff+0x130> -80008bb4: fffe0813 addi a6,t3,-1 -80008bb8: 40880833 sub a6,a6,s0 -80008bbc: ffc87813 andi a6,a6,-4 -80008bc0: 01088833 add a6,a7,a6 -80008bc4: 00069a63 bnez a3,80008bd8 <__mdiff+0x18c> -80008bc8: ffc80813 addi a6,a6,-4 -80008bcc: 00082783 lw a5,0(a6) -80008bd0: fff30313 addi t1,t1,-1 -80008bd4: fe078ae3 beqz a5,80008bc8 <__mdiff+0x17c> -80008bd8: 01c12083 lw ra,28(sp) -80008bdc: 01812403 lw s0,24(sp) -80008be0: 00652823 sw t1,16(a0) -80008be4: 01412483 lw s1,20(sp) -80008be8: 01012903 lw s2,16(sp) -80008bec: 00c12983 lw s3,12(sp) -80008bf0: 00812a03 lw s4,8(sp) -80008bf4: 02010113 addi sp,sp,32 -80008bf8: 00008067 ret -80008bfc: 00000593 li a1,0 -80008c00: d08ff0ef jal ra,80008108 <_Balloc> -80008c04: 01c12083 lw ra,28(sp) -80008c08: 01812403 lw s0,24(sp) -80008c0c: 00100793 li a5,1 -80008c10: 00f52823 sw a5,16(a0) -80008c14: 00052a23 sw zero,20(a0) -80008c18: 01412483 lw s1,20(sp) -80008c1c: 01012903 lw s2,16(sp) -80008c20: 00c12983 lw s3,12(sp) -80008c24: 00812a03 lw s4,8(sp) -80008c28: 02010113 addi sp,sp,32 -80008c2c: 00008067 ret - -80008c30 <__ulp>: -80008c30: 7ff007b7 lui a5,0x7ff00 -80008c34: 00b7f5b3 and a1,a5,a1 -80008c38: fcc007b7 lui a5,0xfcc00 -80008c3c: 00f585b3 add a1,a1,a5 -80008c40: 00b05863 blez a1,80008c50 <__ulp+0x20> -80008c44: 00000793 li a5,0 -80008c48: 00078513 mv a0,a5 -80008c4c: 00008067 ret -80008c50: 40b005b3 neg a1,a1 -80008c54: 4145d593 srai a1,a1,0x14 -80008c58: 01300793 li a5,19 -80008c5c: 00b7c863 blt a5,a1,80008c6c <__ulp+0x3c> -80008c60: 000807b7 lui a5,0x80 -80008c64: 40b7d5b3 sra a1,a5,a1 -80008c68: fddff06f j 80008c44 <__ulp+0x14> -80008c6c: fec58713 addi a4,a1,-20 -80008c70: 01e00693 li a3,30 -80008c74: 00000593 li a1,0 -80008c78: 00100793 li a5,1 -80008c7c: fce6c6e3 blt a3,a4,80008c48 <__ulp+0x18> -80008c80: 800007b7 lui a5,0x80000 -80008c84: 00e7d7b3 srl a5,a5,a4 -80008c88: 00078513 mv a0,a5 -80008c8c: 00008067 ret - -80008c90 <__b2d>: -80008c90: fe010113 addi sp,sp,-32 -80008c94: 00812c23 sw s0,24(sp) -80008c98: 01052403 lw s0,16(a0) -80008c9c: 00912a23 sw s1,20(sp) -80008ca0: 01450493 addi s1,a0,20 -80008ca4: 00241413 slli s0,s0,0x2 -80008ca8: 00848433 add s0,s1,s0 -80008cac: 01212823 sw s2,16(sp) -80008cb0: ffc42903 lw s2,-4(s0) -80008cb4: 01312623 sw s3,12(sp) -80008cb8: 01412423 sw s4,8(sp) -80008cbc: 00090513 mv a0,s2 -80008cc0: 00058a13 mv s4,a1 -80008cc4: 00112e23 sw ra,28(sp) -80008cc8: f40ff0ef jal ra,80008408 <__hi0bits> -80008ccc: 02000713 li a4,32 -80008cd0: 40a707b3 sub a5,a4,a0 -80008cd4: 00fa2023 sw a5,0(s4) -80008cd8: 00a00793 li a5,10 -80008cdc: ffc40993 addi s3,s0,-4 -80008ce0: 08a7d063 bge a5,a0,80008d60 <__b2d+0xd0> -80008ce4: ff550513 addi a0,a0,-11 -80008ce8: 0534f063 bgeu s1,s3,80008d28 <__b2d+0x98> -80008cec: ff842783 lw a5,-8(s0) -80008cf0: 04050063 beqz a0,80008d30 <__b2d+0xa0> -80008cf4: 40a70633 sub a2,a4,a0 -80008cf8: 00c7d733 srl a4,a5,a2 -80008cfc: 00a916b3 sll a3,s2,a0 -80008d00: 00e6e6b3 or a3,a3,a4 -80008d04: ff840593 addi a1,s0,-8 -80008d08: 3ff00737 lui a4,0x3ff00 -80008d0c: 00e6e6b3 or a3,a3,a4 -80008d10: 00a797b3 sll a5,a5,a0 -80008d14: 02b4f263 bgeu s1,a1,80008d38 <__b2d+0xa8> -80008d18: ff442703 lw a4,-12(s0) -80008d1c: 00c75733 srl a4,a4,a2 -80008d20: 00e7e7b3 or a5,a5,a4 -80008d24: 0140006f j 80008d38 <__b2d+0xa8> -80008d28: 00000793 li a5,0 -80008d2c: 06051463 bnez a0,80008d94 <__b2d+0x104> -80008d30: 3ff00737 lui a4,0x3ff00 -80008d34: 00e966b3 or a3,s2,a4 -80008d38: 01c12083 lw ra,28(sp) -80008d3c: 01812403 lw s0,24(sp) -80008d40: 01412483 lw s1,20(sp) -80008d44: 01012903 lw s2,16(sp) -80008d48: 00c12983 lw s3,12(sp) -80008d4c: 00812a03 lw s4,8(sp) -80008d50: 00078513 mv a0,a5 -80008d54: 00068593 mv a1,a3 -80008d58: 02010113 addi sp,sp,32 -80008d5c: 00008067 ret -80008d60: 00b00613 li a2,11 -80008d64: 40a60633 sub a2,a2,a0 -80008d68: 00c95733 srl a4,s2,a2 -80008d6c: 3ff006b7 lui a3,0x3ff00 -80008d70: 00d766b3 or a3,a4,a3 -80008d74: 00000713 li a4,0 -80008d78: 0134f663 bgeu s1,s3,80008d84 <__b2d+0xf4> -80008d7c: ff842703 lw a4,-8(s0) -80008d80: 00c75733 srl a4,a4,a2 -80008d84: 01550513 addi a0,a0,21 -80008d88: 00a91533 sll a0,s2,a0 -80008d8c: 00e567b3 or a5,a0,a4 -80008d90: fa9ff06f j 80008d38 <__b2d+0xa8> -80008d94: 00a91533 sll a0,s2,a0 -80008d98: 3ff00737 lui a4,0x3ff00 -80008d9c: 00e566b3 or a3,a0,a4 -80008da0: 00000793 li a5,0 -80008da4: f95ff06f j 80008d38 <__b2d+0xa8> - -80008da8 <__d2b>: -80008da8: fd010113 addi sp,sp,-48 -80008dac: 01512a23 sw s5,20(sp) -80008db0: 00058a93 mv s5,a1 -80008db4: 00100593 li a1,1 -80008db8: 02812423 sw s0,40(sp) -80008dbc: 02912223 sw s1,36(sp) -80008dc0: 03212023 sw s2,32(sp) -80008dc4: 00060493 mv s1,a2 -80008dc8: 01312e23 sw s3,28(sp) -80008dcc: 01412c23 sw s4,24(sp) -80008dd0: 02112623 sw ra,44(sp) -80008dd4: 00068a13 mv s4,a3 -80008dd8: 00070993 mv s3,a4 -80008ddc: b2cff0ef jal ra,80008108 <_Balloc> -80008de0: 00100637 lui a2,0x100 -80008de4: 0144d413 srli s0,s1,0x14 -80008de8: fff60793 addi a5,a2,-1 # fffff <_start-0x7ff00001> -80008dec: 7ff47413 andi s0,s0,2047 -80008df0: 00050913 mv s2,a0 -80008df4: 0097f7b3 and a5,a5,s1 -80008df8: 00040463 beqz s0,80008e00 <__d2b+0x58> -80008dfc: 00c7e7b3 or a5,a5,a2 -80008e00: 00f12623 sw a5,12(sp) -80008e04: 080a8e63 beqz s5,80008ea0 <__d2b+0xf8> -80008e08: 00810513 addi a0,sp,8 -80008e0c: 01512423 sw s5,8(sp) -80008e10: e6cff0ef jal ra,8000847c <__lo0bits> -80008e14: 00050793 mv a5,a0 -80008e18: 00c12703 lw a4,12(sp) -80008e1c: 06051063 bnez a0,80008e7c <__d2b+0xd4> -80008e20: 00812683 lw a3,8(sp) -80008e24: 00d92a23 sw a3,20(s2) -80008e28: 00e034b3 snez s1,a4 -80008e2c: 00148493 addi s1,s1,1 -80008e30: 00e92c23 sw a4,24(s2) -80008e34: 00992823 sw s1,16(s2) -80008e38: 08040663 beqz s0,80008ec4 <__d2b+0x11c> -80008e3c: bcd40413 addi s0,s0,-1075 -80008e40: 00f40433 add s0,s0,a5 -80008e44: 03500713 li a4,53 -80008e48: 008a2023 sw s0,0(s4) -80008e4c: 40f707b3 sub a5,a4,a5 -80008e50: 00f9a023 sw a5,0(s3) -80008e54: 02c12083 lw ra,44(sp) -80008e58: 02812403 lw s0,40(sp) -80008e5c: 00090513 mv a0,s2 -80008e60: 02412483 lw s1,36(sp) -80008e64: 02012903 lw s2,32(sp) -80008e68: 01c12983 lw s3,28(sp) -80008e6c: 01812a03 lw s4,24(sp) -80008e70: 01412a83 lw s5,20(sp) -80008e74: 03010113 addi sp,sp,48 -80008e78: 00008067 ret -80008e7c: 02000693 li a3,32 -80008e80: 00812603 lw a2,8(sp) -80008e84: 40a686b3 sub a3,a3,a0 -80008e88: 00d716b3 sll a3,a4,a3 -80008e8c: 00c6e6b3 or a3,a3,a2 -80008e90: 00a75733 srl a4,a4,a0 -80008e94: 00d92a23 sw a3,20(s2) -80008e98: 00e12623 sw a4,12(sp) -80008e9c: f8dff06f j 80008e28 <__d2b+0x80> -80008ea0: 00c10513 addi a0,sp,12 -80008ea4: dd8ff0ef jal ra,8000847c <__lo0bits> -80008ea8: 00100793 li a5,1 -80008eac: 00f92823 sw a5,16(s2) -80008eb0: 00c12783 lw a5,12(sp) -80008eb4: 00100493 li s1,1 -80008eb8: 00f92a23 sw a5,20(s2) -80008ebc: 02050793 addi a5,a0,32 -80008ec0: f6041ee3 bnez s0,80008e3c <__d2b+0x94> -80008ec4: 00249713 slli a4,s1,0x2 -80008ec8: 00e90733 add a4,s2,a4 -80008ecc: 01072503 lw a0,16(a4) # 3ff00010 <_start-0x400ffff0> -80008ed0: bce78793 addi a5,a5,-1074 # 7ffffbce <__BSS_END__+0xfffe8e56> -80008ed4: 00fa2023 sw a5,0(s4) -80008ed8: d30ff0ef jal ra,80008408 <__hi0bits> -80008edc: 00549493 slli s1,s1,0x5 -80008ee0: 40a484b3 sub s1,s1,a0 -80008ee4: 0099a023 sw s1,0(s3) -80008ee8: f6dff06f j 80008e54 <__d2b+0xac> - -80008eec <__ratio>: -80008eec: fd010113 addi sp,sp,-48 -80008ef0: 03212023 sw s2,32(sp) -80008ef4: 00058913 mv s2,a1 -80008ef8: 00810593 addi a1,sp,8 -80008efc: 02112623 sw ra,44(sp) -80008f00: 02812423 sw s0,40(sp) -80008f04: 02912223 sw s1,36(sp) -80008f08: 01312e23 sw s3,28(sp) -80008f0c: 00050993 mv s3,a0 -80008f10: d81ff0ef jal ra,80008c90 <__b2d> -80008f14: 00050493 mv s1,a0 -80008f18: 00058413 mv s0,a1 -80008f1c: 00090513 mv a0,s2 -80008f20: 00c10593 addi a1,sp,12 -80008f24: d6dff0ef jal ra,80008c90 <__b2d> -80008f28: 01092783 lw a5,16(s2) -80008f2c: 0109a703 lw a4,16(s3) -80008f30: 00812683 lw a3,8(sp) -80008f34: 40f70733 sub a4,a4,a5 -80008f38: 00c12783 lw a5,12(sp) -80008f3c: 00571713 slli a4,a4,0x5 -80008f40: 40f686b3 sub a3,a3,a5 -80008f44: 00d707b3 add a5,a4,a3 -80008f48: 02f05e63 blez a5,80008f84 <__ratio+0x98> -80008f4c: 01479793 slli a5,a5,0x14 -80008f50: 00878433 add s0,a5,s0 -80008f54: 00050613 mv a2,a0 -80008f58: 00058693 mv a3,a1 -80008f5c: 00048513 mv a0,s1 -80008f60: 00040593 mv a1,s0 -80008f64: 085070ef jal ra,800107e8 <__divdf3> -80008f68: 02c12083 lw ra,44(sp) -80008f6c: 02812403 lw s0,40(sp) -80008f70: 02412483 lw s1,36(sp) -80008f74: 02012903 lw s2,32(sp) -80008f78: 01c12983 lw s3,28(sp) -80008f7c: 03010113 addi sp,sp,48 -80008f80: 00008067 ret -80008f84: 01479713 slli a4,a5,0x14 -80008f88: 40e585b3 sub a1,a1,a4 -80008f8c: fc9ff06f j 80008f54 <__ratio+0x68> - -80008f90 <_mprec_log10>: -80008f90: ff010113 addi sp,sp,-16 -80008f94: 00812423 sw s0,8(sp) -80008f98: 00112623 sw ra,12(sp) -80008f9c: 01212223 sw s2,4(sp) -80008fa0: 01312023 sw s3,0(sp) -80008fa4: 01700793 li a5,23 -80008fa8: 00050413 mv s0,a0 -80008fac: 04a7d463 bge a5,a0,80008ff4 <_mprec_log10+0x64> -80008fb0: 800177b7 lui a5,0x80017 -80008fb4: d087a503 lw a0,-760(a5) # 80016d08 <__BSS_END__+0xffffff90> -80008fb8: d0c7a583 lw a1,-756(a5) -80008fbc: 800177b7 lui a5,0x80017 -80008fc0: d107a903 lw s2,-752(a5) # 80016d10 <__BSS_END__+0xffffff98> -80008fc4: d147a983 lw s3,-748(a5) -80008fc8: fff40413 addi s0,s0,-1 -80008fcc: 00090613 mv a2,s2 -80008fd0: 00098693 mv a3,s3 -80008fd4: 6dd070ef jal ra,80010eb0 <__muldf3> -80008fd8: fe0418e3 bnez s0,80008fc8 <_mprec_log10+0x38> -80008fdc: 00c12083 lw ra,12(sp) -80008fe0: 00812403 lw s0,8(sp) -80008fe4: 00412903 lw s2,4(sp) -80008fe8: 00012983 lw s3,0(sp) -80008fec: 01010113 addi sp,sp,16 -80008ff0: 00008067 ret -80008ff4: 800157b7 lui a5,0x80015 -80008ff8: 00351413 slli s0,a0,0x3 -80008ffc: aa078793 addi a5,a5,-1376 # 80014aa0 <__BSS_END__+0xffffdd28> -80009000: 00878433 add s0,a5,s0 -80009004: 01042503 lw a0,16(s0) -80009008: 01442583 lw a1,20(s0) -8000900c: 00c12083 lw ra,12(sp) -80009010: 00812403 lw s0,8(sp) -80009014: 00412903 lw s2,4(sp) -80009018: 00012983 lw s3,0(sp) -8000901c: 01010113 addi sp,sp,16 -80009020: 00008067 ret - -80009024 <__copybits>: -80009024: 01062683 lw a3,16(a2) -80009028: fff58593 addi a1,a1,-1 -8000902c: 4055d593 srai a1,a1,0x5 -80009030: 00158593 addi a1,a1,1 -80009034: 01460793 addi a5,a2,20 -80009038: 00269693 slli a3,a3,0x2 -8000903c: 00259593 slli a1,a1,0x2 -80009040: 00d786b3 add a3,a5,a3 -80009044: 00b505b3 add a1,a0,a1 -80009048: 02d7f863 bgeu a5,a3,80009078 <__copybits+0x54> -8000904c: 00050713 mv a4,a0 -80009050: 00478793 addi a5,a5,4 -80009054: ffc7a803 lw a6,-4(a5) -80009058: 00470713 addi a4,a4,4 -8000905c: ff072e23 sw a6,-4(a4) -80009060: fed7e8e3 bltu a5,a3,80009050 <__copybits+0x2c> -80009064: 40c687b3 sub a5,a3,a2 -80009068: feb78793 addi a5,a5,-21 -8000906c: ffc7f793 andi a5,a5,-4 -80009070: 00478793 addi a5,a5,4 -80009074: 00f50533 add a0,a0,a5 -80009078: 00b57863 bgeu a0,a1,80009088 <__copybits+0x64> -8000907c: 00450513 addi a0,a0,4 -80009080: fe052e23 sw zero,-4(a0) -80009084: feb56ce3 bltu a0,a1,8000907c <__copybits+0x58> -80009088: 00008067 ret - -8000908c <__any_on>: -8000908c: 01052703 lw a4,16(a0) -80009090: 4055d613 srai a2,a1,0x5 -80009094: 01450693 addi a3,a0,20 -80009098: 02c75a63 bge a4,a2,800090cc <__any_on+0x40> -8000909c: 00271793 slli a5,a4,0x2 -800090a0: 00f687b3 add a5,a3,a5 -800090a4: 04f6fc63 bgeu a3,a5,800090fc <__any_on+0x70> -800090a8: ffc7a503 lw a0,-4(a5) -800090ac: ffc78793 addi a5,a5,-4 -800090b0: 00051a63 bnez a0,800090c4 <__any_on+0x38> -800090b4: 04f6f263 bgeu a3,a5,800090f8 <__any_on+0x6c> -800090b8: ffc78793 addi a5,a5,-4 -800090bc: 0007a703 lw a4,0(a5) -800090c0: fe070ae3 beqz a4,800090b4 <__any_on+0x28> -800090c4: 00100513 li a0,1 -800090c8: 00008067 ret -800090cc: 00261793 slli a5,a2,0x2 -800090d0: 00f687b3 add a5,a3,a5 -800090d4: fce658e3 bge a2,a4,800090a4 <__any_on+0x18> -800090d8: 01f5f593 andi a1,a1,31 -800090dc: fc0584e3 beqz a1,800090a4 <__any_on+0x18> -800090e0: 0007a603 lw a2,0(a5) -800090e4: 00100513 li a0,1 -800090e8: 00b65733 srl a4,a2,a1 -800090ec: 00b715b3 sll a1,a4,a1 -800090f0: fab60ae3 beq a2,a1,800090a4 <__any_on+0x18> -800090f4: 00008067 ret -800090f8: 00008067 ret -800090fc: 00000513 li a0,0 -80009100: 00008067 ret - -80009104 : -80009104: ff010113 addi sp,sp,-16 -80009108: 00812423 sw s0,8(sp) -8000910c: 80000437 lui s0,0x80000 -80009110: 00912223 sw s1,4(sp) -80009114: 00112623 sw ra,12(sp) -80009118: fff44413 not s0,s0 -8000911c: 00060493 mv s1,a2 -80009120: 00062023 sw zero,0(a2) -80009124: 00b47733 and a4,s0,a1 -80009128: 7ff00637 lui a2,0x7ff00 -8000912c: 00058793 mv a5,a1 -80009130: 00050693 mv a3,a0 -80009134: 06c75063 bge a4,a2,80009194 -80009138: 00a768b3 or a7,a4,a0 -8000913c: 04088c63 beqz a7,80009194 -80009140: 00c5f633 and a2,a1,a2 -80009144: 00058813 mv a6,a1 -80009148: 00000893 li a7,0 -8000914c: 02061263 bnez a2,80009170 -80009150: 800177b7 lui a5,0x80017 -80009154: d1c7a683 lw a3,-740(a5) # 80016d1c <__BSS_END__+0xffffffa4> -80009158: d187a603 lw a2,-744(a5) -8000915c: 555070ef jal ra,80010eb0 <__muldf3> -80009160: 00050693 mv a3,a0 -80009164: 00058813 mv a6,a1 -80009168: 00b47733 and a4,s0,a1 -8000916c: fca00893 li a7,-54 -80009170: 41475713 srai a4,a4,0x14 -80009174: 801007b7 lui a5,0x80100 -80009178: fff78793 addi a5,a5,-1 # 800fffff <__BSS_END__+0xe9287> -8000917c: c0270713 addi a4,a4,-1022 -80009180: 00f87833 and a6,a6,a5 -80009184: 01170733 add a4,a4,a7 -80009188: 3fe007b7 lui a5,0x3fe00 -8000918c: 00f867b3 or a5,a6,a5 -80009190: 00e4a023 sw a4,0(s1) -80009194: 00c12083 lw ra,12(sp) -80009198: 00812403 lw s0,8(sp) -8000919c: 00412483 lw s1,4(sp) -800091a0: 00068513 mv a0,a3 -800091a4: 00078593 mv a1,a5 -800091a8: 01010113 addi sp,sp,16 -800091ac: 00008067 ret - -800091b0 <_sprintf_r>: -800091b0: f6010113 addi sp,sp,-160 -800091b4: 08c10e13 addi t3,sp,140 -800091b8: 08f12a23 sw a5,148(sp) -800091bc: 80000337 lui t1,0x80000 -800091c0: ffff07b7 lui a5,0xffff0 -800091c4: 00058e93 mv t4,a1 -800091c8: fff34313 not t1,t1 -800091cc: 08d12623 sw a3,140(sp) -800091d0: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd9490> -800091d4: 00810593 addi a1,sp,8 -800091d8: 000e0693 mv a3,t3 -800091dc: 06112e23 sw ra,124(sp) -800091e0: 00f12a23 sw a5,20(sp) -800091e4: 08e12823 sw a4,144(sp) -800091e8: 09012c23 sw a6,152(sp) -800091ec: 09112e23 sw a7,156(sp) -800091f0: 01d12423 sw t4,8(sp) -800091f4: 01d12c23 sw t4,24(sp) -800091f8: 00612e23 sw t1,28(sp) -800091fc: 00612823 sw t1,16(sp) -80009200: 01c12223 sw t3,4(sp) -80009204: 570000ef jal ra,80009774 <_svfprintf_r> -80009208: 00812783 lw a5,8(sp) -8000920c: 00078023 sb zero,0(a5) -80009210: 07c12083 lw ra,124(sp) -80009214: 0a010113 addi sp,sp,160 -80009218: 00008067 ret - -8000921c : -8000921c: 00050e93 mv t4,a0 -80009220: f6010113 addi sp,sp,-160 -80009224: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -80009228: 08810e13 addi t3,sp,136 -8000922c: 08f12a23 sw a5,148(sp) -80009230: 80000337 lui t1,0x80000 -80009234: ffff07b7 lui a5,0xffff0 -80009238: fff34313 not t1,t1 -8000923c: 08c12423 sw a2,136(sp) -80009240: 08d12623 sw a3,140(sp) -80009244: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd9490> -80009248: 00058613 mv a2,a1 -8000924c: 000e0693 mv a3,t3 -80009250: 00810593 addi a1,sp,8 -80009254: 06112e23 sw ra,124(sp) -80009258: 00f12a23 sw a5,20(sp) -8000925c: 08e12823 sw a4,144(sp) -80009260: 09012c23 sw a6,152(sp) -80009264: 09112e23 sw a7,156(sp) -80009268: 01d12423 sw t4,8(sp) -8000926c: 01d12c23 sw t4,24(sp) -80009270: 00612e23 sw t1,28(sp) -80009274: 00612823 sw t1,16(sp) -80009278: 01c12223 sw t3,4(sp) -8000927c: 4f8000ef jal ra,80009774 <_svfprintf_r> -80009280: 00812783 lw a5,8(sp) -80009284: 00078023 sb zero,0(a5) -80009288: 07c12083 lw ra,124(sp) -8000928c: 0a010113 addi sp,sp,160 -80009290: 00008067 ret - -80009294 <__sread>: -80009294: ff010113 addi sp,sp,-16 -80009298: 00812423 sw s0,8(sp) -8000929c: 00058413 mv s0,a1 -800092a0: 00e59583 lh a1,14(a1) -800092a4: 00112623 sw ra,12(sp) -800092a8: 118050ef jal ra,8000e3c0 <_read_r> -800092ac: 02054063 bltz a0,800092cc <__sread+0x38> -800092b0: 05042783 lw a5,80(s0) # 80000050 <__BSS_END__+0xfffe92d8> -800092b4: 00c12083 lw ra,12(sp) -800092b8: 00a787b3 add a5,a5,a0 -800092bc: 04f42823 sw a5,80(s0) -800092c0: 00812403 lw s0,8(sp) -800092c4: 01010113 addi sp,sp,16 -800092c8: 00008067 ret -800092cc: 00c45783 lhu a5,12(s0) -800092d0: fffff737 lui a4,0xfffff -800092d4: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe8287> -800092d8: 00e7f7b3 and a5,a5,a4 -800092dc: 00f41623 sh a5,12(s0) -800092e0: 00c12083 lw ra,12(sp) -800092e4: 00812403 lw s0,8(sp) -800092e8: 01010113 addi sp,sp,16 -800092ec: 00008067 ret - -800092f0 <__seofread>: -800092f0: 00000513 li a0,0 -800092f4: 00008067 ret - -800092f8 <__swrite>: -800092f8: 00c59783 lh a5,12(a1) -800092fc: fe010113 addi sp,sp,-32 -80009300: 00812c23 sw s0,24(sp) -80009304: 00912a23 sw s1,20(sp) -80009308: 01212823 sw s2,16(sp) -8000930c: 01312623 sw s3,12(sp) -80009310: 00112e23 sw ra,28(sp) -80009314: 1007f713 andi a4,a5,256 -80009318: 00058413 mv s0,a1 -8000931c: 00050493 mv s1,a0 -80009320: 00060913 mv s2,a2 -80009324: 00068993 mv s3,a3 -80009328: 00e59583 lh a1,14(a1) -8000932c: 02071e63 bnez a4,80009368 <__swrite+0x70> -80009330: fffff737 lui a4,0xfffff -80009334: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe8287> -80009338: 00e7f7b3 and a5,a5,a4 -8000933c: 00f41623 sh a5,12(s0) -80009340: 01812403 lw s0,24(sp) -80009344: 01c12083 lw ra,28(sp) -80009348: 00098693 mv a3,s3 -8000934c: 00090613 mv a2,s2 -80009350: 00c12983 lw s3,12(sp) -80009354: 01012903 lw s2,16(sp) -80009358: 00048513 mv a0,s1 -8000935c: 01412483 lw s1,20(sp) -80009360: 02010113 addi sp,sp,32 -80009364: 3e00406f j 8000d744 <_write_r> -80009368: 00200693 li a3,2 -8000936c: 00000613 li a2,0 -80009370: 5ad040ef jal ra,8000e11c <_lseek_r> -80009374: 00c41783 lh a5,12(s0) -80009378: 00e41583 lh a1,14(s0) -8000937c: fb5ff06f j 80009330 <__swrite+0x38> - -80009380 <__sseek>: -80009380: ff010113 addi sp,sp,-16 -80009384: 00812423 sw s0,8(sp) -80009388: 00058413 mv s0,a1 -8000938c: 00e59583 lh a1,14(a1) -80009390: 00112623 sw ra,12(sp) -80009394: 589040ef jal ra,8000e11c <_lseek_r> -80009398: fff00793 li a5,-1 -8000939c: 02f50463 beq a0,a5,800093c4 <__sseek+0x44> -800093a0: 00c45783 lhu a5,12(s0) -800093a4: 00001737 lui a4,0x1 -800093a8: 04a42823 sw a0,80(s0) -800093ac: 00e7e7b3 or a5,a5,a4 -800093b0: 00f41623 sh a5,12(s0) -800093b4: 00c12083 lw ra,12(sp) -800093b8: 00812403 lw s0,8(sp) -800093bc: 01010113 addi sp,sp,16 -800093c0: 00008067 ret -800093c4: 00c45783 lhu a5,12(s0) -800093c8: fffff737 lui a4,0xfffff -800093cc: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe8287> -800093d0: 00e7f7b3 and a5,a5,a4 -800093d4: 00f41623 sh a5,12(s0) -800093d8: 00c12083 lw ra,12(sp) -800093dc: 00812403 lw s0,8(sp) -800093e0: 01010113 addi sp,sp,16 -800093e4: 00008067 ret - -800093e8 <__sclose>: -800093e8: 00e59583 lh a1,14(a1) -800093ec: 4700406f j 8000d85c <_close_r> - -800093f0 : -800093f0: 00b56733 or a4,a0,a1 -800093f4: fff00393 li t2,-1 -800093f8: 00377713 andi a4,a4,3 -800093fc: 10071063 bnez a4,800094fc -80009400: 7f7f87b7 lui a5,0x7f7f8 -80009404: f7f78793 addi a5,a5,-129 # 7f7f7f7f <_start-0x808081> -80009408: 00052603 lw a2,0(a0) -8000940c: 0005a683 lw a3,0(a1) -80009410: 00f672b3 and t0,a2,a5 -80009414: 00f66333 or t1,a2,a5 -80009418: 00f282b3 add t0,t0,a5 -8000941c: 0062e2b3 or t0,t0,t1 -80009420: 10729263 bne t0,t2,80009524 -80009424: 08d61663 bne a2,a3,800094b0 -80009428: 00452603 lw a2,4(a0) -8000942c: 0045a683 lw a3,4(a1) -80009430: 00f672b3 and t0,a2,a5 -80009434: 00f66333 or t1,a2,a5 -80009438: 00f282b3 add t0,t0,a5 -8000943c: 0062e2b3 or t0,t0,t1 -80009440: 0c729e63 bne t0,t2,8000951c -80009444: 06d61663 bne a2,a3,800094b0 -80009448: 00852603 lw a2,8(a0) -8000944c: 0085a683 lw a3,8(a1) -80009450: 00f672b3 and t0,a2,a5 -80009454: 00f66333 or t1,a2,a5 -80009458: 00f282b3 add t0,t0,a5 -8000945c: 0062e2b3 or t0,t0,t1 -80009460: 0c729863 bne t0,t2,80009530 -80009464: 04d61663 bne a2,a3,800094b0 -80009468: 00c52603 lw a2,12(a0) -8000946c: 00c5a683 lw a3,12(a1) -80009470: 00f672b3 and t0,a2,a5 -80009474: 00f66333 or t1,a2,a5 -80009478: 00f282b3 add t0,t0,a5 -8000947c: 0062e2b3 or t0,t0,t1 -80009480: 0c729263 bne t0,t2,80009544 -80009484: 02d61663 bne a2,a3,800094b0 -80009488: 01052603 lw a2,16(a0) -8000948c: 0105a683 lw a3,16(a1) -80009490: 00f672b3 and t0,a2,a5 -80009494: 00f66333 or t1,a2,a5 -80009498: 00f282b3 add t0,t0,a5 -8000949c: 0062e2b3 or t0,t0,t1 -800094a0: 0a729c63 bne t0,t2,80009558 -800094a4: 01450513 addi a0,a0,20 -800094a8: 01458593 addi a1,a1,20 -800094ac: f4d60ee3 beq a2,a3,80009408 -800094b0: 01061713 slli a4,a2,0x10 -800094b4: 01069793 slli a5,a3,0x10 -800094b8: 00f71e63 bne a4,a5,800094d4 -800094bc: 01065713 srli a4,a2,0x10 -800094c0: 0106d793 srli a5,a3,0x10 -800094c4: 40f70533 sub a0,a4,a5 -800094c8: 0ff57593 andi a1,a0,255 -800094cc: 02059063 bnez a1,800094ec -800094d0: 00008067 ret -800094d4: 01075713 srli a4,a4,0x10 -800094d8: 0107d793 srli a5,a5,0x10 -800094dc: 40f70533 sub a0,a4,a5 -800094e0: 0ff57593 andi a1,a0,255 -800094e4: 00059463 bnez a1,800094ec -800094e8: 00008067 ret -800094ec: 0ff77713 andi a4,a4,255 -800094f0: 0ff7f793 andi a5,a5,255 -800094f4: 40f70533 sub a0,a4,a5 -800094f8: 00008067 ret -800094fc: 00054603 lbu a2,0(a0) -80009500: 0005c683 lbu a3,0(a1) -80009504: 00150513 addi a0,a0,1 -80009508: 00158593 addi a1,a1,1 -8000950c: 00d61463 bne a2,a3,80009514 -80009510: fe0616e3 bnez a2,800094fc -80009514: 40d60533 sub a0,a2,a3 -80009518: 00008067 ret -8000951c: 00450513 addi a0,a0,4 -80009520: 00458593 addi a1,a1,4 -80009524: fcd61ce3 bne a2,a3,800094fc -80009528: 00000513 li a0,0 -8000952c: 00008067 ret -80009530: 00850513 addi a0,a0,8 -80009534: 00858593 addi a1,a1,8 -80009538: fcd612e3 bne a2,a3,800094fc -8000953c: 00000513 li a0,0 -80009540: 00008067 ret -80009544: 00c50513 addi a0,a0,12 -80009548: 00c58593 addi a1,a1,12 -8000954c: fad618e3 bne a2,a3,800094fc -80009550: 00000513 li a0,0 -80009554: 00008067 ret -80009558: 01050513 addi a0,a0,16 -8000955c: 01058593 addi a1,a1,16 -80009560: f8d61ee3 bne a2,a3,800094fc -80009564: 00000513 li a0,0 -80009568: 00008067 ret - -8000956c : -8000956c: 00b567b3 or a5,a0,a1 -80009570: 0037f793 andi a5,a5,3 -80009574: 08079263 bnez a5,800095f8 -80009578: 0005a703 lw a4,0(a1) -8000957c: 7f7f86b7 lui a3,0x7f7f8 -80009580: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> -80009584: 00d777b3 and a5,a4,a3 -80009588: 00d787b3 add a5,a5,a3 -8000958c: 00e7e7b3 or a5,a5,a4 -80009590: 00d7e7b3 or a5,a5,a3 -80009594: fff00613 li a2,-1 -80009598: 06c79e63 bne a5,a2,80009614 -8000959c: 00050613 mv a2,a0 -800095a0: fff00813 li a6,-1 -800095a4: 00460613 addi a2,a2,4 # 7ff00004 <_start-0xffffc> -800095a8: 00458593 addi a1,a1,4 -800095ac: fee62e23 sw a4,-4(a2) -800095b0: 0005a703 lw a4,0(a1) -800095b4: 00d777b3 and a5,a4,a3 -800095b8: 00d787b3 add a5,a5,a3 -800095bc: 00e7e7b3 or a5,a5,a4 -800095c0: 00d7e7b3 or a5,a5,a3 -800095c4: ff0780e3 beq a5,a6,800095a4 -800095c8: 0005c783 lbu a5,0(a1) -800095cc: 0015c703 lbu a4,1(a1) -800095d0: 0025c683 lbu a3,2(a1) -800095d4: 00f60023 sb a5,0(a2) -800095d8: 00078a63 beqz a5,800095ec -800095dc: 00e600a3 sb a4,1(a2) -800095e0: 00070663 beqz a4,800095ec -800095e4: 00d60123 sb a3,2(a2) -800095e8: 00069463 bnez a3,800095f0 -800095ec: 00008067 ret -800095f0: 000601a3 sb zero,3(a2) -800095f4: 00008067 ret -800095f8: 00050793 mv a5,a0 -800095fc: 0005c703 lbu a4,0(a1) -80009600: 00178793 addi a5,a5,1 -80009604: 00158593 addi a1,a1,1 -80009608: fee78fa3 sb a4,-1(a5) -8000960c: fe0718e3 bnez a4,800095fc -80009610: 00008067 ret -80009614: 00050613 mv a2,a0 -80009618: fb1ff06f j 800095c8 - -8000961c : -8000961c: 00357793 andi a5,a0,3 -80009620: 00050713 mv a4,a0 -80009624: 04079c63 bnez a5,8000967c -80009628: 7f7f86b7 lui a3,0x7f7f8 -8000962c: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> -80009630: fff00593 li a1,-1 -80009634: 00470713 addi a4,a4,4 -80009638: ffc72603 lw a2,-4(a4) -8000963c: 00d677b3 and a5,a2,a3 -80009640: 00d787b3 add a5,a5,a3 -80009644: 00c7e7b3 or a5,a5,a2 -80009648: 00d7e7b3 or a5,a5,a3 -8000964c: feb784e3 beq a5,a1,80009634 -80009650: ffc74683 lbu a3,-4(a4) -80009654: 40a707b3 sub a5,a4,a0 -80009658: ffd74603 lbu a2,-3(a4) -8000965c: ffe74503 lbu a0,-2(a4) -80009660: 04068063 beqz a3,800096a0 -80009664: 02060a63 beqz a2,80009698 -80009668: 00a03533 snez a0,a0 -8000966c: 00f50533 add a0,a0,a5 -80009670: ffe50513 addi a0,a0,-2 -80009674: 00008067 ret -80009678: fa0688e3 beqz a3,80009628 -8000967c: 00074783 lbu a5,0(a4) -80009680: 00170713 addi a4,a4,1 -80009684: 00377693 andi a3,a4,3 -80009688: fe0798e3 bnez a5,80009678 -8000968c: 40a70733 sub a4,a4,a0 -80009690: fff70513 addi a0,a4,-1 -80009694: 00008067 ret -80009698: ffd78513 addi a0,a5,-3 -8000969c: 00008067 ret -800096a0: ffc78513 addi a0,a5,-4 -800096a4: 00008067 ret - -800096a8 : -800096a8: 00a5e7b3 or a5,a1,a0 -800096ac: 0037f793 andi a5,a5,3 -800096b0: 06079a63 bnez a5,80009724 -800096b4: 00300793 li a5,3 -800096b8: 00050713 mv a4,a0 -800096bc: 06c7e863 bltu a5,a2,8000972c -800096c0: 06060063 beqz a2,80009720 -800096c4: 0005c803 lbu a6,0(a1) -800096c8: fff60693 addi a3,a2,-1 -800096cc: 00158593 addi a1,a1,1 -800096d0: 01070023 sb a6,0(a4) -800096d4: 00170793 addi a5,a4,1 -800096d8: 02080863 beqz a6,80009708 -800096dc: 00c70633 add a2,a4,a2 -800096e0: 00d706b3 add a3,a4,a3 -800096e4: 0140006f j 800096f8 -800096e8: fff5c703 lbu a4,-1(a1) -800096ec: 00178793 addi a5,a5,1 -800096f0: fee78fa3 sb a4,-1(a5) -800096f4: 00070c63 beqz a4,8000970c -800096f8: 00158593 addi a1,a1,1 -800096fc: 40f68833 sub a6,a3,a5 -80009700: fec794e3 bne a5,a2,800096e8 -80009704: 00008067 ret -80009708: 00068813 mv a6,a3 -8000970c: 01078733 add a4,a5,a6 -80009710: 06080063 beqz a6,80009770 -80009714: 00178793 addi a5,a5,1 -80009718: fe078fa3 sb zero,-1(a5) -8000971c: fee79ce3 bne a5,a4,80009714 -80009720: 00008067 ret -80009724: 00050713 mv a4,a0 -80009728: f99ff06f j 800096c0 -8000972c: feff0337 lui t1,0xfeff0 -80009730: 808088b7 lui a7,0x80808 -80009734: eff30313 addi t1,t1,-257 # fefefeff <__BSS_END__+0x7efd9187> -80009738: 08088893 addi a7,a7,128 # 80808080 <__BSS_END__+0x7f1308> -8000973c: 00300e13 li t3,3 -80009740: 0005a683 lw a3,0(a1) -80009744: 006687b3 add a5,a3,t1 -80009748: fff6c813 not a6,a3 -8000974c: 0107f7b3 and a5,a5,a6 -80009750: 0117f7b3 and a5,a5,a7 -80009754: f60798e3 bnez a5,800096c4 -80009758: 00470713 addi a4,a4,4 -8000975c: ffc60613 addi a2,a2,-4 -80009760: fed72e23 sw a3,-4(a4) -80009764: 00458593 addi a1,a1,4 -80009768: fcce6ce3 bltu t3,a2,80009740 -8000976c: f55ff06f j 800096c0 -80009770: 00008067 ret - -80009774 <_svfprintf_r>: -80009774: e1010113 addi sp,sp,-496 -80009778: 1e112623 sw ra,492(sp) -8000977c: 1e812423 sw s0,488(sp) -80009780: 1d712623 sw s7,460(sp) -80009784: 00058413 mv s0,a1 -80009788: 00b12423 sw a1,8(sp) -8000978c: 00060b93 mv s7,a2 -80009790: 00d12a23 sw a3,20(sp) -80009794: 1e912223 sw s1,484(sp) -80009798: 1f212023 sw s2,480(sp) -8000979c: 1d312e23 sw s3,476(sp) -800097a0: 1d412c23 sw s4,472(sp) -800097a4: 1d512a23 sw s5,468(sp) -800097a8: 1d612823 sw s6,464(sp) -800097ac: 1d812423 sw s8,456(sp) -800097b0: 1d912223 sw s9,452(sp) -800097b4: 1da12023 sw s10,448(sp) -800097b8: 1bb12e23 sw s11,444(sp) -800097bc: 02a12423 sw a0,40(sp) -800097c0: d68fe0ef jal ra,80007d28 <_localeconv_r> -800097c4: 00052783 lw a5,0(a0) -800097c8: 00078513 mv a0,a5 -800097cc: 02f12a23 sw a5,52(sp) -800097d0: e4dff0ef jal ra,8000961c -800097d4: 00c45783 lhu a5,12(s0) -800097d8: 02a12623 sw a0,44(sp) -800097dc: 0e012823 sw zero,240(sp) -800097e0: 0e012a23 sw zero,244(sp) -800097e4: 0e012c23 sw zero,248(sp) -800097e8: 0e012e23 sw zero,252(sp) -800097ec: 0807f793 andi a5,a5,128 -800097f0: 00078863 beqz a5,80009800 <_svfprintf_r+0x8c> -800097f4: 01042783 lw a5,16(s0) -800097f8: 00079463 bnez a5,80009800 <_svfprintf_r+0x8c> -800097fc: 7000106f j 8000aefc <_svfprintf_r+0x1788> -80009800: 10c10793 addi a5,sp,268 -80009804: 000b8c93 mv s9,s7 -80009808: 00078893 mv a7,a5 -8000980c: 0ef12223 sw a5,228(sp) -80009810: 000cc703 lbu a4,0(s9) -80009814: 800157b7 lui a5,0x80015 -80009818: bc878793 addi a5,a5,-1080 # 80014bc8 <__BSS_END__+0xffffde50> -8000981c: 00f12623 sw a5,12(sp) -80009820: 0e012623 sw zero,236(sp) -80009824: 800157b7 lui a5,0x80015 -80009828: 0e012423 sw zero,232(sp) -8000982c: 00012e23 sw zero,28(sp) -80009830: 02012823 sw zero,48(sp) -80009834: 02012c23 sw zero,56(sp) -80009838: 04012023 sw zero,64(sp) -8000983c: 04012423 sw zero,72(sp) -80009840: 02012e23 sw zero,60(sp) -80009844: 00012223 sw zero,4(sp) -80009848: d4478c13 addi s8,a5,-700 # 80014d44 <__BSS_END__+0xffffdfcc> -8000984c: 00088d13 mv s10,a7 -80009850: 02812a03 lw s4,40(sp) -80009854: 38070e63 beqz a4,80009bf0 <_svfprintf_r+0x47c> -80009858: 02500693 li a3,37 -8000985c: 00d71463 bne a4,a3,80009864 <_svfprintf_r+0xf0> -80009860: 5400106f j 8000ada0 <_svfprintf_r+0x162c> -80009864: 000c8413 mv s0,s9 -80009868: 00c0006f j 80009874 <_svfprintf_r+0x100> -8000986c: 0ed78a63 beq a5,a3,80009960 <_svfprintf_r+0x1ec> -80009870: 00090413 mv s0,s2 -80009874: 00144783 lbu a5,1(s0) -80009878: 00140913 addi s2,s0,1 -8000987c: fe0798e3 bnez a5,8000986c <_svfprintf_r+0xf8> -80009880: 419904b3 sub s1,s2,s9 -80009884: 36048663 beqz s1,80009bf0 <_svfprintf_r+0x47c> -80009888: 0ec12683 lw a3,236(sp) -8000988c: 0e812703 lw a4,232(sp) -80009890: 019d2023 sw s9,0(s10) -80009894: 009686b3 add a3,a3,s1 -80009898: 00170713 addi a4,a4,1 -8000989c: 009d2223 sw s1,4(s10) -800098a0: 0ed12623 sw a3,236(sp) -800098a4: 0ee12423 sw a4,232(sp) -800098a8: 00700693 li a3,7 -800098ac: 008d0d13 addi s10,s10,8 -800098b0: 0ae6ce63 blt a3,a4,8000996c <_svfprintf_r+0x1f8> -800098b4: 00412783 lw a5,4(sp) -800098b8: 00144703 lbu a4,1(s0) -800098bc: 009787b3 add a5,a5,s1 -800098c0: 00f12223 sw a5,4(sp) -800098c4: 32070663 beqz a4,80009bf0 <_svfprintf_r+0x47c> -800098c8: fff00313 li t1,-1 -800098cc: 00190493 addi s1,s2,1 -800098d0: 00194e03 lbu t3,1(s2) -800098d4: 0c0103a3 sb zero,199(sp) -800098d8: 00000413 li s0,0 -800098dc: 00000913 li s2,0 -800098e0: 05a00993 li s3,90 -800098e4: 00900b13 li s6,9 -800098e8: 02a00b93 li s7,42 -800098ec: 00030d93 mv s11,t1 -800098f0: 00148493 addi s1,s1,1 -800098f4: 000e0a93 mv s5,t3 -800098f8: fe0a8793 addi a5,s5,-32 -800098fc: 1ef9e263 bltu s3,a5,80009ae0 <_svfprintf_r+0x36c> -80009900: 00c12703 lw a4,12(sp) -80009904: 00279793 slli a5,a5,0x2 -80009908: 00e787b3 add a5,a5,a4 -8000990c: 0007a783 lw a5,0(a5) -80009910: 00078067 jr a5 -80009914: 000a0513 mv a0,s4 -80009918: c10fe0ef jal ra,80007d28 <_localeconv_r> -8000991c: 00452783 lw a5,4(a0) -80009920: 00078513 mv a0,a5 -80009924: 02f12e23 sw a5,60(sp) -80009928: cf5ff0ef jal ra,8000961c -8000992c: 04a12423 sw a0,72(sp) -80009930: 00050a93 mv s5,a0 -80009934: 000a0513 mv a0,s4 -80009938: bf0fe0ef jal ra,80007d28 <_localeconv_r> -8000993c: 00852783 lw a5,8(a0) -80009940: 04f12023 sw a5,64(sp) -80009944: 000a8463 beqz s5,8000994c <_svfprintf_r+0x1d8> -80009948: 5400106f j 8000ae88 <_svfprintf_r+0x1714> -8000994c: 0004ce03 lbu t3,0(s1) -80009950: fa1ff06f j 800098f0 <_svfprintf_r+0x17c> -80009954: 02096913 ori s2,s2,32 -80009958: 0004ce03 lbu t3,0(s1) -8000995c: f95ff06f j 800098f0 <_svfprintf_r+0x17c> -80009960: 419904b3 sub s1,s2,s9 -80009964: f60482e3 beqz s1,800098c8 <_svfprintf_r+0x154> -80009968: f21ff06f j 80009888 <_svfprintf_r+0x114> -8000996c: 00812583 lw a1,8(sp) -80009970: 0e410613 addi a2,sp,228 -80009974: 000a0513 mv a0,s4 -80009978: 080050ef jal ra,8000e9f8 <__ssprint_r> -8000997c: 02051a63 bnez a0,800099b0 <_svfprintf_r+0x23c> -80009980: 10c10d13 addi s10,sp,268 -80009984: f31ff06f j 800098b4 <_svfprintf_r+0x140> -80009988: 00812583 lw a1,8(sp) -8000998c: 0e410613 addi a2,sp,228 -80009990: 000a0513 mv a0,s4 -80009994: 064050ef jal ra,8000e9f8 <__ssprint_r> -80009998: 040504e3 beqz a0,8000a1e0 <_svfprintf_r+0xa6c> -8000999c: 01012783 lw a5,16(sp) -800099a0: 00078863 beqz a5,800099b0 <_svfprintf_r+0x23c> -800099a4: 01012583 lw a1,16(sp) -800099a8: 02812503 lw a0,40(sp) -800099ac: b7cfb0ef jal ra,80004d28 <_free_r> -800099b0: 00812783 lw a5,8(sp) -800099b4: 00c7d783 lhu a5,12(a5) -800099b8: 0407f793 andi a5,a5,64 -800099bc: 00078463 beqz a5,800099c4 <_svfprintf_r+0x250> -800099c0: 5e80206f j 8000bfa8 <_svfprintf_r+0x2834> -800099c4: 1ec12083 lw ra,492(sp) -800099c8: 1e812403 lw s0,488(sp) -800099cc: 00412503 lw a0,4(sp) -800099d0: 1e412483 lw s1,484(sp) -800099d4: 1e012903 lw s2,480(sp) -800099d8: 1dc12983 lw s3,476(sp) -800099dc: 1d812a03 lw s4,472(sp) -800099e0: 1d412a83 lw s5,468(sp) -800099e4: 1d012b03 lw s6,464(sp) -800099e8: 1cc12b83 lw s7,460(sp) -800099ec: 1c812c03 lw s8,456(sp) -800099f0: 1c412c83 lw s9,452(sp) -800099f4: 1c012d03 lw s10,448(sp) -800099f8: 1bc12d83 lw s11,444(sp) -800099fc: 1f010113 addi sp,sp,496 -80009a00: 00008067 ret -80009a04: 800147b7 lui a5,0x80014 -80009a08: 7e078793 addi a5,a5,2016 # 800147e0 <__BSS_END__+0xffffda68> -80009a0c: 02f12823 sw a5,48(sp) -80009a10: 02097793 andi a5,s2,32 -80009a14: 000d8313 mv t1,s11 -80009a18: 0e078e63 beqz a5,80009b14 <_svfprintf_r+0x3a0> -80009a1c: 01412783 lw a5,20(sp) -80009a20: 00778793 addi a5,a5,7 -80009a24: ff87f793 andi a5,a5,-8 -80009a28: 0007ab83 lw s7,0(a5) -80009a2c: 0047ad83 lw s11,4(a5) -80009a30: 00878713 addi a4,a5,8 -80009a34: 00e12a23 sw a4,20(sp) -80009a38: 00197793 andi a5,s2,1 -80009a3c: 00078863 beqz a5,80009a4c <_svfprintf_r+0x2d8> -80009a40: 01bbe7b3 or a5,s7,s11 -80009a44: 00078463 beqz a5,80009a4c <_svfprintf_r+0x2d8> -80009a48: 4240106f j 8000ae6c <_svfprintf_r+0x16f8> -80009a4c: bff97993 andi s3,s2,-1025 -80009a50: 00200793 li a5,2 -80009a54: 0c0103a3 sb zero,199(sp) -80009a58: fff00713 li a4,-1 -80009a5c: 0ee30ce3 beq t1,a4,8000a354 <_svfprintf_r+0xbe0> -80009a60: 01bbe733 or a4,s7,s11 -80009a64: f7f9f913 andi s2,s3,-129 -80009a68: 7a071ce3 bnez a4,8000aa20 <_svfprintf_r+0x12ac> -80009a6c: 2e0316e3 bnez t1,8000a558 <_svfprintf_r+0xde4> -80009a70: 62079a63 bnez a5,8000a0a4 <_svfprintf_r+0x930> -80009a74: 0019fb13 andi s6,s3,1 -80009a78: 1b010c93 addi s9,sp,432 -80009a7c: 000b0463 beqz s6,80009a84 <_svfprintf_r+0x310> -80009a80: 3780106f j 8000adf8 <_svfprintf_r+0x1684> -80009a84: 000b0993 mv s3,s6 -80009a88: 006b5463 bge s6,t1,80009a90 <_svfprintf_r+0x31c> -80009a8c: 00030993 mv s3,t1 -80009a90: 0c714703 lbu a4,199(sp) -80009a94: 00012823 sw zero,16(sp) -80009a98: 02012223 sw zero,36(sp) -80009a9c: 02012023 sw zero,32(sp) -80009aa0: 00012c23 sw zero,24(sp) -80009aa4: 64070463 beqz a4,8000a0ec <_svfprintf_r+0x978> -80009aa8: 00198993 addi s3,s3,1 -80009aac: 6400006f j 8000a0ec <_svfprintf_r+0x978> -80009ab0: 00000413 li s0,0 -80009ab4: fd0a8713 addi a4,s5,-48 -80009ab8: 00148493 addi s1,s1,1 -80009abc: 00241793 slli a5,s0,0x2 -80009ac0: fff4ca83 lbu s5,-1(s1) -80009ac4: 008787b3 add a5,a5,s0 -80009ac8: 00179793 slli a5,a5,0x1 -80009acc: 00f70433 add s0,a4,a5 -80009ad0: fd0a8713 addi a4,s5,-48 -80009ad4: feeb72e3 bgeu s6,a4,80009ab8 <_svfprintf_r+0x344> -80009ad8: fe0a8793 addi a5,s5,-32 -80009adc: e2f9f2e3 bgeu s3,a5,80009900 <_svfprintf_r+0x18c> -80009ae0: 100a8863 beqz s5,80009bf0 <_svfprintf_r+0x47c> -80009ae4: 15510623 sb s5,332(sp) -80009ae8: 0c0103a3 sb zero,199(sp) -80009aec: 00100993 li s3,1 -80009af0: 00100b13 li s6,1 -80009af4: 14c10c93 addi s9,sp,332 -80009af8: 5e00006f j 8000a0d8 <_svfprintf_r+0x964> -80009afc: 800147b7 lui a5,0x80014 -80009b00: 7f478793 addi a5,a5,2036 # 800147f4 <__BSS_END__+0xffffda7c> -80009b04: 02f12823 sw a5,48(sp) -80009b08: 02097793 andi a5,s2,32 -80009b0c: 000d8313 mv t1,s11 -80009b10: f00796e3 bnez a5,80009a1c <_svfprintf_r+0x2a8> -80009b14: 01412703 lw a4,20(sp) -80009b18: 01097793 andi a5,s2,16 -80009b1c: 00072b83 lw s7,0(a4) -80009b20: 00470713 addi a4,a4,4 -80009b24: 00e12a23 sw a4,20(sp) -80009b28: 00078463 beqz a5,80009b30 <_svfprintf_r+0x3bc> -80009b2c: 2e40106f j 8000ae10 <_svfprintf_r+0x169c> -80009b30: 04097793 andi a5,s2,64 -80009b34: 00079463 bnez a5,80009b3c <_svfprintf_r+0x3c8> -80009b38: 2d00106f j 8000ae08 <_svfprintf_r+0x1694> -80009b3c: 010b9b93 slli s7,s7,0x10 -80009b40: 010bdb93 srli s7,s7,0x10 -80009b44: 00000d93 li s11,0 -80009b48: ef1ff06f j 80009a38 <_svfprintf_r+0x2c4> -80009b4c: 0004ce03 lbu t3,0(s1) -80009b50: 00496913 ori s2,s2,4 -80009b54: d9dff06f j 800098f0 <_svfprintf_r+0x17c> -80009b58: 02097793 andi a5,s2,32 -80009b5c: 000d8313 mv t1,s11 -80009b60: 14079ce3 bnez a5,8000a4b8 <_svfprintf_r+0xd44> -80009b64: 01412683 lw a3,20(sp) -80009b68: 01097713 andi a4,s2,16 -80009b6c: 00468793 addi a5,a3,4 -80009b70: 0006ab83 lw s7,0(a3) -80009b74: 4c071263 bnez a4,8000a038 <_svfprintf_r+0x8c4> -80009b78: 04097713 andi a4,s2,64 -80009b7c: 00071463 bnez a4,80009b84 <_svfprintf_r+0x410> -80009b80: 1c10106f j 8000b540 <_svfprintf_r+0x1dcc> -80009b84: 010b9b93 slli s7,s7,0x10 -80009b88: 010bdb93 srli s7,s7,0x10 -80009b8c: 00000d93 li s11,0 -80009b90: 00f12a23 sw a5,20(sp) -80009b94: 1410006f j 8000a4d4 <_svfprintf_r+0xd60> -80009b98: 01412683 lw a3,20(sp) -80009b9c: 02097793 andi a5,s2,32 -80009ba0: 00468713 addi a4,a3,4 -80009ba4: 00078463 beqz a5,80009bac <_svfprintf_r+0x438> -80009ba8: 2a40106f j 8000ae4c <_svfprintf_r+0x16d8> -80009bac: 01097793 andi a5,s2,16 -80009bb0: 00078463 beqz a5,80009bb8 <_svfprintf_r+0x444> -80009bb4: 0410106f j 8000b3f4 <_svfprintf_r+0x1c80> -80009bb8: 04097793 andi a5,s2,64 -80009bbc: 00078463 beqz a5,80009bc4 <_svfprintf_r+0x450> -80009bc0: 25d0106f j 8000b61c <_svfprintf_r+0x1ea8> -80009bc4: 20097913 andi s2,s2,512 -80009bc8: 00091463 bnez s2,80009bd0 <_svfprintf_r+0x45c> -80009bcc: 0290106f j 8000b3f4 <_svfprintf_r+0x1c80> -80009bd0: 01412783 lw a5,20(sp) -80009bd4: 00e12a23 sw a4,20(sp) -80009bd8: 00412703 lw a4,4(sp) -80009bdc: 0007a783 lw a5,0(a5) -80009be0: 00048c93 mv s9,s1 -80009be4: 00e78023 sb a4,0(a5) -80009be8: 000cc703 lbu a4,0(s9) -80009bec: c60716e3 bnez a4,80009858 <_svfprintf_r+0xe4> -80009bf0: 0ec12783 lw a5,236(sp) -80009bf4: da078ee3 beqz a5,800099b0 <_svfprintf_r+0x23c> -80009bf8: 00812403 lw s0,8(sp) -80009bfc: 02812503 lw a0,40(sp) -80009c00: 0e410613 addi a2,sp,228 -80009c04: 00040593 mv a1,s0 -80009c08: 5f1040ef jal ra,8000e9f8 <__ssprint_r> -80009c0c: 00c45783 lhu a5,12(s0) -80009c10: da9ff06f j 800099b8 <_svfprintf_r+0x244> -80009c14: 0004ce03 lbu t3,0(s1) -80009c18: 06c00793 li a5,108 -80009c1c: 00fe1463 bne t3,a5,80009c24 <_svfprintf_r+0x4b0> -80009c20: 2bc0106f j 8000aedc <_svfprintf_r+0x1768> -80009c24: 01096913 ori s2,s2,16 -80009c28: cc9ff06f j 800098f0 <_svfprintf_r+0x17c> -80009c2c: 0004ce03 lbu t3,0(s1) -80009c30: 06800793 li a5,104 -80009c34: 00fe1463 bne t3,a5,80009c3c <_svfprintf_r+0x4c8> -80009c38: 2b40106f j 8000aeec <_svfprintf_r+0x1778> -80009c3c: 04096913 ori s2,s2,64 -80009c40: cb1ff06f j 800098f0 <_svfprintf_r+0x17c> -80009c44: 01412703 lw a4,20(sp) -80009c48: ffff87b7 lui a5,0xffff8 -80009c4c: 8307c793 xori a5,a5,-2000 -80009c50: 0cf11423 sh a5,200(sp) -80009c54: 00470793 addi a5,a4,4 -80009c58: 00f12a23 sw a5,20(sp) -80009c5c: 800147b7 lui a5,0x80014 -80009c60: 7e078793 addi a5,a5,2016 # 800147e0 <__BSS_END__+0xffffda68> -80009c64: 000d8313 mv t1,s11 -80009c68: 02f12823 sw a5,48(sp) -80009c6c: 00072b83 lw s7,0(a4) -80009c70: 00000d93 li s11,0 -80009c74: 00296993 ori s3,s2,2 -80009c78: 00200793 li a5,2 -80009c7c: 07800a93 li s5,120 -80009c80: dd5ff06f j 80009a54 <_svfprintf_r+0x2e0> -80009c84: 00897713 andi a4,s2,8 -80009c88: 000d8313 mv t1,s11 -80009c8c: 00070463 beqz a4,80009c94 <_svfprintf_r+0x520> -80009c90: 1880106f j 8000ae18 <_svfprintf_r+0x16a4> -80009c94: 01412783 lw a5,20(sp) -80009c98: 0b010513 addi a0,sp,176 -80009c9c: 01b12823 sw s11,16(sp) -80009ca0: 00778793 addi a5,a5,7 -80009ca4: ff87f793 andi a5,a5,-8 -80009ca8: 0007a583 lw a1,0(a5) -80009cac: 0047a603 lw a2,4(a5) -80009cb0: 00878793 addi a5,a5,8 -80009cb4: 00f12a23 sw a5,20(sp) -80009cb8: 3040a0ef jal ra,80013fbc <__extenddftf2> -80009cbc: 0b012703 lw a4,176(sp) -80009cc0: 01012303 lw t1,16(sp) -80009cc4: 0ee12823 sw a4,240(sp) -80009cc8: 0b412703 lw a4,180(sp) -80009ccc: 0ee12a23 sw a4,244(sp) -80009cd0: 0b812703 lw a4,184(sp) -80009cd4: 0ee12c23 sw a4,248(sp) -80009cd8: 0bc12703 lw a4,188(sp) -80009cdc: 0ee12e23 sw a4,252(sp) -80009ce0: 0f010513 addi a0,sp,240 -80009ce4: 00612823 sw t1,16(sp) -80009ce8: fd5fd0ef jal ra,80007cbc <_ldcheck> -80009cec: 0ca12623 sw a0,204(sp) -80009cf0: 00200713 li a4,2 -80009cf4: 01012303 lw t1,16(sp) -80009cf8: 00e51463 bne a0,a4,80009d00 <_svfprintf_r+0x58c> -80009cfc: 6780106f j 8000b374 <_svfprintf_r+0x1c00> -80009d00: 00100713 li a4,1 -80009d04: 00e51463 bne a0,a4,80009d0c <_svfprintf_r+0x598> -80009d08: 0510106f j 8000b558 <_svfprintf_r+0x1de4> -80009d0c: 06100713 li a4,97 -80009d10: 00ea9463 bne s5,a4,80009d18 <_svfprintf_r+0x5a4> -80009d14: 2840206f j 8000bf98 <_svfprintf_r+0x2824> -80009d18: 04100713 li a4,65 -80009d1c: 00ea9463 bne s5,a4,80009d24 <_svfprintf_r+0x5b0> -80009d20: 5350106f j 8000ba54 <_svfprintf_r+0x22e0> -80009d24: fdfaf793 andi a5,s5,-33 -80009d28: fff00713 li a4,-1 -80009d2c: 04f12623 sw a5,76(sp) -80009d30: 00e31463 bne t1,a4,80009d38 <_svfprintf_r+0x5c4> -80009d34: 1850106f j 8000b6b8 <_svfprintf_r+0x1f44> -80009d38: 04700713 li a4,71 -80009d3c: 00e79463 bne a5,a4,80009d44 <_svfprintf_r+0x5d0> -80009d40: 2740206f j 8000bfb4 <_svfprintf_r+0x2840> -80009d44: 0fc12e83 lw t4,252(sp) -80009d48: 05212c23 sw s2,88(sp) -80009d4c: 10096713 ori a4,s2,256 -80009d50: 0f012283 lw t0,240(sp) -80009d54: 0f412f03 lw t5,244(sp) -80009d58: 0f812f83 lw t6,248(sp) -80009d5c: 000ed463 bgez t4,80009d64 <_svfprintf_r+0x5f0> -80009d60: 0c40206f j 8000be24 <_svfprintf_r+0x26b0> -80009d64: 04012e23 sw zero,92(sp) -80009d68: 00070913 mv s2,a4 -80009d6c: 00012823 sw zero,16(sp) -80009d70: 04c12703 lw a4,76(sp) -80009d74: 04600793 li a5,70 -80009d78: 00f71463 bne a4,a5,80009d80 <_svfprintf_r+0x60c> -80009d7c: 2b50106f j 8000b830 <_svfprintf_r+0x20bc> -80009d80: 04500793 li a5,69 -80009d84: 00f71463 bne a4,a5,80009d8c <_svfprintf_r+0x618> -80009d88: 1240206f j 8000beac <_svfprintf_r+0x2738> -80009d8c: 0b010993 addi s3,sp,176 -80009d90: 0d010793 addi a5,sp,208 -80009d94: 0cc10713 addi a4,sp,204 -80009d98: 00030693 mv a3,t1 -80009d9c: 0dc10813 addi a6,sp,220 -80009da0: 00200613 li a2,2 -80009da4: 00098593 mv a1,s3 -80009da8: 000a0513 mv a0,s4 -80009dac: 04612223 sw t1,68(sp) -80009db0: 0a512823 sw t0,176(sp) -80009db4: 02512223 sw t0,36(sp) -80009db8: 0be12a23 sw t5,180(sp) -80009dbc: 03e12023 sw t5,32(sp) -80009dc0: 0bf12c23 sw t6,184(sp) -80009dc4: 01f12e23 sw t6,28(sp) -80009dc8: 0bd12e23 sw t4,188(sp) -80009dcc: 01d12c23 sw t4,24(sp) -80009dd0: bd9fc0ef jal ra,800069a8 <_ldtoa_r> -80009dd4: 04c12783 lw a5,76(sp) -80009dd8: 04700713 li a4,71 -80009ddc: 00050c93 mv s9,a0 -80009de0: 01812e83 lw t4,24(sp) -80009de4: 01c12f83 lw t6,28(sp) -80009de8: 02012f03 lw t5,32(sp) -80009dec: 02412283 lw t0,36(sp) -80009df0: 04412303 lw t1,68(sp) -80009df4: 00e78463 beq a5,a4,80009dfc <_svfprintf_r+0x688> -80009df8: 4380206f j 8000c230 <_svfprintf_r+0x2abc> -80009dfc: 05812783 lw a5,88(sp) -80009e00: 0017f713 andi a4,a5,1 -80009e04: 00070463 beqz a4,80009e0c <_svfprintf_r+0x698> -80009e08: 1840206f j 8000bf8c <_svfprintf_r+0x2818> -80009e0c: 0dc12703 lw a4,220(sp) -80009e10: 419707b3 sub a5,a4,s9 -80009e14: 00f12e23 sw a5,28(sp) -80009e18: 0cc12783 lw a5,204(sp) -80009e1c: 04700713 li a4,71 -80009e20: 00f12c23 sw a5,24(sp) -80009e24: 04c12783 lw a5,76(sp) -80009e28: 00e79463 bne a5,a4,80009e30 <_svfprintf_r+0x6bc> -80009e2c: 0cd0106f j 8000b6f8 <_svfprintf_r+0x1f84> -80009e30: 04c12783 lw a5,76(sp) -80009e34: 04600713 li a4,70 -80009e38: 00e79463 bne a5,a4,80009e40 <_svfprintf_r+0x6cc> -80009e3c: 3710106f j 8000b9ac <_svfprintf_r+0x2238> -80009e40: 01812783 lw a5,24(sp) -80009e44: 04100593 li a1,65 -80009e48: 0ffaf693 andi a3,s5,255 -80009e4c: fff78713 addi a4,a5,-1 -80009e50: 04c12783 lw a5,76(sp) -80009e54: 0ce12623 sw a4,204(sp) -80009e58: 00000613 li a2,0 -80009e5c: 00b79863 bne a5,a1,80009e6c <_svfprintf_r+0x6f8> -80009e60: 00f68693 addi a3,a3,15 -80009e64: 0ff6f693 andi a3,a3,255 -80009e68: 00100613 li a2,1 -80009e6c: 0cd10a23 sb a3,212(sp) -80009e70: 00075463 bgez a4,80009e78 <_svfprintf_r+0x704> -80009e74: 3240206f j 8000c198 <_svfprintf_r+0x2a24> -80009e78: 02b00693 li a3,43 -80009e7c: 0cd10aa3 sb a3,213(sp) -80009e80: 00900693 li a3,9 -80009e84: 00e6c463 blt a3,a4,80009e8c <_svfprintf_r+0x718> -80009e88: 2440206f j 8000c0cc <_svfprintf_r+0x2958> -80009e8c: 0e310813 addi a6,sp,227 -80009e90: 00080613 mv a2,a6 -80009e94: 00a00513 li a0,10 -80009e98: 06300313 li t1,99 -80009e9c: 00c0006f j 80009ea8 <_svfprintf_r+0x734> -80009ea0: 00058613 mv a2,a1 -80009ea4: 00068713 mv a4,a3 -80009ea8: 02a767b3 rem a5,a4,a0 -80009eac: fff60593 addi a1,a2,-1 -80009eb0: 03078793 addi a5,a5,48 -80009eb4: fef60fa3 sb a5,-1(a2) -80009eb8: 02a746b3 div a3,a4,a0 -80009ebc: fee342e3 blt t1,a4,80009ea0 <_svfprintf_r+0x72c> -80009ec0: 03068713 addi a4,a3,48 -80009ec4: 0ff77713 andi a4,a4,255 -80009ec8: ffe60693 addi a3,a2,-2 -80009ecc: fee58fa3 sb a4,-1(a1) -80009ed0: 0106e463 bltu a3,a6,80009ed8 <_svfprintf_r+0x764> -80009ed4: 3500206f j 8000c224 <_svfprintf_r+0x2ab0> -80009ed8: 0d610593 addi a1,sp,214 -80009edc: 0080006f j 80009ee4 <_svfprintf_r+0x770> -80009ee0: 0006c703 lbu a4,0(a3) -80009ee4: 00158593 addi a1,a1,1 -80009ee8: 00168693 addi a3,a3,1 -80009eec: fee58fa3 sb a4,-1(a1) -80009ef0: ff0698e3 bne a3,a6,80009ee0 <_svfprintf_r+0x76c> -80009ef4: 0e510713 addi a4,sp,229 -80009ef8: 0d610793 addi a5,sp,214 -80009efc: 40c70733 sub a4,a4,a2 -80009f00: 00e78733 add a4,a5,a4 -80009f04: 0d410693 addi a3,sp,212 -80009f08: 40d707b3 sub a5,a4,a3 -80009f0c: 02f12c23 sw a5,56(sp) -80009f10: 01c12783 lw a5,28(sp) -80009f14: 03812683 lw a3,56(sp) -80009f18: 00100713 li a4,1 -80009f1c: 00d78b33 add s6,a5,a3 -80009f20: 00f74463 blt a4,a5,80009f28 <_svfprintf_r+0x7b4> -80009f24: 28c0206f j 8000c1b0 <_svfprintf_r+0x2a3c> -80009f28: 02c12783 lw a5,44(sp) -80009f2c: 00fb0b33 add s6,s6,a5 -80009f30: 05812783 lw a5,88(sp) -80009f34: fffb4993 not s3,s6 -80009f38: 41f9d993 srai s3,s3,0x1f -80009f3c: bff7f913 andi s2,a5,-1025 -80009f40: 10096913 ori s2,s2,256 -80009f44: 013b79b3 and s3,s6,s3 -80009f48: 02012223 sw zero,36(sp) -80009f4c: 02012023 sw zero,32(sp) -80009f50: 00012c23 sw zero,24(sp) -80009f54: 05c12783 lw a5,92(sp) -80009f58: 00079463 bnez a5,80009f60 <_svfprintf_r+0x7ec> -80009f5c: 0110106f j 8000b76c <_svfprintf_r+0x1ff8> -80009f60: 02d00713 li a4,45 -80009f64: 0ce103a3 sb a4,199(sp) -80009f68: 00000313 li t1,0 -80009f6c: 00198993 addi s3,s3,1 -80009f70: 17c0006f j 8000a0ec <_svfprintf_r+0x978> -80009f74: 02097793 andi a5,s2,32 -80009f78: 000d8313 mv t1,s11 -80009f7c: 01096993 ori s3,s2,16 -80009f80: 56079263 bnez a5,8000a4e4 <_svfprintf_r+0xd70> -80009f84: 01412783 lw a5,20(sp) -80009f88: 00478793 addi a5,a5,4 -80009f8c: 01412703 lw a4,20(sp) -80009f90: 00000d93 li s11,0 -80009f94: 00f12a23 sw a5,20(sp) -80009f98: 00072b83 lw s7,0(a4) -80009f9c: 00100793 li a5,1 -80009fa0: ab5ff06f j 80009a54 <_svfprintf_r+0x2e0> -80009fa4: 01412783 lw a5,20(sp) -80009fa8: 0c0103a3 sb zero,199(sp) -80009fac: 0007ac83 lw s9,0(a5) -80009fb0: 00478b93 addi s7,a5,4 -80009fb4: 760c8ce3 beqz s9,8000af2c <_svfprintf_r+0x17b8> -80009fb8: fff00713 li a4,-1 -80009fbc: 00ed9463 bne s11,a4,80009fc4 <_svfprintf_r+0x850> -80009fc0: 4500106f j 8000b410 <_svfprintf_r+0x1c9c> -80009fc4: 000d8613 mv a2,s11 -80009fc8: 00000593 li a1,0 -80009fcc: 000c8513 mv a0,s9 -80009fd0: 01b12a23 sw s11,20(sp) -80009fd4: 858fe0ef jal ra,8000802c -80009fd8: 00a12823 sw a0,16(sp) -80009fdc: 01412303 lw t1,20(sp) -80009fe0: 00051463 bnez a0,80009fe8 <_svfprintf_r+0x874> -80009fe4: 19d0106f j 8000b980 <_svfprintf_r+0x220c> -80009fe8: 01012783 lw a5,16(sp) -80009fec: 41978b33 sub s6,a5,s9 -80009ff0: 0c714703 lbu a4,199(sp) -80009ff4: fffb4993 not s3,s6 -80009ff8: 41f9d993 srai s3,s3,0x1f -80009ffc: 01712a23 sw s7,20(sp) -8000a000: 00012823 sw zero,16(sp) -8000a004: 02012223 sw zero,36(sp) -8000a008: 02012023 sw zero,32(sp) -8000a00c: 00012c23 sw zero,24(sp) -8000a010: 013b79b3 and s3,s6,s3 -8000a014: 00000313 li t1,0 -8000a018: a80718e3 bnez a4,80009aa8 <_svfprintf_r+0x334> -8000a01c: 0d00006f j 8000a0ec <_svfprintf_r+0x978> -8000a020: 02097793 andi a5,s2,32 -8000a024: 000d8313 mv t1,s11 -8000a028: 01096913 ori s2,s2,16 -8000a02c: 48079663 bnez a5,8000a4b8 <_svfprintf_r+0xd44> -8000a030: 01412783 lw a5,20(sp) -8000a034: 00478793 addi a5,a5,4 -8000a038: 01412703 lw a4,20(sp) -8000a03c: 00000d93 li s11,0 -8000a040: 00f12a23 sw a5,20(sp) -8000a044: 00072b83 lw s7,0(a4) -8000a048: 48c0006f j 8000a4d4 <_svfprintf_r+0xd60> -8000a04c: 00896913 ori s2,s2,8 -8000a050: 0004ce03 lbu t3,0(s1) -8000a054: 89dff06f j 800098f0 <_svfprintf_r+0x17c> -8000a058: 02097793 andi a5,s2,32 -8000a05c: 000d8313 mv t1,s11 -8000a060: 01096993 ori s3,s2,16 -8000a064: 4a079463 bnez a5,8000a50c <_svfprintf_r+0xd98> -8000a068: 01412783 lw a5,20(sp) -8000a06c: 00478793 addi a5,a5,4 -8000a070: 01412703 lw a4,20(sp) -8000a074: 00f12a23 sw a5,20(sp) -8000a078: 00072b83 lw s7,0(a4) -8000a07c: 41fbdd93 srai s11,s7,0x1f -8000a080: 000d8713 mv a4,s11 -8000a084: 2a074663 bltz a4,8000a330 <_svfprintf_r+0xbbc> -8000a088: fff00793 li a5,-1 -8000a08c: 4af30463 beq t1,a5,8000a534 <_svfprintf_r+0xdc0> -8000a090: 01bbe7b3 or a5,s7,s11 -8000a094: f7f9f913 andi s2,s3,-129 -8000a098: 48079c63 bnez a5,8000a530 <_svfprintf_r+0xdbc> -8000a09c: 00030463 beqz t1,8000a0a4 <_svfprintf_r+0x930> -8000a0a0: 6200106f j 8000b6c0 <_svfprintf_r+0x1f4c> -8000a0a4: 00000313 li t1,0 -8000a0a8: 00000b13 li s6,0 -8000a0ac: 1b010c93 addi s9,sp,432 -8000a0b0: 9d5ff06f j 80009a84 <_svfprintf_r+0x310> -8000a0b4: 01412703 lw a4,20(sp) -8000a0b8: 0c0103a3 sb zero,199(sp) -8000a0bc: 00100993 li s3,1 -8000a0c0: 00072783 lw a5,0(a4) -8000a0c4: 00470713 addi a4,a4,4 -8000a0c8: 00e12a23 sw a4,20(sp) -8000a0cc: 14f10623 sb a5,332(sp) -8000a0d0: 00100b13 li s6,1 -8000a0d4: 14c10c93 addi s9,sp,332 -8000a0d8: 00012823 sw zero,16(sp) -8000a0dc: 00000313 li t1,0 -8000a0e0: 02012223 sw zero,36(sp) -8000a0e4: 02012023 sw zero,32(sp) -8000a0e8: 00012c23 sw zero,24(sp) -8000a0ec: 00297293 andi t0,s2,2 -8000a0f0: 00028463 beqz t0,8000a0f8 <_svfprintf_r+0x984> -8000a0f4: 00298993 addi s3,s3,2 -8000a0f8: 08497b93 andi s7,s2,132 -8000a0fc: 0ec12703 lw a4,236(sp) -8000a100: 000b9663 bnez s7,8000a10c <_svfprintf_r+0x998> -8000a104: 41340833 sub a6,s0,s3 -8000a108: 130040e3 bgtz a6,8000aa28 <_svfprintf_r+0x12b4> -8000a10c: 0c714683 lbu a3,199(sp) -8000a110: 02068a63 beqz a3,8000a144 <_svfprintf_r+0x9d0> -8000a114: 0e812683 lw a3,232(sp) -8000a118: 0c710613 addi a2,sp,199 -8000a11c: 00cd2023 sw a2,0(s10) -8000a120: 00170713 addi a4,a4,1 -8000a124: 00100613 li a2,1 -8000a128: 00168693 addi a3,a3,1 -8000a12c: 00cd2223 sw a2,4(s10) -8000a130: 0ee12623 sw a4,236(sp) -8000a134: 0ed12423 sw a3,232(sp) -8000a138: 00700613 li a2,7 -8000a13c: 008d0d13 addi s10,s10,8 -8000a140: 0cd64263 blt a2,a3,8000a204 <_svfprintf_r+0xa90> -8000a144: 02028a63 beqz t0,8000a178 <_svfprintf_r+0xa04> -8000a148: 0e812683 lw a3,232(sp) -8000a14c: 0c810613 addi a2,sp,200 -8000a150: 00cd2023 sw a2,0(s10) -8000a154: 00270713 addi a4,a4,2 -8000a158: 00200613 li a2,2 -8000a15c: 00168693 addi a3,a3,1 -8000a160: 00cd2223 sw a2,4(s10) -8000a164: 0ee12623 sw a4,236(sp) -8000a168: 0ed12423 sw a3,232(sp) -8000a16c: 00700613 li a2,7 -8000a170: 008d0d13 addi s10,s10,8 -8000a174: 1ed642e3 blt a2,a3,8000ab58 <_svfprintf_r+0x13e4> -8000a178: 08000693 li a3,128 -8000a17c: 58db8063 beq s7,a3,8000a6fc <_svfprintf_r+0xf88> -8000a180: 41630db3 sub s11,t1,s6 -8000a184: 69b04063 bgtz s11,8000a804 <_svfprintf_r+0x1090> -8000a188: 10097693 andi a3,s2,256 -8000a18c: 42069463 bnez a3,8000a5b4 <_svfprintf_r+0xe40> -8000a190: 0e812783 lw a5,232(sp) -8000a194: 01670733 add a4,a4,s6 -8000a198: 019d2023 sw s9,0(s10) -8000a19c: 00178793 addi a5,a5,1 -8000a1a0: 016d2223 sw s6,4(s10) -8000a1a4: 0ee12623 sw a4,236(sp) -8000a1a8: 0ef12423 sw a5,232(sp) -8000a1ac: 00700693 li a3,7 -8000a1b0: 008d0d13 addi s10,s10,8 -8000a1b4: 04f6c4e3 blt a3,a5,8000a9fc <_svfprintf_r+0x1288> -8000a1b8: 00497913 andi s2,s2,4 -8000a1bc: 00090663 beqz s2,8000a1c8 <_svfprintf_r+0xa54> -8000a1c0: 41340933 sub s2,s0,s3 -8000a1c4: 07204863 bgtz s2,8000a234 <_svfprintf_r+0xac0> -8000a1c8: 01345463 bge s0,s3,8000a1d0 <_svfprintf_r+0xa5c> -8000a1cc: 00098413 mv s0,s3 -8000a1d0: 00412783 lw a5,4(sp) -8000a1d4: 008787b3 add a5,a5,s0 -8000a1d8: 00f12223 sw a5,4(sp) -8000a1dc: fa071663 bnez a4,80009988 <_svfprintf_r+0x214> -8000a1e0: 01012783 lw a5,16(sp) -8000a1e4: 0e012423 sw zero,232(sp) -8000a1e8: 00078863 beqz a5,8000a1f8 <_svfprintf_r+0xa84> -8000a1ec: 01012583 lw a1,16(sp) -8000a1f0: 000a0513 mv a0,s4 -8000a1f4: b35fa0ef jal ra,80004d28 <_free_r> -8000a1f8: 10c10d13 addi s10,sp,268 -8000a1fc: 00048c93 mv s9,s1 -8000a200: 9e9ff06f j 80009be8 <_svfprintf_r+0x474> -8000a204: 00812583 lw a1,8(sp) -8000a208: 0e410613 addi a2,sp,228 -8000a20c: 000a0513 mv a0,s4 -8000a210: 04612623 sw t1,76(sp) -8000a214: 04512223 sw t0,68(sp) -8000a218: 7e0040ef jal ra,8000e9f8 <__ssprint_r> -8000a21c: f8051063 bnez a0,8000999c <_svfprintf_r+0x228> -8000a220: 0ec12703 lw a4,236(sp) -8000a224: 10c10d13 addi s10,sp,268 -8000a228: 04c12303 lw t1,76(sp) -8000a22c: 04412283 lw t0,68(sp) -8000a230: f15ff06f j 8000a144 <_svfprintf_r+0x9d0> -8000a234: 01000693 li a3,16 -8000a238: 0e812783 lw a5,232(sp) -8000a23c: 0126c463 blt a3,s2,8000a244 <_svfprintf_r+0xad0> -8000a240: 4010106f j 8000be40 <_svfprintf_r+0x26cc> -8000a244: 800156b7 lui a3,0x80015 -8000a248: d3468d93 addi s11,a3,-716 # 80014d34 <__BSS_END__+0xffffdfbc> -8000a24c: 01000b13 li s6,16 -8000a250: 00700b93 li s7,7 -8000a254: 00812a83 lw s5,8(sp) -8000a258: 00c0006f j 8000a264 <_svfprintf_r+0xaf0> -8000a25c: ff090913 addi s2,s2,-16 -8000a260: 052b5663 bge s6,s2,8000a2ac <_svfprintf_r+0xb38> -8000a264: 01070713 addi a4,a4,16 -8000a268: 00178793 addi a5,a5,1 -8000a26c: 01bd2023 sw s11,0(s10) -8000a270: 016d2223 sw s6,4(s10) -8000a274: 0ee12623 sw a4,236(sp) -8000a278: 0ef12423 sw a5,232(sp) -8000a27c: 008d0d13 addi s10,s10,8 -8000a280: fcfbdee3 bge s7,a5,8000a25c <_svfprintf_r+0xae8> -8000a284: 0e410613 addi a2,sp,228 -8000a288: 000a8593 mv a1,s5 -8000a28c: 000a0513 mv a0,s4 -8000a290: 768040ef jal ra,8000e9f8 <__ssprint_r> -8000a294: f0051463 bnez a0,8000999c <_svfprintf_r+0x228> -8000a298: ff090913 addi s2,s2,-16 -8000a29c: 0ec12703 lw a4,236(sp) -8000a2a0: 0e812783 lw a5,232(sp) -8000a2a4: 10c10d13 addi s10,sp,268 -8000a2a8: fb2b4ee3 blt s6,s2,8000a264 <_svfprintf_r+0xaf0> -8000a2ac: 01270733 add a4,a4,s2 -8000a2b0: 00178793 addi a5,a5,1 -8000a2b4: 01bd2023 sw s11,0(s10) -8000a2b8: 012d2223 sw s2,4(s10) -8000a2bc: 0ee12623 sw a4,236(sp) -8000a2c0: 0ef12423 sw a5,232(sp) -8000a2c4: 00700693 li a3,7 -8000a2c8: f0f6d0e3 bge a3,a5,8000a1c8 <_svfprintf_r+0xa54> -8000a2cc: 00812583 lw a1,8(sp) -8000a2d0: 0e410613 addi a2,sp,228 -8000a2d4: 000a0513 mv a0,s4 -8000a2d8: 720040ef jal ra,8000e9f8 <__ssprint_r> -8000a2dc: ec051063 bnez a0,8000999c <_svfprintf_r+0x228> -8000a2e0: 0ec12703 lw a4,236(sp) -8000a2e4: ee5ff06f j 8000a1c8 <_svfprintf_r+0xa54> -8000a2e8: 02097793 andi a5,s2,32 -8000a2ec: 000d8313 mv t1,s11 -8000a2f0: 20079c63 bnez a5,8000a508 <_svfprintf_r+0xd94> -8000a2f4: 01412783 lw a5,20(sp) -8000a2f8: 01097713 andi a4,s2,16 -8000a2fc: 00478793 addi a5,a5,4 -8000a300: 00070463 beqz a4,8000a308 <_svfprintf_r+0xb94> -8000a304: 76d0106f j 8000c270 <_svfprintf_r+0x2afc> -8000a308: 04097713 andi a4,s2,64 -8000a30c: 00071463 bnez a4,8000a314 <_svfprintf_r+0xba0> -8000a310: 1ec0106f j 8000b4fc <_svfprintf_r+0x1d88> -8000a314: 01412703 lw a4,20(sp) -8000a318: 00f12a23 sw a5,20(sp) -8000a31c: 00090993 mv s3,s2 -8000a320: 00071b83 lh s7,0(a4) -8000a324: 41fbdd93 srai s11,s7,0x1f -8000a328: 000d8713 mv a4,s11 -8000a32c: d4075ee3 bgez a4,8000a088 <_svfprintf_r+0x914> -8000a330: 41700bb3 neg s7,s7 -8000a334: 017037b3 snez a5,s7 -8000a338: 41b00db3 neg s11,s11 -8000a33c: 40fd8db3 sub s11,s11,a5 -8000a340: 02d00793 li a5,45 -8000a344: 0cf103a3 sb a5,199(sp) -8000a348: fff00713 li a4,-1 -8000a34c: 00100793 li a5,1 -8000a350: f0e31863 bne t1,a4,80009a60 <_svfprintf_r+0x2ec> -8000a354: 00100713 li a4,1 -8000a358: 1ce78e63 beq a5,a4,8000a534 <_svfprintf_r+0xdc0> -8000a35c: 00200713 li a4,2 -8000a360: 20e78863 beq a5,a4,8000a570 <_svfprintf_r+0xdfc> -8000a364: 1b010693 addi a3,sp,432 -8000a368: 0080006f j 8000a370 <_svfprintf_r+0xbfc> -8000a36c: 000c8693 mv a3,s9 -8000a370: 01dd9793 slli a5,s11,0x1d -8000a374: 007bf713 andi a4,s7,7 -8000a378: 003bdb93 srli s7,s7,0x3 -8000a37c: 03070713 addi a4,a4,48 -8000a380: 0177ebb3 or s7,a5,s7 -8000a384: 003ddd93 srli s11,s11,0x3 -8000a388: fee68fa3 sb a4,-1(a3) -8000a38c: 01bbe7b3 or a5,s7,s11 -8000a390: fff68c93 addi s9,a3,-1 -8000a394: fc079ce3 bnez a5,8000a36c <_svfprintf_r+0xbf8> -8000a398: 0019f613 andi a2,s3,1 -8000a39c: 20060463 beqz a2,8000a5a4 <_svfprintf_r+0xe30> -8000a3a0: 03000613 li a2,48 -8000a3a4: 20c70063 beq a4,a2,8000a5a4 <_svfprintf_r+0xe30> -8000a3a8: ffe68693 addi a3,a3,-2 -8000a3ac: 1b010793 addi a5,sp,432 -8000a3b0: fecc8fa3 sb a2,-1(s9) -8000a3b4: 40d78b33 sub s6,a5,a3 -8000a3b8: 00098913 mv s2,s3 -8000a3bc: 00068c93 mv s9,a3 -8000a3c0: ec4ff06f j 80009a84 <_svfprintf_r+0x310> -8000a3c4: 02b00793 li a5,43 -8000a3c8: 0cf103a3 sb a5,199(sp) -8000a3cc: 0004ce03 lbu t3,0(s1) -8000a3d0: d20ff06f j 800098f0 <_svfprintf_r+0x17c> -8000a3d4: 01412783 lw a5,20(sp) -8000a3d8: 0004ce03 lbu t3,0(s1) -8000a3dc: 0007a403 lw s0,0(a5) -8000a3e0: 00478793 addi a5,a5,4 -8000a3e4: 00f12a23 sw a5,20(sp) -8000a3e8: d0045463 bgez s0,800098f0 <_svfprintf_r+0x17c> -8000a3ec: 40800433 neg s0,s0 -8000a3f0: 00496913 ori s2,s2,4 -8000a3f4: cfcff06f j 800098f0 <_svfprintf_r+0x17c> -8000a3f8: 08096913 ori s2,s2,128 -8000a3fc: 0004ce03 lbu t3,0(s1) -8000a400: cf0ff06f j 800098f0 <_svfprintf_r+0x17c> -8000a404: 0004ca83 lbu s5,0(s1) -8000a408: 00148793 addi a5,s1,1 -8000a40c: 017a9463 bne s5,s7,8000a414 <_svfprintf_r+0xca0> -8000a410: 5f10106f j 8000c200 <_svfprintf_r+0x2a8c> -8000a414: fd0a8713 addi a4,s5,-48 -8000a418: 00078493 mv s1,a5 -8000a41c: 00000d93 li s11,0 -8000a420: cceb6c63 bltu s6,a4,800098f8 <_svfprintf_r+0x184> -8000a424: 00148493 addi s1,s1,1 -8000a428: 002d9793 slli a5,s11,0x2 -8000a42c: fff4ca83 lbu s5,-1(s1) -8000a430: 01b787b3 add a5,a5,s11 -8000a434: 00179793 slli a5,a5,0x1 -8000a438: 00e78db3 add s11,a5,a4 -8000a43c: fd0a8713 addi a4,s5,-48 -8000a440: feeb72e3 bgeu s6,a4,8000a424 <_svfprintf_r+0xcb0> -8000a444: cb4ff06f j 800098f8 <_svfprintf_r+0x184> -8000a448: 00196913 ori s2,s2,1 -8000a44c: 0004ce03 lbu t3,0(s1) -8000a450: ca0ff06f j 800098f0 <_svfprintf_r+0x17c> -8000a454: 0c714783 lbu a5,199(sp) -8000a458: 0004ce03 lbu t3,0(s1) -8000a45c: c8079a63 bnez a5,800098f0 <_svfprintf_r+0x17c> -8000a460: 02000793 li a5,32 -8000a464: 0cf103a3 sb a5,199(sp) -8000a468: c88ff06f j 800098f0 <_svfprintf_r+0x17c> -8000a46c: 02097793 andi a5,s2,32 -8000a470: 000d8313 mv t1,s11 -8000a474: 06079663 bnez a5,8000a4e0 <_svfprintf_r+0xd6c> -8000a478: 01412683 lw a3,20(sp) -8000a47c: 01097713 andi a4,s2,16 -8000a480: 00468793 addi a5,a3,4 -8000a484: 0006ab83 lw s7,0(a3) -8000a488: 00070463 beqz a4,8000a490 <_svfprintf_r+0xd1c> -8000a48c: 5dd0106f j 8000c268 <_svfprintf_r+0x2af4> -8000a490: 04097713 andi a4,s2,64 -8000a494: 00071463 bnez a4,8000a49c <_svfprintf_r+0xd28> -8000a498: 0880106f j 8000b520 <_svfprintf_r+0x1dac> -8000a49c: 010b9b93 slli s7,s7,0x10 -8000a4a0: 00f12a23 sw a5,20(sp) -8000a4a4: 010bdb93 srli s7,s7,0x10 -8000a4a8: 00000d93 li s11,0 -8000a4ac: 00090993 mv s3,s2 -8000a4b0: 00100793 li a5,1 -8000a4b4: da0ff06f j 80009a54 <_svfprintf_r+0x2e0> -8000a4b8: 01412783 lw a5,20(sp) -8000a4bc: 00778793 addi a5,a5,7 -8000a4c0: ff87f793 andi a5,a5,-8 -8000a4c4: 0007ab83 lw s7,0(a5) -8000a4c8: 0047ad83 lw s11,4(a5) -8000a4cc: 00878713 addi a4,a5,8 -8000a4d0: 00e12a23 sw a4,20(sp) -8000a4d4: bff97993 andi s3,s2,-1025 -8000a4d8: 00000793 li a5,0 -8000a4dc: d78ff06f j 80009a54 <_svfprintf_r+0x2e0> -8000a4e0: 00090993 mv s3,s2 -8000a4e4: 01412783 lw a5,20(sp) -8000a4e8: 00778793 addi a5,a5,7 -8000a4ec: ff87f793 andi a5,a5,-8 -8000a4f0: 00878713 addi a4,a5,8 -8000a4f4: 0007ab83 lw s7,0(a5) -8000a4f8: 0047ad83 lw s11,4(a5) -8000a4fc: 00e12a23 sw a4,20(sp) -8000a500: 00100793 li a5,1 -8000a504: d50ff06f j 80009a54 <_svfprintf_r+0x2e0> -8000a508: 00090993 mv s3,s2 -8000a50c: 01412783 lw a5,20(sp) -8000a510: 00778793 addi a5,a5,7 -8000a514: ff87f793 andi a5,a5,-8 -8000a518: 0047a703 lw a4,4(a5) -8000a51c: 00878693 addi a3,a5,8 -8000a520: 00d12a23 sw a3,20(sp) -8000a524: 0007ab83 lw s7,0(a5) -8000a528: 00070d93 mv s11,a4 -8000a52c: b59ff06f j 8000a084 <_svfprintf_r+0x910> -8000a530: 00090993 mv s3,s2 -8000a534: 500d9ce3 bnez s11,8000b24c <_svfprintf_r+0x1ad8> -8000a538: 00900793 li a5,9 -8000a53c: 5177e8e3 bltu a5,s7,8000b24c <_svfprintf_r+0x1ad8> -8000a540: 030b8b93 addi s7,s7,48 -8000a544: 1b7107a3 sb s7,431(sp) -8000a548: 00098913 mv s2,s3 -8000a54c: 00100b13 li s6,1 -8000a550: 1af10c93 addi s9,sp,431 -8000a554: d30ff06f j 80009a84 <_svfprintf_r+0x310> -8000a558: 00100713 li a4,1 -8000a55c: 00e79463 bne a5,a4,8000a564 <_svfprintf_r+0xdf0> -8000a560: 1600106f j 8000b6c0 <_svfprintf_r+0x1f4c> -8000a564: 00200713 li a4,2 -8000a568: 00090993 mv s3,s2 -8000a56c: dee79ce3 bne a5,a4,8000a364 <_svfprintf_r+0xbf0> -8000a570: 03012683 lw a3,48(sp) -8000a574: 1b010c93 addi s9,sp,432 -8000a578: 00fbf793 andi a5,s7,15 -8000a57c: 00f687b3 add a5,a3,a5 -8000a580: 0007c783 lbu a5,0(a5) -8000a584: 01cd9713 slli a4,s11,0x1c -8000a588: 004bdb93 srli s7,s7,0x4 -8000a58c: fffc8c93 addi s9,s9,-1 -8000a590: 01776bb3 or s7,a4,s7 -8000a594: 004ddd93 srli s11,s11,0x4 -8000a598: 00fc8023 sb a5,0(s9) -8000a59c: 01bbe7b3 or a5,s7,s11 -8000a5a0: fc079ce3 bnez a5,8000a578 <_svfprintf_r+0xe04> -8000a5a4: 1b010793 addi a5,sp,432 -8000a5a8: 41978b33 sub s6,a5,s9 -8000a5ac: 00098913 mv s2,s3 -8000a5b0: cd4ff06f j 80009a84 <_svfprintf_r+0x310> -8000a5b4: 06500693 li a3,101 -8000a5b8: 3356d463 bge a3,s5,8000a8e0 <_svfprintf_r+0x116c> -8000a5bc: 0f012683 lw a3,240(sp) -8000a5c0: 0a010593 addi a1,sp,160 -8000a5c4: 0b010513 addi a0,sp,176 -8000a5c8: 0ad12823 sw a3,176(sp) -8000a5cc: 0f412683 lw a3,244(sp) -8000a5d0: 04e12223 sw a4,68(sp) -8000a5d4: 0a012023 sw zero,160(sp) -8000a5d8: 0ad12a23 sw a3,180(sp) -8000a5dc: 0f812683 lw a3,248(sp) -8000a5e0: 0a012223 sw zero,164(sp) -8000a5e4: 0a012423 sw zero,168(sp) -8000a5e8: 0ad12c23 sw a3,184(sp) -8000a5ec: 0fc12683 lw a3,252(sp) -8000a5f0: 0a012623 sw zero,172(sp) -8000a5f4: 0ad12e23 sw a3,188(sp) -8000a5f8: 671060ef jal ra,80011468 <__eqtf2> -8000a5fc: 04412703 lw a4,68(sp) -8000a600: 58051263 bnez a0,8000ab84 <_svfprintf_r+0x1410> -8000a604: 0e812783 lw a5,232(sp) -8000a608: 800156b7 lui a3,0x80015 -8000a60c: 81068693 addi a3,a3,-2032 # 80014810 <__BSS_END__+0xffffda98> -8000a610: 00170713 addi a4,a4,1 -8000a614: 00dd2023 sw a3,0(s10) -8000a618: 00178793 addi a5,a5,1 -8000a61c: 00100693 li a3,1 -8000a620: 00dd2223 sw a3,4(s10) -8000a624: 0ee12623 sw a4,236(sp) -8000a628: 0ef12423 sw a5,232(sp) -8000a62c: 00700713 li a4,7 -8000a630: 008d0d13 addi s10,s10,8 -8000a634: 4ef744e3 blt a4,a5,8000b31c <_svfprintf_r+0x1ba8> -8000a638: 0cc12783 lw a5,204(sp) -8000a63c: 01c12703 lw a4,28(sp) -8000a640: 00e7ca63 blt a5,a4,8000a654 <_svfprintf_r+0xee0> -8000a644: 00197793 andi a5,s2,1 -8000a648: 00079663 bnez a5,8000a654 <_svfprintf_r+0xee0> -8000a64c: 0ec12703 lw a4,236(sp) -8000a650: b69ff06f j 8000a1b8 <_svfprintf_r+0xa44> -8000a654: 03412783 lw a5,52(sp) -8000a658: 02c12683 lw a3,44(sp) -8000a65c: 0ec12703 lw a4,236(sp) -8000a660: 00fd2023 sw a5,0(s10) -8000a664: 0e812783 lw a5,232(sp) -8000a668: 00e68733 add a4,a3,a4 -8000a66c: 00dd2223 sw a3,4(s10) -8000a670: 00178793 addi a5,a5,1 -8000a674: 0ee12623 sw a4,236(sp) -8000a678: 0ef12423 sw a5,232(sp) -8000a67c: 00700693 li a3,7 -8000a680: 008d0d13 addi s10,s10,8 -8000a684: 02f6cae3 blt a3,a5,8000aeb8 <_svfprintf_r+0x1744> -8000a688: 01c12783 lw a5,28(sp) -8000a68c: fff78b13 addi s6,a5,-1 -8000a690: b36054e3 blez s6,8000a1b8 <_svfprintf_r+0xa44> -8000a694: 01000693 li a3,16 -8000a698: 0e812783 lw a5,232(sp) -8000a69c: 4b66d0e3 bge a3,s6,8000b33c <_svfprintf_r+0x1bc8> -8000a6a0: 01000b93 li s7,16 -8000a6a4: 00700a93 li s5,7 -8000a6a8: 00812c83 lw s9,8(sp) -8000a6ac: 00c0006f j 8000a6b8 <_svfprintf_r+0xf44> -8000a6b0: ff0b0b13 addi s6,s6,-16 -8000a6b4: 496bd4e3 bge s7,s6,8000b33c <_svfprintf_r+0x1bc8> -8000a6b8: 01070713 addi a4,a4,16 -8000a6bc: 00178793 addi a5,a5,1 -8000a6c0: 018d2023 sw s8,0(s10) -8000a6c4: 017d2223 sw s7,4(s10) -8000a6c8: 0ee12623 sw a4,236(sp) -8000a6cc: 0ef12423 sw a5,232(sp) -8000a6d0: 008d0d13 addi s10,s10,8 -8000a6d4: fcfadee3 bge s5,a5,8000a6b0 <_svfprintf_r+0xf3c> -8000a6d8: 0e410613 addi a2,sp,228 -8000a6dc: 000c8593 mv a1,s9 -8000a6e0: 000a0513 mv a0,s4 -8000a6e4: 314040ef jal ra,8000e9f8 <__ssprint_r> -8000a6e8: aa051a63 bnez a0,8000999c <_svfprintf_r+0x228> -8000a6ec: 0ec12703 lw a4,236(sp) -8000a6f0: 0e812783 lw a5,232(sp) -8000a6f4: 10c10d13 addi s10,sp,268 -8000a6f8: fb9ff06f j 8000a6b0 <_svfprintf_r+0xf3c> -8000a6fc: 41340bb3 sub s7,s0,s3 -8000a700: a97050e3 blez s7,8000a180 <_svfprintf_r+0xa0c> -8000a704: 01000613 li a2,16 -8000a708: 0e812683 lw a3,232(sp) -8000a70c: 0b765463 bge a2,s7,8000a7b4 <_svfprintf_r+0x1040> -8000a710: 04912223 sw s1,68(sp) -8000a714: 000d0793 mv a5,s10 -8000a718: 000b8493 mv s1,s7 -8000a71c: 000c8d13 mv s10,s9 -8000a720: 00098b93 mv s7,s3 -8000a724: 000b0c93 mv s9,s6 -8000a728: 00040993 mv s3,s0 -8000a72c: 01000e93 li t4,16 -8000a730: 00700d93 li s11,7 -8000a734: 00812403 lw s0,8(sp) -8000a738: 00030b13 mv s6,t1 -8000a73c: 00c0006f j 8000a748 <_svfprintf_r+0xfd4> -8000a740: ff048493 addi s1,s1,-16 -8000a744: 049ed863 bge t4,s1,8000a794 <_svfprintf_r+0x1020> -8000a748: 01070713 addi a4,a4,16 -8000a74c: 00168693 addi a3,a3,1 -8000a750: 0187a023 sw s8,0(a5) -8000a754: 01d7a223 sw t4,4(a5) -8000a758: 0ee12623 sw a4,236(sp) -8000a75c: 0ed12423 sw a3,232(sp) -8000a760: 00878793 addi a5,a5,8 -8000a764: fcdddee3 bge s11,a3,8000a740 <_svfprintf_r+0xfcc> -8000a768: 0e410613 addi a2,sp,228 -8000a76c: 00040593 mv a1,s0 -8000a770: 000a0513 mv a0,s4 -8000a774: 284040ef jal ra,8000e9f8 <__ssprint_r> -8000a778: a2051263 bnez a0,8000999c <_svfprintf_r+0x228> -8000a77c: 01000e93 li t4,16 -8000a780: ff048493 addi s1,s1,-16 -8000a784: 0ec12703 lw a4,236(sp) -8000a788: 0e812683 lw a3,232(sp) -8000a78c: 10c10793 addi a5,sp,268 -8000a790: fa9ecce3 blt t4,s1,8000a748 <_svfprintf_r+0xfd4> -8000a794: 00098413 mv s0,s3 -8000a798: 000b8993 mv s3,s7 -8000a79c: 00048b93 mv s7,s1 -8000a7a0: 04412483 lw s1,68(sp) -8000a7a4: 000b0313 mv t1,s6 -8000a7a8: 000c8b13 mv s6,s9 -8000a7ac: 000d0c93 mv s9,s10 -8000a7b0: 00078d13 mv s10,a5 -8000a7b4: 01770733 add a4,a4,s7 -8000a7b8: 00168693 addi a3,a3,1 -8000a7bc: 018d2023 sw s8,0(s10) -8000a7c0: 017d2223 sw s7,4(s10) -8000a7c4: 0ee12623 sw a4,236(sp) -8000a7c8: 0ed12423 sw a3,232(sp) -8000a7cc: 00700613 li a2,7 -8000a7d0: 008d0d13 addi s10,s10,8 -8000a7d4: 9ad656e3 bge a2,a3,8000a180 <_svfprintf_r+0xa0c> -8000a7d8: 00812583 lw a1,8(sp) -8000a7dc: 0e410613 addi a2,sp,228 -8000a7e0: 000a0513 mv a0,s4 -8000a7e4: 04612223 sw t1,68(sp) -8000a7e8: 210040ef jal ra,8000e9f8 <__ssprint_r> -8000a7ec: 9a051863 bnez a0,8000999c <_svfprintf_r+0x228> -8000a7f0: 04412303 lw t1,68(sp) -8000a7f4: 0ec12703 lw a4,236(sp) -8000a7f8: 10c10d13 addi s10,sp,268 -8000a7fc: 41630db3 sub s11,t1,s6 -8000a800: 99b054e3 blez s11,8000a188 <_svfprintf_r+0xa14> -8000a804: 01000613 li a2,16 -8000a808: 0e812683 lw a3,232(sp) -8000a80c: 09b65863 bge a2,s11,8000a89c <_svfprintf_r+0x1128> -8000a810: 000d0793 mv a5,s10 -8000a814: 01000813 li a6,16 -8000a818: 000c8d13 mv s10,s9 -8000a81c: 00700b93 li s7,7 -8000a820: 000b0c93 mv s9,s6 -8000a824: 00098b13 mv s6,s3 -8000a828: 00040993 mv s3,s0 -8000a82c: 00812403 lw s0,8(sp) -8000a830: 00c0006f j 8000a83c <_svfprintf_r+0x10c8> -8000a834: ff0d8d93 addi s11,s11,-16 -8000a838: 05b85863 bge a6,s11,8000a888 <_svfprintf_r+0x1114> -8000a83c: 01070713 addi a4,a4,16 -8000a840: 00168693 addi a3,a3,1 -8000a844: 0187a023 sw s8,0(a5) -8000a848: 0107a223 sw a6,4(a5) -8000a84c: 0ee12623 sw a4,236(sp) -8000a850: 0ed12423 sw a3,232(sp) -8000a854: 00878793 addi a5,a5,8 -8000a858: fcdbdee3 bge s7,a3,8000a834 <_svfprintf_r+0x10c0> -8000a85c: 0e410613 addi a2,sp,228 -8000a860: 00040593 mv a1,s0 -8000a864: 000a0513 mv a0,s4 -8000a868: 190040ef jal ra,8000e9f8 <__ssprint_r> -8000a86c: 92051863 bnez a0,8000999c <_svfprintf_r+0x228> -8000a870: 01000813 li a6,16 -8000a874: ff0d8d93 addi s11,s11,-16 -8000a878: 0ec12703 lw a4,236(sp) -8000a87c: 0e812683 lw a3,232(sp) -8000a880: 10c10793 addi a5,sp,268 -8000a884: fbb84ce3 blt a6,s11,8000a83c <_svfprintf_r+0x10c8> -8000a888: 00098413 mv s0,s3 -8000a88c: 000b0993 mv s3,s6 -8000a890: 000c8b13 mv s6,s9 -8000a894: 000d0c93 mv s9,s10 -8000a898: 00078d13 mv s10,a5 -8000a89c: 01b70733 add a4,a4,s11 -8000a8a0: 00168693 addi a3,a3,1 -8000a8a4: 018d2023 sw s8,0(s10) -8000a8a8: 01bd2223 sw s11,4(s10) -8000a8ac: 0ee12623 sw a4,236(sp) -8000a8b0: 0ed12423 sw a3,232(sp) -8000a8b4: 00700613 li a2,7 -8000a8b8: 008d0d13 addi s10,s10,8 -8000a8bc: 8cd656e3 bge a2,a3,8000a188 <_svfprintf_r+0xa14> -8000a8c0: 00812583 lw a1,8(sp) -8000a8c4: 0e410613 addi a2,sp,228 -8000a8c8: 000a0513 mv a0,s4 -8000a8cc: 12c040ef jal ra,8000e9f8 <__ssprint_r> -8000a8d0: 8c051663 bnez a0,8000999c <_svfprintf_r+0x228> -8000a8d4: 0ec12703 lw a4,236(sp) -8000a8d8: 10c10d13 addi s10,sp,268 -8000a8dc: 8adff06f j 8000a188 <_svfprintf_r+0xa14> -8000a8e0: 0e812603 lw a2,232(sp) -8000a8e4: 01c12783 lw a5,28(sp) -8000a8e8: 00100693 li a3,1 -8000a8ec: 019d2023 sw s9,0(s10) -8000a8f0: 00170d93 addi s11,a4,1 -8000a8f4: 00160b13 addi s6,a2,1 -8000a8f8: 008d0b93 addi s7,s10,8 -8000a8fc: 40f6d063 bge a3,a5,8000acfc <_svfprintf_r+0x1588> -8000a900: 00100693 li a3,1 -8000a904: 00dd2223 sw a3,4(s10) -8000a908: 0fb12623 sw s11,236(sp) -8000a90c: 0f612423 sw s6,232(sp) -8000a910: 00700693 li a3,7 -8000a914: 4966ca63 blt a3,s6,8000ada8 <_svfprintf_r+0x1634> -8000a918: 02c12783 lw a5,44(sp) -8000a91c: 03412703 lw a4,52(sp) -8000a920: 001b0b13 addi s6,s6,1 -8000a924: 00fd8db3 add s11,s11,a5 -8000a928: 00eba023 sw a4,0(s7) -8000a92c: 00fba223 sw a5,4(s7) -8000a930: 0fb12623 sw s11,236(sp) -8000a934: 0f612423 sw s6,232(sp) -8000a938: 00700693 li a3,7 -8000a93c: 008b8b93 addi s7,s7,8 -8000a940: 4966c863 blt a3,s6,8000add0 <_svfprintf_r+0x165c> -8000a944: 0f012683 lw a3,240(sp) -8000a948: 01c12783 lw a5,28(sp) -8000a94c: 001b0813 addi a6,s6,1 -8000a950: 0ad12823 sw a3,176(sp) -8000a954: 0f412683 lw a3,244(sp) -8000a958: 0a010593 addi a1,sp,160 -8000a95c: 0b010513 addi a0,sp,176 -8000a960: 0ad12a23 sw a3,180(sp) -8000a964: 0f812683 lw a3,248(sp) -8000a968: 00080a93 mv s5,a6 -8000a96c: 03012023 sw a6,32(sp) -8000a970: 0ad12c23 sw a3,184(sp) -8000a974: 0fc12683 lw a3,252(sp) -8000a978: 0a012023 sw zero,160(sp) -8000a97c: 0a012223 sw zero,164(sp) -8000a980: 0ad12e23 sw a3,188(sp) -8000a984: fff78693 addi a3,a5,-1 -8000a988: 00d12c23 sw a3,24(sp) -8000a98c: 0a012423 sw zero,168(sp) -8000a990: 0a012623 sw zero,172(sp) -8000a994: 2d5060ef jal ra,80011468 <__eqtf2> -8000a998: 008b8d13 addi s10,s7,8 -8000a99c: 01812683 lw a3,24(sp) -8000a9a0: 02012803 lw a6,32(sp) -8000a9a4: 38050063 beqz a0,8000ad24 <_svfprintf_r+0x15b0> -8000a9a8: 001c8793 addi a5,s9,1 -8000a9ac: 00dd8db3 add s11,s11,a3 -8000a9b0: 00fba023 sw a5,0(s7) -8000a9b4: 00dba223 sw a3,4(s7) -8000a9b8: 0fb12623 sw s11,236(sp) -8000a9bc: 0f512423 sw s5,232(sp) -8000a9c0: 00700793 li a5,7 -8000a9c4: 7957c263 blt a5,s5,8000b148 <_svfprintf_r+0x19d4> -8000a9c8: 010b8793 addi a5,s7,16 -8000a9cc: 002b0a93 addi s5,s6,2 -8000a9d0: 000d0b93 mv s7,s10 -8000a9d4: 00078d13 mv s10,a5 -8000a9d8: 03812683 lw a3,56(sp) -8000a9dc: 0d410793 addi a5,sp,212 -8000a9e0: 00fba023 sw a5,0(s7) -8000a9e4: 00dd8733 add a4,s11,a3 -8000a9e8: 00dba223 sw a3,4(s7) -8000a9ec: 0ee12623 sw a4,236(sp) -8000a9f0: 0f512423 sw s5,232(sp) -8000a9f4: 00700793 li a5,7 -8000a9f8: fd57d063 bge a5,s5,8000a1b8 <_svfprintf_r+0xa44> -8000a9fc: 00812583 lw a1,8(sp) -8000aa00: 0e410613 addi a2,sp,228 -8000aa04: 000a0513 mv a0,s4 -8000aa08: 7f1030ef jal ra,8000e9f8 <__ssprint_r> -8000aa0c: 00050463 beqz a0,8000aa14 <_svfprintf_r+0x12a0> -8000aa10: f8dfe06f j 8000999c <_svfprintf_r+0x228> -8000aa14: 0ec12703 lw a4,236(sp) -8000aa18: 10c10d13 addi s10,sp,268 -8000aa1c: f9cff06f j 8000a1b8 <_svfprintf_r+0xa44> -8000aa20: 00090993 mv s3,s2 -8000aa24: 931ff06f j 8000a354 <_svfprintf_r+0xbe0> -8000aa28: 800157b7 lui a5,0x80015 -8000aa2c: 01000613 li a2,16 -8000aa30: 0e812683 lw a3,232(sp) -8000aa34: d3478d93 addi s11,a5,-716 # 80014d34 <__BSS_END__+0xffffdfbc> -8000aa38: 0d065463 bge a2,a6,8000ab00 <_svfprintf_r+0x138c> -8000aa3c: 04912623 sw s1,76(sp) -8000aa40: 05212823 sw s2,80(sp) -8000aa44: 000d0793 mv a5,s10 -8000aa48: 000d8913 mv s2,s11 -8000aa4c: 000b0d13 mv s10,s6 -8000aa50: 000c8d93 mv s11,s9 -8000aa54: 01000f13 li t5,16 -8000aa58: 00098c93 mv s9,s3 -8000aa5c: 00700393 li t2,7 -8000aa60: 00040993 mv s3,s0 -8000aa64: 04512223 sw t0,68(sp) -8000aa68: 00030b13 mv s6,t1 -8000aa6c: 00812483 lw s1,8(sp) -8000aa70: 00080413 mv s0,a6 -8000aa74: 00c0006f j 8000aa80 <_svfprintf_r+0x130c> -8000aa78: ff040413 addi s0,s0,-16 -8000aa7c: 048f5c63 bge t5,s0,8000aad4 <_svfprintf_r+0x1360> -8000aa80: 01070713 addi a4,a4,16 -8000aa84: 00168693 addi a3,a3,1 -8000aa88: 0127a023 sw s2,0(a5) -8000aa8c: 01e7a223 sw t5,4(a5) -8000aa90: 0ee12623 sw a4,236(sp) -8000aa94: 0ed12423 sw a3,232(sp) -8000aa98: 00878793 addi a5,a5,8 -8000aa9c: fcd3dee3 bge t2,a3,8000aa78 <_svfprintf_r+0x1304> -8000aaa0: 0e410613 addi a2,sp,228 -8000aaa4: 00048593 mv a1,s1 -8000aaa8: 000a0513 mv a0,s4 -8000aaac: 74d030ef jal ra,8000e9f8 <__ssprint_r> -8000aab0: 00050463 beqz a0,8000aab8 <_svfprintf_r+0x1344> -8000aab4: ee9fe06f j 8000999c <_svfprintf_r+0x228> -8000aab8: 01000f13 li t5,16 -8000aabc: ff040413 addi s0,s0,-16 -8000aac0: 0ec12703 lw a4,236(sp) -8000aac4: 0e812683 lw a3,232(sp) -8000aac8: 10c10793 addi a5,sp,268 -8000aacc: 00700393 li t2,7 -8000aad0: fa8f48e3 blt t5,s0,8000aa80 <_svfprintf_r+0x130c> -8000aad4: 00040813 mv a6,s0 -8000aad8: 04412283 lw t0,68(sp) -8000aadc: 00098413 mv s0,s3 -8000aae0: 04c12483 lw s1,76(sp) -8000aae4: 000c8993 mv s3,s9 -8000aae8: 000d8c93 mv s9,s11 -8000aaec: 00090d93 mv s11,s2 -8000aaf0: 05012903 lw s2,80(sp) -8000aaf4: 000b0313 mv t1,s6 -8000aaf8: 000d0b13 mv s6,s10 -8000aafc: 00078d13 mv s10,a5 -8000ab00: 01070733 add a4,a4,a6 -8000ab04: 00168693 addi a3,a3,1 -8000ab08: 01bd2023 sw s11,0(s10) -8000ab0c: 010d2223 sw a6,4(s10) -8000ab10: 0ee12623 sw a4,236(sp) -8000ab14: 0ed12423 sw a3,232(sp) -8000ab18: 00700613 li a2,7 -8000ab1c: 008d0d13 addi s10,s10,8 -8000ab20: ded65663 bge a2,a3,8000a10c <_svfprintf_r+0x998> -8000ab24: 00812583 lw a1,8(sp) -8000ab28: 0e410613 addi a2,sp,228 -8000ab2c: 000a0513 mv a0,s4 -8000ab30: 04612623 sw t1,76(sp) -8000ab34: 04512223 sw t0,68(sp) -8000ab38: 6c1030ef jal ra,8000e9f8 <__ssprint_r> -8000ab3c: 00050463 beqz a0,8000ab44 <_svfprintf_r+0x13d0> -8000ab40: e5dfe06f j 8000999c <_svfprintf_r+0x228> -8000ab44: 0ec12703 lw a4,236(sp) -8000ab48: 10c10d13 addi s10,sp,268 -8000ab4c: 04c12303 lw t1,76(sp) -8000ab50: 04412283 lw t0,68(sp) -8000ab54: db8ff06f j 8000a10c <_svfprintf_r+0x998> -8000ab58: 00812583 lw a1,8(sp) -8000ab5c: 0e410613 addi a2,sp,228 -8000ab60: 000a0513 mv a0,s4 -8000ab64: 04612223 sw t1,68(sp) -8000ab68: 691030ef jal ra,8000e9f8 <__ssprint_r> -8000ab6c: 00050463 beqz a0,8000ab74 <_svfprintf_r+0x1400> -8000ab70: e2dfe06f j 8000999c <_svfprintf_r+0x228> -8000ab74: 0ec12703 lw a4,236(sp) -8000ab78: 10c10d13 addi s10,sp,268 -8000ab7c: 04412303 lw t1,68(sp) -8000ab80: df8ff06f j 8000a178 <_svfprintf_r+0xa04> -8000ab84: 0cc12603 lw a2,204(sp) -8000ab88: 5ec05863 blez a2,8000b178 <_svfprintf_r+0x1a04> -8000ab8c: 01c12783 lw a5,28(sp) -8000ab90: 01812683 lw a3,24(sp) -8000ab94: 00078b13 mv s6,a5 -8000ab98: 30f6ca63 blt a3,a5,8000aeac <_svfprintf_r+0x1738> -8000ab9c: 03605663 blez s6,8000abc8 <_svfprintf_r+0x1454> -8000aba0: 0e812683 lw a3,232(sp) -8000aba4: 01670733 add a4,a4,s6 -8000aba8: 019d2023 sw s9,0(s10) -8000abac: 00168693 addi a3,a3,1 -8000abb0: 016d2223 sw s6,4(s10) -8000abb4: 0ee12623 sw a4,236(sp) -8000abb8: 0ed12423 sw a3,232(sp) -8000abbc: 00700613 li a2,7 -8000abc0: 008d0d13 addi s10,s10,8 -8000abc4: 20d648e3 blt a2,a3,8000b5d4 <_svfprintf_r+0x1e60> -8000abc8: fffb4693 not a3,s6 -8000abcc: 01812783 lw a5,24(sp) -8000abd0: 41f6d693 srai a3,a3,0x1f -8000abd4: 00db7b33 and s6,s6,a3 -8000abd8: 41678b33 sub s6,a5,s6 -8000abdc: 37604863 bgtz s6,8000af4c <_svfprintf_r+0x17d8> -8000abe0: 01812783 lw a5,24(sp) -8000abe4: 40097693 andi a3,s2,1024 -8000abe8: 00fc8ab3 add s5,s9,a5 -8000abec: 3c069663 bnez a3,8000afb8 <_svfprintf_r+0x1844> -8000abf0: 0cc12b03 lw s6,204(sp) -8000abf4: 01c12783 lw a5,28(sp) -8000abf8: 00fb4663 blt s6,a5,8000ac04 <_svfprintf_r+0x1490> -8000abfc: 00197693 andi a3,s2,1 -8000ac00: 200680e3 beqz a3,8000b600 <_svfprintf_r+0x1e8c> -8000ac04: 03412683 lw a3,52(sp) -8000ac08: 02c12783 lw a5,44(sp) -8000ac0c: 00700613 li a2,7 -8000ac10: 00dd2023 sw a3,0(s10) -8000ac14: 0e812683 lw a3,232(sp) -8000ac18: 00f70733 add a4,a4,a5 -8000ac1c: 00fd2223 sw a5,4(s10) -8000ac20: 00168693 addi a3,a3,1 -8000ac24: 0ee12623 sw a4,236(sp) -8000ac28: 0ed12423 sw a3,232(sp) -8000ac2c: 008d0d13 addi s10,s10,8 -8000ac30: 3cd64ce3 blt a2,a3,8000b808 <_svfprintf_r+0x2094> -8000ac34: 01c12683 lw a3,28(sp) -8000ac38: 00dc87b3 add a5,s9,a3 -8000ac3c: 41668b33 sub s6,a3,s6 -8000ac40: 415787b3 sub a5,a5,s5 -8000ac44: 000b0b93 mv s7,s6 -8000ac48: 0167d463 bge a5,s6,8000ac50 <_svfprintf_r+0x14dc> -8000ac4c: 00078b93 mv s7,a5 -8000ac50: 03705663 blez s7,8000ac7c <_svfprintf_r+0x1508> -8000ac54: 0e812783 lw a5,232(sp) -8000ac58: 01770733 add a4,a4,s7 -8000ac5c: 015d2023 sw s5,0(s10) -8000ac60: 00178793 addi a5,a5,1 -8000ac64: 017d2223 sw s7,4(s10) -8000ac68: 0ee12623 sw a4,236(sp) -8000ac6c: 0ef12423 sw a5,232(sp) -8000ac70: 00700693 li a3,7 -8000ac74: 008d0d13 addi s10,s10,8 -8000ac78: 5af6c6e3 blt a3,a5,8000ba24 <_svfprintf_r+0x22b0> -8000ac7c: fffbc793 not a5,s7 -8000ac80: 41f7d793 srai a5,a5,0x1f -8000ac84: 00fbfbb3 and s7,s7,a5 -8000ac88: 417b0b33 sub s6,s6,s7 -8000ac8c: d3605663 blez s6,8000a1b8 <_svfprintf_r+0xa44> -8000ac90: 01000693 li a3,16 -8000ac94: 0e812783 lw a5,232(sp) -8000ac98: 6b66d263 bge a3,s6,8000b33c <_svfprintf_r+0x1bc8> -8000ac9c: 01000b93 li s7,16 -8000aca0: 00700a93 li s5,7 -8000aca4: 00812c83 lw s9,8(sp) -8000aca8: 00c0006f j 8000acb4 <_svfprintf_r+0x1540> -8000acac: ff0b0b13 addi s6,s6,-16 -8000acb0: 696bd663 bge s7,s6,8000b33c <_svfprintf_r+0x1bc8> -8000acb4: 01070713 addi a4,a4,16 -8000acb8: 00178793 addi a5,a5,1 -8000acbc: 018d2023 sw s8,0(s10) -8000acc0: 017d2223 sw s7,4(s10) -8000acc4: 0ee12623 sw a4,236(sp) -8000acc8: 0ef12423 sw a5,232(sp) -8000accc: 008d0d13 addi s10,s10,8 -8000acd0: fcfadee3 bge s5,a5,8000acac <_svfprintf_r+0x1538> -8000acd4: 0e410613 addi a2,sp,228 -8000acd8: 000c8593 mv a1,s9 -8000acdc: 000a0513 mv a0,s4 -8000ace0: 519030ef jal ra,8000e9f8 <__ssprint_r> -8000ace4: 00050463 beqz a0,8000acec <_svfprintf_r+0x1578> -8000ace8: cb5fe06f j 8000999c <_svfprintf_r+0x228> -8000acec: 0ec12703 lw a4,236(sp) -8000acf0: 0e812783 lw a5,232(sp) -8000acf4: 10c10d13 addi s10,sp,268 -8000acf8: fb5ff06f j 8000acac <_svfprintf_r+0x1538> -8000acfc: 00197593 andi a1,s2,1 -8000ad00: c00590e3 bnez a1,8000a900 <_svfprintf_r+0x118c> -8000ad04: 00dd2223 sw a3,4(s10) -8000ad08: 0fb12623 sw s11,236(sp) -8000ad0c: 0f612423 sw s6,232(sp) -8000ad10: 00700793 li a5,7 -8000ad14: 4367ca63 blt a5,s6,8000b148 <_svfprintf_r+0x19d4> -8000ad18: 00260a93 addi s5,a2,2 -8000ad1c: 010d0d13 addi s10,s10,16 -8000ad20: cb9ff06f j 8000a9d8 <_svfprintf_r+0x1264> -8000ad24: cad05ae3 blez a3,8000a9d8 <_svfprintf_r+0x1264> -8000ad28: 01000793 li a5,16 -8000ad2c: 00d7c463 blt a5,a3,8000ad34 <_svfprintf_r+0x15c0> -8000ad30: 4c80106f j 8000c1f8 <_svfprintf_r+0x2a84> -8000ad34: 00812c23 sw s0,24(sp) -8000ad38: 01000c93 li s9,16 -8000ad3c: 00700a93 li s5,7 -8000ad40: 00068413 mv s0,a3 -8000ad44: 00812d03 lw s10,8(sp) -8000ad48: 00080b13 mv s6,a6 -8000ad4c: 0100006f j 8000ad5c <_svfprintf_r+0x15e8> -8000ad50: ff040413 addi s0,s0,-16 -8000ad54: 768cd663 bge s9,s0,8000b4c0 <_svfprintf_r+0x1d4c> -8000ad58: 001b0b13 addi s6,s6,1 -8000ad5c: 010d8d93 addi s11,s11,16 -8000ad60: 018ba023 sw s8,0(s7) -8000ad64: 019ba223 sw s9,4(s7) -8000ad68: 0fb12623 sw s11,236(sp) -8000ad6c: 0f612423 sw s6,232(sp) -8000ad70: 008b8b93 addi s7,s7,8 -8000ad74: fd6adee3 bge s5,s6,8000ad50 <_svfprintf_r+0x15dc> -8000ad78: 0e410613 addi a2,sp,228 -8000ad7c: 000d0593 mv a1,s10 -8000ad80: 000a0513 mv a0,s4 -8000ad84: 475030ef jal ra,8000e9f8 <__ssprint_r> -8000ad88: 00050463 beqz a0,8000ad90 <_svfprintf_r+0x161c> -8000ad8c: c11fe06f j 8000999c <_svfprintf_r+0x228> -8000ad90: 0ec12d83 lw s11,236(sp) -8000ad94: 0e812b03 lw s6,232(sp) -8000ad98: 10c10b93 addi s7,sp,268 -8000ad9c: fb5ff06f j 8000ad50 <_svfprintf_r+0x15dc> -8000ada0: 000c8913 mv s2,s9 -8000ada4: b25fe06f j 800098c8 <_svfprintf_r+0x154> -8000ada8: 00812583 lw a1,8(sp) -8000adac: 0e410613 addi a2,sp,228 -8000adb0: 000a0513 mv a0,s4 -8000adb4: 445030ef jal ra,8000e9f8 <__ssprint_r> -8000adb8: 00050463 beqz a0,8000adc0 <_svfprintf_r+0x164c> -8000adbc: be1fe06f j 8000999c <_svfprintf_r+0x228> -8000adc0: 0ec12d83 lw s11,236(sp) -8000adc4: 0e812b03 lw s6,232(sp) -8000adc8: 10c10b93 addi s7,sp,268 -8000adcc: b4dff06f j 8000a918 <_svfprintf_r+0x11a4> -8000add0: 00812583 lw a1,8(sp) -8000add4: 0e410613 addi a2,sp,228 -8000add8: 000a0513 mv a0,s4 -8000addc: 41d030ef jal ra,8000e9f8 <__ssprint_r> -8000ade0: 00050463 beqz a0,8000ade8 <_svfprintf_r+0x1674> -8000ade4: bb9fe06f j 8000999c <_svfprintf_r+0x228> -8000ade8: 0ec12d83 lw s11,236(sp) -8000adec: 0e812b03 lw s6,232(sp) -8000adf0: 10c10b93 addi s7,sp,268 -8000adf4: b51ff06f j 8000a944 <_svfprintf_r+0x11d0> -8000adf8: 03000793 li a5,48 -8000adfc: 1af107a3 sb a5,431(sp) -8000ae00: 1af10c93 addi s9,sp,431 -8000ae04: c81fe06f j 80009a84 <_svfprintf_r+0x310> -8000ae08: 20097793 andi a5,s2,512 -8000ae0c: 020796e3 bnez a5,8000b638 <_svfprintf_r+0x1ec4> -8000ae10: 00000d93 li s11,0 -8000ae14: c25fe06f j 80009a38 <_svfprintf_r+0x2c4> -8000ae18: 01412783 lw a5,20(sp) -8000ae1c: 0007a703 lw a4,0(a5) -8000ae20: 00478793 addi a5,a5,4 -8000ae24: 00f12a23 sw a5,20(sp) -8000ae28: 00072583 lw a1,0(a4) -8000ae2c: 00472603 lw a2,4(a4) -8000ae30: 00872683 lw a3,8(a4) -8000ae34: 00c72703 lw a4,12(a4) -8000ae38: 0eb12823 sw a1,240(sp) -8000ae3c: 0ec12a23 sw a2,244(sp) -8000ae40: 0ed12c23 sw a3,248(sp) -8000ae44: 0ee12e23 sw a4,252(sp) -8000ae48: e99fe06f j 80009ce0 <_svfprintf_r+0x56c> -8000ae4c: 00412603 lw a2,4(sp) -8000ae50: 0006a783 lw a5,0(a3) -8000ae54: 00e12a23 sw a4,20(sp) -8000ae58: 41f65693 srai a3,a2,0x1f -8000ae5c: 00c7a023 sw a2,0(a5) -8000ae60: 00d7a223 sw a3,4(a5) -8000ae64: 00048c93 mv s9,s1 -8000ae68: d81fe06f j 80009be8 <_svfprintf_r+0x474> -8000ae6c: 03000793 li a5,48 -8000ae70: 00296913 ori s2,s2,2 -8000ae74: 0cf10423 sb a5,200(sp) -8000ae78: 0d5104a3 sb s5,201(sp) -8000ae7c: bff97993 andi s3,s2,-1025 -8000ae80: 00200793 li a5,2 -8000ae84: bd1fe06f j 80009a54 <_svfprintf_r+0x2e0> -8000ae88: 04012783 lw a5,64(sp) -8000ae8c: 0004ce03 lbu t3,0(s1) -8000ae90: 00079463 bnez a5,8000ae98 <_svfprintf_r+0x1724> -8000ae94: a5dfe06f j 800098f0 <_svfprintf_r+0x17c> -8000ae98: 0007c783 lbu a5,0(a5) -8000ae9c: 00079463 bnez a5,8000aea4 <_svfprintf_r+0x1730> -8000aea0: a51fe06f j 800098f0 <_svfprintf_r+0x17c> -8000aea4: 40096913 ori s2,s2,1024 -8000aea8: a49fe06f j 800098f0 <_svfprintf_r+0x17c> -8000aeac: 00068b13 mv s6,a3 -8000aeb0: cf6048e3 bgtz s6,8000aba0 <_svfprintf_r+0x142c> -8000aeb4: d15ff06f j 8000abc8 <_svfprintf_r+0x1454> -8000aeb8: 00812583 lw a1,8(sp) -8000aebc: 0e410613 addi a2,sp,228 -8000aec0: 000a0513 mv a0,s4 -8000aec4: 335030ef jal ra,8000e9f8 <__ssprint_r> -8000aec8: 00050463 beqz a0,8000aed0 <_svfprintf_r+0x175c> -8000aecc: ad1fe06f j 8000999c <_svfprintf_r+0x228> -8000aed0: 0ec12703 lw a4,236(sp) -8000aed4: 10c10d13 addi s10,sp,268 -8000aed8: fb0ff06f j 8000a688 <_svfprintf_r+0xf14> -8000aedc: 0014ce03 lbu t3,1(s1) -8000aee0: 02096913 ori s2,s2,32 -8000aee4: 00148493 addi s1,s1,1 -8000aee8: a09fe06f j 800098f0 <_svfprintf_r+0x17c> -8000aeec: 0014ce03 lbu t3,1(s1) -8000aef0: 20096913 ori s2,s2,512 -8000aef4: 00148493 addi s1,s1,1 -8000aef8: 9f9fe06f j 800098f0 <_svfprintf_r+0x17c> -8000aefc: 02812503 lw a0,40(sp) -8000af00: 04000593 li a1,64 -8000af04: dfdf50ef jal ra,80000d00 <_malloc_r> -8000af08: 00812783 lw a5,8(sp) -8000af0c: 00a7a023 sw a0,0(a5) -8000af10: 00a7a823 sw a0,16(a5) -8000af14: 00051463 bnez a0,8000af1c <_svfprintf_r+0x17a8> -8000af18: 3380106f j 8000c250 <_svfprintf_r+0x2adc> -8000af1c: 00812703 lw a4,8(sp) -8000af20: 04000793 li a5,64 -8000af24: 00f72a23 sw a5,20(a4) -8000af28: 8d9fe06f j 80009800 <_svfprintf_r+0x8c> -8000af2c: 00600793 li a5,6 -8000af30: 000d8b13 mv s6,s11 -8000af34: 6db7e263 bltu a5,s11,8000b5f8 <_svfprintf_r+0x1e84> -8000af38: 800157b7 lui a5,0x80015 -8000af3c: 000b0993 mv s3,s6 -8000af40: 01712a23 sw s7,20(sp) -8000af44: 80878c93 addi s9,a5,-2040 # 80014808 <__BSS_END__+0xffffda90> -8000af48: 990ff06f j 8000a0d8 <_svfprintf_r+0x964> -8000af4c: 01000613 li a2,16 -8000af50: 0e812683 lw a3,232(sp) -8000af54: 63665663 bge a2,s6,8000b580 <_svfprintf_r+0x1e0c> -8000af58: 01000d93 li s11,16 -8000af5c: 00700a93 li s5,7 -8000af60: 00812b83 lw s7,8(sp) -8000af64: 00c0006f j 8000af70 <_svfprintf_r+0x17fc> -8000af68: ff0b0b13 addi s6,s6,-16 -8000af6c: 616dda63 bge s11,s6,8000b580 <_svfprintf_r+0x1e0c> -8000af70: 01070713 addi a4,a4,16 -8000af74: 00168693 addi a3,a3,1 -8000af78: 018d2023 sw s8,0(s10) -8000af7c: 01bd2223 sw s11,4(s10) -8000af80: 0ee12623 sw a4,236(sp) -8000af84: 0ed12423 sw a3,232(sp) -8000af88: 008d0d13 addi s10,s10,8 -8000af8c: fcdadee3 bge s5,a3,8000af68 <_svfprintf_r+0x17f4> -8000af90: 0e410613 addi a2,sp,228 -8000af94: 000b8593 mv a1,s7 -8000af98: 000a0513 mv a0,s4 -8000af9c: 25d030ef jal ra,8000e9f8 <__ssprint_r> -8000afa0: 00050463 beqz a0,8000afa8 <_svfprintf_r+0x1834> -8000afa4: 9f9fe06f j 8000999c <_svfprintf_r+0x228> -8000afa8: 0ec12703 lw a4,236(sp) -8000afac: 0e812683 lw a3,232(sp) -8000afb0: 10c10d13 addi s10,sp,268 -8000afb4: fb5ff06f j 8000af68 <_svfprintf_r+0x17f4> -8000afb8: 01c12783 lw a5,28(sp) -8000afbc: 02012b83 lw s7,32(sp) -8000afc0: 00912c23 sw s1,24(sp) -8000afc4: 00fc87b3 add a5,s9,a5 -8000afc8: 05212223 sw s2,68(sp) -8000afcc: 04812623 sw s0,76(sp) -8000afd0: 02412483 lw s1,36(sp) -8000afd4: 03312023 sw s3,32(sp) -8000afd8: 03912223 sw s9,36(sp) -8000afdc: 000d0693 mv a3,s10 -8000afe0: 00700b13 li s6,7 -8000afe4: 01000d93 li s11,16 -8000afe8: 04812903 lw s2,72(sp) -8000afec: 04012403 lw s0,64(sp) -8000aff0: 00812983 lw s3,8(sp) -8000aff4: 00078d13 mv s10,a5 -8000aff8: 080b8a63 beqz s7,8000b08c <_svfprintf_r+0x1918> -8000affc: 08049a63 bnez s1,8000b090 <_svfprintf_r+0x191c> -8000b000: fff40413 addi s0,s0,-1 -8000b004: fffb8b93 addi s7,s7,-1 -8000b008: 03c12783 lw a5,60(sp) -8000b00c: 01270733 add a4,a4,s2 -8000b010: 0126a223 sw s2,4(a3) -8000b014: 00f6a023 sw a5,0(a3) -8000b018: 0e812783 lw a5,232(sp) -8000b01c: 0ee12623 sw a4,236(sp) -8000b020: 00868693 addi a3,a3,8 -8000b024: 00178793 addi a5,a5,1 -8000b028: 0ef12423 sw a5,232(sp) -8000b02c: 0efb4c63 blt s6,a5,8000b124 <_svfprintf_r+0x19b0> -8000b030: 00044603 lbu a2,0(s0) -8000b034: 415d05b3 sub a1,s10,s5 -8000b038: 00060c93 mv s9,a2 -8000b03c: 00c5d463 bge a1,a2,8000b044 <_svfprintf_r+0x18d0> -8000b040: 00058c93 mv s9,a1 -8000b044: 03905663 blez s9,8000b070 <_svfprintf_r+0x18fc> -8000b048: 0e812603 lw a2,232(sp) -8000b04c: 01970733 add a4,a4,s9 -8000b050: 0156a023 sw s5,0(a3) -8000b054: 00160613 addi a2,a2,1 -8000b058: 0196a223 sw s9,4(a3) -8000b05c: 0ee12623 sw a4,236(sp) -8000b060: 0ec12423 sw a2,232(sp) -8000b064: 2ecb4463 blt s6,a2,8000b34c <_svfprintf_r+0x1bd8> -8000b068: 00044603 lbu a2,0(s0) -8000b06c: 00868693 addi a3,a3,8 -8000b070: fffcc593 not a1,s9 -8000b074: 41f5d593 srai a1,a1,0x1f -8000b078: 00bcf7b3 and a5,s9,a1 -8000b07c: 40f60cb3 sub s9,a2,a5 -8000b080: 01904c63 bgtz s9,8000b098 <_svfprintf_r+0x1924> -8000b084: 00ca8ab3 add s5,s5,a2 -8000b088: f60b9ae3 bnez s7,8000affc <_svfprintf_r+0x1888> -8000b08c: 62048e63 beqz s1,8000b6c8 <_svfprintf_r+0x1f54> -8000b090: fff48493 addi s1,s1,-1 -8000b094: f75ff06f j 8000b008 <_svfprintf_r+0x1894> -8000b098: 0e812603 lw a2,232(sp) -8000b09c: 019dc863 blt s11,s9,8000b0ac <_svfprintf_r+0x1938> -8000b0a0: 0580006f j 8000b0f8 <_svfprintf_r+0x1984> -8000b0a4: ff0c8c93 addi s9,s9,-16 -8000b0a8: 059dd863 bge s11,s9,8000b0f8 <_svfprintf_r+0x1984> -8000b0ac: 01070713 addi a4,a4,16 -8000b0b0: 00160613 addi a2,a2,1 -8000b0b4: 0186a023 sw s8,0(a3) -8000b0b8: 01b6a223 sw s11,4(a3) -8000b0bc: 0ee12623 sw a4,236(sp) -8000b0c0: 0ec12423 sw a2,232(sp) -8000b0c4: 00868693 addi a3,a3,8 -8000b0c8: fccb5ee3 bge s6,a2,8000b0a4 <_svfprintf_r+0x1930> -8000b0cc: 0e410613 addi a2,sp,228 -8000b0d0: 00098593 mv a1,s3 -8000b0d4: 000a0513 mv a0,s4 -8000b0d8: 121030ef jal ra,8000e9f8 <__ssprint_r> -8000b0dc: 00050463 beqz a0,8000b0e4 <_svfprintf_r+0x1970> -8000b0e0: 8bdfe06f j 8000999c <_svfprintf_r+0x228> -8000b0e4: ff0c8c93 addi s9,s9,-16 -8000b0e8: 0ec12703 lw a4,236(sp) -8000b0ec: 0e812603 lw a2,232(sp) -8000b0f0: 10c10693 addi a3,sp,268 -8000b0f4: fb9dcce3 blt s11,s9,8000b0ac <_svfprintf_r+0x1938> -8000b0f8: 01970733 add a4,a4,s9 -8000b0fc: 00160613 addi a2,a2,1 -8000b100: 0186a023 sw s8,0(a3) -8000b104: 0196a223 sw s9,4(a3) -8000b108: 0ee12623 sw a4,236(sp) -8000b10c: 0ec12423 sw a2,232(sp) -8000b110: 66cb4863 blt s6,a2,8000b780 <_svfprintf_r+0x200c> -8000b114: 00044603 lbu a2,0(s0) -8000b118: 00868693 addi a3,a3,8 -8000b11c: 00ca8ab3 add s5,s5,a2 -8000b120: f69ff06f j 8000b088 <_svfprintf_r+0x1914> -8000b124: 0e410613 addi a2,sp,228 -8000b128: 00098593 mv a1,s3 -8000b12c: 000a0513 mv a0,s4 -8000b130: 0c9030ef jal ra,8000e9f8 <__ssprint_r> -8000b134: 00050463 beqz a0,8000b13c <_svfprintf_r+0x19c8> -8000b138: 865fe06f j 8000999c <_svfprintf_r+0x228> -8000b13c: 0ec12703 lw a4,236(sp) -8000b140: 10c10693 addi a3,sp,268 -8000b144: eedff06f j 8000b030 <_svfprintf_r+0x18bc> -8000b148: 00812583 lw a1,8(sp) -8000b14c: 0e410613 addi a2,sp,228 -8000b150: 000a0513 mv a0,s4 -8000b154: 0a5030ef jal ra,8000e9f8 <__ssprint_r> -8000b158: 00050463 beqz a0,8000b160 <_svfprintf_r+0x19ec> -8000b15c: 841fe06f j 8000999c <_svfprintf_r+0x228> -8000b160: 0e812603 lw a2,232(sp) -8000b164: 0ec12d83 lw s11,236(sp) -8000b168: 11410d13 addi s10,sp,276 -8000b16c: 00160a93 addi s5,a2,1 -8000b170: 10c10b93 addi s7,sp,268 -8000b174: 865ff06f j 8000a9d8 <_svfprintf_r+0x1264> -8000b178: 0e812683 lw a3,232(sp) -8000b17c: 800155b7 lui a1,0x80015 -8000b180: 81058593 addi a1,a1,-2032 # 80014810 <__BSS_END__+0xffffda98> -8000b184: 00bd2023 sw a1,0(s10) -8000b188: 00170713 addi a4,a4,1 -8000b18c: 00100593 li a1,1 -8000b190: 00168693 addi a3,a3,1 -8000b194: 00bd2223 sw a1,4(s10) -8000b198: 0ee12623 sw a4,236(sp) -8000b19c: 0ed12423 sw a3,232(sp) -8000b1a0: 00700593 li a1,7 -8000b1a4: 008d0d13 addi s10,s10,8 -8000b1a8: 06d5ce63 blt a1,a3,8000b224 <_svfprintf_r+0x1ab0> -8000b1ac: 26061a63 bnez a2,8000b420 <_svfprintf_r+0x1cac> -8000b1b0: 01c12783 lw a5,28(sp) -8000b1b4: 00197693 andi a3,s2,1 -8000b1b8: 00f6e6b3 or a3,a3,a5 -8000b1bc: 00069463 bnez a3,8000b1c4 <_svfprintf_r+0x1a50> -8000b1c0: ff9fe06f j 8000a1b8 <_svfprintf_r+0xa44> -8000b1c4: 03412683 lw a3,52(sp) -8000b1c8: 02c12783 lw a5,44(sp) -8000b1cc: 00700613 li a2,7 -8000b1d0: 00dd2023 sw a3,0(s10) -8000b1d4: 0e812683 lw a3,232(sp) -8000b1d8: 00f70733 add a4,a4,a5 -8000b1dc: 00fd2223 sw a5,4(s10) -8000b1e0: 00168693 addi a3,a3,1 -8000b1e4: 0ee12623 sw a4,236(sp) -8000b1e8: 0ed12423 sw a3,232(sp) -8000b1ec: 008d0893 addi a7,s10,8 -8000b1f0: 48d64c63 blt a2,a3,8000b688 <_svfprintf_r+0x1f14> -8000b1f4: 01c12783 lw a5,28(sp) -8000b1f8: 00168693 addi a3,a3,1 -8000b1fc: 0198a023 sw s9,0(a7) -8000b200: 00e78733 add a4,a5,a4 -8000b204: 00f8a223 sw a5,4(a7) -8000b208: 0ee12623 sw a4,236(sp) -8000b20c: 0ed12423 sw a3,232(sp) -8000b210: 00700793 li a5,7 -8000b214: 00888d13 addi s10,a7,8 -8000b218: 00d7c463 blt a5,a3,8000b220 <_svfprintf_r+0x1aac> -8000b21c: f9dfe06f j 8000a1b8 <_svfprintf_r+0xa44> -8000b220: fdcff06f j 8000a9fc <_svfprintf_r+0x1288> -8000b224: 00812583 lw a1,8(sp) -8000b228: 0e410613 addi a2,sp,228 -8000b22c: 000a0513 mv a0,s4 -8000b230: 7c8030ef jal ra,8000e9f8 <__ssprint_r> -8000b234: 00050463 beqz a0,8000b23c <_svfprintf_r+0x1ac8> -8000b238: f64fe06f j 8000999c <_svfprintf_r+0x228> -8000b23c: 0cc12603 lw a2,204(sp) -8000b240: 0ec12703 lw a4,236(sp) -8000b244: 10c10d13 addi s10,sp,268 -8000b248: f65ff06f j 8000b1ac <_svfprintf_r+0x1a38> -8000b24c: 1b010c93 addi s9,sp,432 -8000b250: 00000793 li a5,0 -8000b254: 4009f913 andi s2,s3,1024 -8000b258: 00912823 sw s1,16(sp) -8000b25c: 01312c23 sw s3,24(sp) -8000b260: 0ff00b13 li s6,255 -8000b264: 000c8993 mv s3,s9 -8000b268: 02612023 sw t1,32(sp) -8000b26c: 000a0c93 mv s9,s4 -8000b270: 04012483 lw s1,64(sp) -8000b274: 000d8a13 mv s4,s11 -8000b278: 000d0d93 mv s11,s10 -8000b27c: 00040d13 mv s10,s0 -8000b280: 00078413 mv s0,a5 -8000b284: 0240006f j 8000b2a8 <_svfprintf_r+0x1b34> -8000b288: 00a00613 li a2,10 -8000b28c: 00000693 li a3,0 -8000b290: 000b8513 mv a0,s7 -8000b294: 000a0593 mv a1,s4 -8000b298: 50d040ef jal ra,8000ffa4 <__udivdi3> -8000b29c: 540a0863 beqz s4,8000b7ec <_svfprintf_r+0x2078> -8000b2a0: 00050b93 mv s7,a0 -8000b2a4: 00058a13 mv s4,a1 -8000b2a8: 00a00613 li a2,10 -8000b2ac: 00000693 li a3,0 -8000b2b0: 000b8513 mv a0,s7 -8000b2b4: 000a0593 mv a1,s4 -8000b2b8: 120050ef jal ra,800103d8 <__umoddi3> -8000b2bc: 03050513 addi a0,a0,48 -8000b2c0: fea98fa3 sb a0,-1(s3) -8000b2c4: 00140413 addi s0,s0,1 -8000b2c8: fff98993 addi s3,s3,-1 -8000b2cc: fa090ee3 beqz s2,8000b288 <_svfprintf_r+0x1b14> -8000b2d0: 0004c683 lbu a3,0(s1) -8000b2d4: fad41ae3 bne s0,a3,8000b288 <_svfprintf_r+0x1b14> -8000b2d8: fb6408e3 beq s0,s6,8000b288 <_svfprintf_r+0x1b14> -8000b2dc: 4c0a1863 bnez s4,8000b7ac <_svfprintf_r+0x2038> -8000b2e0: 00900793 li a5,9 -8000b2e4: 4d77e463 bltu a5,s7,8000b7ac <_svfprintf_r+0x2038> -8000b2e8: 000c8a13 mv s4,s9 -8000b2ec: 00098c93 mv s9,s3 -8000b2f0: 01812983 lw s3,24(sp) -8000b2f4: 1b010793 addi a5,sp,432 -8000b2f8: 00812e23 sw s0,28(sp) -8000b2fc: 04912023 sw s1,64(sp) -8000b300: 000d0413 mv s0,s10 -8000b304: 02012303 lw t1,32(sp) -8000b308: 01012483 lw s1,16(sp) -8000b30c: 000d8d13 mv s10,s11 -8000b310: 41978b33 sub s6,a5,s9 -8000b314: 00098913 mv s2,s3 -8000b318: f6cfe06f j 80009a84 <_svfprintf_r+0x310> -8000b31c: 00812583 lw a1,8(sp) -8000b320: 0e410613 addi a2,sp,228 -8000b324: 000a0513 mv a0,s4 -8000b328: 6d0030ef jal ra,8000e9f8 <__ssprint_r> -8000b32c: 00050463 beqz a0,8000b334 <_svfprintf_r+0x1bc0> -8000b330: e6cfe06f j 8000999c <_svfprintf_r+0x228> -8000b334: 10c10d13 addi s10,sp,268 -8000b338: b00ff06f j 8000a638 <_svfprintf_r+0xec4> -8000b33c: 01670733 add a4,a4,s6 -8000b340: 00178793 addi a5,a5,1 -8000b344: 018d2023 sw s8,0(s10) -8000b348: e59fe06f j 8000a1a0 <_svfprintf_r+0xa2c> -8000b34c: 0e410613 addi a2,sp,228 -8000b350: 00098593 mv a1,s3 -8000b354: 000a0513 mv a0,s4 -8000b358: 6a0030ef jal ra,8000e9f8 <__ssprint_r> -8000b35c: 00050463 beqz a0,8000b364 <_svfprintf_r+0x1bf0> -8000b360: e3cfe06f j 8000999c <_svfprintf_r+0x228> -8000b364: 00044603 lbu a2,0(s0) -8000b368: 0ec12703 lw a4,236(sp) -8000b36c: 10c10693 addi a3,sp,268 -8000b370: d01ff06f j 8000b070 <_svfprintf_r+0x18fc> -8000b374: 0f012783 lw a5,240(sp) -8000b378: 0a010593 addi a1,sp,160 -8000b37c: 0b010513 addi a0,sp,176 -8000b380: 0af12823 sw a5,176(sp) -8000b384: 0f412783 lw a5,244(sp) -8000b388: 0a012023 sw zero,160(sp) -8000b38c: 0a012223 sw zero,164(sp) -8000b390: 0af12a23 sw a5,180(sp) -8000b394: 0f812783 lw a5,248(sp) -8000b398: 0a012423 sw zero,168(sp) -8000b39c: 0a012623 sw zero,172(sp) -8000b3a0: 0af12c23 sw a5,184(sp) -8000b3a4: 0fc12783 lw a5,252(sp) -8000b3a8: 0af12e23 sw a5,188(sp) -8000b3ac: 2cc060ef jal ra,80011678 <__letf2> -8000b3b0: 44054463 bltz a0,8000b7f8 <_svfprintf_r+0x2084> -8000b3b4: 0c714703 lbu a4,199(sp) -8000b3b8: 04700793 li a5,71 -8000b3bc: 2157d663 bge a5,s5,8000b5c8 <_svfprintf_r+0x1e54> -8000b3c0: 800147b7 lui a5,0x80014 -8000b3c4: 7d478c93 addi s9,a5,2004 # 800147d4 <__BSS_END__+0xffffda5c> -8000b3c8: 00012823 sw zero,16(sp) -8000b3cc: 02012223 sw zero,36(sp) -8000b3d0: 02012023 sw zero,32(sp) -8000b3d4: 00012c23 sw zero,24(sp) -8000b3d8: f7f97913 andi s2,s2,-129 -8000b3dc: 00300993 li s3,3 -8000b3e0: 00300b13 li s6,3 -8000b3e4: 00000313 li t1,0 -8000b3e8: 00070463 beqz a4,8000b3f0 <_svfprintf_r+0x1c7c> -8000b3ec: ebcfe06f j 80009aa8 <_svfprintf_r+0x334> -8000b3f0: cfdfe06f j 8000a0ec <_svfprintf_r+0x978> -8000b3f4: 01412783 lw a5,20(sp) -8000b3f8: 00048c93 mv s9,s1 -8000b3fc: 0007a783 lw a5,0(a5) -8000b400: 00e12a23 sw a4,20(sp) -8000b404: 00412703 lw a4,4(sp) -8000b408: 00e7a023 sw a4,0(a5) -8000b40c: fdcfe06f j 80009be8 <_svfprintf_r+0x474> -8000b410: 000c8513 mv a0,s9 -8000b414: a08fe0ef jal ra,8000961c -8000b418: 00050b13 mv s6,a0 -8000b41c: bd5fe06f j 80009ff0 <_svfprintf_r+0x87c> -8000b420: 03412683 lw a3,52(sp) -8000b424: 02c12783 lw a5,44(sp) -8000b428: 00700593 li a1,7 -8000b42c: 00dd2023 sw a3,0(s10) -8000b430: 0e812683 lw a3,232(sp) -8000b434: 00f70733 add a4,a4,a5 -8000b438: 00fd2223 sw a5,4(s10) -8000b43c: 00168693 addi a3,a3,1 -8000b440: 0ee12623 sw a4,236(sp) -8000b444: 0ed12423 sw a3,232(sp) -8000b448: 008d0893 addi a7,s10,8 -8000b44c: 22d5ce63 blt a1,a3,8000b688 <_svfprintf_r+0x1f14> -8000b450: da0652e3 bgez a2,8000b1f4 <_svfprintf_r+0x1a80> -8000b454: ff000593 li a1,-16 -8000b458: 40c00b33 neg s6,a2 -8000b45c: 2eb652e3 bge a2,a1,8000bf40 <_svfprintf_r+0x27cc> -8000b460: 01000b93 li s7,16 -8000b464: 00700a93 li s5,7 -8000b468: 00812d03 lw s10,8(sp) -8000b46c: 00c0006f j 8000b478 <_svfprintf_r+0x1d04> -8000b470: ff0b0b13 addi s6,s6,-16 -8000b474: 2d6bd6e3 bge s7,s6,8000bf40 <_svfprintf_r+0x27cc> -8000b478: 01070713 addi a4,a4,16 -8000b47c: 00168693 addi a3,a3,1 -8000b480: 0188a023 sw s8,0(a7) -8000b484: 0178a223 sw s7,4(a7) -8000b488: 0ee12623 sw a4,236(sp) -8000b48c: 0ed12423 sw a3,232(sp) -8000b490: 00888893 addi a7,a7,8 -8000b494: fcdadee3 bge s5,a3,8000b470 <_svfprintf_r+0x1cfc> -8000b498: 0e410613 addi a2,sp,228 -8000b49c: 000d0593 mv a1,s10 -8000b4a0: 000a0513 mv a0,s4 -8000b4a4: 554030ef jal ra,8000e9f8 <__ssprint_r> -8000b4a8: 00050463 beqz a0,8000b4b0 <_svfprintf_r+0x1d3c> -8000b4ac: cf0fe06f j 8000999c <_svfprintf_r+0x228> -8000b4b0: 0ec12703 lw a4,236(sp) -8000b4b4: 0e812683 lw a3,232(sp) -8000b4b8: 10c10893 addi a7,sp,268 -8000b4bc: fb5ff06f j 8000b470 <_svfprintf_r+0x1cfc> -8000b4c0: 00040693 mv a3,s0 -8000b4c4: 01812403 lw s0,24(sp) -8000b4c8: 001b0a93 addi s5,s6,1 -8000b4cc: 008b8793 addi a5,s7,8 -8000b4d0: 00dd8db3 add s11,s11,a3 -8000b4d4: 00dba223 sw a3,4(s7) -8000b4d8: 018ba023 sw s8,0(s7) -8000b4dc: 0fb12623 sw s11,236(sp) -8000b4e0: 0f512423 sw s5,232(sp) -8000b4e4: 00700693 li a3,7 -8000b4e8: c756c0e3 blt a3,s5,8000b148 <_svfprintf_r+0x19d4> -8000b4ec: 001a8a93 addi s5,s5,1 -8000b4f0: 00878d13 addi s10,a5,8 -8000b4f4: 00078b93 mv s7,a5 -8000b4f8: ce0ff06f j 8000a9d8 <_svfprintf_r+0x1264> -8000b4fc: 20097713 andi a4,s2,512 -8000b500: 16070263 beqz a4,8000b664 <_svfprintf_r+0x1ef0> -8000b504: 01412703 lw a4,20(sp) -8000b508: 00090993 mv s3,s2 -8000b50c: 00f12a23 sw a5,20(sp) -8000b510: 00070b83 lb s7,0(a4) -8000b514: 41fbdd93 srai s11,s7,0x1f -8000b518: 000d8713 mv a4,s11 -8000b51c: b69fe06f j 8000a084 <_svfprintf_r+0x910> -8000b520: 20097713 andi a4,s2,512 -8000b524: 12070663 beqz a4,8000b650 <_svfprintf_r+0x1edc> -8000b528: 00f12a23 sw a5,20(sp) -8000b52c: 0ffbfb93 andi s7,s7,255 -8000b530: 00000d93 li s11,0 -8000b534: 00090993 mv s3,s2 -8000b538: 00100793 li a5,1 -8000b53c: d18fe06f j 80009a54 <_svfprintf_r+0x2e0> -8000b540: 20097713 andi a4,s2,512 -8000b544: 10070063 beqz a4,8000b644 <_svfprintf_r+0x1ed0> -8000b548: 0ffbfb93 andi s7,s7,255 -8000b54c: 00000d93 li s11,0 -8000b550: 00f12a23 sw a5,20(sp) -8000b554: f81fe06f j 8000a4d4 <_svfprintf_r+0xd60> -8000b558: 0fc12783 lw a5,252(sp) -8000b55c: 1207d263 bgez a5,8000b680 <_svfprintf_r+0x1f0c> -8000b560: 02d00793 li a5,45 -8000b564: 0cf103a3 sb a5,199(sp) -8000b568: 02d00713 li a4,45 -8000b56c: 04700793 li a5,71 -8000b570: 4b57d463 bge a5,s5,8000ba18 <_svfprintf_r+0x22a4> -8000b574: 800147b7 lui a5,0x80014 -8000b578: 7dc78c93 addi s9,a5,2012 # 800147dc <__BSS_END__+0xffffda64> -8000b57c: e4dff06f j 8000b3c8 <_svfprintf_r+0x1c54> -8000b580: 01670733 add a4,a4,s6 -8000b584: 00168693 addi a3,a3,1 -8000b588: 018d2023 sw s8,0(s10) -8000b58c: 016d2223 sw s6,4(s10) -8000b590: 0ee12623 sw a4,236(sp) -8000b594: 0ed12423 sw a3,232(sp) -8000b598: 00700613 li a2,7 -8000b59c: 008d0d13 addi s10,s10,8 -8000b5a0: e4d65063 bge a2,a3,8000abe0 <_svfprintf_r+0x146c> -8000b5a4: 00812583 lw a1,8(sp) -8000b5a8: 0e410613 addi a2,sp,228 -8000b5ac: 000a0513 mv a0,s4 -8000b5b0: 448030ef jal ra,8000e9f8 <__ssprint_r> -8000b5b4: 00050463 beqz a0,8000b5bc <_svfprintf_r+0x1e48> -8000b5b8: be4fe06f j 8000999c <_svfprintf_r+0x228> -8000b5bc: 0ec12703 lw a4,236(sp) -8000b5c0: 10c10d13 addi s10,sp,268 -8000b5c4: e1cff06f j 8000abe0 <_svfprintf_r+0x146c> -8000b5c8: 800147b7 lui a5,0x80014 -8000b5cc: 7d078c93 addi s9,a5,2000 # 800147d0 <__BSS_END__+0xffffda58> -8000b5d0: df9ff06f j 8000b3c8 <_svfprintf_r+0x1c54> -8000b5d4: 00812583 lw a1,8(sp) -8000b5d8: 0e410613 addi a2,sp,228 -8000b5dc: 000a0513 mv a0,s4 -8000b5e0: 418030ef jal ra,8000e9f8 <__ssprint_r> -8000b5e4: 00050463 beqz a0,8000b5ec <_svfprintf_r+0x1e78> -8000b5e8: bb4fe06f j 8000999c <_svfprintf_r+0x228> -8000b5ec: 0ec12703 lw a4,236(sp) -8000b5f0: 10c10d13 addi s10,sp,268 -8000b5f4: dd4ff06f j 8000abc8 <_svfprintf_r+0x1454> -8000b5f8: 00600b13 li s6,6 -8000b5fc: 93dff06f j 8000af38 <_svfprintf_r+0x17c4> -8000b600: 01c12683 lw a3,28(sp) -8000b604: 00dc87b3 add a5,s9,a3 -8000b608: 41668b33 sub s6,a3,s6 -8000b60c: 41578bb3 sub s7,a5,s5 -8000b610: e77b5663 bge s6,s7,8000ac7c <_svfprintf_r+0x1508> -8000b614: 000b0b93 mv s7,s6 -8000b618: e64ff06f j 8000ac7c <_svfprintf_r+0x1508> -8000b61c: 01412783 lw a5,20(sp) -8000b620: 00e12a23 sw a4,20(sp) -8000b624: 00412703 lw a4,4(sp) -8000b628: 0007a783 lw a5,0(a5) -8000b62c: 00048c93 mv s9,s1 -8000b630: 00e79023 sh a4,0(a5) -8000b634: db4fe06f j 80009be8 <_svfprintf_r+0x474> -8000b638: 0ffbfb93 andi s7,s7,255 -8000b63c: 00000d93 li s11,0 -8000b640: bf8fe06f j 80009a38 <_svfprintf_r+0x2c4> -8000b644: 00000d93 li s11,0 -8000b648: 00f12a23 sw a5,20(sp) -8000b64c: e89fe06f j 8000a4d4 <_svfprintf_r+0xd60> -8000b650: 00f12a23 sw a5,20(sp) -8000b654: 00000d93 li s11,0 -8000b658: 00090993 mv s3,s2 -8000b65c: 00100793 li a5,1 -8000b660: bf4fe06f j 80009a54 <_svfprintf_r+0x2e0> -8000b664: 01412703 lw a4,20(sp) -8000b668: 00090993 mv s3,s2 -8000b66c: 00f12a23 sw a5,20(sp) -8000b670: 00072b83 lw s7,0(a4) -8000b674: 41fbdd93 srai s11,s7,0x1f -8000b678: 000d8713 mv a4,s11 -8000b67c: a09fe06f j 8000a084 <_svfprintf_r+0x910> -8000b680: 0c714703 lbu a4,199(sp) -8000b684: ee9ff06f j 8000b56c <_svfprintf_r+0x1df8> -8000b688: 00812583 lw a1,8(sp) -8000b68c: 0e410613 addi a2,sp,228 -8000b690: 000a0513 mv a0,s4 -8000b694: 364030ef jal ra,8000e9f8 <__ssprint_r> -8000b698: 00050463 beqz a0,8000b6a0 <_svfprintf_r+0x1f2c> -8000b69c: b00fe06f j 8000999c <_svfprintf_r+0x228> -8000b6a0: 0cc12603 lw a2,204(sp) -8000b6a4: 0ec12703 lw a4,236(sp) -8000b6a8: 0e812683 lw a3,232(sp) -8000b6ac: 10c10893 addi a7,sp,268 -8000b6b0: b40652e3 bgez a2,8000b1f4 <_svfprintf_r+0x1a80> -8000b6b4: da1ff06f j 8000b454 <_svfprintf_r+0x1ce0> -8000b6b8: 00600313 li t1,6 -8000b6bc: e88fe06f j 80009d44 <_svfprintf_r+0x5d0> -8000b6c0: 00090993 mv s3,s2 -8000b6c4: e7dfe06f j 8000a540 <_svfprintf_r+0xdcc> -8000b6c8: 02412c83 lw s9,36(sp) -8000b6cc: 01c12783 lw a5,28(sp) -8000b6d0: 04812023 sw s0,64(sp) -8000b6d4: 00068d13 mv s10,a3 -8000b6d8: 00fc86b3 add a3,s9,a5 -8000b6dc: 01812483 lw s1,24(sp) -8000b6e0: 04412903 lw s2,68(sp) -8000b6e4: 04c12403 lw s0,76(sp) -8000b6e8: 02012983 lw s3,32(sp) -8000b6ec: d156f263 bgeu a3,s5,8000abf0 <_svfprintf_r+0x147c> -8000b6f0: 00068a93 mv s5,a3 -8000b6f4: cfcff06f j 8000abf0 <_svfprintf_r+0x147c> -8000b6f8: 01812783 lw a5,24(sp) -8000b6fc: ffd00713 li a4,-3 -8000b700: 00e7c463 blt a5,a4,8000b708 <_svfprintf_r+0x1f94> -8000b704: 00f35a63 bge t1,a5,8000b718 <_svfprintf_r+0x1fa4> -8000b708: ffea8a93 addi s5,s5,-2 -8000b70c: fdfaf793 andi a5,s5,-33 -8000b710: 04f12623 sw a5,76(sp) -8000b714: f2cfe06f j 80009e40 <_svfprintf_r+0x6cc> -8000b718: 01c12703 lw a4,28(sp) -8000b71c: 01812783 lw a5,24(sp) -8000b720: 2ce7c463 blt a5,a4,8000b9e8 <_svfprintf_r+0x2274> -8000b724: 05812703 lw a4,88(sp) -8000b728: 00078b13 mv s6,a5 -8000b72c: 00177713 andi a4,a4,1 -8000b730: 00070663 beqz a4,8000b73c <_svfprintf_r+0x1fc8> -8000b734: 02c12703 lw a4,44(sp) -8000b738: 00e78b33 add s6,a5,a4 -8000b73c: 05812783 lw a5,88(sp) -8000b740: 4007f713 andi a4,a5,1024 -8000b744: 00070663 beqz a4,8000b750 <_svfprintf_r+0x1fdc> -8000b748: 01812783 lw a5,24(sp) -8000b74c: 1af048e3 bgtz a5,8000c0fc <_svfprintf_r+0x2988> -8000b750: fffb4993 not s3,s6 -8000b754: 41f9d993 srai s3,s3,0x1f -8000b758: 013b79b3 and s3,s6,s3 -8000b75c: 06700a93 li s5,103 -8000b760: 02012223 sw zero,36(sp) -8000b764: 02012023 sw zero,32(sp) -8000b768: fecfe06f j 80009f54 <_svfprintf_r+0x7e0> -8000b76c: 0c714703 lbu a4,199(sp) -8000b770: 00000313 li t1,0 -8000b774: 00070463 beqz a4,8000b77c <_svfprintf_r+0x2008> -8000b778: b30fe06f j 80009aa8 <_svfprintf_r+0x334> -8000b77c: 971fe06f j 8000a0ec <_svfprintf_r+0x978> -8000b780: 0e410613 addi a2,sp,228 -8000b784: 00098593 mv a1,s3 -8000b788: 000a0513 mv a0,s4 -8000b78c: 26c030ef jal ra,8000e9f8 <__ssprint_r> -8000b790: 00050463 beqz a0,8000b798 <_svfprintf_r+0x2024> -8000b794: a08fe06f j 8000999c <_svfprintf_r+0x228> -8000b798: 00044603 lbu a2,0(s0) -8000b79c: 0ec12703 lw a4,236(sp) -8000b7a0: 10c10693 addi a3,sp,268 -8000b7a4: 00ca8ab3 add s5,s5,a2 -8000b7a8: 8e1ff06f j 8000b088 <_svfprintf_r+0x1914> -8000b7ac: 04812783 lw a5,72(sp) -8000b7b0: 03c12583 lw a1,60(sp) -8000b7b4: 00000413 li s0,0 -8000b7b8: 40f989b3 sub s3,s3,a5 -8000b7bc: 00078613 mv a2,a5 -8000b7c0: 00098513 mv a0,s3 -8000b7c4: ee5fd0ef jal ra,800096a8 -8000b7c8: 0014c803 lbu a6,1(s1) -8000b7cc: 00a00613 li a2,10 -8000b7d0: 00000693 li a3,0 -8000b7d4: 01003833 snez a6,a6 -8000b7d8: 000b8513 mv a0,s7 -8000b7dc: 000a0593 mv a1,s4 -8000b7e0: 010484b3 add s1,s1,a6 -8000b7e4: 7c0040ef jal ra,8000ffa4 <__udivdi3> -8000b7e8: ab9ff06f j 8000b2a0 <_svfprintf_r+0x1b2c> -8000b7ec: 00900793 li a5,9 -8000b7f0: ab77e8e3 bltu a5,s7,8000b2a0 <_svfprintf_r+0x1b2c> -8000b7f4: af5ff06f j 8000b2e8 <_svfprintf_r+0x1b74> -8000b7f8: 02d00793 li a5,45 -8000b7fc: 0cf103a3 sb a5,199(sp) -8000b800: 02d00713 li a4,45 -8000b804: bb5ff06f j 8000b3b8 <_svfprintf_r+0x1c44> -8000b808: 00812583 lw a1,8(sp) -8000b80c: 0e410613 addi a2,sp,228 -8000b810: 000a0513 mv a0,s4 -8000b814: 1e4030ef jal ra,8000e9f8 <__ssprint_r> -8000b818: 00050463 beqz a0,8000b820 <_svfprintf_r+0x20ac> -8000b81c: 980fe06f j 8000999c <_svfprintf_r+0x228> -8000b820: 0cc12b03 lw s6,204(sp) -8000b824: 0ec12703 lw a4,236(sp) -8000b828: 10c10d13 addi s10,sp,268 -8000b82c: c08ff06f j 8000ac34 <_svfprintf_r+0x14c0> -8000b830: 0b010993 addi s3,sp,176 -8000b834: 00030693 mv a3,t1 -8000b838: 0cc10713 addi a4,sp,204 -8000b83c: 0dc10813 addi a6,sp,220 -8000b840: 0d010793 addi a5,sp,208 -8000b844: 00300613 li a2,3 -8000b848: 00098593 mv a1,s3 -8000b84c: 000a0513 mv a0,s4 -8000b850: 04612223 sw t1,68(sp) -8000b854: 0a512823 sw t0,176(sp) -8000b858: 02512223 sw t0,36(sp) -8000b85c: 0be12a23 sw t5,180(sp) -8000b860: 03e12023 sw t5,32(sp) -8000b864: 0bf12c23 sw t6,184(sp) -8000b868: 01f12e23 sw t6,28(sp) -8000b86c: 0bd12e23 sw t4,188(sp) -8000b870: 01d12c23 sw t4,24(sp) -8000b874: 934fb0ef jal ra,800069a8 <_ldtoa_r> -8000b878: 00054683 lbu a3,0(a0) -8000b87c: 03000713 li a4,48 -8000b880: 00050c93 mv s9,a0 -8000b884: 01812e83 lw t4,24(sp) -8000b888: 01c12f83 lw t6,28(sp) -8000b88c: 02012f03 lw t5,32(sp) -8000b890: 02412283 lw t0,36(sp) -8000b894: 04412303 lw t1,68(sp) -8000b898: 0a010b93 addi s7,sp,160 -8000b89c: 06e68c63 beq a3,a4,8000b914 <_svfprintf_r+0x21a0> -8000b8a0: 0cc12703 lw a4,204(sp) -8000b8a4: 00670b33 add s6,a4,t1 -8000b8a8: 016c8b33 add s6,s9,s6 -8000b8ac: 000b8593 mv a1,s7 -8000b8b0: 00098513 mv a0,s3 -8000b8b4: 00612c23 sw t1,24(sp) -8000b8b8: 0a512823 sw t0,176(sp) -8000b8bc: 0be12a23 sw t5,180(sp) -8000b8c0: 0bf12c23 sw t6,184(sp) -8000b8c4: 0bd12e23 sw t4,188(sp) -8000b8c8: 0a012023 sw zero,160(sp) -8000b8cc: 0a012223 sw zero,164(sp) -8000b8d0: 0a012423 sw zero,168(sp) -8000b8d4: 0a012623 sw zero,172(sp) -8000b8d8: 391050ef jal ra,80011468 <__eqtf2> -8000b8dc: 000b0713 mv a4,s6 -8000b8e0: 01812303 lw t1,24(sp) -8000b8e4: 00051463 bnez a0,8000b8ec <_svfprintf_r+0x2178> -8000b8e8: d28fe06f j 80009e10 <_svfprintf_r+0x69c> -8000b8ec: 0dc12703 lw a4,220(sp) -8000b8f0: 03000613 li a2,48 -8000b8f4: 01676463 bltu a4,s6,8000b8fc <_svfprintf_r+0x2188> -8000b8f8: d18fe06f j 80009e10 <_svfprintf_r+0x69c> -8000b8fc: 00170793 addi a5,a4,1 -8000b900: 0cf12e23 sw a5,220(sp) -8000b904: 00c70023 sb a2,0(a4) -8000b908: 0dc12703 lw a4,220(sp) -8000b90c: ff6768e3 bltu a4,s6,8000b8fc <_svfprintf_r+0x2188> -8000b910: d00fe06f j 80009e10 <_svfprintf_r+0x69c> -8000b914: 0a010b93 addi s7,sp,160 -8000b918: 000b8593 mv a1,s7 -8000b91c: 00098513 mv a0,s3 -8000b920: 04612223 sw t1,68(sp) -8000b924: 0a512823 sw t0,176(sp) -8000b928: 02512223 sw t0,36(sp) -8000b92c: 0be12a23 sw t5,180(sp) -8000b930: 03e12023 sw t5,32(sp) -8000b934: 0bf12c23 sw t6,184(sp) -8000b938: 01f12e23 sw t6,28(sp) -8000b93c: 0bd12e23 sw t4,188(sp) -8000b940: 01d12c23 sw t4,24(sp) -8000b944: 0a012023 sw zero,160(sp) -8000b948: 0a012223 sw zero,164(sp) -8000b94c: 0a012423 sw zero,168(sp) -8000b950: 0a012623 sw zero,172(sp) -8000b954: 315050ef jal ra,80011468 <__eqtf2> -8000b958: 01812e83 lw t4,24(sp) -8000b95c: 01c12f83 lw t6,28(sp) -8000b960: 02012f03 lw t5,32(sp) -8000b964: 02412283 lw t0,36(sp) -8000b968: 04412303 lw t1,68(sp) -8000b96c: f2050ae3 beqz a0,8000b8a0 <_svfprintf_r+0x212c> -8000b970: 00100713 li a4,1 -8000b974: 40670733 sub a4,a4,t1 -8000b978: 0ce12623 sw a4,204(sp) -8000b97c: f29ff06f j 8000b8a4 <_svfprintf_r+0x2130> -8000b980: 0c714703 lbu a4,199(sp) -8000b984: 01712a23 sw s7,20(sp) -8000b988: 02012223 sw zero,36(sp) -8000b98c: 02012023 sw zero,32(sp) -8000b990: 00012c23 sw zero,24(sp) -8000b994: 00030993 mv s3,t1 -8000b998: 00030b13 mv s6,t1 -8000b99c: 00000313 li t1,0 -8000b9a0: 00070463 beqz a4,8000b9a8 <_svfprintf_r+0x2234> -8000b9a4: 904fe06f j 80009aa8 <_svfprintf_r+0x334> -8000b9a8: f44fe06f j 8000a0ec <_svfprintf_r+0x978> -8000b9ac: 05812783 lw a5,88(sp) -8000b9b0: 0017f713 andi a4,a5,1 -8000b9b4: 01812783 lw a5,24(sp) -8000b9b8: 00676733 or a4,a4,t1 -8000b9bc: 00f054e3 blez a5,8000c1c4 <_svfprintf_r+0x2a50> -8000b9c0: 7c071263 bnez a4,8000c184 <_svfprintf_r+0x2a10> -8000b9c4: 01812b03 lw s6,24(sp) -8000b9c8: 06600a93 li s5,102 -8000b9cc: 05812783 lw a5,88(sp) -8000b9d0: 4007f713 andi a4,a5,1024 -8000b9d4: 72071663 bnez a4,8000c100 <_svfprintf_r+0x298c> -8000b9d8: fffb4993 not s3,s6 -8000b9dc: 41f9d993 srai s3,s3,0x1f -8000b9e0: 013b79b3 and s3,s6,s3 -8000b9e4: d7dff06f j 8000b760 <_svfprintf_r+0x1fec> -8000b9e8: 01c12783 lw a5,28(sp) -8000b9ec: 02c12703 lw a4,44(sp) -8000b9f0: 06700a93 li s5,103 -8000b9f4: 00e78b33 add s6,a5,a4 -8000b9f8: 01812783 lw a5,24(sp) -8000b9fc: fcf048e3 bgtz a5,8000b9cc <_svfprintf_r+0x2258> -8000ba00: 40fb0b33 sub s6,s6,a5 -8000ba04: 001b0b13 addi s6,s6,1 -8000ba08: fffb4993 not s3,s6 -8000ba0c: 41f9d993 srai s3,s3,0x1f -8000ba10: 013b79b3 and s3,s6,s3 -8000ba14: d4dff06f j 8000b760 <_svfprintf_r+0x1fec> -8000ba18: 800147b7 lui a5,0x80014 -8000ba1c: 7d878c93 addi s9,a5,2008 # 800147d8 <__BSS_END__+0xffffda60> -8000ba20: 9a9ff06f j 8000b3c8 <_svfprintf_r+0x1c54> -8000ba24: 00812583 lw a1,8(sp) -8000ba28: 0e410613 addi a2,sp,228 -8000ba2c: 000a0513 mv a0,s4 -8000ba30: 7c9020ef jal ra,8000e9f8 <__ssprint_r> -8000ba34: 00050463 beqz a0,8000ba3c <_svfprintf_r+0x22c8> -8000ba38: f65fd06f j 8000999c <_svfprintf_r+0x228> -8000ba3c: 0cc12b03 lw s6,204(sp) -8000ba40: 01c12783 lw a5,28(sp) -8000ba44: 0ec12703 lw a4,236(sp) -8000ba48: 10c10d13 addi s10,sp,268 -8000ba4c: 41678b33 sub s6,a5,s6 -8000ba50: a2cff06f j 8000ac7c <_svfprintf_r+0x1508> -8000ba54: 03000793 li a5,48 -8000ba58: 0cf10423 sb a5,200(sp) -8000ba5c: 05800793 li a5,88 -8000ba60: 0cf104a3 sb a5,201(sp) -8000ba64: 00296793 ori a5,s2,2 -8000ba68: 06300713 li a4,99 -8000ba6c: 04f12c23 sw a5,88(sp) -8000ba70: 00012823 sw zero,16(sp) -8000ba74: 14c10c93 addi s9,sp,332 -8000ba78: 4a674263 blt a4,t1,8000bf1c <_svfprintf_r+0x27a8> -8000ba7c: 0fc12e83 lw t4,252(sp) -8000ba80: fdfaf793 andi a5,s5,-33 -8000ba84: 04f12623 sw a5,76(sp) -8000ba88: 04012e23 sw zero,92(sp) -8000ba8c: 10296913 ori s2,s2,258 -8000ba90: 0f012283 lw t0,240(sp) -8000ba94: 0f412f03 lw t5,244(sp) -8000ba98: 0f812f83 lw t6,248(sp) -8000ba9c: 380ec863 bltz t4,8000be2c <_svfprintf_r+0x26b8> -8000baa0: 06100713 li a4,97 -8000baa4: 52ea8063 beq s5,a4,8000bfc4 <_svfprintf_r+0x2850> -8000baa8: 04100713 li a4,65 -8000baac: 00ea8463 beq s5,a4,8000bab4 <_svfprintf_r+0x2340> -8000bab0: ac0fe06f j 80009d70 <_svfprintf_r+0x5fc> -8000bab4: 0b010993 addi s3,sp,176 -8000bab8: 00098513 mv a0,s3 -8000babc: 04612a23 sw t1,84(sp) -8000bac0: 0a512823 sw t0,176(sp) -8000bac4: 0be12a23 sw t5,180(sp) -8000bac8: 0bf12c23 sw t6,184(sp) -8000bacc: 0bd12e23 sw t4,188(sp) -8000bad0: 6f8080ef jal ra,800141c8 <__trunctfdf2> -8000bad4: 0cc10613 addi a2,sp,204 -8000bad8: e2cfd0ef jal ra,80009104 -8000badc: 00058613 mv a2,a1 -8000bae0: 00050593 mv a1,a0 -8000bae4: 00098513 mv a0,s3 -8000bae8: 4d4080ef jal ra,80013fbc <__extenddftf2> -8000baec: 0b012703 lw a4,176(sp) -8000baf0: 09010793 addi a5,sp,144 -8000baf4: 0a010b93 addi s7,sp,160 -8000baf8: 08e12823 sw a4,144(sp) -8000bafc: 0b412703 lw a4,180(sp) -8000bb00: 08010613 addi a2,sp,128 -8000bb04: 00078593 mv a1,a5 -8000bb08: 08e12a23 sw a4,148(sp) -8000bb0c: 0b812703 lw a4,184(sp) -8000bb10: 000b8513 mv a0,s7 -8000bb14: 00f12e23 sw a5,28(sp) -8000bb18: 08e12c23 sw a4,152(sp) -8000bb1c: 0bc12703 lw a4,188(sp) -8000bb20: 04c12823 sw a2,80(sp) -8000bb24: 08012023 sw zero,128(sp) -8000bb28: 08e12e23 sw a4,156(sp) -8000bb2c: 3ffc0737 lui a4,0x3ffc0 -8000bb30: 08e12623 sw a4,140(sp) -8000bb34: 08012223 sw zero,132(sp) -8000bb38: 08012423 sw zero,136(sp) -8000bb3c: 481050ef jal ra,800117bc <__multf3> -8000bb40: 0a012783 lw a5,160(sp) -8000bb44: 0a412803 lw a6,164(sp) -8000bb48: 0a812e83 lw t4,168(sp) -8000bb4c: 0ac12f03 lw t5,172(sp) -8000bb50: 000b8593 mv a1,s7 -8000bb54: 00098513 mv a0,s3 -8000bb58: 0af12823 sw a5,176(sp) -8000bb5c: 04f12223 sw a5,68(sp) -8000bb60: 0b012a23 sw a6,180(sp) -8000bb64: 03012223 sw a6,36(sp) -8000bb68: 0bd12c23 sw t4,184(sp) -8000bb6c: 03d12023 sw t4,32(sp) -8000bb70: 0be12e23 sw t5,188(sp) -8000bb74: 01e12c23 sw t5,24(sp) -8000bb78: 0a012023 sw zero,160(sp) -8000bb7c: 0a012223 sw zero,164(sp) -8000bb80: 0a012423 sw zero,168(sp) -8000bb84: 0a012623 sw zero,172(sp) -8000bb88: 0e1050ef jal ra,80011468 <__eqtf2> -8000bb8c: 01812f03 lw t5,24(sp) -8000bb90: 02012e83 lw t4,32(sp) -8000bb94: 02412803 lw a6,36(sp) -8000bb98: 04412783 lw a5,68(sp) -8000bb9c: 05412303 lw t1,84(sp) -8000bba0: 00051663 bnez a0,8000bbac <_svfprintf_r+0x2438> -8000bba4: 00100713 li a4,1 -8000bba8: 0ce12623 sw a4,204(sp) -8000bbac: 80014737 lui a4,0x80014 -8000bbb0: 7f470713 addi a4,a4,2036 # 800147f4 <__BSS_END__+0xffffda7c> -8000bbb4: 04e12223 sw a4,68(sp) -8000bbb8: fff30b13 addi s6,t1,-1 -8000bbbc: 01912c23 sw s9,24(sp) -8000bbc0: 06912023 sw s1,96(sp) -8000bbc4: 07512223 sw s5,100(sp) -8000bbc8: 07a12a23 sw s10,116(sp) -8000bbcc: 07412c23 sw s4,120(sp) -8000bbd0: 07912e23 sw s9,124(sp) -8000bbd4: 07212423 sw s2,104(sp) -8000bbd8: 06812623 sw s0,108(sp) -8000bbdc: 06612823 sw t1,112(sp) -8000bbe0: 000b0c93 mv s9,s6 -8000bbe4: 00078d13 mv s10,a5 -8000bbe8: 00080d93 mv s11,a6 -8000bbec: 000e8a13 mv s4,t4 -8000bbf0: 000f0a93 mv s5,t5 -8000bbf4: 01c12483 lw s1,28(sp) -8000bbf8: 0540006f j 8000bc4c <_svfprintf_r+0x24d8> -8000bbfc: 000b8593 mv a1,s7 -8000bc00: 00098513 mv a0,s3 -8000bc04: 02c12223 sw a2,36(sp) -8000bc08: 03f12023 sw t6,32(sp) -8000bc0c: 00512e23 sw t0,28(sp) -8000bc10: 0a512a23 sw t0,180(sp) -8000bc14: 0bf12c23 sw t6,184(sp) -8000bc18: 0ac12e23 sw a2,188(sp) -8000bc1c: 0b212823 sw s2,176(sp) -8000bc20: 0a012023 sw zero,160(sp) -8000bc24: 0a012223 sw zero,164(sp) -8000bc28: 0a012423 sw zero,168(sp) -8000bc2c: 0a012623 sw zero,172(sp) -8000bc30: 039050ef jal ra,80011468 <__eqtf2> -8000bc34: fffc8c93 addi s9,s9,-1 -8000bc38: 01c12283 lw t0,28(sp) -8000bc3c: 02012f83 lw t6,32(sp) -8000bc40: 02412603 lw a2,36(sp) -8000bc44: 0e050463 beqz a0,8000bd2c <_svfprintf_r+0x25b8> -8000bc48: 01612c23 sw s6,24(sp) -8000bc4c: 400307b7 lui a5,0x40030 -8000bc50: 00048613 mv a2,s1 -8000bc54: 000b8593 mv a1,s7 -8000bc58: 00098513 mv a0,s3 -8000bc5c: 08f12e23 sw a5,156(sp) -8000bc60: 0ba12023 sw s10,160(sp) -8000bc64: 0bb12223 sw s11,164(sp) -8000bc68: 0b412423 sw s4,168(sp) -8000bc6c: 0b512623 sw s5,172(sp) -8000bc70: 08012823 sw zero,144(sp) -8000bc74: 08012a23 sw zero,148(sp) -8000bc78: 08012c23 sw zero,152(sp) -8000bc7c: 341050ef jal ra,800117bc <__multf3> -8000bc80: 00098513 mv a0,s3 -8000bc84: 060080ef jal ra,80013ce4 <__fixtfsi> -8000bc88: 00050593 mv a1,a0 -8000bc8c: 00050413 mv s0,a0 -8000bc90: 00098513 mv a0,s3 -8000bc94: 0bc12b03 lw s6,188(sp) -8000bc98: 0b012a83 lw s5,176(sp) -8000bc9c: 0b412a03 lw s4,180(sp) -8000bca0: 0b812903 lw s2,184(sp) -8000bca4: 190080ef jal ra,80013e34 <__floatsitf> -8000bca8: 0b012783 lw a5,176(sp) -8000bcac: 05012603 lw a2,80(sp) -8000bcb0: 00048593 mv a1,s1 -8000bcb4: 08f12023 sw a5,128(sp) -8000bcb8: 0b412783 lw a5,180(sp) -8000bcbc: 000b8513 mv a0,s7 -8000bcc0: 09612e23 sw s6,156(sp) -8000bcc4: 08f12223 sw a5,132(sp) -8000bcc8: 0b812783 lw a5,184(sp) -8000bccc: 09512823 sw s5,144(sp) -8000bcd0: 09412a23 sw s4,148(sp) -8000bcd4: 08f12423 sw a5,136(sp) -8000bcd8: 0bc12783 lw a5,188(sp) -8000bcdc: 09212c23 sw s2,152(sp) -8000bce0: 08f12623 sw a5,140(sp) -8000bce4: 2e1060ef jal ra,800127c4 <__subtf3> -8000bce8: 04412783 lw a5,68(sp) -8000bcec: 01812703 lw a4,24(sp) -8000bcf0: 0a012903 lw s2,160(sp) -8000bcf4: 008787b3 add a5,a5,s0 -8000bcf8: 0007c783 lbu a5,0(a5) # 40030000 <_start-0x3ffd0000> -8000bcfc: 0a412283 lw t0,164(sp) -8000bd00: 0a812f83 lw t6,168(sp) -8000bd04: 0ac12603 lw a2,172(sp) -8000bd08: 00170b13 addi s6,a4,1 -8000bd0c: fefb0fa3 sb a5,-1(s6) -8000bd10: 05912a23 sw s9,84(sp) -8000bd14: fff00793 li a5,-1 -8000bd18: 00090d13 mv s10,s2 -8000bd1c: 00028d93 mv s11,t0 -8000bd20: 000f8a13 mv s4,t6 -8000bd24: 00060a93 mv s5,a2 -8000bd28: ecfc9ae3 bne s9,a5,8000bbfc <_svfprintf_r+0x2488> -8000bd2c: 07012303 lw t1,112(sp) -8000bd30: 00090393 mv t2,s2 -8000bd34: 3ffe06b7 lui a3,0x3ffe0 -8000bd38: 000b8593 mv a1,s7 -8000bd3c: 00098513 mv a0,s3 -8000bd40: 02612023 sw t1,32(sp) -8000bd44: 00812e23 sw s0,28(sp) -8000bd48: 06012483 lw s1,96(sp) -8000bd4c: 06412a83 lw s5,100(sp) -8000bd50: 0a712823 sw t2,176(sp) -8000bd54: 06712223 sw t2,100(sp) -8000bd58: 0a512a23 sw t0,180(sp) -8000bd5c: 06512023 sw t0,96(sp) -8000bd60: 0bf12c23 sw t6,184(sp) -8000bd64: 05f12823 sw t6,80(sp) -8000bd68: 0ac12e23 sw a2,188(sp) -8000bd6c: 02c12223 sw a2,36(sp) -8000bd70: 0a012023 sw zero,160(sp) -8000bd74: 0a012223 sw zero,164(sp) -8000bd78: 0a012423 sw zero,168(sp) -8000bd7c: 0ad12623 sw a3,172(sp) -8000bd80: 7b4050ef jal ra,80011534 <__getf2> -8000bd84: 07412d03 lw s10,116(sp) -8000bd88: 06c12403 lw s0,108(sp) -8000bd8c: 000b0d93 mv s11,s6 -8000bd90: 07812a03 lw s4,120(sp) -8000bd94: 07c12c83 lw s9,124(sp) -8000bd98: 06812903 lw s2,104(sp) -8000bd9c: 02012303 lw t1,32(sp) -8000bda0: 0aa04663 bgtz a0,8000be4c <_svfprintf_r+0x26d8> -8000bda4: 06412383 lw t2,100(sp) -8000bda8: 06012283 lw t0,96(sp) -8000bdac: 05012f83 lw t6,80(sp) -8000bdb0: 02412603 lw a2,36(sp) -8000bdb4: 3ffe06b7 lui a3,0x3ffe0 -8000bdb8: 000b8593 mv a1,s7 -8000bdbc: 00098513 mv a0,s3 -8000bdc0: 0a712823 sw t2,176(sp) -8000bdc4: 0a512a23 sw t0,180(sp) -8000bdc8: 0bf12c23 sw t6,184(sp) -8000bdcc: 0ac12e23 sw a2,188(sp) -8000bdd0: 0a012023 sw zero,160(sp) -8000bdd4: 0a012223 sw zero,164(sp) -8000bdd8: 0a012423 sw zero,168(sp) -8000bddc: 0ad12623 sw a3,172(sp) -8000bde0: 688050ef jal ra,80011468 <__eqtf2> -8000bde4: 02012303 lw t1,32(sp) -8000bde8: 00051863 bnez a0,8000bdf8 <_svfprintf_r+0x2684> -8000bdec: 01c12783 lw a5,28(sp) -8000bdf0: 0017fb13 andi s6,a5,1 -8000bdf4: 040b1c63 bnez s6,8000be4c <_svfprintf_r+0x26d8> -8000bdf8: 05412783 lw a5,84(sp) -8000bdfc: 03000613 li a2,48 -8000be00: 00178693 addi a3,a5,1 -8000be04: 00dd86b3 add a3,s11,a3 -8000be08: 0007c863 bltz a5,8000be18 <_svfprintf_r+0x26a4> -8000be0c: 001d8d93 addi s11,s11,1 -8000be10: fecd8fa3 sb a2,-1(s11) -8000be14: ffb69ce3 bne a3,s11,8000be0c <_svfprintf_r+0x2698> -8000be18: 419d87b3 sub a5,s11,s9 -8000be1c: 00f12e23 sw a5,28(sp) -8000be20: ff9fd06f j 80009e18 <_svfprintf_r+0x6a4> -8000be24: 00012823 sw zero,16(sp) -8000be28: 00070913 mv s2,a4 -8000be2c: 80000737 lui a4,0x80000 -8000be30: 02d00793 li a5,45 -8000be34: 01d74eb3 xor t4,a4,t4 -8000be38: 04f12e23 sw a5,92(sp) -8000be3c: c65ff06f j 8000baa0 <_svfprintf_r+0x232c> -8000be40: 800156b7 lui a3,0x80015 -8000be44: d3468d93 addi s11,a3,-716 # 80014d34 <__BSS_END__+0xffffdfbc> -8000be48: c64fe06f j 8000a2ac <_svfprintf_r+0xb38> -8000be4c: 01812783 lw a5,24(sp) -8000be50: 000d8693 mv a3,s11 -8000be54: 0cf12e23 sw a5,220(sp) -8000be58: 04412783 lw a5,68(sp) -8000be5c: fffdc603 lbu a2,-1(s11) -8000be60: 00f7c583 lbu a1,15(a5) -8000be64: 02b61063 bne a2,a1,8000be84 <_svfprintf_r+0x2710> -8000be68: 03000513 li a0,48 -8000be6c: fea68fa3 sb a0,-1(a3) -8000be70: 0dc12683 lw a3,220(sp) -8000be74: fff68793 addi a5,a3,-1 -8000be78: 0cf12e23 sw a5,220(sp) -8000be7c: fff6c603 lbu a2,-1(a3) -8000be80: fec586e3 beq a1,a2,8000be6c <_svfprintf_r+0x26f8> -8000be84: 00160593 addi a1,a2,1 -8000be88: 03900513 li a0,57 -8000be8c: 0ff5f593 andi a1,a1,255 -8000be90: 00a60663 beq a2,a0,8000be9c <_svfprintf_r+0x2728> -8000be94: feb68fa3 sb a1,-1(a3) -8000be98: f81ff06f j 8000be18 <_svfprintf_r+0x26a4> -8000be9c: 04412783 lw a5,68(sp) -8000bea0: 00a7c583 lbu a1,10(a5) -8000bea4: feb68fa3 sb a1,-1(a3) -8000bea8: f71ff06f j 8000be18 <_svfprintf_r+0x26a4> -8000beac: 00130b13 addi s6,t1,1 -8000beb0: 0b010993 addi s3,sp,176 -8000beb4: 0dc10813 addi a6,sp,220 -8000beb8: 0d010793 addi a5,sp,208 -8000bebc: 0cc10713 addi a4,sp,204 -8000bec0: 000b0693 mv a3,s6 -8000bec4: 00200613 li a2,2 -8000bec8: 00098593 mv a1,s3 -8000becc: 000a0513 mv a0,s4 -8000bed0: 04612223 sw t1,68(sp) -8000bed4: 0a512823 sw t0,176(sp) -8000bed8: 02512223 sw t0,36(sp) -8000bedc: 0be12a23 sw t5,180(sp) -8000bee0: 03e12023 sw t5,32(sp) -8000bee4: 0bf12c23 sw t6,184(sp) -8000bee8: 01f12e23 sw t6,28(sp) -8000beec: 0bd12e23 sw t4,188(sp) -8000bef0: 01d12c23 sw t4,24(sp) -8000bef4: ab5fa0ef jal ra,800069a8 <_ldtoa_r> -8000bef8: 01812e83 lw t4,24(sp) -8000befc: 01c12f83 lw t6,28(sp) -8000bf00: 02012f03 lw t5,32(sp) -8000bf04: 02412283 lw t0,36(sp) -8000bf08: 04412303 lw t1,68(sp) -8000bf0c: 00050c93 mv s9,a0 -8000bf10: 016c8b33 add s6,s9,s6 -8000bf14: 0a010b93 addi s7,sp,160 -8000bf18: 995ff06f j 8000b8ac <_svfprintf_r+0x2138> -8000bf1c: 00130593 addi a1,t1,1 -8000bf20: 000a0513 mv a0,s4 -8000bf24: 00612823 sw t1,16(sp) -8000bf28: dd9f40ef jal ra,80000d00 <_malloc_r> -8000bf2c: 00050c93 mv s9,a0 -8000bf30: 01012303 lw t1,16(sp) -8000bf34: 30050263 beqz a0,8000c238 <_svfprintf_r+0x2ac4> -8000bf38: 00a12823 sw a0,16(sp) -8000bf3c: b41ff06f j 8000ba7c <_svfprintf_r+0x2308> -8000bf40: 01670733 add a4,a4,s6 -8000bf44: 00168693 addi a3,a3,1 -8000bf48: 0188a023 sw s8,0(a7) -8000bf4c: 0168a223 sw s6,4(a7) -8000bf50: 0ee12623 sw a4,236(sp) -8000bf54: 0ed12423 sw a3,232(sp) -8000bf58: 00700613 li a2,7 -8000bf5c: 00888893 addi a7,a7,8 -8000bf60: a8d65a63 bge a2,a3,8000b1f4 <_svfprintf_r+0x1a80> -8000bf64: 00812583 lw a1,8(sp) -8000bf68: 0e410613 addi a2,sp,228 -8000bf6c: 000a0513 mv a0,s4 -8000bf70: 289020ef jal ra,8000e9f8 <__ssprint_r> -8000bf74: 00050463 beqz a0,8000bf7c <_svfprintf_r+0x2808> -8000bf78: a25fd06f j 8000999c <_svfprintf_r+0x228> -8000bf7c: 0ec12703 lw a4,236(sp) -8000bf80: 0e812683 lw a3,232(sp) -8000bf84: 10c10893 addi a7,sp,268 -8000bf88: a6cff06f j 8000b1f4 <_svfprintf_r+0x1a80> -8000bf8c: 006c8b33 add s6,s9,t1 -8000bf90: 0a010b93 addi s7,sp,160 -8000bf94: 919ff06f j 8000b8ac <_svfprintf_r+0x2138> -8000bf98: 03000793 li a5,48 -8000bf9c: 0cf10423 sb a5,200(sp) -8000bfa0: 07800793 li a5,120 -8000bfa4: abdff06f j 8000ba60 <_svfprintf_r+0x22ec> -8000bfa8: fff00793 li a5,-1 -8000bfac: 00f12223 sw a5,4(sp) -8000bfb0: a15fd06f j 800099c4 <_svfprintf_r+0x250> -8000bfb4: 00030463 beqz t1,8000bfbc <_svfprintf_r+0x2848> -8000bfb8: d8dfd06f j 80009d44 <_svfprintf_r+0x5d0> -8000bfbc: 00100313 li t1,1 -8000bfc0: d85fd06f j 80009d44 <_svfprintf_r+0x5d0> -8000bfc4: 0b010993 addi s3,sp,176 -8000bfc8: 00098513 mv a0,s3 -8000bfcc: 04612a23 sw t1,84(sp) -8000bfd0: 0a512823 sw t0,176(sp) -8000bfd4: 0be12a23 sw t5,180(sp) -8000bfd8: 0bf12c23 sw t6,184(sp) -8000bfdc: 0bd12e23 sw t4,188(sp) -8000bfe0: 1e8080ef jal ra,800141c8 <__trunctfdf2> -8000bfe4: 0cc10613 addi a2,sp,204 -8000bfe8: 91cfd0ef jal ra,80009104 -8000bfec: 00058613 mv a2,a1 -8000bff0: 00050593 mv a1,a0 -8000bff4: 00098513 mv a0,s3 -8000bff8: 7c5070ef jal ra,80013fbc <__extenddftf2> -8000bffc: 0b012703 lw a4,176(sp) -8000c000: 09010793 addi a5,sp,144 -8000c004: 0a010b93 addi s7,sp,160 -8000c008: 08e12823 sw a4,144(sp) -8000c00c: 0b412703 lw a4,180(sp) -8000c010: 08010613 addi a2,sp,128 -8000c014: 00078593 mv a1,a5 -8000c018: 08e12a23 sw a4,148(sp) -8000c01c: 0b812703 lw a4,184(sp) -8000c020: 000b8513 mv a0,s7 -8000c024: 00f12e23 sw a5,28(sp) -8000c028: 08e12c23 sw a4,152(sp) -8000c02c: 0bc12703 lw a4,188(sp) -8000c030: 04c12823 sw a2,80(sp) -8000c034: 08012023 sw zero,128(sp) -8000c038: 08e12e23 sw a4,156(sp) -8000c03c: 3ffc0737 lui a4,0x3ffc0 -8000c040: 08e12623 sw a4,140(sp) -8000c044: 08012223 sw zero,132(sp) -8000c048: 08012423 sw zero,136(sp) -8000c04c: 770050ef jal ra,800117bc <__multf3> -8000c050: 0a012783 lw a5,160(sp) -8000c054: 0a412803 lw a6,164(sp) -8000c058: 0a812e83 lw t4,168(sp) -8000c05c: 0ac12f03 lw t5,172(sp) -8000c060: 000b8593 mv a1,s7 -8000c064: 00098513 mv a0,s3 -8000c068: 0af12823 sw a5,176(sp) -8000c06c: 04f12223 sw a5,68(sp) -8000c070: 0b012a23 sw a6,180(sp) -8000c074: 03012223 sw a6,36(sp) -8000c078: 0bd12c23 sw t4,184(sp) -8000c07c: 03d12023 sw t4,32(sp) -8000c080: 0be12e23 sw t5,188(sp) -8000c084: 01e12c23 sw t5,24(sp) -8000c088: 0a012023 sw zero,160(sp) -8000c08c: 0a012223 sw zero,164(sp) -8000c090: 0a012423 sw zero,168(sp) -8000c094: 0a012623 sw zero,172(sp) -8000c098: 3d0050ef jal ra,80011468 <__eqtf2> -8000c09c: 01812f03 lw t5,24(sp) -8000c0a0: 02012e83 lw t4,32(sp) -8000c0a4: 02412803 lw a6,36(sp) -8000c0a8: 04412783 lw a5,68(sp) -8000c0ac: 05412303 lw t1,84(sp) -8000c0b0: 00051663 bnez a0,8000c0bc <_svfprintf_r+0x2948> -8000c0b4: 00100713 li a4,1 -8000c0b8: 0ce12623 sw a4,204(sp) -8000c0bc: 80014737 lui a4,0x80014 -8000c0c0: 7e070713 addi a4,a4,2016 # 800147e0 <__BSS_END__+0xffffda68> -8000c0c4: 04e12223 sw a4,68(sp) -8000c0c8: af1ff06f j 8000bbb8 <_svfprintf_r+0x2444> -8000c0cc: 0d610693 addi a3,sp,214 -8000c0d0: 00061863 bnez a2,8000c0e0 <_svfprintf_r+0x296c> -8000c0d4: 03000693 li a3,48 -8000c0d8: 0cd10b23 sb a3,214(sp) -8000c0dc: 0d710693 addi a3,sp,215 -8000c0e0: 1b010793 addi a5,sp,432 -8000c0e4: 40f68633 sub a2,a3,a5 -8000c0e8: 03070713 addi a4,a4,48 -8000c0ec: 0dd60793 addi a5,a2,221 -8000c0f0: 00e68023 sb a4,0(a3) -8000c0f4: 02f12c23 sw a5,56(sp) -8000c0f8: e19fd06f j 80009f10 <_svfprintf_r+0x79c> -8000c0fc: 06700a93 li s5,103 -8000c100: 04012583 lw a1,64(sp) -8000c104: 01812783 lw a5,24(sp) -8000c108: 02012223 sw zero,36(sp) -8000c10c: 0005c703 lbu a4,0(a1) -8000c110: 02012023 sw zero,32(sp) -8000c114: 0ff00613 li a2,255 -8000c118: 02c70e63 beq a4,a2,8000c154 <_svfprintf_r+0x29e0> -8000c11c: 02f75c63 bge a4,a5,8000c154 <_svfprintf_r+0x29e0> -8000c120: 0015c683 lbu a3,1(a1) -8000c124: 40e787b3 sub a5,a5,a4 -8000c128: 00068e63 beqz a3,8000c144 <_svfprintf_r+0x29d0> -8000c12c: 02012703 lw a4,32(sp) -8000c130: 00158593 addi a1,a1,1 -8000c134: 00170713 addi a4,a4,1 -8000c138: 02e12023 sw a4,32(sp) -8000c13c: 00068713 mv a4,a3 -8000c140: fd9ff06f j 8000c118 <_svfprintf_r+0x29a4> -8000c144: 02412683 lw a3,36(sp) -8000c148: 00168693 addi a3,a3,1 -8000c14c: 02d12223 sw a3,36(sp) -8000c150: fc9ff06f j 8000c118 <_svfprintf_r+0x29a4> -8000c154: 00f12c23 sw a5,24(sp) -8000c158: 02412703 lw a4,36(sp) -8000c15c: 02012783 lw a5,32(sp) -8000c160: 04b12023 sw a1,64(sp) -8000c164: 00e78733 add a4,a5,a4 -8000c168: 04812783 lw a5,72(sp) -8000c16c: 02f70733 mul a4,a4,a5 -8000c170: 01670b33 add s6,a4,s6 -8000c174: fffb4993 not s3,s6 -8000c178: 41f9d993 srai s3,s3,0x1f -8000c17c: 013b79b3 and s3,s6,s3 -8000c180: dd5fd06f j 80009f54 <_svfprintf_r+0x7e0> -8000c184: 02c12703 lw a4,44(sp) -8000c188: 06600a93 li s5,102 -8000c18c: 00e78b33 add s6,a5,a4 -8000c190: 006b0b33 add s6,s6,t1 -8000c194: 839ff06f j 8000b9cc <_svfprintf_r+0x2258> -8000c198: 01812783 lw a5,24(sp) -8000c19c: 00100713 li a4,1 -8000c1a0: 02d00693 li a3,45 -8000c1a4: 40f70733 sub a4,a4,a5 -8000c1a8: 0cd10aa3 sb a3,213(sp) -8000c1ac: cd5fd06f j 80009e80 <_svfprintf_r+0x70c> -8000c1b0: 05812783 lw a5,88(sp) -8000c1b4: 0017f713 andi a4,a5,1 -8000c1b8: 00071463 bnez a4,8000c1c0 <_svfprintf_r+0x2a4c> -8000c1bc: d75fd06f j 80009f30 <_svfprintf_r+0x7bc> -8000c1c0: d69fd06f j 80009f28 <_svfprintf_r+0x7b4> -8000c1c4: 00071a63 bnez a4,8000c1d8 <_svfprintf_r+0x2a64> -8000c1c8: 00100993 li s3,1 -8000c1cc: 06600a93 li s5,102 -8000c1d0: 00100b13 li s6,1 -8000c1d4: d8cff06f j 8000b760 <_svfprintf_r+0x1fec> -8000c1d8: 02c12783 lw a5,44(sp) -8000c1dc: 06600a93 li s5,102 -8000c1e0: 00178b13 addi s6,a5,1 -8000c1e4: 006b0b33 add s6,s6,t1 -8000c1e8: fffb4993 not s3,s6 -8000c1ec: 41f9d993 srai s3,s3,0x1f -8000c1f0: 013b79b3 and s3,s6,s3 -8000c1f4: d6cff06f j 8000b760 <_svfprintf_r+0x1fec> -8000c1f8: 000d0793 mv a5,s10 -8000c1fc: ad4ff06f j 8000b4d0 <_svfprintf_r+0x1d5c> -8000c200: 01412703 lw a4,20(sp) -8000c204: 00072d83 lw s11,0(a4) -8000c208: 00470713 addi a4,a4,4 -8000c20c: 000dd463 bgez s11,8000c214 <_svfprintf_r+0x2aa0> -8000c210: fff00d93 li s11,-1 -8000c214: 0014ce03 lbu t3,1(s1) -8000c218: 00e12a23 sw a4,20(sp) -8000c21c: 00078493 mv s1,a5 -8000c220: ed0fd06f j 800098f0 <_svfprintf_r+0x17c> -8000c224: 00200793 li a5,2 -8000c228: 02f12c23 sw a5,56(sp) -8000c22c: ce5fd06f j 80009f10 <_svfprintf_r+0x79c> -8000c230: 00030b13 mv s6,t1 -8000c234: cddff06f j 8000bf10 <_svfprintf_r+0x279c> -8000c238: 00812683 lw a3,8(sp) -8000c23c: 00c6d783 lhu a5,12(a3) -8000c240: 0407e713 ori a4,a5,64 -8000c244: 00070793 mv a5,a4 -8000c248: 00e69623 sh a4,12(a3) -8000c24c: f6cfd06f j 800099b8 <_svfprintf_r+0x244> -8000c250: 02812703 lw a4,40(sp) -8000c254: 00c00793 li a5,12 -8000c258: 00f72023 sw a5,0(a4) -8000c25c: fff00793 li a5,-1 -8000c260: 00f12223 sw a5,4(sp) -8000c264: f60fd06f j 800099c4 <_svfprintf_r+0x250> -8000c268: 00090993 mv s3,s2 -8000c26c: d21fd06f j 80009f8c <_svfprintf_r+0x818> -8000c270: 00090993 mv s3,s2 -8000c274: dfdfd06f j 8000a070 <_svfprintf_r+0x8fc> - -8000c278 <__sprint_r.part.0>: -8000c278: 0645a783 lw a5,100(a1) -8000c27c: fd010113 addi sp,sp,-48 -8000c280: 01612823 sw s6,16(sp) -8000c284: 02112623 sw ra,44(sp) -8000c288: 02812423 sw s0,40(sp) -8000c28c: 02912223 sw s1,36(sp) -8000c290: 03212023 sw s2,32(sp) -8000c294: 01312e23 sw s3,28(sp) -8000c298: 01412c23 sw s4,24(sp) -8000c29c: 01512a23 sw s5,20(sp) -8000c2a0: 01712623 sw s7,12(sp) -8000c2a4: 01812423 sw s8,8(sp) -8000c2a8: 01279713 slli a4,a5,0x12 -8000c2ac: 00060b13 mv s6,a2 -8000c2b0: 0a075863 bgez a4,8000c360 <__sprint_r.part.0+0xe8> -8000c2b4: 00862783 lw a5,8(a2) -8000c2b8: 00058913 mv s2,a1 -8000c2bc: 00050a13 mv s4,a0 -8000c2c0: 00062b83 lw s7,0(a2) -8000c2c4: fff00a93 li s5,-1 -8000c2c8: 08078863 beqz a5,8000c358 <__sprint_r.part.0+0xe0> -8000c2cc: 004bac03 lw s8,4(s7) -8000c2d0: 000ba403 lw s0,0(s7) -8000c2d4: 002c5993 srli s3,s8,0x2 -8000c2d8: 06098663 beqz s3,8000c344 <__sprint_r.part.0+0xcc> -8000c2dc: 00000493 li s1,0 -8000c2e0: 00c0006f j 8000c2ec <__sprint_r.part.0+0x74> -8000c2e4: 00440413 addi s0,s0,4 -8000c2e8: 04998c63 beq s3,s1,8000c340 <__sprint_r.part.0+0xc8> -8000c2ec: 00042583 lw a1,0(s0) -8000c2f0: 00090613 mv a2,s2 -8000c2f4: 000a0513 mv a0,s4 -8000c2f8: 009010ef jal ra,8000db00 <_fputwc_r> -8000c2fc: 00148493 addi s1,s1,1 -8000c300: ff5512e3 bne a0,s5,8000c2e4 <__sprint_r.part.0+0x6c> -8000c304: fff00513 li a0,-1 -8000c308: 02c12083 lw ra,44(sp) -8000c30c: 02812403 lw s0,40(sp) -8000c310: 000b2423 sw zero,8(s6) -8000c314: 000b2223 sw zero,4(s6) -8000c318: 02412483 lw s1,36(sp) -8000c31c: 02012903 lw s2,32(sp) -8000c320: 01c12983 lw s3,28(sp) -8000c324: 01812a03 lw s4,24(sp) -8000c328: 01412a83 lw s5,20(sp) -8000c32c: 01012b03 lw s6,16(sp) -8000c330: 00c12b83 lw s7,12(sp) -8000c334: 00812c03 lw s8,8(sp) -8000c338: 03010113 addi sp,sp,48 -8000c33c: 00008067 ret -8000c340: 008b2783 lw a5,8(s6) -8000c344: ffcc7c13 andi s8,s8,-4 -8000c348: 418787b3 sub a5,a5,s8 -8000c34c: 00fb2423 sw a5,8(s6) -8000c350: 008b8b93 addi s7,s7,8 -8000c354: f6079ce3 bnez a5,8000c2cc <__sprint_r.part.0+0x54> -8000c358: 00000513 li a0,0 -8000c35c: fadff06f j 8000c308 <__sprint_r.part.0+0x90> -8000c360: 0b1010ef jal ra,8000dc10 <__sfvwrite_r> -8000c364: fa5ff06f j 8000c308 <__sprint_r.part.0+0x90> - -8000c368 <__sprint_r>: -8000c368: 00862703 lw a4,8(a2) -8000c36c: 00070463 beqz a4,8000c374 <__sprint_r+0xc> -8000c370: f09ff06f j 8000c278 <__sprint_r.part.0> -8000c374: 00062223 sw zero,4(a2) -8000c378: 00000513 li a0,0 -8000c37c: 00008067 ret - -8000c380 <_vfiprintf_r>: -8000c380: ed010113 addi sp,sp,-304 -8000c384: 11312e23 sw s3,284(sp) -8000c388: 11412c23 sw s4,280(sp) -8000c38c: 11812423 sw s8,264(sp) -8000c390: 12112623 sw ra,300(sp) -8000c394: 12812423 sw s0,296(sp) -8000c398: 12912223 sw s1,292(sp) -8000c39c: 13212023 sw s2,288(sp) -8000c3a0: 11512a23 sw s5,276(sp) -8000c3a4: 11612823 sw s6,272(sp) -8000c3a8: 11712623 sw s7,268(sp) -8000c3ac: 11912223 sw s9,260(sp) -8000c3b0: 11a12023 sw s10,256(sp) -8000c3b4: 0fb12e23 sw s11,252(sp) -8000c3b8: 00d12823 sw a3,16(sp) -8000c3bc: 00050a13 mv s4,a0 -8000c3c0: 00058993 mv s3,a1 -8000c3c4: 00060c13 mv s8,a2 -8000c3c8: 00050663 beqz a0,8000c3d4 <_vfiprintf_r+0x54> -8000c3cc: 03852783 lw a5,56(a0) -8000c3d0: 1a0784e3 beqz a5,8000cd78 <_vfiprintf_r+0x9f8> -8000c3d4: 00c99703 lh a4,12(s3) -8000c3d8: 01071793 slli a5,a4,0x10 -8000c3dc: 0107d793 srli a5,a5,0x10 -8000c3e0: 01279693 slli a3,a5,0x12 -8000c3e4: 0206c663 bltz a3,8000c410 <_vfiprintf_r+0x90> -8000c3e8: 0649a683 lw a3,100(s3) -8000c3ec: 000027b7 lui a5,0x2 -8000c3f0: 00f767b3 or a5,a4,a5 -8000c3f4: ffffe737 lui a4,0xffffe -8000c3f8: fff70713 addi a4,a4,-1 # ffffdfff <__BSS_END__+0x7ffe7287> -8000c3fc: 00e6f733 and a4,a3,a4 -8000c400: 00f99623 sh a5,12(s3) -8000c404: 01079793 slli a5,a5,0x10 -8000c408: 06e9a223 sw a4,100(s3) -8000c40c: 0107d793 srli a5,a5,0x10 -8000c410: 0087f713 andi a4,a5,8 -8000c414: 18070263 beqz a4,8000c598 <_vfiprintf_r+0x218> -8000c418: 0109a703 lw a4,16(s3) -8000c41c: 16070e63 beqz a4,8000c598 <_vfiprintf_r+0x218> -8000c420: 01a7f793 andi a5,a5,26 -8000c424: 00a00713 li a4,10 -8000c428: 18e78a63 beq a5,a4,8000c5bc <_vfiprintf_r+0x23c> -8000c42c: 800157b7 lui a5,0x80015 -8000c430: d5478793 addi a5,a5,-684 # 80014d54 <__BSS_END__+0xffffdfdc> -8000c434: 80015b37 lui s6,0x80015 -8000c438: 04c10493 addi s1,sp,76 -8000c43c: 00f12a23 sw a5,20(sp) -8000c440: 80015937 lui s2,0x80015 -8000c444: ec0b0793 addi a5,s6,-320 # 80014ec0 <__BSS_END__+0xffffe148> -8000c448: 000c0b93 mv s7,s8 -8000c44c: 04912023 sw s1,64(sp) -8000c450: 04012423 sw zero,72(sp) -8000c454: 04012223 sw zero,68(sp) -8000c458: 00012c23 sw zero,24(sp) -8000c45c: 00012e23 sw zero,28(sp) -8000c460: 02012223 sw zero,36(sp) -8000c464: 02012023 sw zero,32(sp) -8000c468: 00012623 sw zero,12(sp) -8000c46c: 00f12223 sw a5,4(sp) -8000c470: ed090913 addi s2,s2,-304 # 80014ed0 <__BSS_END__+0xffffe158> -8000c474: 00048c13 mv s8,s1 -8000c478: 000bc783 lbu a5,0(s7) -8000c47c: 16078863 beqz a5,8000c5ec <_vfiprintf_r+0x26c> -8000c480: 02500713 li a4,37 -8000c484: 5ae78ae3 beq a5,a4,8000d238 <_vfiprintf_r+0xeb8> -8000c488: 000b8413 mv s0,s7 -8000c48c: 00c0006f j 8000c498 <_vfiprintf_r+0x118> -8000c490: 14e78863 beq a5,a4,8000c5e0 <_vfiprintf_r+0x260> -8000c494: 000c8413 mv s0,s9 -8000c498: 00144783 lbu a5,1(s0) -8000c49c: 00140c93 addi s9,s0,1 -8000c4a0: fe0798e3 bnez a5,8000c490 <_vfiprintf_r+0x110> -8000c4a4: 417c8d33 sub s10,s9,s7 -8000c4a8: 140d0263 beqz s10,8000c5ec <_vfiprintf_r+0x26c> -8000c4ac: 04812703 lw a4,72(sp) -8000c4b0: 04412783 lw a5,68(sp) -8000c4b4: 017c2023 sw s7,0(s8) # 1000 <_start-0x7ffff000> -8000c4b8: 00ed0733 add a4,s10,a4 -8000c4bc: 00178793 addi a5,a5,1 -8000c4c0: 01ac2223 sw s10,4(s8) -8000c4c4: 04e12423 sw a4,72(sp) -8000c4c8: 04f12223 sw a5,68(sp) -8000c4cc: 00700693 li a3,7 -8000c4d0: 008c0c13 addi s8,s8,8 -8000c4d4: 02f6d063 bge a3,a5,8000c4f4 <_vfiprintf_r+0x174> -8000c4d8: 50070ce3 beqz a4,8000d1f0 <_vfiprintf_r+0xe70> -8000c4dc: 04010613 addi a2,sp,64 -8000c4e0: 00098593 mv a1,s3 -8000c4e4: 000a0513 mv a0,s4 -8000c4e8: d91ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000c4ec: 10051c63 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000c4f0: 00048c13 mv s8,s1 -8000c4f4: 00c12703 lw a4,12(sp) -8000c4f8: 00144783 lbu a5,1(s0) -8000c4fc: 01a70733 add a4,a4,s10 -8000c500: 00e12623 sw a4,12(sp) -8000c504: 0e078463 beqz a5,8000c5ec <_vfiprintf_r+0x26c> -8000c508: 001c8b93 addi s7,s9,1 -8000c50c: 001cc703 lbu a4,1(s9) -8000c510: 02010da3 sb zero,59(sp) -8000c514: fff00a93 li s5,-1 -8000c518: 00000413 li s0,0 -8000c51c: 00000b13 li s6,0 -8000c520: 05a00c93 li s9,90 -8000c524: 00900d13 li s10,9 -8000c528: 02a00613 li a2,42 -8000c52c: 001b8b93 addi s7,s7,1 -8000c530: fe070793 addi a5,a4,-32 -8000c534: 1efce463 bltu s9,a5,8000c71c <_vfiprintf_r+0x39c> -8000c538: 01412683 lw a3,20(sp) -8000c53c: 00279793 slli a5,a5,0x2 -8000c540: 00d787b3 add a5,a5,a3 -8000c544: 0007a783 lw a5,0(a5) -8000c548: 00078067 jr a5 -8000c54c: 000a0513 mv a0,s4 -8000c550: fd8fb0ef jal ra,80007d28 <_localeconv_r> -8000c554: 00452783 lw a5,4(a0) -8000c558: 00078513 mv a0,a5 -8000c55c: 02f12023 sw a5,32(sp) -8000c560: 8bcfd0ef jal ra,8000961c -8000c564: 02a12223 sw a0,36(sp) -8000c568: 00050d93 mv s11,a0 -8000c56c: 000a0513 mv a0,s4 -8000c570: fb8fb0ef jal ra,80007d28 <_localeconv_r> -8000c574: 00852783 lw a5,8(a0) -8000c578: 02a00613 li a2,42 -8000c57c: 00f12e23 sw a5,28(sp) -8000c580: 540d96e3 bnez s11,8000d2cc <_vfiprintf_r+0xf4c> -8000c584: 000bc703 lbu a4,0(s7) -8000c588: fa5ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000c58c: 020b6b13 ori s6,s6,32 -8000c590: 000bc703 lbu a4,0(s7) -8000c594: f99ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000c598: 00098593 mv a1,s3 -8000c59c: 000a0513 mv a0,s4 -8000c5a0: d1df70ef jal ra,800042bc <__swsetup_r> -8000c5a4: 00050463 beqz a0,8000c5ac <_vfiprintf_r+0x22c> -8000c5a8: 03c0106f j 8000d5e4 <_vfiprintf_r+0x1264> -8000c5ac: 00c9d783 lhu a5,12(s3) -8000c5b0: 00a00713 li a4,10 -8000c5b4: 01a7f793 andi a5,a5,26 -8000c5b8: e6e79ae3 bne a5,a4,8000c42c <_vfiprintf_r+0xac> -8000c5bc: 00e99783 lh a5,14(s3) -8000c5c0: e607c6e3 bltz a5,8000c42c <_vfiprintf_r+0xac> -8000c5c4: 01012683 lw a3,16(sp) -8000c5c8: 000c0613 mv a2,s8 -8000c5cc: 00098593 mv a1,s3 -8000c5d0: 000a0513 mv a0,s4 -8000c5d4: 078010ef jal ra,8000d64c <__sbprintf> -8000c5d8: 00a12623 sw a0,12(sp) -8000c5dc: 0380006f j 8000c614 <_vfiprintf_r+0x294> -8000c5e0: 417c8d33 sub s10,s9,s7 -8000c5e4: f20d02e3 beqz s10,8000c508 <_vfiprintf_r+0x188> -8000c5e8: ec5ff06f j 8000c4ac <_vfiprintf_r+0x12c> -8000c5ec: 04812783 lw a5,72(sp) -8000c5f0: 00078a63 beqz a5,8000c604 <_vfiprintf_r+0x284> -8000c5f4: 04010613 addi a2,sp,64 -8000c5f8: 00098593 mv a1,s3 -8000c5fc: 000a0513 mv a0,s4 -8000c600: c79ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000c604: 00c9d783 lhu a5,12(s3) -8000c608: 0407f793 andi a5,a5,64 -8000c60c: 00078463 beqz a5,8000c614 <_vfiprintf_r+0x294> -8000c610: 7d50006f j 8000d5e4 <_vfiprintf_r+0x1264> -8000c614: 12c12083 lw ra,300(sp) -8000c618: 12812403 lw s0,296(sp) -8000c61c: 00c12503 lw a0,12(sp) -8000c620: 12412483 lw s1,292(sp) -8000c624: 12012903 lw s2,288(sp) -8000c628: 11c12983 lw s3,284(sp) -8000c62c: 11812a03 lw s4,280(sp) -8000c630: 11412a83 lw s5,276(sp) -8000c634: 11012b03 lw s6,272(sp) -8000c638: 10c12b83 lw s7,268(sp) -8000c63c: 10812c03 lw s8,264(sp) -8000c640: 10412c83 lw s9,260(sp) -8000c644: 10012d03 lw s10,256(sp) -8000c648: 0fc12d83 lw s11,252(sp) -8000c64c: 13010113 addi sp,sp,304 -8000c650: 00008067 ret -8000c654: 800147b7 lui a5,0x80014 -8000c658: 7f478793 addi a5,a5,2036 # 800147f4 <__BSS_END__+0xffffda7c> -8000c65c: 00f12c23 sw a5,24(sp) -8000c660: 020b7793 andi a5,s6,32 -8000c664: 52078863 beqz a5,8000cb94 <_vfiprintf_r+0x814> -8000c668: 01012783 lw a5,16(sp) -8000c66c: 00778693 addi a3,a5,7 -8000c670: ff86f693 andi a3,a3,-8 -8000c674: 0006ad83 lw s11,0(a3) -8000c678: 0046ae83 lw t4,4(a3) -8000c67c: 00868793 addi a5,a3,8 -8000c680: 00f12823 sw a5,16(sp) -8000c684: 001b7693 andi a3,s6,1 -8000c688: 00068663 beqz a3,8000c694 <_vfiprintf_r+0x314> -8000c68c: 01dde6b3 or a3,s11,t4 -8000c690: 420690e3 bnez a3,8000d2b0 <_vfiprintf_r+0xf30> -8000c694: bffb7c93 andi s9,s6,-1025 -8000c698: 00200713 li a4,2 -8000c69c: 02010da3 sb zero,59(sp) -8000c6a0: fff00693 li a3,-1 -8000c6a4: 66da8063 beq s5,a3,8000cd04 <_vfiprintf_r+0x984> -8000c6a8: 01dde6b3 or a3,s11,t4 -8000c6ac: f7fcfb13 andi s6,s9,-129 -8000c6b0: 1e0698e3 bnez a3,8000d0a0 <_vfiprintf_r+0xd20> -8000c6b4: 740a9463 bnez s5,8000cdfc <_vfiprintf_r+0xa7c> -8000c6b8: 340714e3 bnez a4,8000d200 <_vfiprintf_r+0xe80> -8000c6bc: 001cf793 andi a5,s9,1 -8000c6c0: 00f12423 sw a5,8(sp) -8000c6c4: 0f010d13 addi s10,sp,240 -8000c6c8: 380796e3 bnez a5,8000d254 <_vfiprintf_r+0xed4> -8000c6cc: 00812783 lw a5,8(sp) -8000c6d0: 000a8c93 mv s9,s5 -8000c6d4: 00fad463 bge s5,a5,8000c6dc <_vfiprintf_r+0x35c> -8000c6d8: 00078c93 mv s9,a5 -8000c6dc: 03b14783 lbu a5,59(sp) -8000c6e0: 00f037b3 snez a5,a5 -8000c6e4: 00fc8cb3 add s9,s9,a5 -8000c6e8: 0540006f j 8000c73c <_vfiprintf_r+0x3bc> -8000c6ec: 00000413 li s0,0 -8000c6f0: fd070693 addi a3,a4,-48 -8000c6f4: 001b8b93 addi s7,s7,1 -8000c6f8: 00241793 slli a5,s0,0x2 -8000c6fc: fffbc703 lbu a4,-1(s7) -8000c700: 00878433 add s0,a5,s0 -8000c704: 00141413 slli s0,s0,0x1 -8000c708: 00868433 add s0,a3,s0 -8000c70c: fd070693 addi a3,a4,-48 -8000c710: fedd72e3 bgeu s10,a3,8000c6f4 <_vfiprintf_r+0x374> -8000c714: fe070793 addi a5,a4,-32 -8000c718: e2fcf0e3 bgeu s9,a5,8000c538 <_vfiprintf_r+0x1b8> -8000c71c: ec0708e3 beqz a4,8000c5ec <_vfiprintf_r+0x26c> -8000c720: 00100793 li a5,1 -8000c724: 08e10623 sb a4,140(sp) -8000c728: 02010da3 sb zero,59(sp) -8000c72c: 00100c93 li s9,1 -8000c730: 00f12423 sw a5,8(sp) -8000c734: 08c10d13 addi s10,sp,140 -8000c738: 00000a93 li s5,0 -8000c73c: 002b7f93 andi t6,s6,2 -8000c740: 000f8463 beqz t6,8000c748 <_vfiprintf_r+0x3c8> -8000c744: 002c8c93 addi s9,s9,2 -8000c748: 04412703 lw a4,68(sp) -8000c74c: 084b7f13 andi t5,s6,132 -8000c750: 04812783 lw a5,72(sp) -8000c754: 00170693 addi a3,a4,1 -8000c758: 00068613 mv a2,a3 -8000c75c: 000f1663 bnez t5,8000c768 <_vfiprintf_r+0x3e8> -8000c760: 41940db3 sub s11,s0,s9 -8000c764: 15b042e3 bgtz s11,8000d0a8 <_vfiprintf_r+0xd28> -8000c768: 03b14583 lbu a1,59(sp) -8000c76c: 008c0693 addi a3,s8,8 -8000c770: 02058c63 beqz a1,8000c7a8 <_vfiprintf_r+0x428> -8000c774: 03b10713 addi a4,sp,59 -8000c778: 00178793 addi a5,a5,1 -8000c77c: 00ec2023 sw a4,0(s8) -8000c780: 00100713 li a4,1 -8000c784: 00ec2223 sw a4,4(s8) -8000c788: 04f12423 sw a5,72(sp) -8000c78c: 04c12223 sw a2,68(sp) -8000c790: 00700713 li a4,7 -8000c794: 0cc746e3 blt a4,a2,8000d060 <_vfiprintf_r+0xce0> -8000c798: 00060713 mv a4,a2 -8000c79c: 00068c13 mv s8,a3 -8000c7a0: 00160613 addi a2,a2,1 -8000c7a4: 00868693 addi a3,a3,8 -8000c7a8: 040f8e63 beqz t6,8000c804 <_vfiprintf_r+0x484> -8000c7ac: 03c10713 addi a4,sp,60 -8000c7b0: 00278793 addi a5,a5,2 -8000c7b4: 00ec2023 sw a4,0(s8) -8000c7b8: 00200713 li a4,2 -8000c7bc: 00ec2223 sw a4,4(s8) -8000c7c0: 04f12423 sw a5,72(sp) -8000c7c4: 04c12223 sw a2,68(sp) -8000c7c8: 00700713 li a4,7 -8000c7cc: 08c750e3 bge a4,a2,8000d04c <_vfiprintf_r+0xccc> -8000c7d0: 24078ae3 beqz a5,8000d224 <_vfiprintf_r+0xea4> -8000c7d4: 04010613 addi a2,sp,64 -8000c7d8: 00098593 mv a1,s3 -8000c7dc: 000a0513 mv a0,s4 -8000c7e0: 03e12423 sw t5,40(sp) -8000c7e4: a95ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000c7e8: e0051ee3 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000c7ec: 04412703 lw a4,68(sp) -8000c7f0: 04812783 lw a5,72(sp) -8000c7f4: 02812f03 lw t5,40(sp) -8000c7f8: 05410693 addi a3,sp,84 -8000c7fc: 00170613 addi a2,a4,1 -8000c800: 00048c13 mv s8,s1 -8000c804: 08000593 li a1,128 -8000c808: 66bf0063 beq t5,a1,8000ce68 <_vfiprintf_r+0xae8> -8000c80c: 00812583 lw a1,8(sp) -8000c810: 40ba8ab3 sub s5,s5,a1 -8000c814: 73504863 bgtz s5,8000cf44 <_vfiprintf_r+0xbc4> -8000c818: 00812703 lw a4,8(sp) -8000c81c: 01ac2023 sw s10,0(s8) -8000c820: 04c12223 sw a2,68(sp) -8000c824: 00f707b3 add a5,a4,a5 -8000c828: 00ec2223 sw a4,4(s8) -8000c82c: 04f12423 sw a5,72(sp) -8000c830: 00700713 li a4,7 -8000c834: 02c75263 bge a4,a2,8000c858 <_vfiprintf_r+0x4d8> -8000c838: 18078863 beqz a5,8000c9c8 <_vfiprintf_r+0x648> -8000c83c: 04010613 addi a2,sp,64 -8000c840: 00098593 mv a1,s3 -8000c844: 000a0513 mv a0,s4 -8000c848: a31ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000c84c: da051ce3 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000c850: 04812783 lw a5,72(sp) -8000c854: 00048693 mv a3,s1 -8000c858: 004b7313 andi t1,s6,4 -8000c85c: 00030663 beqz t1,8000c868 <_vfiprintf_r+0x4e8> -8000c860: 41940c33 sub s8,s0,s9 -8000c864: 17804e63 bgtz s8,8000c9e0 <_vfiprintf_r+0x660> -8000c868: 01945463 bge s0,s9,8000c870 <_vfiprintf_r+0x4f0> -8000c86c: 000c8413 mv s0,s9 -8000c870: 00c12703 lw a4,12(sp) -8000c874: 00870733 add a4,a4,s0 -8000c878: 00e12623 sw a4,12(sp) -8000c87c: 78079063 bnez a5,8000cffc <_vfiprintf_r+0xc7c> -8000c880: 04012223 sw zero,68(sp) -8000c884: 00048c13 mv s8,s1 -8000c888: bf1ff06f j 8000c478 <_vfiprintf_r+0xf8> -8000c88c: 020b7793 andi a5,s6,32 -8000c890: 010b6c93 ori s9,s6,16 -8000c894: 54079263 bnez a5,8000cdd8 <_vfiprintf_r+0xa58> -8000c898: 01012783 lw a5,16(sp) -8000c89c: 00478713 addi a4,a5,4 -8000c8a0: 01012783 lw a5,16(sp) -8000c8a4: 00000e93 li t4,0 -8000c8a8: 00e12823 sw a4,16(sp) -8000c8ac: 0007ad83 lw s11,0(a5) -8000c8b0: 00100713 li a4,1 -8000c8b4: de9ff06f j 8000c69c <_vfiprintf_r+0x31c> -8000c8b8: 080b6b13 ori s6,s6,128 -8000c8bc: 000bc703 lbu a4,0(s7) -8000c8c0: c6dff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000c8c4: 01012783 lw a5,16(sp) -8000c8c8: 02010da3 sb zero,59(sp) -8000c8cc: 0007ad03 lw s10,0(a5) -8000c8d0: 00478d93 addi s11,a5,4 -8000c8d4: 360d08e3 beqz s10,8000d444 <_vfiprintf_r+0x10c4> -8000c8d8: fff00793 li a5,-1 -8000c8dc: 22fa84e3 beq s5,a5,8000d304 <_vfiprintf_r+0xf84> -8000c8e0: 000a8613 mv a2,s5 -8000c8e4: 00000593 li a1,0 -8000c8e8: 000d0513 mv a0,s10 -8000c8ec: f40fb0ef jal ra,8000802c -8000c8f0: 4c050ae3 beqz a0,8000d5c4 <_vfiprintf_r+0x1244> -8000c8f4: 41a507b3 sub a5,a0,s10 -8000c8f8: 00f12423 sw a5,8(sp) -8000c8fc: 01b12823 sw s11,16(sp) -8000c900: 00000a93 li s5,0 -8000c904: dc9ff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000c908: 020b7793 andi a5,s6,32 -8000c90c: 010b6313 ori t1,s6,16 -8000c910: 46079a63 bnez a5,8000cd84 <_vfiprintf_r+0xa04> -8000c914: 01012783 lw a5,16(sp) -8000c918: 00478713 addi a4,a5,4 -8000c91c: 01012783 lw a5,16(sp) -8000c920: 00000e93 li t4,0 -8000c924: 00e12823 sw a4,16(sp) -8000c928: 0007ad83 lw s11,0(a5) -8000c92c: 4740006f j 8000cda0 <_vfiprintf_r+0xa20> -8000c930: 020b7793 andi a5,s6,32 -8000c934: 010b6c93 ori s9,s6,16 -8000c938: 46079c63 bnez a5,8000cdb0 <_vfiprintf_r+0xa30> -8000c93c: 01012783 lw a5,16(sp) -8000c940: 00478713 addi a4,a5,4 -8000c944: 01012783 lw a5,16(sp) -8000c948: 00e12823 sw a4,16(sp) -8000c94c: 0007ad83 lw s11,0(a5) -8000c950: 41fdde93 srai t4,s11,0x1f -8000c954: 000e8713 mv a4,t4 -8000c958: 38074263 bltz a4,8000ccdc <_vfiprintf_r+0x95c> -8000c95c: fff00713 li a4,-1 -8000c960: 00ea8a63 beq s5,a4,8000c974 <_vfiprintf_r+0x5f4> -8000c964: 01dde733 or a4,s11,t4 -8000c968: f7fcfb13 andi s6,s9,-129 -8000c96c: 080708e3 beqz a4,8000d1fc <_vfiprintf_r+0xe7c> -8000c970: 000b0c93 mv s9,s6 -8000c974: 1c0e94e3 bnez t4,8000d33c <_vfiprintf_r+0xfbc> -8000c978: 00900713 li a4,9 -8000c97c: 1db760e3 bltu a4,s11,8000d33c <_vfiprintf_r+0xfbc> -8000c980: 030d8793 addi a5,s11,48 -8000c984: 0ef107a3 sb a5,239(sp) -8000c988: 00100793 li a5,1 -8000c98c: 000c8b13 mv s6,s9 -8000c990: 00f12423 sw a5,8(sp) -8000c994: 0ef10d13 addi s10,sp,239 -8000c998: d35ff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000c99c: 01012703 lw a4,16(sp) -8000c9a0: 02010da3 sb zero,59(sp) -8000c9a4: 00100c93 li s9,1 -8000c9a8: 00072783 lw a5,0(a4) -8000c9ac: 00470713 addi a4,a4,4 -8000c9b0: 00e12823 sw a4,16(sp) -8000c9b4: 08f10623 sb a5,140(sp) -8000c9b8: 00100793 li a5,1 -8000c9bc: 00f12423 sw a5,8(sp) -8000c9c0: 08c10d13 addi s10,sp,140 -8000c9c4: d75ff06f j 8000c738 <_vfiprintf_r+0x3b8> -8000c9c8: 04012223 sw zero,68(sp) -8000c9cc: 004b7313 andi t1,s6,4 -8000c9d0: 7c030c63 beqz t1,8000d1a8 <_vfiprintf_r+0xe28> -8000c9d4: 41940c33 sub s8,s0,s9 -8000c9d8: 7d805863 blez s8,8000d1a8 <_vfiprintf_r+0xe28> -8000c9dc: 00048693 mv a3,s1 -8000c9e0: 01000713 li a4,16 -8000c9e4: 04412603 lw a2,68(sp) -8000c9e8: 3f875ae3 bge a4,s8,8000d5dc <_vfiprintf_r+0x125c> -8000c9ec: 01000d13 li s10,16 -8000c9f0: 00700d93 li s11,7 -8000c9f4: 0180006f j 8000ca0c <_vfiprintf_r+0x68c> -8000c9f8: 00260593 addi a1,a2,2 -8000c9fc: 00868693 addi a3,a3,8 -8000ca00: 00070613 mv a2,a4 -8000ca04: ff0c0c13 addi s8,s8,-16 -8000ca08: 058d5a63 bge s10,s8,8000ca5c <_vfiprintf_r+0x6dc> -8000ca0c: 00412583 lw a1,4(sp) -8000ca10: 01078793 addi a5,a5,16 -8000ca14: 00160713 addi a4,a2,1 -8000ca18: 00b6a023 sw a1,0(a3) -8000ca1c: 01a6a223 sw s10,4(a3) -8000ca20: 04f12423 sw a5,72(sp) -8000ca24: 04e12223 sw a4,68(sp) -8000ca28: fcedd8e3 bge s11,a4,8000c9f8 <_vfiprintf_r+0x678> -8000ca2c: 42078663 beqz a5,8000ce58 <_vfiprintf_r+0xad8> -8000ca30: 04010613 addi a2,sp,64 -8000ca34: 00098593 mv a1,s3 -8000ca38: 000a0513 mv a0,s4 -8000ca3c: 83dff0ef jal ra,8000c278 <__sprint_r.part.0> -8000ca40: bc0512e3 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000ca44: 04412603 lw a2,68(sp) -8000ca48: ff0c0c13 addi s8,s8,-16 -8000ca4c: 04812783 lw a5,72(sp) -8000ca50: 00048693 mv a3,s1 -8000ca54: 00160593 addi a1,a2,1 -8000ca58: fb8d4ae3 blt s10,s8,8000ca0c <_vfiprintf_r+0x68c> -8000ca5c: 00412703 lw a4,4(sp) -8000ca60: 018787b3 add a5,a5,s8 -8000ca64: 0186a223 sw s8,4(a3) -8000ca68: 00e6a023 sw a4,0(a3) -8000ca6c: 04f12423 sw a5,72(sp) -8000ca70: 04b12223 sw a1,68(sp) -8000ca74: 00700713 li a4,7 -8000ca78: deb758e3 bge a4,a1,8000c868 <_vfiprintf_r+0x4e8> -8000ca7c: 72078663 beqz a5,8000d1a8 <_vfiprintf_r+0xe28> -8000ca80: 04010613 addi a2,sp,64 -8000ca84: 00098593 mv a1,s3 -8000ca88: 000a0513 mv a0,s4 -8000ca8c: fecff0ef jal ra,8000c278 <__sprint_r.part.0> -8000ca90: b6051ae3 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000ca94: 04812783 lw a5,72(sp) -8000ca98: dd1ff06f j 8000c868 <_vfiprintf_r+0x4e8> -8000ca9c: 03b14783 lbu a5,59(sp) -8000caa0: 000bc703 lbu a4,0(s7) -8000caa4: a80794e3 bnez a5,8000c52c <_vfiprintf_r+0x1ac> -8000caa8: 02000793 li a5,32 -8000caac: 02f10da3 sb a5,59(sp) -8000cab0: a7dff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000cab4: 02b00793 li a5,43 -8000cab8: 02f10da3 sb a5,59(sp) -8000cabc: 000bc703 lbu a4,0(s7) -8000cac0: a6dff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000cac4: 01012783 lw a5,16(sp) -8000cac8: 000bc703 lbu a4,0(s7) -8000cacc: 0007a403 lw s0,0(a5) -8000cad0: 00478793 addi a5,a5,4 -8000cad4: 00f12823 sw a5,16(sp) -8000cad8: a4045ae3 bgez s0,8000c52c <_vfiprintf_r+0x1ac> -8000cadc: 40800433 neg s0,s0 -8000cae0: 004b6b13 ori s6,s6,4 -8000cae4: a49ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000cae8: 001b6b13 ori s6,s6,1 -8000caec: 000bc703 lbu a4,0(s7) -8000caf0: a3dff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000caf4: 000bc703 lbu a4,0(s7) -8000caf8: 001b8793 addi a5,s7,1 -8000cafc: 30c700e3 beq a4,a2,8000d5fc <_vfiprintf_r+0x127c> -8000cb00: fd070693 addi a3,a4,-48 -8000cb04: 00078b93 mv s7,a5 -8000cb08: 00000a93 li s5,0 -8000cb0c: a2dd62e3 bltu s10,a3,8000c530 <_vfiprintf_r+0x1b0> -8000cb10: 001b8b93 addi s7,s7,1 -8000cb14: 002a9793 slli a5,s5,0x2 -8000cb18: fffbc703 lbu a4,-1(s7) -8000cb1c: 01578ab3 add s5,a5,s5 -8000cb20: 001a9a93 slli s5,s5,0x1 -8000cb24: 00da8ab3 add s5,s5,a3 -8000cb28: fd070693 addi a3,a4,-48 -8000cb2c: fedd72e3 bgeu s10,a3,8000cb10 <_vfiprintf_r+0x790> -8000cb30: a01ff06f j 8000c530 <_vfiprintf_r+0x1b0> -8000cb34: 000bc703 lbu a4,0(s7) -8000cb38: 004b6b13 ori s6,s6,4 -8000cb3c: 9f1ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000cb40: 020b7793 andi a5,s6,32 -8000cb44: 28079863 bnez a5,8000cdd4 <_vfiprintf_r+0xa54> -8000cb48: 01012783 lw a5,16(sp) -8000cb4c: 010b7693 andi a3,s6,16 -8000cb50: 00478713 addi a4,a5,4 -8000cb54: 0007a783 lw a5,0(a5) -8000cb58: 2c0694e3 bnez a3,8000d620 <_vfiprintf_r+0x12a0> -8000cb5c: 040b7693 andi a3,s6,64 -8000cb60: 100682e3 beqz a3,8000d464 <_vfiprintf_r+0x10e4> -8000cb64: 01079d93 slli s11,a5,0x10 -8000cb68: 00e12823 sw a4,16(sp) -8000cb6c: 010ddd93 srli s11,s11,0x10 -8000cb70: 00000e93 li t4,0 -8000cb74: 000b0c93 mv s9,s6 -8000cb78: 00100713 li a4,1 -8000cb7c: b21ff06f j 8000c69c <_vfiprintf_r+0x31c> -8000cb80: 800147b7 lui a5,0x80014 -8000cb84: 7e078793 addi a5,a5,2016 # 800147e0 <__BSS_END__+0xffffda68> -8000cb88: 00f12c23 sw a5,24(sp) -8000cb8c: 020b7793 andi a5,s6,32 -8000cb90: ac079ce3 bnez a5,8000c668 <_vfiprintf_r+0x2e8> -8000cb94: 01012603 lw a2,16(sp) -8000cb98: 010b7693 andi a3,s6,16 -8000cb9c: 00062783 lw a5,0(a2) -8000cba0: 00460613 addi a2,a2,4 -8000cba4: 00c12823 sw a2,16(sp) -8000cba8: 66069863 bnez a3,8000d218 <_vfiprintf_r+0xe98> -8000cbac: 040b7693 andi a3,s6,64 -8000cbb0: 66068063 beqz a3,8000d210 <_vfiprintf_r+0xe90> -8000cbb4: 01079d93 slli s11,a5,0x10 -8000cbb8: 010ddd93 srli s11,s11,0x10 -8000cbbc: 00000e93 li t4,0 -8000cbc0: ac5ff06f j 8000c684 <_vfiprintf_r+0x304> -8000cbc4: 01012783 lw a5,16(sp) -8000cbc8: ffff8737 lui a4,0xffff8 -8000cbcc: 83074713 xori a4,a4,-2000 -8000cbd0: 0007ad83 lw s11,0(a5) -8000cbd4: 00478793 addi a5,a5,4 -8000cbd8: 00f12823 sw a5,16(sp) -8000cbdc: 800147b7 lui a5,0x80014 -8000cbe0: 7e078793 addi a5,a5,2016 # 800147e0 <__BSS_END__+0xffffda68> -8000cbe4: 02e11e23 sh a4,60(sp) -8000cbe8: 00000e93 li t4,0 -8000cbec: 002b6c93 ori s9,s6,2 -8000cbf0: 00f12c23 sw a5,24(sp) -8000cbf4: 00200713 li a4,2 -8000cbf8: aa5ff06f j 8000c69c <_vfiprintf_r+0x31c> -8000cbfc: 020b7793 andi a5,s6,32 -8000cc00: 18079063 bnez a5,8000cd80 <_vfiprintf_r+0xa00> -8000cc04: 01012783 lw a5,16(sp) -8000cc08: 010b7693 andi a3,s6,16 -8000cc0c: 00478713 addi a4,a5,4 -8000cc10: 0007a783 lw a5,0(a5) -8000cc14: 20069ae3 bnez a3,8000d628 <_vfiprintf_r+0x12a8> -8000cc18: 040b7693 andi a3,s6,64 -8000cc1c: 060684e3 beqz a3,8000d484 <_vfiprintf_r+0x1104> -8000cc20: 01079d93 slli s11,a5,0x10 -8000cc24: 010ddd93 srli s11,s11,0x10 -8000cc28: 00000e93 li t4,0 -8000cc2c: 000b0313 mv t1,s6 -8000cc30: 00e12823 sw a4,16(sp) -8000cc34: 16c0006f j 8000cda0 <_vfiprintf_r+0xa20> -8000cc38: 01012683 lw a3,16(sp) -8000cc3c: 020b7793 andi a5,s6,32 -8000cc40: 00468713 addi a4,a3,4 -8000cc44: 6a079263 bnez a5,8000d2e8 <_vfiprintf_r+0xf68> -8000cc48: 010b7793 andi a5,s6,16 -8000cc4c: 7e079063 bnez a5,8000d42c <_vfiprintf_r+0x10ac> -8000cc50: 040b7793 andi a5,s6,64 -8000cc54: 0e0798e3 bnez a5,8000d544 <_vfiprintf_r+0x11c4> -8000cc58: 200b7313 andi t1,s6,512 -8000cc5c: 7c030863 beqz t1,8000d42c <_vfiprintf_r+0x10ac> -8000cc60: 01012783 lw a5,16(sp) -8000cc64: 00e12823 sw a4,16(sp) -8000cc68: 00c12703 lw a4,12(sp) -8000cc6c: 0007a783 lw a5,0(a5) -8000cc70: 00e78023 sb a4,0(a5) -8000cc74: 805ff06f j 8000c478 <_vfiprintf_r+0xf8> -8000cc78: 000bc703 lbu a4,0(s7) -8000cc7c: 06c00793 li a5,108 -8000cc80: 78f70e63 beq a4,a5,8000d41c <_vfiprintf_r+0x109c> -8000cc84: 010b6b13 ori s6,s6,16 -8000cc88: 8a5ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000cc8c: 000bc703 lbu a4,0(s7) -8000cc90: 06800793 li a5,104 -8000cc94: 76f70c63 beq a4,a5,8000d40c <_vfiprintf_r+0x108c> -8000cc98: 040b6b13 ori s6,s6,64 -8000cc9c: 891ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000cca0: 020b7793 andi a5,s6,32 -8000cca4: 10079463 bnez a5,8000cdac <_vfiprintf_r+0xa2c> -8000cca8: 01012703 lw a4,16(sp) -8000ccac: 010b7793 andi a5,s6,16 -8000ccb0: 00470713 addi a4,a4,4 # ffff8004 <__BSS_END__+0x7ffe128c> -8000ccb4: 16079ee3 bnez a5,8000d630 <_vfiprintf_r+0x12b0> -8000ccb8: 040b7793 andi a5,s6,64 -8000ccbc: 7e078263 beqz a5,8000d4a0 <_vfiprintf_r+0x1120> -8000ccc0: 01012783 lw a5,16(sp) -8000ccc4: 00e12823 sw a4,16(sp) -8000ccc8: 000b0c93 mv s9,s6 -8000cccc: 00079d83 lh s11,0(a5) -8000ccd0: 41fdde93 srai t4,s11,0x1f -8000ccd4: 000e8713 mv a4,t4 -8000ccd8: c80752e3 bgez a4,8000c95c <_vfiprintf_r+0x5dc> -8000ccdc: 41b007b3 neg a5,s11 -8000cce0: 00f03733 snez a4,a5 -8000cce4: 41d00eb3 neg t4,t4 -8000cce8: 40ee8eb3 sub t4,t4,a4 -8000ccec: 02d00713 li a4,45 -8000ccf0: 02e10da3 sb a4,59(sp) -8000ccf4: fff00693 li a3,-1 -8000ccf8: 00078d93 mv s11,a5 -8000ccfc: 00100713 li a4,1 -8000cd00: 9ada94e3 bne s5,a3,8000c6a8 <_vfiprintf_r+0x328> -8000cd04: 00100693 li a3,1 -8000cd08: c6d706e3 beq a4,a3,8000c974 <_vfiprintf_r+0x5f4> -8000cd0c: 00200693 li a3,2 -8000cd10: 10d70063 beq a4,a3,8000ce10 <_vfiprintf_r+0xa90> -8000cd14: 0f010693 addi a3,sp,240 -8000cd18: 0080006f j 8000cd20 <_vfiprintf_r+0x9a0> -8000cd1c: 000d0693 mv a3,s10 -8000cd20: 01de9793 slli a5,t4,0x1d -8000cd24: 007df713 andi a4,s11,7 -8000cd28: 003ddd93 srli s11,s11,0x3 -8000cd2c: 03070713 addi a4,a4,48 -8000cd30: 01b7edb3 or s11,a5,s11 -8000cd34: 003ede93 srli t4,t4,0x3 -8000cd38: fee68fa3 sb a4,-1(a3) -8000cd3c: 01dde7b3 or a5,s11,t4 -8000cd40: fff68d13 addi s10,a3,-1 -8000cd44: fc079ce3 bnez a5,8000cd1c <_vfiprintf_r+0x99c> -8000cd48: 001cf793 andi a5,s9,1 -8000cd4c: 0e078c63 beqz a5,8000ce44 <_vfiprintf_r+0xac4> -8000cd50: 03000793 li a5,48 -8000cd54: 0ef70863 beq a4,a5,8000ce44 <_vfiprintf_r+0xac4> -8000cd58: ffe68693 addi a3,a3,-2 -8000cd5c: fefd0fa3 sb a5,-1(s10) -8000cd60: 0f010793 addi a5,sp,240 -8000cd64: 40d787b3 sub a5,a5,a3 -8000cd68: 00f12423 sw a5,8(sp) -8000cd6c: 000c8b13 mv s6,s9 -8000cd70: 00068d13 mv s10,a3 -8000cd74: 959ff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000cd78: e51f70ef jal ra,80004bc8 <__sinit> -8000cd7c: e58ff06f j 8000c3d4 <_vfiprintf_r+0x54> -8000cd80: 000b0313 mv t1,s6 -8000cd84: 01012783 lw a5,16(sp) -8000cd88: 00778713 addi a4,a5,7 -8000cd8c: ff877713 andi a4,a4,-8 -8000cd90: 00072d83 lw s11,0(a4) -8000cd94: 00472e83 lw t4,4(a4) -8000cd98: 00870793 addi a5,a4,8 -8000cd9c: 00f12823 sw a5,16(sp) -8000cda0: bff37c93 andi s9,t1,-1025 -8000cda4: 00000713 li a4,0 -8000cda8: 8f5ff06f j 8000c69c <_vfiprintf_r+0x31c> -8000cdac: 000b0c93 mv s9,s6 -8000cdb0: 01012783 lw a5,16(sp) -8000cdb4: 00778793 addi a5,a5,7 -8000cdb8: ff87f793 andi a5,a5,-8 -8000cdbc: 0047a703 lw a4,4(a5) -8000cdc0: 00878693 addi a3,a5,8 -8000cdc4: 00d12823 sw a3,16(sp) -8000cdc8: 0007ad83 lw s11,0(a5) -8000cdcc: 00070e93 mv t4,a4 -8000cdd0: b89ff06f j 8000c958 <_vfiprintf_r+0x5d8> -8000cdd4: 000b0c93 mv s9,s6 -8000cdd8: 01012783 lw a5,16(sp) -8000cddc: 00778713 addi a4,a5,7 -8000cde0: ff877713 andi a4,a4,-8 -8000cde4: 00870793 addi a5,a4,8 -8000cde8: 00072d83 lw s11,0(a4) -8000cdec: 00472e83 lw t4,4(a4) -8000cdf0: 00f12823 sw a5,16(sp) -8000cdf4: 00100713 li a4,1 -8000cdf8: 8a5ff06f j 8000c69c <_vfiprintf_r+0x31c> -8000cdfc: 00100693 li a3,1 -8000ce00: 7ad70863 beq a4,a3,8000d5b0 <_vfiprintf_r+0x1230> -8000ce04: 00200693 li a3,2 -8000ce08: 000b0c93 mv s9,s6 -8000ce0c: f0d714e3 bne a4,a3,8000cd14 <_vfiprintf_r+0x994> -8000ce10: 01812683 lw a3,24(sp) -8000ce14: 0f010d13 addi s10,sp,240 -8000ce18: 00fdf793 andi a5,s11,15 -8000ce1c: 00f687b3 add a5,a3,a5 -8000ce20: 0007c783 lbu a5,0(a5) -8000ce24: 01ce9713 slli a4,t4,0x1c -8000ce28: 004ddd93 srli s11,s11,0x4 -8000ce2c: fffd0d13 addi s10,s10,-1 -8000ce30: 01b76db3 or s11,a4,s11 -8000ce34: 004ede93 srli t4,t4,0x4 -8000ce38: 00fd0023 sb a5,0(s10) -8000ce3c: 01dde7b3 or a5,s11,t4 -8000ce40: fc079ce3 bnez a5,8000ce18 <_vfiprintf_r+0xa98> -8000ce44: 0f010793 addi a5,sp,240 -8000ce48: 41a787b3 sub a5,a5,s10 -8000ce4c: 00f12423 sw a5,8(sp) -8000ce50: 000c8b13 mv s6,s9 -8000ce54: 879ff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000ce58: 00100593 li a1,1 -8000ce5c: 00000613 li a2,0 -8000ce60: 00048693 mv a3,s1 -8000ce64: ba1ff06f j 8000ca04 <_vfiprintf_r+0x684> -8000ce68: 41940db3 sub s11,s0,s9 -8000ce6c: 9bb050e3 blez s11,8000c80c <_vfiprintf_r+0x48c> -8000ce70: 01000593 li a1,16 -8000ce74: 77b5de63 bge a1,s11,8000d5f0 <_vfiprintf_r+0x1270> -8000ce78: 01000e93 li t4,16 -8000ce7c: 00700f13 li t5,7 -8000ce80: 0180006f j 8000ce98 <_vfiprintf_r+0xb18> -8000ce84: 00270593 addi a1,a4,2 -8000ce88: 008c0c13 addi s8,s8,8 -8000ce8c: 00068713 mv a4,a3 -8000ce90: ff0d8d93 addi s11,s11,-16 -8000ce94: 05bedc63 bge t4,s11,8000ceec <_vfiprintf_r+0xb6c> -8000ce98: 01078793 addi a5,a5,16 -8000ce9c: 00170693 addi a3,a4,1 -8000cea0: 012c2023 sw s2,0(s8) -8000cea4: 01dc2223 sw t4,4(s8) -8000cea8: 04f12423 sw a5,72(sp) -8000ceac: 04d12223 sw a3,68(sp) -8000ceb0: fcdf5ae3 bge t5,a3,8000ce84 <_vfiprintf_r+0xb04> -8000ceb4: 16078063 beqz a5,8000d014 <_vfiprintf_r+0xc94> -8000ceb8: 04010613 addi a2,sp,64 -8000cebc: 00098593 mv a1,s3 -8000cec0: 000a0513 mv a0,s4 -8000cec4: bb4ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000cec8: f2051e63 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000cecc: 04412703 lw a4,68(sp) -8000ced0: 01000e93 li t4,16 -8000ced4: ff0d8d93 addi s11,s11,-16 -8000ced8: 04812783 lw a5,72(sp) -8000cedc: 00048c13 mv s8,s1 -8000cee0: 00170593 addi a1,a4,1 -8000cee4: 00700f13 li t5,7 -8000cee8: fbbec8e3 blt t4,s11,8000ce98 <_vfiprintf_r+0xb18> -8000ceec: 008c0513 addi a0,s8,8 -8000cef0: 01b787b3 add a5,a5,s11 -8000cef4: 012c2023 sw s2,0(s8) -8000cef8: 01bc2223 sw s11,4(s8) -8000cefc: 04f12423 sw a5,72(sp) -8000cf00: 04b12223 sw a1,68(sp) -8000cf04: 00700713 li a4,7 -8000cf08: 38b75a63 bge a4,a1,8000d29c <_vfiprintf_r+0xf1c> -8000cf0c: 5c078063 beqz a5,8000d4cc <_vfiprintf_r+0x114c> -8000cf10: 04010613 addi a2,sp,64 -8000cf14: 00098593 mv a1,s3 -8000cf18: 000a0513 mv a0,s4 -8000cf1c: b5cff0ef jal ra,8000c278 <__sprint_r.part.0> -8000cf20: ee051263 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000cf24: 00812583 lw a1,8(sp) -8000cf28: 04412703 lw a4,68(sp) -8000cf2c: 04812783 lw a5,72(sp) -8000cf30: 40ba8ab3 sub s5,s5,a1 -8000cf34: 05410693 addi a3,sp,84 -8000cf38: 00170613 addi a2,a4,1 -8000cf3c: 00048c13 mv s8,s1 -8000cf40: 8d505ce3 blez s5,8000c818 <_vfiprintf_r+0x498> -8000cf44: 01000593 li a1,16 -8000cf48: 5755de63 bge a1,s5,8000d4c4 <_vfiprintf_r+0x1144> -8000cf4c: 01000893 li a7,16 -8000cf50: 00700d93 li s11,7 -8000cf54: 0180006f j 8000cf6c <_vfiprintf_r+0xbec> -8000cf58: 00270613 addi a2,a4,2 -8000cf5c: 008c0c13 addi s8,s8,8 -8000cf60: 00068713 mv a4,a3 -8000cf64: ff0a8a93 addi s5,s5,-16 -8000cf68: 0558da63 bge a7,s5,8000cfbc <_vfiprintf_r+0xc3c> -8000cf6c: 01078793 addi a5,a5,16 -8000cf70: 00170693 addi a3,a4,1 -8000cf74: 012c2023 sw s2,0(s8) -8000cf78: 011c2223 sw a7,4(s8) -8000cf7c: 04f12423 sw a5,72(sp) -8000cf80: 04d12223 sw a3,68(sp) -8000cf84: fcdddae3 bge s11,a3,8000cf58 <_vfiprintf_r+0xbd8> -8000cf88: 06078263 beqz a5,8000cfec <_vfiprintf_r+0xc6c> -8000cf8c: 04010613 addi a2,sp,64 -8000cf90: 00098593 mv a1,s3 -8000cf94: 000a0513 mv a0,s4 -8000cf98: ae0ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000cf9c: e6051463 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000cfa0: 04412703 lw a4,68(sp) -8000cfa4: 01000893 li a7,16 -8000cfa8: ff0a8a93 addi s5,s5,-16 -8000cfac: 04812783 lw a5,72(sp) -8000cfb0: 00048c13 mv s8,s1 -8000cfb4: 00170613 addi a2,a4,1 -8000cfb8: fb58cae3 blt a7,s5,8000cf6c <_vfiprintf_r+0xbec> -8000cfbc: 008c0593 addi a1,s8,8 -8000cfc0: 015787b3 add a5,a5,s5 -8000cfc4: 012c2023 sw s2,0(s8) -8000cfc8: 015c2223 sw s5,4(s8) -8000cfcc: 04f12423 sw a5,72(sp) -8000cfd0: 04c12223 sw a2,68(sp) -8000cfd4: 00700713 li a4,7 -8000cfd8: 1ec74463 blt a4,a2,8000d1c0 <_vfiprintf_r+0xe40> -8000cfdc: 00160613 addi a2,a2,1 -8000cfe0: 00858693 addi a3,a1,8 -8000cfe4: 00058c13 mv s8,a1 -8000cfe8: 831ff06f j 8000c818 <_vfiprintf_r+0x498> -8000cfec: 00100613 li a2,1 -8000cff0: 00000713 li a4,0 -8000cff4: 00048c13 mv s8,s1 -8000cff8: f6dff06f j 8000cf64 <_vfiprintf_r+0xbe4> -8000cffc: 04010613 addi a2,sp,64 -8000d000: 00098593 mv a1,s3 -8000d004: 000a0513 mv a0,s4 -8000d008: a70ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000d00c: 86050ae3 beqz a0,8000c880 <_vfiprintf_r+0x500> -8000d010: df4ff06f j 8000c604 <_vfiprintf_r+0x284> -8000d014: 00100593 li a1,1 -8000d018: 00000713 li a4,0 -8000d01c: 00048c13 mv s8,s1 -8000d020: e71ff06f j 8000ce90 <_vfiprintf_r+0xb10> -8000d024: 24079063 bnez a5,8000d264 <_vfiprintf_r+0xee4> -8000d028: 03b14703 lbu a4,59(sp) -8000d02c: 4e071e63 bnez a4,8000d528 <_vfiprintf_r+0x11a8> -8000d030: 200f8863 beqz t6,8000d240 <_vfiprintf_r+0xec0> -8000d034: 03c10793 addi a5,sp,60 -8000d038: 04f12623 sw a5,76(sp) -8000d03c: 00200793 li a5,2 -8000d040: 04f12823 sw a5,80(sp) -8000d044: 00100613 li a2,1 -8000d048: 05410693 addi a3,sp,84 -8000d04c: 00060713 mv a4,a2 -8000d050: 00068c13 mv s8,a3 -8000d054: 00160613 addi a2,a2,1 -8000d058: 00868693 addi a3,a3,8 -8000d05c: fa8ff06f j 8000c804 <_vfiprintf_r+0x484> -8000d060: fc0788e3 beqz a5,8000d030 <_vfiprintf_r+0xcb0> -8000d064: 04010613 addi a2,sp,64 -8000d068: 00098593 mv a1,s3 -8000d06c: 000a0513 mv a0,s4 -8000d070: 03e12623 sw t5,44(sp) -8000d074: 03f12423 sw t6,40(sp) -8000d078: a00ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000d07c: d8051463 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000d080: 04412703 lw a4,68(sp) -8000d084: 04812783 lw a5,72(sp) -8000d088: 05410693 addi a3,sp,84 -8000d08c: 00170613 addi a2,a4,1 -8000d090: 00048c13 mv s8,s1 -8000d094: 02c12f03 lw t5,44(sp) -8000d098: 02812f83 lw t6,40(sp) -8000d09c: f0cff06f j 8000c7a8 <_vfiprintf_r+0x428> -8000d0a0: 000b0c93 mv s9,s6 -8000d0a4: c61ff06f j 8000cd04 <_vfiprintf_r+0x984> -8000d0a8: 01000613 li a2,16 -8000d0ac: 53b65463 bge a2,s11,8000d5d4 <_vfiprintf_r+0x1254> -8000d0b0: 000b8593 mv a1,s7 -8000d0b4: 000c0613 mv a2,s8 -8000d0b8: 00040b93 mv s7,s0 -8000d0bc: 000a8c13 mv s8,s5 -8000d0c0: 000d8413 mv s0,s11 -8000d0c4: 01000e93 li t4,16 -8000d0c8: 00700293 li t0,7 -8000d0cc: 03f12423 sw t6,40(sp) -8000d0d0: 000f0a93 mv s5,t5 -8000d0d4: 00058d93 mv s11,a1 -8000d0d8: 01c0006f j 8000d0f4 <_vfiprintf_r+0xd74> -8000d0dc: 00270593 addi a1,a4,2 -8000d0e0: 00860613 addi a2,a2,8 -8000d0e4: 00068713 mv a4,a3 -8000d0e8: ff040413 addi s0,s0,-16 -8000d0ec: 048ede63 bge t4,s0,8000d148 <_vfiprintf_r+0xdc8> -8000d0f0: 00170693 addi a3,a4,1 -8000d0f4: 00412583 lw a1,4(sp) -8000d0f8: 01078793 addi a5,a5,16 -8000d0fc: 01d62223 sw t4,4(a2) -8000d100: 00b62023 sw a1,0(a2) -8000d104: 04f12423 sw a5,72(sp) -8000d108: 04d12223 sw a3,68(sp) -8000d10c: fcd2d8e3 bge t0,a3,8000d0dc <_vfiprintf_r+0xd5c> -8000d110: 08078463 beqz a5,8000d198 <_vfiprintf_r+0xe18> -8000d114: 04010613 addi a2,sp,64 -8000d118: 00098593 mv a1,s3 -8000d11c: 000a0513 mv a0,s4 -8000d120: 958ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000d124: ce051063 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000d128: 04412703 lw a4,68(sp) -8000d12c: 01000e93 li t4,16 -8000d130: ff040413 addi s0,s0,-16 -8000d134: 04812783 lw a5,72(sp) -8000d138: 00048613 mv a2,s1 -8000d13c: 00170593 addi a1,a4,1 -8000d140: 00700293 li t0,7 -8000d144: fa8ec6e3 blt t4,s0,8000d0f0 <_vfiprintf_r+0xd70> -8000d148: 02812f83 lw t6,40(sp) -8000d14c: 000d8713 mv a4,s11 -8000d150: 000a8f13 mv t5,s5 -8000d154: 00040d93 mv s11,s0 -8000d158: 000c0a93 mv s5,s8 -8000d15c: 000b8413 mv s0,s7 -8000d160: 00060c13 mv s8,a2 -8000d164: 00070b93 mv s7,a4 -8000d168: 00412703 lw a4,4(sp) -8000d16c: 01b787b3 add a5,a5,s11 -8000d170: 01bc2223 sw s11,4(s8) -8000d174: 00ec2023 sw a4,0(s8) -8000d178: 04f12423 sw a5,72(sp) -8000d17c: 04b12223 sw a1,68(sp) -8000d180: 00700713 li a4,7 -8000d184: eab740e3 blt a4,a1,8000d024 <_vfiprintf_r+0xca4> -8000d188: 008c0c13 addi s8,s8,8 -8000d18c: 00158613 addi a2,a1,1 -8000d190: 00058713 mv a4,a1 -8000d194: dd4ff06f j 8000c768 <_vfiprintf_r+0x3e8> -8000d198: 00000713 li a4,0 -8000d19c: 00100593 li a1,1 -8000d1a0: 00048613 mv a2,s1 -8000d1a4: f45ff06f j 8000d0e8 <_vfiprintf_r+0xd68> -8000d1a8: 01945463 bge s0,s9,8000d1b0 <_vfiprintf_r+0xe30> -8000d1ac: 000c8413 mv s0,s9 -8000d1b0: 00c12783 lw a5,12(sp) -8000d1b4: 008787b3 add a5,a5,s0 -8000d1b8: 00f12623 sw a5,12(sp) -8000d1bc: ec4ff06f j 8000c880 <_vfiprintf_r+0x500> -8000d1c0: 14078e63 beqz a5,8000d31c <_vfiprintf_r+0xf9c> -8000d1c4: 04010613 addi a2,sp,64 -8000d1c8: 00098593 mv a1,s3 -8000d1cc: 000a0513 mv a0,s4 -8000d1d0: 8a8ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000d1d4: c2051863 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000d1d8: 04412603 lw a2,68(sp) -8000d1dc: 04812783 lw a5,72(sp) -8000d1e0: 05410693 addi a3,sp,84 -8000d1e4: 00160613 addi a2,a2,1 -8000d1e8: 00048c13 mv s8,s1 -8000d1ec: e2cff06f j 8000c818 <_vfiprintf_r+0x498> -8000d1f0: 04012223 sw zero,68(sp) -8000d1f4: 00048c13 mv s8,s1 -8000d1f8: afcff06f j 8000c4f4 <_vfiprintf_r+0x174> -8000d1fc: 3a0a9a63 bnez s5,8000d5b0 <_vfiprintf_r+0x1230> -8000d200: 00000a93 li s5,0 -8000d204: 00012423 sw zero,8(sp) -8000d208: 0f010d13 addi s10,sp,240 -8000d20c: cc0ff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000d210: 200b7693 andi a3,s6,512 -8000d214: 38069863 bnez a3,8000d5a4 <_vfiprintf_r+0x1224> -8000d218: 00078d93 mv s11,a5 -8000d21c: 00000e93 li t4,0 -8000d220: c64ff06f j 8000c684 <_vfiprintf_r+0x304> -8000d224: 05410693 addi a3,sp,84 -8000d228: 00100613 li a2,1 -8000d22c: 00000713 li a4,0 -8000d230: 00048c13 mv s8,s1 -8000d234: dd0ff06f j 8000c804 <_vfiprintf_r+0x484> -8000d238: 000b8c93 mv s9,s7 -8000d23c: accff06f j 8000c508 <_vfiprintf_r+0x188> -8000d240: 00000713 li a4,0 -8000d244: 05410693 addi a3,sp,84 -8000d248: 00100613 li a2,1 -8000d24c: 00048c13 mv s8,s1 -8000d250: db4ff06f j 8000c804 <_vfiprintf_r+0x484> -8000d254: 03000793 li a5,48 -8000d258: 0ef107a3 sb a5,239(sp) -8000d25c: 0ef10d13 addi s10,sp,239 -8000d260: c6cff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000d264: 04010613 addi a2,sp,64 -8000d268: 00098593 mv a1,s3 -8000d26c: 000a0513 mv a0,s4 -8000d270: 03e12623 sw t5,44(sp) -8000d274: 03f12423 sw t6,40(sp) -8000d278: 800ff0ef jal ra,8000c278 <__sprint_r.part.0> -8000d27c: b8051463 bnez a0,8000c604 <_vfiprintf_r+0x284> -8000d280: 04412703 lw a4,68(sp) -8000d284: 04812783 lw a5,72(sp) -8000d288: 00048c13 mv s8,s1 -8000d28c: 00170613 addi a2,a4,1 -8000d290: 02c12f03 lw t5,44(sp) -8000d294: 02812f83 lw t6,40(sp) -8000d298: cd0ff06f j 8000c768 <_vfiprintf_r+0x3e8> -8000d29c: 00158613 addi a2,a1,1 -8000d2a0: 00850693 addi a3,a0,8 -8000d2a4: 00058713 mv a4,a1 -8000d2a8: 00050c13 mv s8,a0 -8000d2ac: d60ff06f j 8000c80c <_vfiprintf_r+0x48c> -8000d2b0: 03000693 li a3,48 -8000d2b4: 002b6b13 ori s6,s6,2 -8000d2b8: 02e10ea3 sb a4,61(sp) -8000d2bc: 02d10e23 sb a3,60(sp) -8000d2c0: bffb7c93 andi s9,s6,-1025 -8000d2c4: 00200713 li a4,2 -8000d2c8: bd4ff06f j 8000c69c <_vfiprintf_r+0x31c> -8000d2cc: 01c12783 lw a5,28(sp) -8000d2d0: 000bc703 lbu a4,0(s7) -8000d2d4: a4078c63 beqz a5,8000c52c <_vfiprintf_r+0x1ac> -8000d2d8: 0007c783 lbu a5,0(a5) -8000d2dc: a4078863 beqz a5,8000c52c <_vfiprintf_r+0x1ac> -8000d2e0: 400b6b13 ori s6,s6,1024 -8000d2e4: a48ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000d2e8: 00c12603 lw a2,12(sp) -8000d2ec: 0006a783 lw a5,0(a3) -8000d2f0: 00e12823 sw a4,16(sp) -8000d2f4: 41f65693 srai a3,a2,0x1f -8000d2f8: 00c7a023 sw a2,0(a5) -8000d2fc: 00d7a223 sw a3,4(a5) -8000d300: 978ff06f j 8000c478 <_vfiprintf_r+0xf8> -8000d304: 000d0513 mv a0,s10 -8000d308: b14fc0ef jal ra,8000961c -8000d30c: 00a12423 sw a0,8(sp) -8000d310: 01b12823 sw s11,16(sp) -8000d314: 00000a93 li s5,0 -8000d318: bb4ff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000d31c: 00812783 lw a5,8(sp) -8000d320: 00100713 li a4,1 -8000d324: 05a12623 sw s10,76(sp) -8000d328: 04f12823 sw a5,80(sp) -8000d32c: 04f12423 sw a5,72(sp) -8000d330: 04e12223 sw a4,68(sp) -8000d334: 05410693 addi a3,sp,84 -8000d338: d20ff06f j 8000c858 <_vfiprintf_r+0x4d8> -8000d33c: 400cf793 andi a5,s9,1024 -8000d340: 0f010d13 addi s10,sp,240 -8000d344: 01812423 sw s8,8(sp) -8000d348: 00078c13 mv s8,a5 -8000d34c: 000b8793 mv a5,s7 -8000d350: 02812423 sw s0,40(sp) -8000d354: 03412623 sw s4,44(sp) -8000d358: 00098b93 mv s7,s3 -8000d35c: 00000b13 li s6,0 -8000d360: 000d0993 mv s3,s10 -8000d364: 01c12403 lw s0,28(sp) -8000d368: 000e8a13 mv s4,t4 -8000d36c: 00078d13 mv s10,a5 -8000d370: 0240006f j 8000d394 <_vfiprintf_r+0x1014> -8000d374: 00a00613 li a2,10 -8000d378: 00000693 li a3,0 -8000d37c: 000d8513 mv a0,s11 -8000d380: 000a0593 mv a1,s4 -8000d384: 421020ef jal ra,8000ffa4 <__udivdi3> -8000d388: 220a0863 beqz s4,8000d5b8 <_vfiprintf_r+0x1238> -8000d38c: 00050d93 mv s11,a0 -8000d390: 00058a13 mv s4,a1 -8000d394: 00a00613 li a2,10 -8000d398: 00000693 li a3,0 -8000d39c: 000d8513 mv a0,s11 -8000d3a0: 000a0593 mv a1,s4 -8000d3a4: 034030ef jal ra,800103d8 <__umoddi3> -8000d3a8: 03050513 addi a0,a0,48 -8000d3ac: fea98fa3 sb a0,-1(s3) -8000d3b0: 001b0b13 addi s6,s6,1 -8000d3b4: fff98993 addi s3,s3,-1 -8000d3b8: fa0c0ee3 beqz s8,8000d374 <_vfiprintf_r+0xff4> -8000d3bc: 00044703 lbu a4,0(s0) -8000d3c0: fb671ae3 bne a4,s6,8000d374 <_vfiprintf_r+0xff4> -8000d3c4: 0ff00793 li a5,255 -8000d3c8: fafb06e3 beq s6,a5,8000d374 <_vfiprintf_r+0xff4> -8000d3cc: 100a1a63 bnez s4,8000d4e0 <_vfiprintf_r+0x1160> -8000d3d0: 00900793 li a5,9 -8000d3d4: 11b7e663 bltu a5,s11,8000d4e0 <_vfiprintf_r+0x1160> -8000d3d8: 000d0793 mv a5,s10 -8000d3dc: 00098d13 mv s10,s3 -8000d3e0: 000b8993 mv s3,s7 -8000d3e4: 00078b93 mv s7,a5 -8000d3e8: 0f010793 addi a5,sp,240 -8000d3ec: 41a787b3 sub a5,a5,s10 -8000d3f0: 00812e23 sw s0,28(sp) -8000d3f4: 00812c03 lw s8,8(sp) -8000d3f8: 02812403 lw s0,40(sp) -8000d3fc: 02c12a03 lw s4,44(sp) -8000d400: 00f12423 sw a5,8(sp) -8000d404: 000c8b13 mv s6,s9 -8000d408: ac4ff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000d40c: 001bc703 lbu a4,1(s7) -8000d410: 200b6b13 ori s6,s6,512 -8000d414: 001b8b93 addi s7,s7,1 -8000d418: 914ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000d41c: 001bc703 lbu a4,1(s7) -8000d420: 020b6b13 ori s6,s6,32 -8000d424: 001b8b93 addi s7,s7,1 -8000d428: 904ff06f j 8000c52c <_vfiprintf_r+0x1ac> -8000d42c: 01012783 lw a5,16(sp) -8000d430: 0007a783 lw a5,0(a5) -8000d434: 00e12823 sw a4,16(sp) -8000d438: 00c12703 lw a4,12(sp) -8000d43c: 00e7a023 sw a4,0(a5) -8000d440: 838ff06f j 8000c478 <_vfiprintf_r+0xf8> -8000d444: 01512423 sw s5,8(sp) -8000d448: 00600793 li a5,6 -8000d44c: 0d57ea63 bltu a5,s5,8000d520 <_vfiprintf_r+0x11a0> -8000d450: 80015e37 lui t3,0x80015 -8000d454: 00812c83 lw s9,8(sp) -8000d458: 01b12823 sw s11,16(sp) -8000d45c: 808e0d13 addi s10,t3,-2040 # 80014808 <__BSS_END__+0xffffda90> -8000d460: ad8ff06f j 8000c738 <_vfiprintf_r+0x3b8> -8000d464: 200b7693 andi a3,s6,512 -8000d468: 12068263 beqz a3,8000d58c <_vfiprintf_r+0x120c> -8000d46c: 00e12823 sw a4,16(sp) -8000d470: 0ff7fd93 andi s11,a5,255 -8000d474: 00000e93 li t4,0 -8000d478: 000b0c93 mv s9,s6 -8000d47c: 00100713 li a4,1 -8000d480: a1cff06f j 8000c69c <_vfiprintf_r+0x31c> -8000d484: 200b7693 andi a3,s6,512 -8000d488: 0e068863 beqz a3,8000d578 <_vfiprintf_r+0x11f8> -8000d48c: 0ff7fd93 andi s11,a5,255 -8000d490: 00000e93 li t4,0 -8000d494: 000b0313 mv t1,s6 -8000d498: 00e12823 sw a4,16(sp) -8000d49c: 905ff06f j 8000cda0 <_vfiprintf_r+0xa20> -8000d4a0: 200b7793 andi a5,s6,512 -8000d4a4: 0a078c63 beqz a5,8000d55c <_vfiprintf_r+0x11dc> -8000d4a8: 01012783 lw a5,16(sp) -8000d4ac: 000b0c93 mv s9,s6 -8000d4b0: 00e12823 sw a4,16(sp) -8000d4b4: 00078d83 lb s11,0(a5) -8000d4b8: 41fdde93 srai t4,s11,0x1f -8000d4bc: 000e8713 mv a4,t4 -8000d4c0: c98ff06f j 8000c958 <_vfiprintf_r+0x5d8> -8000d4c4: 00068593 mv a1,a3 -8000d4c8: af9ff06f j 8000cfc0 <_vfiprintf_r+0xc40> -8000d4cc: 05410693 addi a3,sp,84 -8000d4d0: 00100613 li a2,1 -8000d4d4: 00000713 li a4,0 -8000d4d8: 00048c13 mv s8,s1 -8000d4dc: b30ff06f j 8000c80c <_vfiprintf_r+0x48c> -8000d4e0: 02412783 lw a5,36(sp) -8000d4e4: 02012583 lw a1,32(sp) -8000d4e8: 00000b13 li s6,0 -8000d4ec: 40f989b3 sub s3,s3,a5 -8000d4f0: 00078613 mv a2,a5 -8000d4f4: 00098513 mv a0,s3 -8000d4f8: 9b0fc0ef jal ra,800096a8 -8000d4fc: 00144703 lbu a4,1(s0) -8000d500: 00a00613 li a2,10 -8000d504: 00000693 li a3,0 -8000d508: 00e03733 snez a4,a4 -8000d50c: 000d8513 mv a0,s11 -8000d510: 000a0593 mv a1,s4 -8000d514: 00e40433 add s0,s0,a4 -8000d518: 28d020ef jal ra,8000ffa4 <__udivdi3> -8000d51c: e71ff06f j 8000d38c <_vfiprintf_r+0x100c> -8000d520: 00f12423 sw a5,8(sp) -8000d524: f2dff06f j 8000d450 <_vfiprintf_r+0x10d0> -8000d528: 03b10793 addi a5,sp,59 -8000d52c: 04f12623 sw a5,76(sp) -8000d530: 00100793 li a5,1 -8000d534: 04f12823 sw a5,80(sp) -8000d538: 00100613 li a2,1 -8000d53c: 05410693 addi a3,sp,84 -8000d540: a58ff06f j 8000c798 <_vfiprintf_r+0x418> -8000d544: 01012783 lw a5,16(sp) -8000d548: 00e12823 sw a4,16(sp) -8000d54c: 00c12703 lw a4,12(sp) -8000d550: 0007a783 lw a5,0(a5) -8000d554: 00e79023 sh a4,0(a5) -8000d558: f21fe06f j 8000c478 <_vfiprintf_r+0xf8> -8000d55c: 01012783 lw a5,16(sp) -8000d560: 000b0c93 mv s9,s6 -8000d564: 00e12823 sw a4,16(sp) -8000d568: 0007ad83 lw s11,0(a5) -8000d56c: 41fdde93 srai t4,s11,0x1f -8000d570: 000e8713 mv a4,t4 -8000d574: be4ff06f j 8000c958 <_vfiprintf_r+0x5d8> -8000d578: 00078d93 mv s11,a5 -8000d57c: 00000e93 li t4,0 -8000d580: 000b0313 mv t1,s6 -8000d584: 00e12823 sw a4,16(sp) -8000d588: 819ff06f j 8000cda0 <_vfiprintf_r+0xa20> -8000d58c: 00e12823 sw a4,16(sp) -8000d590: 00078d93 mv s11,a5 -8000d594: 00000e93 li t4,0 -8000d598: 000b0c93 mv s9,s6 -8000d59c: 00100713 li a4,1 -8000d5a0: 8fcff06f j 8000c69c <_vfiprintf_r+0x31c> -8000d5a4: 0ff7fd93 andi s11,a5,255 -8000d5a8: 00000e93 li t4,0 -8000d5ac: 8d8ff06f j 8000c684 <_vfiprintf_r+0x304> -8000d5b0: 000b0c93 mv s9,s6 -8000d5b4: bccff06f j 8000c980 <_vfiprintf_r+0x600> -8000d5b8: 00900793 li a5,9 -8000d5bc: ddb7e8e3 bltu a5,s11,8000d38c <_vfiprintf_r+0x100c> -8000d5c0: e19ff06f j 8000d3d8 <_vfiprintf_r+0x1058> -8000d5c4: 01512423 sw s5,8(sp) -8000d5c8: 01b12823 sw s11,16(sp) -8000d5cc: 00000a93 li s5,0 -8000d5d0: 8fcff06f j 8000c6cc <_vfiprintf_r+0x34c> -8000d5d4: 00068593 mv a1,a3 -8000d5d8: b91ff06f j 8000d168 <_vfiprintf_r+0xde8> -8000d5dc: 00160593 addi a1,a2,1 -8000d5e0: c7cff06f j 8000ca5c <_vfiprintf_r+0x6dc> -8000d5e4: fff00793 li a5,-1 -8000d5e8: 00f12623 sw a5,12(sp) -8000d5ec: 828ff06f j 8000c614 <_vfiprintf_r+0x294> -8000d5f0: 00068513 mv a0,a3 -8000d5f4: 00060593 mv a1,a2 -8000d5f8: 8f9ff06f j 8000cef0 <_vfiprintf_r+0xb70> -8000d5fc: 01012703 lw a4,16(sp) -8000d600: 00072a83 lw s5,0(a4) -8000d604: 00470693 addi a3,a4,4 -8000d608: 000ad463 bgez s5,8000d610 <_vfiprintf_r+0x1290> -8000d60c: fff00a93 li s5,-1 -8000d610: 001bc703 lbu a4,1(s7) -8000d614: 00d12823 sw a3,16(sp) -8000d618: 00078b93 mv s7,a5 -8000d61c: f11fe06f j 8000c52c <_vfiprintf_r+0x1ac> -8000d620: 000b0c93 mv s9,s6 -8000d624: a7cff06f j 8000c8a0 <_vfiprintf_r+0x520> -8000d628: 000b0313 mv t1,s6 -8000d62c: af0ff06f j 8000c91c <_vfiprintf_r+0x59c> -8000d630: 000b0c93 mv s9,s6 -8000d634: b10ff06f j 8000c944 <_vfiprintf_r+0x5c4> - -8000d638 : -8000d638: 00060693 mv a3,a2 -8000d63c: 00058613 mv a2,a1 -8000d640: 00050593 mv a1,a0 -8000d644: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -8000d648: d39fe06f j 8000c380 <_vfiprintf_r> - -8000d64c <__sbprintf>: -8000d64c: 00c5d783 lhu a5,12(a1) -8000d650: 0645ae03 lw t3,100(a1) -8000d654: 00e5d303 lhu t1,14(a1) -8000d658: 01c5a883 lw a7,28(a1) -8000d65c: 0245a803 lw a6,36(a1) -8000d660: b8010113 addi sp,sp,-1152 -8000d664: ffd7f793 andi a5,a5,-3 -8000d668: 40000713 li a4,1024 -8000d66c: 46812c23 sw s0,1144(sp) -8000d670: 00f11a23 sh a5,20(sp) -8000d674: 00058413 mv s0,a1 -8000d678: 07010793 addi a5,sp,112 -8000d67c: 00810593 addi a1,sp,8 -8000d680: 46912a23 sw s1,1140(sp) -8000d684: 47212823 sw s2,1136(sp) -8000d688: 46112e23 sw ra,1148(sp) -8000d68c: 00050913 mv s2,a0 -8000d690: 07c12623 sw t3,108(sp) -8000d694: 00611b23 sh t1,22(sp) -8000d698: 03112223 sw a7,36(sp) -8000d69c: 03012623 sw a6,44(sp) -8000d6a0: 00f12423 sw a5,8(sp) -8000d6a4: 00f12c23 sw a5,24(sp) -8000d6a8: 00e12823 sw a4,16(sp) -8000d6ac: 00e12e23 sw a4,28(sp) -8000d6b0: 02012023 sw zero,32(sp) -8000d6b4: ccdfe0ef jal ra,8000c380 <_vfiprintf_r> -8000d6b8: 00050493 mv s1,a0 -8000d6bc: 02055c63 bgez a0,8000d6f4 <__sbprintf+0xa8> -8000d6c0: 01415783 lhu a5,20(sp) -8000d6c4: 0407f793 andi a5,a5,64 -8000d6c8: 00078863 beqz a5,8000d6d8 <__sbprintf+0x8c> -8000d6cc: 00c45783 lhu a5,12(s0) -8000d6d0: 0407e793 ori a5,a5,64 -8000d6d4: 00f41623 sh a5,12(s0) -8000d6d8: 47c12083 lw ra,1148(sp) -8000d6dc: 47812403 lw s0,1144(sp) -8000d6e0: 00048513 mv a0,s1 -8000d6e4: 47012903 lw s2,1136(sp) -8000d6e8: 47412483 lw s1,1140(sp) -8000d6ec: 48010113 addi sp,sp,1152 -8000d6f0: 00008067 ret -8000d6f4: 00810593 addi a1,sp,8 -8000d6f8: 00090513 mv a0,s2 -8000d6fc: 930f70ef jal ra,8000482c <_fflush_r> -8000d700: fc0500e3 beqz a0,8000d6c0 <__sbprintf+0x74> -8000d704: fff00493 li s1,-1 -8000d708: fb9ff06f j 8000d6c0 <__sbprintf+0x74> - -8000d70c <_wctomb_r>: -8000d70c: 1101a303 lw t1,272(gp) # 80016c78 <__global_locale+0xe0> -8000d710: 00030067 jr t1 - -8000d714 <__ascii_wctomb>: -8000d714: 02058463 beqz a1,8000d73c <__ascii_wctomb+0x28> -8000d718: 0ff00793 li a5,255 -8000d71c: 00c7e863 bltu a5,a2,8000d72c <__ascii_wctomb+0x18> -8000d720: 00c58023 sb a2,0(a1) -8000d724: 00100513 li a0,1 -8000d728: 00008067 ret -8000d72c: 08a00793 li a5,138 -8000d730: 00f52023 sw a5,0(a0) -8000d734: fff00513 li a0,-1 -8000d738: 00008067 ret -8000d73c: 00000513 li a0,0 -8000d740: 00008067 ret - -8000d744 <_write_r>: -8000d744: ff010113 addi sp,sp,-16 -8000d748: 00058793 mv a5,a1 -8000d74c: 00812423 sw s0,8(sp) -8000d750: 00912223 sw s1,4(sp) -8000d754: 00060593 mv a1,a2 -8000d758: 00050493 mv s1,a0 -8000d75c: 00078513 mv a0,a5 -8000d760: 00068613 mv a2,a3 -8000d764: 00112623 sw ra,12(sp) -8000d768: 2001a623 sw zero,524(gp) # 80016d74 -8000d76c: d6df20ef jal ra,800004d8 <_write> -8000d770: fff00793 li a5,-1 -8000d774: 00f50c63 beq a0,a5,8000d78c <_write_r+0x48> -8000d778: 00c12083 lw ra,12(sp) -8000d77c: 00812403 lw s0,8(sp) -8000d780: 00412483 lw s1,4(sp) -8000d784: 01010113 addi sp,sp,16 -8000d788: 00008067 ret -8000d78c: 20c1a783 lw a5,524(gp) # 80016d74 -8000d790: fe0784e3 beqz a5,8000d778 <_write_r+0x34> -8000d794: 00c12083 lw ra,12(sp) -8000d798: 00812403 lw s0,8(sp) -8000d79c: 00f4a023 sw a5,0(s1) -8000d7a0: 00412483 lw s1,4(sp) -8000d7a4: 01010113 addi sp,sp,16 -8000d7a8: 00008067 ret - -8000d7ac <_calloc_r>: -8000d7ac: 02c585b3 mul a1,a1,a2 -8000d7b0: ff010113 addi sp,sp,-16 -8000d7b4: 00812423 sw s0,8(sp) -8000d7b8: 00112623 sw ra,12(sp) -8000d7bc: d44f30ef jal ra,80000d00 <_malloc_r> -8000d7c0: 00050413 mv s0,a0 -8000d7c4: 02050863 beqz a0,8000d7f4 <_calloc_r+0x48> -8000d7c8: ffc52603 lw a2,-4(a0) -8000d7cc: 02400713 li a4,36 -8000d7d0: ffc67613 andi a2,a2,-4 -8000d7d4: ffc60613 addi a2,a2,-4 -8000d7d8: 06c76063 bltu a4,a2,8000d838 <_calloc_r+0x8c> -8000d7dc: 01300693 li a3,19 -8000d7e0: 00050793 mv a5,a0 -8000d7e4: 02c6e263 bltu a3,a2,8000d808 <_calloc_r+0x5c> -8000d7e8: 0007a023 sw zero,0(a5) -8000d7ec: 0007a223 sw zero,4(a5) -8000d7f0: 0007a423 sw zero,8(a5) -8000d7f4: 00040513 mv a0,s0 -8000d7f8: 00c12083 lw ra,12(sp) -8000d7fc: 00812403 lw s0,8(sp) -8000d800: 01010113 addi sp,sp,16 -8000d804: 00008067 ret -8000d808: 00052023 sw zero,0(a0) -8000d80c: 00052223 sw zero,4(a0) -8000d810: 01b00793 li a5,27 -8000d814: 04c7f063 bgeu a5,a2,8000d854 <_calloc_r+0xa8> -8000d818: 00052423 sw zero,8(a0) -8000d81c: 00052623 sw zero,12(a0) -8000d820: 01050793 addi a5,a0,16 -8000d824: fce612e3 bne a2,a4,8000d7e8 <_calloc_r+0x3c> -8000d828: 00052823 sw zero,16(a0) -8000d82c: 01850793 addi a5,a0,24 -8000d830: 00052a23 sw zero,20(a0) -8000d834: fb5ff06f j 8000d7e8 <_calloc_r+0x3c> -8000d838: 00000593 li a1,0 -8000d83c: c81f30ef jal ra,800014bc -8000d840: 00040513 mv a0,s0 -8000d844: 00c12083 lw ra,12(sp) -8000d848: 00812403 lw s0,8(sp) -8000d84c: 01010113 addi sp,sp,16 -8000d850: 00008067 ret -8000d854: 00850793 addi a5,a0,8 -8000d858: f91ff06f j 8000d7e8 <_calloc_r+0x3c> - -8000d85c <_close_r>: -8000d85c: ff010113 addi sp,sp,-16 -8000d860: 00812423 sw s0,8(sp) -8000d864: 00912223 sw s1,4(sp) -8000d868: 00050493 mv s1,a0 -8000d86c: 00058513 mv a0,a1 -8000d870: 00112623 sw ra,12(sp) -8000d874: 2001a623 sw zero,524(gp) # 80016d74 -8000d878: a71f20ef jal ra,800002e8 <_close> -8000d87c: fff00793 li a5,-1 -8000d880: 00f50c63 beq a0,a5,8000d898 <_close_r+0x3c> -8000d884: 00c12083 lw ra,12(sp) -8000d888: 00812403 lw s0,8(sp) -8000d88c: 00412483 lw s1,4(sp) -8000d890: 01010113 addi sp,sp,16 -8000d894: 00008067 ret -8000d898: 20c1a783 lw a5,524(gp) # 80016d74 -8000d89c: fe0784e3 beqz a5,8000d884 <_close_r+0x28> -8000d8a0: 00c12083 lw ra,12(sp) -8000d8a4: 00812403 lw s0,8(sp) -8000d8a8: 00f4a023 sw a5,0(s1) -8000d8ac: 00412483 lw s1,4(sp) -8000d8b0: 01010113 addi sp,sp,16 -8000d8b4: 00008067 ret - -8000d8b8 <_fclose_r>: -8000d8b8: ff010113 addi sp,sp,-16 -8000d8bc: 00112623 sw ra,12(sp) -8000d8c0: 00812423 sw s0,8(sp) -8000d8c4: 00912223 sw s1,4(sp) -8000d8c8: 01212023 sw s2,0(sp) -8000d8cc: 02058063 beqz a1,8000d8ec <_fclose_r+0x34> -8000d8d0: 00050493 mv s1,a0 -8000d8d4: 00058413 mv s0,a1 -8000d8d8: 00050663 beqz a0,8000d8e4 <_fclose_r+0x2c> -8000d8dc: 03852783 lw a5,56(a0) -8000d8e0: 0a078c63 beqz a5,8000d998 <_fclose_r+0xe0> -8000d8e4: 00c41783 lh a5,12(s0) -8000d8e8: 02079263 bnez a5,8000d90c <_fclose_r+0x54> -8000d8ec: 00c12083 lw ra,12(sp) -8000d8f0: 00812403 lw s0,8(sp) -8000d8f4: 00000913 li s2,0 -8000d8f8: 00090513 mv a0,s2 -8000d8fc: 00412483 lw s1,4(sp) -8000d900: 00012903 lw s2,0(sp) -8000d904: 01010113 addi sp,sp,16 -8000d908: 00008067 ret -8000d90c: 00040593 mv a1,s0 -8000d910: 00048513 mv a0,s1 -8000d914: cbdf60ef jal ra,800045d0 <__sflush_r> -8000d918: 02c42783 lw a5,44(s0) -8000d91c: 00050913 mv s2,a0 -8000d920: 00078a63 beqz a5,8000d934 <_fclose_r+0x7c> -8000d924: 01c42583 lw a1,28(s0) -8000d928: 00048513 mv a0,s1 -8000d92c: 000780e7 jalr a5 -8000d930: 06054c63 bltz a0,8000d9a8 <_fclose_r+0xf0> -8000d934: 00c45783 lhu a5,12(s0) -8000d938: 0807f793 andi a5,a5,128 -8000d93c: 06079e63 bnez a5,8000d9b8 <_fclose_r+0x100> -8000d940: 03042583 lw a1,48(s0) -8000d944: 00058c63 beqz a1,8000d95c <_fclose_r+0xa4> -8000d948: 04040793 addi a5,s0,64 -8000d94c: 00f58663 beq a1,a5,8000d958 <_fclose_r+0xa0> -8000d950: 00048513 mv a0,s1 -8000d954: bd4f70ef jal ra,80004d28 <_free_r> -8000d958: 02042823 sw zero,48(s0) -8000d95c: 04442583 lw a1,68(s0) -8000d960: 00058863 beqz a1,8000d970 <_fclose_r+0xb8> -8000d964: 00048513 mv a0,s1 -8000d968: bc0f70ef jal ra,80004d28 <_free_r> -8000d96c: 04042223 sw zero,68(s0) -8000d970: a68f70ef jal ra,80004bd8 <__sfp_lock_acquire> -8000d974: 00041623 sh zero,12(s0) -8000d978: a64f70ef jal ra,80004bdc <__sfp_lock_release> -8000d97c: 00c12083 lw ra,12(sp) -8000d980: 00812403 lw s0,8(sp) -8000d984: 00090513 mv a0,s2 -8000d988: 00412483 lw s1,4(sp) -8000d98c: 00012903 lw s2,0(sp) -8000d990: 01010113 addi sp,sp,16 -8000d994: 00008067 ret -8000d998: a30f70ef jal ra,80004bc8 <__sinit> -8000d99c: 00c41783 lh a5,12(s0) -8000d9a0: f40786e3 beqz a5,8000d8ec <_fclose_r+0x34> -8000d9a4: f69ff06f j 8000d90c <_fclose_r+0x54> -8000d9a8: 00c45783 lhu a5,12(s0) -8000d9ac: fff00913 li s2,-1 -8000d9b0: 0807f793 andi a5,a5,128 -8000d9b4: f80786e3 beqz a5,8000d940 <_fclose_r+0x88> -8000d9b8: 01042583 lw a1,16(s0) -8000d9bc: 00048513 mv a0,s1 -8000d9c0: b68f70ef jal ra,80004d28 <_free_r> -8000d9c4: f7dff06f j 8000d940 <_fclose_r+0x88> - -8000d9c8 : -8000d9c8: 00050593 mv a1,a0 -8000d9cc: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -8000d9d0: ee9ff06f j 8000d8b8 <_fclose_r> - -8000d9d4 <__fputwc>: -8000d9d4: fd010113 addi sp,sp,-48 -8000d9d8: 02812423 sw s0,40(sp) -8000d9dc: 01312e23 sw s3,28(sp) -8000d9e0: 01512a23 sw s5,20(sp) -8000d9e4: 02112623 sw ra,44(sp) -8000d9e8: 02912223 sw s1,36(sp) -8000d9ec: 03212023 sw s2,32(sp) -8000d9f0: 01412c23 sw s4,24(sp) -8000d9f4: 01612823 sw s6,16(sp) -8000d9f8: 00050993 mv s3,a0 -8000d9fc: 00058a93 mv s5,a1 -8000da00: 00060413 mv s0,a2 -8000da04: bb0fa0ef jal ra,80007db4 <__locale_mb_cur_max> -8000da08: 00100793 li a5,1 -8000da0c: 02f51063 bne a0,a5,8000da2c <__fputwc+0x58> -8000da10: fffa8793 addi a5,s5,-1 -8000da14: 0fe00713 li a4,254 -8000da18: 00f76a63 bltu a4,a5,8000da2c <__fputwc+0x58> -8000da1c: 0ffaf713 andi a4,s5,255 -8000da20: 00e10623 sb a4,12(sp) -8000da24: 00100913 li s2,1 -8000da28: 02c0006f j 8000da54 <__fputwc+0x80> -8000da2c: 05c40693 addi a3,s0,92 -8000da30: 000a8613 mv a2,s5 -8000da34: 00c10593 addi a1,sp,12 -8000da38: 00098513 mv a0,s3 -8000da3c: 46c020ef jal ra,8000fea8 <_wcrtomb_r> -8000da40: fff00793 li a5,-1 -8000da44: 00050913 mv s2,a0 -8000da48: 0af50463 beq a0,a5,8000daf0 <__fputwc+0x11c> -8000da4c: 08050e63 beqz a0,8000dae8 <__fputwc+0x114> -8000da50: 00c14703 lbu a4,12(sp) -8000da54: 00000493 li s1,0 -8000da58: fff00a13 li s4,-1 -8000da5c: 00a00b13 li s6,10 -8000da60: 0280006f j 8000da88 <__fputwc+0xb4> -8000da64: 00042783 lw a5,0(s0) -8000da68: 00178693 addi a3,a5,1 -8000da6c: 00d42023 sw a3,0(s0) -8000da70: 00e78023 sb a4,0(a5) -8000da74: 00148493 addi s1,s1,1 -8000da78: 00c10793 addi a5,sp,12 -8000da7c: 009787b3 add a5,a5,s1 -8000da80: 0724f463 bgeu s1,s2,8000dae8 <__fputwc+0x114> -8000da84: 0007c703 lbu a4,0(a5) -8000da88: 00842783 lw a5,8(s0) -8000da8c: fff78793 addi a5,a5,-1 -8000da90: 00f42423 sw a5,8(s0) -8000da94: fc07d8e3 bgez a5,8000da64 <__fputwc+0x90> -8000da98: 01842683 lw a3,24(s0) -8000da9c: 00070593 mv a1,a4 -8000daa0: 00040613 mv a2,s0 -8000daa4: 00098513 mv a0,s3 -8000daa8: 00d7c463 blt a5,a3,8000dab0 <__fputwc+0xdc> -8000daac: fb671ce3 bne a4,s6,8000da64 <__fputwc+0x90> -8000dab0: 264020ef jal ra,8000fd14 <__swbuf_r> -8000dab4: fd4510e3 bne a0,s4,8000da74 <__fputwc+0xa0> -8000dab8: fff00913 li s2,-1 -8000dabc: 02c12083 lw ra,44(sp) -8000dac0: 02812403 lw s0,40(sp) -8000dac4: 00090513 mv a0,s2 -8000dac8: 02412483 lw s1,36(sp) -8000dacc: 02012903 lw s2,32(sp) -8000dad0: 01c12983 lw s3,28(sp) -8000dad4: 01812a03 lw s4,24(sp) -8000dad8: 01412a83 lw s5,20(sp) -8000dadc: 01012b03 lw s6,16(sp) -8000dae0: 03010113 addi sp,sp,48 -8000dae4: 00008067 ret -8000dae8: 000a8913 mv s2,s5 -8000daec: fd1ff06f j 8000dabc <__fputwc+0xe8> -8000daf0: 00c45783 lhu a5,12(s0) -8000daf4: 0407e793 ori a5,a5,64 -8000daf8: 00f41623 sh a5,12(s0) -8000dafc: fc1ff06f j 8000dabc <__fputwc+0xe8> - -8000db00 <_fputwc_r>: -8000db00: 00c61783 lh a5,12(a2) -8000db04: 01279713 slli a4,a5,0x12 -8000db08: 02074063 bltz a4,8000db28 <_fputwc_r+0x28> -8000db0c: 06462703 lw a4,100(a2) -8000db10: 000026b7 lui a3,0x2 -8000db14: 00d7e7b3 or a5,a5,a3 -8000db18: 000026b7 lui a3,0x2 -8000db1c: 00d76733 or a4,a4,a3 -8000db20: 00f61623 sh a5,12(a2) -8000db24: 06e62223 sw a4,100(a2) -8000db28: eadff06f j 8000d9d4 <__fputwc> - -8000db2c : -8000db2c: fe010113 addi sp,sp,-32 -8000db30: 00812c23 sw s0,24(sp) -8000db34: 1c81a403 lw s0,456(gp) # 80016d30 <_impure_ptr> -8000db38: 00912a23 sw s1,20(sp) -8000db3c: 00112e23 sw ra,28(sp) -8000db40: 00050493 mv s1,a0 -8000db44: 00058613 mv a2,a1 -8000db48: 00040663 beqz s0,8000db54 -8000db4c: 03842783 lw a5,56(s0) -8000db50: 04078463 beqz a5,8000db98 -8000db54: 00c61783 lh a5,12(a2) -8000db58: 01279713 slli a4,a5,0x12 -8000db5c: 02074063 bltz a4,8000db7c -8000db60: 06462703 lw a4,100(a2) -8000db64: 000026b7 lui a3,0x2 -8000db68: 00d7e7b3 or a5,a5,a3 -8000db6c: 000026b7 lui a3,0x2 -8000db70: 00d76733 or a4,a4,a3 -8000db74: 00f61623 sh a5,12(a2) -8000db78: 06e62223 sw a4,100(a2) -8000db7c: 00040513 mv a0,s0 -8000db80: 01812403 lw s0,24(sp) -8000db84: 01c12083 lw ra,28(sp) -8000db88: 00048593 mv a1,s1 -8000db8c: 01412483 lw s1,20(sp) -8000db90: 02010113 addi sp,sp,32 -8000db94: e41ff06f j 8000d9d4 <__fputwc> -8000db98: 00040513 mv a0,s0 -8000db9c: 00b12623 sw a1,12(sp) -8000dba0: 828f70ef jal ra,80004bc8 <__sinit> -8000dba4: 00c12603 lw a2,12(sp) -8000dba8: fadff06f j 8000db54 - -8000dbac <_fstat_r>: -8000dbac: ff010113 addi sp,sp,-16 -8000dbb0: 00058793 mv a5,a1 -8000dbb4: 00812423 sw s0,8(sp) -8000dbb8: 00912223 sw s1,4(sp) -8000dbbc: 00050493 mv s1,a0 -8000dbc0: 00060593 mv a1,a2 -8000dbc4: 00078513 mv a0,a5 -8000dbc8: 00112623 sw ra,12(sp) -8000dbcc: 2001a623 sw zero,524(gp) # 80016d74 -8000dbd0: f34f20ef jal ra,80000304 <_fstat> -8000dbd4: fff00793 li a5,-1 -8000dbd8: 00f50c63 beq a0,a5,8000dbf0 <_fstat_r+0x44> -8000dbdc: 00c12083 lw ra,12(sp) -8000dbe0: 00812403 lw s0,8(sp) -8000dbe4: 00412483 lw s1,4(sp) -8000dbe8: 01010113 addi sp,sp,16 -8000dbec: 00008067 ret -8000dbf0: 20c1a783 lw a5,524(gp) # 80016d74 -8000dbf4: fe0784e3 beqz a5,8000dbdc <_fstat_r+0x30> -8000dbf8: 00c12083 lw ra,12(sp) -8000dbfc: 00812403 lw s0,8(sp) -8000dc00: 00f4a023 sw a5,0(s1) -8000dc04: 00412483 lw s1,4(sp) -8000dc08: 01010113 addi sp,sp,16 -8000dc0c: 00008067 ret - -8000dc10 <__sfvwrite_r>: -8000dc10: 00862783 lw a5,8(a2) -8000dc14: 34078263 beqz a5,8000df58 <__sfvwrite_r+0x348> -8000dc18: 00c5d783 lhu a5,12(a1) -8000dc1c: fd010113 addi sp,sp,-48 -8000dc20: 02812423 sw s0,40(sp) -8000dc24: 01412c23 sw s4,24(sp) -8000dc28: 01512a23 sw s5,20(sp) -8000dc2c: 02112623 sw ra,44(sp) -8000dc30: 02912223 sw s1,36(sp) -8000dc34: 03212023 sw s2,32(sp) -8000dc38: 01312e23 sw s3,28(sp) -8000dc3c: 01612823 sw s6,16(sp) -8000dc40: 01712623 sw s7,12(sp) -8000dc44: 01812423 sw s8,8(sp) -8000dc48: 01912223 sw s9,4(sp) -8000dc4c: 01a12023 sw s10,0(sp) -8000dc50: 0087f713 andi a4,a5,8 -8000dc54: 00058413 mv s0,a1 -8000dc58: 00050a93 mv s5,a0 -8000dc5c: 00060a13 mv s4,a2 -8000dc60: 08070a63 beqz a4,8000dcf4 <__sfvwrite_r+0xe4> -8000dc64: 0105a703 lw a4,16(a1) -8000dc68: 08070663 beqz a4,8000dcf4 <__sfvwrite_r+0xe4> -8000dc6c: 0027f713 andi a4,a5,2 -8000dc70: 000a2483 lw s1,0(s4) -8000dc74: 0a070063 beqz a4,8000dd14 <__sfvwrite_r+0x104> -8000dc78: 02442703 lw a4,36(s0) -8000dc7c: 01c42783 lw a5,28(s0) -8000dc80: 80000b37 lui s6,0x80000 -8000dc84: 00000993 li s3,0 -8000dc88: 00000913 li s2,0 -8000dc8c: c00b4b13 xori s6,s6,-1024 -8000dc90: 00098613 mv a2,s3 -8000dc94: 00078593 mv a1,a5 -8000dc98: 000a8513 mv a0,s5 -8000dc9c: 04090463 beqz s2,8000dce4 <__sfvwrite_r+0xd4> -8000dca0: 00090693 mv a3,s2 -8000dca4: 012b7463 bgeu s6,s2,8000dcac <__sfvwrite_r+0x9c> -8000dca8: 000b0693 mv a3,s6 -8000dcac: 000700e7 jalr a4 -8000dcb0: 28a05a63 blez a0,8000df44 <__sfvwrite_r+0x334> -8000dcb4: 008a2783 lw a5,8(s4) -8000dcb8: 00a989b3 add s3,s3,a0 -8000dcbc: 40a90933 sub s2,s2,a0 -8000dcc0: 40a78533 sub a0,a5,a0 -8000dcc4: 00aa2423 sw a0,8(s4) -8000dcc8: 20050c63 beqz a0,8000dee0 <__sfvwrite_r+0x2d0> -8000dccc: 01c42783 lw a5,28(s0) -8000dcd0: 02442703 lw a4,36(s0) -8000dcd4: 00098613 mv a2,s3 -8000dcd8: 00078593 mv a1,a5 -8000dcdc: 000a8513 mv a0,s5 -8000dce0: fc0910e3 bnez s2,8000dca0 <__sfvwrite_r+0x90> -8000dce4: 0004a983 lw s3,0(s1) -8000dce8: 0044a903 lw s2,4(s1) -8000dcec: 00848493 addi s1,s1,8 -8000dcf0: fa1ff06f j 8000dc90 <__sfvwrite_r+0x80> -8000dcf4: 00040593 mv a1,s0 -8000dcf8: 000a8513 mv a0,s5 -8000dcfc: dc0f60ef jal ra,800042bc <__swsetup_r> -8000dd00: 3a051c63 bnez a0,8000e0b8 <__sfvwrite_r+0x4a8> -8000dd04: 00c45783 lhu a5,12(s0) -8000dd08: 000a2483 lw s1,0(s4) -8000dd0c: 0027f713 andi a4,a5,2 -8000dd10: f60714e3 bnez a4,8000dc78 <__sfvwrite_r+0x68> -8000dd14: 0017f713 andi a4,a5,1 -8000dd18: 24071463 bnez a4,8000df60 <__sfvwrite_r+0x350> -8000dd1c: 00842c83 lw s9,8(s0) -8000dd20: 00042503 lw a0,0(s0) -8000dd24: 80000bb7 lui s7,0x80000 -8000dd28: ffebcc13 xori s8,s7,-2 -8000dd2c: 00000b13 li s6,0 -8000dd30: 00000913 li s2,0 -8000dd34: fffbcb93 not s7,s7 -8000dd38: 0e090e63 beqz s2,8000de34 <__sfvwrite_r+0x224> -8000dd3c: 2007f713 andi a4,a5,512 -8000dd40: 24070c63 beqz a4,8000df98 <__sfvwrite_r+0x388> -8000dd44: 000c8d13 mv s10,s9 -8000dd48: 2f996263 bltu s2,s9,8000e02c <__sfvwrite_r+0x41c> -8000dd4c: 4807f713 andi a4,a5,1152 -8000dd50: 08070a63 beqz a4,8000dde4 <__sfvwrite_r+0x1d4> -8000dd54: 01442683 lw a3,20(s0) -8000dd58: 01042583 lw a1,16(s0) -8000dd5c: 00190713 addi a4,s2,1 -8000dd60: 00169993 slli s3,a3,0x1 -8000dd64: 00d986b3 add a3,s3,a3 -8000dd68: 01f6d993 srli s3,a3,0x1f -8000dd6c: 40b50cb3 sub s9,a0,a1 -8000dd70: 00d989b3 add s3,s3,a3 -8000dd74: 4019d993 srai s3,s3,0x1 -8000dd78: 01970733 add a4,a4,s9 -8000dd7c: 00098613 mv a2,s3 -8000dd80: 00e9f663 bgeu s3,a4,8000dd8c <__sfvwrite_r+0x17c> -8000dd84: 00070993 mv s3,a4 -8000dd88: 00070613 mv a2,a4 -8000dd8c: 4007f793 andi a5,a5,1024 -8000dd90: 2e078463 beqz a5,8000e078 <__sfvwrite_r+0x468> -8000dd94: 00060593 mv a1,a2 -8000dd98: 000a8513 mv a0,s5 -8000dd9c: f65f20ef jal ra,80000d00 <_malloc_r> -8000dda0: 00050d13 mv s10,a0 -8000dda4: 30050263 beqz a0,8000e0a8 <__sfvwrite_r+0x498> -8000dda8: 01042583 lw a1,16(s0) -8000ddac: 000c8613 mv a2,s9 -8000ddb0: 3d4000ef jal ra,8000e184 -8000ddb4: 00c45783 lhu a5,12(s0) -8000ddb8: b7f7f793 andi a5,a5,-1153 -8000ddbc: 0807e793 ori a5,a5,128 -8000ddc0: 00f41623 sh a5,12(s0) -8000ddc4: 019d0533 add a0,s10,s9 -8000ddc8: 419987b3 sub a5,s3,s9 -8000ddcc: 01a42823 sw s10,16(s0) -8000ddd0: 00a42023 sw a0,0(s0) -8000ddd4: 01342a23 sw s3,20(s0) -8000ddd8: 00090c93 mv s9,s2 -8000dddc: 00f42423 sw a5,8(s0) -8000dde0: 00090d13 mv s10,s2 -8000dde4: 000d0613 mv a2,s10 -8000dde8: 000b0593 mv a1,s6 -8000ddec: 4b4000ef jal ra,8000e2a0 -8000ddf0: 00842783 lw a5,8(s0) -8000ddf4: 00042603 lw a2,0(s0) -8000ddf8: 00090993 mv s3,s2 -8000ddfc: 41978cb3 sub s9,a5,s9 -8000de00: 01a60633 add a2,a2,s10 -8000de04: 01942423 sw s9,8(s0) -8000de08: 00c42023 sw a2,0(s0) -8000de0c: 00000913 li s2,0 -8000de10: 008a2783 lw a5,8(s4) -8000de14: 013b0b33 add s6,s6,s3 -8000de18: 413789b3 sub s3,a5,s3 -8000de1c: 013a2423 sw s3,8(s4) -8000de20: 0c098063 beqz s3,8000dee0 <__sfvwrite_r+0x2d0> -8000de24: 00842c83 lw s9,8(s0) -8000de28: 00042503 lw a0,0(s0) -8000de2c: 00c45783 lhu a5,12(s0) -8000de30: f00916e3 bnez s2,8000dd3c <__sfvwrite_r+0x12c> -8000de34: 0004ab03 lw s6,0(s1) -8000de38: 0044a903 lw s2,4(s1) -8000de3c: 00848493 addi s1,s1,8 -8000de40: ef9ff06f j 8000dd38 <__sfvwrite_r+0x128> -8000de44: 0044a983 lw s3,4(s1) -8000de48: 0004ab83 lw s7,0(s1) -8000de4c: 00848493 addi s1,s1,8 -8000de50: fe098ae3 beqz s3,8000de44 <__sfvwrite_r+0x234> -8000de54: 00098613 mv a2,s3 -8000de58: 00a00593 li a1,10 -8000de5c: 000b8513 mv a0,s7 -8000de60: 9ccfa0ef jal ra,8000802c -8000de64: 12050463 beqz a0,8000df8c <__sfvwrite_r+0x37c> -8000de68: 00150513 addi a0,a0,1 -8000de6c: 41750b33 sub s6,a0,s7 -8000de70: 000b0793 mv a5,s6 -8000de74: 00098c13 mv s8,s3 -8000de78: 0137f463 bgeu a5,s3,8000de80 <__sfvwrite_r+0x270> -8000de7c: 00078c13 mv s8,a5 -8000de80: 00042503 lw a0,0(s0) -8000de84: 01042783 lw a5,16(s0) -8000de88: 01442683 lw a3,20(s0) -8000de8c: 00a7f863 bgeu a5,a0,8000de9c <__sfvwrite_r+0x28c> -8000de90: 00842903 lw s2,8(s0) -8000de94: 01268933 add s2,a3,s2 -8000de98: 09894263 blt s2,s8,8000df1c <__sfvwrite_r+0x30c> -8000de9c: 1adc4863 blt s8,a3,8000e04c <__sfvwrite_r+0x43c> -8000dea0: 02442783 lw a5,36(s0) -8000dea4: 01c42583 lw a1,28(s0) -8000dea8: 000b8613 mv a2,s7 -8000deac: 000a8513 mv a0,s5 -8000deb0: 000780e7 jalr a5 -8000deb4: 00050913 mv s2,a0 -8000deb8: 08a05663 blez a0,8000df44 <__sfvwrite_r+0x334> -8000debc: 412b0b33 sub s6,s6,s2 -8000dec0: 00100513 li a0,1 -8000dec4: 160b0a63 beqz s6,8000e038 <__sfvwrite_r+0x428> -8000dec8: 008a2783 lw a5,8(s4) -8000decc: 012b8bb3 add s7,s7,s2 -8000ded0: 412989b3 sub s3,s3,s2 -8000ded4: 41278933 sub s2,a5,s2 -8000ded8: 012a2423 sw s2,8(s4) -8000dedc: 08091a63 bnez s2,8000df70 <__sfvwrite_r+0x360> -8000dee0: 00000513 li a0,0 -8000dee4: 02c12083 lw ra,44(sp) -8000dee8: 02812403 lw s0,40(sp) -8000deec: 02412483 lw s1,36(sp) -8000def0: 02012903 lw s2,32(sp) -8000def4: 01c12983 lw s3,28(sp) -8000def8: 01812a03 lw s4,24(sp) -8000defc: 01412a83 lw s5,20(sp) -8000df00: 01012b03 lw s6,16(sp) -8000df04: 00c12b83 lw s7,12(sp) -8000df08: 00812c03 lw s8,8(sp) -8000df0c: 00412c83 lw s9,4(sp) -8000df10: 00012d03 lw s10,0(sp) -8000df14: 03010113 addi sp,sp,48 -8000df18: 00008067 ret -8000df1c: 000b8593 mv a1,s7 -8000df20: 00090613 mv a2,s2 -8000df24: 37c000ef jal ra,8000e2a0 -8000df28: 00042783 lw a5,0(s0) -8000df2c: 00040593 mv a1,s0 -8000df30: 000a8513 mv a0,s5 -8000df34: 012787b3 add a5,a5,s2 -8000df38: 00f42023 sw a5,0(s0) -8000df3c: 8f1f60ef jal ra,8000482c <_fflush_r> -8000df40: f6050ee3 beqz a0,8000debc <__sfvwrite_r+0x2ac> -8000df44: 00c41783 lh a5,12(s0) -8000df48: 0407e793 ori a5,a5,64 -8000df4c: 00f41623 sh a5,12(s0) -8000df50: fff00513 li a0,-1 -8000df54: f91ff06f j 8000dee4 <__sfvwrite_r+0x2d4> -8000df58: 00000513 li a0,0 -8000df5c: 00008067 ret -8000df60: 00000b13 li s6,0 -8000df64: 00000513 li a0,0 -8000df68: 00000b93 li s7,0 -8000df6c: 00000993 li s3,0 -8000df70: ec098ae3 beqz s3,8000de44 <__sfvwrite_r+0x234> -8000df74: ee051ee3 bnez a0,8000de70 <__sfvwrite_r+0x260> -8000df78: 00098613 mv a2,s3 -8000df7c: 00a00593 li a1,10 -8000df80: 000b8513 mv a0,s7 -8000df84: 8a8fa0ef jal ra,8000802c -8000df88: ee0510e3 bnez a0,8000de68 <__sfvwrite_r+0x258> -8000df8c: 00198793 addi a5,s3,1 -8000df90: 00078b13 mv s6,a5 -8000df94: ee1ff06f j 8000de74 <__sfvwrite_r+0x264> -8000df98: 01042783 lw a5,16(s0) -8000df9c: 04a7e263 bltu a5,a0,8000dfe0 <__sfvwrite_r+0x3d0> -8000dfa0: 01442783 lw a5,20(s0) -8000dfa4: 02f96e63 bltu s2,a5,8000dfe0 <__sfvwrite_r+0x3d0> -8000dfa8: 00090693 mv a3,s2 -8000dfac: 012c7463 bgeu s8,s2,8000dfb4 <__sfvwrite_r+0x3a4> -8000dfb0: 000b8693 mv a3,s7 -8000dfb4: 02f6c6b3 div a3,a3,a5 -8000dfb8: 02442703 lw a4,36(s0) -8000dfbc: 01c42583 lw a1,28(s0) -8000dfc0: 000b0613 mv a2,s6 -8000dfc4: 000a8513 mv a0,s5 -8000dfc8: 02f686b3 mul a3,a3,a5 -8000dfcc: 000700e7 jalr a4 -8000dfd0: f6a05ae3 blez a0,8000df44 <__sfvwrite_r+0x334> -8000dfd4: 00050993 mv s3,a0 -8000dfd8: 41390933 sub s2,s2,s3 -8000dfdc: e35ff06f j 8000de10 <__sfvwrite_r+0x200> -8000dfe0: 000c8993 mv s3,s9 -8000dfe4: 01997463 bgeu s2,s9,8000dfec <__sfvwrite_r+0x3dc> -8000dfe8: 00090993 mv s3,s2 -8000dfec: 00098613 mv a2,s3 -8000dff0: 000b0593 mv a1,s6 -8000dff4: 2ac000ef jal ra,8000e2a0 -8000dff8: 00842783 lw a5,8(s0) -8000dffc: 00042703 lw a4,0(s0) -8000e000: 413787b3 sub a5,a5,s3 -8000e004: 01370733 add a4,a4,s3 -8000e008: 00f42423 sw a5,8(s0) -8000e00c: 00e42023 sw a4,0(s0) -8000e010: fc0794e3 bnez a5,8000dfd8 <__sfvwrite_r+0x3c8> -8000e014: 00040593 mv a1,s0 -8000e018: 000a8513 mv a0,s5 -8000e01c: 811f60ef jal ra,8000482c <_fflush_r> -8000e020: f20512e3 bnez a0,8000df44 <__sfvwrite_r+0x334> -8000e024: 41390933 sub s2,s2,s3 -8000e028: de9ff06f j 8000de10 <__sfvwrite_r+0x200> -8000e02c: 00090c93 mv s9,s2 -8000e030: 00090d13 mv s10,s2 -8000e034: db1ff06f j 8000dde4 <__sfvwrite_r+0x1d4> -8000e038: 00040593 mv a1,s0 -8000e03c: 000a8513 mv a0,s5 -8000e040: fecf60ef jal ra,8000482c <_fflush_r> -8000e044: e80502e3 beqz a0,8000dec8 <__sfvwrite_r+0x2b8> -8000e048: efdff06f j 8000df44 <__sfvwrite_r+0x334> -8000e04c: 000c0613 mv a2,s8 -8000e050: 000b8593 mv a1,s7 -8000e054: 24c000ef jal ra,8000e2a0 -8000e058: 00842703 lw a4,8(s0) -8000e05c: 00042783 lw a5,0(s0) -8000e060: 000c0913 mv s2,s8 -8000e064: 41870733 sub a4,a4,s8 -8000e068: 01878c33 add s8,a5,s8 -8000e06c: 00e42423 sw a4,8(s0) -8000e070: 01842023 sw s8,0(s0) -8000e074: e49ff06f j 8000debc <__sfvwrite_r+0x2ac> -8000e078: 000a8513 mv a0,s5 -8000e07c: 3ac000ef jal ra,8000e428 <_realloc_r> -8000e080: 00050d13 mv s10,a0 -8000e084: d40510e3 bnez a0,8000ddc4 <__sfvwrite_r+0x1b4> -8000e088: 01042583 lw a1,16(s0) -8000e08c: 000a8513 mv a0,s5 -8000e090: c99f60ef jal ra,80004d28 <_free_r> -8000e094: 00c41783 lh a5,12(s0) -8000e098: 00c00713 li a4,12 -8000e09c: 00eaa023 sw a4,0(s5) -8000e0a0: f7f7f793 andi a5,a5,-129 -8000e0a4: ea5ff06f j 8000df48 <__sfvwrite_r+0x338> -8000e0a8: 00c00793 li a5,12 -8000e0ac: 00faa023 sw a5,0(s5) -8000e0b0: 00c41783 lh a5,12(s0) -8000e0b4: e95ff06f j 8000df48 <__sfvwrite_r+0x338> -8000e0b8: fff00513 li a0,-1 -8000e0bc: e29ff06f j 8000dee4 <__sfvwrite_r+0x2d4> - -8000e0c0 <_isatty_r>: -8000e0c0: ff010113 addi sp,sp,-16 -8000e0c4: 00812423 sw s0,8(sp) -8000e0c8: 00912223 sw s1,4(sp) -8000e0cc: 00050493 mv s1,a0 -8000e0d0: 00058513 mv a0,a1 -8000e0d4: 00112623 sw ra,12(sp) -8000e0d8: 2001a623 sw zero,524(gp) # 80016d74 -8000e0dc: a5cf20ef jal ra,80000338 <_isatty> -8000e0e0: fff00793 li a5,-1 -8000e0e4: 00f50c63 beq a0,a5,8000e0fc <_isatty_r+0x3c> -8000e0e8: 00c12083 lw ra,12(sp) -8000e0ec: 00812403 lw s0,8(sp) -8000e0f0: 00412483 lw s1,4(sp) -8000e0f4: 01010113 addi sp,sp,16 -8000e0f8: 00008067 ret -8000e0fc: 20c1a783 lw a5,524(gp) # 80016d74 -8000e100: fe0784e3 beqz a5,8000e0e8 <_isatty_r+0x28> -8000e104: 00c12083 lw ra,12(sp) -8000e108: 00812403 lw s0,8(sp) -8000e10c: 00f4a023 sw a5,0(s1) -8000e110: 00412483 lw s1,4(sp) -8000e114: 01010113 addi sp,sp,16 -8000e118: 00008067 ret - -8000e11c <_lseek_r>: -8000e11c: ff010113 addi sp,sp,-16 -8000e120: 00058793 mv a5,a1 -8000e124: 00812423 sw s0,8(sp) -8000e128: 00912223 sw s1,4(sp) -8000e12c: 00060593 mv a1,a2 -8000e130: 00050493 mv s1,a0 -8000e134: 00078513 mv a0,a5 -8000e138: 00068613 mv a2,a3 -8000e13c: 00112623 sw ra,12(sp) -8000e140: 2001a623 sw zero,524(gp) # 80016d74 -8000e144: a18f20ef jal ra,8000035c <_lseek> -8000e148: fff00793 li a5,-1 -8000e14c: 00f50c63 beq a0,a5,8000e164 <_lseek_r+0x48> -8000e150: 00c12083 lw ra,12(sp) -8000e154: 00812403 lw s0,8(sp) -8000e158: 00412483 lw s1,4(sp) -8000e15c: 01010113 addi sp,sp,16 -8000e160: 00008067 ret -8000e164: 20c1a783 lw a5,524(gp) # 80016d74 -8000e168: fe0784e3 beqz a5,8000e150 <_lseek_r+0x34> -8000e16c: 00c12083 lw ra,12(sp) -8000e170: 00812403 lw s0,8(sp) -8000e174: 00f4a023 sw a5,0(s1) -8000e178: 00412483 lw s1,4(sp) -8000e17c: 01010113 addi sp,sp,16 -8000e180: 00008067 ret - -8000e184 : -8000e184: 00a5c7b3 xor a5,a1,a0 -8000e188: 0037f793 andi a5,a5,3 -8000e18c: 00c508b3 add a7,a0,a2 -8000e190: 06079263 bnez a5,8000e1f4 -8000e194: 00300793 li a5,3 -8000e198: 04c7fe63 bgeu a5,a2,8000e1f4 -8000e19c: 00357793 andi a5,a0,3 -8000e1a0: 00050713 mv a4,a0 -8000e1a4: 06079863 bnez a5,8000e214 -8000e1a8: ffc8f613 andi a2,a7,-4 -8000e1ac: fe060793 addi a5,a2,-32 -8000e1b0: 08f76c63 bltu a4,a5,8000e248 -8000e1b4: 02c77c63 bgeu a4,a2,8000e1ec -8000e1b8: 00058693 mv a3,a1 -8000e1bc: 00070793 mv a5,a4 -8000e1c0: 0006a803 lw a6,0(a3) # 2000 <_start-0x7fffe000> -8000e1c4: 00478793 addi a5,a5,4 -8000e1c8: 00468693 addi a3,a3,4 -8000e1cc: ff07ae23 sw a6,-4(a5) -8000e1d0: fec7e8e3 bltu a5,a2,8000e1c0 -8000e1d4: fff60793 addi a5,a2,-1 -8000e1d8: 40e787b3 sub a5,a5,a4 -8000e1dc: ffc7f793 andi a5,a5,-4 -8000e1e0: 00478793 addi a5,a5,4 -8000e1e4: 00f70733 add a4,a4,a5 -8000e1e8: 00f585b3 add a1,a1,a5 -8000e1ec: 01176863 bltu a4,a7,8000e1fc -8000e1f0: 00008067 ret -8000e1f4: 00050713 mv a4,a0 -8000e1f8: ff157ce3 bgeu a0,a7,8000e1f0 -8000e1fc: 0005c783 lbu a5,0(a1) -8000e200: 00170713 addi a4,a4,1 -8000e204: 00158593 addi a1,a1,1 -8000e208: fef70fa3 sb a5,-1(a4) -8000e20c: ff1768e3 bltu a4,a7,8000e1fc -8000e210: 00008067 ret -8000e214: 0005c683 lbu a3,0(a1) -8000e218: 00170713 addi a4,a4,1 -8000e21c: 00377793 andi a5,a4,3 -8000e220: fed70fa3 sb a3,-1(a4) -8000e224: 00158593 addi a1,a1,1 -8000e228: f80780e3 beqz a5,8000e1a8 -8000e22c: 0005c683 lbu a3,0(a1) -8000e230: 00170713 addi a4,a4,1 -8000e234: 00377793 andi a5,a4,3 -8000e238: fed70fa3 sb a3,-1(a4) -8000e23c: 00158593 addi a1,a1,1 -8000e240: fc079ae3 bnez a5,8000e214 -8000e244: f65ff06f j 8000e1a8 -8000e248: 0005a683 lw a3,0(a1) -8000e24c: 0045a283 lw t0,4(a1) -8000e250: 0085af83 lw t6,8(a1) -8000e254: 00c5af03 lw t5,12(a1) -8000e258: 0105ae83 lw t4,16(a1) -8000e25c: 0145ae03 lw t3,20(a1) -8000e260: 0185a303 lw t1,24(a1) -8000e264: 01c5a803 lw a6,28(a1) -8000e268: 02458593 addi a1,a1,36 -8000e26c: 00d72023 sw a3,0(a4) -8000e270: ffc5a683 lw a3,-4(a1) -8000e274: 00572223 sw t0,4(a4) -8000e278: 01f72423 sw t6,8(a4) -8000e27c: 01e72623 sw t5,12(a4) -8000e280: 01d72823 sw t4,16(a4) -8000e284: 01c72a23 sw t3,20(a4) -8000e288: 00672c23 sw t1,24(a4) -8000e28c: 01072e23 sw a6,28(a4) -8000e290: 02470713 addi a4,a4,36 -8000e294: fed72e23 sw a3,-4(a4) -8000e298: faf768e3 bltu a4,a5,8000e248 -8000e29c: f19ff06f j 8000e1b4 - -8000e2a0 : -8000e2a0: 02a5f663 bgeu a1,a0,8000e2cc -8000e2a4: 00c587b3 add a5,a1,a2 -8000e2a8: 02f57263 bgeu a0,a5,8000e2cc -8000e2ac: 00c50733 add a4,a0,a2 -8000e2b0: 0e060a63 beqz a2,8000e3a4 -8000e2b4: fff78793 addi a5,a5,-1 -8000e2b8: 0007c683 lbu a3,0(a5) -8000e2bc: fff70713 addi a4,a4,-1 -8000e2c0: 00d70023 sb a3,0(a4) -8000e2c4: fef598e3 bne a1,a5,8000e2b4 -8000e2c8: 00008067 ret -8000e2cc: 00f00793 li a5,15 -8000e2d0: 02c7e863 bltu a5,a2,8000e300 -8000e2d4: 00050793 mv a5,a0 -8000e2d8: fff60693 addi a3,a2,-1 -8000e2dc: 0c060c63 beqz a2,8000e3b4 -8000e2e0: 00168693 addi a3,a3,1 -8000e2e4: 00d786b3 add a3,a5,a3 -8000e2e8: 00158593 addi a1,a1,1 -8000e2ec: fff5c703 lbu a4,-1(a1) -8000e2f0: 00178793 addi a5,a5,1 -8000e2f4: fee78fa3 sb a4,-1(a5) -8000e2f8: fed798e3 bne a5,a3,8000e2e8 -8000e2fc: 00008067 ret -8000e300: 00a5e7b3 or a5,a1,a0 -8000e304: 0037f793 andi a5,a5,3 -8000e308: 0a079063 bnez a5,8000e3a8 -8000e30c: ff060893 addi a7,a2,-16 -8000e310: ff08f893 andi a7,a7,-16 -8000e314: 01088893 addi a7,a7,16 -8000e318: 01150833 add a6,a0,a7 -8000e31c: 00058713 mv a4,a1 -8000e320: 00050793 mv a5,a0 -8000e324: 00072683 lw a3,0(a4) -8000e328: 01078793 addi a5,a5,16 -8000e32c: 01070713 addi a4,a4,16 -8000e330: fed7a823 sw a3,-16(a5) -8000e334: ff472683 lw a3,-12(a4) -8000e338: fed7aa23 sw a3,-12(a5) -8000e33c: ff872683 lw a3,-8(a4) -8000e340: fed7ac23 sw a3,-8(a5) -8000e344: ffc72683 lw a3,-4(a4) -8000e348: fed7ae23 sw a3,-4(a5) -8000e34c: fcf81ce3 bne a6,a5,8000e324 -8000e350: 00c67713 andi a4,a2,12 -8000e354: 011585b3 add a1,a1,a7 -8000e358: 00f67813 andi a6,a2,15 -8000e35c: 04070e63 beqz a4,8000e3b8 -8000e360: 00058713 mv a4,a1 -8000e364: 00078893 mv a7,a5 -8000e368: 00300e13 li t3,3 -8000e36c: 00470713 addi a4,a4,4 -8000e370: ffc72303 lw t1,-4(a4) -8000e374: 00488893 addi a7,a7,4 -8000e378: 40e806b3 sub a3,a6,a4 -8000e37c: fe68ae23 sw t1,-4(a7) -8000e380: 00d586b3 add a3,a1,a3 -8000e384: fede64e3 bltu t3,a3,8000e36c -8000e388: ffc80713 addi a4,a6,-4 -8000e38c: ffc77713 andi a4,a4,-4 -8000e390: 00470713 addi a4,a4,4 -8000e394: 00367613 andi a2,a2,3 -8000e398: 00e787b3 add a5,a5,a4 -8000e39c: 00e585b3 add a1,a1,a4 -8000e3a0: f39ff06f j 8000e2d8 -8000e3a4: 00008067 ret -8000e3a8: fff60693 addi a3,a2,-1 -8000e3ac: 00050793 mv a5,a0 -8000e3b0: f31ff06f j 8000e2e0 -8000e3b4: 00008067 ret -8000e3b8: 00080613 mv a2,a6 -8000e3bc: f1dff06f j 8000e2d8 - -8000e3c0 <_read_r>: -8000e3c0: ff010113 addi sp,sp,-16 -8000e3c4: 00058793 mv a5,a1 -8000e3c8: 00812423 sw s0,8(sp) -8000e3cc: 00912223 sw s1,4(sp) -8000e3d0: 00060593 mv a1,a2 -8000e3d4: 00050493 mv s1,a0 -8000e3d8: 00078513 mv a0,a5 -8000e3dc: 00068613 mv a2,a3 -8000e3e0: 00112623 sw ra,12(sp) -8000e3e4: 2001a623 sw zero,524(gp) # 80016d74 -8000e3e8: 83cf20ef jal ra,80000424 <_read> -8000e3ec: fff00793 li a5,-1 -8000e3f0: 00f50c63 beq a0,a5,8000e408 <_read_r+0x48> -8000e3f4: 00c12083 lw ra,12(sp) -8000e3f8: 00812403 lw s0,8(sp) -8000e3fc: 00412483 lw s1,4(sp) -8000e400: 01010113 addi sp,sp,16 -8000e404: 00008067 ret -8000e408: 20c1a783 lw a5,524(gp) # 80016d74 -8000e40c: fe0784e3 beqz a5,8000e3f4 <_read_r+0x34> -8000e410: 00c12083 lw ra,12(sp) -8000e414: 00812403 lw s0,8(sp) -8000e418: 00f4a023 sw a5,0(s1) -8000e41c: 00412483 lw s1,4(sp) -8000e420: 01010113 addi sp,sp,16 -8000e424: 00008067 ret - -8000e428 <_realloc_r>: -8000e428: fd010113 addi sp,sp,-48 -8000e42c: 01312e23 sw s3,28(sp) -8000e430: 02112623 sw ra,44(sp) -8000e434: 02812423 sw s0,40(sp) -8000e438: 02912223 sw s1,36(sp) -8000e43c: 03212023 sw s2,32(sp) -8000e440: 01412c23 sw s4,24(sp) -8000e444: 01512a23 sw s5,20(sp) -8000e448: 01612823 sw s6,16(sp) -8000e44c: 01712623 sw s7,12(sp) -8000e450: 01812423 sw s8,8(sp) -8000e454: 00060993 mv s3,a2 -8000e458: 22058a63 beqz a1,8000e68c <_realloc_r+0x264> -8000e45c: 00058b13 mv s6,a1 -8000e460: 00050a93 mv s5,a0 -8000e464: 934f30ef jal ra,80001598 <__malloc_lock> -8000e468: 00b98413 addi s0,s3,11 -8000e46c: 01600793 li a5,22 -8000e470: 0e87fc63 bgeu a5,s0,8000e568 <_realloc_r+0x140> -8000e474: ff847413 andi s0,s0,-8 -8000e478: 00040713 mv a4,s0 -8000e47c: 0e044c63 bltz s0,8000e574 <_realloc_r+0x14c> -8000e480: 0f346a63 bltu s0,s3,8000e574 <_realloc_r+0x14c> -8000e484: ffcb2783 lw a5,-4(s6) # 7ffffffc <__BSS_END__+0xfffe9284> -8000e488: ff8b0913 addi s2,s6,-8 -8000e48c: ffc7f493 andi s1,a5,-4 -8000e490: 00990a33 add s4,s2,s1 -8000e494: 1ae4d263 bge s1,a4,8000e638 <_realloc_r+0x210> -8000e498: c2818b93 addi s7,gp,-984 # 80016790 <__malloc_av_> -8000e49c: 008ba603 lw a2,8(s7) # 80000008 <__BSS_END__+0xfffe9290> -8000e4a0: 004a2683 lw a3,4(s4) -8000e4a4: 25460663 beq a2,s4,8000e6f0 <_realloc_r+0x2c8> -8000e4a8: ffe6f613 andi a2,a3,-2 -8000e4ac: 00ca0633 add a2,s4,a2 -8000e4b0: 00462603 lw a2,4(a2) -8000e4b4: 00167613 andi a2,a2,1 -8000e4b8: 1a061c63 bnez a2,8000e670 <_realloc_r+0x248> -8000e4bc: ffc6f693 andi a3,a3,-4 -8000e4c0: 00d48633 add a2,s1,a3 -8000e4c4: 34e65663 bge a2,a4,8000e810 <_realloc_r+0x3e8> -8000e4c8: 0017f793 andi a5,a5,1 -8000e4cc: 02079463 bnez a5,8000e4f4 <_realloc_r+0xcc> -8000e4d0: ff8b2c03 lw s8,-8(s6) -8000e4d4: 41890c33 sub s8,s2,s8 -8000e4d8: 004c2783 lw a5,4(s8) -8000e4dc: ffc7f793 andi a5,a5,-4 -8000e4e0: 00d786b3 add a3,a5,a3 -8000e4e4: 00968bb3 add s7,a3,s1 -8000e4e8: 0cebd663 bge s7,a4,8000e5b4 <_realloc_r+0x18c> -8000e4ec: 00f48bb3 add s7,s1,a5 -8000e4f0: 34ebd863 bge s7,a4,8000e840 <_realloc_r+0x418> -8000e4f4: 00098593 mv a1,s3 -8000e4f8: 000a8513 mv a0,s5 -8000e4fc: 805f20ef jal ra,80000d00 <_malloc_r> -8000e500: 00050993 mv s3,a0 -8000e504: 04050c63 beqz a0,8000e55c <_realloc_r+0x134> -8000e508: ffcb2783 lw a5,-4(s6) -8000e50c: ff850713 addi a4,a0,-8 -8000e510: ffe7f793 andi a5,a5,-2 -8000e514: 00f907b3 add a5,s2,a5 -8000e518: 30e78a63 beq a5,a4,8000e82c <_realloc_r+0x404> -8000e51c: ffc48613 addi a2,s1,-4 -8000e520: 02400793 li a5,36 -8000e524: 38c7ea63 bltu a5,a2,8000e8b8 <_realloc_r+0x490> -8000e528: 01300713 li a4,19 -8000e52c: 000b2683 lw a3,0(s6) -8000e530: 28c76463 bltu a4,a2,8000e7b8 <_realloc_r+0x390> -8000e534: 00050793 mv a5,a0 -8000e538: 000b0713 mv a4,s6 -8000e53c: 00d7a023 sw a3,0(a5) -8000e540: 00472683 lw a3,4(a4) -8000e544: 00d7a223 sw a3,4(a5) -8000e548: 00872703 lw a4,8(a4) -8000e54c: 00e7a423 sw a4,8(a5) -8000e550: 000b0593 mv a1,s6 -8000e554: 000a8513 mv a0,s5 -8000e558: fd0f60ef jal ra,80004d28 <_free_r> -8000e55c: 000a8513 mv a0,s5 -8000e560: 83cf30ef jal ra,8000159c <__malloc_unlock> -8000e564: 01c0006f j 8000e580 <_realloc_r+0x158> -8000e568: 01000413 li s0,16 -8000e56c: 01000713 li a4,16 -8000e570: f1347ae3 bgeu s0,s3,8000e484 <_realloc_r+0x5c> -8000e574: 00c00793 li a5,12 -8000e578: 00faa023 sw a5,0(s5) -8000e57c: 00000993 li s3,0 -8000e580: 02c12083 lw ra,44(sp) -8000e584: 02812403 lw s0,40(sp) -8000e588: 00098513 mv a0,s3 -8000e58c: 02412483 lw s1,36(sp) -8000e590: 02012903 lw s2,32(sp) -8000e594: 01c12983 lw s3,28(sp) -8000e598: 01812a03 lw s4,24(sp) -8000e59c: 01412a83 lw s5,20(sp) -8000e5a0: 01012b03 lw s6,16(sp) -8000e5a4: 00c12b83 lw s7,12(sp) -8000e5a8: 00812c03 lw s8,8(sp) -8000e5ac: 03010113 addi sp,sp,48 -8000e5b0: 00008067 ret -8000e5b4: 00ca2783 lw a5,12(s4) -8000e5b8: 008a2703 lw a4,8(s4) -8000e5bc: ffc48613 addi a2,s1,-4 -8000e5c0: 02400693 li a3,36 -8000e5c4: 00f72623 sw a5,12(a4) -8000e5c8: 00e7a423 sw a4,8(a5) -8000e5cc: 008c2703 lw a4,8(s8) -8000e5d0: 00cc2783 lw a5,12(s8) -8000e5d4: 008c0993 addi s3,s8,8 -8000e5d8: 017c0a33 add s4,s8,s7 -8000e5dc: 00f72623 sw a5,12(a4) -8000e5e0: 00e7a423 sw a4,8(a5) -8000e5e4: 2ec6e063 bltu a3,a2,8000e8c4 <_realloc_r+0x49c> -8000e5e8: 01300693 li a3,19 -8000e5ec: 000b2703 lw a4,0(s6) -8000e5f0: 00098793 mv a5,s3 -8000e5f4: 02c6f263 bgeu a3,a2,8000e618 <_realloc_r+0x1f0> -8000e5f8: 00ec2423 sw a4,8(s8) -8000e5fc: 004b2703 lw a4,4(s6) -8000e600: 01b00793 li a5,27 -8000e604: 00ec2623 sw a4,12(s8) -8000e608: 008b2703 lw a4,8(s6) -8000e60c: 32c7ee63 bltu a5,a2,8000e948 <_realloc_r+0x520> -8000e610: 010c0793 addi a5,s8,16 -8000e614: 008b0b13 addi s6,s6,8 -8000e618: 00e7a023 sw a4,0(a5) -8000e61c: 004b2703 lw a4,4(s6) -8000e620: 000b8493 mv s1,s7 -8000e624: 000c0913 mv s2,s8 -8000e628: 00e7a223 sw a4,4(a5) -8000e62c: 008b2703 lw a4,8(s6) -8000e630: 00098b13 mv s6,s3 -8000e634: 00e7a423 sw a4,8(a5) -8000e638: 00492603 lw a2,4(s2) -8000e63c: 408487b3 sub a5,s1,s0 -8000e640: 00f00713 li a4,15 -8000e644: 00167613 andi a2,a2,1 -8000e648: 06f76c63 bltu a4,a5,8000e6c0 <_realloc_r+0x298> -8000e64c: 00c4e633 or a2,s1,a2 -8000e650: 00c92223 sw a2,4(s2) -8000e654: 004a2783 lw a5,4(s4) -8000e658: 0017e793 ori a5,a5,1 -8000e65c: 00fa2223 sw a5,4(s4) -8000e660: 000a8513 mv a0,s5 -8000e664: f39f20ef jal ra,8000159c <__malloc_unlock> -8000e668: 000b0993 mv s3,s6 -8000e66c: f15ff06f j 8000e580 <_realloc_r+0x158> -8000e670: 0017f793 andi a5,a5,1 -8000e674: e80790e3 bnez a5,8000e4f4 <_realloc_r+0xcc> -8000e678: ff8b2c03 lw s8,-8(s6) -8000e67c: 41890c33 sub s8,s2,s8 -8000e680: 004c2783 lw a5,4(s8) -8000e684: ffc7f793 andi a5,a5,-4 -8000e688: e65ff06f j 8000e4ec <_realloc_r+0xc4> -8000e68c: 02812403 lw s0,40(sp) -8000e690: 02c12083 lw ra,44(sp) -8000e694: 02412483 lw s1,36(sp) -8000e698: 02012903 lw s2,32(sp) -8000e69c: 01c12983 lw s3,28(sp) -8000e6a0: 01812a03 lw s4,24(sp) -8000e6a4: 01412a83 lw s5,20(sp) -8000e6a8: 01012b03 lw s6,16(sp) -8000e6ac: 00c12b83 lw s7,12(sp) -8000e6b0: 00812c03 lw s8,8(sp) -8000e6b4: 00060593 mv a1,a2 -8000e6b8: 03010113 addi sp,sp,48 -8000e6bc: e44f206f j 80000d00 <_malloc_r> -8000e6c0: 00866633 or a2,a2,s0 -8000e6c4: 00c92223 sw a2,4(s2) -8000e6c8: 008905b3 add a1,s2,s0 -8000e6cc: 0017e793 ori a5,a5,1 -8000e6d0: 00f5a223 sw a5,4(a1) -8000e6d4: 004a2783 lw a5,4(s4) -8000e6d8: 00858593 addi a1,a1,8 -8000e6dc: 000a8513 mv a0,s5 -8000e6e0: 0017e793 ori a5,a5,1 -8000e6e4: 00fa2223 sw a5,4(s4) -8000e6e8: e40f60ef jal ra,80004d28 <_free_r> -8000e6ec: f75ff06f j 8000e660 <_realloc_r+0x238> -8000e6f0: ffc6f693 andi a3,a3,-4 -8000e6f4: 00d48633 add a2,s1,a3 -8000e6f8: 01040593 addi a1,s0,16 -8000e6fc: 0eb65063 bge a2,a1,8000e7dc <_realloc_r+0x3b4> -8000e700: 0017f793 andi a5,a5,1 -8000e704: de0798e3 bnez a5,8000e4f4 <_realloc_r+0xcc> -8000e708: ff8b2c03 lw s8,-8(s6) -8000e70c: 41890c33 sub s8,s2,s8 -8000e710: 004c2783 lw a5,4(s8) -8000e714: ffc7f793 andi a5,a5,-4 -8000e718: 00d786b3 add a3,a5,a3 -8000e71c: 00968a33 add s4,a3,s1 -8000e720: dcba46e3 blt s4,a1,8000e4ec <_realloc_r+0xc4> -8000e724: 00cc2783 lw a5,12(s8) -8000e728: 008c2703 lw a4,8(s8) -8000e72c: ffc48613 addi a2,s1,-4 -8000e730: 02400693 li a3,36 -8000e734: 00f72623 sw a5,12(a4) -8000e738: 00e7a423 sw a4,8(a5) -8000e73c: 008c0993 addi s3,s8,8 -8000e740: 22c6e663 bltu a3,a2,8000e96c <_realloc_r+0x544> -8000e744: 01300593 li a1,19 -8000e748: 000b2703 lw a4,0(s6) -8000e74c: 00098793 mv a5,s3 -8000e750: 02c5f263 bgeu a1,a2,8000e774 <_realloc_r+0x34c> -8000e754: 00ec2423 sw a4,8(s8) -8000e758: 004b2703 lw a4,4(s6) -8000e75c: 01b00793 li a5,27 -8000e760: 00ec2623 sw a4,12(s8) -8000e764: 24c7ea63 bltu a5,a2,8000e9b8 <_realloc_r+0x590> -8000e768: 008b2703 lw a4,8(s6) -8000e76c: 010c0793 addi a5,s8,16 -8000e770: 008b0b13 addi s6,s6,8 -8000e774: 00e7a023 sw a4,0(a5) -8000e778: 004b2703 lw a4,4(s6) -8000e77c: 00e7a223 sw a4,4(a5) -8000e780: 008b2703 lw a4,8(s6) -8000e784: 00e7a423 sw a4,8(a5) -8000e788: 008c0733 add a4,s8,s0 -8000e78c: 408a07b3 sub a5,s4,s0 -8000e790: 00eba423 sw a4,8(s7) -8000e794: 0017e793 ori a5,a5,1 -8000e798: 00f72223 sw a5,4(a4) -8000e79c: 004c2783 lw a5,4(s8) -8000e7a0: 000a8513 mv a0,s5 -8000e7a4: 0017f793 andi a5,a5,1 -8000e7a8: 0087e433 or s0,a5,s0 -8000e7ac: 008c2223 sw s0,4(s8) -8000e7b0: dedf20ef jal ra,8000159c <__malloc_unlock> -8000e7b4: dcdff06f j 8000e580 <_realloc_r+0x158> -8000e7b8: 00d52023 sw a3,0(a0) -8000e7bc: 004b2683 lw a3,4(s6) -8000e7c0: 01b00713 li a4,27 -8000e7c4: 00d52223 sw a3,4(a0) -8000e7c8: 10c76c63 bltu a4,a2,8000e8e0 <_realloc_r+0x4b8> -8000e7cc: 008b0713 addi a4,s6,8 -8000e7d0: 00850793 addi a5,a0,8 -8000e7d4: 008b2683 lw a3,8(s6) -8000e7d8: d65ff06f j 8000e53c <_realloc_r+0x114> -8000e7dc: 00890933 add s2,s2,s0 -8000e7e0: 408607b3 sub a5,a2,s0 -8000e7e4: 012ba423 sw s2,8(s7) -8000e7e8: 0017e793 ori a5,a5,1 -8000e7ec: 00f92223 sw a5,4(s2) -8000e7f0: ffcb2783 lw a5,-4(s6) -8000e7f4: 000a8513 mv a0,s5 -8000e7f8: 000b0993 mv s3,s6 -8000e7fc: 0017f793 andi a5,a5,1 -8000e800: 0087e433 or s0,a5,s0 -8000e804: fe8b2e23 sw s0,-4(s6) -8000e808: d95f20ef jal ra,8000159c <__malloc_unlock> -8000e80c: d75ff06f j 8000e580 <_realloc_r+0x158> -8000e810: 00ca2783 lw a5,12(s4) -8000e814: 008a2703 lw a4,8(s4) -8000e818: 00060493 mv s1,a2 -8000e81c: 00c90a33 add s4,s2,a2 -8000e820: 00f72623 sw a5,12(a4) -8000e824: 00e7a423 sw a4,8(a5) -8000e828: e11ff06f j 8000e638 <_realloc_r+0x210> -8000e82c: ffc52783 lw a5,-4(a0) -8000e830: ffc7f793 andi a5,a5,-4 -8000e834: 00f484b3 add s1,s1,a5 -8000e838: 00990a33 add s4,s2,s1 -8000e83c: dfdff06f j 8000e638 <_realloc_r+0x210> -8000e840: 00cc2703 lw a4,12(s8) -8000e844: 008c2683 lw a3,8(s8) -8000e848: ffc48613 addi a2,s1,-4 -8000e84c: 02400593 li a1,36 -8000e850: 00e6a623 sw a4,12(a3) -8000e854: 00d72423 sw a3,8(a4) -8000e858: 008c0993 addi s3,s8,8 -8000e85c: 017c0a33 add s4,s8,s7 -8000e860: 06c5e263 bltu a1,a2,8000e8c4 <_realloc_r+0x49c> -8000e864: 01300513 li a0,19 -8000e868: 000b2683 lw a3,0(s6) -8000e86c: 00098713 mv a4,s3 -8000e870: 02c57263 bgeu a0,a2,8000e894 <_realloc_r+0x46c> -8000e874: 00dc2423 sw a3,8(s8) -8000e878: 004b2703 lw a4,4(s6) -8000e87c: 01b00793 li a5,27 -8000e880: 00ec2623 sw a4,12(s8) -8000e884: 0ac7e063 bltu a5,a2,8000e924 <_realloc_r+0x4fc> -8000e888: 008b2683 lw a3,8(s6) -8000e88c: 010c0713 addi a4,s8,16 -8000e890: 008b0b13 addi s6,s6,8 -8000e894: 00d72023 sw a3,0(a4) -8000e898: 004b2683 lw a3,4(s6) -8000e89c: 000b8493 mv s1,s7 -8000e8a0: 000c0913 mv s2,s8 -8000e8a4: 00d72223 sw a3,4(a4) -8000e8a8: 008b2783 lw a5,8(s6) -8000e8ac: 00098b13 mv s6,s3 -8000e8b0: 00f72423 sw a5,8(a4) -8000e8b4: d85ff06f j 8000e638 <_realloc_r+0x210> -8000e8b8: 000b0593 mv a1,s6 -8000e8bc: 9e5ff0ef jal ra,8000e2a0 -8000e8c0: c91ff06f j 8000e550 <_realloc_r+0x128> -8000e8c4: 000b0593 mv a1,s6 -8000e8c8: 00098513 mv a0,s3 -8000e8cc: 9d5ff0ef jal ra,8000e2a0 -8000e8d0: 00098b13 mv s6,s3 -8000e8d4: 000b8493 mv s1,s7 -8000e8d8: 000c0913 mv s2,s8 -8000e8dc: d5dff06f j 8000e638 <_realloc_r+0x210> -8000e8e0: 008b2703 lw a4,8(s6) -8000e8e4: 00e52423 sw a4,8(a0) -8000e8e8: 00cb2703 lw a4,12(s6) -8000e8ec: 00e52623 sw a4,12(a0) -8000e8f0: 00f60a63 beq a2,a5,8000e904 <_realloc_r+0x4dc> -8000e8f4: 010b0713 addi a4,s6,16 -8000e8f8: 01050793 addi a5,a0,16 -8000e8fc: 010b2683 lw a3,16(s6) -8000e900: c3dff06f j 8000e53c <_realloc_r+0x114> -8000e904: 010b2683 lw a3,16(s6) -8000e908: 018b0713 addi a4,s6,24 -8000e90c: 01850793 addi a5,a0,24 -8000e910: 00d52823 sw a3,16(a0) -8000e914: 014b2683 lw a3,20(s6) -8000e918: 00d52a23 sw a3,20(a0) -8000e91c: 018b2683 lw a3,24(s6) -8000e920: c1dff06f j 8000e53c <_realloc_r+0x114> -8000e924: 008b2783 lw a5,8(s6) -8000e928: 00fc2823 sw a5,16(s8) -8000e92c: 00cb2783 lw a5,12(s6) -8000e930: 00fc2a23 sw a5,20(s8) -8000e934: 04b60463 beq a2,a1,8000e97c <_realloc_r+0x554> -8000e938: 010b2683 lw a3,16(s6) -8000e93c: 018c0713 addi a4,s8,24 -8000e940: 010b0b13 addi s6,s6,16 -8000e944: f51ff06f j 8000e894 <_realloc_r+0x46c> -8000e948: 00ec2823 sw a4,16(s8) -8000e94c: 00cb2703 lw a4,12(s6) -8000e950: 02400793 li a5,36 -8000e954: 00ec2a23 sw a4,20(s8) -8000e958: 010b2703 lw a4,16(s6) -8000e95c: 04f60063 beq a2,a5,8000e99c <_realloc_r+0x574> -8000e960: 018c0793 addi a5,s8,24 -8000e964: 010b0b13 addi s6,s6,16 -8000e968: cb1ff06f j 8000e618 <_realloc_r+0x1f0> -8000e96c: 000b0593 mv a1,s6 -8000e970: 00098513 mv a0,s3 -8000e974: 92dff0ef jal ra,8000e2a0 -8000e978: e11ff06f j 8000e788 <_realloc_r+0x360> -8000e97c: 010b2783 lw a5,16(s6) -8000e980: 020c0713 addi a4,s8,32 -8000e984: 018b0b13 addi s6,s6,24 -8000e988: 00fc2c23 sw a5,24(s8) -8000e98c: ffcb2783 lw a5,-4(s6) -8000e990: 00fc2e23 sw a5,28(s8) -8000e994: 000b2683 lw a3,0(s6) -8000e998: efdff06f j 8000e894 <_realloc_r+0x46c> -8000e99c: 00ec2c23 sw a4,24(s8) -8000e9a0: 014b2703 lw a4,20(s6) -8000e9a4: 020c0793 addi a5,s8,32 -8000e9a8: 018b0b13 addi s6,s6,24 -8000e9ac: 00ec2e23 sw a4,28(s8) -8000e9b0: 000b2703 lw a4,0(s6) -8000e9b4: c65ff06f j 8000e618 <_realloc_r+0x1f0> -8000e9b8: 008b2783 lw a5,8(s6) -8000e9bc: 00fc2823 sw a5,16(s8) -8000e9c0: 00cb2783 lw a5,12(s6) -8000e9c4: 00fc2a23 sw a5,20(s8) -8000e9c8: 010b2703 lw a4,16(s6) -8000e9cc: 00d60863 beq a2,a3,8000e9dc <_realloc_r+0x5b4> -8000e9d0: 018c0793 addi a5,s8,24 -8000e9d4: 010b0b13 addi s6,s6,16 -8000e9d8: d9dff06f j 8000e774 <_realloc_r+0x34c> -8000e9dc: 00ec2c23 sw a4,24(s8) -8000e9e0: 014b2703 lw a4,20(s6) -8000e9e4: 020c0793 addi a5,s8,32 -8000e9e8: 018b0b13 addi s6,s6,24 -8000e9ec: 00ec2e23 sw a4,28(s8) -8000e9f0: 000b2703 lw a4,0(s6) -8000e9f4: d81ff06f j 8000e774 <_realloc_r+0x34c> - -8000e9f8 <__ssprint_r>: -8000e9f8: 00862783 lw a5,8(a2) -8000e9fc: fd010113 addi sp,sp,-48 -8000ea00: 01512a23 sw s5,20(sp) -8000ea04: 02112623 sw ra,44(sp) -8000ea08: 02812423 sw s0,40(sp) -8000ea0c: 02912223 sw s1,36(sp) -8000ea10: 03212023 sw s2,32(sp) -8000ea14: 01312e23 sw s3,28(sp) -8000ea18: 01412c23 sw s4,24(sp) -8000ea1c: 01612823 sw s6,16(sp) -8000ea20: 01712623 sw s7,12(sp) -8000ea24: 01812423 sw s8,8(sp) -8000ea28: 00060a93 mv s5,a2 -8000ea2c: 14078863 beqz a5,8000eb7c <__ssprint_r+0x184> -8000ea30: 00050b13 mv s6,a0 -8000ea34: 00058413 mv s0,a1 -8000ea38: 00062983 lw s3,0(a2) -8000ea3c: 0005a503 lw a0,0(a1) -8000ea40: 0085a483 lw s1,8(a1) -8000ea44: 0d40006f j 8000eb18 <__ssprint_r+0x120> -8000ea48: 00c45783 lhu a5,12(s0) -8000ea4c: 4807f713 andi a4,a5,1152 -8000ea50: 08070a63 beqz a4,8000eae4 <__ssprint_r+0xec> -8000ea54: 01442683 lw a3,20(s0) -8000ea58: 01042583 lw a1,16(s0) -8000ea5c: 00190713 addi a4,s2,1 -8000ea60: 00169493 slli s1,a3,0x1 -8000ea64: 00d486b3 add a3,s1,a3 -8000ea68: 01f6d493 srli s1,a3,0x1f -8000ea6c: 40b50a33 sub s4,a0,a1 -8000ea70: 00d484b3 add s1,s1,a3 -8000ea74: 4014d493 srai s1,s1,0x1 -8000ea78: 01470733 add a4,a4,s4 -8000ea7c: 00048613 mv a2,s1 -8000ea80: 00e4f663 bgeu s1,a4,8000ea8c <__ssprint_r+0x94> -8000ea84: 00070493 mv s1,a4 -8000ea88: 00070613 mv a2,a4 -8000ea8c: 4007f793 andi a5,a5,1024 -8000ea90: 0a078663 beqz a5,8000eb3c <__ssprint_r+0x144> -8000ea94: 00060593 mv a1,a2 -8000ea98: 000b0513 mv a0,s6 -8000ea9c: a64f20ef jal ra,80000d00 <_malloc_r> -8000eaa0: 00050c13 mv s8,a0 -8000eaa4: 0a050a63 beqz a0,8000eb58 <__ssprint_r+0x160> -8000eaa8: 01042583 lw a1,16(s0) -8000eaac: 000a0613 mv a2,s4 -8000eab0: ed4ff0ef jal ra,8000e184 -8000eab4: 00c45783 lhu a5,12(s0) -8000eab8: b7f7f793 andi a5,a5,-1153 -8000eabc: 0807e793 ori a5,a5,128 -8000eac0: 00f41623 sh a5,12(s0) -8000eac4: 014c0533 add a0,s8,s4 -8000eac8: 41448a33 sub s4,s1,s4 -8000eacc: 00942a23 sw s1,20(s0) -8000ead0: 01442423 sw s4,8(s0) -8000ead4: 01842823 sw s8,16(s0) -8000ead8: 00a42023 sw a0,0(s0) -8000eadc: 00090493 mv s1,s2 -8000eae0: 00090a13 mv s4,s2 -8000eae4: 000a0613 mv a2,s4 -8000eae8: 000b8593 mv a1,s7 -8000eaec: fb4ff0ef jal ra,8000e2a0 -8000eaf0: 00842703 lw a4,8(s0) -8000eaf4: 00042503 lw a0,0(s0) -8000eaf8: 008aa783 lw a5,8(s5) -8000eafc: 409704b3 sub s1,a4,s1 -8000eb00: 01450533 add a0,a0,s4 -8000eb04: 00942423 sw s1,8(s0) -8000eb08: 00a42023 sw a0,0(s0) -8000eb0c: 41278933 sub s2,a5,s2 -8000eb10: 012aa423 sw s2,8(s5) -8000eb14: 06090463 beqz s2,8000eb7c <__ssprint_r+0x184> -8000eb18: 0049a903 lw s2,4(s3) -8000eb1c: 0009ab83 lw s7,0(s3) -8000eb20: 00048a13 mv s4,s1 -8000eb24: 00898993 addi s3,s3,8 -8000eb28: fe0908e3 beqz s2,8000eb18 <__ssprint_r+0x120> -8000eb2c: f0997ee3 bgeu s2,s1,8000ea48 <__ssprint_r+0x50> -8000eb30: 00090493 mv s1,s2 -8000eb34: 00090a13 mv s4,s2 -8000eb38: fadff06f j 8000eae4 <__ssprint_r+0xec> -8000eb3c: 000b0513 mv a0,s6 -8000eb40: 8e9ff0ef jal ra,8000e428 <_realloc_r> -8000eb44: 00050c13 mv s8,a0 -8000eb48: f6051ee3 bnez a0,8000eac4 <__ssprint_r+0xcc> -8000eb4c: 01042583 lw a1,16(s0) -8000eb50: 000b0513 mv a0,s6 -8000eb54: 9d4f60ef jal ra,80004d28 <_free_r> -8000eb58: 00c00793 li a5,12 -8000eb5c: 00fb2023 sw a5,0(s6) -8000eb60: 00c45783 lhu a5,12(s0) -8000eb64: fff00513 li a0,-1 -8000eb68: 0407e793 ori a5,a5,64 -8000eb6c: 00f41623 sh a5,12(s0) -8000eb70: 000aa423 sw zero,8(s5) -8000eb74: 000aa223 sw zero,4(s5) -8000eb78: 00c0006f j 8000eb84 <__ssprint_r+0x18c> -8000eb7c: 000aa223 sw zero,4(s5) -8000eb80: 00000513 li a0,0 -8000eb84: 02c12083 lw ra,44(sp) -8000eb88: 02812403 lw s0,40(sp) -8000eb8c: 02412483 lw s1,36(sp) -8000eb90: 02012903 lw s2,32(sp) -8000eb94: 01c12983 lw s3,28(sp) -8000eb98: 01812a03 lw s4,24(sp) -8000eb9c: 01412a83 lw s5,20(sp) -8000eba0: 01012b03 lw s6,16(sp) -8000eba4: 00c12b83 lw s7,12(sp) -8000eba8: 00812c03 lw s8,8(sp) -8000ebac: 03010113 addi sp,sp,48 -8000ebb0: 00008067 ret - -8000ebb4 <_svfiprintf_r>: -8000ebb4: 00c5d783 lhu a5,12(a1) -8000ebb8: ed010113 addi sp,sp,-304 -8000ebbc: 11512a23 sw s5,276(sp) -8000ebc0: 11712623 sw s7,268(sp) -8000ebc4: 0fb12e23 sw s11,252(sp) -8000ebc8: 12112623 sw ra,300(sp) -8000ebcc: 12812423 sw s0,296(sp) -8000ebd0: 12912223 sw s1,292(sp) -8000ebd4: 13212023 sw s2,288(sp) -8000ebd8: 11312e23 sw s3,284(sp) -8000ebdc: 11412c23 sw s4,280(sp) -8000ebe0: 11612823 sw s6,272(sp) -8000ebe4: 11812423 sw s8,264(sp) -8000ebe8: 11912223 sw s9,260(sp) -8000ebec: 11a12023 sw s10,256(sp) -8000ebf0: 0807f793 andi a5,a5,128 -8000ebf4: 00d12423 sw a3,8(sp) -8000ebf8: 00058a93 mv s5,a1 -8000ebfc: 00050b93 mv s7,a0 -8000ec00: 00060d93 mv s11,a2 -8000ec04: 00078663 beqz a5,8000ec10 <_svfiprintf_r+0x5c> -8000ec08: 0105a783 lw a5,16(a1) -8000ec0c: 5e078ce3 beqz a5,8000fa04 <_svfiprintf_r+0xe50> -8000ec10: 80015d37 lui s10,0x80015 -8000ec14: 04c10993 addi s3,sp,76 -8000ec18: fe4d0793 addi a5,s10,-28 # 80014fe4 <__BSS_END__+0xffffe26c> -8000ec1c: 80015b37 lui s6,0x80015 -8000ec20: 800154b7 lui s1,0x80015 -8000ec24: 000d8a13 mv s4,s11 -8000ec28: 05312023 sw s3,64(sp) -8000ec2c: 04012423 sw zero,72(sp) -8000ec30: 04012223 sw zero,68(sp) -8000ec34: 00012a23 sw zero,20(sp) -8000ec38: 00012e23 sw zero,28(sp) -8000ec3c: 02012023 sw zero,32(sp) -8000ec40: 02012223 sw zero,36(sp) -8000ec44: 00012223 sw zero,4(sp) -8000ec48: 00f12623 sw a5,12(sp) -8000ec4c: 150b0b13 addi s6,s6,336 # 80015150 <__BSS_END__+0xffffe3d8> -8000ec50: 16048493 addi s1,s1,352 # 80015160 <__BSS_END__+0xffffe3e8> -8000ec54: 01712823 sw s7,16(sp) -8000ec58: 00098d93 mv s11,s3 -8000ec5c: 000a4783 lbu a5,0(s4) -8000ec60: 12078463 beqz a5,8000ed88 <_svfiprintf_r+0x1d4> -8000ec64: 02500693 li a3,37 -8000ec68: 52d784e3 beq a5,a3,8000f990 <_svfiprintf_r+0xddc> -8000ec6c: 000a0413 mv s0,s4 -8000ec70: 00c0006f j 8000ec7c <_svfiprintf_r+0xc8> -8000ec74: 0ed78663 beq a5,a3,8000ed60 <_svfiprintf_r+0x1ac> -8000ec78: 000c0413 mv s0,s8 -8000ec7c: 00144783 lbu a5,1(s0) -8000ec80: 00140c13 addi s8,s0,1 -8000ec84: fe0798e3 bnez a5,8000ec74 <_svfiprintf_r+0xc0> -8000ec88: 414c0cb3 sub s9,s8,s4 -8000ec8c: 0e0c8e63 beqz s9,8000ed88 <_svfiprintf_r+0x1d4> -8000ec90: 04812703 lw a4,72(sp) -8000ec94: 04412783 lw a5,68(sp) -8000ec98: 014da023 sw s4,0(s11) -8000ec9c: 01970733 add a4,a4,s9 -8000eca0: 00178793 addi a5,a5,1 -8000eca4: 019da223 sw s9,4(s11) -8000eca8: 04e12423 sw a4,72(sp) -8000ecac: 04f12223 sw a5,68(sp) -8000ecb0: 00700713 li a4,7 -8000ecb4: 008d8d93 addi s11,s11,8 -8000ecb8: 0af74a63 blt a4,a5,8000ed6c <_svfiprintf_r+0x1b8> -8000ecbc: 00412703 lw a4,4(sp) -8000ecc0: 00144783 lbu a5,1(s0) -8000ecc4: 01970733 add a4,a4,s9 -8000ecc8: 00e12223 sw a4,4(sp) -8000eccc: 0a078e63 beqz a5,8000ed88 <_svfiprintf_r+0x1d4> -8000ecd0: fff00813 li a6,-1 -8000ecd4: 001c0a13 addi s4,s8,1 -8000ecd8: 001c4683 lbu a3,1(s8) -8000ecdc: 02010da3 sb zero,59(sp) -8000ece0: 00000413 li s0,0 -8000ece4: 00000913 li s2,0 -8000ece8: 05a00c13 li s8,90 -8000ecec: 00900c93 li s9,9 -8000ecf0: 02a00d13 li s10,42 -8000ecf4: 00080b93 mv s7,a6 -8000ecf8: 001a0a13 addi s4,s4,1 -8000ecfc: fe068793 addi a5,a3,-32 -8000ed00: 1cfc6063 bltu s8,a5,8000eec0 <_svfiprintf_r+0x30c> -8000ed04: 00c12703 lw a4,12(sp) -8000ed08: 00279793 slli a5,a5,0x2 -8000ed0c: 00e787b3 add a5,a5,a4 -8000ed10: 0007a783 lw a5,0(a5) -8000ed14: 00078067 jr a5 -8000ed18: 01012503 lw a0,16(sp) -8000ed1c: 80cf90ef jal ra,80007d28 <_localeconv_r> -8000ed20: 00452783 lw a5,4(a0) -8000ed24: 00078513 mv a0,a5 -8000ed28: 02f12223 sw a5,36(sp) -8000ed2c: 8f1fa0ef jal ra,8000961c -8000ed30: 02a12023 sw a0,32(sp) -8000ed34: 01012503 lw a0,16(sp) -8000ed38: ff1f80ef jal ra,80007d28 <_localeconv_r> -8000ed3c: 00852703 lw a4,8(a0) -8000ed40: 02012783 lw a5,32(sp) -8000ed44: 00e12e23 sw a4,28(sp) -8000ed48: 440798e3 bnez a5,8000f998 <_svfiprintf_r+0xde4> -8000ed4c: 000a4683 lbu a3,0(s4) -8000ed50: fa9ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000ed54: 02096913 ori s2,s2,32 -8000ed58: 000a4683 lbu a3,0(s4) -8000ed5c: f9dff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000ed60: 414c0cb3 sub s9,s8,s4 -8000ed64: f60c86e3 beqz s9,8000ecd0 <_svfiprintf_r+0x11c> -8000ed68: f29ff06f j 8000ec90 <_svfiprintf_r+0xdc> -8000ed6c: 01012503 lw a0,16(sp) -8000ed70: 04010613 addi a2,sp,64 -8000ed74: 000a8593 mv a1,s5 -8000ed78: c81ff0ef jal ra,8000e9f8 <__ssprint_r> -8000ed7c: 02051463 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000ed80: 00098d93 mv s11,s3 -8000ed84: f39ff06f j 8000ecbc <_svfiprintf_r+0x108> -8000ed88: 04812783 lw a5,72(sp) -8000ed8c: 01012b83 lw s7,16(sp) -8000ed90: 00078a63 beqz a5,8000eda4 <_svfiprintf_r+0x1f0> -8000ed94: 04010613 addi a2,sp,64 -8000ed98: 000a8593 mv a1,s5 -8000ed9c: 000b8513 mv a0,s7 -8000eda0: c59ff0ef jal ra,8000e9f8 <__ssprint_r> -8000eda4: 00cad783 lhu a5,12(s5) -8000eda8: 0407f793 andi a5,a5,64 -8000edac: 700796e3 bnez a5,8000fcb8 <_svfiprintf_r+0x1104> -8000edb0: 12c12083 lw ra,300(sp) -8000edb4: 12812403 lw s0,296(sp) -8000edb8: 00412503 lw a0,4(sp) -8000edbc: 12412483 lw s1,292(sp) -8000edc0: 12012903 lw s2,288(sp) -8000edc4: 11c12983 lw s3,284(sp) -8000edc8: 11812a03 lw s4,280(sp) -8000edcc: 11412a83 lw s5,276(sp) -8000edd0: 11012b03 lw s6,272(sp) -8000edd4: 10c12b83 lw s7,268(sp) -8000edd8: 10812c03 lw s8,264(sp) -8000eddc: 10412c83 lw s9,260(sp) -8000ede0: 10012d03 lw s10,256(sp) -8000ede4: 0fc12d83 lw s11,252(sp) -8000ede8: 13010113 addi sp,sp,304 -8000edec: 00008067 ret -8000edf0: 800147b7 lui a5,0x80014 -8000edf4: 7f478793 addi a5,a5,2036 # 800147f4 <__BSS_END__+0xffffda7c> -8000edf8: 00f12a23 sw a5,20(sp) -8000edfc: 02097793 andi a5,s2,32 -8000ee00: 000b8813 mv a6,s7 -8000ee04: 4c078863 beqz a5,8000f2d4 <_svfiprintf_r+0x720> -8000ee08: 00812783 lw a5,8(sp) -8000ee0c: 00778613 addi a2,a5,7 -8000ee10: ff867613 andi a2,a2,-8 -8000ee14: 00062d03 lw s10,0(a2) -8000ee18: 00462c83 lw s9,4(a2) -8000ee1c: 00860793 addi a5,a2,8 -8000ee20: 00f12423 sw a5,8(sp) -8000ee24: 00197613 andi a2,s2,1 -8000ee28: 00060663 beqz a2,8000ee34 <_svfiprintf_r+0x280> -8000ee2c: 019d6633 or a2,s10,s9 -8000ee30: 380612e3 bnez a2,8000f9b4 <_svfiprintf_r+0xe00> -8000ee34: bff97c13 andi s8,s2,-1025 -8000ee38: 00200693 li a3,2 -8000ee3c: 02010da3 sb zero,59(sp) -8000ee40: fff00613 li a2,-1 -8000ee44: 60c80663 beq a6,a2,8000f450 <_svfiprintf_r+0x89c> -8000ee48: 019d6633 or a2,s10,s9 -8000ee4c: f7fc7913 andi s2,s8,-129 -8000ee50: 140614e3 bnez a2,8000f798 <_svfiprintf_r+0xbe4> -8000ee54: 6e081463 bnez a6,8000f53c <_svfiprintf_r+0x988> -8000ee58: 2e0694e3 bnez a3,8000f940 <_svfiprintf_r+0xd8c> -8000ee5c: 001c7c93 andi s9,s8,1 -8000ee60: 0f010b93 addi s7,sp,240 -8000ee64: 000c8863 beqz s9,8000ee74 <_svfiprintf_r+0x2c0> -8000ee68: 03000793 li a5,48 -8000ee6c: 0ef107a3 sb a5,239(sp) -8000ee70: 0ef10b93 addi s7,sp,239 -8000ee74: 00080c13 mv s8,a6 -8000ee78: 01985463 bge a6,s9,8000ee80 <_svfiprintf_r+0x2cc> -8000ee7c: 000c8c13 mv s8,s9 -8000ee80: 03b14783 lbu a5,59(sp) -8000ee84: 00f037b3 snez a5,a5 -8000ee88: 00fc0c33 add s8,s8,a5 -8000ee8c: 0500006f j 8000eedc <_svfiprintf_r+0x328> -8000ee90: 00000413 li s0,0 -8000ee94: fd068713 addi a4,a3,-48 -8000ee98: 001a0a13 addi s4,s4,1 -8000ee9c: 00241793 slli a5,s0,0x2 -8000eea0: fffa4683 lbu a3,-1(s4) -8000eea4: 00878433 add s0,a5,s0 -8000eea8: 00141413 slli s0,s0,0x1 -8000eeac: 00870433 add s0,a4,s0 -8000eeb0: fd068713 addi a4,a3,-48 -8000eeb4: feecf2e3 bgeu s9,a4,8000ee98 <_svfiprintf_r+0x2e4> -8000eeb8: fe068793 addi a5,a3,-32 -8000eebc: e4fc74e3 bgeu s8,a5,8000ed04 <_svfiprintf_r+0x150> -8000eec0: ec0684e3 beqz a3,8000ed88 <_svfiprintf_r+0x1d4> -8000eec4: 08d10623 sb a3,140(sp) -8000eec8: 02010da3 sb zero,59(sp) -8000eecc: 00100c13 li s8,1 -8000eed0: 00100c93 li s9,1 -8000eed4: 08c10b93 addi s7,sp,140 -8000eed8: 00000813 li a6,0 -8000eedc: 00297e93 andi t4,s2,2 -8000eee0: 000e8463 beqz t4,8000eee8 <_svfiprintf_r+0x334> -8000eee4: 002c0c13 addi s8,s8,2 -8000eee8: 08497e13 andi t3,s2,132 -8000eeec: 04812783 lw a5,72(sp) -8000eef0: 04412603 lw a2,68(sp) -8000eef4: 000e1663 bnez t3,8000ef00 <_svfiprintf_r+0x34c> -8000eef8: 41840d33 sub s10,s0,s8 -8000eefc: 0ba042e3 bgtz s10,8000f7a0 <_svfiprintf_r+0xbec> -8000ef00: 03b14503 lbu a0,59(sp) -8000ef04: 00160593 addi a1,a2,1 -8000ef08: 008d8693 addi a3,s11,8 -8000ef0c: 04050063 beqz a0,8000ef4c <_svfiprintf_r+0x398> -8000ef10: 03b10513 addi a0,sp,59 -8000ef14: 00178793 addi a5,a5,1 -8000ef18: 00ada023 sw a0,0(s11) -8000ef1c: 00100513 li a0,1 -8000ef20: 00ada223 sw a0,4(s11) -8000ef24: 04f12423 sw a5,72(sp) -8000ef28: 04b12223 sw a1,68(sp) -8000ef2c: 00700513 li a0,7 -8000ef30: 18b546e3 blt a0,a1,8000f8bc <_svfiprintf_r+0xd08> -8000ef34: 00260f13 addi t5,a2,2 -8000ef38: 010d8513 addi a0,s11,16 -8000ef3c: 00058613 mv a2,a1 -8000ef40: 00068d93 mv s11,a3 -8000ef44: 000f0593 mv a1,t5 -8000ef48: 00050693 mv a3,a0 -8000ef4c: 020e8c63 beqz t4,8000ef84 <_svfiprintf_r+0x3d0> -8000ef50: 03c10613 addi a2,sp,60 -8000ef54: 00278793 addi a5,a5,2 -8000ef58: 00cda023 sw a2,0(s11) -8000ef5c: 00200613 li a2,2 -8000ef60: 00cda223 sw a2,4(s11) -8000ef64: 04f12423 sw a5,72(sp) -8000ef68: 04b12223 sw a1,68(sp) -8000ef6c: 00700613 li a2,7 -8000ef70: 18b648e3 blt a2,a1,8000f900 <_svfiprintf_r+0xd4c> -8000ef74: 00058613 mv a2,a1 -8000ef78: 00068d93 mv s11,a3 -8000ef7c: 00158593 addi a1,a1,1 -8000ef80: 00868693 addi a3,a3,8 -8000ef84: 08000513 li a0,128 -8000ef88: 60ae0663 beq t3,a0,8000f594 <_svfiprintf_r+0x9e0> -8000ef8c: 41980d33 sub s10,a6,s9 -8000ef90: 6fa04a63 bgtz s10,8000f684 <_svfiprintf_r+0xad0> -8000ef94: 00fc87b3 add a5,s9,a5 -8000ef98: 017da023 sw s7,0(s11) -8000ef9c: 019da223 sw s9,4(s11) -8000efa0: 04f12423 sw a5,72(sp) -8000efa4: 04b12223 sw a1,68(sp) -8000efa8: 00700613 li a2,7 -8000efac: 7ab64a63 blt a2,a1,8000f760 <_svfiprintf_r+0xbac> -8000efb0: 00497893 andi a7,s2,4 -8000efb4: 00088663 beqz a7,8000efc0 <_svfiprintf_r+0x40c> -8000efb8: 41840cb3 sub s9,s0,s8 -8000efbc: 1f904863 bgtz s9,8000f1ac <_svfiprintf_r+0x5f8> -8000efc0: 01845463 bge s0,s8,8000efc8 <_svfiprintf_r+0x414> -8000efc4: 000c0413 mv s0,s8 -8000efc8: 00412703 lw a4,4(sp) -8000efcc: 00870733 add a4,a4,s0 -8000efd0: 00e12223 sw a4,4(sp) -8000efd4: 7a079663 bnez a5,8000f780 <_svfiprintf_r+0xbcc> -8000efd8: 04012223 sw zero,68(sp) -8000efdc: 00098d93 mv s11,s3 -8000efe0: c7dff06f j 8000ec5c <_svfiprintf_r+0xa8> -8000efe4: 00812783 lw a5,8(sp) -8000efe8: 000b8813 mv a6,s7 -8000efec: 02010da3 sb zero,59(sp) -8000eff0: 0007ab83 lw s7,0(a5) -8000eff4: 00478d13 addi s10,a5,4 -8000eff8: 340b8ce3 beqz s7,8000fb50 <_svfiprintf_r+0xf9c> -8000effc: fff00793 li a5,-1 -8000f000: 1ef806e3 beq a6,a5,8000f9ec <_svfiprintf_r+0xe38> -8000f004: 00080613 mv a2,a6 -8000f008: 00000593 li a1,0 -8000f00c: 000b8513 mv a0,s7 -8000f010: 01012423 sw a6,8(sp) -8000f014: 818f90ef jal ra,8000802c -8000f018: 00812803 lw a6,8(sp) -8000f01c: 480500e3 beqz a0,8000fc9c <_svfiprintf_r+0x10e8> -8000f020: 41750cb3 sub s9,a0,s7 -8000f024: 01a12423 sw s10,8(sp) -8000f028: 00000813 li a6,0 -8000f02c: e49ff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000f030: 02097793 andi a5,s2,32 -8000f034: 000b8813 mv a6,s7 -8000f038: 01096893 ori a7,s2,16 -8000f03c: 48079463 bnez a5,8000f4c4 <_svfiprintf_r+0x910> -8000f040: 00812783 lw a5,8(sp) -8000f044: 00478693 addi a3,a5,4 -8000f048: 00812783 lw a5,8(sp) -8000f04c: 00000c93 li s9,0 -8000f050: 00d12423 sw a3,8(sp) -8000f054: 0007ad03 lw s10,0(a5) -8000f058: 4880006f j 8000f4e0 <_svfiprintf_r+0x92c> -8000f05c: 02097793 andi a5,s2,32 -8000f060: 000b8813 mv a6,s7 -8000f064: 01096c13 ori s8,s2,16 -8000f068: 48079463 bnez a5,8000f4f0 <_svfiprintf_r+0x93c> -8000f06c: 00812783 lw a5,8(sp) -8000f070: 00478693 addi a3,a5,4 -8000f074: 00812783 lw a5,8(sp) -8000f078: 00000c93 li s9,0 -8000f07c: 00d12423 sw a3,8(sp) -8000f080: 0007ad03 lw s10,0(a5) -8000f084: 00100693 li a3,1 -8000f088: db5ff06f j 8000ee3c <_svfiprintf_r+0x288> -8000f08c: 08096913 ori s2,s2,128 -8000f090: 000a4683 lbu a3,0(s4) -8000f094: c65ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f098: 000a4683 lbu a3,0(s4) -8000f09c: 001a0793 addi a5,s4,1 -8000f0a0: 43a682e3 beq a3,s10,8000fcc4 <_svfiprintf_r+0x1110> -8000f0a4: fd068713 addi a4,a3,-48 -8000f0a8: 00078a13 mv s4,a5 -8000f0ac: 00000b93 li s7,0 -8000f0b0: c4ece6e3 bltu s9,a4,8000ecfc <_svfiprintf_r+0x148> -8000f0b4: 001a0a13 addi s4,s4,1 -8000f0b8: 002b9793 slli a5,s7,0x2 -8000f0bc: fffa4683 lbu a3,-1(s4) -8000f0c0: 01778833 add a6,a5,s7 -8000f0c4: 00181813 slli a6,a6,0x1 -8000f0c8: 00e80bb3 add s7,a6,a4 -8000f0cc: fd068713 addi a4,a3,-48 -8000f0d0: feecf2e3 bgeu s9,a4,8000f0b4 <_svfiprintf_r+0x500> -8000f0d4: c29ff06f j 8000ecfc <_svfiprintf_r+0x148> -8000f0d8: 000a4683 lbu a3,0(s4) -8000f0dc: 00496913 ori s2,s2,4 -8000f0e0: c19ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f0e4: 02b00793 li a5,43 -8000f0e8: 02f10da3 sb a5,59(sp) -8000f0ec: 000a4683 lbu a3,0(s4) -8000f0f0: c09ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f0f4: 00812783 lw a5,8(sp) -8000f0f8: 000a4683 lbu a3,0(s4) -8000f0fc: 0007a403 lw s0,0(a5) -8000f100: 00478793 addi a5,a5,4 -8000f104: 00f12423 sw a5,8(sp) -8000f108: be0458e3 bgez s0,8000ecf8 <_svfiprintf_r+0x144> -8000f10c: 40800433 neg s0,s0 -8000f110: 00496913 ori s2,s2,4 -8000f114: be5ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f118: 02097793 andi a5,s2,32 -8000f11c: 000b8813 mv a6,s7 -8000f120: 01096c13 ori s8,s2,16 -8000f124: 3e079a63 bnez a5,8000f518 <_svfiprintf_r+0x964> -8000f128: 00812783 lw a5,8(sp) -8000f12c: 00478693 addi a3,a5,4 -8000f130: 00812783 lw a5,8(sp) -8000f134: 00d12423 sw a3,8(sp) -8000f138: 0007ad03 lw s10,0(a5) -8000f13c: 41fd5c93 srai s9,s10,0x1f -8000f140: 000c8693 mv a3,s9 -8000f144: 2e06c263 bltz a3,8000f428 <_svfiprintf_r+0x874> -8000f148: fff00693 li a3,-1 -8000f14c: 00d80a63 beq a6,a3,8000f160 <_svfiprintf_r+0x5ac> -8000f150: 019d66b3 or a3,s10,s9 -8000f154: f7fc7913 andi s2,s8,-129 -8000f158: 7e068263 beqz a3,8000f93c <_svfiprintf_r+0xd88> -8000f15c: 00090c13 mv s8,s2 -8000f160: 0c0c92e3 bnez s9,8000fa24 <_svfiprintf_r+0xe70> -8000f164: 00900693 li a3,9 -8000f168: 0ba6eee3 bltu a3,s10,8000fa24 <_svfiprintf_r+0xe70> -8000f16c: 030d0793 addi a5,s10,48 -8000f170: 0ef107a3 sb a5,239(sp) -8000f174: 000c0913 mv s2,s8 -8000f178: 00100c93 li s9,1 -8000f17c: 0ef10b93 addi s7,sp,239 -8000f180: cf5ff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000f184: 00812703 lw a4,8(sp) -8000f188: 02010da3 sb zero,59(sp) -8000f18c: 00100c13 li s8,1 -8000f190: 00072783 lw a5,0(a4) -8000f194: 00470713 addi a4,a4,4 -8000f198: 00e12423 sw a4,8(sp) -8000f19c: 08f10623 sb a5,140(sp) -8000f1a0: 00100c93 li s9,1 -8000f1a4: 08c10b93 addi s7,sp,140 -8000f1a8: d31ff06f j 8000eed8 <_svfiprintf_r+0x324> -8000f1ac: 01000593 li a1,16 -8000f1b0: 04412603 lw a2,68(sp) -8000f1b4: 0795d263 bge a1,s9,8000f218 <_svfiprintf_r+0x664> -8000f1b8: 01000d13 li s10,16 -8000f1bc: 00700d93 li s11,7 -8000f1c0: 01012903 lw s2,16(sp) -8000f1c4: 00c0006f j 8000f1d0 <_svfiprintf_r+0x61c> -8000f1c8: ff0c8c93 addi s9,s9,-16 -8000f1cc: 059d5663 bge s10,s9,8000f218 <_svfiprintf_r+0x664> -8000f1d0: 01078793 addi a5,a5,16 -8000f1d4: 00160613 addi a2,a2,1 -8000f1d8: 0166a023 sw s6,0(a3) -8000f1dc: 01a6a223 sw s10,4(a3) -8000f1e0: 04f12423 sw a5,72(sp) -8000f1e4: 04c12223 sw a2,68(sp) -8000f1e8: 00868693 addi a3,a3,8 -8000f1ec: fccddee3 bge s11,a2,8000f1c8 <_svfiprintf_r+0x614> -8000f1f0: 04010613 addi a2,sp,64 -8000f1f4: 000a8593 mv a1,s5 -8000f1f8: 00090513 mv a0,s2 -8000f1fc: ffcff0ef jal ra,8000e9f8 <__ssprint_r> -8000f200: ba0512e3 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f204: ff0c8c93 addi s9,s9,-16 -8000f208: 04812783 lw a5,72(sp) -8000f20c: 04412603 lw a2,68(sp) -8000f210: 00098693 mv a3,s3 -8000f214: fb9d4ee3 blt s10,s9,8000f1d0 <_svfiprintf_r+0x61c> -8000f218: 019787b3 add a5,a5,s9 -8000f21c: 00160613 addi a2,a2,1 -8000f220: 0166a023 sw s6,0(a3) -8000f224: 0196a223 sw s9,4(a3) -8000f228: 04f12423 sw a5,72(sp) -8000f22c: 04c12223 sw a2,68(sp) -8000f230: 00700693 li a3,7 -8000f234: d8c6d6e3 bge a3,a2,8000efc0 <_svfiprintf_r+0x40c> -8000f238: 01012503 lw a0,16(sp) -8000f23c: 04010613 addi a2,sp,64 -8000f240: 000a8593 mv a1,s5 -8000f244: fb4ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f248: b4051ee3 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f24c: 04812783 lw a5,72(sp) -8000f250: d71ff06f j 8000efc0 <_svfiprintf_r+0x40c> -8000f254: 00196913 ori s2,s2,1 -8000f258: 000a4683 lbu a3,0(s4) -8000f25c: a9dff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f260: 03b14783 lbu a5,59(sp) -8000f264: 000a4683 lbu a3,0(s4) -8000f268: a80798e3 bnez a5,8000ecf8 <_svfiprintf_r+0x144> -8000f26c: 02000793 li a5,32 -8000f270: 02f10da3 sb a5,59(sp) -8000f274: a85ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f278: 02097793 andi a5,s2,32 -8000f27c: 000b8813 mv a6,s7 -8000f280: 26079663 bnez a5,8000f4ec <_svfiprintf_r+0x938> -8000f284: 00812783 lw a5,8(sp) -8000f288: 01097613 andi a2,s2,16 -8000f28c: 00478693 addi a3,a5,4 -8000f290: 0007a783 lw a5,0(a5) -8000f294: 260618e3 bnez a2,8000fd04 <_svfiprintf_r+0x1150> -8000f298: 04097613 andi a2,s2,64 -8000f29c: 0e060ae3 beqz a2,8000fb90 <_svfiprintf_r+0xfdc> -8000f2a0: 01079d13 slli s10,a5,0x10 -8000f2a4: 00d12423 sw a3,8(sp) -8000f2a8: 010d5d13 srli s10,s10,0x10 -8000f2ac: 00000c93 li s9,0 -8000f2b0: 00090c13 mv s8,s2 -8000f2b4: 00100693 li a3,1 -8000f2b8: b85ff06f j 8000ee3c <_svfiprintf_r+0x288> -8000f2bc: 800147b7 lui a5,0x80014 -8000f2c0: 7e078793 addi a5,a5,2016 # 800147e0 <__BSS_END__+0xffffda68> -8000f2c4: 00f12a23 sw a5,20(sp) -8000f2c8: 02097793 andi a5,s2,32 -8000f2cc: 000b8813 mv a6,s7 -8000f2d0: b2079ce3 bnez a5,8000ee08 <_svfiprintf_r+0x254> -8000f2d4: 00812703 lw a4,8(sp) -8000f2d8: 01097613 andi a2,s2,16 -8000f2dc: 00072783 lw a5,0(a4) -8000f2e0: 00470713 addi a4,a4,4 -8000f2e4: 00e12423 sw a4,8(sp) -8000f2e8: 66061863 bnez a2,8000f958 <_svfiprintf_r+0xda4> -8000f2ec: 04097613 andi a2,s2,64 -8000f2f0: 66060063 beqz a2,8000f950 <_svfiprintf_r+0xd9c> -8000f2f4: 01079d13 slli s10,a5,0x10 -8000f2f8: 010d5d13 srli s10,s10,0x10 -8000f2fc: 00000c93 li s9,0 -8000f300: b25ff06f j 8000ee24 <_svfiprintf_r+0x270> -8000f304: 00812783 lw a5,8(sp) -8000f308: ffff86b7 lui a3,0xffff8 -8000f30c: 8306c693 xori a3,a3,-2000 -8000f310: 0007ad03 lw s10,0(a5) -8000f314: 02d11e23 sh a3,60(sp) -8000f318: 00478793 addi a5,a5,4 -8000f31c: 800146b7 lui a3,0x80014 -8000f320: 00f12423 sw a5,8(sp) -8000f324: 7e068793 addi a5,a3,2016 # 800147e0 <__BSS_END__+0xffffda68> -8000f328: 000b8813 mv a6,s7 -8000f32c: 00000c93 li s9,0 -8000f330: 00296c13 ori s8,s2,2 -8000f334: 00f12a23 sw a5,20(sp) -8000f338: 00200693 li a3,2 -8000f33c: b01ff06f j 8000ee3c <_svfiprintf_r+0x288> -8000f340: 02097793 andi a5,s2,32 -8000f344: 000b8813 mv a6,s7 -8000f348: 16079c63 bnez a5,8000f4c0 <_svfiprintf_r+0x90c> -8000f34c: 00812783 lw a5,8(sp) -8000f350: 01097613 andi a2,s2,16 -8000f354: 00478693 addi a3,a5,4 -8000f358: 0007a783 lw a5,0(a5) -8000f35c: 1a0618e3 bnez a2,8000fd0c <_svfiprintf_r+0x1158> -8000f360: 04097613 andi a2,s2,64 -8000f364: 000608e3 beqz a2,8000fb74 <_svfiprintf_r+0xfc0> -8000f368: 01079d13 slli s10,a5,0x10 -8000f36c: 010d5d13 srli s10,s10,0x10 -8000f370: 00000c93 li s9,0 -8000f374: 00090893 mv a7,s2 -8000f378: 00d12423 sw a3,8(sp) -8000f37c: 1640006f j 8000f4e0 <_svfiprintf_r+0x92c> -8000f380: 00812703 lw a4,8(sp) -8000f384: 02097793 andi a5,s2,32 -8000f388: 00470693 addi a3,a4,4 -8000f38c: 64079263 bnez a5,8000f9d0 <_svfiprintf_r+0xe1c> -8000f390: 01097793 andi a5,s2,16 -8000f394: 7a079263 bnez a5,8000fb38 <_svfiprintf_r+0xf84> -8000f398: 04097793 andi a5,s2,64 -8000f39c: 080796e3 bnez a5,8000fc28 <_svfiprintf_r+0x1074> -8000f3a0: 20097893 andi a7,s2,512 -8000f3a4: 78088a63 beqz a7,8000fb38 <_svfiprintf_r+0xf84> -8000f3a8: 00812783 lw a5,8(sp) -8000f3ac: 00412703 lw a4,4(sp) -8000f3b0: 00d12423 sw a3,8(sp) -8000f3b4: 0007a783 lw a5,0(a5) -8000f3b8: 00e78023 sb a4,0(a5) -8000f3bc: 8a1ff06f j 8000ec5c <_svfiprintf_r+0xa8> -8000f3c0: 000a4683 lbu a3,0(s4) -8000f3c4: 06c00793 li a5,108 -8000f3c8: 76f68063 beq a3,a5,8000fb28 <_svfiprintf_r+0xf74> -8000f3cc: 01096913 ori s2,s2,16 -8000f3d0: 929ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f3d4: 000a4683 lbu a3,0(s4) -8000f3d8: 06800793 li a5,104 -8000f3dc: 70f68463 beq a3,a5,8000fae4 <_svfiprintf_r+0xf30> -8000f3e0: 04096913 ori s2,s2,64 -8000f3e4: 915ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f3e8: 02097793 andi a5,s2,32 -8000f3ec: 000b8813 mv a6,s7 -8000f3f0: 12079263 bnez a5,8000f514 <_svfiprintf_r+0x960> -8000f3f4: 00812703 lw a4,8(sp) -8000f3f8: 01097793 andi a5,s2,16 -8000f3fc: 00470693 addi a3,a4,4 -8000f400: 0e079ee3 bnez a5,8000fcfc <_svfiprintf_r+0x1148> -8000f404: 04097793 andi a5,s2,64 -8000f408: 7a078463 beqz a5,8000fbb0 <_svfiprintf_r+0xffc> -8000f40c: 00812783 lw a5,8(sp) -8000f410: 00d12423 sw a3,8(sp) -8000f414: 00090c13 mv s8,s2 -8000f418: 00079d03 lh s10,0(a5) -8000f41c: 41fd5c93 srai s9,s10,0x1f -8000f420: 000c8693 mv a3,s9 -8000f424: d206d2e3 bgez a3,8000f148 <_svfiprintf_r+0x594> -8000f428: 41a007b3 neg a5,s10 -8000f42c: 00f036b3 snez a3,a5 -8000f430: 41900e33 neg t3,s9 -8000f434: 40de0cb3 sub s9,t3,a3 -8000f438: 02d00693 li a3,45 -8000f43c: 02d10da3 sb a3,59(sp) -8000f440: fff00613 li a2,-1 -8000f444: 00078d13 mv s10,a5 -8000f448: 00100693 li a3,1 -8000f44c: 9ec81ee3 bne a6,a2,8000ee48 <_svfiprintf_r+0x294> -8000f450: 00100613 li a2,1 -8000f454: d0c686e3 beq a3,a2,8000f160 <_svfiprintf_r+0x5ac> -8000f458: 00200613 li a2,2 -8000f45c: 0ec68a63 beq a3,a2,8000f550 <_svfiprintf_r+0x99c> -8000f460: 0f010613 addi a2,sp,240 -8000f464: 0080006f j 8000f46c <_svfiprintf_r+0x8b8> -8000f468: 000b8613 mv a2,s7 -8000f46c: 01dc9793 slli a5,s9,0x1d -8000f470: 007d7693 andi a3,s10,7 -8000f474: 003d5d13 srli s10,s10,0x3 -8000f478: 03068693 addi a3,a3,48 -8000f47c: 01a7ed33 or s10,a5,s10 -8000f480: 003cdc93 srli s9,s9,0x3 -8000f484: fed60fa3 sb a3,-1(a2) -8000f488: 019d67b3 or a5,s10,s9 -8000f48c: fff60b93 addi s7,a2,-1 -8000f490: fc079ce3 bnez a5,8000f468 <_svfiprintf_r+0x8b4> -8000f494: 001c7793 andi a5,s8,1 -8000f498: 0e078663 beqz a5,8000f584 <_svfiprintf_r+0x9d0> -8000f49c: 03000793 li a5,48 -8000f4a0: 0ef68263 beq a3,a5,8000f584 <_svfiprintf_r+0x9d0> -8000f4a4: ffe60613 addi a2,a2,-2 -8000f4a8: fefb8fa3 sb a5,-1(s7) -8000f4ac: 0f010793 addi a5,sp,240 -8000f4b0: 40c78cb3 sub s9,a5,a2 -8000f4b4: 000c0913 mv s2,s8 -8000f4b8: 00060b93 mv s7,a2 -8000f4bc: 9b9ff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000f4c0: 00090893 mv a7,s2 -8000f4c4: 00812783 lw a5,8(sp) -8000f4c8: 00778693 addi a3,a5,7 -8000f4cc: ff86f693 andi a3,a3,-8 -8000f4d0: 0006ad03 lw s10,0(a3) -8000f4d4: 0046ac83 lw s9,4(a3) -8000f4d8: 00868793 addi a5,a3,8 -8000f4dc: 00f12423 sw a5,8(sp) -8000f4e0: bff8fc13 andi s8,a7,-1025 -8000f4e4: 00000693 li a3,0 -8000f4e8: 955ff06f j 8000ee3c <_svfiprintf_r+0x288> -8000f4ec: 00090c13 mv s8,s2 -8000f4f0: 00812783 lw a5,8(sp) -8000f4f4: 00778693 addi a3,a5,7 -8000f4f8: ff86f693 andi a3,a3,-8 -8000f4fc: 00868793 addi a5,a3,8 -8000f500: 0006ad03 lw s10,0(a3) -8000f504: 0046ac83 lw s9,4(a3) -8000f508: 00f12423 sw a5,8(sp) -8000f50c: 00100693 li a3,1 -8000f510: 92dff06f j 8000ee3c <_svfiprintf_r+0x288> -8000f514: 00090c13 mv s8,s2 -8000f518: 00812783 lw a5,8(sp) -8000f51c: 00778793 addi a5,a5,7 -8000f520: ff87f793 andi a5,a5,-8 -8000f524: 0047a683 lw a3,4(a5) -8000f528: 00878713 addi a4,a5,8 -8000f52c: 00e12423 sw a4,8(sp) -8000f530: 0007ad03 lw s10,0(a5) -8000f534: 00068c93 mv s9,a3 -8000f538: c0dff06f j 8000f144 <_svfiprintf_r+0x590> -8000f53c: 00100613 li a2,1 -8000f540: 74c68a63 beq a3,a2,8000fc94 <_svfiprintf_r+0x10e0> -8000f544: 00200613 li a2,2 -8000f548: 00090c13 mv s8,s2 -8000f54c: f0c69ae3 bne a3,a2,8000f460 <_svfiprintf_r+0x8ac> -8000f550: 01412683 lw a3,20(sp) -8000f554: 0f010b93 addi s7,sp,240 -8000f558: 00fd7793 andi a5,s10,15 -8000f55c: 00f687b3 add a5,a3,a5 -8000f560: 0007c783 lbu a5,0(a5) -8000f564: 01cc9713 slli a4,s9,0x1c -8000f568: 004d5d13 srli s10,s10,0x4 -8000f56c: fffb8b93 addi s7,s7,-1 -8000f570: 01a76d33 or s10,a4,s10 -8000f574: 004cdc93 srli s9,s9,0x4 -8000f578: 00fb8023 sb a5,0(s7) -8000f57c: 019d67b3 or a5,s10,s9 -8000f580: fc079ce3 bnez a5,8000f558 <_svfiprintf_r+0x9a4> -8000f584: 0f010793 addi a5,sp,240 -8000f588: 41778cb3 sub s9,a5,s7 -8000f58c: 000c0913 mv s2,s8 -8000f590: 8e5ff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000f594: 41840d33 sub s10,s0,s8 -8000f598: 9fa05ae3 blez s10,8000ef8c <_svfiprintf_r+0x3d8> -8000f59c: 01000513 li a0,16 -8000f5a0: 71a55663 bge a0,s10,8000fcac <_svfiprintf_r+0x10f8> -8000f5a4: 000d8713 mv a4,s11 -8000f5a8: 01212c23 sw s2,24(sp) -8000f5ac: 000a0d93 mv s11,s4 -8000f5b0: 000d0913 mv s2,s10 -8000f5b4: 00040a13 mv s4,s0 -8000f5b8: 000c8d13 mv s10,s9 -8000f5bc: 01000693 li a3,16 -8000f5c0: 000c0c93 mv s9,s8 -8000f5c4: 00700e13 li t3,7 -8000f5c8: 00080c13 mv s8,a6 -8000f5cc: 01012403 lw s0,16(sp) -8000f5d0: 00c0006f j 8000f5dc <_svfiprintf_r+0xa28> -8000f5d4: ff090913 addi s2,s2,-16 -8000f5d8: 0526da63 bge a3,s2,8000f62c <_svfiprintf_r+0xa78> -8000f5dc: 01078793 addi a5,a5,16 -8000f5e0: 00160613 addi a2,a2,1 -8000f5e4: 00972023 sw s1,0(a4) -8000f5e8: 00d72223 sw a3,4(a4) -8000f5ec: 04f12423 sw a5,72(sp) -8000f5f0: 04c12223 sw a2,68(sp) -8000f5f4: 00870713 addi a4,a4,8 -8000f5f8: fcce5ee3 bge t3,a2,8000f5d4 <_svfiprintf_r+0xa20> -8000f5fc: 04010613 addi a2,sp,64 -8000f600: 000a8593 mv a1,s5 -8000f604: 00040513 mv a0,s0 -8000f608: bf0ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f60c: f8051c63 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f610: 01000693 li a3,16 -8000f614: ff090913 addi s2,s2,-16 -8000f618: 04812783 lw a5,72(sp) -8000f61c: 04412603 lw a2,68(sp) -8000f620: 00098713 mv a4,s3 -8000f624: 00700e13 li t3,7 -8000f628: fb26cae3 blt a3,s2,8000f5dc <_svfiprintf_r+0xa28> -8000f62c: 000c0813 mv a6,s8 -8000f630: 000c8c13 mv s8,s9 -8000f634: 000d0c93 mv s9,s10 -8000f638: 00090d13 mv s10,s2 -8000f63c: 01812903 lw s2,24(sp) -8000f640: 000a0413 mv s0,s4 -8000f644: 00160613 addi a2,a2,1 -8000f648: 000d8a13 mv s4,s11 -8000f64c: 00870513 addi a0,a4,8 -8000f650: 00070d93 mv s11,a4 -8000f654: 01a787b3 add a5,a5,s10 -8000f658: 009da023 sw s1,0(s11) -8000f65c: 01ada223 sw s10,4(s11) -8000f660: 04f12423 sw a5,72(sp) -8000f664: 04c12223 sw a2,68(sp) -8000f668: 00700693 li a3,7 -8000f66c: 48c6c463 blt a3,a2,8000faf4 <_svfiprintf_r+0xf40> -8000f670: 41980d33 sub s10,a6,s9 -8000f674: 00160593 addi a1,a2,1 -8000f678: 00850693 addi a3,a0,8 -8000f67c: 00050d93 mv s11,a0 -8000f680: 91a05ae3 blez s10,8000ef94 <_svfiprintf_r+0x3e0> -8000f684: 01000513 li a0,16 -8000f688: 55a55663 bge a0,s10,8000fbd4 <_svfiprintf_r+0x1020> -8000f68c: 01212c23 sw s2,24(sp) -8000f690: 01000693 li a3,16 -8000f694: 000d0913 mv s2,s10 -8000f698: 00700813 li a6,7 -8000f69c: 000a0d13 mv s10,s4 -8000f6a0: 00040a13 mv s4,s0 -8000f6a4: 01012403 lw s0,16(sp) -8000f6a8: 00c0006f j 8000f6b4 <_svfiprintf_r+0xb00> -8000f6ac: ff090913 addi s2,s2,-16 -8000f6b0: 0526da63 bge a3,s2,8000f704 <_svfiprintf_r+0xb50> -8000f6b4: 01078793 addi a5,a5,16 -8000f6b8: 00160613 addi a2,a2,1 -8000f6bc: 009da023 sw s1,0(s11) -8000f6c0: 00dda223 sw a3,4(s11) -8000f6c4: 04f12423 sw a5,72(sp) -8000f6c8: 04c12223 sw a2,68(sp) -8000f6cc: 008d8d93 addi s11,s11,8 -8000f6d0: fcc85ee3 bge a6,a2,8000f6ac <_svfiprintf_r+0xaf8> -8000f6d4: 04010613 addi a2,sp,64 -8000f6d8: 000a8593 mv a1,s5 -8000f6dc: 00040513 mv a0,s0 -8000f6e0: b18ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f6e4: ec051063 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f6e8: 01000693 li a3,16 -8000f6ec: ff090913 addi s2,s2,-16 -8000f6f0: 04812783 lw a5,72(sp) -8000f6f4: 04412603 lw a2,68(sp) -8000f6f8: 00098d93 mv s11,s3 -8000f6fc: 00700813 li a6,7 -8000f700: fb26cae3 blt a3,s2,8000f6b4 <_svfiprintf_r+0xb00> -8000f704: 000a0413 mv s0,s4 -8000f708: 000d0a13 mv s4,s10 -8000f70c: 00090d13 mv s10,s2 -8000f710: 01812903 lw s2,24(sp) -8000f714: 00160593 addi a1,a2,1 -8000f718: 008d8613 addi a2,s11,8 -8000f71c: 01a787b3 add a5,a5,s10 -8000f720: 009da023 sw s1,0(s11) -8000f724: 01ada223 sw s10,4(s11) -8000f728: 04f12423 sw a5,72(sp) -8000f72c: 04b12223 sw a1,68(sp) -8000f730: 00700693 li a3,7 -8000f734: 22b6c863 blt a3,a1,8000f964 <_svfiprintf_r+0xdb0> -8000f738: 00060d93 mv s11,a2 -8000f73c: 00158593 addi a1,a1,1 -8000f740: 00fc87b3 add a5,s9,a5 -8000f744: 00860693 addi a3,a2,8 -8000f748: 017da023 sw s7,0(s11) -8000f74c: 019da223 sw s9,4(s11) -8000f750: 04f12423 sw a5,72(sp) -8000f754: 04b12223 sw a1,68(sp) -8000f758: 00700613 li a2,7 -8000f75c: 84b65ae3 bge a2,a1,8000efb0 <_svfiprintf_r+0x3fc> -8000f760: 01012503 lw a0,16(sp) -8000f764: 04010613 addi a2,sp,64 -8000f768: 000a8593 mv a1,s5 -8000f76c: a8cff0ef jal ra,8000e9f8 <__ssprint_r> -8000f770: e2051a63 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f774: 04812783 lw a5,72(sp) -8000f778: 00098693 mv a3,s3 -8000f77c: 835ff06f j 8000efb0 <_svfiprintf_r+0x3fc> -8000f780: 01012503 lw a0,16(sp) -8000f784: 04010613 addi a2,sp,64 -8000f788: 000a8593 mv a1,s5 -8000f78c: a6cff0ef jal ra,8000e9f8 <__ssprint_r> -8000f790: 840504e3 beqz a0,8000efd8 <_svfiprintf_r+0x424> -8000f794: e10ff06f j 8000eda4 <_svfiprintf_r+0x1f0> -8000f798: 00090c13 mv s8,s2 -8000f79c: cb5ff06f j 8000f450 <_svfiprintf_r+0x89c> -8000f7a0: 01000693 li a3,16 -8000f7a4: 0ba6dc63 bge a3,s10,8000f85c <_svfiprintf_r+0xca8> -8000f7a8: 000d8713 mv a4,s11 -8000f7ac: 03212623 sw s2,44(sp) -8000f7b0: 000a0d93 mv s11,s4 -8000f7b4: 00700f13 li t5,7 -8000f7b8: 00040a13 mv s4,s0 -8000f7bc: 01d12c23 sw t4,24(sp) -8000f7c0: 000d0413 mv s0,s10 -8000f7c4: 03c12423 sw t3,40(sp) -8000f7c8: 000c8d13 mv s10,s9 -8000f7cc: 01012903 lw s2,16(sp) -8000f7d0: 000c0c93 mv s9,s8 -8000f7d4: 00080c13 mv s8,a6 -8000f7d8: 00c0006f j 8000f7e4 <_svfiprintf_r+0xc30> -8000f7dc: ff040413 addi s0,s0,-16 -8000f7e0: 0486da63 bge a3,s0,8000f834 <_svfiprintf_r+0xc80> -8000f7e4: 01078793 addi a5,a5,16 -8000f7e8: 00160613 addi a2,a2,1 -8000f7ec: 01672023 sw s6,0(a4) -8000f7f0: 00d72223 sw a3,4(a4) -8000f7f4: 04f12423 sw a5,72(sp) -8000f7f8: 04c12223 sw a2,68(sp) -8000f7fc: 00870713 addi a4,a4,8 -8000f800: fccf5ee3 bge t5,a2,8000f7dc <_svfiprintf_r+0xc28> -8000f804: 04010613 addi a2,sp,64 -8000f808: 000a8593 mv a1,s5 -8000f80c: 00090513 mv a0,s2 -8000f810: 9e8ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f814: d8051863 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f818: 01000693 li a3,16 -8000f81c: ff040413 addi s0,s0,-16 -8000f820: 04812783 lw a5,72(sp) -8000f824: 04412603 lw a2,68(sp) -8000f828: 00098713 mv a4,s3 -8000f82c: 00700f13 li t5,7 -8000f830: fa86cae3 blt a3,s0,8000f7e4 <_svfiprintf_r+0xc30> -8000f834: 01812e83 lw t4,24(sp) -8000f838: 02812e03 lw t3,40(sp) -8000f83c: 02c12903 lw s2,44(sp) -8000f840: 000c0813 mv a6,s8 -8000f844: 000c8c13 mv s8,s9 -8000f848: 000d0c93 mv s9,s10 -8000f84c: 00040d13 mv s10,s0 -8000f850: 000a0413 mv s0,s4 -8000f854: 000d8a13 mv s4,s11 -8000f858: 00070d93 mv s11,a4 -8000f85c: 01a787b3 add a5,a5,s10 -8000f860: 00160613 addi a2,a2,1 -8000f864: 016da023 sw s6,0(s11) -8000f868: 01ada223 sw s10,4(s11) -8000f86c: 04f12423 sw a5,72(sp) -8000f870: 04c12223 sw a2,68(sp) -8000f874: 00700693 li a3,7 -8000f878: 008d8d93 addi s11,s11,8 -8000f87c: e8c6d263 bge a3,a2,8000ef00 <_svfiprintf_r+0x34c> -8000f880: 01012503 lw a0,16(sp) -8000f884: 04010613 addi a2,sp,64 -8000f888: 000a8593 mv a1,s5 -8000f88c: 03012623 sw a6,44(sp) -8000f890: 03c12423 sw t3,40(sp) -8000f894: 01d12c23 sw t4,24(sp) -8000f898: 960ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f89c: d0051463 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f8a0: 04812783 lw a5,72(sp) -8000f8a4: 04412603 lw a2,68(sp) -8000f8a8: 00098d93 mv s11,s3 -8000f8ac: 02c12803 lw a6,44(sp) -8000f8b0: 02812e03 lw t3,40(sp) -8000f8b4: 01812e83 lw t4,24(sp) -8000f8b8: e48ff06f j 8000ef00 <_svfiprintf_r+0x34c> -8000f8bc: 01012503 lw a0,16(sp) -8000f8c0: 04010613 addi a2,sp,64 -8000f8c4: 000a8593 mv a1,s5 -8000f8c8: 03012623 sw a6,44(sp) -8000f8cc: 03c12423 sw t3,40(sp) -8000f8d0: 01d12c23 sw t4,24(sp) -8000f8d4: 924ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f8d8: cc051663 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f8dc: 04412603 lw a2,68(sp) -8000f8e0: 04812783 lw a5,72(sp) -8000f8e4: 05410693 addi a3,sp,84 -8000f8e8: 00160593 addi a1,a2,1 -8000f8ec: 00098d93 mv s11,s3 -8000f8f0: 02c12803 lw a6,44(sp) -8000f8f4: 02812e03 lw t3,40(sp) -8000f8f8: 01812e83 lw t4,24(sp) -8000f8fc: e50ff06f j 8000ef4c <_svfiprintf_r+0x398> -8000f900: 01012503 lw a0,16(sp) -8000f904: 04010613 addi a2,sp,64 -8000f908: 000a8593 mv a1,s5 -8000f90c: 03012423 sw a6,40(sp) -8000f910: 01c12c23 sw t3,24(sp) -8000f914: 8e4ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f918: c8051663 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f91c: 04412603 lw a2,68(sp) -8000f920: 04812783 lw a5,72(sp) -8000f924: 05410693 addi a3,sp,84 -8000f928: 00160593 addi a1,a2,1 -8000f92c: 00098d93 mv s11,s3 -8000f930: 02812803 lw a6,40(sp) -8000f934: 01812e03 lw t3,24(sp) -8000f938: e4cff06f j 8000ef84 <_svfiprintf_r+0x3d0> -8000f93c: 34081c63 bnez a6,8000fc94 <_svfiprintf_r+0x10e0> -8000f940: 00000813 li a6,0 -8000f944: 00000c93 li s9,0 -8000f948: 0f010b93 addi s7,sp,240 -8000f94c: d28ff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000f950: 20097613 andi a2,s2,512 -8000f954: 2e061663 bnez a2,8000fc40 <_svfiprintf_r+0x108c> -8000f958: 00078d13 mv s10,a5 -8000f95c: 00000c93 li s9,0 -8000f960: cc4ff06f j 8000ee24 <_svfiprintf_r+0x270> -8000f964: 01012503 lw a0,16(sp) -8000f968: 04010613 addi a2,sp,64 -8000f96c: 000a8593 mv a1,s5 -8000f970: 888ff0ef jal ra,8000e9f8 <__ssprint_r> -8000f974: c2051863 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000f978: 04412583 lw a1,68(sp) -8000f97c: 04812783 lw a5,72(sp) -8000f980: 05410693 addi a3,sp,84 -8000f984: 00158593 addi a1,a1,1 -8000f988: 00098d93 mv s11,s3 -8000f98c: e08ff06f j 8000ef94 <_svfiprintf_r+0x3e0> -8000f990: 000a0c13 mv s8,s4 -8000f994: b3cff06f j 8000ecd0 <_svfiprintf_r+0x11c> -8000f998: 01c12783 lw a5,28(sp) -8000f99c: 000a4683 lbu a3,0(s4) -8000f9a0: b4078c63 beqz a5,8000ecf8 <_svfiprintf_r+0x144> -8000f9a4: 0007c783 lbu a5,0(a5) -8000f9a8: b4078863 beqz a5,8000ecf8 <_svfiprintf_r+0x144> -8000f9ac: 40096913 ori s2,s2,1024 -8000f9b0: b48ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000f9b4: 03000613 li a2,48 -8000f9b8: 00296913 ori s2,s2,2 -8000f9bc: 02d10ea3 sb a3,61(sp) -8000f9c0: 02c10e23 sb a2,60(sp) -8000f9c4: bff97c13 andi s8,s2,-1025 -8000f9c8: 00200693 li a3,2 -8000f9cc: c70ff06f j 8000ee3c <_svfiprintf_r+0x288> -8000f9d0: 00072783 lw a5,0(a4) -8000f9d4: 00412703 lw a4,4(sp) -8000f9d8: 00d12423 sw a3,8(sp) -8000f9dc: 41f75613 srai a2,a4,0x1f -8000f9e0: 00e7a023 sw a4,0(a5) -8000f9e4: 00c7a223 sw a2,4(a5) -8000f9e8: a74ff06f j 8000ec5c <_svfiprintf_r+0xa8> -8000f9ec: 000b8513 mv a0,s7 -8000f9f0: c2df90ef jal ra,8000961c -8000f9f4: 00050c93 mv s9,a0 -8000f9f8: 01a12423 sw s10,8(sp) -8000f9fc: 00000813 li a6,0 -8000fa00: c74ff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000fa04: 04000593 li a1,64 -8000fa08: af8f10ef jal ra,80000d00 <_malloc_r> -8000fa0c: 00aaa023 sw a0,0(s5) -8000fa10: 00aaa823 sw a0,16(s5) -8000fa14: 2c050a63 beqz a0,8000fce8 <_svfiprintf_r+0x1134> -8000fa18: 04000793 li a5,64 -8000fa1c: 00faaa23 sw a5,20(s5) -8000fa20: 9f0ff06f j 8000ec10 <_svfiprintf_r+0x5c> -8000fa24: 400c7793 andi a5,s8,1024 -8000fa28: 0f010b93 addi s7,sp,240 -8000fa2c: 00812c23 sw s0,24(sp) -8000fa30: 00078413 mv s0,a5 -8000fa34: 000c8793 mv a5,s9 -8000fa38: 03412623 sw s4,44(sp) -8000fa3c: 000a8c93 mv s9,s5 -8000fa40: 00000913 li s2,0 -8000fa44: 000b8a93 mv s5,s7 -8000fa48: 03012423 sw a6,40(sp) -8000fa4c: 01c12a03 lw s4,28(sp) -8000fa50: 00078b93 mv s7,a5 -8000fa54: 0240006f j 8000fa78 <_svfiprintf_r+0xec4> -8000fa58: 00a00613 li a2,10 -8000fa5c: 00000693 li a3,0 -8000fa60: 000d0513 mv a0,s10 -8000fa64: 000b8593 mv a1,s7 -8000fa68: 53c000ef jal ra,8000ffa4 <__udivdi3> -8000fa6c: 1a0b8863 beqz s7,8000fc1c <_svfiprintf_r+0x1068> -8000fa70: 00050d13 mv s10,a0 -8000fa74: 00058b93 mv s7,a1 -8000fa78: 00a00613 li a2,10 -8000fa7c: 00000693 li a3,0 -8000fa80: 000d0513 mv a0,s10 -8000fa84: 000b8593 mv a1,s7 -8000fa88: 151000ef jal ra,800103d8 <__umoddi3> -8000fa8c: 03050513 addi a0,a0,48 -8000fa90: feaa8fa3 sb a0,-1(s5) -8000fa94: 00190913 addi s2,s2,1 -8000fa98: fffa8a93 addi s5,s5,-1 -8000fa9c: fa040ee3 beqz s0,8000fa58 <_svfiprintf_r+0xea4> -8000faa0: 000a4683 lbu a3,0(s4) -8000faa4: fb269ae3 bne a3,s2,8000fa58 <_svfiprintf_r+0xea4> -8000faa8: 0ff00793 li a5,255 -8000faac: faf906e3 beq s2,a5,8000fa58 <_svfiprintf_r+0xea4> -8000fab0: 120b9663 bnez s7,8000fbdc <_svfiprintf_r+0x1028> -8000fab4: 00900793 li a5,9 -8000fab8: 13a7e263 bltu a5,s10,8000fbdc <_svfiprintf_r+0x1028> -8000fabc: 000a8b93 mv s7,s5 -8000fac0: 0f010793 addi a5,sp,240 -8000fac4: 01412e23 sw s4,28(sp) -8000fac8: 000c8a93 mv s5,s9 -8000facc: 01812403 lw s0,24(sp) -8000fad0: 02812803 lw a6,40(sp) -8000fad4: 02c12a03 lw s4,44(sp) -8000fad8: 41778cb3 sub s9,a5,s7 -8000fadc: 000c0913 mv s2,s8 -8000fae0: b94ff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000fae4: 001a4683 lbu a3,1(s4) -8000fae8: 20096913 ori s2,s2,512 -8000faec: 001a0a13 addi s4,s4,1 -8000faf0: a08ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000faf4: 01012503 lw a0,16(sp) -8000faf8: 04010613 addi a2,sp,64 -8000fafc: 000a8593 mv a1,s5 -8000fb00: 01012c23 sw a6,24(sp) -8000fb04: ef5fe0ef jal ra,8000e9f8 <__ssprint_r> -8000fb08: a8051e63 bnez a0,8000eda4 <_svfiprintf_r+0x1f0> -8000fb0c: 04412603 lw a2,68(sp) -8000fb10: 04812783 lw a5,72(sp) -8000fb14: 05410693 addi a3,sp,84 -8000fb18: 00160593 addi a1,a2,1 -8000fb1c: 00098d93 mv s11,s3 -8000fb20: 01812803 lw a6,24(sp) -8000fb24: c68ff06f j 8000ef8c <_svfiprintf_r+0x3d8> -8000fb28: 001a4683 lbu a3,1(s4) -8000fb2c: 02096913 ori s2,s2,32 -8000fb30: 001a0a13 addi s4,s4,1 -8000fb34: 9c4ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000fb38: 00812783 lw a5,8(sp) -8000fb3c: 00412703 lw a4,4(sp) -8000fb40: 0007a783 lw a5,0(a5) -8000fb44: 00d12423 sw a3,8(sp) -8000fb48: 00e7a023 sw a4,0(a5) -8000fb4c: 910ff06f j 8000ec5c <_svfiprintf_r+0xa8> -8000fb50: 00600793 li a5,6 -8000fb54: 00080c93 mv s9,a6 -8000fb58: 0107f463 bgeu a5,a6,8000fb60 <_svfiprintf_r+0xfac> -8000fb5c: 00600c93 li s9,6 -8000fb60: 80015337 lui t1,0x80015 -8000fb64: 000c8c13 mv s8,s9 -8000fb68: 01a12423 sw s10,8(sp) -8000fb6c: 80830b93 addi s7,t1,-2040 # 80014808 <__BSS_END__+0xffffda90> -8000fb70: b68ff06f j 8000eed8 <_svfiprintf_r+0x324> -8000fb74: 20097613 andi a2,s2,512 -8000fb78: 10060463 beqz a2,8000fc80 <_svfiprintf_r+0x10cc> -8000fb7c: 0ff7fd13 andi s10,a5,255 -8000fb80: 00000c93 li s9,0 -8000fb84: 00090893 mv a7,s2 -8000fb88: 00d12423 sw a3,8(sp) -8000fb8c: 955ff06f j 8000f4e0 <_svfiprintf_r+0x92c> -8000fb90: 20097613 andi a2,s2,512 -8000fb94: 0c060a63 beqz a2,8000fc68 <_svfiprintf_r+0x10b4> -8000fb98: 00d12423 sw a3,8(sp) -8000fb9c: 0ff7fd13 andi s10,a5,255 -8000fba0: 00000c93 li s9,0 -8000fba4: 00090c13 mv s8,s2 -8000fba8: 00100693 li a3,1 -8000fbac: a90ff06f j 8000ee3c <_svfiprintf_r+0x288> -8000fbb0: 20097793 andi a5,s2,512 -8000fbb4: 08078c63 beqz a5,8000fc4c <_svfiprintf_r+0x1098> -8000fbb8: 00812783 lw a5,8(sp) -8000fbbc: 00090c13 mv s8,s2 -8000fbc0: 00d12423 sw a3,8(sp) -8000fbc4: 00078d03 lb s10,0(a5) -8000fbc8: 41fd5c93 srai s9,s10,0x1f -8000fbcc: 000c8693 mv a3,s9 -8000fbd0: d74ff06f j 8000f144 <_svfiprintf_r+0x590> -8000fbd4: 00068613 mv a2,a3 -8000fbd8: b45ff06f j 8000f71c <_svfiprintf_r+0xb68> -8000fbdc: 02012783 lw a5,32(sp) -8000fbe0: 02412583 lw a1,36(sp) -8000fbe4: 00000913 li s2,0 -8000fbe8: 40fa8ab3 sub s5,s5,a5 -8000fbec: 00078613 mv a2,a5 -8000fbf0: 000a8513 mv a0,s5 -8000fbf4: ab5f90ef jal ra,800096a8 -8000fbf8: 001a4803 lbu a6,1(s4) -8000fbfc: 00a00613 li a2,10 -8000fc00: 00000693 li a3,0 -8000fc04: 01003833 snez a6,a6 -8000fc08: 000d0513 mv a0,s10 -8000fc0c: 000b8593 mv a1,s7 -8000fc10: 010a0a33 add s4,s4,a6 -8000fc14: 390000ef jal ra,8000ffa4 <__udivdi3> -8000fc18: e59ff06f j 8000fa70 <_svfiprintf_r+0xebc> -8000fc1c: 00900793 li a5,9 -8000fc20: e5a7e8e3 bltu a5,s10,8000fa70 <_svfiprintf_r+0xebc> -8000fc24: e99ff06f j 8000fabc <_svfiprintf_r+0xf08> -8000fc28: 00812783 lw a5,8(sp) -8000fc2c: 00412703 lw a4,4(sp) -8000fc30: 00d12423 sw a3,8(sp) -8000fc34: 0007a783 lw a5,0(a5) -8000fc38: 00e79023 sh a4,0(a5) -8000fc3c: 820ff06f j 8000ec5c <_svfiprintf_r+0xa8> -8000fc40: 0ff7fd13 andi s10,a5,255 -8000fc44: 00000c93 li s9,0 -8000fc48: 9dcff06f j 8000ee24 <_svfiprintf_r+0x270> -8000fc4c: 00812783 lw a5,8(sp) -8000fc50: 00090c13 mv s8,s2 -8000fc54: 00d12423 sw a3,8(sp) -8000fc58: 0007ad03 lw s10,0(a5) -8000fc5c: 41fd5c93 srai s9,s10,0x1f -8000fc60: 000c8693 mv a3,s9 -8000fc64: ce0ff06f j 8000f144 <_svfiprintf_r+0x590> -8000fc68: 00d12423 sw a3,8(sp) -8000fc6c: 00078d13 mv s10,a5 -8000fc70: 00000c93 li s9,0 -8000fc74: 00090c13 mv s8,s2 -8000fc78: 00100693 li a3,1 -8000fc7c: 9c0ff06f j 8000ee3c <_svfiprintf_r+0x288> -8000fc80: 00078d13 mv s10,a5 -8000fc84: 00000c93 li s9,0 -8000fc88: 00090893 mv a7,s2 -8000fc8c: 00d12423 sw a3,8(sp) -8000fc90: 851ff06f j 8000f4e0 <_svfiprintf_r+0x92c> -8000fc94: 00090c13 mv s8,s2 -8000fc98: cd4ff06f j 8000f16c <_svfiprintf_r+0x5b8> -8000fc9c: 00080c93 mv s9,a6 -8000fca0: 01a12423 sw s10,8(sp) -8000fca4: 00000813 li a6,0 -8000fca8: 9ccff06f j 8000ee74 <_svfiprintf_r+0x2c0> -8000fcac: 00068513 mv a0,a3 -8000fcb0: 00058613 mv a2,a1 -8000fcb4: 9a1ff06f j 8000f654 <_svfiprintf_r+0xaa0> -8000fcb8: fff00793 li a5,-1 -8000fcbc: 00f12223 sw a5,4(sp) -8000fcc0: 8f0ff06f j 8000edb0 <_svfiprintf_r+0x1fc> -8000fcc4: 00812703 lw a4,8(sp) -8000fcc8: 00072b83 lw s7,0(a4) -8000fccc: 00470713 addi a4,a4,4 -8000fcd0: 000bd463 bgez s7,8000fcd8 <_svfiprintf_r+0x1124> -8000fcd4: fff00b93 li s7,-1 -8000fcd8: 001a4683 lbu a3,1(s4) -8000fcdc: 00e12423 sw a4,8(sp) -8000fce0: 00078a13 mv s4,a5 -8000fce4: 814ff06f j 8000ecf8 <_svfiprintf_r+0x144> -8000fce8: 00c00793 li a5,12 -8000fcec: 00fba023 sw a5,0(s7) -8000fcf0: fff00793 li a5,-1 -8000fcf4: 00f12223 sw a5,4(sp) -8000fcf8: 8b8ff06f j 8000edb0 <_svfiprintf_r+0x1fc> -8000fcfc: 00090c13 mv s8,s2 -8000fd00: c30ff06f j 8000f130 <_svfiprintf_r+0x57c> -8000fd04: 00090c13 mv s8,s2 -8000fd08: b6cff06f j 8000f074 <_svfiprintf_r+0x4c0> -8000fd0c: 00090893 mv a7,s2 -8000fd10: b38ff06f j 8000f048 <_svfiprintf_r+0x494> - -8000fd14 <__swbuf_r>: -8000fd14: fe010113 addi sp,sp,-32 -8000fd18: 00812c23 sw s0,24(sp) -8000fd1c: 00912a23 sw s1,20(sp) -8000fd20: 01212823 sw s2,16(sp) -8000fd24: 00112e23 sw ra,28(sp) -8000fd28: 01312623 sw s3,12(sp) -8000fd2c: 00050913 mv s2,a0 -8000fd30: 00058493 mv s1,a1 -8000fd34: 00060413 mv s0,a2 -8000fd38: 00050663 beqz a0,8000fd44 <__swbuf_r+0x30> -8000fd3c: 03852783 lw a5,56(a0) -8000fd40: 14078863 beqz a5,8000fe90 <__swbuf_r+0x17c> -8000fd44: 00c41703 lh a4,12(s0) -8000fd48: 01842783 lw a5,24(s0) -8000fd4c: 01071693 slli a3,a4,0x10 -8000fd50: 0106d693 srli a3,a3,0x10 -8000fd54: 00f42423 sw a5,8(s0) -8000fd58: 0086f793 andi a5,a3,8 -8000fd5c: 08078263 beqz a5,8000fde0 <__swbuf_r+0xcc> -8000fd60: 01042783 lw a5,16(s0) -8000fd64: 06078e63 beqz a5,8000fde0 <__swbuf_r+0xcc> -8000fd68: 01269613 slli a2,a3,0x12 -8000fd6c: 0ff4f993 andi s3,s1,255 -8000fd70: 0ff4f493 andi s1,s1,255 -8000fd74: 08065e63 bgez a2,8000fe10 <__swbuf_r+0xfc> -8000fd78: 00042703 lw a4,0(s0) -8000fd7c: 01442683 lw a3,20(s0) -8000fd80: 40f707b3 sub a5,a4,a5 -8000fd84: 0ad7de63 bge a5,a3,8000fe40 <__swbuf_r+0x12c> -8000fd88: 00842683 lw a3,8(s0) -8000fd8c: 00170613 addi a2,a4,1 -8000fd90: 00c42023 sw a2,0(s0) -8000fd94: fff68693 addi a3,a3,-1 -8000fd98: 00d42423 sw a3,8(s0) -8000fd9c: 01370023 sb s3,0(a4) -8000fda0: 01442703 lw a4,20(s0) -8000fda4: 00178793 addi a5,a5,1 -8000fda8: 0cf70863 beq a4,a5,8000fe78 <__swbuf_r+0x164> -8000fdac: 00c45783 lhu a5,12(s0) -8000fdb0: 0017f793 andi a5,a5,1 -8000fdb4: 00078663 beqz a5,8000fdc0 <__swbuf_r+0xac> -8000fdb8: 00a00793 li a5,10 -8000fdbc: 0af48e63 beq s1,a5,8000fe78 <__swbuf_r+0x164> -8000fdc0: 01c12083 lw ra,28(sp) -8000fdc4: 01812403 lw s0,24(sp) -8000fdc8: 00048513 mv a0,s1 -8000fdcc: 01012903 lw s2,16(sp) -8000fdd0: 01412483 lw s1,20(sp) -8000fdd4: 00c12983 lw s3,12(sp) -8000fdd8: 02010113 addi sp,sp,32 -8000fddc: 00008067 ret -8000fde0: 00040593 mv a1,s0 -8000fde4: 00090513 mv a0,s2 -8000fde8: cd4f40ef jal ra,800042bc <__swsetup_r> -8000fdec: 08051e63 bnez a0,8000fe88 <__swbuf_r+0x174> -8000fdf0: 00c41703 lh a4,12(s0) -8000fdf4: 0ff4f993 andi s3,s1,255 -8000fdf8: 01042783 lw a5,16(s0) -8000fdfc: 01071693 slli a3,a4,0x10 -8000fe00: 0106d693 srli a3,a3,0x10 -8000fe04: 01269613 slli a2,a3,0x12 -8000fe08: 0ff4f493 andi s1,s1,255 -8000fe0c: f60646e3 bltz a2,8000fd78 <__swbuf_r+0x64> -8000fe10: 06442683 lw a3,100(s0) -8000fe14: 00002637 lui a2,0x2 -8000fe18: 00c76733 or a4,a4,a2 -8000fe1c: ffffe637 lui a2,0xffffe -8000fe20: fff60613 addi a2,a2,-1 # ffffdfff <__BSS_END__+0x7ffe7287> -8000fe24: 00c6f6b3 and a3,a3,a2 -8000fe28: 00e41623 sh a4,12(s0) -8000fe2c: 00042703 lw a4,0(s0) -8000fe30: 06d42223 sw a3,100(s0) -8000fe34: 01442683 lw a3,20(s0) -8000fe38: 40f707b3 sub a5,a4,a5 -8000fe3c: f4d7c6e3 blt a5,a3,8000fd88 <__swbuf_r+0x74> -8000fe40: 00040593 mv a1,s0 -8000fe44: 00090513 mv a0,s2 -8000fe48: 9e5f40ef jal ra,8000482c <_fflush_r> -8000fe4c: 02051e63 bnez a0,8000fe88 <__swbuf_r+0x174> -8000fe50: 00042703 lw a4,0(s0) -8000fe54: 00842683 lw a3,8(s0) -8000fe58: 00100793 li a5,1 -8000fe5c: 00170613 addi a2,a4,1 -8000fe60: fff68693 addi a3,a3,-1 -8000fe64: 00c42023 sw a2,0(s0) -8000fe68: 00d42423 sw a3,8(s0) -8000fe6c: 01370023 sb s3,0(a4) -8000fe70: 01442703 lw a4,20(s0) -8000fe74: f2f71ce3 bne a4,a5,8000fdac <__swbuf_r+0x98> -8000fe78: 00040593 mv a1,s0 -8000fe7c: 00090513 mv a0,s2 -8000fe80: 9adf40ef jal ra,8000482c <_fflush_r> -8000fe84: f2050ee3 beqz a0,8000fdc0 <__swbuf_r+0xac> -8000fe88: fff00493 li s1,-1 -8000fe8c: f35ff06f j 8000fdc0 <__swbuf_r+0xac> -8000fe90: d39f40ef jal ra,80004bc8 <__sinit> -8000fe94: eb1ff06f j 8000fd44 <__swbuf_r+0x30> - -8000fe98 <__swbuf>: -8000fe98: 00058613 mv a2,a1 -8000fe9c: 00050593 mv a1,a0 -8000fea0: 1c81a503 lw a0,456(gp) # 80016d30 <_impure_ptr> -8000fea4: e71ff06f j 8000fd14 <__swbuf_r> - -8000fea8 <_wcrtomb_r>: -8000fea8: fe010113 addi sp,sp,-32 -8000feac: 00812c23 sw s0,24(sp) -8000feb0: 00912a23 sw s1,20(sp) -8000feb4: 00112e23 sw ra,28(sp) -8000feb8: 00050413 mv s0,a0 -8000febc: 00068493 mv s1,a3 -8000fec0: 1101a783 lw a5,272(gp) # 80016c78 <__global_locale+0xe0> -8000fec4: 02058263 beqz a1,8000fee8 <_wcrtomb_r+0x40> -8000fec8: 000780e7 jalr a5 -8000fecc: fff00793 li a5,-1 -8000fed0: 02f50663 beq a0,a5,8000fefc <_wcrtomb_r+0x54> -8000fed4: 01c12083 lw ra,28(sp) -8000fed8: 01812403 lw s0,24(sp) -8000fedc: 01412483 lw s1,20(sp) -8000fee0: 02010113 addi sp,sp,32 -8000fee4: 00008067 ret -8000fee8: 00000613 li a2,0 -8000feec: 00410593 addi a1,sp,4 -8000fef0: 000780e7 jalr a5 -8000fef4: fff00793 li a5,-1 -8000fef8: fcf51ee3 bne a0,a5,8000fed4 <_wcrtomb_r+0x2c> -8000fefc: 0004a023 sw zero,0(s1) -8000ff00: 08a00793 li a5,138 -8000ff04: 00f42023 sw a5,0(s0) -8000ff08: 01c12083 lw ra,28(sp) -8000ff0c: 01812403 lw s0,24(sp) -8000ff10: 01412483 lw s1,20(sp) -8000ff14: 02010113 addi sp,sp,32 -8000ff18: 00008067 ret - -8000ff1c : -8000ff1c: fe010113 addi sp,sp,-32 -8000ff20: 00812c23 sw s0,24(sp) -8000ff24: 00912a23 sw s1,20(sp) -8000ff28: 1c81a403 lw s0,456(gp) # 80016d30 <_impure_ptr> -8000ff2c: 00112e23 sw ra,28(sp) -8000ff30: 00060493 mv s1,a2 -8000ff34: 1101a783 lw a5,272(gp) # 80016c78 <__global_locale+0xe0> -8000ff38: 00060693 mv a3,a2 -8000ff3c: 02050863 beqz a0,8000ff6c -8000ff40: 00058613 mv a2,a1 -8000ff44: 00050593 mv a1,a0 -8000ff48: 00040513 mv a0,s0 -8000ff4c: 000780e7 jalr a5 -8000ff50: fff00793 li a5,-1 -8000ff54: 02f50863 beq a0,a5,8000ff84 -8000ff58: 01c12083 lw ra,28(sp) -8000ff5c: 01812403 lw s0,24(sp) -8000ff60: 01412483 lw s1,20(sp) -8000ff64: 02010113 addi sp,sp,32 -8000ff68: 00008067 ret -8000ff6c: 00000613 li a2,0 -8000ff70: 00410593 addi a1,sp,4 -8000ff74: 00040513 mv a0,s0 -8000ff78: 000780e7 jalr a5 -8000ff7c: fff00793 li a5,-1 -8000ff80: fcf51ce3 bne a0,a5,8000ff58 -8000ff84: 0004a023 sw zero,0(s1) -8000ff88: 08a00793 li a5,138 -8000ff8c: 00f42023 sw a5,0(s0) -8000ff90: 01c12083 lw ra,28(sp) -8000ff94: 01812403 lw s0,24(sp) -8000ff98: 01412483 lw s1,20(sp) -8000ff9c: 02010113 addi sp,sp,32 -8000ffa0: 00008067 ret - -8000ffa4 <__udivdi3>: -8000ffa4: 00058793 mv a5,a1 -8000ffa8: 00060813 mv a6,a2 -8000ffac: 00068893 mv a7,a3 -8000ffb0: 00050313 mv t1,a0 -8000ffb4: 28069663 bnez a3,80010240 <__udivdi3+0x29c> -8000ffb8: 80015737 lui a4,0x80015 -8000ffbc: 22470713 addi a4,a4,548 # 80015224 <__BSS_END__+0xffffe4ac> -8000ffc0: 0ec5f663 bgeu a1,a2,800100ac <__udivdi3+0x108> -8000ffc4: 000106b7 lui a3,0x10 -8000ffc8: 0cd67863 bgeu a2,a3,80010098 <__udivdi3+0xf4> -8000ffcc: 0ff00693 li a3,255 -8000ffd0: 00c6b6b3 sltu a3,a3,a2 -8000ffd4: 00369693 slli a3,a3,0x3 -8000ffd8: 00d658b3 srl a7,a2,a3 -8000ffdc: 01170733 add a4,a4,a7 -8000ffe0: 00074703 lbu a4,0(a4) -8000ffe4: 00d706b3 add a3,a4,a3 -8000ffe8: 02000713 li a4,32 -8000ffec: 40d70733 sub a4,a4,a3 -8000fff0: 00070c63 beqz a4,80010008 <__udivdi3+0x64> -8000fff4: 00e797b3 sll a5,a5,a4 -8000fff8: 00d556b3 srl a3,a0,a3 -8000fffc: 00e61833 sll a6,a2,a4 -80010000: 00f6e5b3 or a1,a3,a5 -80010004: 00e51333 sll t1,a0,a4 -80010008: 01085513 srli a0,a6,0x10 -8001000c: 02a5f733 remu a4,a1,a0 -80010010: 01081613 slli a2,a6,0x10 -80010014: 01065613 srli a2,a2,0x10 -80010018: 01035693 srli a3,t1,0x10 -8001001c: 02a5d5b3 divu a1,a1,a0 -80010020: 01071713 slli a4,a4,0x10 -80010024: 00d766b3 or a3,a4,a3 -80010028: 02b607b3 mul a5,a2,a1 -8001002c: 00058713 mv a4,a1 -80010030: 00f6fe63 bgeu a3,a5,8001004c <__udivdi3+0xa8> -80010034: 010686b3 add a3,a3,a6 -80010038: fff58713 addi a4,a1,-1 -8001003c: 0106e863 bltu a3,a6,8001004c <__udivdi3+0xa8> -80010040: 00f6f663 bgeu a3,a5,8001004c <__udivdi3+0xa8> -80010044: ffe58713 addi a4,a1,-2 -80010048: 010686b3 add a3,a3,a6 -8001004c: 40f686b3 sub a3,a3,a5 -80010050: 02a6f7b3 remu a5,a3,a0 -80010054: 01031313 slli t1,t1,0x10 -80010058: 01035313 srli t1,t1,0x10 -8001005c: 02a6d6b3 divu a3,a3,a0 -80010060: 01079793 slli a5,a5,0x10 -80010064: 0067e333 or t1,a5,t1 -80010068: 02d605b3 mul a1,a2,a3 -8001006c: 00068513 mv a0,a3 -80010070: 00b37c63 bgeu t1,a1,80010088 <__udivdi3+0xe4> -80010074: 00680333 add t1,a6,t1 -80010078: fff68513 addi a0,a3,-1 # ffff <_start-0x7fff0001> -8001007c: 01036663 bltu t1,a6,80010088 <__udivdi3+0xe4> -80010080: 00b37463 bgeu t1,a1,80010088 <__udivdi3+0xe4> -80010084: ffe68513 addi a0,a3,-2 -80010088: 01071713 slli a4,a4,0x10 -8001008c: 00a76733 or a4,a4,a0 -80010090: 00000593 li a1,0 -80010094: 0e40006f j 80010178 <__udivdi3+0x1d4> -80010098: 010008b7 lui a7,0x1000 -8001009c: 01000693 li a3,16 -800100a0: f3166ce3 bltu a2,a7,8000ffd8 <__udivdi3+0x34> -800100a4: 01800693 li a3,24 -800100a8: f31ff06f j 8000ffd8 <__udivdi3+0x34> -800100ac: 00061663 bnez a2,800100b8 <__udivdi3+0x114> -800100b0: 00100693 li a3,1 -800100b4: 02c6d833 divu a6,a3,a2 -800100b8: 000106b7 lui a3,0x10 -800100bc: 0cd87263 bgeu a6,a3,80010180 <__udivdi3+0x1dc> -800100c0: 0ff00693 li a3,255 -800100c4: 0106f463 bgeu a3,a6,800100cc <__udivdi3+0x128> -800100c8: 00800893 li a7,8 -800100cc: 011856b3 srl a3,a6,a7 -800100d0: 00d70733 add a4,a4,a3 -800100d4: 00074683 lbu a3,0(a4) -800100d8: 02000713 li a4,32 -800100dc: 011686b3 add a3,a3,a7 -800100e0: 40d70733 sub a4,a4,a3 -800100e4: 0a071863 bnez a4,80010194 <__udivdi3+0x1f0> -800100e8: 410787b3 sub a5,a5,a6 -800100ec: 00100593 li a1,1 -800100f0: 01085613 srli a2,a6,0x10 -800100f4: 01081893 slli a7,a6,0x10 -800100f8: 0108d893 srli a7,a7,0x10 -800100fc: 01035693 srli a3,t1,0x10 -80010100: 02c7f733 remu a4,a5,a2 -80010104: 02c7d7b3 divu a5,a5,a2 -80010108: 01071713 slli a4,a4,0x10 -8001010c: 00d766b3 or a3,a4,a3 -80010110: 02f88533 mul a0,a7,a5 -80010114: 00078713 mv a4,a5 -80010118: 00a6fe63 bgeu a3,a0,80010134 <__udivdi3+0x190> -8001011c: 010686b3 add a3,a3,a6 -80010120: fff78713 addi a4,a5,-1 -80010124: 0106e863 bltu a3,a6,80010134 <__udivdi3+0x190> -80010128: 00a6f663 bgeu a3,a0,80010134 <__udivdi3+0x190> -8001012c: ffe78713 addi a4,a5,-2 -80010130: 010686b3 add a3,a3,a6 -80010134: 40a686b3 sub a3,a3,a0 -80010138: 02c6f7b3 remu a5,a3,a2 -8001013c: 01031313 slli t1,t1,0x10 -80010140: 01035313 srli t1,t1,0x10 -80010144: 02c6d6b3 divu a3,a3,a2 -80010148: 01079793 slli a5,a5,0x10 -8001014c: 0067e333 or t1,a5,t1 -80010150: 02d888b3 mul a7,a7,a3 -80010154: 00068513 mv a0,a3 -80010158: 01137c63 bgeu t1,a7,80010170 <__udivdi3+0x1cc> -8001015c: 00680333 add t1,a6,t1 -80010160: fff68513 addi a0,a3,-1 # ffff <_start-0x7fff0001> -80010164: 01036663 bltu t1,a6,80010170 <__udivdi3+0x1cc> -80010168: 01137463 bgeu t1,a7,80010170 <__udivdi3+0x1cc> -8001016c: ffe68513 addi a0,a3,-2 -80010170: 01071713 slli a4,a4,0x10 -80010174: 00a76733 or a4,a4,a0 -80010178: 00070513 mv a0,a4 -8001017c: 00008067 ret -80010180: 010006b7 lui a3,0x1000 -80010184: 01000893 li a7,16 -80010188: f4d862e3 bltu a6,a3,800100cc <__udivdi3+0x128> -8001018c: 01800893 li a7,24 -80010190: f3dff06f j 800100cc <__udivdi3+0x128> -80010194: 00e81833 sll a6,a6,a4 -80010198: 00d7d5b3 srl a1,a5,a3 -8001019c: 00e51333 sll t1,a0,a4 -800101a0: 00d556b3 srl a3,a0,a3 -800101a4: 01085513 srli a0,a6,0x10 -800101a8: 00e797b3 sll a5,a5,a4 -800101ac: 02a5f733 remu a4,a1,a0 -800101b0: 00f6e8b3 or a7,a3,a5 -800101b4: 01081793 slli a5,a6,0x10 -800101b8: 0107d793 srli a5,a5,0x10 -800101bc: 0108d613 srli a2,a7,0x10 -800101c0: 02a5d5b3 divu a1,a1,a0 -800101c4: 01071713 slli a4,a4,0x10 -800101c8: 00c76733 or a4,a4,a2 -800101cc: 02b786b3 mul a3,a5,a1 -800101d0: 00058613 mv a2,a1 -800101d4: 00d77e63 bgeu a4,a3,800101f0 <__udivdi3+0x24c> -800101d8: 01070733 add a4,a4,a6 -800101dc: fff58613 addi a2,a1,-1 -800101e0: 01076863 bltu a4,a6,800101f0 <__udivdi3+0x24c> -800101e4: 00d77663 bgeu a4,a3,800101f0 <__udivdi3+0x24c> -800101e8: ffe58613 addi a2,a1,-2 -800101ec: 01070733 add a4,a4,a6 -800101f0: 40d706b3 sub a3,a4,a3 -800101f4: 02a6f733 remu a4,a3,a0 -800101f8: 01089893 slli a7,a7,0x10 -800101fc: 0108d893 srli a7,a7,0x10 -80010200: 02a6d6b3 divu a3,a3,a0 -80010204: 01071713 slli a4,a4,0x10 -80010208: 02d785b3 mul a1,a5,a3 -8001020c: 011767b3 or a5,a4,a7 -80010210: 00068713 mv a4,a3 -80010214: 00b7fe63 bgeu a5,a1,80010230 <__udivdi3+0x28c> -80010218: 010787b3 add a5,a5,a6 -8001021c: fff68713 addi a4,a3,-1 # ffffff <_start-0x7f000001> -80010220: 0107e863 bltu a5,a6,80010230 <__udivdi3+0x28c> -80010224: 00b7f663 bgeu a5,a1,80010230 <__udivdi3+0x28c> -80010228: ffe68713 addi a4,a3,-2 -8001022c: 010787b3 add a5,a5,a6 -80010230: 40b787b3 sub a5,a5,a1 -80010234: 01061593 slli a1,a2,0x10 -80010238: 00e5e5b3 or a1,a1,a4 -8001023c: eb5ff06f j 800100f0 <__udivdi3+0x14c> -80010240: 18d5e663 bltu a1,a3,800103cc <__udivdi3+0x428> -80010244: 00010737 lui a4,0x10 -80010248: 04e6f463 bgeu a3,a4,80010290 <__udivdi3+0x2ec> -8001024c: 0ff00813 li a6,255 -80010250: 00d83733 sltu a4,a6,a3 -80010254: 00371713 slli a4,a4,0x3 -80010258: 80015837 lui a6,0x80015 -8001025c: 22480813 addi a6,a6,548 # 80015224 <__BSS_END__+0xffffe4ac> -80010260: 00e6d5b3 srl a1,a3,a4 -80010264: 010585b3 add a1,a1,a6 -80010268: 0005c803 lbu a6,0(a1) -8001026c: 02000593 li a1,32 -80010270: 00e80833 add a6,a6,a4 -80010274: 410585b3 sub a1,a1,a6 -80010278: 02059663 bnez a1,800102a4 <__udivdi3+0x300> -8001027c: 00100713 li a4,1 -80010280: eef6ece3 bltu a3,a5,80010178 <__udivdi3+0x1d4> -80010284: 00c53533 sltu a0,a0,a2 -80010288: 00154713 xori a4,a0,1 -8001028c: eedff06f j 80010178 <__udivdi3+0x1d4> -80010290: 010005b7 lui a1,0x1000 -80010294: 01000713 li a4,16 -80010298: fcb6e0e3 bltu a3,a1,80010258 <__udivdi3+0x2b4> -8001029c: 01800713 li a4,24 -800102a0: fb9ff06f j 80010258 <__udivdi3+0x2b4> -800102a4: 01065733 srl a4,a2,a6 -800102a8: 00b696b3 sll a3,a3,a1 -800102ac: 00d766b3 or a3,a4,a3 -800102b0: 0106de93 srli t4,a3,0x10 -800102b4: 0107d733 srl a4,a5,a6 -800102b8: 03d778b3 remu a7,a4,t4 -800102bc: 00b797b3 sll a5,a5,a1 -800102c0: 01055833 srl a6,a0,a6 -800102c4: 00f86333 or t1,a6,a5 -800102c8: 01069793 slli a5,a3,0x10 -800102cc: 0107d793 srli a5,a5,0x10 -800102d0: 01035813 srli a6,t1,0x10 -800102d4: 00b61633 sll a2,a2,a1 -800102d8: 03d75733 divu a4,a4,t4 -800102dc: 01089893 slli a7,a7,0x10 -800102e0: 0108e833 or a6,a7,a6 -800102e4: 02e78f33 mul t5,a5,a4 -800102e8: 00070e13 mv t3,a4 -800102ec: 01e87e63 bgeu a6,t5,80010308 <__udivdi3+0x364> -800102f0: 00d80833 add a6,a6,a3 -800102f4: fff70e13 addi t3,a4,-1 # ffff <_start-0x7fff0001> -800102f8: 00d86863 bltu a6,a3,80010308 <__udivdi3+0x364> -800102fc: 01e87663 bgeu a6,t5,80010308 <__udivdi3+0x364> -80010300: ffe70e13 addi t3,a4,-2 -80010304: 00d80833 add a6,a6,a3 -80010308: 41e80833 sub a6,a6,t5 -8001030c: 03d878b3 remu a7,a6,t4 -80010310: 03d85833 divu a6,a6,t4 -80010314: 01089893 slli a7,a7,0x10 -80010318: 03078eb3 mul t4,a5,a6 -8001031c: 01031793 slli a5,t1,0x10 -80010320: 0107d793 srli a5,a5,0x10 -80010324: 00f8e7b3 or a5,a7,a5 -80010328: 00080713 mv a4,a6 -8001032c: 01d7fe63 bgeu a5,t4,80010348 <__udivdi3+0x3a4> -80010330: 00d787b3 add a5,a5,a3 -80010334: fff80713 addi a4,a6,-1 -80010338: 00d7e863 bltu a5,a3,80010348 <__udivdi3+0x3a4> -8001033c: 01d7f663 bgeu a5,t4,80010348 <__udivdi3+0x3a4> -80010340: ffe80713 addi a4,a6,-2 -80010344: 00d787b3 add a5,a5,a3 -80010348: 010e1e13 slli t3,t3,0x10 -8001034c: 41d787b3 sub a5,a5,t4 -80010350: 00010eb7 lui t4,0x10 -80010354: 00ee6733 or a4,t3,a4 -80010358: fffe8813 addi a6,t4,-1 # ffff <_start-0x7fff0001> -8001035c: 01077333 and t1,a4,a6 -80010360: 01075893 srli a7,a4,0x10 -80010364: 01067833 and a6,a2,a6 -80010368: 01065613 srli a2,a2,0x10 -8001036c: 03030e33 mul t3,t1,a6 -80010370: 03088833 mul a6,a7,a6 -80010374: 010e5693 srli a3,t3,0x10 -80010378: 02c30333 mul t1,t1,a2 -8001037c: 01030333 add t1,t1,a6 -80010380: 006686b3 add a3,a3,t1 -80010384: 02c888b3 mul a7,a7,a2 -80010388: 0106f463 bgeu a3,a6,80010390 <__udivdi3+0x3ec> -8001038c: 01d888b3 add a7,a7,t4 -80010390: 0106d613 srli a2,a3,0x10 -80010394: 011608b3 add a7,a2,a7 -80010398: 0317e663 bltu a5,a7,800103c4 <__udivdi3+0x420> -8001039c: cf179ae3 bne a5,a7,80010090 <__udivdi3+0xec> -800103a0: 000107b7 lui a5,0x10 -800103a4: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -800103a8: 00f6f6b3 and a3,a3,a5 -800103ac: 01069693 slli a3,a3,0x10 -800103b0: 00fe7e33 and t3,t3,a5 -800103b4: 00b51533 sll a0,a0,a1 -800103b8: 01c686b3 add a3,a3,t3 -800103bc: 00000593 li a1,0 -800103c0: dad57ce3 bgeu a0,a3,80010178 <__udivdi3+0x1d4> -800103c4: fff70713 addi a4,a4,-1 -800103c8: cc9ff06f j 80010090 <__udivdi3+0xec> -800103cc: 00000593 li a1,0 -800103d0: 00000713 li a4,0 -800103d4: da5ff06f j 80010178 <__udivdi3+0x1d4> - -800103d8 <__umoddi3>: -800103d8: 00060893 mv a7,a2 -800103dc: 00068713 mv a4,a3 -800103e0: 00050793 mv a5,a0 -800103e4: 00058813 mv a6,a1 -800103e8: 22069c63 bnez a3,80010620 <__umoddi3+0x248> -800103ec: 800156b7 lui a3,0x80015 -800103f0: 22468693 addi a3,a3,548 # 80015224 <__BSS_END__+0xffffe4ac> -800103f4: 0cc5fc63 bgeu a1,a2,800104cc <__umoddi3+0xf4> -800103f8: 00010337 lui t1,0x10 -800103fc: 0a667e63 bgeu a2,t1,800104b8 <__umoddi3+0xe0> -80010400: 0ff00313 li t1,255 -80010404: 00c37463 bgeu t1,a2,8001040c <__umoddi3+0x34> -80010408: 00800713 li a4,8 -8001040c: 00e65333 srl t1,a2,a4 -80010410: 006686b3 add a3,a3,t1 -80010414: 0006ce03 lbu t3,0(a3) -80010418: 02000313 li t1,32 -8001041c: 00ee0e33 add t3,t3,a4 -80010420: 41c30333 sub t1,t1,t3 -80010424: 00030c63 beqz t1,8001043c <__umoddi3+0x64> -80010428: 006595b3 sll a1,a1,t1 -8001042c: 01c55e33 srl t3,a0,t3 -80010430: 006618b3 sll a7,a2,t1 -80010434: 00be6833 or a6,t3,a1 -80010438: 006517b3 sll a5,a0,t1 -8001043c: 0108d613 srli a2,a7,0x10 -80010440: 02c87733 remu a4,a6,a2 -80010444: 01089513 slli a0,a7,0x10 -80010448: 01055513 srli a0,a0,0x10 -8001044c: 0107d693 srli a3,a5,0x10 -80010450: 02c85833 divu a6,a6,a2 -80010454: 01071713 slli a4,a4,0x10 -80010458: 00d766b3 or a3,a4,a3 -8001045c: 03050833 mul a6,a0,a6 -80010460: 0106fa63 bgeu a3,a6,80010474 <__umoddi3+0x9c> -80010464: 011686b3 add a3,a3,a7 -80010468: 0116e663 bltu a3,a7,80010474 <__umoddi3+0x9c> -8001046c: 0106f463 bgeu a3,a6,80010474 <__umoddi3+0x9c> -80010470: 011686b3 add a3,a3,a7 -80010474: 410686b3 sub a3,a3,a6 -80010478: 02c6f733 remu a4,a3,a2 -8001047c: 01079793 slli a5,a5,0x10 -80010480: 0107d793 srli a5,a5,0x10 -80010484: 02c6d6b3 divu a3,a3,a2 -80010488: 02d506b3 mul a3,a0,a3 -8001048c: 01071513 slli a0,a4,0x10 -80010490: 00f567b3 or a5,a0,a5 -80010494: 00d7fa63 bgeu a5,a3,800104a8 <__umoddi3+0xd0> -80010498: 011787b3 add a5,a5,a7 -8001049c: 0117e663 bltu a5,a7,800104a8 <__umoddi3+0xd0> -800104a0: 00d7f463 bgeu a5,a3,800104a8 <__umoddi3+0xd0> -800104a4: 011787b3 add a5,a5,a7 -800104a8: 40d787b3 sub a5,a5,a3 -800104ac: 0067d533 srl a0,a5,t1 -800104b0: 00000593 li a1,0 -800104b4: 00008067 ret -800104b8: 01000337 lui t1,0x1000 -800104bc: 01000713 li a4,16 -800104c0: f46666e3 bltu a2,t1,8001040c <__umoddi3+0x34> -800104c4: 01800713 li a4,24 -800104c8: f45ff06f j 8001040c <__umoddi3+0x34> -800104cc: 00061663 bnez a2,800104d8 <__umoddi3+0x100> -800104d0: 00100613 li a2,1 -800104d4: 031658b3 divu a7,a2,a7 -800104d8: 00010637 lui a2,0x10 -800104dc: 0ac8f263 bgeu a7,a2,80010580 <__umoddi3+0x1a8> -800104e0: 0ff00613 li a2,255 -800104e4: 01167463 bgeu a2,a7,800104ec <__umoddi3+0x114> -800104e8: 00800713 li a4,8 -800104ec: 00e8d633 srl a2,a7,a4 -800104f0: 00c686b3 add a3,a3,a2 -800104f4: 0006ce03 lbu t3,0(a3) -800104f8: 02000313 li t1,32 -800104fc: 00ee0e33 add t3,t3,a4 -80010500: 41c30333 sub t1,t1,t3 -80010504: 08031863 bnez t1,80010594 <__umoddi3+0x1bc> -80010508: 411585b3 sub a1,a1,a7 -8001050c: 0108d713 srli a4,a7,0x10 -80010510: 01089513 slli a0,a7,0x10 -80010514: 01055513 srli a0,a0,0x10 -80010518: 0107d613 srli a2,a5,0x10 -8001051c: 02e5f6b3 remu a3,a1,a4 -80010520: 02e5d5b3 divu a1,a1,a4 -80010524: 01069693 slli a3,a3,0x10 -80010528: 00c6e6b3 or a3,a3,a2 -8001052c: 02b505b3 mul a1,a0,a1 -80010530: 00b6fa63 bgeu a3,a1,80010544 <__umoddi3+0x16c> -80010534: 011686b3 add a3,a3,a7 -80010538: 0116e663 bltu a3,a7,80010544 <__umoddi3+0x16c> -8001053c: 00b6f463 bgeu a3,a1,80010544 <__umoddi3+0x16c> -80010540: 011686b3 add a3,a3,a7 -80010544: 40b685b3 sub a1,a3,a1 -80010548: 02e5f6b3 remu a3,a1,a4 -8001054c: 01079793 slli a5,a5,0x10 -80010550: 0107d793 srli a5,a5,0x10 -80010554: 02e5d5b3 divu a1,a1,a4 -80010558: 02b505b3 mul a1,a0,a1 -8001055c: 01069513 slli a0,a3,0x10 -80010560: 00f567b3 or a5,a0,a5 -80010564: 00b7fa63 bgeu a5,a1,80010578 <__umoddi3+0x1a0> -80010568: 011787b3 add a5,a5,a7 -8001056c: 0117e663 bltu a5,a7,80010578 <__umoddi3+0x1a0> -80010570: 00b7f463 bgeu a5,a1,80010578 <__umoddi3+0x1a0> -80010574: 011787b3 add a5,a5,a7 -80010578: 40b787b3 sub a5,a5,a1 -8001057c: f31ff06f j 800104ac <__umoddi3+0xd4> -80010580: 01000637 lui a2,0x1000 -80010584: 01000713 li a4,16 -80010588: f6c8e2e3 bltu a7,a2,800104ec <__umoddi3+0x114> -8001058c: 01800713 li a4,24 -80010590: f5dff06f j 800104ec <__umoddi3+0x114> -80010594: 006898b3 sll a7,a7,t1 -80010598: 01c5d733 srl a4,a1,t3 -8001059c: 006517b3 sll a5,a0,t1 -800105a0: 01c55e33 srl t3,a0,t3 -800105a4: 0108d513 srli a0,a7,0x10 -800105a8: 02a776b3 remu a3,a4,a0 -800105ac: 006595b3 sll a1,a1,t1 -800105b0: 00be6e33 or t3,t3,a1 -800105b4: 01089593 slli a1,a7,0x10 -800105b8: 0105d593 srli a1,a1,0x10 -800105bc: 010e5613 srli a2,t3,0x10 -800105c0: 02a75733 divu a4,a4,a0 -800105c4: 01069693 slli a3,a3,0x10 -800105c8: 00c6e6b3 or a3,a3,a2 -800105cc: 02e58733 mul a4,a1,a4 -800105d0: 00e6fa63 bgeu a3,a4,800105e4 <__umoddi3+0x20c> -800105d4: 011686b3 add a3,a3,a7 -800105d8: 0116e663 bltu a3,a7,800105e4 <__umoddi3+0x20c> -800105dc: 00e6f463 bgeu a3,a4,800105e4 <__umoddi3+0x20c> -800105e0: 011686b3 add a3,a3,a7 -800105e4: 40e68633 sub a2,a3,a4 -800105e8: 02a676b3 remu a3,a2,a0 -800105ec: 010e1e13 slli t3,t3,0x10 -800105f0: 010e5e13 srli t3,t3,0x10 -800105f4: 02a65633 divu a2,a2,a0 -800105f8: 01069693 slli a3,a3,0x10 -800105fc: 02c58633 mul a2,a1,a2 -80010600: 01c6e5b3 or a1,a3,t3 -80010604: 00c5fa63 bgeu a1,a2,80010618 <__umoddi3+0x240> -80010608: 011585b3 add a1,a1,a7 -8001060c: 0115e663 bltu a1,a7,80010618 <__umoddi3+0x240> -80010610: 00c5f463 bgeu a1,a2,80010618 <__umoddi3+0x240> -80010614: 011585b3 add a1,a1,a7 -80010618: 40c585b3 sub a1,a1,a2 -8001061c: ef1ff06f j 8001050c <__umoddi3+0x134> -80010620: e8d5eae3 bltu a1,a3,800104b4 <__umoddi3+0xdc> -80010624: 00010737 lui a4,0x10 -80010628: 04e6fc63 bgeu a3,a4,80010680 <__umoddi3+0x2a8> -8001062c: 0ff00e93 li t4,255 -80010630: 00deb733 sltu a4,t4,a3 -80010634: 00371713 slli a4,a4,0x3 -80010638: 80015337 lui t1,0x80015 -8001063c: 00e6d8b3 srl a7,a3,a4 -80010640: 22430313 addi t1,t1,548 # 80015224 <__BSS_END__+0xffffe4ac> -80010644: 006888b3 add a7,a7,t1 -80010648: 0008ce83 lbu t4,0(a7) # 1000000 <_start-0x7f000000> -8001064c: 02000e13 li t3,32 -80010650: 00ee8eb3 add t4,t4,a4 -80010654: 41de0e33 sub t3,t3,t4 -80010658: 020e1e63 bnez t3,80010694 <__umoddi3+0x2bc> -8001065c: 00b6e463 bltu a3,a1,80010664 <__umoddi3+0x28c> -80010660: 00c56a63 bltu a0,a2,80010674 <__umoddi3+0x29c> -80010664: 40c507b3 sub a5,a0,a2 -80010668: 40d585b3 sub a1,a1,a3 -8001066c: 00f53533 sltu a0,a0,a5 -80010670: 40a58833 sub a6,a1,a0 -80010674: 00078513 mv a0,a5 -80010678: 00080593 mv a1,a6 -8001067c: e39ff06f j 800104b4 <__umoddi3+0xdc> -80010680: 010008b7 lui a7,0x1000 -80010684: 01000713 li a4,16 -80010688: fb16e8e3 bltu a3,a7,80010638 <__umoddi3+0x260> -8001068c: 01800713 li a4,24 -80010690: fa9ff06f j 80010638 <__umoddi3+0x260> -80010694: 01d65733 srl a4,a2,t4 -80010698: 01c696b3 sll a3,a3,t3 -8001069c: 00d766b3 or a3,a4,a3 -800106a0: 0106d813 srli a6,a3,0x10 -800106a4: 01d5d733 srl a4,a1,t4 -800106a8: 03077333 remu t1,a4,a6 -800106ac: 01c595b3 sll a1,a1,t3 -800106b0: 01d557b3 srl a5,a0,t4 -800106b4: 00b7e7b3 or a5,a5,a1 -800106b8: 01069593 slli a1,a3,0x10 -800106bc: 0105d593 srli a1,a1,0x10 -800106c0: 0107d893 srli a7,a5,0x10 -800106c4: 01c61633 sll a2,a2,t3 -800106c8: 01c51533 sll a0,a0,t3 -800106cc: 03075733 divu a4,a4,a6 -800106d0: 01031313 slli t1,t1,0x10 -800106d4: 011368b3 or a7,t1,a7 -800106d8: 02e58f33 mul t5,a1,a4 -800106dc: 00070313 mv t1,a4 -800106e0: 01e8fe63 bgeu a7,t5,800106fc <__umoddi3+0x324> -800106e4: 00d888b3 add a7,a7,a3 -800106e8: fff70313 addi t1,a4,-1 # ffff <_start-0x7fff0001> -800106ec: 00d8e863 bltu a7,a3,800106fc <__umoddi3+0x324> -800106f0: 01e8f663 bgeu a7,t5,800106fc <__umoddi3+0x324> -800106f4: ffe70313 addi t1,a4,-2 -800106f8: 00d888b3 add a7,a7,a3 -800106fc: 41e888b3 sub a7,a7,t5 -80010700: 0308ff33 remu t5,a7,a6 -80010704: 0308d8b3 divu a7,a7,a6 -80010708: 010f1f13 slli t5,t5,0x10 -8001070c: 03158833 mul a6,a1,a7 -80010710: 01079593 slli a1,a5,0x10 -80010714: 0105d593 srli a1,a1,0x10 -80010718: 00bf65b3 or a1,t5,a1 -8001071c: 00088793 mv a5,a7 -80010720: 0105fe63 bgeu a1,a6,8001073c <__umoddi3+0x364> -80010724: 00d585b3 add a1,a1,a3 -80010728: fff88793 addi a5,a7,-1 # ffffff <_start-0x7f000001> -8001072c: 00d5e863 bltu a1,a3,8001073c <__umoddi3+0x364> -80010730: 0105f663 bgeu a1,a6,8001073c <__umoddi3+0x364> -80010734: ffe88793 addi a5,a7,-2 -80010738: 00d585b3 add a1,a1,a3 -8001073c: 01031313 slli t1,t1,0x10 -80010740: 00010f37 lui t5,0x10 -80010744: 00f36333 or t1,t1,a5 -80010748: ffff0793 addi a5,t5,-1 # ffff <_start-0x7fff0001> -8001074c: 00f378b3 and a7,t1,a5 -80010750: 410585b3 sub a1,a1,a6 -80010754: 01035313 srli t1,t1,0x10 -80010758: 01065813 srli a6,a2,0x10 -8001075c: 00f677b3 and a5,a2,a5 -80010760: 02f88733 mul a4,a7,a5 -80010764: 02f307b3 mul a5,t1,a5 -80010768: 030888b3 mul a7,a7,a6 -8001076c: 03030333 mul t1,t1,a6 -80010770: 00f888b3 add a7,a7,a5 -80010774: 01075813 srli a6,a4,0x10 -80010778: 01180833 add a6,a6,a7 -8001077c: 00f87463 bgeu a6,a5,80010784 <__umoddi3+0x3ac> -80010780: 01e30333 add t1,t1,t5 -80010784: 01085793 srli a5,a6,0x10 -80010788: 00678333 add t1,a5,t1 -8001078c: 000107b7 lui a5,0x10 -80010790: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -80010794: 00f87833 and a6,a6,a5 -80010798: 01081813 slli a6,a6,0x10 -8001079c: 00f77733 and a4,a4,a5 -800107a0: 00e80733 add a4,a6,a4 -800107a4: 0065e663 bltu a1,t1,800107b0 <__umoddi3+0x3d8> -800107a8: 00659e63 bne a1,t1,800107c4 <__umoddi3+0x3ec> -800107ac: 00e57c63 bgeu a0,a4,800107c4 <__umoddi3+0x3ec> -800107b0: 40c70633 sub a2,a4,a2 -800107b4: 00c73733 sltu a4,a4,a2 -800107b8: 00d70733 add a4,a4,a3 -800107bc: 40e30333 sub t1,t1,a4 -800107c0: 00060713 mv a4,a2 -800107c4: 40e50733 sub a4,a0,a4 -800107c8: 00e53533 sltu a0,a0,a4 -800107cc: 406585b3 sub a1,a1,t1 -800107d0: 40a585b3 sub a1,a1,a0 -800107d4: 01d597b3 sll a5,a1,t4 -800107d8: 01c75733 srl a4,a4,t3 -800107dc: 00e7e533 or a0,a5,a4 -800107e0: 01c5d5b3 srl a1,a1,t3 -800107e4: cd1ff06f j 800104b4 <__umoddi3+0xdc> - -800107e8 <__divdf3>: -800107e8: fd010113 addi sp,sp,-48 -800107ec: 0145d813 srli a6,a1,0x14 -800107f0: 02912223 sw s1,36(sp) -800107f4: 01312e23 sw s3,28(sp) -800107f8: 01412c23 sw s4,24(sp) -800107fc: 01612823 sw s6,16(sp) -80010800: 01712623 sw s7,12(sp) -80010804: 00c59493 slli s1,a1,0xc -80010808: 02112623 sw ra,44(sp) -8001080c: 02812423 sw s0,40(sp) -80010810: 03212023 sw s2,32(sp) -80010814: 01512a23 sw s5,20(sp) -80010818: 7ff87813 andi a6,a6,2047 -8001081c: 00050b13 mv s6,a0 -80010820: 00060b93 mv s7,a2 -80010824: 00068a13 mv s4,a3 -80010828: 00c4d493 srli s1,s1,0xc -8001082c: 01f5d993 srli s3,a1,0x1f -80010830: 0a080063 beqz a6,800108d0 <__divdf3+0xe8> -80010834: 7ff00793 li a5,2047 -80010838: 0ef80e63 beq a6,a5,80010934 <__divdf3+0x14c> -8001083c: 01d55a93 srli s5,a0,0x1d -80010840: 00349493 slli s1,s1,0x3 -80010844: 009ae4b3 or s1,s5,s1 -80010848: 00800ab7 lui s5,0x800 -8001084c: 0154eab3 or s5,s1,s5 -80010850: 00351413 slli s0,a0,0x3 -80010854: c0180913 addi s2,a6,-1023 -80010858: 00000b13 li s6,0 -8001085c: 014a5513 srli a0,s4,0x14 -80010860: 00ca1493 slli s1,s4,0xc -80010864: 7ff57813 andi a6,a0,2047 -80010868: 00c4d493 srli s1,s1,0xc -8001086c: 01fa5a13 srli s4,s4,0x1f -80010870: 10080063 beqz a6,80010970 <__divdf3+0x188> -80010874: 7ff00793 li a5,2047 -80010878: 16f80063 beq a6,a5,800109d8 <__divdf3+0x1f0> -8001087c: 00349513 slli a0,s1,0x3 -80010880: 01dbd793 srli a5,s7,0x1d -80010884: 00a7e533 or a0,a5,a0 -80010888: 008004b7 lui s1,0x800 -8001088c: 009564b3 or s1,a0,s1 -80010890: 003b9f13 slli t5,s7,0x3 -80010894: c0180513 addi a0,a6,-1023 -80010898: 00000793 li a5,0 -8001089c: 002b1713 slli a4,s6,0x2 -800108a0: 00f76733 or a4,a4,a5 -800108a4: fff70713 addi a4,a4,-1 -800108a8: 00e00693 li a3,14 -800108ac: 0149c633 xor a2,s3,s4 -800108b0: 40a90833 sub a6,s2,a0 -800108b4: 14e6ee63 bltu a3,a4,80010a10 <__divdf3+0x228> -800108b8: 800156b7 lui a3,0x80015 -800108bc: 00271713 slli a4,a4,0x2 -800108c0: 17068693 addi a3,a3,368 # 80015170 <__BSS_END__+0xffffe3f8> -800108c4: 00d70733 add a4,a4,a3 -800108c8: 00072703 lw a4,0(a4) -800108cc: 00070067 jr a4 -800108d0: 00a4eab3 or s5,s1,a0 -800108d4: 060a8e63 beqz s5,80010950 <__divdf3+0x168> -800108d8: 04048063 beqz s1,80010918 <__divdf3+0x130> -800108dc: 00048513 mv a0,s1 -800108e0: 41d030ef jal ra,800144fc <__clzsi2> -800108e4: ff550793 addi a5,a0,-11 -800108e8: 01c00713 li a4,28 -800108ec: 02f74c63 blt a4,a5,80010924 <__divdf3+0x13c> -800108f0: 01d00a93 li s5,29 -800108f4: ff850413 addi s0,a0,-8 -800108f8: 40fa8ab3 sub s5,s5,a5 -800108fc: 008494b3 sll s1,s1,s0 -80010900: 015b5ab3 srl s5,s6,s5 -80010904: 009aeab3 or s5,s5,s1 -80010908: 008b1433 sll s0,s6,s0 -8001090c: c0d00813 li a6,-1011 -80010910: 40a80933 sub s2,a6,a0 -80010914: f45ff06f j 80010858 <__divdf3+0x70> -80010918: 3e5030ef jal ra,800144fc <__clzsi2> -8001091c: 02050513 addi a0,a0,32 -80010920: fc5ff06f j 800108e4 <__divdf3+0xfc> -80010924: fd850493 addi s1,a0,-40 -80010928: 009b1ab3 sll s5,s6,s1 -8001092c: 00000413 li s0,0 -80010930: fddff06f j 8001090c <__divdf3+0x124> -80010934: 00a4eab3 or s5,s1,a0 -80010938: 020a8463 beqz s5,80010960 <__divdf3+0x178> -8001093c: 00050413 mv s0,a0 -80010940: 00048a93 mv s5,s1 -80010944: 7ff00913 li s2,2047 -80010948: 00300b13 li s6,3 -8001094c: f11ff06f j 8001085c <__divdf3+0x74> -80010950: 00000413 li s0,0 -80010954: 00000913 li s2,0 -80010958: 00100b13 li s6,1 -8001095c: f01ff06f j 8001085c <__divdf3+0x74> -80010960: 00000413 li s0,0 -80010964: 7ff00913 li s2,2047 -80010968: 00200b13 li s6,2 -8001096c: ef1ff06f j 8001085c <__divdf3+0x74> -80010970: 0174ef33 or t5,s1,s7 -80010974: 060f0e63 beqz t5,800109f0 <__divdf3+0x208> -80010978: 04048063 beqz s1,800109b8 <__divdf3+0x1d0> -8001097c: 00048513 mv a0,s1 -80010980: 37d030ef jal ra,800144fc <__clzsi2> -80010984: ff550793 addi a5,a0,-11 -80010988: 01c00713 li a4,28 -8001098c: 02f74e63 blt a4,a5,800109c8 <__divdf3+0x1e0> -80010990: 01d00713 li a4,29 -80010994: ff850f13 addi t5,a0,-8 -80010998: 40f70733 sub a4,a4,a5 -8001099c: 01e494b3 sll s1,s1,t5 -800109a0: 00ebd733 srl a4,s7,a4 -800109a4: 009764b3 or s1,a4,s1 -800109a8: 01eb9f33 sll t5,s7,t5 -800109ac: c0d00613 li a2,-1011 -800109b0: 40a60533 sub a0,a2,a0 -800109b4: ee5ff06f j 80010898 <__divdf3+0xb0> -800109b8: 000b8513 mv a0,s7 -800109bc: 341030ef jal ra,800144fc <__clzsi2> -800109c0: 02050513 addi a0,a0,32 -800109c4: fc1ff06f j 80010984 <__divdf3+0x19c> -800109c8: fd850493 addi s1,a0,-40 -800109cc: 009b94b3 sll s1,s7,s1 -800109d0: 00000f13 li t5,0 -800109d4: fd9ff06f j 800109ac <__divdf3+0x1c4> -800109d8: 0174ef33 or t5,s1,s7 -800109dc: 020f0263 beqz t5,80010a00 <__divdf3+0x218> -800109e0: 000b8f13 mv t5,s7 -800109e4: 7ff00513 li a0,2047 -800109e8: 00300793 li a5,3 -800109ec: eb1ff06f j 8001089c <__divdf3+0xb4> -800109f0: 00000493 li s1,0 -800109f4: 00000513 li a0,0 -800109f8: 00100793 li a5,1 -800109fc: ea1ff06f j 8001089c <__divdf3+0xb4> -80010a00: 00000493 li s1,0 -80010a04: 7ff00513 li a0,2047 -80010a08: 00200793 li a5,2 -80010a0c: e91ff06f j 8001089c <__divdf3+0xb4> -80010a10: 0154e663 bltu s1,s5,80010a1c <__divdf3+0x234> -80010a14: 349a9863 bne s5,s1,80010d64 <__divdf3+0x57c> -80010a18: 35e46663 bltu s0,t5,80010d64 <__divdf3+0x57c> -80010a1c: 01fa9693 slli a3,s5,0x1f -80010a20: 00145713 srli a4,s0,0x1 -80010a24: 01f41793 slli a5,s0,0x1f -80010a28: 001ada93 srli s5,s5,0x1 -80010a2c: 00e6e433 or s0,a3,a4 -80010a30: 00849513 slli a0,s1,0x8 -80010a34: 018f5493 srli s1,t5,0x18 -80010a38: 00a4e533 or a0,s1,a0 -80010a3c: 01055e13 srli t3,a0,0x10 -80010a40: 03cad8b3 divu a7,s5,t3 -80010a44: 01051313 slli t1,a0,0x10 -80010a48: 01035313 srli t1,t1,0x10 -80010a4c: 01045713 srli a4,s0,0x10 -80010a50: 008f1593 slli a1,t5,0x8 -80010a54: 03caf4b3 remu s1,s5,t3 -80010a58: 00088f93 mv t6,a7 -80010a5c: 031306b3 mul a3,t1,a7 -80010a60: 01049a93 slli s5,s1,0x10 -80010a64: 01576733 or a4,a4,s5 -80010a68: 00d77e63 bgeu a4,a3,80010a84 <__divdf3+0x29c> -80010a6c: 00a70733 add a4,a4,a0 -80010a70: fff88f93 addi t6,a7,-1 -80010a74: 00a76863 bltu a4,a0,80010a84 <__divdf3+0x29c> -80010a78: 00d77663 bgeu a4,a3,80010a84 <__divdf3+0x29c> -80010a7c: ffe88f93 addi t6,a7,-2 -80010a80: 00a70733 add a4,a4,a0 -80010a84: 40d70733 sub a4,a4,a3 -80010a88: 03c75eb3 divu t4,a4,t3 -80010a8c: 01041413 slli s0,s0,0x10 -80010a90: 01045413 srli s0,s0,0x10 -80010a94: 03c77733 remu a4,a4,t3 -80010a98: 000e8693 mv a3,t4 -80010a9c: 03d308b3 mul a7,t1,t4 -80010aa0: 01071713 slli a4,a4,0x10 -80010aa4: 00e46733 or a4,s0,a4 -80010aa8: 01177e63 bgeu a4,a7,80010ac4 <__divdf3+0x2dc> -80010aac: 00a70733 add a4,a4,a0 -80010ab0: fffe8693 addi a3,t4,-1 -80010ab4: 00a76863 bltu a4,a0,80010ac4 <__divdf3+0x2dc> -80010ab8: 01177663 bgeu a4,a7,80010ac4 <__divdf3+0x2dc> -80010abc: ffee8693 addi a3,t4,-2 -80010ac0: 00a70733 add a4,a4,a0 -80010ac4: 010f9f93 slli t6,t6,0x10 -80010ac8: 00dfefb3 or t6,t6,a3 -80010acc: 000106b7 lui a3,0x10 -80010ad0: 41170433 sub s0,a4,a7 -80010ad4: fff68893 addi a7,a3,-1 # ffff <_start-0x7fff0001> -80010ad8: 010fdf13 srli t5,t6,0x10 -80010adc: 011ff733 and a4,t6,a7 -80010ae0: 0105de93 srli t4,a1,0x10 -80010ae4: 0115f8b3 and a7,a1,a7 -80010ae8: 031703b3 mul t2,a4,a7 -80010aec: 031f04b3 mul s1,t5,a7 -80010af0: 02ee8733 mul a4,t4,a4 -80010af4: 03df02b3 mul t0,t5,t4 -80010af8: 00970f33 add t5,a4,s1 -80010afc: 0103d713 srli a4,t2,0x10 -80010b00: 01e70733 add a4,a4,t5 -80010b04: 00977463 bgeu a4,s1,80010b0c <__divdf3+0x324> -80010b08: 00d282b3 add t0,t0,a3 -80010b0c: 01075f13 srli t5,a4,0x10 -80010b10: 005f0f33 add t5,t5,t0 -80010b14: 000102b7 lui t0,0x10 -80010b18: fff28293 addi t0,t0,-1 # ffff <_start-0x7fff0001> -80010b1c: 005776b3 and a3,a4,t0 -80010b20: 01069693 slli a3,a3,0x10 -80010b24: 0053f3b3 and t2,t2,t0 -80010b28: 007686b3 add a3,a3,t2 -80010b2c: 01e46863 bltu s0,t5,80010b3c <__divdf3+0x354> -80010b30: 000f8493 mv s1,t6 -80010b34: 05e41463 bne s0,t5,80010b7c <__divdf3+0x394> -80010b38: 04d7f263 bgeu a5,a3,80010b7c <__divdf3+0x394> -80010b3c: 00b787b3 add a5,a5,a1 -80010b40: 00b7b733 sltu a4,a5,a1 -80010b44: 00a70733 add a4,a4,a0 -80010b48: 00e40433 add s0,s0,a4 -80010b4c: ffff8493 addi s1,t6,-1 -80010b50: 00856663 bltu a0,s0,80010b5c <__divdf3+0x374> -80010b54: 02851463 bne a0,s0,80010b7c <__divdf3+0x394> -80010b58: 02b7e263 bltu a5,a1,80010b7c <__divdf3+0x394> -80010b5c: 01e46663 bltu s0,t5,80010b68 <__divdf3+0x380> -80010b60: 008f1e63 bne t5,s0,80010b7c <__divdf3+0x394> -80010b64: 00d7fc63 bgeu a5,a3,80010b7c <__divdf3+0x394> -80010b68: 00b787b3 add a5,a5,a1 -80010b6c: 00b7b733 sltu a4,a5,a1 -80010b70: 00a70733 add a4,a4,a0 -80010b74: ffef8493 addi s1,t6,-2 -80010b78: 00e40433 add s0,s0,a4 -80010b7c: 40d786b3 sub a3,a5,a3 -80010b80: 41e40433 sub s0,s0,t5 -80010b84: 00d7b7b3 sltu a5,a5,a3 -80010b88: 40f40433 sub s0,s0,a5 -80010b8c: fff00f13 li t5,-1 -80010b90: 12850463 beq a0,s0,80010cb8 <__divdf3+0x4d0> -80010b94: 03c45f33 divu t5,s0,t3 -80010b98: 0106d713 srli a4,a3,0x10 -80010b9c: 03c47433 remu s0,s0,t3 -80010ba0: 03e307b3 mul a5,t1,t5 -80010ba4: 01041413 slli s0,s0,0x10 -80010ba8: 00876433 or s0,a4,s0 -80010bac: 000f0713 mv a4,t5 -80010bb0: 00f47e63 bgeu s0,a5,80010bcc <__divdf3+0x3e4> -80010bb4: 00a40433 add s0,s0,a0 -80010bb8: ffff0713 addi a4,t5,-1 -80010bbc: 00a46863 bltu s0,a0,80010bcc <__divdf3+0x3e4> -80010bc0: 00f47663 bgeu s0,a5,80010bcc <__divdf3+0x3e4> -80010bc4: ffef0713 addi a4,t5,-2 -80010bc8: 00a40433 add s0,s0,a0 -80010bcc: 40f40433 sub s0,s0,a5 -80010bd0: 03c45f33 divu t5,s0,t3 -80010bd4: 01069693 slli a3,a3,0x10 -80010bd8: 0106d693 srli a3,a3,0x10 -80010bdc: 03c47433 remu s0,s0,t3 -80010be0: 000f0793 mv a5,t5 -80010be4: 03e30333 mul t1,t1,t5 -80010be8: 01041413 slli s0,s0,0x10 -80010bec: 0086e433 or s0,a3,s0 -80010bf0: 00647e63 bgeu s0,t1,80010c0c <__divdf3+0x424> -80010bf4: 00a40433 add s0,s0,a0 -80010bf8: ffff0793 addi a5,t5,-1 -80010bfc: 00a46863 bltu s0,a0,80010c0c <__divdf3+0x424> -80010c00: 00647663 bgeu s0,t1,80010c0c <__divdf3+0x424> -80010c04: ffef0793 addi a5,t5,-2 -80010c08: 00a40433 add s0,s0,a0 -80010c0c: 01071713 slli a4,a4,0x10 -80010c10: 00f76733 or a4,a4,a5 -80010c14: 01071793 slli a5,a4,0x10 -80010c18: 0107d793 srli a5,a5,0x10 -80010c1c: 40640433 sub s0,s0,t1 -80010c20: 01075313 srli t1,a4,0x10 -80010c24: 03178e33 mul t3,a5,a7 -80010c28: 031308b3 mul a7,t1,a7 -80010c2c: 026e8333 mul t1,t4,t1 -80010c30: 02fe8eb3 mul t4,t4,a5 -80010c34: 010e5793 srli a5,t3,0x10 -80010c38: 011e8eb3 add t4,t4,a7 -80010c3c: 01d787b3 add a5,a5,t4 -80010c40: 0117f663 bgeu a5,a7,80010c4c <__divdf3+0x464> -80010c44: 000106b7 lui a3,0x10 -80010c48: 00d30333 add t1,t1,a3 -80010c4c: 0107d893 srli a7,a5,0x10 -80010c50: 006888b3 add a7,a7,t1 -80010c54: 00010337 lui t1,0x10 -80010c58: fff30313 addi t1,t1,-1 # ffff <_start-0x7fff0001> -80010c5c: 0067f6b3 and a3,a5,t1 -80010c60: 01069693 slli a3,a3,0x10 -80010c64: 006e7e33 and t3,t3,t1 -80010c68: 01c686b3 add a3,a3,t3 -80010c6c: 01146863 bltu s0,a7,80010c7c <__divdf3+0x494> -80010c70: 23141c63 bne s0,a7,80010ea8 <__divdf3+0x6c0> -80010c74: 00070f13 mv t5,a4 -80010c78: 04068063 beqz a3,80010cb8 <__divdf3+0x4d0> -80010c7c: 00850433 add s0,a0,s0 -80010c80: fff70f13 addi t5,a4,-1 -80010c84: 02a46463 bltu s0,a0,80010cac <__divdf3+0x4c4> -80010c88: 01146663 bltu s0,a7,80010c94 <__divdf3+0x4ac> -80010c8c: 21141c63 bne s0,a7,80010ea4 <__divdf3+0x6bc> -80010c90: 02d5f063 bgeu a1,a3,80010cb0 <__divdf3+0x4c8> -80010c94: 00159793 slli a5,a1,0x1 -80010c98: 00b7b5b3 sltu a1,a5,a1 -80010c9c: 00a58533 add a0,a1,a0 -80010ca0: ffe70f13 addi t5,a4,-2 -80010ca4: 00a40433 add s0,s0,a0 -80010ca8: 00078593 mv a1,a5 -80010cac: 01141463 bne s0,a7,80010cb4 <__divdf3+0x4cc> -80010cb0: 00b68463 beq a3,a1,80010cb8 <__divdf3+0x4d0> -80010cb4: 001f6f13 ori t5,t5,1 -80010cb8: 3ff80713 addi a4,a6,1023 -80010cbc: 10e05263 blez a4,80010dc0 <__divdf3+0x5d8> -80010cc0: 007f7793 andi a5,t5,7 -80010cc4: 02078063 beqz a5,80010ce4 <__divdf3+0x4fc> -80010cc8: 00ff7793 andi a5,t5,15 -80010ccc: 00400693 li a3,4 -80010cd0: 00d78a63 beq a5,a3,80010ce4 <__divdf3+0x4fc> -80010cd4: 004f0693 addi a3,t5,4 -80010cd8: 01e6bf33 sltu t5,a3,t5 -80010cdc: 01e484b3 add s1,s1,t5 -80010ce0: 00068f13 mv t5,a3 -80010ce4: 00749793 slli a5,s1,0x7 -80010ce8: 0007da63 bgez a5,80010cfc <__divdf3+0x514> -80010cec: ff0007b7 lui a5,0xff000 -80010cf0: fff78793 addi a5,a5,-1 # feffffff <__BSS_END__+0x7efe9287> -80010cf4: 00f4f4b3 and s1,s1,a5 -80010cf8: 40080713 addi a4,a6,1024 -80010cfc: 7fe00793 li a5,2046 -80010d00: 18e7c263 blt a5,a4,80010e84 <__divdf3+0x69c> -80010d04: 003f5f13 srli t5,t5,0x3 -80010d08: 01d49793 slli a5,s1,0x1d -80010d0c: 01e7e7b3 or a5,a5,t5 -80010d10: 0034d513 srli a0,s1,0x3 -80010d14: 00c51513 slli a0,a0,0xc -80010d18: 7ff77713 andi a4,a4,2047 -80010d1c: 01471713 slli a4,a4,0x14 -80010d20: 02c12083 lw ra,44(sp) -80010d24: 02812403 lw s0,40(sp) -80010d28: 00c55513 srli a0,a0,0xc -80010d2c: 00e56533 or a0,a0,a4 -80010d30: 01f61613 slli a2,a2,0x1f -80010d34: 00c56733 or a4,a0,a2 -80010d38: 02412483 lw s1,36(sp) -80010d3c: 02012903 lw s2,32(sp) -80010d40: 01c12983 lw s3,28(sp) -80010d44: 01812a03 lw s4,24(sp) -80010d48: 01412a83 lw s5,20(sp) -80010d4c: 01012b03 lw s6,16(sp) -80010d50: 00c12b83 lw s7,12(sp) -80010d54: 00078513 mv a0,a5 -80010d58: 00070593 mv a1,a4 -80010d5c: 03010113 addi sp,sp,48 -80010d60: 00008067 ret -80010d64: fff80813 addi a6,a6,-1 -80010d68: 00000793 li a5,0 -80010d6c: cc5ff06f j 80010a30 <__divdf3+0x248> -80010d70: 00098613 mv a2,s3 -80010d74: 000a8493 mv s1,s5 -80010d78: 00040f13 mv t5,s0 -80010d7c: 000b0793 mv a5,s6 -80010d80: 00200713 li a4,2 -80010d84: 10e78063 beq a5,a4,80010e84 <__divdf3+0x69c> -80010d88: 00300713 li a4,3 -80010d8c: 0ee78263 beq a5,a4,80010e70 <__divdf3+0x688> -80010d90: 00100713 li a4,1 -80010d94: f2e792e3 bne a5,a4,80010cb8 <__divdf3+0x4d0> -80010d98: 00000513 li a0,0 -80010d9c: 00000793 li a5,0 -80010da0: 0940006f j 80010e34 <__divdf3+0x64c> -80010da4: 000a0613 mv a2,s4 -80010da8: fd9ff06f j 80010d80 <__divdf3+0x598> -80010dac: 000804b7 lui s1,0x80 -80010db0: 00000f13 li t5,0 -80010db4: 00000613 li a2,0 -80010db8: 00300793 li a5,3 -80010dbc: fc5ff06f j 80010d80 <__divdf3+0x598> -80010dc0: 00100513 li a0,1 -80010dc4: 40e50533 sub a0,a0,a4 -80010dc8: 03800793 li a5,56 -80010dcc: fca7c6e3 blt a5,a0,80010d98 <__divdf3+0x5b0> -80010dd0: 01f00793 li a5,31 -80010dd4: 06a7c463 blt a5,a0,80010e3c <__divdf3+0x654> -80010dd8: 41e80813 addi a6,a6,1054 -80010ddc: 010497b3 sll a5,s1,a6 -80010de0: 00af5733 srl a4,t5,a0 -80010de4: 010f1833 sll a6,t5,a6 -80010de8: 00e7e7b3 or a5,a5,a4 -80010dec: 01003833 snez a6,a6 -80010df0: 0107e7b3 or a5,a5,a6 -80010df4: 00a4d533 srl a0,s1,a0 -80010df8: 0077f713 andi a4,a5,7 -80010dfc: 02070063 beqz a4,80010e1c <__divdf3+0x634> -80010e00: 00f7f713 andi a4,a5,15 -80010e04: 00400693 li a3,4 -80010e08: 00d70a63 beq a4,a3,80010e1c <__divdf3+0x634> -80010e0c: 00478713 addi a4,a5,4 -80010e10: 00f737b3 sltu a5,a4,a5 -80010e14: 00f50533 add a0,a0,a5 -80010e18: 00070793 mv a5,a4 -80010e1c: 00851713 slli a4,a0,0x8 -80010e20: 06074a63 bltz a4,80010e94 <__divdf3+0x6ac> -80010e24: 01d51713 slli a4,a0,0x1d -80010e28: 0037d793 srli a5,a5,0x3 -80010e2c: 00f767b3 or a5,a4,a5 -80010e30: 00355513 srli a0,a0,0x3 -80010e34: 00000713 li a4,0 -80010e38: eddff06f j 80010d14 <__divdf3+0x52c> -80010e3c: fe100793 li a5,-31 -80010e40: 40e787b3 sub a5,a5,a4 -80010e44: 02000693 li a3,32 -80010e48: 00f4d7b3 srl a5,s1,a5 -80010e4c: 00000713 li a4,0 -80010e50: 00d50663 beq a0,a3,80010e5c <__divdf3+0x674> -80010e54: 43e80813 addi a6,a6,1086 -80010e58: 01049733 sll a4,s1,a6 -80010e5c: 01e76f33 or t5,a4,t5 -80010e60: 01e03f33 snez t5,t5 -80010e64: 01e7e7b3 or a5,a5,t5 -80010e68: 00000513 li a0,0 -80010e6c: f8dff06f j 80010df8 <__divdf3+0x610> -80010e70: 00080537 lui a0,0x80 -80010e74: 00000793 li a5,0 -80010e78: 7ff00713 li a4,2047 -80010e7c: 00000613 li a2,0 -80010e80: e95ff06f j 80010d14 <__divdf3+0x52c> -80010e84: 00000513 li a0,0 -80010e88: 00000793 li a5,0 -80010e8c: 7ff00713 li a4,2047 -80010e90: e85ff06f j 80010d14 <__divdf3+0x52c> -80010e94: 00000513 li a0,0 -80010e98: 00000793 li a5,0 -80010e9c: 00100713 li a4,1 -80010ea0: e75ff06f j 80010d14 <__divdf3+0x52c> -80010ea4: 000f0713 mv a4,t5 -80010ea8: 00070f13 mv t5,a4 -80010eac: e09ff06f j 80010cb4 <__divdf3+0x4cc> - -80010eb0 <__muldf3>: -80010eb0: fd010113 addi sp,sp,-48 -80010eb4: 01312e23 sw s3,28(sp) -80010eb8: 0145d993 srli s3,a1,0x14 -80010ebc: 02812423 sw s0,40(sp) -80010ec0: 02912223 sw s1,36(sp) -80010ec4: 01412c23 sw s4,24(sp) -80010ec8: 01512a23 sw s5,20(sp) -80010ecc: 01612823 sw s6,16(sp) -80010ed0: 00c59493 slli s1,a1,0xc -80010ed4: 02112623 sw ra,44(sp) -80010ed8: 03212023 sw s2,32(sp) -80010edc: 01712623 sw s7,12(sp) -80010ee0: 7ff9f993 andi s3,s3,2047 -80010ee4: 00050413 mv s0,a0 -80010ee8: 00060b13 mv s6,a2 -80010eec: 00068a93 mv s5,a3 -80010ef0: 00c4d493 srli s1,s1,0xc -80010ef4: 01f5da13 srli s4,a1,0x1f -80010ef8: 0a098263 beqz s3,80010f9c <__muldf3+0xec> -80010efc: 7ff00793 li a5,2047 -80010f00: 10f98063 beq s3,a5,80011000 <__muldf3+0x150> -80010f04: 01d55793 srli a5,a0,0x1d -80010f08: 00349493 slli s1,s1,0x3 -80010f0c: 0097e4b3 or s1,a5,s1 -80010f10: 008007b7 lui a5,0x800 -80010f14: 00f4e4b3 or s1,s1,a5 -80010f18: 00351913 slli s2,a0,0x3 -80010f1c: c0198993 addi s3,s3,-1023 -80010f20: 00000b93 li s7,0 -80010f24: 014ad513 srli a0,s5,0x14 -80010f28: 00ca9413 slli s0,s5,0xc -80010f2c: 7ff57513 andi a0,a0,2047 -80010f30: 00c45413 srli s0,s0,0xc -80010f34: 01fada93 srli s5,s5,0x1f -80010f38: 10050063 beqz a0,80011038 <__muldf3+0x188> -80010f3c: 7ff00793 li a5,2047 -80010f40: 16f50063 beq a0,a5,800110a0 <__muldf3+0x1f0> -80010f44: 01db5793 srli a5,s6,0x1d -80010f48: 00341413 slli s0,s0,0x3 -80010f4c: 0087e433 or s0,a5,s0 -80010f50: 008007b7 lui a5,0x800 -80010f54: 00f46433 or s0,s0,a5 -80010f58: c0150513 addi a0,a0,-1023 # 7fc01 <_start-0x7ff803ff> -80010f5c: 003b1793 slli a5,s6,0x3 -80010f60: 00000713 li a4,0 -80010f64: 002b9693 slli a3,s7,0x2 -80010f68: 00e6e6b3 or a3,a3,a4 -80010f6c: 00a98533 add a0,s3,a0 -80010f70: fff68693 addi a3,a3,-1 # ffff <_start-0x7fff0001> -80010f74: 00e00593 li a1,14 -80010f78: 015a4633 xor a2,s4,s5 -80010f7c: 00150813 addi a6,a0,1 -80010f80: 14d5ec63 bltu a1,a3,800110d8 <__muldf3+0x228> -80010f84: 800155b7 lui a1,0x80015 -80010f88: 00269693 slli a3,a3,0x2 -80010f8c: 1ac58593 addi a1,a1,428 # 800151ac <__BSS_END__+0xffffe434> -80010f90: 00b686b3 add a3,a3,a1 -80010f94: 0006a683 lw a3,0(a3) -80010f98: 00068067 jr a3 -80010f9c: 00a4e933 or s2,s1,a0 -80010fa0: 06090c63 beqz s2,80011018 <__muldf3+0x168> -80010fa4: 04048063 beqz s1,80010fe4 <__muldf3+0x134> -80010fa8: 00048513 mv a0,s1 -80010fac: 550030ef jal ra,800144fc <__clzsi2> -80010fb0: ff550713 addi a4,a0,-11 -80010fb4: 01c00793 li a5,28 -80010fb8: 02e7cc63 blt a5,a4,80010ff0 <__muldf3+0x140> -80010fbc: 01d00793 li a5,29 -80010fc0: ff850913 addi s2,a0,-8 -80010fc4: 40e787b3 sub a5,a5,a4 -80010fc8: 012494b3 sll s1,s1,s2 -80010fcc: 00f457b3 srl a5,s0,a5 -80010fd0: 0097e4b3 or s1,a5,s1 -80010fd4: 01241933 sll s2,s0,s2 -80010fd8: c0d00993 li s3,-1011 -80010fdc: 40a989b3 sub s3,s3,a0 -80010fe0: f41ff06f j 80010f20 <__muldf3+0x70> -80010fe4: 518030ef jal ra,800144fc <__clzsi2> -80010fe8: 02050513 addi a0,a0,32 -80010fec: fc5ff06f j 80010fb0 <__muldf3+0x100> -80010ff0: fd850493 addi s1,a0,-40 -80010ff4: 009414b3 sll s1,s0,s1 -80010ff8: 00000913 li s2,0 -80010ffc: fddff06f j 80010fd8 <__muldf3+0x128> -80011000: 00a4e933 or s2,s1,a0 -80011004: 02090263 beqz s2,80011028 <__muldf3+0x178> -80011008: 00050913 mv s2,a0 -8001100c: 7ff00993 li s3,2047 -80011010: 00300b93 li s7,3 -80011014: f11ff06f j 80010f24 <__muldf3+0x74> -80011018: 00000493 li s1,0 -8001101c: 00000993 li s3,0 -80011020: 00100b93 li s7,1 -80011024: f01ff06f j 80010f24 <__muldf3+0x74> -80011028: 00000493 li s1,0 -8001102c: 7ff00993 li s3,2047 -80011030: 00200b93 li s7,2 -80011034: ef1ff06f j 80010f24 <__muldf3+0x74> -80011038: 016467b3 or a5,s0,s6 -8001103c: 06078e63 beqz a5,800110b8 <__muldf3+0x208> -80011040: 04040063 beqz s0,80011080 <__muldf3+0x1d0> -80011044: 00040513 mv a0,s0 -80011048: 4b4030ef jal ra,800144fc <__clzsi2> -8001104c: ff550693 addi a3,a0,-11 -80011050: 01c00793 li a5,28 -80011054: 02d7ce63 blt a5,a3,80011090 <__muldf3+0x1e0> -80011058: 01d00713 li a4,29 -8001105c: ff850793 addi a5,a0,-8 -80011060: 40d70733 sub a4,a4,a3 -80011064: 00f41433 sll s0,s0,a5 -80011068: 00eb5733 srl a4,s6,a4 -8001106c: 00876433 or s0,a4,s0 -80011070: 00fb17b3 sll a5,s6,a5 -80011074: c0d00713 li a4,-1011 -80011078: 40a70533 sub a0,a4,a0 -8001107c: ee5ff06f j 80010f60 <__muldf3+0xb0> -80011080: 000b0513 mv a0,s6 -80011084: 478030ef jal ra,800144fc <__clzsi2> -80011088: 02050513 addi a0,a0,32 -8001108c: fc1ff06f j 8001104c <__muldf3+0x19c> -80011090: fd850413 addi s0,a0,-40 -80011094: 008b1433 sll s0,s6,s0 -80011098: 00000793 li a5,0 -8001109c: fd9ff06f j 80011074 <__muldf3+0x1c4> -800110a0: 016467b3 or a5,s0,s6 -800110a4: 02078263 beqz a5,800110c8 <__muldf3+0x218> -800110a8: 000b0793 mv a5,s6 -800110ac: 7ff00513 li a0,2047 -800110b0: 00300713 li a4,3 -800110b4: eb1ff06f j 80010f64 <__muldf3+0xb4> -800110b8: 00000413 li s0,0 -800110bc: 00000513 li a0,0 -800110c0: 00100713 li a4,1 -800110c4: ea1ff06f j 80010f64 <__muldf3+0xb4> -800110c8: 00000413 li s0,0 -800110cc: 7ff00513 li a0,2047 -800110d0: 00200713 li a4,2 -800110d4: e91ff06f j 80010f64 <__muldf3+0xb4> -800110d8: 00010f37 lui t5,0x10 -800110dc: ffff0e93 addi t4,t5,-1 # ffff <_start-0x7fff0001> -800110e0: 01095713 srli a4,s2,0x10 -800110e4: 0107d893 srli a7,a5,0x10 -800110e8: 01d97933 and s2,s2,t4 -800110ec: 01d7f7b3 and a5,a5,t4 -800110f0: 032885b3 mul a1,a7,s2 -800110f4: 032786b3 mul a3,a5,s2 -800110f8: 02f70fb3 mul t6,a4,a5 -800110fc: 01f58333 add t1,a1,t6 -80011100: 0106d593 srli a1,a3,0x10 -80011104: 006585b3 add a1,a1,t1 -80011108: 03170e33 mul t3,a4,a7 -8001110c: 01f5f463 bgeu a1,t6,80011114 <__muldf3+0x264> -80011110: 01ee0e33 add t3,t3,t5 -80011114: 0105d393 srli t2,a1,0x10 -80011118: 01d5f5b3 and a1,a1,t4 -8001111c: 01d6f6b3 and a3,a3,t4 -80011120: 01045f13 srli t5,s0,0x10 -80011124: 01d472b3 and t0,s0,t4 -80011128: 01059593 slli a1,a1,0x10 -8001112c: 00d585b3 add a1,a1,a3 -80011130: 02570eb3 mul t4,a4,t0 -80011134: 032286b3 mul a3,t0,s2 -80011138: 032f0933 mul s2,t5,s2 -8001113c: 01d90333 add t1,s2,t4 -80011140: 0106d913 srli s2,a3,0x10 -80011144: 00690933 add s2,s2,t1 -80011148: 03e70733 mul a4,a4,t5 -8001114c: 01d97663 bgeu s2,t4,80011158 <__muldf3+0x2a8> -80011150: 00010337 lui t1,0x10 -80011154: 00670733 add a4,a4,t1 -80011158: 01095e93 srli t4,s2,0x10 -8001115c: 000109b7 lui s3,0x10 -80011160: 00ee8eb3 add t4,t4,a4 -80011164: fff98713 addi a4,s3,-1 # ffff <_start-0x7fff0001> -80011168: 00e97933 and s2,s2,a4 -8001116c: 00e6f6b3 and a3,a3,a4 -80011170: 0104d413 srli s0,s1,0x10 -80011174: 01091913 slli s2,s2,0x10 -80011178: 00e4f4b3 and s1,s1,a4 -8001117c: 00d90933 add s2,s2,a3 -80011180: 02978733 mul a4,a5,s1 -80011184: 012383b3 add t2,t2,s2 -80011188: 02f40333 mul t1,s0,a5 -8001118c: 029886b3 mul a3,a7,s1 -80011190: 028887b3 mul a5,a7,s0 -80011194: 006688b3 add a7,a3,t1 -80011198: 01075693 srli a3,a4,0x10 -8001119c: 011686b3 add a3,a3,a7 -800111a0: 0066f463 bgeu a3,t1,800111a8 <__muldf3+0x2f8> -800111a4: 013787b3 add a5,a5,s3 -800111a8: 0106d893 srli a7,a3,0x10 -800111ac: 000109b7 lui s3,0x10 -800111b0: 00f88fb3 add t6,a7,a5 -800111b4: fff98793 addi a5,s3,-1 # ffff <_start-0x7fff0001> -800111b8: 00f6f6b3 and a3,a3,a5 -800111bc: 00f77733 and a4,a4,a5 -800111c0: 029288b3 mul a7,t0,s1 -800111c4: 01069693 slli a3,a3,0x10 -800111c8: 00e686b3 add a3,a3,a4 -800111cc: 025407b3 mul a5,s0,t0 -800111d0: 029f04b3 mul s1,t5,s1 -800111d4: 028f0333 mul t1,t5,s0 -800111d8: 00f484b3 add s1,s1,a5 -800111dc: 0108d413 srli s0,a7,0x10 -800111e0: 009404b3 add s1,s0,s1 -800111e4: 00f4f463 bgeu s1,a5,800111ec <__muldf3+0x33c> -800111e8: 01330333 add t1,t1,s3 -800111ec: 000107b7 lui a5,0x10 -800111f0: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -800111f4: 00f4f733 and a4,s1,a5 -800111f8: 00f8f8b3 and a7,a7,a5 -800111fc: 01071713 slli a4,a4,0x10 -80011200: 007e0e33 add t3,t3,t2 -80011204: 01170733 add a4,a4,a7 -80011208: 012e3933 sltu s2,t3,s2 -8001120c: 01d70733 add a4,a4,t4 -80011210: 01270433 add s0,a4,s2 -80011214: 00de0e33 add t3,t3,a3 -80011218: 00de36b3 sltu a3,t3,a3 -8001121c: 01f408b3 add a7,s0,t6 -80011220: 00d88f33 add t5,a7,a3 -80011224: 01d73733 sltu a4,a4,t4 -80011228: 01243433 sltu s0,s0,s2 -8001122c: 00876433 or s0,a4,s0 -80011230: 0104d493 srli s1,s1,0x10 -80011234: 01f8b8b3 sltu a7,a7,t6 -80011238: 00df36b3 sltu a3,t5,a3 -8001123c: 00940433 add s0,s0,s1 -80011240: 00d8e6b3 or a3,a7,a3 -80011244: 00d40433 add s0,s0,a3 -80011248: 00640433 add s0,s0,t1 -8001124c: 017f5793 srli a5,t5,0x17 -80011250: 00941413 slli s0,s0,0x9 -80011254: 00f46433 or s0,s0,a5 -80011258: 009e1793 slli a5,t3,0x9 -8001125c: 00b7e7b3 or a5,a5,a1 -80011260: 00f037b3 snez a5,a5 -80011264: 017e5e13 srli t3,t3,0x17 -80011268: 009f1713 slli a4,t5,0x9 -8001126c: 01c7e7b3 or a5,a5,t3 -80011270: 00e7e7b3 or a5,a5,a4 -80011274: 00741713 slli a4,s0,0x7 -80011278: 10075263 bgez a4,8001137c <__muldf3+0x4cc> -8001127c: 0017d713 srli a4,a5,0x1 -80011280: 0017f793 andi a5,a5,1 -80011284: 00f767b3 or a5,a4,a5 -80011288: 01f41713 slli a4,s0,0x1f -8001128c: 00e7e7b3 or a5,a5,a4 -80011290: 00145413 srli s0,s0,0x1 -80011294: 3ff80693 addi a3,a6,1023 -80011298: 0ed05663 blez a3,80011384 <__muldf3+0x4d4> -8001129c: 0077f713 andi a4,a5,7 -800112a0: 02070063 beqz a4,800112c0 <__muldf3+0x410> -800112a4: 00f7f713 andi a4,a5,15 -800112a8: 00400593 li a1,4 -800112ac: 00b70a63 beq a4,a1,800112c0 <__muldf3+0x410> -800112b0: 00478713 addi a4,a5,4 -800112b4: 00f737b3 sltu a5,a4,a5 -800112b8: 00f40433 add s0,s0,a5 -800112bc: 00070793 mv a5,a4 -800112c0: 00741713 slli a4,s0,0x7 -800112c4: 00075a63 bgez a4,800112d8 <__muldf3+0x428> -800112c8: ff000737 lui a4,0xff000 -800112cc: fff70713 addi a4,a4,-1 # feffffff <__BSS_END__+0x7efe9287> -800112d0: 00e47433 and s0,s0,a4 -800112d4: 40080693 addi a3,a6,1024 -800112d8: 7fe00713 li a4,2046 -800112dc: 16d74663 blt a4,a3,80011448 <__muldf3+0x598> -800112e0: 0037d713 srli a4,a5,0x3 -800112e4: 01d41793 slli a5,s0,0x1d -800112e8: 00e7e7b3 or a5,a5,a4 -800112ec: 00345413 srli s0,s0,0x3 -800112f0: 00c41413 slli s0,s0,0xc -800112f4: 7ff6f713 andi a4,a3,2047 -800112f8: 01471713 slli a4,a4,0x14 -800112fc: 00c45413 srli s0,s0,0xc -80011300: 00e46433 or s0,s0,a4 -80011304: 01f61613 slli a2,a2,0x1f -80011308: 00c46733 or a4,s0,a2 -8001130c: 02c12083 lw ra,44(sp) -80011310: 02812403 lw s0,40(sp) -80011314: 02412483 lw s1,36(sp) -80011318: 02012903 lw s2,32(sp) -8001131c: 01c12983 lw s3,28(sp) -80011320: 01812a03 lw s4,24(sp) -80011324: 01412a83 lw s5,20(sp) -80011328: 01012b03 lw s6,16(sp) -8001132c: 00c12b83 lw s7,12(sp) -80011330: 00078513 mv a0,a5 -80011334: 00070593 mv a1,a4 -80011338: 03010113 addi sp,sp,48 -8001133c: 00008067 ret -80011340: 000a0613 mv a2,s4 -80011344: 00048413 mv s0,s1 -80011348: 00090793 mv a5,s2 -8001134c: 000b8713 mv a4,s7 -80011350: 00200693 li a3,2 -80011354: 0ed70a63 beq a4,a3,80011448 <__muldf3+0x598> -80011358: 00300693 li a3,3 -8001135c: 0cd70c63 beq a4,a3,80011434 <__muldf3+0x584> -80011360: 00100693 li a3,1 -80011364: f2d718e3 bne a4,a3,80011294 <__muldf3+0x3e4> -80011368: 00000413 li s0,0 -8001136c: 00000793 li a5,0 -80011370: 0880006f j 800113f8 <__muldf3+0x548> -80011374: 000a8613 mv a2,s5 -80011378: fd9ff06f j 80011350 <__muldf3+0x4a0> -8001137c: 00050813 mv a6,a0 -80011380: f15ff06f j 80011294 <__muldf3+0x3e4> -80011384: 00100593 li a1,1 -80011388: 40d585b3 sub a1,a1,a3 -8001138c: 03800713 li a4,56 -80011390: fcb74ce3 blt a4,a1,80011368 <__muldf3+0x4b8> -80011394: 01f00713 li a4,31 -80011398: 06b74463 blt a4,a1,80011400 <__muldf3+0x550> -8001139c: 41e80813 addi a6,a6,1054 -800113a0: 01041733 sll a4,s0,a6 -800113a4: 00b7d6b3 srl a3,a5,a1 -800113a8: 010797b3 sll a5,a5,a6 -800113ac: 00d76733 or a4,a4,a3 -800113b0: 00f037b3 snez a5,a5 -800113b4: 00f767b3 or a5,a4,a5 -800113b8: 00b45433 srl s0,s0,a1 -800113bc: 0077f713 andi a4,a5,7 -800113c0: 02070063 beqz a4,800113e0 <__muldf3+0x530> -800113c4: 00f7f713 andi a4,a5,15 -800113c8: 00400693 li a3,4 -800113cc: 00d70a63 beq a4,a3,800113e0 <__muldf3+0x530> -800113d0: 00478713 addi a4,a5,4 -800113d4: 00f737b3 sltu a5,a4,a5 -800113d8: 00f40433 add s0,s0,a5 -800113dc: 00070793 mv a5,a4 -800113e0: 00841713 slli a4,s0,0x8 -800113e4: 06074a63 bltz a4,80011458 <__muldf3+0x5a8> -800113e8: 01d41713 slli a4,s0,0x1d -800113ec: 0037d793 srli a5,a5,0x3 -800113f0: 00f767b3 or a5,a4,a5 -800113f4: 00345413 srli s0,s0,0x3 -800113f8: 00000693 li a3,0 -800113fc: ef5ff06f j 800112f0 <__muldf3+0x440> -80011400: fe100713 li a4,-31 -80011404: 40d70733 sub a4,a4,a3 -80011408: 02000513 li a0,32 -8001140c: 00e45733 srl a4,s0,a4 -80011410: 00000693 li a3,0 -80011414: 00a58663 beq a1,a0,80011420 <__muldf3+0x570> -80011418: 43e80813 addi a6,a6,1086 -8001141c: 010416b3 sll a3,s0,a6 -80011420: 00f6e7b3 or a5,a3,a5 -80011424: 00f037b3 snez a5,a5 -80011428: 00f767b3 or a5,a4,a5 -8001142c: 00000413 li s0,0 -80011430: f8dff06f j 800113bc <__muldf3+0x50c> -80011434: 00080437 lui s0,0x80 -80011438: 00000793 li a5,0 -8001143c: 7ff00693 li a3,2047 -80011440: 00000613 li a2,0 -80011444: eadff06f j 800112f0 <__muldf3+0x440> -80011448: 00000413 li s0,0 -8001144c: 00000793 li a5,0 -80011450: 7ff00693 li a3,2047 -80011454: e9dff06f j 800112f0 <__muldf3+0x440> -80011458: 00000413 li s0,0 -8001145c: 00000793 li a5,0 -80011460: 00100693 li a3,1 -80011464: e8dff06f j 800112f0 <__muldf3+0x440> - -80011468 <__eqtf2>: -80011468: 00c52783 lw a5,12(a0) -8001146c: 0005af03 lw t5,0(a1) -80011470: 0045af83 lw t6,4(a1) -80011474: 0085a283 lw t0,8(a1) -80011478: 00c5a583 lw a1,12(a1) -8001147c: 00008737 lui a4,0x8 -80011480: 0107d693 srli a3,a5,0x10 -80011484: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80011488: 01079813 slli a6,a5,0x10 -8001148c: 01059e93 slli t4,a1,0x10 -80011490: 01f7d613 srli a2,a5,0x1f -80011494: 00e6f6b3 and a3,a3,a4 -80011498: 0105d793 srli a5,a1,0x10 -8001149c: ff010113 addi sp,sp,-16 -800114a0: 00052883 lw a7,0(a0) -800114a4: 00452303 lw t1,4(a0) -800114a8: 00852e03 lw t3,8(a0) -800114ac: 01085813 srli a6,a6,0x10 -800114b0: 010ede93 srli t4,t4,0x10 -800114b4: 00e7f7b3 and a5,a5,a4 -800114b8: 01f5d593 srli a1,a1,0x1f -800114bc: 02e69063 bne a3,a4,800114dc <__eqtf2+0x74> -800114c0: 0068e733 or a4,a7,t1 -800114c4: 01c76733 or a4,a4,t3 -800114c8: 01076733 or a4,a4,a6 -800114cc: 00100513 li a0,1 -800114d0: 04071a63 bnez a4,80011524 <__eqtf2+0xbc> -800114d4: 04d79863 bne a5,a3,80011524 <__eqtf2+0xbc> -800114d8: 0080006f j 800114e0 <__eqtf2+0x78> -800114dc: 00e79c63 bne a5,a4,800114f4 <__eqtf2+0x8c> -800114e0: 01ff6733 or a4,t5,t6 -800114e4: 00576733 or a4,a4,t0 -800114e8: 01d76733 or a4,a4,t4 -800114ec: 00100513 li a0,1 -800114f0: 02071a63 bnez a4,80011524 <__eqtf2+0xbc> -800114f4: 00100513 li a0,1 -800114f8: 02d79663 bne a5,a3,80011524 <__eqtf2+0xbc> -800114fc: 03e89463 bne a7,t5,80011524 <__eqtf2+0xbc> -80011500: 03f31263 bne t1,t6,80011524 <__eqtf2+0xbc> -80011504: 025e1063 bne t3,t0,80011524 <__eqtf2+0xbc> -80011508: 01d81e63 bne a6,t4,80011524 <__eqtf2+0xbc> -8001150c: 02b60063 beq a2,a1,8001152c <__eqtf2+0xc4> -80011510: 00079a63 bnez a5,80011524 <__eqtf2+0xbc> -80011514: 0068e533 or a0,a7,t1 -80011518: 01c56533 or a0,a0,t3 -8001151c: 01056533 or a0,a0,a6 -80011520: 00a03533 snez a0,a0 -80011524: 01010113 addi sp,sp,16 -80011528: 00008067 ret -8001152c: 00000513 li a0,0 -80011530: ff5ff06f j 80011524 <__eqtf2+0xbc> - -80011534 <__getf2>: -80011534: 00052f83 lw t6,0(a0) -80011538: 00452803 lw a6,4(a0) -8001153c: 00852e03 lw t3,8(a0) -80011540: 00c52503 lw a0,12(a0) -80011544: 00c5a603 lw a2,12(a1) -80011548: 000087b7 lui a5,0x8 -8001154c: 01055693 srli a3,a0,0x10 -80011550: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80011554: 01061313 slli t1,a2,0x10 -80011558: 01065713 srli a4,a2,0x10 -8001155c: 0005a283 lw t0,0(a1) -80011560: 0045a883 lw a7,4(a1) -80011564: 0085ae83 lw t4,8(a1) -80011568: 00f6f6b3 and a3,a3,a5 -8001156c: 01051593 slli a1,a0,0x10 -80011570: ff010113 addi sp,sp,-16 -80011574: 0105d593 srli a1,a1,0x10 -80011578: 01f55513 srli a0,a0,0x1f -8001157c: 01035313 srli t1,t1,0x10 -80011580: 00f77733 and a4,a4,a5 -80011584: 01f65613 srli a2,a2,0x1f -80011588: 00f69e63 bne a3,a5,800115a4 <__getf2+0x70> -8001158c: 01f867b3 or a5,a6,t6 -80011590: 01c7e7b3 or a5,a5,t3 -80011594: 00b7e7b3 or a5,a5,a1 -80011598: 0c078863 beqz a5,80011668 <__getf2+0x134> -8001159c: ffe00513 li a0,-2 -800115a0: 0600006f j 80011600 <__getf2+0xcc> -800115a4: 00f71a63 bne a4,a5,800115b8 <__getf2+0x84> -800115a8: 0058e7b3 or a5,a7,t0 -800115ac: 01d7e7b3 or a5,a5,t4 -800115b0: 0067e7b3 or a5,a5,t1 -800115b4: fe0794e3 bnez a5,8001159c <__getf2+0x68> -800115b8: 0a069a63 bnez a3,8001166c <__getf2+0x138> -800115bc: 01f867b3 or a5,a6,t6 -800115c0: 01c7e7b3 or a5,a5,t3 -800115c4: 00b7e7b3 or a5,a5,a1 -800115c8: 0017b793 seqz a5,a5 -800115cc: 00071a63 bnez a4,800115e0 <__getf2+0xac> -800115d0: 0058ef33 or t5,a7,t0 -800115d4: 01df6f33 or t5,t5,t4 -800115d8: 006f6f33 or t5,t5,t1 -800115dc: 060f0a63 beqz t5,80011650 <__getf2+0x11c> -800115e0: 00079a63 bnez a5,800115f4 <__getf2+0xc0> -800115e4: 02c50263 beq a0,a2,80011608 <__getf2+0xd4> -800115e8: 06050063 beqz a0,80011648 <__getf2+0x114> -800115ec: fff00513 li a0,-1 -800115f0: 0100006f j 80011600 <__getf2+0xcc> -800115f4: fff00513 li a0,-1 -800115f8: 00060463 beqz a2,80011600 <__getf2+0xcc> -800115fc: 00060513 mv a0,a2 -80011600: 01010113 addi sp,sp,16 -80011604: 00008067 ret -80011608: fed740e3 blt a4,a3,800115e8 <__getf2+0xb4> -8001160c: 00e6d663 bge a3,a4,80011618 <__getf2+0xe4> -80011610: fe0518e3 bnez a0,80011600 <__getf2+0xcc> -80011614: fd9ff06f j 800115ec <__getf2+0xb8> -80011618: fcb368e3 bltu t1,a1,800115e8 <__getf2+0xb4> -8001161c: 02659e63 bne a1,t1,80011658 <__getf2+0x124> -80011620: fdcee4e3 bltu t4,t3,800115e8 <__getf2+0xb4> -80011624: 03ce9e63 bne t4,t3,80011660 <__getf2+0x12c> -80011628: fd08e0e3 bltu a7,a6,800115e8 <__getf2+0xb4> -8001162c: 01089463 bne a7,a6,80011634 <__getf2+0x100> -80011630: fbf2ece3 bltu t0,t6,800115e8 <__getf2+0xb4> -80011634: fd186ee3 bltu a6,a7,80011610 <__getf2+0xdc> -80011638: 01089463 bne a7,a6,80011640 <__getf2+0x10c> -8001163c: fc5feae3 bltu t6,t0,80011610 <__getf2+0xdc> -80011640: 00000513 li a0,0 -80011644: fbdff06f j 80011600 <__getf2+0xcc> -80011648: 00100513 li a0,1 -8001164c: fb5ff06f j 80011600 <__getf2+0xcc> -80011650: fe0798e3 bnez a5,80011640 <__getf2+0x10c> -80011654: f95ff06f j 800115e8 <__getf2+0xb4> -80011658: fa65ece3 bltu a1,t1,80011610 <__getf2+0xdc> -8001165c: fe5ff06f j 80011640 <__getf2+0x10c> -80011660: fbde68e3 bltu t3,t4,80011610 <__getf2+0xdc> -80011664: fddff06f j 80011640 <__getf2+0x10c> -80011668: f4d700e3 beq a4,a3,800115a8 <__getf2+0x74> -8001166c: f6071ce3 bnez a4,800115e4 <__getf2+0xb0> -80011670: 00000793 li a5,0 -80011674: f5dff06f j 800115d0 <__getf2+0x9c> - -80011678 <__letf2>: -80011678: 00052f83 lw t6,0(a0) -8001167c: 00452803 lw a6,4(a0) -80011680: 00852e03 lw t3,8(a0) -80011684: 00c52503 lw a0,12(a0) -80011688: 00c5a603 lw a2,12(a1) -8001168c: 000087b7 lui a5,0x8 -80011690: 01055693 srli a3,a0,0x10 -80011694: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80011698: 01061313 slli t1,a2,0x10 -8001169c: 01065713 srli a4,a2,0x10 -800116a0: 0005a283 lw t0,0(a1) -800116a4: 0045a883 lw a7,4(a1) -800116a8: 0085ae83 lw t4,8(a1) -800116ac: 00f6f6b3 and a3,a3,a5 -800116b0: 01051593 slli a1,a0,0x10 -800116b4: ff010113 addi sp,sp,-16 -800116b8: 0105d593 srli a1,a1,0x10 -800116bc: 01f55513 srli a0,a0,0x1f -800116c0: 01035313 srli t1,t1,0x10 -800116c4: 00f77733 and a4,a4,a5 -800116c8: 01f65613 srli a2,a2,0x1f -800116cc: 00f69e63 bne a3,a5,800116e8 <__letf2+0x70> -800116d0: 01f867b3 or a5,a6,t6 -800116d4: 01c7e7b3 or a5,a5,t3 -800116d8: 00b7e7b3 or a5,a5,a1 -800116dc: 0c078863 beqz a5,800117ac <__letf2+0x134> -800116e0: 00200513 li a0,2 -800116e4: 0600006f j 80011744 <__letf2+0xcc> -800116e8: 00f71a63 bne a4,a5,800116fc <__letf2+0x84> -800116ec: 0058e7b3 or a5,a7,t0 -800116f0: 01d7e7b3 or a5,a5,t4 -800116f4: 0067e7b3 or a5,a5,t1 -800116f8: fe0794e3 bnez a5,800116e0 <__letf2+0x68> -800116fc: 0a069a63 bnez a3,800117b0 <__letf2+0x138> -80011700: 01f867b3 or a5,a6,t6 -80011704: 01c7e7b3 or a5,a5,t3 -80011708: 00b7e7b3 or a5,a5,a1 -8001170c: 0017b793 seqz a5,a5 -80011710: 00071a63 bnez a4,80011724 <__letf2+0xac> -80011714: 0058ef33 or t5,a7,t0 -80011718: 01df6f33 or t5,t5,t4 -8001171c: 006f6f33 or t5,t5,t1 -80011720: 060f0a63 beqz t5,80011794 <__letf2+0x11c> -80011724: 00079a63 bnez a5,80011738 <__letf2+0xc0> -80011728: 02c50263 beq a0,a2,8001174c <__letf2+0xd4> -8001172c: 06050063 beqz a0,8001178c <__letf2+0x114> -80011730: fff00513 li a0,-1 -80011734: 0100006f j 80011744 <__letf2+0xcc> -80011738: fff00513 li a0,-1 -8001173c: 00060463 beqz a2,80011744 <__letf2+0xcc> -80011740: 00060513 mv a0,a2 -80011744: 01010113 addi sp,sp,16 -80011748: 00008067 ret -8001174c: fed740e3 blt a4,a3,8001172c <__letf2+0xb4> -80011750: 00e6d663 bge a3,a4,8001175c <__letf2+0xe4> -80011754: fe0518e3 bnez a0,80011744 <__letf2+0xcc> -80011758: fd9ff06f j 80011730 <__letf2+0xb8> -8001175c: fcb368e3 bltu t1,a1,8001172c <__letf2+0xb4> -80011760: 02659e63 bne a1,t1,8001179c <__letf2+0x124> -80011764: fdcee4e3 bltu t4,t3,8001172c <__letf2+0xb4> -80011768: 03ce9e63 bne t4,t3,800117a4 <__letf2+0x12c> -8001176c: fd08e0e3 bltu a7,a6,8001172c <__letf2+0xb4> -80011770: 01089463 bne a7,a6,80011778 <__letf2+0x100> -80011774: fbf2ece3 bltu t0,t6,8001172c <__letf2+0xb4> -80011778: fd186ee3 bltu a6,a7,80011754 <__letf2+0xdc> -8001177c: 01089463 bne a7,a6,80011784 <__letf2+0x10c> -80011780: fc5feae3 bltu t6,t0,80011754 <__letf2+0xdc> -80011784: 00000513 li a0,0 -80011788: fbdff06f j 80011744 <__letf2+0xcc> -8001178c: 00100513 li a0,1 -80011790: fb5ff06f j 80011744 <__letf2+0xcc> -80011794: fe0798e3 bnez a5,80011784 <__letf2+0x10c> -80011798: f95ff06f j 8001172c <__letf2+0xb4> -8001179c: fa65ece3 bltu a1,t1,80011754 <__letf2+0xdc> -800117a0: fe5ff06f j 80011784 <__letf2+0x10c> -800117a4: fbde68e3 bltu t3,t4,80011754 <__letf2+0xdc> -800117a8: fddff06f j 80011784 <__letf2+0x10c> -800117ac: f4d700e3 beq a4,a3,800116ec <__letf2+0x74> -800117b0: f6071ce3 bnez a4,80011728 <__letf2+0xb0> -800117b4: 00000793 li a5,0 -800117b8: f5dff06f j 80011714 <__letf2+0x9c> - -800117bc <__multf3>: -800117bc: f4010113 addi sp,sp,-192 -800117c0: 0b312623 sw s3,172(sp) -800117c4: 00c5a983 lw s3,12(a1) -800117c8: 0005a683 lw a3,0(a1) -800117cc: 0045a783 lw a5,4(a1) -800117d0: 00a12623 sw a0,12(sp) -800117d4: 0085a503 lw a0,8(a1) -800117d8: 01099713 slli a4,s3,0x10 -800117dc: 0b212823 sw s2,176(sp) -800117e0: 0b412423 sw s4,168(sp) -800117e4: 0b512223 sw s5,164(sp) -800117e8: 0b612023 sw s6,160(sp) -800117ec: 00062a03 lw s4,0(a2) # 1000000 <_start-0x7f000000> -800117f0: 00462b03 lw s6,4(a2) -800117f4: 00862a83 lw s5,8(a2) -800117f8: 00c62903 lw s2,12(a2) -800117fc: 00008637 lui a2,0x8 -80011800: 0a912a23 sw s1,180(sp) -80011804: 01075713 srli a4,a4,0x10 -80011808: 0109d493 srli s1,s3,0x10 -8001180c: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> -80011810: 07312623 sw s3,108(sp) -80011814: 0a112e23 sw ra,188(sp) -80011818: 0a812c23 sw s0,184(sp) -8001181c: 09712e23 sw s7,156(sp) -80011820: 09812c23 sw s8,152(sp) -80011824: 09912a23 sw s9,148(sp) -80011828: 09a12823 sw s10,144(sp) -8001182c: 09b12623 sw s11,140(sp) -80011830: 06d12023 sw a3,96(sp) -80011834: 06f12223 sw a5,100(sp) -80011838: 06a12423 sw a0,104(sp) -8001183c: 02d12823 sw a3,48(sp) -80011840: 02f12a23 sw a5,52(sp) -80011844: 02a12c23 sw a0,56(sp) -80011848: 02e12e23 sw a4,60(sp) -8001184c: 00c4f4b3 and s1,s1,a2 -80011850: 01f9d993 srli s3,s3,0x1f -80011854: 12048863 beqz s1,80011984 <__multf3+0x1c8> -80011858: 24c48663 beq s1,a2,80011aa4 <__multf3+0x2e8> -8001185c: 000107b7 lui a5,0x10 -80011860: 00f767b3 or a5,a4,a5 -80011864: 02f12e23 sw a5,60(sp) -80011868: 03010613 addi a2,sp,48 -8001186c: 03c10793 addi a5,sp,60 -80011870: 0007a703 lw a4,0(a5) # 10000 <_start-0x7fff0000> -80011874: ffc7a683 lw a3,-4(a5) -80011878: ffc78793 addi a5,a5,-4 -8001187c: 00371713 slli a4,a4,0x3 -80011880: 01d6d693 srli a3,a3,0x1d -80011884: 00d76733 or a4,a4,a3 -80011888: 00e7a223 sw a4,4(a5) -8001188c: fef612e3 bne a2,a5,80011870 <__multf3+0xb4> -80011890: 03012783 lw a5,48(sp) -80011894: ffffc537 lui a0,0xffffc -80011898: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe5289> -8001189c: 00379793 slli a5,a5,0x3 -800118a0: 02f12823 sw a5,48(sp) -800118a4: 00a484b3 add s1,s1,a0 -800118a8: 00000b93 li s7,0 -800118ac: 01091513 slli a0,s2,0x10 -800118b0: 00008737 lui a4,0x8 -800118b4: 01095793 srli a5,s2,0x10 -800118b8: 01055513 srli a0,a0,0x10 -800118bc: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -800118c0: 07212623 sw s2,108(sp) -800118c4: 07412023 sw s4,96(sp) -800118c8: 07612223 sw s6,100(sp) -800118cc: 07512423 sw s5,104(sp) -800118d0: 05412023 sw s4,64(sp) -800118d4: 05612223 sw s6,68(sp) -800118d8: 05512423 sw s5,72(sp) -800118dc: 04a12623 sw a0,76(sp) -800118e0: 00e7f7b3 and a5,a5,a4 -800118e4: 01f95913 srli s2,s2,0x1f -800118e8: 1e078263 beqz a5,80011acc <__multf3+0x310> -800118ec: 30e78063 beq a5,a4,80011bec <__multf3+0x430> -800118f0: 00010ab7 lui s5,0x10 -800118f4: 01556ab3 or s5,a0,s5 -800118f8: 05512623 sw s5,76(sp) -800118fc: 04010593 addi a1,sp,64 -80011900: 04c10713 addi a4,sp,76 -80011904: 00072683 lw a3,0(a4) -80011908: ffc72603 lw a2,-4(a4) -8001190c: ffc70713 addi a4,a4,-4 -80011910: 00369693 slli a3,a3,0x3 -80011914: 01d65613 srli a2,a2,0x1d -80011918: 00c6e6b3 or a3,a3,a2 -8001191c: 00d72223 sw a3,4(a4) -80011920: fee592e3 bne a1,a4,80011904 <__multf3+0x148> -80011924: 04012703 lw a4,64(sp) -80011928: ffffc537 lui a0,0xffffc -8001192c: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe5289> -80011930: 00371713 slli a4,a4,0x3 -80011934: 04e12023 sw a4,64(sp) -80011938: 00a787b3 add a5,a5,a0 -8001193c: 00000713 li a4,0 -80011940: 00f487b3 add a5,s1,a5 -80011944: 02f12023 sw a5,32(sp) -80011948: 00178793 addi a5,a5,1 -8001194c: 00f12e23 sw a5,28(sp) -80011950: 002b9793 slli a5,s7,0x2 -80011954: 0129c6b3 xor a3,s3,s2 -80011958: 00e7e7b3 or a5,a5,a4 -8001195c: 00d12823 sw a3,16(sp) -80011960: fff78793 addi a5,a5,-1 -80011964: 00e00693 li a3,14 -80011968: 2af6e663 bltu a3,a5,80011c14 <__multf3+0x458> -8001196c: 800156b7 lui a3,0x80015 -80011970: 00279793 slli a5,a5,0x2 -80011974: 1e868693 addi a3,a3,488 # 800151e8 <__BSS_END__+0xffffe470> -80011978: 00d787b3 add a5,a5,a3 -8001197c: 0007a783 lw a5,0(a5) -80011980: 00078067 jr a5 -80011984: 00d7e633 or a2,a5,a3 -80011988: 00a66633 or a2,a2,a0 -8001198c: 00e66633 or a2,a2,a4 -80011990: 12060863 beqz a2,80011ac0 <__multf3+0x304> -80011994: 06070063 beqz a4,800119f4 <__multf3+0x238> -80011998: 00070513 mv a0,a4 -8001199c: 361020ef jal ra,800144fc <__clzsi2> -800119a0: ff450693 addi a3,a0,-12 -800119a4: 4056d793 srai a5,a3,0x5 -800119a8: 01f6f693 andi a3,a3,31 -800119ac: 06068e63 beqz a3,80011a28 <__multf3+0x26c> -800119b0: ffc00713 li a4,-4 -800119b4: 02e78733 mul a4,a5,a4 -800119b8: 03010313 addi t1,sp,48 -800119bc: 02000813 li a6,32 -800119c0: 00279593 slli a1,a5,0x2 -800119c4: 40d80833 sub a6,a6,a3 -800119c8: 00c70713 addi a4,a4,12 -800119cc: 00e30733 add a4,t1,a4 -800119d0: 08e31463 bne t1,a4,80011a58 <__multf3+0x29c> -800119d4: 08010713 addi a4,sp,128 -800119d8: 00b705b3 add a1,a4,a1 -800119dc: 03012703 lw a4,48(sp) -800119e0: fff78793 addi a5,a5,-1 -800119e4: 00d716b3 sll a3,a4,a3 -800119e8: fad5a823 sw a3,-80(a1) -800119ec: fff00693 li a3,-1 -800119f0: 0a00006f j 80011a90 <__multf3+0x2d4> -800119f4: 00050863 beqz a0,80011a04 <__multf3+0x248> -800119f8: 305020ef jal ra,800144fc <__clzsi2> -800119fc: 02050513 addi a0,a0,32 -80011a00: fa1ff06f j 800119a0 <__multf3+0x1e4> -80011a04: 00078a63 beqz a5,80011a18 <__multf3+0x25c> -80011a08: 00078513 mv a0,a5 -80011a0c: 2f1020ef jal ra,800144fc <__clzsi2> -80011a10: 04050513 addi a0,a0,64 -80011a14: f8dff06f j 800119a0 <__multf3+0x1e4> -80011a18: 00068513 mv a0,a3 -80011a1c: 2e1020ef jal ra,800144fc <__clzsi2> -80011a20: 06050513 addi a0,a0,96 -80011a24: f7dff06f j 800119a0 <__multf3+0x1e4> -80011a28: ffc00613 li a2,-4 -80011a2c: 02c78633 mul a2,a5,a2 -80011a30: 03c10713 addi a4,sp,60 -80011a34: 00300693 li a3,3 -80011a38: 00c705b3 add a1,a4,a2 -80011a3c: 0005a583 lw a1,0(a1) -80011a40: fff68693 addi a3,a3,-1 -80011a44: ffc70713 addi a4,a4,-4 -80011a48: 00b72223 sw a1,4(a4) -80011a4c: fef6d6e3 bge a3,a5,80011a38 <__multf3+0x27c> -80011a50: fff78793 addi a5,a5,-1 -80011a54: f99ff06f j 800119ec <__multf3+0x230> -80011a58: ffc72603 lw a2,-4(a4) -80011a5c: 00072883 lw a7,0(a4) -80011a60: 00b70e33 add t3,a4,a1 -80011a64: 01065633 srl a2,a2,a6 -80011a68: 00d898b3 sll a7,a7,a3 -80011a6c: 01166633 or a2,a2,a7 -80011a70: 00ce2023 sw a2,0(t3) -80011a74: ffc70713 addi a4,a4,-4 -80011a78: f59ff06f j 800119d0 <__multf3+0x214> -80011a7c: 00279713 slli a4,a5,0x2 -80011a80: 03010613 addi a2,sp,48 -80011a84: 00e60733 add a4,a2,a4 -80011a88: 00072023 sw zero,0(a4) -80011a8c: fff78793 addi a5,a5,-1 -80011a90: fed796e3 bne a5,a3,80011a7c <__multf3+0x2c0> -80011a94: ffffc4b7 lui s1,0xffffc -80011a98: 01148493 addi s1,s1,17 # ffffc011 <__BSS_END__+0x7ffe5299> -80011a9c: 40a484b3 sub s1,s1,a0 -80011aa0: e09ff06f j 800118a8 <__multf3+0xec> -80011aa4: 00d7e7b3 or a5,a5,a3 -80011aa8: 00a7e7b3 or a5,a5,a0 -80011aac: 00e7e7b3 or a5,a5,a4 -80011ab0: 00300b93 li s7,3 -80011ab4: de079ce3 bnez a5,800118ac <__multf3+0xf0> -80011ab8: 00200b93 li s7,2 -80011abc: df1ff06f j 800118ac <__multf3+0xf0> -80011ac0: 00000493 li s1,0 -80011ac4: 00100b93 li s7,1 -80011ac8: de5ff06f j 800118ac <__multf3+0xf0> -80011acc: 016a67b3 or a5,s4,s6 -80011ad0: 0157e7b3 or a5,a5,s5 -80011ad4: 00a7e7b3 or a5,a5,a0 -80011ad8: 12078863 beqz a5,80011c08 <__multf3+0x44c> -80011adc: 04050e63 beqz a0,80011b38 <__multf3+0x37c> -80011ae0: 21d020ef jal ra,800144fc <__clzsi2> -80011ae4: ff450613 addi a2,a0,-12 -80011ae8: 40565713 srai a4,a2,0x5 -80011aec: 01f67613 andi a2,a2,31 -80011af0: 08060063 beqz a2,80011b70 <__multf3+0x3b4> -80011af4: ffc00693 li a3,-4 -80011af8: 02d706b3 mul a3,a4,a3 -80011afc: 04010313 addi t1,sp,64 -80011b00: 02000793 li a5,32 -80011b04: 00271813 slli a6,a4,0x2 -80011b08: 40c787b3 sub a5,a5,a2 -80011b0c: 00c68693 addi a3,a3,12 -80011b10: 00d306b3 add a3,t1,a3 -80011b14: 08d31663 bne t1,a3,80011ba0 <__multf3+0x3e4> -80011b18: 08010793 addi a5,sp,128 -80011b1c: 01078833 add a6,a5,a6 -80011b20: 04012783 lw a5,64(sp) -80011b24: fff70713 addi a4,a4,-1 -80011b28: 00c79633 sll a2,a5,a2 -80011b2c: fcc82023 sw a2,-64(a6) -80011b30: fff00693 li a3,-1 -80011b34: 0a40006f j 80011bd8 <__multf3+0x41c> -80011b38: 000a8a63 beqz s5,80011b4c <__multf3+0x390> -80011b3c: 000a8513 mv a0,s5 -80011b40: 1bd020ef jal ra,800144fc <__clzsi2> -80011b44: 02050513 addi a0,a0,32 -80011b48: f9dff06f j 80011ae4 <__multf3+0x328> -80011b4c: 000b0a63 beqz s6,80011b60 <__multf3+0x3a4> -80011b50: 000b0513 mv a0,s6 -80011b54: 1a9020ef jal ra,800144fc <__clzsi2> -80011b58: 04050513 addi a0,a0,64 -80011b5c: f89ff06f j 80011ae4 <__multf3+0x328> -80011b60: 000a0513 mv a0,s4 -80011b64: 199020ef jal ra,800144fc <__clzsi2> -80011b68: 06050513 addi a0,a0,96 -80011b6c: f79ff06f j 80011ae4 <__multf3+0x328> -80011b70: ffc00613 li a2,-4 -80011b74: 02c70633 mul a2,a4,a2 -80011b78: 04c10693 addi a3,sp,76 -80011b7c: 00300793 li a5,3 -80011b80: 00c685b3 add a1,a3,a2 -80011b84: 0005a583 lw a1,0(a1) -80011b88: fff78793 addi a5,a5,-1 -80011b8c: ffc68693 addi a3,a3,-4 -80011b90: 00b6a223 sw a1,4(a3) -80011b94: fee7d6e3 bge a5,a4,80011b80 <__multf3+0x3c4> -80011b98: fff70713 addi a4,a4,-1 -80011b9c: f95ff06f j 80011b30 <__multf3+0x374> -80011ba0: ffc6a583 lw a1,-4(a3) -80011ba4: 0006a883 lw a7,0(a3) -80011ba8: 01068e33 add t3,a3,a6 -80011bac: 00f5d5b3 srl a1,a1,a5 -80011bb0: 00c898b3 sll a7,a7,a2 -80011bb4: 0115e5b3 or a1,a1,a7 -80011bb8: 00be2023 sw a1,0(t3) -80011bbc: ffc68693 addi a3,a3,-4 -80011bc0: f55ff06f j 80011b14 <__multf3+0x358> -80011bc4: 00271793 slli a5,a4,0x2 -80011bc8: 04010613 addi a2,sp,64 -80011bcc: 00f607b3 add a5,a2,a5 -80011bd0: 0007a023 sw zero,0(a5) -80011bd4: fff70713 addi a4,a4,-1 -80011bd8: fed716e3 bne a4,a3,80011bc4 <__multf3+0x408> -80011bdc: ffffc7b7 lui a5,0xffffc -80011be0: 01178793 addi a5,a5,17 # ffffc011 <__BSS_END__+0x7ffe5299> -80011be4: 40a787b3 sub a5,a5,a0 -80011be8: d55ff06f j 8001193c <__multf3+0x180> -80011bec: 016a6a33 or s4,s4,s6 -80011bf0: 015a6ab3 or s5,s4,s5 -80011bf4: 00aaeab3 or s5,s5,a0 -80011bf8: 00300713 li a4,3 -80011bfc: d40a92e3 bnez s5,80011940 <__multf3+0x184> -80011c00: 00200713 li a4,2 -80011c04: d3dff06f j 80011940 <__multf3+0x184> -80011c08: 00000793 li a5,0 -80011c0c: 00100713 li a4,1 -80011c10: d31ff06f j 80011940 <__multf3+0x184> -80011c14: 03012703 lw a4,48(sp) -80011c18: 04012e03 lw t3,64(sp) -80011c1c: 00010537 lui a0,0x10 -80011c20: fff50693 addi a3,a0,-1 # ffff <_start-0x7fff0001> -80011c24: 01075f93 srli t6,a4,0x10 -80011c28: 010e5a93 srli s5,t3,0x10 -80011c2c: 00d77733 and a4,a4,a3 -80011c30: 00de7e33 and t3,t3,a3 -80011c34: 02ea87b3 mul a5,s5,a4 -80011c38: 02ee0633 mul a2,t3,a4 -80011c3c: 03cf8833 mul a6,t6,t3 -80011c40: 010785b3 add a1,a5,a6 -80011c44: 01065793 srli a5,a2,0x10 -80011c48: 00b787b3 add a5,a5,a1 -80011c4c: 035f8b33 mul s6,t6,s5 -80011c50: 0107f463 bgeu a5,a6,80011c58 <__multf3+0x49c> -80011c54: 00ab0b33 add s6,s6,a0 -80011c58: 04412f03 lw t5,68(sp) -80011c5c: 0107d293 srli t0,a5,0x10 -80011c60: 00d7f7b3 and a5,a5,a3 -80011c64: 00d67633 and a2,a2,a3 -80011c68: 01079793 slli a5,a5,0x10 -80011c6c: 00c787b3 add a5,a5,a2 -80011c70: 010f5493 srli s1,t5,0x10 -80011c74: 00df7f33 and t5,t5,a3 -80011c78: 02f12223 sw a5,36(sp) -80011c7c: 06f12023 sw a5,96(sp) -80011c80: 02ef06b3 mul a3,t5,a4 -80011c84: 02e487b3 mul a5,s1,a4 -80011c88: 03ef8633 mul a2,t6,t5 -80011c8c: 00c78533 add a0,a5,a2 -80011c90: 0106d793 srli a5,a3,0x10 -80011c94: 00a787b3 add a5,a5,a0 -80011c98: 029f8a33 mul s4,t6,s1 -80011c9c: 00c7f663 bgeu a5,a2,80011ca8 <__multf3+0x4ec> -80011ca0: 00010637 lui a2,0x10 -80011ca4: 00ca0a33 add s4,s4,a2 -80011ca8: 00010637 lui a2,0x10 -80011cac: fff60593 addi a1,a2,-1 # ffff <_start-0x7fff0001> -80011cb0: 00b7f533 and a0,a5,a1 -80011cb4: 0107dd93 srli s11,a5,0x10 -80011cb8: 03412783 lw a5,52(sp) -80011cbc: 00b6f6b3 and a3,a3,a1 -80011cc0: 01051513 slli a0,a0,0x10 -80011cc4: 0107d913 srli s2,a5,0x10 -80011cc8: 00b7f5b3 and a1,a5,a1 -80011ccc: 00d50533 add a0,a0,a3 -80011cd0: 02ba87b3 mul a5,s5,a1 -80011cd4: 00a282b3 add t0,t0,a0 -80011cd8: 02be06b3 mul a3,t3,a1 -80011cdc: 03c90333 mul t1,s2,t3 -80011ce0: 00678833 add a6,a5,t1 -80011ce4: 0106d793 srli a5,a3,0x10 -80011ce8: 010787b3 add a5,a5,a6 -80011cec: 032a88b3 mul a7,s5,s2 -80011cf0: 0067f463 bgeu a5,t1,80011cf8 <__multf3+0x53c> -80011cf4: 00c888b3 add a7,a7,a2 -80011cf8: 0107d993 srli s3,a5,0x10 -80011cfc: 011989b3 add s3,s3,a7 -80011d00: 000108b7 lui a7,0x10 -80011d04: fff88613 addi a2,a7,-1 # ffff <_start-0x7fff0001> -80011d08: 00c7f833 and a6,a5,a2 -80011d0c: 01081813 slli a6,a6,0x10 -80011d10: 00c6f7b3 and a5,a3,a2 -80011d14: 00f80833 add a6,a6,a5 -80011d18: 03e58633 mul a2,a1,t5 -80011d1c: 03e907b3 mul a5,s2,t5 -80011d20: 01065e93 srli t4,a2,0x10 -80011d24: 02b486b3 mul a3,s1,a1 -80011d28: 00f686b3 add a3,a3,a5 -80011d2c: 00de86b3 add a3,t4,a3 -80011d30: 03248333 mul t1,s1,s2 -80011d34: 00f6f463 bgeu a3,a5,80011d3c <__multf3+0x580> -80011d38: 01130333 add t1,t1,a7 -80011d3c: 0106d793 srli a5,a3,0x10 -80011d40: 04812e83 lw t4,72(sp) -80011d44: 006787b3 add a5,a5,t1 -80011d48: 000103b7 lui t2,0x10 -80011d4c: 02f12423 sw a5,40(sp) -80011d50: fff38793 addi a5,t2,-1 # ffff <_start-0x7fff0001> -80011d54: 010ed413 srli s0,t4,0x10 -80011d58: 00fefeb3 and t4,t4,a5 -80011d5c: 02e408b3 mul a7,s0,a4 -80011d60: 00f67633 and a2,a2,a5 -80011d64: 00f6f6b3 and a3,a3,a5 -80011d68: 01069693 slli a3,a3,0x10 -80011d6c: 00c686b3 add a3,a3,a2 -80011d70: 02ee8333 mul t1,t4,a4 -80011d74: 03df8bb3 mul s7,t6,t4 -80011d78: 017887b3 add a5,a7,s7 -80011d7c: 01035893 srli a7,t1,0x10 -80011d80: 00f888b3 add a7,a7,a5 -80011d84: 028f8633 mul a2,t6,s0 -80011d88: 0178f463 bgeu a7,s7,80011d90 <__multf3+0x5d4> -80011d8c: 00760633 add a2,a2,t2 -80011d90: 0108d793 srli a5,a7,0x10 -80011d94: 00010c37 lui s8,0x10 -80011d98: 00c787b3 add a5,a5,a2 -80011d9c: fffc0613 addi a2,s8,-1 # ffff <_start-0x7fff0001> -80011da0: 02f12623 sw a5,44(sp) -80011da4: 00c8f7b3 and a5,a7,a2 -80011da8: 03812883 lw a7,56(sp) -80011dac: 00c37333 and t1,t1,a2 -80011db0: 01079793 slli a5,a5,0x10 -80011db4: 0108d393 srli t2,a7,0x10 -80011db8: 00c8f633 and a2,a7,a2 -80011dbc: 006787b3 add a5,a5,t1 -80011dc0: 03c608b3 mul a7,a2,t3 -80011dc4: 03c38cb3 mul s9,t2,t3 -80011dc8: 0108dd13 srli s10,a7,0x10 -80011dcc: 02ca8333 mul t1,s5,a2 -80011dd0: 01930333 add t1,t1,s9 -80011dd4: 006d0333 add t1,s10,t1 -80011dd8: 027a8bb3 mul s7,s5,t2 -80011ddc: 01937463 bgeu t1,s9,80011de4 <__multf3+0x628> -80011de0: 018b8bb3 add s7,s7,s8 -80011de4: 01035c13 srli s8,t1,0x10 -80011de8: 017c0bb3 add s7,s8,s7 -80011dec: 00010c37 lui s8,0x10 -80011df0: 005b02b3 add t0,s6,t0 -80011df4: fffc0c93 addi s9,s8,-1 # ffff <_start-0x7fff0001> -80011df8: 00a2b533 sltu a0,t0,a0 -80011dfc: 01937333 and t1,t1,s9 -80011e00: 00ad8db3 add s11,s11,a0 -80011e04: 01031313 slli t1,t1,0x10 -80011e08: 0198f8b3 and a7,a7,s9 -80011e0c: 014d8a33 add s4,s11,s4 -80011e10: 011308b3 add a7,t1,a7 -80011e14: 01028333 add t1,t0,a6 -80011e18: 01033833 sltu a6,t1,a6 -80011e1c: 00612a23 sw t1,20(sp) -80011e20: 06612223 sw t1,100(sp) -80011e24: 013a0333 add t1,s4,s3 -80011e28: 01030b33 add s6,t1,a6 -80011e2c: 013339b3 sltu s3,t1,s3 -80011e30: 010b3833 sltu a6,s6,a6 -80011e34: 0109e833 or a6,s3,a6 -80011e38: 00aa3533 sltu a0,s4,a0 -80011e3c: 00a80533 add a0,a6,a0 -80011e40: 02812803 lw a6,40(sp) -80011e44: 00db02b3 add t0,s6,a3 -80011e48: 02812983 lw s3,40(sp) -80011e4c: 00d2b6b3 sltu a3,t0,a3 -80011e50: 01050533 add a0,a0,a6 -80011e54: 02c12303 lw t1,44(sp) -80011e58: 00d50833 add a6,a0,a3 -80011e5c: 00f282b3 add t0,t0,a5 -80011e60: 01353533 sltu a0,a0,s3 -80011e64: 00d836b3 sltu a3,a6,a3 -80011e68: 00f2b7b3 sltu a5,t0,a5 -80011e6c: 00680db3 add s11,a6,t1 -80011e70: 00d566b3 or a3,a0,a3 -80011e74: 02c12503 lw a0,44(sp) -80011e78: 00fd8333 add t1,s11,a5 -80011e7c: 011282b3 add t0,t0,a7 -80011e80: 0112b8b3 sltu a7,t0,a7 -80011e84: 00f337b3 sltu a5,t1,a5 -80011e88: 00512c23 sw t0,24(sp) -80011e8c: 06512423 sw t0,104(sp) -80011e90: 017302b3 add t0,t1,s7 -80011e94: 04c12303 lw t1,76(sp) -80011e98: 01128d33 add s10,t0,a7 -80011e9c: 00adbdb3 sltu s11,s11,a0 -80011ea0: 00fde7b3 or a5,s11,a5 -80011ea4: 0172bbb3 sltu s7,t0,s7 -80011ea8: 011d38b3 sltu a7,s10,a7 -80011eac: 00f686b3 add a3,a3,a5 -80011eb0: 01035293 srli t0,t1,0x10 -80011eb4: 011bea33 or s4,s7,a7 -80011eb8: 01937333 and t1,t1,s9 -80011ebc: 02e307b3 mul a5,t1,a4 -80011ec0: 01468a33 add s4,a3,s4 -80011ec4: 02e28733 mul a4,t0,a4 -80011ec8: 0107d893 srli a7,a5,0x10 -80011ecc: 026f86b3 mul a3,t6,t1 -80011ed0: 00d70733 add a4,a4,a3 -80011ed4: 00e888b3 add a7,a7,a4 -80011ed8: 025f8fb3 mul t6,t6,t0 -80011edc: 00d8f463 bgeu a7,a3,80011ee4 <__multf3+0x728> -80011ee0: 018f8fb3 add t6,t6,s8 -80011ee4: 03c12983 lw s3,60(sp) -80011ee8: 000106b7 lui a3,0x10 -80011eec: fff68513 addi a0,a3,-1 # ffff <_start-0x7fff0001> -80011ef0: 0108d713 srli a4,a7,0x10 -80011ef4: 00a8f8b3 and a7,a7,a0 -80011ef8: 01f70733 add a4,a4,t6 -80011efc: 00a7f7b3 and a5,a5,a0 -80011f00: 0109df93 srli t6,s3,0x10 -80011f04: 01089893 slli a7,a7,0x10 -80011f08: 00a9f9b3 and s3,s3,a0 -80011f0c: 00f888b3 add a7,a7,a5 -80011f10: 03fa8b33 mul s6,s5,t6 -80011f14: 00070d93 mv s11,a4 -80011f18: 033e07b3 mul a5,t3,s3 -80011f1c: 033a8ab3 mul s5,s5,s3 -80011f20: 0107d813 srli a6,a5,0x10 -80011f24: 03cf8e33 mul t3,t6,t3 -80011f28: 01ca8ab3 add s5,s5,t3 -80011f2c: 01580ab3 add s5,a6,s5 -80011f30: 01caf463 bgeu s5,t3,80011f38 <__multf3+0x77c> -80011f34: 00db0b33 add s6,s6,a3 -80011f38: 010ad813 srli a6,s5,0x10 -80011f3c: 01680733 add a4,a6,s6 -80011f40: 00010b37 lui s6,0x10 -80011f44: 02e12423 sw a4,40(sp) -80011f48: fffb0713 addi a4,s6,-1 # ffff <_start-0x7fff0001> -80011f4c: 00eaf833 and a6,s5,a4 -80011f50: 00e7f7b3 and a5,a5,a4 -80011f54: 01081813 slli a6,a6,0x10 -80011f58: 00f80833 add a6,a6,a5 -80011f5c: 02be86b3 mul a3,t4,a1 -80011f60: 03d90e33 mul t3,s2,t4 -80011f64: 0106d513 srli a0,a3,0x10 -80011f68: 02b407b3 mul a5,s0,a1 -80011f6c: 01c787b3 add a5,a5,t3 -80011f70: 00f507b3 add a5,a0,a5 -80011f74: 02890733 mul a4,s2,s0 -80011f78: 01c7f463 bgeu a5,t3,80011f80 <__multf3+0x7c4> -80011f7c: 01670733 add a4,a4,s6 -80011f80: 0107d513 srli a0,a5,0x10 -80011f84: 00e50733 add a4,a0,a4 -80011f88: 00010b37 lui s6,0x10 -80011f8c: 02e12623 sw a4,44(sp) -80011f90: fffb0713 addi a4,s6,-1 # ffff <_start-0x7fff0001> -80011f94: 00e7f533 and a0,a5,a4 -80011f98: 00e6f6b3 and a3,a3,a4 -80011f9c: 03e38e33 mul t3,t2,t5 -80011fa0: 01051513 slli a0,a0,0x10 -80011fa4: 00d50533 add a0,a0,a3 -80011fa8: 03e60733 mul a4,a2,t5 -80011fac: 02c487b3 mul a5,s1,a2 -80011fb0: 01075693 srli a3,a4,0x10 -80011fb4: 01c787b3 add a5,a5,t3 -80011fb8: 00f687b3 add a5,a3,a5 -80011fbc: 02748ab3 mul s5,s1,t2 -80011fc0: 01c7f463 bgeu a5,t3,80011fc8 <__multf3+0x80c> -80011fc4: 016a8ab3 add s5,s5,s6 -80011fc8: 000106b7 lui a3,0x10 -80011fcc: fff68e13 addi t3,a3,-1 # ffff <_start-0x7fff0001> -80011fd0: 01c7f6b3 and a3,a5,t3 -80011fd4: 0107db93 srli s7,a5,0x10 -80011fd8: 011d07b3 add a5,s10,a7 -80011fdc: 01c77733 and a4,a4,t3 -80011fe0: 0117b8b3 sltu a7,a5,a7 -80011fe4: 01ba0a33 add s4,s4,s11 -80011fe8: 01069693 slli a3,a3,0x10 -80011fec: 00e686b3 add a3,a3,a4 -80011ff0: 011a0d33 add s10,s4,a7 -80011ff4: 02812703 lw a4,40(sp) -80011ff8: 011d38b3 sltu a7,s10,a7 -80011ffc: 01ba3a33 sltu s4,s4,s11 -80012000: 010787b3 add a5,a5,a6 -80012004: 011a6a33 or s4,s4,a7 -80012008: 02812883 lw a7,40(sp) -8001200c: 0107b833 sltu a6,a5,a6 -80012010: 00ed0b33 add s6,s10,a4 -80012014: 02c12703 lw a4,44(sp) -80012018: 010b0cb3 add s9,s6,a6 -8001201c: 00a787b3 add a5,a5,a0 -80012020: 011b3b33 sltu s6,s6,a7 -80012024: 010cb833 sltu a6,s9,a6 -80012028: 00a7b533 sltu a0,a5,a0 -8001202c: 00ec8733 add a4,s9,a4 -80012030: 010b6b33 or s6,s6,a6 -80012034: 02c12803 lw a6,44(sp) -80012038: 00a70c33 add s8,a4,a0 -8001203c: 015b8bb3 add s7,s7,s5 -80012040: 00d787b3 add a5,a5,a3 -80012044: 00d7b6b3 sltu a3,a5,a3 -80012048: 017c0ab3 add s5,s8,s7 -8001204c: 00da8e33 add t3,s5,a3 -80012050: 01073733 sltu a4,a4,a6 -80012054: 00ac3533 sltu a0,s8,a0 -80012058: 00a76733 or a4,a4,a0 -8001205c: 00de36b3 sltu a3,t3,a3 -80012060: 016a0a33 add s4,s4,s6 -80012064: 017abab3 sltu s5,s5,s7 -80012068: 00ea0a33 add s4,s4,a4 -8001206c: 00daeab3 or s5,s5,a3 -80012070: 015a06b3 add a3,s4,s5 -80012074: 02ce8833 mul a6,t4,a2 -80012078: 06f12623 sw a5,108(sp) -8001207c: 03d38a33 mul s4,t2,t4 -80012080: 01085513 srli a0,a6,0x10 -80012084: 02c40733 mul a4,s0,a2 -80012088: 01470733 add a4,a4,s4 -8001208c: 00e50733 add a4,a0,a4 -80012090: 027408b3 mul a7,s0,t2 -80012094: 01477663 bgeu a4,s4,800120a0 <__multf3+0x8e4> -80012098: 00010537 lui a0,0x10 -8001209c: 00a888b3 add a7,a7,a0 -800120a0: 00010a37 lui s4,0x10 -800120a4: 01075513 srli a0,a4,0x10 -800120a8: fffa0a93 addi s5,s4,-1 # ffff <_start-0x7fff0001> -800120ac: 011508b3 add a7,a0,a7 -800120b0: 01577533 and a0,a4,s5 -800120b4: 01587833 and a6,a6,s5 -800120b8: 01051513 slli a0,a0,0x10 -800120bc: 02690ab3 mul s5,s2,t1 -800120c0: 01050533 add a0,a0,a6 -800120c4: 02b30833 mul a6,t1,a1 -800120c8: 02b285b3 mul a1,t0,a1 -800120cc: 01085713 srli a4,a6,0x10 -800120d0: 015585b3 add a1,a1,s5 -800120d4: 00b70733 add a4,a4,a1 -800120d8: 02590933 mul s2,s2,t0 -800120dc: 01577463 bgeu a4,s5,800120e4 <__multf3+0x928> -800120e0: 01490933 add s2,s2,s4 -800120e4: 00010ab7 lui s5,0x10 -800120e8: 01075593 srli a1,a4,0x10 -800120ec: fffa8a13 addi s4,s5,-1 # ffff <_start-0x7fff0001> -800120f0: 01487833 and a6,a6,s4 -800120f4: 01258933 add s2,a1,s2 -800120f8: 014775b3 and a1,a4,s4 -800120fc: 01059593 slli a1,a1,0x10 -80012100: 03e98733 mul a4,s3,t5 -80012104: 010585b3 add a1,a1,a6 -80012108: 03ef8f33 mul t5,t6,t5 -8001210c: 01075813 srli a6,a4,0x10 -80012110: 03f48a33 mul s4,s1,t6 -80012114: 033484b3 mul s1,s1,s3 -80012118: 01e484b3 add s1,s1,t5 -8001211c: 009804b3 add s1,a6,s1 -80012120: 01e4f463 bgeu s1,t5,80012128 <__multf3+0x96c> -80012124: 015a0a33 add s4,s4,s5 -80012128: 0104db13 srli s6,s1,0x10 -8001212c: 014b0b33 add s6,s6,s4 -80012130: 00010a37 lui s4,0x10 -80012134: fffa0f13 addi t5,s4,-1 # ffff <_start-0x7fff0001> -80012138: 01e4f833 and a6,s1,t5 -8001213c: 01e77733 and a4,a4,t5 -80012140: 026384b3 mul s1,t2,t1 -80012144: 01081813 slli a6,a6,0x10 -80012148: 00e80833 add a6,a6,a4 -8001214c: 02660f33 mul t5,a2,t1 -80012150: 02c28633 mul a2,t0,a2 -80012154: 010f5713 srli a4,t5,0x10 -80012158: 00960633 add a2,a2,s1 -8001215c: 00c70633 add a2,a4,a2 -80012160: 025383b3 mul t2,t2,t0 -80012164: 00967463 bgeu a2,s1,8001216c <__multf3+0x9b0> -80012168: 014383b3 add t2,t2,s4 -8001216c: 00010a37 lui s4,0x10 -80012170: 01065713 srli a4,a2,0x10 -80012174: fffa0493 addi s1,s4,-1 # ffff <_start-0x7fff0001> -80012178: 007703b3 add t2,a4,t2 -8001217c: 00967733 and a4,a2,s1 -80012180: 009f7f33 and t5,t5,s1 -80012184: 01071713 slli a4,a4,0x10 -80012188: 01e70733 add a4,a4,t5 -8001218c: 03340633 mul a2,s0,s3 -80012190: 033e8f33 mul t5,t4,s3 -80012194: 03df8eb3 mul t4,t6,t4 -80012198: 010f5a93 srli s5,t5,0x10 -8001219c: 01d60633 add a2,a2,t4 -800121a0: 00ca8633 add a2,s5,a2 -800121a4: 03f404b3 mul s1,s0,t6 -800121a8: 01d67463 bgeu a2,t4,800121b0 <__multf3+0x9f4> -800121ac: 014484b3 add s1,s1,s4 -800121b0: 01065c13 srli s8,a2,0x10 -800121b4: 00010cb7 lui s9,0x10 -800121b8: 009c0c33 add s8,s8,s1 -800121bc: 00ae0e33 add t3,t3,a0 -800121c0: fffc8493 addi s1,s9,-1 # ffff <_start-0x7fff0001> -800121c4: 00ae3533 sltu a0,t3,a0 -800121c8: 011686b3 add a3,a3,a7 -800121cc: 00967633 and a2,a2,s1 -800121d0: 00a68db3 add s11,a3,a0 -800121d4: 009f7f33 and t5,t5,s1 -800121d8: 00be0e33 add t3,t3,a1 -800121dc: 01061613 slli a2,a2,0x10 -800121e0: 01e60633 add a2,a2,t5 -800121e4: 00be35b3 sltu a1,t3,a1 -800121e8: 012d8f33 add t5,s11,s2 -800121ec: 010e0e33 add t3,t3,a6 -800121f0: 00bf0d33 add s10,t5,a1 -800121f4: 016d0eb3 add t4,s10,s6 -800121f8: 07c12823 sw t3,112(sp) -800121fc: 010e3e33 sltu t3,t3,a6 -80012200: 01ce8a33 add s4,t4,t3 -80012204: 0116b6b3 sltu a3,a3,a7 -80012208: 00bd35b3 sltu a1,s10,a1 -8001220c: 00adb533 sltu a0,s11,a0 -80012210: 012f3933 sltu s2,t5,s2 -80012214: 00a6e533 or a0,a3,a0 -80012218: 00b96933 or s2,s2,a1 -8001221c: 016ebeb3 sltu t4,t4,s6 -80012220: 01ca3e33 sltu t3,s4,t3 -80012224: 01250533 add a0,a0,s2 -80012228: 01ceeeb3 or t4,t4,t3 -8001222c: 00ea0833 add a6,s4,a4 -80012230: 01d50533 add a0,a0,t4 -80012234: 00e83733 sltu a4,a6,a4 -80012238: 00750533 add a0,a0,t2 -8001223c: 00e506b3 add a3,a0,a4 -80012240: 007533b3 sltu t2,a0,t2 -80012244: 03330533 mul a0,t1,s3 -80012248: 00c80833 add a6,a6,a2 -8001224c: 00e6b733 sltu a4,a3,a4 -80012250: 00c83633 sltu a2,a6,a2 -80012254: 018686b3 add a3,a3,s8 -80012258: 00c685b3 add a1,a3,a2 -8001225c: 0186bc33 sltu s8,a3,s8 -80012260: 00c5b633 sltu a2,a1,a2 -80012264: 07012a23 sw a6,116(sp) -80012268: 00e3e733 or a4,t2,a4 -8001226c: 026f8333 mul t1,t6,t1 -80012270: 01055693 srli a3,a0,0x10 -80012274: 00cc6633 or a2,s8,a2 -80012278: 033289b3 mul s3,t0,s3 -8001227c: 006989b3 add s3,s3,t1 -80012280: 03f28fb3 mul t6,t0,t6 -80012284: 013682b3 add t0,a3,s3 -80012288: 0062f463 bgeu t0,t1,80012290 <__multf3+0xad4> -8001228c: 019f8fb3 add t6,t6,s9 -80012290: 0092f6b3 and a3,t0,s1 -80012294: 01069693 slli a3,a3,0x10 -80012298: 009574b3 and s1,a0,s1 -8001229c: 009684b3 add s1,a3,s1 -800122a0: 0102d293 srli t0,t0,0x10 -800122a4: 009585b3 add a1,a1,s1 -800122a8: 00e282b3 add t0,t0,a4 -800122ac: 01412683 lw a3,20(sp) -800122b0: 02412703 lw a4,36(sp) -800122b4: 0095b4b3 sltu s1,a1,s1 -800122b8: 00c282b3 add t0,t0,a2 -800122bc: 009282b3 add t0,t0,s1 -800122c0: 01f28fb3 add t6,t0,t6 -800122c4: 00d762b3 or t0,a4,a3 -800122c8: 01812703 lw a4,24(sp) -800122cc: 00d79793 slli a5,a5,0xd -800122d0: 06b12c23 sw a1,120(sp) -800122d4: 005762b3 or t0,a4,t0 -800122d8: 07f12e23 sw t6,124(sp) -800122dc: 0057e7b3 or a5,a5,t0 -800122e0: 06010713 addi a4,sp,96 -800122e4: 07010593 addi a1,sp,112 -800122e8: 00c72683 lw a3,12(a4) -800122ec: 01072603 lw a2,16(a4) -800122f0: 00470713 addi a4,a4,4 -800122f4: 0136d693 srli a3,a3,0x13 -800122f8: 00d61613 slli a2,a2,0xd -800122fc: 00c6e6b3 or a3,a3,a2 -80012300: fed72e23 sw a3,-4(a4) -80012304: fee592e3 bne a1,a4,800122e8 <__multf3+0xb2c> -80012308: 06012703 lw a4,96(sp) -8001230c: 06812683 lw a3,104(sp) -80012310: 00f037b3 snez a5,a5 -80012314: 00e7e7b3 or a5,a5,a4 -80012318: 04d12c23 sw a3,88(sp) -8001231c: 06c12703 lw a4,108(sp) -80012320: 06412683 lw a3,100(sp) -80012324: 04f12823 sw a5,80(sp) -80012328: 04e12e23 sw a4,92(sp) -8001232c: 04d12a23 sw a3,84(sp) -80012330: 00b71693 slli a3,a4,0xb -80012334: 2206d863 bgez a3,80012564 <__multf3+0xda8> -80012338: 01f79793 slli a5,a5,0x1f -8001233c: 05010713 addi a4,sp,80 -80012340: 05c10593 addi a1,sp,92 -80012344: 00072683 lw a3,0(a4) -80012348: 00472603 lw a2,4(a4) -8001234c: 00470713 addi a4,a4,4 -80012350: 0016d693 srli a3,a3,0x1 -80012354: 01f61613 slli a2,a2,0x1f -80012358: 00c6e6b3 or a3,a3,a2 -8001235c: fed72e23 sw a3,-4(a4) -80012360: fee592e3 bne a1,a4,80012344 <__multf3+0xb88> -80012364: 05c12703 lw a4,92(sp) -80012368: 00f037b3 snez a5,a5 -8001236c: 00175713 srli a4,a4,0x1 -80012370: 04e12e23 sw a4,92(sp) -80012374: 05012703 lw a4,80(sp) -80012378: 00f767b3 or a5,a4,a5 -8001237c: 04f12823 sw a5,80(sp) -80012380: 01c12703 lw a4,28(sp) -80012384: 000047b7 lui a5,0x4 -80012388: fff78793 addi a5,a5,-1 # 3fff <_start-0x7fffc001> -8001238c: 00f707b3 add a5,a4,a5 -80012390: 1ef05c63 blez a5,80012588 <__multf3+0xdcc> -80012394: 05012703 lw a4,80(sp) -80012398: 00777693 andi a3,a4,7 -8001239c: 04068463 beqz a3,800123e4 <__multf3+0xc28> -800123a0: 00f77693 andi a3,a4,15 -800123a4: 00400613 li a2,4 -800123a8: 02c68e63 beq a3,a2,800123e4 <__multf3+0xc28> -800123ac: 05412683 lw a3,84(sp) -800123b0: 00470713 addi a4,a4,4 -800123b4: 04e12823 sw a4,80(sp) -800123b8: 00473713 sltiu a4,a4,4 -800123bc: 00d706b3 add a3,a4,a3 -800123c0: 00e6b733 sltu a4,a3,a4 -800123c4: 04d12a23 sw a3,84(sp) -800123c8: 05812683 lw a3,88(sp) -800123cc: 00d706b3 add a3,a4,a3 -800123d0: 04d12c23 sw a3,88(sp) -800123d4: 00e6b6b3 sltu a3,a3,a4 -800123d8: 05c12703 lw a4,92(sp) -800123dc: 00e686b3 add a3,a3,a4 -800123e0: 04d12e23 sw a3,92(sp) -800123e4: 05c12703 lw a4,92(sp) -800123e8: 00b71693 slli a3,a4,0xb -800123ec: 0206d063 bgez a3,8001240c <__multf3+0xc50> -800123f0: fff007b7 lui a5,0xfff00 -800123f4: fff78793 addi a5,a5,-1 # ffefffff <__BSS_END__+0x7fee9287> -800123f8: 00f77733 and a4,a4,a5 -800123fc: 04e12e23 sw a4,92(sp) -80012400: 01c12703 lw a4,28(sp) -80012404: 000047b7 lui a5,0x4 -80012408: 00f707b3 add a5,a4,a5 -8001240c: 05010713 addi a4,sp,80 -80012410: 05c10593 addi a1,sp,92 -80012414: 00072683 lw a3,0(a4) -80012418: 00472603 lw a2,4(a4) -8001241c: 00470713 addi a4,a4,4 -80012420: 0036d693 srli a3,a3,0x3 -80012424: 01d61613 slli a2,a2,0x1d -80012428: 00c6e6b3 or a3,a3,a2 -8001242c: fed72e23 sw a3,-4(a4) -80012430: feb712e3 bne a4,a1,80012414 <__multf3+0xc58> -80012434: 00008737 lui a4,0x8 -80012438: ffe70693 addi a3,a4,-2 # 7ffe <_start-0x7fff8002> -8001243c: 12f6ca63 blt a3,a5,80012570 <__multf3+0xdb4> -80012440: 05c12703 lw a4,92(sp) -80012444: 00375713 srli a4,a4,0x3 -80012448: 04e12e23 sw a4,92(sp) -8001244c: 05c12703 lw a4,92(sp) -80012450: 01179793 slli a5,a5,0x11 -80012454: 800106b7 lui a3,0x80010 -80012458: 06e11623 sh a4,108(sp) -8001245c: 06c12703 lw a4,108(sp) -80012460: fff68693 addi a3,a3,-1 # 8000ffff <__BSS_END__+0xffff9287> -80012464: 0117d793 srli a5,a5,0x11 -80012468: 00d77733 and a4,a4,a3 -8001246c: 01079793 slli a5,a5,0x10 -80012470: 00f767b3 or a5,a4,a5 -80012474: 01012703 lw a4,16(sp) -80012478: 00179793 slli a5,a5,0x1 -8001247c: 0017d793 srli a5,a5,0x1 -80012480: 01f71713 slli a4,a4,0x1f -80012484: 00c12683 lw a3,12(sp) -80012488: 00e7e7b3 or a5,a5,a4 -8001248c: 05012703 lw a4,80(sp) -80012490: 0bc12083 lw ra,188(sp) -80012494: 0b812403 lw s0,184(sp) -80012498: 00e6a023 sw a4,0(a3) -8001249c: 05412703 lw a4,84(sp) -800124a0: 00f6a623 sw a5,12(a3) -800124a4: 0b412483 lw s1,180(sp) -800124a8: 00e6a223 sw a4,4(a3) -800124ac: 05812703 lw a4,88(sp) -800124b0: 0b012903 lw s2,176(sp) -800124b4: 0ac12983 lw s3,172(sp) -800124b8: 00e6a423 sw a4,8(a3) -800124bc: 0a812a03 lw s4,168(sp) -800124c0: 0a412a83 lw s5,164(sp) -800124c4: 0a012b03 lw s6,160(sp) -800124c8: 09c12b83 lw s7,156(sp) -800124cc: 09812c03 lw s8,152(sp) -800124d0: 09412c83 lw s9,148(sp) -800124d4: 09012d03 lw s10,144(sp) -800124d8: 08c12d83 lw s11,140(sp) -800124dc: 00068513 mv a0,a3 -800124e0: 0c010113 addi sp,sp,192 -800124e4: 00008067 ret -800124e8: 01312823 sw s3,16(sp) -800124ec: 03012783 lw a5,48(sp) -800124f0: 04f12823 sw a5,80(sp) -800124f4: 03412783 lw a5,52(sp) -800124f8: 04f12a23 sw a5,84(sp) -800124fc: 03812783 lw a5,56(sp) -80012500: 04f12c23 sw a5,88(sp) -80012504: 03c12783 lw a5,60(sp) -80012508: 04f12e23 sw a5,92(sp) -8001250c: 00200793 li a5,2 -80012510: 26fb8c63 beq s7,a5,80012788 <__multf3+0xfcc> -80012514: 00300793 li a5,3 -80012518: 28fb8663 beq s7,a5,800127a4 <__multf3+0xfe8> -8001251c: 00100793 li a5,1 -80012520: e6fb90e3 bne s7,a5,80012380 <__multf3+0xbc4> -80012524: 04012e23 sw zero,92(sp) -80012528: 04012c23 sw zero,88(sp) -8001252c: 04012a23 sw zero,84(sp) -80012530: 04012823 sw zero,80(sp) -80012534: 2140006f j 80012748 <__multf3+0xf8c> -80012538: 01212823 sw s2,16(sp) -8001253c: 04012783 lw a5,64(sp) -80012540: 00070b93 mv s7,a4 -80012544: 04f12823 sw a5,80(sp) -80012548: 04412783 lw a5,68(sp) -8001254c: 04f12a23 sw a5,84(sp) -80012550: 04812783 lw a5,72(sp) -80012554: 04f12c23 sw a5,88(sp) -80012558: 04c12783 lw a5,76(sp) -8001255c: 04f12e23 sw a5,92(sp) -80012560: fadff06f j 8001250c <__multf3+0xd50> -80012564: 02012783 lw a5,32(sp) -80012568: 00f12e23 sw a5,28(sp) -8001256c: e15ff06f j 80012380 <__multf3+0xbc4> -80012570: 04012e23 sw zero,92(sp) -80012574: 04012c23 sw zero,88(sp) -80012578: 04012a23 sw zero,84(sp) -8001257c: 04012823 sw zero,80(sp) -80012580: fff70793 addi a5,a4,-1 -80012584: ec9ff06f j 8001244c <__multf3+0xc90> -80012588: 00100713 li a4,1 -8001258c: 40f707b3 sub a5,a4,a5 -80012590: 07400713 li a4,116 -80012594: 1af74e63 blt a4,a5,80012750 <__multf3+0xf94> -80012598: 4057d893 srai a7,a5,0x5 -8001259c: 00000713 li a4,0 -800125a0: 01f7f793 andi a5,a5,31 -800125a4: 00000693 li a3,0 -800125a8: 00269613 slli a2,a3,0x2 -800125ac: 03169a63 bne a3,a7,800125e0 <__multf3+0xe24> -800125b0: 04079463 bnez a5,800125f8 <__multf3+0xe3c> -800125b4: 00300513 li a0,3 -800125b8: 05010593 addi a1,sp,80 -800125bc: 40d506b3 sub a3,a0,a3 -800125c0: 00c58533 add a0,a1,a2 -800125c4: 00052503 lw a0,0(a0) # 10000 <_start-0x7fff0000> -800125c8: 00178793 addi a5,a5,1 # 4001 <_start-0x7fffbfff> -800125cc: 00458593 addi a1,a1,4 -800125d0: fea5ae23 sw a0,-4(a1) -800125d4: fef6d6e3 bge a3,a5,800125c0 <__multf3+0xe04> -800125d8: 00400613 li a2,4 -800125dc: 0b80006f j 80012694 <__multf3+0xed8> -800125e0: 05010593 addi a1,sp,80 -800125e4: 00c58633 add a2,a1,a2 -800125e8: 00062603 lw a2,0(a2) -800125ec: 00168693 addi a3,a3,1 -800125f0: 00c76733 or a4,a4,a2 -800125f4: fb5ff06f j 800125a8 <__multf3+0xdec> -800125f8: 08010693 addi a3,sp,128 -800125fc: 00c686b3 add a3,a3,a2 -80012600: fd06a683 lw a3,-48(a3) -80012604: 02000813 li a6,32 -80012608: 40f80833 sub a6,a6,a5 -8001260c: 010696b3 sll a3,a3,a6 -80012610: 00d76733 or a4,a4,a3 -80012614: 05010693 addi a3,sp,80 -80012618: 00c68633 add a2,a3,a2 -8001261c: 00300693 li a3,3 -80012620: 00000513 li a0,0 -80012624: 411686b3 sub a3,a3,a7 -80012628: 00460613 addi a2,a2,4 -8001262c: 02d54463 blt a0,a3,80012654 <__multf3+0xe98> -80012630: 08010613 addi a2,sp,128 -80012634: 00269693 slli a3,a3,0x2 -80012638: 00d606b3 add a3,a2,a3 -8001263c: 05c12603 lw a2,92(sp) -80012640: 00f657b3 srl a5,a2,a5 -80012644: fcf6a823 sw a5,-48(a3) -80012648: 00400793 li a5,4 -8001264c: 411787b3 sub a5,a5,a7 -80012650: f89ff06f j 800125d8 <__multf3+0xe1c> -80012654: 00251313 slli t1,a0,0x2 -80012658: 05010593 addi a1,sp,80 -8001265c: 00658333 add t1,a1,t1 -80012660: 00062e03 lw t3,0(a2) -80012664: ffc62583 lw a1,-4(a2) -80012668: 00150513 addi a0,a0,1 -8001266c: 010e1e33 sll t3,t3,a6 -80012670: 00f5d5b3 srl a1,a1,a5 -80012674: 01c5e5b3 or a1,a1,t3 -80012678: 00b32023 sw a1,0(t1) # 10000 <_start-0x7fff0000> -8001267c: fadff06f j 80012628 <__multf3+0xe6c> -80012680: 00279693 slli a3,a5,0x2 -80012684: 05010593 addi a1,sp,80 -80012688: 00d586b3 add a3,a1,a3 -8001268c: 0006a023 sw zero,0(a3) -80012690: 00178793 addi a5,a5,1 -80012694: fec796e3 bne a5,a2,80012680 <__multf3+0xec4> -80012698: 05012683 lw a3,80(sp) -8001269c: 00e03733 snez a4,a4 -800126a0: 00d76733 or a4,a4,a3 -800126a4: 04e12823 sw a4,80(sp) -800126a8: 00777693 andi a3,a4,7 -800126ac: 04068263 beqz a3,800126f0 <__multf3+0xf34> -800126b0: 00f77693 andi a3,a4,15 -800126b4: 02f68e63 beq a3,a5,800126f0 <__multf3+0xf34> -800126b8: 05412783 lw a5,84(sp) -800126bc: 00470713 addi a4,a4,4 -800126c0: 04e12823 sw a4,80(sp) -800126c4: 00473713 sltiu a4,a4,4 -800126c8: 00f707b3 add a5,a4,a5 -800126cc: 00e7b733 sltu a4,a5,a4 -800126d0: 04f12a23 sw a5,84(sp) -800126d4: 05812783 lw a5,88(sp) -800126d8: 00f707b3 add a5,a4,a5 -800126dc: 04f12c23 sw a5,88(sp) -800126e0: 00e7b7b3 sltu a5,a5,a4 -800126e4: 05c12703 lw a4,92(sp) -800126e8: 00e787b3 add a5,a5,a4 -800126ec: 04f12e23 sw a5,92(sp) -800126f0: 05c12783 lw a5,92(sp) -800126f4: 00c79713 slli a4,a5,0xc -800126f8: 00075e63 bgez a4,80012714 <__multf3+0xf58> -800126fc: 04012e23 sw zero,92(sp) -80012700: 04012c23 sw zero,88(sp) -80012704: 04012a23 sw zero,84(sp) -80012708: 04012823 sw zero,80(sp) -8001270c: 00100793 li a5,1 -80012710: d3dff06f j 8001244c <__multf3+0xc90> -80012714: 05010793 addi a5,sp,80 -80012718: 05c10613 addi a2,sp,92 -8001271c: 0007a703 lw a4,0(a5) -80012720: 0047a683 lw a3,4(a5) -80012724: 00478793 addi a5,a5,4 -80012728: 00375713 srli a4,a4,0x3 -8001272c: 01d69693 slli a3,a3,0x1d -80012730: 00d76733 or a4,a4,a3 -80012734: fee7ae23 sw a4,-4(a5) -80012738: fef612e3 bne a2,a5,8001271c <__multf3+0xf60> -8001273c: 05c12783 lw a5,92(sp) -80012740: 0037d793 srli a5,a5,0x3 -80012744: 04f12e23 sw a5,92(sp) -80012748: 00000793 li a5,0 -8001274c: d01ff06f j 8001244c <__multf3+0xc90> -80012750: 05412783 lw a5,84(sp) -80012754: 05012703 lw a4,80(sp) -80012758: 00f76733 or a4,a4,a5 -8001275c: 05812783 lw a5,88(sp) -80012760: 00f76733 or a4,a4,a5 -80012764: 05c12783 lw a5,92(sp) -80012768: 00f76733 or a4,a4,a5 -8001276c: 00000793 li a5,0 -80012770: cc070ee3 beqz a4,8001244c <__multf3+0xc90> -80012774: 04012e23 sw zero,92(sp) -80012778: 04012c23 sw zero,88(sp) -8001277c: 04012a23 sw zero,84(sp) -80012780: 04012823 sw zero,80(sp) -80012784: cc9ff06f j 8001244c <__multf3+0xc90> -80012788: 000087b7 lui a5,0x8 -8001278c: 04012e23 sw zero,92(sp) -80012790: 04012c23 sw zero,88(sp) -80012794: 04012a23 sw zero,84(sp) -80012798: 04012823 sw zero,80(sp) -8001279c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800127a0: cadff06f j 8001244c <__multf3+0xc90> -800127a4: 000087b7 lui a5,0x8 -800127a8: 04f12e23 sw a5,92(sp) -800127ac: 04012c23 sw zero,88(sp) -800127b0: 04012a23 sw zero,84(sp) -800127b4: 04012823 sw zero,80(sp) -800127b8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800127bc: 00012823 sw zero,16(sp) -800127c0: c8dff06f j 8001244c <__multf3+0xc90> - -800127c4 <__subtf3>: -800127c4: fa010113 addi sp,sp,-96 -800127c8: 0085a783 lw a5,8(a1) -800127cc: 05212823 sw s2,80(sp) -800127d0: 00c5a903 lw s2,12(a1) -800127d4: 0045a703 lw a4,4(a1) -800127d8: 04912a23 sw s1,84(sp) -800127dc: 00050493 mv s1,a0 -800127e0: 0005a503 lw a0,0(a1) -800127e4: 02f12c23 sw a5,56(sp) -800127e8: 00f12c23 sw a5,24(sp) -800127ec: 00062303 lw t1,0(a2) -800127f0: 01091793 slli a5,s2,0x10 -800127f4: 00462883 lw a7,4(a2) -800127f8: 00862683 lw a3,8(a2) -800127fc: 00c62803 lw a6,12(a2) -80012800: 04812c23 sw s0,88(sp) -80012804: 0107d793 srli a5,a5,0x10 -80012808: 00191413 slli s0,s2,0x1 -8001280c: 03212e23 sw s2,60(sp) -80012810: 04112e23 sw ra,92(sp) -80012814: 05312623 sw s3,76(sp) -80012818: 05412423 sw s4,72(sp) -8001281c: 05512223 sw s5,68(sp) -80012820: 02a12823 sw a0,48(sp) -80012824: 02e12a23 sw a4,52(sp) -80012828: 00a12823 sw a0,16(sp) -8001282c: 00e12a23 sw a4,20(sp) -80012830: 00f12e23 sw a5,28(sp) -80012834: 01145413 srli s0,s0,0x11 -80012838: 01f95913 srli s2,s2,0x1f -8001283c: 01010e13 addi t3,sp,16 -80012840: 01c10593 addi a1,sp,28 -80012844: 0005a783 lw a5,0(a1) -80012848: ffc5a703 lw a4,-4(a1) -8001284c: ffc58593 addi a1,a1,-4 -80012850: 00379793 slli a5,a5,0x3 -80012854: 01d75713 srli a4,a4,0x1d -80012858: 00e7e7b3 or a5,a5,a4 -8001285c: 00f5a223 sw a5,4(a1) -80012860: febe12e3 bne t3,a1,80012844 <__subtf3+0x80> -80012864: 01012703 lw a4,16(sp) -80012868: 01081793 slli a5,a6,0x10 -8001286c: 00181613 slli a2,a6,0x1 -80012870: 00371713 slli a4,a4,0x3 -80012874: 0107d793 srli a5,a5,0x10 -80012878: 02612823 sw t1,48(sp) -8001287c: 03112a23 sw a7,52(sp) -80012880: 03012e23 sw a6,60(sp) -80012884: 02612023 sw t1,32(sp) -80012888: 03112223 sw a7,36(sp) -8001288c: 00e12823 sw a4,16(sp) -80012890: 02d12c23 sw a3,56(sp) -80012894: 02d12423 sw a3,40(sp) -80012898: 02f12623 sw a5,44(sp) -8001289c: 01165613 srli a2,a2,0x11 -800128a0: 01f85813 srli a6,a6,0x1f -800128a4: 02010313 addi t1,sp,32 -800128a8: 02c10893 addi a7,sp,44 -800128ac: 0008a783 lw a5,0(a7) -800128b0: ffc8a683 lw a3,-4(a7) -800128b4: ffc88893 addi a7,a7,-4 -800128b8: 00379793 slli a5,a5,0x3 -800128bc: 01d6d693 srli a3,a3,0x1d -800128c0: 00d7e7b3 or a5,a5,a3 -800128c4: 00f8a223 sw a5,4(a7) -800128c8: ff1312e3 bne t1,a7,800128ac <__subtf3+0xe8> -800128cc: 02012783 lw a5,32(sp) -800128d0: 000086b7 lui a3,0x8 -800128d4: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> -800128d8: 00379793 slli a5,a5,0x3 -800128dc: 02f12023 sw a5,32(sp) -800128e0: 02d61063 bne a2,a3,80012900 <__subtf3+0x13c> -800128e4: 02812503 lw a0,40(sp) -800128e8: 02412683 lw a3,36(sp) -800128ec: 00a6e6b3 or a3,a3,a0 -800128f0: 02c12503 lw a0,44(sp) -800128f4: 00a6e6b3 or a3,a3,a0 -800128f8: 00f6e6b3 or a3,a3,a5 -800128fc: 00069463 bnez a3,80012904 <__subtf3+0x140> -80012900: 00184813 xori a6,a6,1 -80012904: 40c40533 sub a0,s0,a2 -80012908: 13281ce3 bne a6,s2,80013240 <__subtf3+0xa7c> -8001290c: 30a05463 blez a0,80012c14 <__subtf3+0x450> -80012910: 0c061663 bnez a2,800129dc <__subtf3+0x218> -80012914: 02412583 lw a1,36(sp) -80012918: 02812603 lw a2,40(sp) -8001291c: 02c12803 lw a6,44(sp) -80012920: 00c5e6b3 or a3,a1,a2 -80012924: 0106e6b3 or a3,a3,a6 -80012928: 00f6e6b3 or a3,a3,a5 -8001292c: 02069063 bnez a3,8001294c <__subtf3+0x188> -80012930: 01412783 lw a5,20(sp) -80012934: 02e12823 sw a4,48(sp) -80012938: 02f12a23 sw a5,52(sp) -8001293c: 01812783 lw a5,24(sp) -80012940: 02f12c23 sw a5,56(sp) -80012944: 01c12783 lw a5,28(sp) -80012948: 30c0006f j 80012c54 <__subtf3+0x490> -8001294c: fff50693 addi a3,a0,-1 -80012950: 06069063 bnez a3,800129b0 <__subtf3+0x1ec> -80012954: 01412683 lw a3,20(sp) -80012958: 00f707b3 add a5,a4,a5 -8001295c: 00e7b733 sltu a4,a5,a4 -80012960: 00d585b3 add a1,a1,a3 -80012964: 02f12823 sw a5,48(sp) -80012968: 00e587b3 add a5,a1,a4 -8001296c: 00e7b733 sltu a4,a5,a4 -80012970: 02f12a23 sw a5,52(sp) -80012974: 01812783 lw a5,24(sp) -80012978: 00d5b6b3 sltu a3,a1,a3 -8001297c: 00e6e733 or a4,a3,a4 -80012980: 00f606b3 add a3,a2,a5 -80012984: 00e68633 add a2,a3,a4 -80012988: 00e63733 sltu a4,a2,a4 -8001298c: 00f6b7b3 sltu a5,a3,a5 -80012990: 00e7e7b3 or a5,a5,a4 -80012994: 01c12703 lw a4,28(sp) -80012998: 02c12c23 sw a2,56(sp) -8001299c: 00e80833 add a6,a6,a4 -800129a0: 010787b3 add a5,a5,a6 -800129a4: 02f12e23 sw a5,60(sp) -800129a8: 00100413 li s0,1 -800129ac: 1dc0006f j 80012b88 <__subtf3+0x3c4> -800129b0: 000087b7 lui a5,0x8 -800129b4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800129b8: f6f50ce3 beq a0,a5,80012930 <__subtf3+0x16c> -800129bc: 07400793 li a5,116 -800129c0: 06d7d263 bge a5,a3,80012a24 <__subtf3+0x260> -800129c4: 00100793 li a5,1 -800129c8: 02012623 sw zero,44(sp) -800129cc: 02012423 sw zero,40(sp) -800129d0: 02012223 sw zero,36(sp) -800129d4: 02f12023 sw a5,32(sp) -800129d8: 1480006f j 80012b20 <__subtf3+0x35c> -800129dc: 000087b7 lui a5,0x8 -800129e0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800129e4: 02f41263 bne s0,a5,80012a08 <__subtf3+0x244> -800129e8: 01412783 lw a5,20(sp) -800129ec: 02e12823 sw a4,48(sp) -800129f0: 02f12a23 sw a5,52(sp) -800129f4: 01812783 lw a5,24(sp) -800129f8: 02f12c23 sw a5,56(sp) -800129fc: 01c12783 lw a5,28(sp) -80012a00: 02f12e23 sw a5,60(sp) -80012a04: 2580006f j 80012c5c <__subtf3+0x498> -80012a08: 02c12783 lw a5,44(sp) -80012a0c: 00080737 lui a4,0x80 -80012a10: 00e7e7b3 or a5,a5,a4 -80012a14: 02f12623 sw a5,44(sp) -80012a18: 07400793 li a5,116 -80012a1c: faa7c4e3 blt a5,a0,800129c4 <__subtf3+0x200> -80012a20: 00050693 mv a3,a0 -80012a24: 4056de13 srai t3,a3,0x5 -80012a28: 01f6f793 andi a5,a3,31 -80012a2c: 00000613 li a2,0 -80012a30: 00000713 li a4,0 -80012a34: 00271693 slli a3,a4,0x2 -80012a38: 03c71863 bne a4,t3,80012a68 <__subtf3+0x2a4> -80012a3c: 04079063 bnez a5,80012a7c <__subtf3+0x2b8> -80012a40: 00300593 li a1,3 -80012a44: 40e58733 sub a4,a1,a4 -80012a48: 00d885b3 add a1,a7,a3 -80012a4c: 0005a583 lw a1,0(a1) -80012a50: 00178793 addi a5,a5,1 -80012a54: 00488893 addi a7,a7,4 -80012a58: feb8ae23 sw a1,-4(a7) -80012a5c: fef756e3 bge a4,a5,80012a48 <__subtf3+0x284> -80012a60: 00400693 li a3,4 -80012a64: 0a80006f j 80012b0c <__subtf3+0x348> -80012a68: 00d306b3 add a3,t1,a3 -80012a6c: 0006a683 lw a3,0(a3) -80012a70: 00170713 addi a4,a4,1 # 80001 <_start-0x7ff7ffff> -80012a74: 00d66633 or a2,a2,a3 -80012a78: fbdff06f j 80012a34 <__subtf3+0x270> -80012a7c: 04010713 addi a4,sp,64 -80012a80: 00d70733 add a4,a4,a3 -80012a84: fe072703 lw a4,-32(a4) -80012a88: 02000813 li a6,32 -80012a8c: 40f80833 sub a6,a6,a5 -80012a90: 01071733 sll a4,a4,a6 -80012a94: 00e66633 or a2,a2,a4 -80012a98: 00300713 li a4,3 -80012a9c: 00d306b3 add a3,t1,a3 -80012aa0: 00000513 li a0,0 -80012aa4: 41c70733 sub a4,a4,t3 -80012aa8: 00468693 addi a3,a3,4 -80012aac: 02e54463 blt a0,a4,80012ad4 <__subtf3+0x310> -80012ab0: 04010693 addi a3,sp,64 -80012ab4: 00271713 slli a4,a4,0x2 -80012ab8: 00e68733 add a4,a3,a4 -80012abc: 02c12683 lw a3,44(sp) -80012ac0: 00f6d7b3 srl a5,a3,a5 -80012ac4: fef72023 sw a5,-32(a4) -80012ac8: 00400793 li a5,4 -80012acc: 41c787b3 sub a5,a5,t3 -80012ad0: f91ff06f j 80012a60 <__subtf3+0x29c> -80012ad4: ffc6a583 lw a1,-4(a3) -80012ad8: 0006ae83 lw t4,0(a3) -80012adc: 00251893 slli a7,a0,0x2 -80012ae0: 00f5d5b3 srl a1,a1,a5 -80012ae4: 010e9eb3 sll t4,t4,a6 -80012ae8: 011308b3 add a7,t1,a7 -80012aec: 01d5e5b3 or a1,a1,t4 -80012af0: 00b8a023 sw a1,0(a7) -80012af4: 00150513 addi a0,a0,1 -80012af8: fb1ff06f j 80012aa8 <__subtf3+0x2e4> -80012afc: 00279713 slli a4,a5,0x2 -80012b00: 00e30733 add a4,t1,a4 -80012b04: 00072023 sw zero,0(a4) -80012b08: 00178793 addi a5,a5,1 -80012b0c: fed798e3 bne a5,a3,80012afc <__subtf3+0x338> -80012b10: 02012783 lw a5,32(sp) -80012b14: 00c03633 snez a2,a2 -80012b18: 00c7e633 or a2,a5,a2 -80012b1c: 02c12023 sw a2,32(sp) -80012b20: 01012683 lw a3,16(sp) -80012b24: 02012783 lw a5,32(sp) -80012b28: 01412703 lw a4,20(sp) -80012b2c: 02812583 lw a1,40(sp) -80012b30: 00f687b3 add a5,a3,a5 -80012b34: 00d7b6b3 sltu a3,a5,a3 -80012b38: 02f12823 sw a5,48(sp) -80012b3c: 02412783 lw a5,36(sp) -80012b40: 02c12503 lw a0,44(sp) -80012b44: 00f707b3 add a5,a4,a5 -80012b48: 00d78633 add a2,a5,a3 -80012b4c: 00e7b733 sltu a4,a5,a4 -80012b50: 00d637b3 sltu a5,a2,a3 -80012b54: 00f767b3 or a5,a4,a5 -80012b58: 01812703 lw a4,24(sp) -80012b5c: 01c12683 lw a3,28(sp) -80012b60: 02c12a23 sw a2,52(sp) -80012b64: 00b705b3 add a1,a4,a1 -80012b68: 00f58633 add a2,a1,a5 -80012b6c: 00e5b733 sltu a4,a1,a4 -80012b70: 00f637b3 sltu a5,a2,a5 -80012b74: 00a686b3 add a3,a3,a0 -80012b78: 00f76733 or a4,a4,a5 -80012b7c: 00e68733 add a4,a3,a4 -80012b80: 02c12c23 sw a2,56(sp) -80012b84: 02e12e23 sw a4,60(sp) -80012b88: 03c12783 lw a5,60(sp) -80012b8c: 00c79713 slli a4,a5,0xc -80012b90: 0c075663 bgez a4,80012c5c <__subtf3+0x498> -80012b94: fff80737 lui a4,0xfff80 -80012b98: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff69287> -80012b9c: 00e7f7b3 and a5,a5,a4 -80012ba0: 02f12e23 sw a5,60(sp) -80012ba4: 03012783 lw a5,48(sp) -80012ba8: 00140413 addi s0,s0,1 # 80001 <_start-0x7ff7ffff> -80012bac: 03c10593 addi a1,sp,60 -80012bb0: 01f79713 slli a4,a5,0x1f -80012bb4: 03010793 addi a5,sp,48 -80012bb8: 0007a683 lw a3,0(a5) -80012bbc: 0047a603 lw a2,4(a5) -80012bc0: 00478793 addi a5,a5,4 -80012bc4: 0016d693 srli a3,a3,0x1 -80012bc8: 01f61613 slli a2,a2,0x1f -80012bcc: 00c6e6b3 or a3,a3,a2 -80012bd0: fed7ae23 sw a3,-4(a5) -80012bd4: fef592e3 bne a1,a5,80012bb8 <__subtf3+0x3f4> -80012bd8: 03c12783 lw a5,60(sp) -80012bdc: 0017d793 srli a5,a5,0x1 -80012be0: 02f12e23 sw a5,60(sp) -80012be4: 00e037b3 snez a5,a4 -80012be8: 03012703 lw a4,48(sp) -80012bec: 00f767b3 or a5,a4,a5 -80012bf0: 02f12823 sw a5,48(sp) -80012bf4: 000087b7 lui a5,0x8 -80012bf8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012bfc: 06f41063 bne s0,a5,80012c5c <__subtf3+0x498> -80012c00: 02012e23 sw zero,60(sp) -80012c04: 02012c23 sw zero,56(sp) -80012c08: 02012a23 sw zero,52(sp) -80012c0c: 02012823 sw zero,48(sp) -80012c10: 04c0006f j 80012c5c <__subtf3+0x498> -80012c14: 40050863 beqz a0,80013024 <__subtf3+0x860> -80012c18: 40860533 sub a0,a2,s0 -80012c1c: 22041c63 bnez s0,80012e54 <__subtf3+0x690> -80012c20: 01412883 lw a7,20(sp) -80012c24: 01812803 lw a6,24(sp) -80012c28: 01c12303 lw t1,28(sp) -80012c2c: 0108e6b3 or a3,a7,a6 -80012c30: 0066e6b3 or a3,a3,t1 -80012c34: 00e6e6b3 or a3,a3,a4 -80012c38: 18069863 bnez a3,80012dc8 <__subtf3+0x604> -80012c3c: 02f12823 sw a5,48(sp) -80012c40: 02412783 lw a5,36(sp) -80012c44: 02f12a23 sw a5,52(sp) -80012c48: 02812783 lw a5,40(sp) -80012c4c: 02f12c23 sw a5,56(sp) -80012c50: 02c12783 lw a5,44(sp) -80012c54: 02f12e23 sw a5,60(sp) -80012c58: 00050413 mv s0,a0 -80012c5c: 03012783 lw a5,48(sp) -80012c60: 0077f713 andi a4,a5,7 -80012c64: 04070463 beqz a4,80012cac <__subtf3+0x4e8> -80012c68: 00f7f713 andi a4,a5,15 -80012c6c: 00400693 li a3,4 -80012c70: 02d70e63 beq a4,a3,80012cac <__subtf3+0x4e8> -80012c74: 03412703 lw a4,52(sp) -80012c78: 00478793 addi a5,a5,4 -80012c7c: 02f12823 sw a5,48(sp) -80012c80: 0047b793 sltiu a5,a5,4 -80012c84: 00e78733 add a4,a5,a4 -80012c88: 00f737b3 sltu a5,a4,a5 -80012c8c: 02e12a23 sw a4,52(sp) -80012c90: 03812703 lw a4,56(sp) -80012c94: 00e78733 add a4,a5,a4 -80012c98: 02e12c23 sw a4,56(sp) -80012c9c: 00f73733 sltu a4,a4,a5 -80012ca0: 03c12783 lw a5,60(sp) -80012ca4: 00f70733 add a4,a4,a5 -80012ca8: 02e12e23 sw a4,60(sp) -80012cac: 03c12783 lw a5,60(sp) -80012cb0: 00c79713 slli a4,a5,0xc -80012cb4: 02075463 bgez a4,80012cdc <__subtf3+0x518> -80012cb8: 00008737 lui a4,0x8 -80012cbc: 00140413 addi s0,s0,1 -80012cc0: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80012cc4: 00e41463 bne s0,a4,80012ccc <__subtf3+0x508> -80012cc8: 0080106f j 80013cd0 <__subtf3+0x150c> -80012ccc: fff80737 lui a4,0xfff80 -80012cd0: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff69287> -80012cd4: 00e7f7b3 and a5,a5,a4 -80012cd8: 02f12e23 sw a5,60(sp) -80012cdc: 03010793 addi a5,sp,48 -80012ce0: 03c10613 addi a2,sp,60 -80012ce4: 0007a703 lw a4,0(a5) -80012ce8: 0047a683 lw a3,4(a5) -80012cec: 00478793 addi a5,a5,4 -80012cf0: 00375713 srli a4,a4,0x3 -80012cf4: 01d69693 slli a3,a3,0x1d -80012cf8: 00d76733 or a4,a4,a3 -80012cfc: fee7ae23 sw a4,-4(a5) -80012d00: fef612e3 bne a2,a5,80012ce4 <__subtf3+0x520> -80012d04: 03c12783 lw a5,60(sp) -80012d08: 000086b7 lui a3,0x8 -80012d0c: 0037d713 srli a4,a5,0x3 -80012d10: 02e12e23 sw a4,60(sp) -80012d14: fff68793 addi a5,a3,-1 # 7fff <_start-0x7fff8001> -80012d18: 02f41a63 bne s0,a5,80012d4c <__subtf3+0x588> -80012d1c: 03412603 lw a2,52(sp) -80012d20: 03012783 lw a5,48(sp) -80012d24: 00c7e7b3 or a5,a5,a2 -80012d28: 03812603 lw a2,56(sp) -80012d2c: 00c7e7b3 or a5,a5,a2 -80012d30: 00e7e7b3 or a5,a5,a4 -80012d34: 00078c63 beqz a5,80012d4c <__subtf3+0x588> -80012d38: 02d12e23 sw a3,60(sp) -80012d3c: 02012c23 sw zero,56(sp) -80012d40: 02012a23 sw zero,52(sp) -80012d44: 02012823 sw zero,48(sp) -80012d48: 00000913 li s2,0 -80012d4c: 03c12783 lw a5,60(sp) -80012d50: 01141413 slli s0,s0,0x11 -80012d54: 01145413 srli s0,s0,0x11 -80012d58: 00f11623 sh a5,12(sp) -80012d5c: 01041793 slli a5,s0,0x10 -80012d60: 00c12403 lw s0,12(sp) -80012d64: 80010737 lui a4,0x80010 -80012d68: fff70713 addi a4,a4,-1 # 8000ffff <__BSS_END__+0xffff9287> -80012d6c: 00e47433 and s0,s0,a4 -80012d70: 00f46433 or s0,s0,a5 -80012d74: 03012783 lw a5,48(sp) -80012d78: 00141413 slli s0,s0,0x1 -80012d7c: 01f91913 slli s2,s2,0x1f -80012d80: 00f4a023 sw a5,0(s1) -80012d84: 03412783 lw a5,52(sp) -80012d88: 00145413 srli s0,s0,0x1 -80012d8c: 01246433 or s0,s0,s2 -80012d90: 00f4a223 sw a5,4(s1) -80012d94: 03812783 lw a5,56(sp) -80012d98: 0084a623 sw s0,12(s1) -80012d9c: 05c12083 lw ra,92(sp) -80012da0: 05812403 lw s0,88(sp) -80012da4: 00f4a423 sw a5,8(s1) -80012da8: 00048513 mv a0,s1 -80012dac: 05012903 lw s2,80(sp) -80012db0: 05412483 lw s1,84(sp) -80012db4: 04c12983 lw s3,76(sp) -80012db8: 04812a03 lw s4,72(sp) -80012dbc: 04412a83 lw s5,68(sp) -80012dc0: 06010113 addi sp,sp,96 -80012dc4: 00008067 ret -80012dc8: fff50693 addi a3,a0,-1 -80012dcc: 04069e63 bnez a3,80012e28 <__subtf3+0x664> -80012dd0: 02412683 lw a3,36(sp) -80012dd4: 00f70733 add a4,a4,a5 -80012dd8: 00f737b3 sltu a5,a4,a5 -80012ddc: 00d88633 add a2,a7,a3 -80012de0: 02e12823 sw a4,48(sp) -80012de4: 00f60733 add a4,a2,a5 -80012de8: 00f737b3 sltu a5,a4,a5 -80012dec: 02e12a23 sw a4,52(sp) -80012df0: 02812703 lw a4,40(sp) -80012df4: 00d636b3 sltu a3,a2,a3 -80012df8: 00f6e7b3 or a5,a3,a5 -80012dfc: 00e806b3 add a3,a6,a4 -80012e00: 00f68633 add a2,a3,a5 -80012e04: 00f637b3 sltu a5,a2,a5 -80012e08: 00e6b733 sltu a4,a3,a4 -80012e0c: 00f76733 or a4,a4,a5 -80012e10: 02c12783 lw a5,44(sp) -80012e14: 02c12c23 sw a2,56(sp) -80012e18: 00f30333 add t1,t1,a5 -80012e1c: 00670733 add a4,a4,t1 -80012e20: 02e12e23 sw a4,60(sp) -80012e24: b85ff06f j 800129a8 <__subtf3+0x1e4> -80012e28: 00008737 lui a4,0x8 -80012e2c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80012e30: e0e506e3 beq a0,a4,80012c3c <__subtf3+0x478> -80012e34: 07400793 li a5,116 -80012e38: 06d7d463 bge a5,a3,80012ea0 <__subtf3+0x6dc> -80012e3c: 00100793 li a5,1 -80012e40: 00012e23 sw zero,28(sp) -80012e44: 00012c23 sw zero,24(sp) -80012e48: 00012a23 sw zero,20(sp) -80012e4c: 00f12823 sw a5,16(sp) -80012e50: 1640006f j 80012fb4 <__subtf3+0x7f0> -80012e54: 00008737 lui a4,0x8 -80012e58: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80012e5c: 02e61463 bne a2,a4,80012e84 <__subtf3+0x6c0> -80012e60: 02f12823 sw a5,48(sp) -80012e64: 02412783 lw a5,36(sp) -80012e68: 00060413 mv s0,a2 -80012e6c: 02f12a23 sw a5,52(sp) -80012e70: 02812783 lw a5,40(sp) -80012e74: 02f12c23 sw a5,56(sp) -80012e78: 02c12783 lw a5,44(sp) -80012e7c: 02f12e23 sw a5,60(sp) -80012e80: dddff06f j 80012c5c <__subtf3+0x498> -80012e84: 01c12783 lw a5,28(sp) -80012e88: 00080737 lui a4,0x80 -80012e8c: 00e7e7b3 or a5,a5,a4 -80012e90: 00f12e23 sw a5,28(sp) -80012e94: 07400793 li a5,116 -80012e98: faa7c2e3 blt a5,a0,80012e3c <__subtf3+0x678> -80012e9c: 00050693 mv a3,a0 -80012ea0: 02000793 li a5,32 -80012ea4: 02f6c533 div a0,a3,a5 -80012ea8: 00000713 li a4,0 -80012eac: 02f6e7b3 rem a5,a3,a5 -80012eb0: 00000693 li a3,0 -80012eb4: 04a74063 blt a4,a0,80012ef4 <__subtf3+0x730> -80012eb8: 00050813 mv a6,a0 -80012ebc: 00055463 bgez a0,80012ec4 <__subtf3+0x700> -80012ec0: 00000813 li a6,0 -80012ec4: 00251713 slli a4,a0,0x2 -80012ec8: 04079263 bnez a5,80012f0c <__subtf3+0x748> -80012ecc: 00300813 li a6,3 -80012ed0: 40a80533 sub a0,a6,a0 -80012ed4: 00e58833 add a6,a1,a4 -80012ed8: 00082803 lw a6,0(a6) -80012edc: 00178793 addi a5,a5,1 -80012ee0: 00458593 addi a1,a1,4 -80012ee4: ff05ae23 sw a6,-4(a1) -80012ee8: fef556e3 bge a0,a5,80012ed4 <__subtf3+0x710> -80012eec: 00300593 li a1,3 -80012ef0: 0b00006f j 80012fa0 <__subtf3+0x7dc> -80012ef4: 00271813 slli a6,a4,0x2 -80012ef8: 010e0833 add a6,t3,a6 -80012efc: 00082803 lw a6,0(a6) -80012f00: 00170713 addi a4,a4,1 # 80001 <_start-0x7ff7ffff> -80012f04: 0106e6b3 or a3,a3,a6 -80012f08: fadff06f j 80012eb4 <__subtf3+0x6f0> -80012f0c: 04010593 addi a1,sp,64 -80012f10: 00281813 slli a6,a6,0x2 -80012f14: 01058833 add a6,a1,a6 -80012f18: fd082583 lw a1,-48(a6) -80012f1c: 02000313 li t1,32 -80012f20: 40f30333 sub t1,t1,a5 -80012f24: 006595b3 sll a1,a1,t1 -80012f28: 00b6e6b3 or a3,a3,a1 -80012f2c: 00ee05b3 add a1,t3,a4 -80012f30: 00300713 li a4,3 -80012f34: 00000893 li a7,0 -80012f38: 40a70733 sub a4,a4,a0 -80012f3c: 00458593 addi a1,a1,4 -80012f40: 02e8c463 blt a7,a4,80012f68 <__subtf3+0x7a4> -80012f44: 04010593 addi a1,sp,64 -80012f48: 00271713 slli a4,a4,0x2 -80012f4c: 00e58733 add a4,a1,a4 -80012f50: 01c12583 lw a1,28(sp) -80012f54: 00f5d7b3 srl a5,a1,a5 -80012f58: fcf72823 sw a5,-48(a4) -80012f5c: 00400793 li a5,4 -80012f60: 40a787b3 sub a5,a5,a0 -80012f64: f89ff06f j 80012eec <__subtf3+0x728> -80012f68: ffc5a803 lw a6,-4(a1) -80012f6c: 0005af03 lw t5,0(a1) -80012f70: 00289e93 slli t4,a7,0x2 -80012f74: 00f85833 srl a6,a6,a5 -80012f78: 006f1f33 sll t5,t5,t1 -80012f7c: 01de0eb3 add t4,t3,t4 -80012f80: 01e86833 or a6,a6,t5 -80012f84: 010ea023 sw a6,0(t4) -80012f88: 00188893 addi a7,a7,1 -80012f8c: fb1ff06f j 80012f3c <__subtf3+0x778> -80012f90: 00279713 slli a4,a5,0x2 -80012f94: 00ee0733 add a4,t3,a4 -80012f98: 00072023 sw zero,0(a4) -80012f9c: 00178793 addi a5,a5,1 -80012fa0: fef5d8e3 bge a1,a5,80012f90 <__subtf3+0x7cc> -80012fa4: 01012783 lw a5,16(sp) -80012fa8: 00d036b3 snez a3,a3 -80012fac: 00d7e6b3 or a3,a5,a3 -80012fb0: 00d12823 sw a3,16(sp) -80012fb4: 02012683 lw a3,32(sp) -80012fb8: 01012783 lw a5,16(sp) -80012fbc: 02412703 lw a4,36(sp) -80012fc0: 01812503 lw a0,24(sp) -80012fc4: 00f687b3 add a5,a3,a5 -80012fc8: 00d7b6b3 sltu a3,a5,a3 -80012fcc: 02f12823 sw a5,48(sp) -80012fd0: 01412783 lw a5,20(sp) -80012fd4: 01c12803 lw a6,28(sp) -80012fd8: 00060413 mv s0,a2 -80012fdc: 00f707b3 add a5,a4,a5 -80012fe0: 00d785b3 add a1,a5,a3 -80012fe4: 00e7b733 sltu a4,a5,a4 -80012fe8: 00d5b7b3 sltu a5,a1,a3 -80012fec: 00f767b3 or a5,a4,a5 -80012ff0: 02812703 lw a4,40(sp) -80012ff4: 02c12683 lw a3,44(sp) -80012ff8: 02b12a23 sw a1,52(sp) -80012ffc: 00a70533 add a0,a4,a0 -80013000: 00f505b3 add a1,a0,a5 -80013004: 00e53733 sltu a4,a0,a4 -80013008: 00f5b7b3 sltu a5,a1,a5 -8001300c: 010686b3 add a3,a3,a6 -80013010: 00f76733 or a4,a4,a5 -80013014: 00e68733 add a4,a3,a4 -80013018: 02b12c23 sw a1,56(sp) -8001301c: 02e12e23 sw a4,60(sp) -80013020: b69ff06f j 80012b88 <__subtf3+0x3c4> -80013024: 00008fb7 lui t6,0x8 -80013028: 00140f13 addi t5,s0,1 -8001302c: ffef8613 addi a2,t6,-2 # 7ffe <_start-0x7fff8002> -80013030: 00cf7633 and a2,t5,a2 -80013034: 02412683 lw a3,36(sp) -80013038: 02812583 lw a1,40(sp) -8001303c: 02c12503 lw a0,44(sp) -80013040: 01412303 lw t1,20(sp) -80013044: 01812883 lw a7,24(sp) -80013048: 01c12e03 lw t3,28(sp) -8001304c: 03010813 addi a6,sp,48 -80013050: 03c10e93 addi t4,sp,60 -80013054: 14061663 bnez a2,800131a0 <__subtf3+0x9dc> -80013058: 01136633 or a2,t1,a7 -8001305c: 01c66633 or a2,a2,t3 -80013060: 00e66633 or a2,a2,a4 -80013064: 0a041663 bnez s0,80013110 <__subtf3+0x94c> -80013068: 00061c63 bnez a2,80013080 <__subtf3+0x8bc> -8001306c: 02f12823 sw a5,48(sp) -80013070: 02d12a23 sw a3,52(sp) -80013074: 02b12c23 sw a1,56(sp) -80013078: 02a12e23 sw a0,60(sp) -8001307c: be1ff06f j 80012c5c <__subtf3+0x498> -80013080: 00b6e633 or a2,a3,a1 -80013084: 00a66633 or a2,a2,a0 -80013088: 00f66633 or a2,a2,a5 -8001308c: 00061c63 bnez a2,800130a4 <__subtf3+0x8e0> -80013090: 02e12823 sw a4,48(sp) -80013094: 02612a23 sw t1,52(sp) -80013098: 03112c23 sw a7,56(sp) -8001309c: 03c12e23 sw t3,60(sp) -800130a0: bbdff06f j 80012c5c <__subtf3+0x498> -800130a4: 00f707b3 add a5,a4,a5 -800130a8: 00e7b733 sltu a4,a5,a4 -800130ac: 006686b3 add a3,a3,t1 -800130b0: 02f12823 sw a5,48(sp) -800130b4: 00e687b3 add a5,a3,a4 -800130b8: 00e7b733 sltu a4,a5,a4 -800130bc: 0066b6b3 sltu a3,a3,t1 -800130c0: 00e6e733 or a4,a3,a4 -800130c4: 011585b3 add a1,a1,a7 -800130c8: 02f12a23 sw a5,52(sp) -800130cc: 00e587b3 add a5,a1,a4 -800130d0: 0115b633 sltu a2,a1,a7 -800130d4: 00e7b733 sltu a4,a5,a4 -800130d8: 00e66733 or a4,a2,a4 -800130dc: 01c50633 add a2,a0,t3 -800130e0: 00c70633 add a2,a4,a2 -800130e4: 02f12c23 sw a5,56(sp) -800130e8: 00c61793 slli a5,a2,0xc -800130ec: 0007c663 bltz a5,800130f8 <__subtf3+0x934> -800130f0: 02c12e23 sw a2,60(sp) -800130f4: b69ff06f j 80012c5c <__subtf3+0x498> -800130f8: fff80737 lui a4,0xfff80 -800130fc: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff69287> -80013100: 00e67633 and a2,a2,a4 -80013104: 02c12e23 sw a2,60(sp) -80013108: 00100413 li s0,1 -8001310c: b51ff06f j 80012c5c <__subtf3+0x498> -80013110: 00061e63 bnez a2,8001312c <__subtf3+0x968> -80013114: 02f12823 sw a5,48(sp) -80013118: 02d12a23 sw a3,52(sp) -8001311c: 02b12c23 sw a1,56(sp) -80013120: 02a12e23 sw a0,60(sp) -80013124: ffff8413 addi s0,t6,-1 -80013128: b35ff06f j 80012c5c <__subtf3+0x498> -8001312c: 00b6e633 or a2,a3,a1 -80013130: 00a66633 or a2,a2,a0 -80013134: 00f667b3 or a5,a2,a5 -80013138: 00079c63 bnez a5,80013150 <__subtf3+0x98c> -8001313c: 02e12823 sw a4,48(sp) -80013140: 02612a23 sw t1,52(sp) -80013144: 03112c23 sw a7,56(sp) -80013148: 03c12e23 sw t3,60(sp) -8001314c: fd9ff06f j 80013124 <__subtf3+0x960> -80013150: 03f12e23 sw t6,60(sp) -80013154: 02012c23 sw zero,56(sp) -80013158: 02012a23 sw zero,52(sp) -8001315c: 02012823 sw zero,48(sp) -80013160: 000e8793 mv a5,t4 -80013164: 0007a703 lw a4,0(a5) -80013168: ffc7a683 lw a3,-4(a5) -8001316c: ffc78793 addi a5,a5,-4 -80013170: 00371713 slli a4,a4,0x3 -80013174: 01d6d693 srli a3,a3,0x1d -80013178: 00d76733 or a4,a4,a3 -8001317c: 00e7a223 sw a4,4(a5) -80013180: fef812e3 bne a6,a5,80013164 <__subtf3+0x9a0> -80013184: 03012783 lw a5,48(sp) -80013188: 00008437 lui s0,0x8 -8001318c: 00000913 li s2,0 -80013190: 00379793 slli a5,a5,0x3 -80013194: 02f12823 sw a5,48(sp) -80013198: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> -8001319c: ac1ff06f j 80012c5c <__subtf3+0x498> -800131a0: 00f707b3 add a5,a4,a5 -800131a4: 00e7b733 sltu a4,a5,a4 -800131a8: 006686b3 add a3,a3,t1 -800131ac: 02f12823 sw a5,48(sp) -800131b0: 00e687b3 add a5,a3,a4 -800131b4: 00e7b733 sltu a4,a5,a4 -800131b8: 0066b6b3 sltu a3,a3,t1 -800131bc: 00e6e733 or a4,a3,a4 -800131c0: 01158633 add a2,a1,a7 -800131c4: 00e606b3 add a3,a2,a4 -800131c8: 00e6b733 sltu a4,a3,a4 -800131cc: 01163633 sltu a2,a2,a7 -800131d0: 00e66633 or a2,a2,a4 -800131d4: 01c50733 add a4,a0,t3 -800131d8: 00e60633 add a2,a2,a4 -800131dc: 02f12a23 sw a5,52(sp) -800131e0: 02d12c23 sw a3,56(sp) -800131e4: 02c12e23 sw a2,60(sp) -800131e8: 00080793 mv a5,a6 -800131ec: 0007a703 lw a4,0(a5) -800131f0: 0047a683 lw a3,4(a5) -800131f4: 00478793 addi a5,a5,4 -800131f8: 00175713 srli a4,a4,0x1 -800131fc: 01f69693 slli a3,a3,0x1f -80013200: 00d76733 or a4,a4,a3 -80013204: fee7ae23 sw a4,-4(a5) -80013208: fefe92e3 bne t4,a5,800131ec <__subtf3+0xa28> -8001320c: 000087b7 lui a5,0x8 -80013210: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80013214: 00ff0c63 beq t5,a5,8001322c <__subtf3+0xa68> -80013218: 03c12783 lw a5,60(sp) -8001321c: 0017d793 srli a5,a5,0x1 -80013220: 02f12e23 sw a5,60(sp) -80013224: 000f0413 mv s0,t5 -80013228: a35ff06f j 80012c5c <__subtf3+0x498> -8001322c: 02012e23 sw zero,60(sp) -80013230: 02012c23 sw zero,56(sp) -80013234: 02012a23 sw zero,52(sp) -80013238: 02012823 sw zero,48(sp) -8001323c: fe9ff06f j 80013224 <__subtf3+0xa60> -80013240: 28a05263 blez a0,800134c4 <__subtf3+0xd00> -80013244: 0c061263 bnez a2,80013308 <__subtf3+0xb44> -80013248: 02412803 lw a6,36(sp) -8001324c: 02812603 lw a2,40(sp) -80013250: 02c12e03 lw t3,44(sp) -80013254: 00c865b3 or a1,a6,a2 -80013258: 01c5e5b3 or a1,a1,t3 -8001325c: 00f5e5b3 or a1,a1,a5 -80013260: ec058863 beqz a1,80012930 <__subtf3+0x16c> -80013264: fff50693 addi a3,a0,-1 -80013268: 06069a63 bnez a3,800132dc <__subtf3+0xb18> -8001326c: 01412883 lw a7,20(sp) -80013270: 40f707b3 sub a5,a4,a5 -80013274: 00f735b3 sltu a1,a4,a5 -80013278: 41088533 sub a0,a7,a6 -8001327c: 00a8b333 sltu t1,a7,a0 -80013280: 40b50533 sub a0,a0,a1 -80013284: 02f12823 sw a5,48(sp) -80013288: 02a12a23 sw a0,52(sp) -8001328c: 00000593 li a1,0 -80013290: 00f77663 bgeu a4,a5,8001329c <__subtf3+0xad8> -80013294: 411805b3 sub a1,a6,a7 -80013298: 0015b593 seqz a1,a1 -8001329c: 01812803 lw a6,24(sp) -800132a0: 0065e5b3 or a1,a1,t1 -800132a4: 40c80533 sub a0,a6,a2 -800132a8: 00a837b3 sltu a5,a6,a0 -800132ac: 40b50533 sub a0,a0,a1 -800132b0: 02a12c23 sw a0,56(sp) -800132b4: 00058663 beqz a1,800132c0 <__subtf3+0xafc> -800132b8: 41060633 sub a2,a2,a6 -800132bc: 00163693 seqz a3,a2 -800132c0: 01c12703 lw a4,28(sp) -800132c4: 00f6e7b3 or a5,a3,a5 -800132c8: 41c70733 sub a4,a4,t3 -800132cc: 40f707b3 sub a5,a4,a5 -800132d0: 02f12e23 sw a5,60(sp) -800132d4: 00100413 li s0,1 -800132d8: 1cc0006f j 800134a4 <__subtf3+0xce0> -800132dc: 000087b7 lui a5,0x8 -800132e0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800132e4: e4f50663 beq a0,a5,80012930 <__subtf3+0x16c> -800132e8: 07400793 li a5,116 -800132ec: 04d7d263 bge a5,a3,80013330 <__subtf3+0xb6c> -800132f0: 00100793 li a5,1 -800132f4: 02012623 sw zero,44(sp) -800132f8: 02012423 sw zero,40(sp) -800132fc: 02012223 sw zero,36(sp) -80013300: 02f12023 sw a5,32(sp) -80013304: 1280006f j 8001342c <__subtf3+0xc68> -80013308: 000087b7 lui a5,0x8 -8001330c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80013310: ecf40c63 beq s0,a5,800129e8 <__subtf3+0x224> -80013314: 02c12783 lw a5,44(sp) -80013318: 00080737 lui a4,0x80 -8001331c: 00e7e7b3 or a5,a5,a4 -80013320: 02f12623 sw a5,44(sp) -80013324: 07400793 li a5,116 -80013328: fca7c4e3 blt a5,a0,800132f0 <__subtf3+0xb2c> -8001332c: 00050693 mv a3,a0 -80013330: 4056de13 srai t3,a3,0x5 -80013334: 01f6f793 andi a5,a3,31 -80013338: 00000613 li a2,0 -8001333c: 00000713 li a4,0 -80013340: 00271693 slli a3,a4,0x2 -80013344: 03c71863 bne a4,t3,80013374 <__subtf3+0xbb0> -80013348: 04079063 bnez a5,80013388 <__subtf3+0xbc4> -8001334c: 00300593 li a1,3 -80013350: 40e58733 sub a4,a1,a4 -80013354: 00d885b3 add a1,a7,a3 -80013358: 0005a583 lw a1,0(a1) -8001335c: 00178793 addi a5,a5,1 -80013360: 00488893 addi a7,a7,4 -80013364: feb8ae23 sw a1,-4(a7) -80013368: fef756e3 bge a4,a5,80013354 <__subtf3+0xb90> -8001336c: 00400693 li a3,4 -80013370: 0a80006f j 80013418 <__subtf3+0xc54> -80013374: 00d306b3 add a3,t1,a3 -80013378: 0006a683 lw a3,0(a3) -8001337c: 00170713 addi a4,a4,1 # 80001 <_start-0x7ff7ffff> -80013380: 00d66633 or a2,a2,a3 -80013384: fbdff06f j 80013340 <__subtf3+0xb7c> -80013388: 04010713 addi a4,sp,64 -8001338c: 00d70733 add a4,a4,a3 -80013390: fe072703 lw a4,-32(a4) -80013394: 02000813 li a6,32 -80013398: 40f80833 sub a6,a6,a5 -8001339c: 01071733 sll a4,a4,a6 -800133a0: 00e66633 or a2,a2,a4 -800133a4: 00300713 li a4,3 -800133a8: 00d306b3 add a3,t1,a3 -800133ac: 00000513 li a0,0 -800133b0: 41c70733 sub a4,a4,t3 -800133b4: 00468693 addi a3,a3,4 -800133b8: 02e54463 blt a0,a4,800133e0 <__subtf3+0xc1c> -800133bc: 04010693 addi a3,sp,64 -800133c0: 00271713 slli a4,a4,0x2 -800133c4: 00e68733 add a4,a3,a4 -800133c8: 02c12683 lw a3,44(sp) -800133cc: 00f6d7b3 srl a5,a3,a5 -800133d0: fef72023 sw a5,-32(a4) -800133d4: 00400793 li a5,4 -800133d8: 41c787b3 sub a5,a5,t3 -800133dc: f91ff06f j 8001336c <__subtf3+0xba8> -800133e0: ffc6a583 lw a1,-4(a3) -800133e4: 0006ae83 lw t4,0(a3) -800133e8: 00251893 slli a7,a0,0x2 -800133ec: 00f5d5b3 srl a1,a1,a5 -800133f0: 010e9eb3 sll t4,t4,a6 -800133f4: 011308b3 add a7,t1,a7 -800133f8: 01d5e5b3 or a1,a1,t4 -800133fc: 00b8a023 sw a1,0(a7) -80013400: 00150513 addi a0,a0,1 -80013404: fb1ff06f j 800133b4 <__subtf3+0xbf0> -80013408: 00279713 slli a4,a5,0x2 -8001340c: 00e30733 add a4,t1,a4 -80013410: 00072023 sw zero,0(a4) -80013414: 00178793 addi a5,a5,1 -80013418: fed798e3 bne a5,a3,80013408 <__subtf3+0xc44> -8001341c: 02012783 lw a5,32(sp) -80013420: 00c03633 snez a2,a2 -80013424: 00c7e633 or a2,a5,a2 -80013428: 02c12023 sw a2,32(sp) -8001342c: 01412683 lw a3,20(sp) -80013430: 01012583 lw a1,16(sp) -80013434: 02012703 lw a4,32(sp) -80013438: 02412783 lw a5,36(sp) -8001343c: 40e58733 sub a4,a1,a4 -80013440: 40f687b3 sub a5,a3,a5 -80013444: 00f6b633 sltu a2,a3,a5 -80013448: 00e5b6b3 sltu a3,a1,a4 -8001344c: 40d786b3 sub a3,a5,a3 -80013450: 02d12a23 sw a3,52(sp) -80013454: 02e12823 sw a4,48(sp) -80013458: 00000693 li a3,0 -8001345c: 00e5f463 bgeu a1,a4,80013464 <__subtf3+0xca0> -80013460: 0017b693 seqz a3,a5 -80013464: 00c6e6b3 or a3,a3,a2 -80013468: 02812703 lw a4,40(sp) -8001346c: 01812603 lw a2,24(sp) -80013470: 40e60733 sub a4,a2,a4 -80013474: 40d707b3 sub a5,a4,a3 -80013478: 02f12c23 sw a5,56(sp) -8001347c: 00e635b3 sltu a1,a2,a4 -80013480: 00000613 li a2,0 -80013484: 00068463 beqz a3,8001348c <__subtf3+0xcc8> -80013488: 00173613 seqz a2,a4 -8001348c: 01c12783 lw a5,28(sp) -80013490: 02c12703 lw a4,44(sp) -80013494: 00b66633 or a2,a2,a1 -80013498: 40e787b3 sub a5,a5,a4 -8001349c: 40c787b3 sub a5,a5,a2 -800134a0: 02f12e23 sw a5,60(sp) -800134a4: 03c12783 lw a5,60(sp) -800134a8: 00c79713 slli a4,a5,0xc -800134ac: fa075863 bgez a4,80012c5c <__subtf3+0x498> -800134b0: 00080737 lui a4,0x80 -800134b4: fff70713 addi a4,a4,-1 # 7ffff <_start-0x7ff80001> -800134b8: 00e7f7b3 and a5,a5,a4 -800134bc: 02f12e23 sw a5,60(sp) -800134c0: 5a40006f j 80013a64 <__subtf3+0x12a0> -800134c4: 2c050e63 beqz a0,800137a0 <__subtf3+0xfdc> -800134c8: 408606b3 sub a3,a2,s0 -800134cc: 0e041663 bnez s0,800135b8 <__subtf3+0xdf4> -800134d0: 01412303 lw t1,20(sp) -800134d4: 01812883 lw a7,24(sp) -800134d8: 01c12f03 lw t5,28(sp) -800134dc: 01136eb3 or t4,t1,a7 -800134e0: 01eeeeb3 or t4,t4,t5 -800134e4: 00eeeeb3 or t4,t4,a4 -800134e8: 020e9663 bnez t4,80013514 <__subtf3+0xd50> -800134ec: 02f12823 sw a5,48(sp) -800134f0: 02412783 lw a5,36(sp) -800134f4: 00068413 mv s0,a3 -800134f8: 02f12a23 sw a5,52(sp) -800134fc: 02812783 lw a5,40(sp) -80013500: 02f12c23 sw a5,56(sp) -80013504: 02c12783 lw a5,44(sp) -80013508: 02f12e23 sw a5,60(sp) -8001350c: 00080913 mv s2,a6 -80013510: f4cff06f j 80012c5c <__subtf3+0x498> -80013514: fff68513 addi a0,a3,-1 -80013518: 06051a63 bnez a0,8001358c <__subtf3+0xdc8> -8001351c: 02412583 lw a1,36(sp) -80013520: 40e78733 sub a4,a5,a4 -80013524: 00e7b6b3 sltu a3,a5,a4 -80013528: 40658633 sub a2,a1,t1 -8001352c: 00c5be33 sltu t3,a1,a2 -80013530: 40d60633 sub a2,a2,a3 -80013534: 02e12823 sw a4,48(sp) -80013538: 02c12a23 sw a2,52(sp) -8001353c: 00000693 li a3,0 -80013540: 00e7f663 bgeu a5,a4,8001354c <__subtf3+0xd88> -80013544: 40b306b3 sub a3,t1,a1 -80013548: 0016b693 seqz a3,a3 -8001354c: 02812583 lw a1,40(sp) -80013550: 01c6e733 or a4,a3,t3 -80013554: 411586b3 sub a3,a1,a7 -80013558: 00d5b633 sltu a2,a1,a3 -8001355c: 40e686b3 sub a3,a3,a4 -80013560: 02d12c23 sw a3,56(sp) -80013564: 00070663 beqz a4,80013570 <__subtf3+0xdac> -80013568: 40b888b3 sub a7,a7,a1 -8001356c: 0018b513 seqz a0,a7 -80013570: 02c12783 lw a5,44(sp) -80013574: 00c56533 or a0,a0,a2 -80013578: 00080913 mv s2,a6 -8001357c: 41e787b3 sub a5,a5,t5 -80013580: 40a78533 sub a0,a5,a0 -80013584: 02a12e23 sw a0,60(sp) -80013588: d4dff06f j 800132d4 <__subtf3+0xb10> -8001358c: 00008737 lui a4,0x8 -80013590: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80013594: f4e68ce3 beq a3,a4,800134ec <__subtf3+0xd28> -80013598: 07400793 li a5,116 -8001359c: 0aa7dc63 bge a5,a0,80013654 <__subtf3+0xe90> -800135a0: 00100793 li a5,1 -800135a4: 00012e23 sw zero,28(sp) -800135a8: 00012c23 sw zero,24(sp) -800135ac: 00012a23 sw zero,20(sp) -800135b0: 00f12823 sw a5,16(sp) -800135b4: 1680006f j 8001371c <__subtf3+0xf58> -800135b8: 00008737 lui a4,0x8 -800135bc: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -800135c0: 02e61463 bne a2,a4,800135e8 <__subtf3+0xe24> -800135c4: 02f12823 sw a5,48(sp) -800135c8: 02412783 lw a5,36(sp) -800135cc: 00060413 mv s0,a2 -800135d0: 02f12a23 sw a5,52(sp) -800135d4: 02812783 lw a5,40(sp) -800135d8: 02f12c23 sw a5,56(sp) -800135dc: 02c12783 lw a5,44(sp) -800135e0: 02f12e23 sw a5,60(sp) -800135e4: f29ff06f j 8001350c <__subtf3+0xd48> -800135e8: 01c12783 lw a5,28(sp) -800135ec: 00080737 lui a4,0x80 -800135f0: 00e7e7b3 or a5,a5,a4 -800135f4: 00f12e23 sw a5,28(sp) -800135f8: 07400793 li a5,116 -800135fc: fad7c2e3 blt a5,a3,800135a0 <__subtf3+0xddc> -80013600: 02000793 li a5,32 -80013604: 02f6c533 div a0,a3,a5 -80013608: 00000713 li a4,0 -8001360c: 02f6e7b3 rem a5,a3,a5 -80013610: 00000693 li a3,0 -80013614: 04a74463 blt a4,a0,8001365c <__subtf3+0xe98> -80013618: 00050893 mv a7,a0 -8001361c: 00055463 bgez a0,80013624 <__subtf3+0xe60> -80013620: 00000893 li a7,0 -80013624: 00251713 slli a4,a0,0x2 -80013628: 04079663 bnez a5,80013674 <__subtf3+0xeb0> -8001362c: 00300893 li a7,3 -80013630: 40a88533 sub a0,a7,a0 -80013634: 00e588b3 add a7,a1,a4 -80013638: 0008a883 lw a7,0(a7) -8001363c: 00178793 addi a5,a5,1 -80013640: 00458593 addi a1,a1,4 -80013644: ff15ae23 sw a7,-4(a1) -80013648: fef556e3 bge a0,a5,80013634 <__subtf3+0xe70> -8001364c: 00300593 li a1,3 -80013650: 0b80006f j 80013708 <__subtf3+0xf44> -80013654: 00050693 mv a3,a0 -80013658: fa9ff06f j 80013600 <__subtf3+0xe3c> -8001365c: 00271893 slli a7,a4,0x2 -80013660: 011e08b3 add a7,t3,a7 -80013664: 0008a883 lw a7,0(a7) -80013668: 00170713 addi a4,a4,1 # 80001 <_start-0x7ff7ffff> -8001366c: 0116e6b3 or a3,a3,a7 -80013670: fa5ff06f j 80013614 <__subtf3+0xe50> -80013674: 04010593 addi a1,sp,64 -80013678: 00289893 slli a7,a7,0x2 -8001367c: 011588b3 add a7,a1,a7 -80013680: fd08a583 lw a1,-48(a7) -80013684: 02000e93 li t4,32 -80013688: 40fe8eb3 sub t4,t4,a5 -8001368c: 01d595b3 sll a1,a1,t4 -80013690: 00b6e6b3 or a3,a3,a1 -80013694: 00ee05b3 add a1,t3,a4 -80013698: 00300713 li a4,3 -8001369c: 00000313 li t1,0 -800136a0: 40a70733 sub a4,a4,a0 -800136a4: 00458593 addi a1,a1,4 -800136a8: 02e34463 blt t1,a4,800136d0 <__subtf3+0xf0c> -800136ac: 04010593 addi a1,sp,64 -800136b0: 00271713 slli a4,a4,0x2 -800136b4: 00e58733 add a4,a1,a4 -800136b8: 01c12583 lw a1,28(sp) -800136bc: 00f5d7b3 srl a5,a1,a5 -800136c0: fcf72823 sw a5,-48(a4) -800136c4: 00400793 li a5,4 -800136c8: 40a787b3 sub a5,a5,a0 -800136cc: f81ff06f j 8001364c <__subtf3+0xe88> -800136d0: ffc5a883 lw a7,-4(a1) -800136d4: 0005af83 lw t6,0(a1) -800136d8: 00231f13 slli t5,t1,0x2 -800136dc: 00f8d8b3 srl a7,a7,a5 -800136e0: 01df9fb3 sll t6,t6,t4 -800136e4: 01ee0f33 add t5,t3,t5 -800136e8: 01f8e8b3 or a7,a7,t6 -800136ec: 011f2023 sw a7,0(t5) -800136f0: 00130313 addi t1,t1,1 -800136f4: fb1ff06f j 800136a4 <__subtf3+0xee0> -800136f8: 00279713 slli a4,a5,0x2 -800136fc: 00ee0733 add a4,t3,a4 -80013700: 00072023 sw zero,0(a4) -80013704: 00178793 addi a5,a5,1 -80013708: fef5d8e3 bge a1,a5,800136f8 <__subtf3+0xf34> -8001370c: 01012783 lw a5,16(sp) -80013710: 00d036b3 snez a3,a3 -80013714: 00d7e6b3 or a3,a5,a3 -80013718: 00d12823 sw a3,16(sp) -8001371c: 02412683 lw a3,36(sp) -80013720: 02012503 lw a0,32(sp) -80013724: 01012703 lw a4,16(sp) -80013728: 01412783 lw a5,20(sp) -8001372c: 40e50733 sub a4,a0,a4 -80013730: 40f687b3 sub a5,a3,a5 -80013734: 00f6b5b3 sltu a1,a3,a5 -80013738: 00e536b3 sltu a3,a0,a4 -8001373c: 40d786b3 sub a3,a5,a3 -80013740: 02d12a23 sw a3,52(sp) -80013744: 02e12823 sw a4,48(sp) -80013748: 00000693 li a3,0 -8001374c: 00e57463 bgeu a0,a4,80013754 <__subtf3+0xf90> -80013750: 0017b693 seqz a3,a5 -80013754: 00b6e6b3 or a3,a3,a1 -80013758: 01812703 lw a4,24(sp) -8001375c: 02812583 lw a1,40(sp) -80013760: 40e58733 sub a4,a1,a4 -80013764: 40d707b3 sub a5,a4,a3 -80013768: 02f12c23 sw a5,56(sp) -8001376c: 00e5b533 sltu a0,a1,a4 -80013770: 00000593 li a1,0 -80013774: 00068463 beqz a3,8001377c <__subtf3+0xfb8> -80013778: 00173593 seqz a1,a4 -8001377c: 02c12783 lw a5,44(sp) -80013780: 01c12703 lw a4,28(sp) -80013784: 00a5e5b3 or a1,a1,a0 -80013788: 00060413 mv s0,a2 -8001378c: 40e787b3 sub a5,a5,a4 -80013790: 40b787b3 sub a5,a5,a1 -80013794: 02f12e23 sw a5,60(sp) -80013798: 00080913 mv s2,a6 -8001379c: d09ff06f j 800134a4 <__subtf3+0xce0> -800137a0: 00008f37 lui t5,0x8 -800137a4: ffef0693 addi a3,t5,-2 # 7ffe <_start-0x7fff8002> -800137a8: 00140593 addi a1,s0,1 -800137ac: 00d5f5b3 and a1,a1,a3 -800137b0: 02412603 lw a2,36(sp) -800137b4: 01412683 lw a3,20(sp) -800137b8: 01812883 lw a7,24(sp) -800137bc: 01c12e83 lw t4,28(sp) -800137c0: 02812303 lw t1,40(sp) -800137c4: 02c12e03 lw t3,44(sp) -800137c8: 1e059063 bnez a1,800139a8 <__subtf3+0x11e4> -800137cc: 006665b3 or a1,a2,t1 -800137d0: 0116e533 or a0,a3,a7 -800137d4: 01c5e5b3 or a1,a1,t3 -800137d8: 01d56533 or a0,a0,t4 -800137dc: 00f5e5b3 or a1,a1,a5 -800137e0: 00e56533 or a0,a0,a4 -800137e4: 10041a63 bnez s0,800138f8 <__subtf3+0x1134> -800137e8: 02051463 bnez a0,80013810 <__subtf3+0x104c> -800137ec: 02f12823 sw a5,48(sp) -800137f0: 02c12a23 sw a2,52(sp) -800137f4: 02612c23 sw t1,56(sp) -800137f8: 03c12e23 sw t3,60(sp) -800137fc: 00080913 mv s2,a6 -80013800: c4059e63 bnez a1,80012c5c <__subtf3+0x498> -80013804: 00000413 li s0,0 -80013808: 00000913 li s2,0 -8001380c: c50ff06f j 80012c5c <__subtf3+0x498> -80013810: 00059c63 bnez a1,80013828 <__subtf3+0x1064> -80013814: 02e12823 sw a4,48(sp) -80013818: 02d12a23 sw a3,52(sp) -8001381c: 03112c23 sw a7,56(sp) -80013820: 03d12e23 sw t4,60(sp) -80013824: c38ff06f j 80012c5c <__subtf3+0x498> -80013828: 40f705b3 sub a1,a4,a5 -8001382c: 40c68fb3 sub t6,a3,a2 -80013830: 00b73f33 sltu t5,a4,a1 -80013834: 01f6b533 sltu a0,a3,t6 -80013838: 41ef8fb3 sub t6,t6,t5 -8001383c: 02b12823 sw a1,48(sp) -80013840: 03f12a23 sw t6,52(sp) -80013844: 00000f13 li t5,0 -80013848: 00b77663 bgeu a4,a1,80013854 <__subtf3+0x1090> -8001384c: 40d60f33 sub t5,a2,a3 -80013850: 001f3f13 seqz t5,t5 -80013854: 406882b3 sub t0,a7,t1 -80013858: 00af6f33 or t5,t5,a0 -8001385c: 41e289b3 sub s3,t0,t5 -80013860: 03312c23 sw s3,56(sp) -80013864: 0058ba33 sltu s4,a7,t0 -80013868: 00000393 li t2,0 -8001386c: 000f0463 beqz t5,80013874 <__subtf3+0x10b0> -80013870: 0012b393 seqz t2,t0 -80013874: 41ce8533 sub a0,t4,t3 -80013878: 0143e3b3 or t2,t2,s4 -8001387c: 40750533 sub a0,a0,t2 -80013880: 02a12e23 sw a0,60(sp) -80013884: 00c51f13 slli t5,a0,0xc -80013888: 060f5063 bgez t5,800138e8 <__subtf3+0x1124> -8001388c: 40e78733 sub a4,a5,a4 -80013890: 40d606b3 sub a3,a2,a3 -80013894: 00e7b5b3 sltu a1,a5,a4 -80013898: 40b685b3 sub a1,a3,a1 -8001389c: 02b12a23 sw a1,52(sp) -800138a0: 02e12823 sw a4,48(sp) -800138a4: 00d63633 sltu a2,a2,a3 -800138a8: 00000593 li a1,0 -800138ac: 00e7f463 bgeu a5,a4,800138b4 <__subtf3+0x10f0> -800138b0: 0016b593 seqz a1,a3 -800138b4: 00c5e633 or a2,a1,a2 -800138b8: 41130733 sub a4,t1,a7 -800138bc: 00e336b3 sltu a3,t1,a4 -800138c0: 40c70733 sub a4,a4,a2 -800138c4: 02e12c23 sw a4,56(sp) -800138c8: 00000593 li a1,0 -800138cc: 00060463 beqz a2,800138d4 <__subtf3+0x1110> -800138d0: 0012b593 seqz a1,t0 -800138d4: 41de0733 sub a4,t3,t4 -800138d8: 00d5e5b3 or a1,a1,a3 -800138dc: 40b705b3 sub a1,a4,a1 -800138e0: 02b12e23 sw a1,60(sp) -800138e4: c29ff06f j 8001350c <__subtf3+0xd48> -800138e8: 01f5e5b3 or a1,a1,t6 -800138ec: 0135e5b3 or a1,a1,s3 -800138f0: 00a5e5b3 or a1,a1,a0 -800138f4: f0dff06f j 80013800 <__subtf3+0x103c> -800138f8: 03010f93 addi t6,sp,48 -800138fc: 04051e63 bnez a0,80013958 <__subtf3+0x1194> -80013900: 02059e63 bnez a1,8001393c <__subtf3+0x1178> -80013904: 03e12e23 sw t5,60(sp) -80013908: 02012c23 sw zero,56(sp) -8001390c: 02012a23 sw zero,52(sp) -80013910: 02012823 sw zero,48(sp) -80013914: 03c10793 addi a5,sp,60 -80013918: 0007a703 lw a4,0(a5) -8001391c: ffc7a683 lw a3,-4(a5) -80013920: ffc78793 addi a5,a5,-4 -80013924: 00371713 slli a4,a4,0x3 -80013928: 01d6d693 srli a3,a3,0x1d -8001392c: 00d76733 or a4,a4,a3 -80013930: 00e7a223 sw a4,4(a5) -80013934: feff92e3 bne t6,a5,80013918 <__subtf3+0x1154> -80013938: 84dff06f j 80013184 <__subtf3+0x9c0> -8001393c: 02f12823 sw a5,48(sp) -80013940: 02c12a23 sw a2,52(sp) -80013944: 02612c23 sw t1,56(sp) -80013948: 03c12e23 sw t3,60(sp) -8001394c: 00080913 mv s2,a6 -80013950: ffff0413 addi s0,t5,-1 -80013954: b08ff06f j 80012c5c <__subtf3+0x498> -80013958: 00059c63 bnez a1,80013970 <__subtf3+0x11ac> -8001395c: 02e12823 sw a4,48(sp) -80013960: 02d12a23 sw a3,52(sp) -80013964: 03112c23 sw a7,56(sp) -80013968: 03d12e23 sw t4,60(sp) -8001396c: fe5ff06f j 80013950 <__subtf3+0x118c> -80013970: 03e12e23 sw t5,60(sp) -80013974: 02012c23 sw zero,56(sp) -80013978: 02012a23 sw zero,52(sp) -8001397c: 02012823 sw zero,48(sp) -80013980: 03c10793 addi a5,sp,60 -80013984: 0007a703 lw a4,0(a5) -80013988: ffc7a683 lw a3,-4(a5) -8001398c: ffc78793 addi a5,a5,-4 -80013990: 00371713 slli a4,a4,0x3 -80013994: 01d6d693 srli a3,a3,0x1d -80013998: 00d76733 or a4,a4,a3 -8001399c: 00e7a223 sw a4,4(a5) -800139a0: feff92e3 bne t6,a5,80013984 <__subtf3+0x11c0> -800139a4: fe0ff06f j 80013184 <__subtf3+0x9c0> -800139a8: 40f705b3 sub a1,a4,a5 -800139ac: 40c682b3 sub t0,a3,a2 -800139b0: 00b73fb3 sltu t6,a4,a1 -800139b4: 0056bf33 sltu t5,a3,t0 -800139b8: 41f282b3 sub t0,t0,t6 -800139bc: 02b12823 sw a1,48(sp) -800139c0: 02512a23 sw t0,52(sp) -800139c4: 00000f93 li t6,0 -800139c8: 00b77663 bgeu a4,a1,800139d4 <__subtf3+0x1210> -800139cc: 40d60fb3 sub t6,a2,a3 -800139d0: 001fbf93 seqz t6,t6 -800139d4: 406883b3 sub t2,a7,t1 -800139d8: 01efefb3 or t6,t6,t5 -800139dc: 41f38a33 sub s4,t2,t6 -800139e0: 03412c23 sw s4,56(sp) -800139e4: 0078bab3 sltu s5,a7,t2 -800139e8: 00000993 li s3,0 -800139ec: 000f8463 beqz t6,800139f4 <__subtf3+0x1230> -800139f0: 0013b993 seqz s3,t2 -800139f4: 41ce8f33 sub t5,t4,t3 -800139f8: 0159e9b3 or s3,s3,s5 -800139fc: 413f0f33 sub t5,t5,s3 -80013a00: 03e12e23 sw t5,60(sp) -80013a04: 00cf1f93 slli t6,t5,0xc -80013a08: 0a0fde63 bgez t6,80013ac4 <__subtf3+0x1300> -80013a0c: 40e78733 sub a4,a5,a4 -80013a10: 40d606b3 sub a3,a2,a3 -80013a14: 00e7b5b3 sltu a1,a5,a4 -80013a18: 40b685b3 sub a1,a3,a1 -80013a1c: 02b12a23 sw a1,52(sp) -80013a20: 02e12823 sw a4,48(sp) -80013a24: 00d63633 sltu a2,a2,a3 -80013a28: 00000593 li a1,0 -80013a2c: 00e7f463 bgeu a5,a4,80013a34 <__subtf3+0x1270> -80013a30: 0016b593 seqz a1,a3 -80013a34: 41130733 sub a4,t1,a7 -80013a38: 00c5e633 or a2,a1,a2 -80013a3c: 00e336b3 sltu a3,t1,a4 -80013a40: 40c70733 sub a4,a4,a2 -80013a44: 02e12c23 sw a4,56(sp) -80013a48: 00060463 beqz a2,80013a50 <__subtf3+0x128c> -80013a4c: 0013b513 seqz a0,t2 -80013a50: 41de0733 sub a4,t3,t4 -80013a54: 00d567b3 or a5,a0,a3 -80013a58: 40f707b3 sub a5,a4,a5 -80013a5c: 02f12e23 sw a5,60(sp) -80013a60: 00080913 mv s2,a6 -80013a64: 03c12503 lw a0,60(sp) -80013a68: 06050863 beqz a0,80013ad8 <__subtf3+0x1314> -80013a6c: 291000ef jal ra,800144fc <__clzsi2> -80013a70: ff450513 addi a0,a0,-12 -80013a74: 02000693 li a3,32 -80013a78: 02d56833 rem a6,a0,a3 -80013a7c: 02d547b3 div a5,a0,a3 -80013a80: 08080863 beqz a6,80013b10 <__subtf3+0x134c> -80013a84: ffc00713 li a4,-4 -80013a88: 03010313 addi t1,sp,48 -80013a8c: 00279593 slli a1,a5,0x2 -80013a90: 410686b3 sub a3,a3,a6 -80013a94: 02e78733 mul a4,a5,a4 -80013a98: 00c70713 addi a4,a4,12 -80013a9c: 00e30733 add a4,t1,a4 -80013aa0: 0ae31063 bne t1,a4,80013b40 <__subtf3+0x137c> -80013aa4: 04010713 addi a4,sp,64 -80013aa8: 00b705b3 add a1,a4,a1 -80013aac: 03012703 lw a4,48(sp) -80013ab0: fff78793 addi a5,a5,-1 -80013ab4: 01071833 sll a6,a4,a6 -80013ab8: ff05a823 sw a6,-16(a1) -80013abc: fff00693 li a3,-1 -80013ac0: 0b80006f j 80013b78 <__subtf3+0x13b4> -80013ac4: 0055e5b3 or a1,a1,t0 -80013ac8: 0145e5b3 or a1,a1,s4 -80013acc: 01e5e5b3 or a1,a1,t5 -80013ad0: d2058ae3 beqz a1,80013804 <__subtf3+0x1040> -80013ad4: f91ff06f j 80013a64 <__subtf3+0x12a0> -80013ad8: 03812503 lw a0,56(sp) -80013adc: 00050863 beqz a0,80013aec <__subtf3+0x1328> -80013ae0: 21d000ef jal ra,800144fc <__clzsi2> -80013ae4: 02050513 addi a0,a0,32 -80013ae8: f89ff06f j 80013a70 <__subtf3+0x12ac> -80013aec: 03412503 lw a0,52(sp) -80013af0: 00050863 beqz a0,80013b00 <__subtf3+0x133c> -80013af4: 209000ef jal ra,800144fc <__clzsi2> -80013af8: 04050513 addi a0,a0,64 -80013afc: f75ff06f j 80013a70 <__subtf3+0x12ac> -80013b00: 03012503 lw a0,48(sp) -80013b04: 1f9000ef jal ra,800144fc <__clzsi2> -80013b08: 06050513 addi a0,a0,96 -80013b0c: f65ff06f j 80013a70 <__subtf3+0x12ac> -80013b10: ffc00613 li a2,-4 -80013b14: 02c78633 mul a2,a5,a2 -80013b18: 03c10713 addi a4,sp,60 -80013b1c: 00300693 li a3,3 -80013b20: 00c705b3 add a1,a4,a2 -80013b24: 0005a583 lw a1,0(a1) -80013b28: fff68693 addi a3,a3,-1 -80013b2c: ffc70713 addi a4,a4,-4 -80013b30: 00b72223 sw a1,4(a4) -80013b34: fef6d6e3 bge a3,a5,80013b20 <__subtf3+0x135c> -80013b38: fff78793 addi a5,a5,-1 -80013b3c: f81ff06f j 80013abc <__subtf3+0x12f8> -80013b40: ffc72603 lw a2,-4(a4) -80013b44: 00072883 lw a7,0(a4) -80013b48: 00b70e33 add t3,a4,a1 -80013b4c: 00d65633 srl a2,a2,a3 -80013b50: 010898b3 sll a7,a7,a6 -80013b54: 01166633 or a2,a2,a7 -80013b58: 00ce2023 sw a2,0(t3) -80013b5c: ffc70713 addi a4,a4,-4 -80013b60: f41ff06f j 80013aa0 <__subtf3+0x12dc> -80013b64: 00279713 slli a4,a5,0x2 -80013b68: 03010613 addi a2,sp,48 -80013b6c: 00e60733 add a4,a2,a4 -80013b70: 00072023 sw zero,0(a4) -80013b74: fff78793 addi a5,a5,-1 -80013b78: fed796e3 bne a5,a3,80013b64 <__subtf3+0x13a0> -80013b7c: 12854e63 blt a0,s0,80013cb8 <__subtf3+0x14f4> -80013b80: 40850433 sub s0,a0,s0 -80013b84: 00140413 addi s0,s0,1 -80013b88: 02000793 li a5,32 -80013b8c: 02f44833 div a6,s0,a5 -80013b90: 00000513 li a0,0 -80013b94: 00000713 li a4,0 -80013b98: 02f46433 rem s0,s0,a5 -80013b9c: 05074263 blt a4,a6,80013be0 <__subtf3+0x141c> -80013ba0: 00080693 mv a3,a6 -80013ba4: 00085463 bgez a6,80013bac <__subtf3+0x13e8> -80013ba8: 00000693 li a3,0 -80013bac: 00281713 slli a4,a6,0x2 -80013bb0: 04041663 bnez s0,80013bfc <__subtf3+0x1438> -80013bb4: 00300793 li a5,3 -80013bb8: 03010693 addi a3,sp,48 -80013bbc: 41078833 sub a6,a5,a6 -80013bc0: 00e687b3 add a5,a3,a4 -80013bc4: 0007a783 lw a5,0(a5) -80013bc8: 00140413 addi s0,s0,1 -80013bcc: 00468693 addi a3,a3,4 -80013bd0: fef6ae23 sw a5,-4(a3) -80013bd4: fe8856e3 bge a6,s0,80013bc0 <__subtf3+0x13fc> -80013bd8: 00300713 li a4,3 -80013bdc: 0c00006f j 80013c9c <__subtf3+0x14d8> -80013be0: 00271793 slli a5,a4,0x2 -80013be4: 03010693 addi a3,sp,48 -80013be8: 00f687b3 add a5,a3,a5 -80013bec: 0007a783 lw a5,0(a5) -80013bf0: 00170713 addi a4,a4,1 -80013bf4: 00f56533 or a0,a0,a5 -80013bf8: fa5ff06f j 80013b9c <__subtf3+0x13d8> -80013bfc: 04010793 addi a5,sp,64 -80013c00: 00269693 slli a3,a3,0x2 -80013c04: 00d786b3 add a3,a5,a3 -80013c08: ff06a783 lw a5,-16(a3) -80013c0c: 02000593 li a1,32 -80013c10: 408585b3 sub a1,a1,s0 -80013c14: 00b797b3 sll a5,a5,a1 -80013c18: 00f56533 or a0,a0,a5 -80013c1c: 03010793 addi a5,sp,48 -80013c20: 00e78733 add a4,a5,a4 -80013c24: 00300793 li a5,3 -80013c28: 00000613 li a2,0 -80013c2c: 410787b3 sub a5,a5,a6 -80013c30: 00470713 addi a4,a4,4 -80013c34: 02f64463 blt a2,a5,80013c5c <__subtf3+0x1498> -80013c38: 04010713 addi a4,sp,64 -80013c3c: 00279793 slli a5,a5,0x2 -80013c40: 00f707b3 add a5,a4,a5 -80013c44: 03c12703 lw a4,60(sp) -80013c48: 00875433 srl s0,a4,s0 -80013c4c: fe87a823 sw s0,-16(a5) -80013c50: 00400413 li s0,4 -80013c54: 41040433 sub s0,s0,a6 -80013c58: f81ff06f j 80013bd8 <__subtf3+0x1414> -80013c5c: 00261893 slli a7,a2,0x2 -80013c60: 03010693 addi a3,sp,48 -80013c64: 011688b3 add a7,a3,a7 -80013c68: 00072303 lw t1,0(a4) -80013c6c: ffc72683 lw a3,-4(a4) -80013c70: 00160613 addi a2,a2,1 -80013c74: 00b31333 sll t1,t1,a1 -80013c78: 0086d6b3 srl a3,a3,s0 -80013c7c: 0066e6b3 or a3,a3,t1 -80013c80: 00d8a023 sw a3,0(a7) -80013c84: fadff06f j 80013c30 <__subtf3+0x146c> -80013c88: 00241793 slli a5,s0,0x2 -80013c8c: 03010693 addi a3,sp,48 -80013c90: 00f687b3 add a5,a3,a5 -80013c94: 0007a023 sw zero,0(a5) -80013c98: 00140413 addi s0,s0,1 -80013c9c: fe8756e3 bge a4,s0,80013c88 <__subtf3+0x14c4> -80013ca0: 03012703 lw a4,48(sp) -80013ca4: 00a037b3 snez a5,a0 -80013ca8: 00000413 li s0,0 -80013cac: 00f767b3 or a5,a4,a5 -80013cb0: 02f12823 sw a5,48(sp) -80013cb4: fa9fe06f j 80012c5c <__subtf3+0x498> -80013cb8: 03c12783 lw a5,60(sp) -80013cbc: fff80737 lui a4,0xfff80 -80013cc0: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff69287> -80013cc4: 40a40433 sub s0,s0,a0 -80013cc8: 00e7f7b3 and a5,a5,a4 -80013ccc: d35fe06f j 80012a00 <__subtf3+0x23c> -80013cd0: 02012e23 sw zero,60(sp) -80013cd4: 02012c23 sw zero,56(sp) -80013cd8: 02012a23 sw zero,52(sp) -80013cdc: 02012823 sw zero,48(sp) -80013ce0: ffdfe06f j 80012cdc <__subtf3+0x518> - -80013ce4 <__fixtfsi>: -80013ce4: 00c52703 lw a4,12(a0) -80013ce8: 00852783 lw a5,8(a0) -80013cec: 00452683 lw a3,4(a0) -80013cf0: 00052603 lw a2,0(a0) -80013cf4: fe010113 addi sp,sp,-32 -80013cf8: 00f12423 sw a5,8(sp) -80013cfc: 00e12623 sw a4,12(sp) -80013d00: 00f12c23 sw a5,24(sp) -80013d04: 01071593 slli a1,a4,0x10 -80013d08: 00171793 slli a5,a4,0x1 -80013d0c: 01f75813 srli a6,a4,0x1f -80013d10: 00004737 lui a4,0x4 -80013d14: 00d12223 sw a3,4(sp) -80013d18: 00d12a23 sw a3,20(sp) -80013d1c: 00c12023 sw a2,0(sp) -80013d20: 0117d693 srli a3,a5,0x11 -80013d24: 00c12823 sw a2,16(sp) -80013d28: ffe70793 addi a5,a4,-2 # 3ffe <_start-0x7fffc002> -80013d2c: 00000513 li a0,0 -80013d30: 00d7dc63 bge a5,a3,80013d48 <__fixtfsi+0x64> -80013d34: 01d70793 addi a5,a4,29 -80013d38: 00d7dc63 bge a5,a3,80013d50 <__fixtfsi+0x6c> -80013d3c: 80000537 lui a0,0x80000 -80013d40: fff54513 not a0,a0 -80013d44: 00a80533 add a0,a6,a0 -80013d48: 02010113 addi sp,sp,32 -80013d4c: 00008067 ret -80013d50: 000107b7 lui a5,0x10 -80013d54: 0105d593 srli a1,a1,0x10 -80013d58: 00f5e5b3 or a1,a1,a5 -80013d5c: 06f70793 addi a5,a4,111 -80013d60: 40d787b3 sub a5,a5,a3 -80013d64: 4057d713 srai a4,a5,0x5 -80013d68: 00b12e23 sw a1,28(sp) -80013d6c: 01f7f793 andi a5,a5,31 -80013d70: 08079863 bnez a5,80013e00 <__fixtfsi+0x11c> -80013d74: 00271793 slli a5,a4,0x2 -80013d78: 02010693 addi a3,sp,32 -80013d7c: 00f687b3 add a5,a3,a5 -80013d80: ff07a783 lw a5,-16(a5) # fff0 <_start-0x7fff0010> -80013d84: 00200613 li a2,2 -80013d88: 00f12823 sw a5,16(sp) -80013d8c: 00200793 li a5,2 -80013d90: 00e78463 beq a5,a4,80013d98 <__fixtfsi+0xb4> -80013d94: 00100613 li a2,1 -80013d98: 00400713 li a4,4 -80013d9c: 00261793 slli a5,a2,0x2 -80013da0: 01010693 addi a3,sp,16 -80013da4: 00f687b3 add a5,a3,a5 -80013da8: 0007a023 sw zero,0(a5) -80013dac: 00160613 addi a2,a2,1 -80013db0: fee616e3 bne a2,a4,80013d9c <__fixtfsi+0xb8> -80013db4: 01012503 lw a0,16(sp) -80013db8: f80808e3 beqz a6,80013d48 <__fixtfsi+0x64> -80013dbc: 40a00533 neg a0,a0 -80013dc0: f89ff06f j 80013d48 <__fixtfsi+0x64> -80013dc4: ff062683 lw a3,-16(a2) -80013dc8: ff072303 lw t1,-16(a4) -80013dcc: 011696b3 sll a3,a3,a7 -80013dd0: 00f35333 srl t1,t1,a5 -80013dd4: 0066e6b3 or a3,a3,t1 -80013dd8: 00d12823 sw a3,16(sp) -80013ddc: 00100693 li a3,1 -80013de0: fea6c2e3 blt a3,a0,80013dc4 <__fixtfsi+0xe0> -80013de4: 00168613 addi a2,a3,1 -80013de8: 02010713 addi a4,sp,32 -80013dec: 00269693 slli a3,a3,0x2 -80013df0: 00d706b3 add a3,a4,a3 -80013df4: 00f5d7b3 srl a5,a1,a5 -80013df8: fef6a823 sw a5,-16(a3) -80013dfc: f9dff06f j 80013d98 <__fixtfsi+0xb4> -80013e00: 00170613 addi a2,a4,1 -80013e04: 02010893 addi a7,sp,32 -80013e08: 00300513 li a0,3 -80013e0c: 00261613 slli a2,a2,0x2 -80013e10: 40e50533 sub a0,a0,a4 -80013e14: 00c88633 add a2,a7,a2 -80013e18: 00271713 slli a4,a4,0x2 -80013e1c: 02000893 li a7,32 -80013e20: 02010313 addi t1,sp,32 -80013e24: 00000693 li a3,0 -80013e28: 40f888b3 sub a7,a7,a5 -80013e2c: 00e30733 add a4,t1,a4 -80013e30: fb1ff06f j 80013de0 <__fixtfsi+0xfc> - -80013e34 <__floatsitf>: -80013e34: fd010113 addi sp,sp,-48 -80013e38: 02912223 sw s1,36(sp) -80013e3c: 02112623 sw ra,44(sp) -80013e40: 02812423 sw s0,40(sp) -80013e44: 03212023 sw s2,32(sp) -80013e48: 00050493 mv s1,a0 -80013e4c: 14058c63 beqz a1,80013fa4 <__floatsitf+0x170> -80013e50: 41f5d793 srai a5,a1,0x1f -80013e54: 00b7c433 xor s0,a5,a1 -80013e58: 40f40433 sub s0,s0,a5 -80013e5c: 00040513 mv a0,s0 -80013e60: 01f5d913 srli s2,a1,0x1f -80013e64: 698000ef jal ra,800144fc <__clzsi2> -80013e68: 000045b7 lui a1,0x4 -80013e6c: 01e58593 addi a1,a1,30 # 401e <_start-0x7fffbfe2> -80013e70: 40a585b3 sub a1,a1,a0 -80013e74: 05150513 addi a0,a0,81 # 80000051 <__BSS_END__+0xfffe92d9> -80013e78: 00812823 sw s0,16(sp) -80013e7c: 00012a23 sw zero,20(sp) -80013e80: 00012c23 sw zero,24(sp) -80013e84: 00012e23 sw zero,28(sp) -80013e88: 01f57693 andi a3,a0,31 -80013e8c: 04068063 beqz a3,80013ecc <__floatsitf+0x98> -80013e90: 05f00713 li a4,95 -80013e94: 00300793 li a5,3 -80013e98: 00a74c63 blt a4,a0,80013eb0 <__floatsitf+0x7c> -80013e9c: 02000793 li a5,32 -80013ea0: 40d787b3 sub a5,a5,a3 -80013ea4: 00f457b3 srl a5,s0,a5 -80013ea8: 00f12e23 sw a5,28(sp) -80013eac: 00200793 li a5,2 -80013eb0: fff78713 addi a4,a5,-1 -80013eb4: 02010613 addi a2,sp,32 -80013eb8: 00279793 slli a5,a5,0x2 -80013ebc: 00f607b3 add a5,a2,a5 -80013ec0: 00d41433 sll s0,s0,a3 -80013ec4: fe87a823 sw s0,-16(a5) -80013ec8: 0500006f j 80013f18 <__floatsitf+0xe4> -80013ecc: 40555693 srai a3,a0,0x5 -80013ed0: 00300713 li a4,3 -80013ed4: 40d70733 sub a4,a4,a3 -80013ed8: 02010793 addi a5,sp,32 -80013edc: 00271713 slli a4,a4,0x2 -80013ee0: 00e78733 add a4,a5,a4 -80013ee4: ff072783 lw a5,-16(a4) -80013ee8: 00200713 li a4,2 -80013eec: 00f12e23 sw a5,28(sp) -80013ef0: 05f00793 li a5,95 -80013ef4: 02a7c263 blt a5,a0,80013f18 <__floatsitf+0xe4> -80013ef8: 00200793 li a5,2 -80013efc: 40d787b3 sub a5,a5,a3 -80013f00: 02010713 addi a4,sp,32 -80013f04: 00279793 slli a5,a5,0x2 -80013f08: 00f707b3 add a5,a4,a5 -80013f0c: ff07a783 lw a5,-16(a5) -80013f10: 00100713 li a4,1 -80013f14: 00f12c23 sw a5,24(sp) -80013f18: fff00693 li a3,-1 -80013f1c: 00271793 slli a5,a4,0x2 -80013f20: 01010613 addi a2,sp,16 -80013f24: 00f607b3 add a5,a2,a5 -80013f28: 0007a023 sw zero,0(a5) -80013f2c: fff70713 addi a4,a4,-1 -80013f30: fed716e3 bne a4,a3,80013f1c <__floatsitf+0xe8> -80013f34: 01c12783 lw a5,28(sp) -80013f38: 01159593 slli a1,a1,0x11 -80013f3c: 80010737 lui a4,0x80010 -80013f40: 00f11623 sh a5,12(sp) -80013f44: 00c12783 lw a5,12(sp) -80013f48: 0115d593 srli a1,a1,0x11 -80013f4c: fff70713 addi a4,a4,-1 # 8000ffff <__BSS_END__+0xffff9287> -80013f50: 00e7f7b3 and a5,a5,a4 -80013f54: 01059593 slli a1,a1,0x10 -80013f58: 00b7e5b3 or a1,a5,a1 -80013f5c: 01012783 lw a5,16(sp) -80013f60: 00159593 slli a1,a1,0x1 -80013f64: 01f91913 slli s2,s2,0x1f -80013f68: 00f4a023 sw a5,0(s1) -80013f6c: 01412783 lw a5,20(sp) -80013f70: 02c12083 lw ra,44(sp) -80013f74: 02812403 lw s0,40(sp) -80013f78: 00f4a223 sw a5,4(s1) -80013f7c: 01812783 lw a5,24(sp) -80013f80: 0015d593 srli a1,a1,0x1 -80013f84: 0125e5b3 or a1,a1,s2 -80013f88: 00f4a423 sw a5,8(s1) -80013f8c: 00b4a623 sw a1,12(s1) -80013f90: 00048513 mv a0,s1 -80013f94: 02012903 lw s2,32(sp) -80013f98: 02412483 lw s1,36(sp) -80013f9c: 03010113 addi sp,sp,48 -80013fa0: 00008067 ret -80013fa4: 00012e23 sw zero,28(sp) -80013fa8: 00012c23 sw zero,24(sp) -80013fac: 00012a23 sw zero,20(sp) -80013fb0: 00012823 sw zero,16(sp) -80013fb4: 00000913 li s2,0 -80013fb8: f7dff06f j 80013f34 <__floatsitf+0x100> - -80013fbc <__extenddftf2>: -80013fbc: 01465793 srli a5,a2,0x14 -80013fc0: 00c61713 slli a4,a2,0xc -80013fc4: 7ff7f793 andi a5,a5,2047 -80013fc8: fd010113 addi sp,sp,-48 -80013fcc: 00c75713 srli a4,a4,0xc -80013fd0: 00178693 addi a3,a5,1 -80013fd4: 02812423 sw s0,40(sp) -80013fd8: 02912223 sw s1,36(sp) -80013fdc: 02112623 sw ra,44(sp) -80013fe0: 00b12823 sw a1,16(sp) -80013fe4: 00e12a23 sw a4,20(sp) -80013fe8: 00012e23 sw zero,28(sp) -80013fec: 00012c23 sw zero,24(sp) -80013ff0: 7fe6f693 andi a3,a3,2046 -80013ff4: 00050493 mv s1,a0 -80013ff8: 01f65413 srli s0,a2,0x1f -80013ffc: 0a068063 beqz a3,8001409c <__extenddftf2+0xe0> -80014000: 000046b7 lui a3,0x4 -80014004: c0068693 addi a3,a3,-1024 # 3c00 <_start-0x7fffc400> -80014008: 0045d513 srli a0,a1,0x4 -8001400c: 00d787b3 add a5,a5,a3 -80014010: 00475693 srli a3,a4,0x4 -80014014: 01c71713 slli a4,a4,0x1c -80014018: 00a76733 or a4,a4,a0 -8001401c: 01c59593 slli a1,a1,0x1c -80014020: 00d12e23 sw a3,28(sp) -80014024: 00e12c23 sw a4,24(sp) -80014028: 00b12a23 sw a1,20(sp) -8001402c: 00012823 sw zero,16(sp) -80014030: 01c12703 lw a4,28(sp) -80014034: 01179793 slli a5,a5,0x11 -80014038: 800106b7 lui a3,0x80010 -8001403c: 00e11623 sh a4,12(sp) -80014040: 00c12703 lw a4,12(sp) -80014044: 0117d793 srli a5,a5,0x11 -80014048: fff68693 addi a3,a3,-1 # 8000ffff <__BSS_END__+0xffff9287> -8001404c: 00d77733 and a4,a4,a3 -80014050: 01079793 slli a5,a5,0x10 -80014054: 00f767b3 or a5,a4,a5 -80014058: 01012703 lw a4,16(sp) -8001405c: 00179793 slli a5,a5,0x1 -80014060: 01f41413 slli s0,s0,0x1f -80014064: 00e4a023 sw a4,0(s1) -80014068: 01412703 lw a4,20(sp) -8001406c: 0017d793 srli a5,a5,0x1 -80014070: 0087e7b3 or a5,a5,s0 -80014074: 00e4a223 sw a4,4(s1) -80014078: 01812703 lw a4,24(sp) -8001407c: 02c12083 lw ra,44(sp) -80014080: 02812403 lw s0,40(sp) -80014084: 00e4a423 sw a4,8(s1) -80014088: 00f4a623 sw a5,12(s1) -8001408c: 00048513 mv a0,s1 -80014090: 02412483 lw s1,36(sp) -80014094: 03010113 addi sp,sp,48 -80014098: 00008067 ret -8001409c: 00b76533 or a0,a4,a1 -800140a0: 0e079663 bnez a5,8001418c <__extenddftf2+0x1d0> -800140a4: f80506e3 beqz a0,80014030 <__extenddftf2+0x74> -800140a8: 04070e63 beqz a4,80014104 <__extenddftf2+0x148> -800140ac: 00070513 mv a0,a4 -800140b0: 44c000ef jal ra,800144fc <__clzsi2> -800140b4: 03150613 addi a2,a0,49 -800140b8: 40565713 srai a4,a2,0x5 -800140bc: 01f67613 andi a2,a2,31 -800140c0: 04060863 beqz a2,80014110 <__extenddftf2+0x154> -800140c4: ffc00693 li a3,-4 -800140c8: 02d706b3 mul a3,a4,a3 -800140cc: 01010313 addi t1,sp,16 -800140d0: 02000793 li a5,32 -800140d4: 00271813 slli a6,a4,0x2 -800140d8: 40c787b3 sub a5,a5,a2 -800140dc: 00c68693 addi a3,a3,12 -800140e0: 00d306b3 add a3,t1,a3 -800140e4: 08d31263 bne t1,a3,80014168 <__extenddftf2+0x1ac> -800140e8: 02010793 addi a5,sp,32 -800140ec: 01078833 add a6,a5,a6 -800140f0: 01012783 lw a5,16(sp) -800140f4: fff70713 addi a4,a4,-1 -800140f8: 00c79633 sll a2,a5,a2 -800140fc: fec82823 sw a2,-16(a6) -80014100: 03c0006f j 8001413c <__extenddftf2+0x180> -80014104: 3f8000ef jal ra,800144fc <__clzsi2> -80014108: 02050513 addi a0,a0,32 -8001410c: fa9ff06f j 800140b4 <__extenddftf2+0xf8> -80014110: ffc00613 li a2,-4 -80014114: 02c70633 mul a2,a4,a2 -80014118: 01c10693 addi a3,sp,28 -8001411c: 00300793 li a5,3 -80014120: 00c685b3 add a1,a3,a2 -80014124: 0005a583 lw a1,0(a1) -80014128: fff78793 addi a5,a5,-1 -8001412c: ffc68693 addi a3,a3,-4 -80014130: 00b6a223 sw a1,4(a3) -80014134: fee7d6e3 bge a5,a4,80014120 <__extenddftf2+0x164> -80014138: fff70713 addi a4,a4,-1 -8001413c: fff00693 li a3,-1 -80014140: 00271793 slli a5,a4,0x2 -80014144: 01010613 addi a2,sp,16 -80014148: 00f607b3 add a5,a2,a5 -8001414c: 0007a023 sw zero,0(a5) -80014150: fff70713 addi a4,a4,-1 -80014154: fed716e3 bne a4,a3,80014140 <__extenddftf2+0x184> -80014158: 000047b7 lui a5,0x4 -8001415c: c0c78793 addi a5,a5,-1012 # 3c0c <_start-0x7fffc3f4> -80014160: 40a787b3 sub a5,a5,a0 -80014164: ecdff06f j 80014030 <__extenddftf2+0x74> -80014168: ffc6a583 lw a1,-4(a3) -8001416c: 0006a883 lw a7,0(a3) -80014170: 01068e33 add t3,a3,a6 -80014174: 00f5d5b3 srl a1,a1,a5 -80014178: 00c898b3 sll a7,a7,a2 -8001417c: 0115e5b3 or a1,a1,a7 -80014180: 00be2023 sw a1,0(t3) -80014184: ffc68693 addi a3,a3,-4 -80014188: f5dff06f j 800140e4 <__extenddftf2+0x128> -8001418c: 000087b7 lui a5,0x8 -80014190: 02050863 beqz a0,800141c0 <__extenddftf2+0x204> -80014194: 01c71793 slli a5,a4,0x1c -80014198: 0045d693 srli a3,a1,0x4 -8001419c: 00d7e7b3 or a5,a5,a3 -800141a0: 00f12c23 sw a5,24(sp) -800141a4: 00475713 srli a4,a4,0x4 -800141a8: 000087b7 lui a5,0x8 -800141ac: 01c59593 slli a1,a1,0x1c -800141b0: 00f76733 or a4,a4,a5 -800141b4: 00b12a23 sw a1,20(sp) -800141b8: 00012823 sw zero,16(sp) -800141bc: 00e12e23 sw a4,28(sp) -800141c0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800141c4: e6dff06f j 80014030 <__extenddftf2+0x74> - -800141c8 <__trunctfdf2>: -800141c8: 00c52583 lw a1,12(a0) -800141cc: 00852783 lw a5,8(a0) -800141d0: 00452703 lw a4,4(a0) -800141d4: fe010113 addi sp,sp,-32 -800141d8: 00052683 lw a3,0(a0) -800141dc: 00f12423 sw a5,8(sp) -800141e0: 00f12c23 sw a5,24(sp) -800141e4: 01059793 slli a5,a1,0x10 -800141e8: 00e12223 sw a4,4(sp) -800141ec: 00e12a23 sw a4,20(sp) -800141f0: 0107d793 srli a5,a5,0x10 -800141f4: 00159713 slli a4,a1,0x1 -800141f8: 00b12623 sw a1,12(sp) -800141fc: 00d12023 sw a3,0(sp) -80014200: 00d12823 sw a3,16(sp) -80014204: 00f12e23 sw a5,28(sp) -80014208: 01175713 srli a4,a4,0x11 -8001420c: 01f5d593 srli a1,a1,0x1f -80014210: 01010313 addi t1,sp,16 -80014214: 01c10613 addi a2,sp,28 -80014218: 00062783 lw a5,0(a2) -8001421c: ffc62683 lw a3,-4(a2) -80014220: ffc60613 addi a2,a2,-4 -80014224: 00379793 slli a5,a5,0x3 -80014228: 01d6d693 srli a3,a3,0x1d -8001422c: 00d7e7b3 or a5,a5,a3 -80014230: 00f62223 sw a5,4(a2) -80014234: fec312e3 bne t1,a2,80014218 <__trunctfdf2+0x50> -80014238: 01012683 lw a3,16(sp) -8001423c: 00170793 addi a5,a4,1 -80014240: 00369513 slli a0,a3,0x3 -80014244: 000086b7 lui a3,0x8 -80014248: ffe68693 addi a3,a3,-2 # 7ffe <_start-0x7fff8002> -8001424c: 00a12823 sw a0,16(sp) -80014250: 00d7f7b3 and a5,a5,a3 -80014254: 1a078a63 beqz a5,80014408 <__trunctfdf2+0x240> -80014258: ffffc7b7 lui a5,0xffffc -8001425c: 40078793 addi a5,a5,1024 # ffffc400 <__BSS_END__+0x7ffe5688> -80014260: 00f70733 add a4,a4,a5 -80014264: 7fe00793 li a5,2046 -80014268: 1ee7cc63 blt a5,a4,80014460 <__trunctfdf2+0x298> -8001426c: 06e05863 blez a4,800142dc <__trunctfdf2+0x114> -80014270: 01812803 lw a6,24(sp) -80014274: 01c12603 lw a2,28(sp) -80014278: 01412783 lw a5,20(sp) -8001427c: 01c85693 srli a3,a6,0x1c -80014280: 00461613 slli a2,a2,0x4 -80014284: 00d66633 or a2,a2,a3 -80014288: 00479693 slli a3,a5,0x4 -8001428c: 00a6e6b3 or a3,a3,a0 -80014290: 01c7d793 srli a5,a5,0x1c -80014294: 00481813 slli a6,a6,0x4 -80014298: 00d036b3 snez a3,a3 -8001429c: 0107e7b3 or a5,a5,a6 -800142a0: 00f6e6b3 or a3,a3,a5 -800142a4: 00c12a23 sw a2,20(sp) -800142a8: 00d12823 sw a3,16(sp) -800142ac: 01012683 lw a3,16(sp) -800142b0: 01412783 lw a5,20(sp) -800142b4: 0076f613 andi a2,a3,7 -800142b8: 1a060a63 beqz a2,8001446c <__trunctfdf2+0x2a4> -800142bc: 00f6f613 andi a2,a3,15 -800142c0: 00400513 li a0,4 -800142c4: 1aa60463 beq a2,a0,8001446c <__trunctfdf2+0x2a4> -800142c8: 00468613 addi a2,a3,4 -800142cc: 00d636b3 sltu a3,a2,a3 -800142d0: 00d787b3 add a5,a5,a3 -800142d4: 00060693 mv a3,a2 -800142d8: 1940006f j 8001446c <__trunctfdf2+0x2a4> -800142dc: fcc00793 li a5,-52 -800142e0: 00f75c63 bge a4,a5,800142f8 <__trunctfdf2+0x130> -800142e4: 00012a23 sw zero,20(sp) -800142e8: 00100793 li a5,1 -800142ec: 00f12823 sw a5,16(sp) -800142f0: 00000713 li a4,0 -800142f4: fb9ff06f j 800142ac <__trunctfdf2+0xe4> -800142f8: 01c12783 lw a5,28(sp) -800142fc: 000806b7 lui a3,0x80 -80014300: 00000e13 li t3,0 -80014304: 00d7e7b3 or a5,a5,a3 -80014308: 00f12e23 sw a5,28(sp) -8001430c: 03d00793 li a5,61 -80014310: 40e78733 sub a4,a5,a4 -80014314: 40575513 srai a0,a4,0x5 -80014318: 00030693 mv a3,t1 -8001431c: 01f77713 andi a4,a4,31 -80014320: 00000793 li a5,0 -80014324: 0006a803 lw a6,0(a3) # 80000 <_start-0x7ff80000> -80014328: 00178793 addi a5,a5,1 -8001432c: 00468693 addi a3,a3,4 -80014330: 010e6e33 or t3,t3,a6 -80014334: fef518e3 bne a0,a5,80014324 <__trunctfdf2+0x15c> -80014338: 00251693 slli a3,a0,0x2 -8001433c: 04071663 bnez a4,80014388 <__trunctfdf2+0x1c0> -80014340: 00300793 li a5,3 -80014344: 40a78533 sub a0,a5,a0 -80014348: 00d607b3 add a5,a2,a3 -8001434c: 0007a783 lw a5,0(a5) -80014350: 00170713 addi a4,a4,1 -80014354: 00460613 addi a2,a2,4 -80014358: fef62e23 sw a5,-4(a2) -8001435c: fee556e3 bge a0,a4,80014348 <__trunctfdf2+0x180> -80014360: 00400693 li a3,4 -80014364: 00271793 slli a5,a4,0x2 -80014368: 00f307b3 add a5,t1,a5 -8001436c: 0007a023 sw zero,0(a5) -80014370: 00170713 addi a4,a4,1 -80014374: fed718e3 bne a4,a3,80014364 <__trunctfdf2+0x19c> -80014378: 01012703 lw a4,16(sp) -8001437c: 01c037b3 snez a5,t3 -80014380: 00f767b3 or a5,a4,a5 -80014384: f69ff06f j 800142ec <__trunctfdf2+0x124> -80014388: 02010793 addi a5,sp,32 -8001438c: 00d787b3 add a5,a5,a3 -80014390: ff07a783 lw a5,-16(a5) -80014394: 02000893 li a7,32 -80014398: 40e888b3 sub a7,a7,a4 -8001439c: 011797b3 sll a5,a5,a7 -800143a0: 00fe6e33 or t3,t3,a5 -800143a4: 00300793 li a5,3 -800143a8: 00d306b3 add a3,t1,a3 -800143ac: 00000813 li a6,0 -800143b0: 40a787b3 sub a5,a5,a0 -800143b4: 00468693 addi a3,a3,4 -800143b8: 02f84463 blt a6,a5,800143e0 <__trunctfdf2+0x218> -800143bc: 02010693 addi a3,sp,32 -800143c0: 00279793 slli a5,a5,0x2 -800143c4: 00f687b3 add a5,a3,a5 -800143c8: 01c12683 lw a3,28(sp) -800143cc: 00e6d733 srl a4,a3,a4 -800143d0: fee7a823 sw a4,-16(a5) -800143d4: 00400713 li a4,4 -800143d8: 40a70733 sub a4,a4,a0 -800143dc: f85ff06f j 80014360 <__trunctfdf2+0x198> -800143e0: ffc6a603 lw a2,-4(a3) -800143e4: 0006af03 lw t5,0(a3) -800143e8: 00281e93 slli t4,a6,0x2 -800143ec: 00e65633 srl a2,a2,a4 -800143f0: 011f1f33 sll t5,t5,a7 -800143f4: 01d30eb3 add t4,t1,t4 -800143f8: 01e66633 or a2,a2,t5 -800143fc: 00cea023 sw a2,0(t4) -80014400: 00180813 addi a6,a6,1 -80014404: fb1ff06f j 800143b4 <__trunctfdf2+0x1ec> -80014408: 01412603 lw a2,20(sp) -8001440c: 01812783 lw a5,24(sp) -80014410: 01c12803 lw a6,28(sp) -80014414: 00f666b3 or a3,a2,a5 -80014418: 0106e6b3 or a3,a3,a6 -8001441c: 00a6e6b3 or a3,a3,a0 -80014420: 00071863 bnez a4,80014430 <__trunctfdf2+0x268> -80014424: 00d036b3 snez a3,a3 -80014428: 00000793 li a5,0 -8001442c: e89ff06f j 800142b4 <__trunctfdf2+0xec> -80014430: 0a068c63 beqz a3,800144e8 <__trunctfdf2+0x320> -80014434: 01c65693 srli a3,a2,0x1c -80014438: 00481813 slli a6,a6,0x4 -8001443c: 00479613 slli a2,a5,0x4 -80014440: 01c7d793 srli a5,a5,0x1c -80014444: 00400737 lui a4,0x400 -80014448: 00c6e6b3 or a3,a3,a2 -8001444c: 0107e7b3 or a5,a5,a6 -80014450: 00e7e7b3 or a5,a5,a4 -80014454: ff86f693 andi a3,a3,-8 -80014458: 7ff00713 li a4,2047 -8001445c: e59ff06f j 800142b4 <__trunctfdf2+0xec> -80014460: 00000793 li a5,0 -80014464: 00000693 li a3,0 -80014468: 7ff00713 li a4,2047 -8001446c: 00879613 slli a2,a5,0x8 -80014470: 00065e63 bgez a2,8001448c <__trunctfdf2+0x2c4> -80014474: 00170713 addi a4,a4,1 # 400001 <_start-0x7fbfffff> -80014478: 7ff00613 li a2,2047 -8001447c: 06c70a63 beq a4,a2,800144f0 <__trunctfdf2+0x328> -80014480: ff800637 lui a2,0xff800 -80014484: fff60613 addi a2,a2,-1 # ff7fffff <__BSS_END__+0x7f7e9287> -80014488: 00c7f7b3 and a5,a5,a2 -8001448c: 01d79613 slli a2,a5,0x1d -80014490: 0036d693 srli a3,a3,0x3 -80014494: 00d666b3 or a3,a2,a3 -80014498: 7ff00613 li a2,2047 -8001449c: 0037d793 srli a5,a5,0x3 -800144a0: 00c71e63 bne a4,a2,800144bc <__trunctfdf2+0x2f4> -800144a4: 00f6e6b3 or a3,a3,a5 -800144a8: 00000793 li a5,0 -800144ac: 00068863 beqz a3,800144bc <__trunctfdf2+0x2f4> -800144b0: 000807b7 lui a5,0x80 -800144b4: 00000693 li a3,0 -800144b8: 00000593 li a1,0 -800144bc: 00c79793 slli a5,a5,0xc -800144c0: 7ff77713 andi a4,a4,2047 -800144c4: 01471713 slli a4,a4,0x14 -800144c8: 00c7d793 srli a5,a5,0xc -800144cc: 01f59593 slli a1,a1,0x1f -800144d0: 00e7e7b3 or a5,a5,a4 -800144d4: 00b7e733 or a4,a5,a1 -800144d8: 00068513 mv a0,a3 -800144dc: 00070593 mv a1,a4 -800144e0: 02010113 addi sp,sp,32 -800144e4: 00008067 ret -800144e8: 00000793 li a5,0 -800144ec: f7dff06f j 80014468 <__trunctfdf2+0x2a0> -800144f0: 00000793 li a5,0 -800144f4: 00000693 li a3,0 -800144f8: f95ff06f j 8001448c <__trunctfdf2+0x2c4> - -800144fc <__clzsi2>: -800144fc: 000107b7 lui a5,0x10 -80014500: 02f57a63 bgeu a0,a5,80014534 <__clzsi2+0x38> -80014504: 0ff00793 li a5,255 -80014508: 00a7b7b3 sltu a5,a5,a0 -8001450c: 00379793 slli a5,a5,0x3 -80014510: 02000713 li a4,32 -80014514: 40f70733 sub a4,a4,a5 -80014518: 00f557b3 srl a5,a0,a5 -8001451c: 80015537 lui a0,0x80015 -80014520: 22450513 addi a0,a0,548 # 80015224 <__BSS_END__+0xffffe4ac> -80014524: 00a787b3 add a5,a5,a0 -80014528: 0007c503 lbu a0,0(a5) # 10000 <_start-0x7fff0000> -8001452c: 40a70533 sub a0,a4,a0 -80014530: 00008067 ret -80014534: 01000737 lui a4,0x1000 -80014538: 01000793 li a5,16 -8001453c: fce56ae3 bltu a0,a4,80014510 <__clzsi2+0x14> -80014540: 01800793 li a5,24 -80014544: fcdff06f j 80014510 <__clzsi2+0x14> - -Disassembly of section .rodata: - -80014548 : -80014548: 0030 addi a2,sp,8 -8001454a: 0000 unimp -8001454c: 0031 c.nop 12 -8001454e: 0000 unimp -80014550: 0032 c.slli zero,0xc -80014552: 0000 unimp -80014554: 00000033 add zero,zero,zero -80014558: 0034 addi a3,sp,8 -8001455a: 0000 unimp -8001455c: 0035 c.nop 13 -8001455e: 0000 unimp -80014560: 0036 c.slli zero,0xd -80014562: 0000 unimp -80014564: 00000037 lui zero,0x0 -80014568: 0038 addi a4,sp,8 -8001456a: 0000 unimp -8001456c: 0039 c.nop 14 -8001456e: 0000 unimp -80014570: 0061 c.nop 24 -80014572: 0000 unimp -80014574: 0062 c.slli zero,0x18 -80014576: 0000 unimp -80014578: 00000063 beqz zero,80014578 <__clzsi2+0x7c> -8001457c: 0064 addi s1,sp,12 -8001457e: 0000 unimp -80014580: 0065 c.nop 25 -80014582: 0000 unimp -80014584: 0066 c.slli zero,0x19 -80014586: 0000 unimp -80014588: 5245 li tp,-15 -8001458a: 4f52 lw t5,20(sp) -8001458c: 3a52 fld fs4,304(sp) -8001458e: 5f20 lw s0,120(a4) -80014590: 6e75 lui t3,0x1d -80014592: 696c flw fa1,84(a0) -80014594: 6b6e flw fs6,216(sp) -80014596: 6e20 flw fs0,88(a2) -80014598: 7920746f jal s0,8001bd2a <__BSS_END__+0x4fb2> -8001459c: 7465 lui s0,0xffff9 -8001459e: 6920 flw fs0,80(a0) -800145a0: 706d c.lui zero,0xffffb -800145a2: 656c flw fa1,76(a0) -800145a4: 656d lui a0,0x1b -800145a6: 746e flw fs0,248(sp) -800145a8: 6465 lui s0,0x19 -800145aa: 000a c.slli zero,0x2 -800145ac: 5245 li tp,-15 -800145ae: 4f52 lw t5,20(sp) -800145b0: 3a52 fld fs4,304(sp) -800145b2: 5f20 lw s0,120(a4) -800145b4: 696c flw fa1,84(a0) -800145b6: 6b6e flw fs6,216(sp) -800145b8: 6e20 flw fs0,88(a2) -800145ba: 7920746f jal s0,8001bd4c <__BSS_END__+0x4fd4> -800145be: 7465 lui s0,0xffff9 -800145c0: 6920 flw fs0,80(a0) -800145c2: 706d c.lui zero,0xffffb -800145c4: 656c flw fa1,76(a0) -800145c6: 656d lui a0,0x1b -800145c8: 746e flw fs0,248(sp) -800145ca: 6465 lui s0,0x19 -800145cc: 000a c.slli zero,0x2 -800145ce: 0000 unimp -800145d0: 70786173 csrrsi sp,0x707,16 -800145d4: 0a79 addi s4,s4,30 -800145d6: 5b61 li s6,-8 -800145d8: 6425 lui s0,0x9 -800145da: 3a5d jal 80013f90 <__floatsitf+0x15c> -800145dc: 0020 addi s0,sp,8 -800145de: 0000 unimp -800145e0: 6425 lui s0,0x9 -800145e2: 0a20 addi s0,sp,280 -800145e4: 0000 unimp -800145e6: 0000 unimp -800145e8: 620a flw ft4,128(sp) -800145ea: 5d64255b 0x5d64255b -800145ee: 203a fld ft0,392(sp) -800145f0: 0000 unimp -800145f2: 0000 unimp -800145f4: 3c0a fld fs8,160(sp) -800145f6: 70786173 csrrsi sp,0x707,16 -800145fa: 3e79 jal 80014198 <__extenddftf2+0x1dc> -800145fc: 6620 flw fs0,72(a2) -800145fe: 6961 lui s2,0x18 -80014600: 656c flw fa1,76(a0) -80014602: 2064 fld fs1,192(s0) -80014604: 7461 lui s0,0xffff8 -80014606: 3c20 fld fs0,120(s0) -80014608: 6e69 lui t3,0x1a -8001460a: 6564 flw fs1,76(a0) -8001460c: 3a78 fld fa4,240(a2) -8001460e: 2520 fld fs0,72(a0) -80014610: 3e64 fld fs1,248(a2) -80014612: 2021 jal 8001461a <__clzsi2+0x11e> -80014614: 000a c.slli zero,0x2 -80014616: 0000 unimp -80014618: 500a 0x500a -8001461a: 5341 li t1,-16 -8001461c: 2e444553 0x2e444553 -80014620: 2e2e fld ft8,200(sp) -80014622: 2e2e fld ft8,200(sp) -80014624: 2e2e fld ft8,200(sp) -80014626: 2e2e fld ft8,200(sp) -80014628: 2e2e fld ft8,200(sp) -8001462a: 2e2e fld ft8,200(sp) -8001462c: 2e2e fld ft8,200(sp) -8001462e: 2e2e fld ft8,200(sp) -80014630: 2e2e fld ft8,200(sp) -80014632: 2e2e fld ft8,200(sp) -80014634: 2e2e fld ft8,200(sp) -80014636: 2e2e fld ft8,200(sp) -80014638: 202e fld ft0,200(sp) -8001463a: 733c flw fa5,96(a4) -8001463c: 7861 lui a6,0xffff8 -8001463e: 7970 flw fa2,116(a0) -80014640: 203e fld ft0,456(sp) -80014642: 000a c.slli zero,0x2 -80014644: 2370 fld fa2,192(a4) -80014646: 8000 0x8000 -80014648: 1aa0 addi s0,sp,376 -8001464a: 8000 0x8000 -8001464c: 1aa0 addi s0,sp,376 -8001464e: 8000 0x8000 -80014650: 23bc fld fa5,64(a5) -80014652: 8000 0x8000 -80014654: 1aa0 addi s0,sp,376 -80014656: 8000 0x8000 -80014658: 1aa0 addi s0,sp,376 -8001465a: 8000 0x8000 -8001465c: 1aa0 addi s0,sp,376 -8001465e: 8000 0x8000 -80014660: 1884 addi s1,sp,112 -80014662: 8000 0x8000 -80014664: 1aa0 addi s0,sp,376 -80014666: 8000 0x8000 -80014668: 1aa0 addi s0,sp,376 -8001466a: 8000 0x8000 -8001466c: 2398 fld fa4,0(a5) -8001466e: 8000 0x8000 -80014670: 2388 fld fa0,0(a5) -80014672: 8000 0x8000 -80014674: 1aa0 addi s0,sp,376 -80014676: 8000 0x8000 -80014678: 1b0c addi a1,sp,432 -8001467a: 8000 0x8000 -8001467c: 1b18 addi a4,sp,432 -8001467e: 8000 0x8000 -80014680: 1aa0 addi s0,sp,376 -80014682: 8000 0x8000 -80014684: 1c74 addi a3,sp,572 -80014686: 8000 0x8000 -80014688: 1a70 addi a2,sp,316 -8001468a: 8000 0x8000 -8001468c: 1a70 addi a2,sp,316 -8001468e: 8000 0x8000 -80014690: 1a70 addi a2,sp,316 -80014692: 8000 0x8000 -80014694: 1a70 addi a2,sp,316 -80014696: 8000 0x8000 -80014698: 1a70 addi a2,sp,316 -8001469a: 8000 0x8000 -8001469c: 1a70 addi a2,sp,316 -8001469e: 8000 0x8000 -800146a0: 1a70 addi a2,sp,316 -800146a2: 8000 0x8000 -800146a4: 1a70 addi a2,sp,316 -800146a6: 8000 0x8000 -800146a8: 1a70 addi a2,sp,316 -800146aa: 8000 0x8000 -800146ac: 1aa0 addi s0,sp,376 -800146ae: 8000 0x8000 -800146b0: 1aa0 addi s0,sp,376 -800146b2: 8000 0x8000 -800146b4: 1aa0 addi s0,sp,376 -800146b6: 8000 0x8000 -800146b8: 1aa0 addi s0,sp,376 -800146ba: 8000 0x8000 -800146bc: 1aa0 addi s0,sp,376 -800146be: 8000 0x8000 -800146c0: 1aa0 addi s0,sp,376 -800146c2: 8000 0x8000 -800146c4: 1aa0 addi s0,sp,376 -800146c6: 8000 0x8000 -800146c8: 1f9c addi a5,sp,1008 -800146ca: 8000 0x8000 -800146cc: 1aa0 addi s0,sp,376 -800146ce: 8000 0x8000 -800146d0: 1d68 addi a0,sp,700 -800146d2: 8000 0x8000 -800146d4: 226c fld fa1,192(a2) -800146d6: 8000 0x8000 -800146d8: 1f9c addi a5,sp,1008 -800146da: 8000 0x8000 -800146dc: 1f9c addi a5,sp,1008 -800146de: 8000 0x8000 -800146e0: 1f9c addi a5,sp,1008 -800146e2: 8000 0x8000 -800146e4: 1aa0 addi s0,sp,376 -800146e6: 8000 0x8000 -800146e8: 1aa0 addi s0,sp,376 -800146ea: 8000 0x8000 -800146ec: 1aa0 addi s0,sp,376 -800146ee: 8000 0x8000 -800146f0: 1aa0 addi s0,sp,376 -800146f2: 8000 0x8000 -800146f4: 1d5c addi a5,sp,692 -800146f6: 8000 0x8000 -800146f8: 1aa0 addi s0,sp,376 -800146fa: 8000 0x8000 -800146fc: 1aa0 addi s0,sp,376 -800146fe: 8000 0x8000 -80014700: 1d30 addi a2,sp,696 -80014702: 8000 0x8000 -80014704: 1aa0 addi s0,sp,376 -80014706: 8000 0x8000 -80014708: 1aa0 addi s0,sp,376 -8001470a: 8000 0x8000 -8001470c: 1aa0 addi s0,sp,376 -8001470e: 8000 0x8000 -80014710: 1cb0 addi a2,sp,632 -80014712: 8000 0x8000 -80014714: 1aa0 addi s0,sp,376 -80014716: 8000 0x8000 -80014718: 1c80 addi s0,sp,624 -8001471a: 8000 0x8000 -8001471c: 1aa0 addi s0,sp,376 -8001471e: 8000 0x8000 -80014720: 1aa0 addi s0,sp,376 -80014722: 8000 0x8000 -80014724: 1abc addi a5,sp,376 -80014726: 8000 0x8000 -80014728: 1aa0 addi s0,sp,376 -8001472a: 8000 0x8000 -8001472c: 1aa0 addi s0,sp,376 -8001472e: 8000 0x8000 -80014730: 1aa0 addi s0,sp,376 -80014732: 8000 0x8000 -80014734: 1aa0 addi s0,sp,376 -80014736: 8000 0x8000 -80014738: 1aa0 addi s0,sp,376 -8001473a: 8000 0x8000 -8001473c: 1aa0 addi s0,sp,376 -8001473e: 8000 0x8000 -80014740: 1aa0 addi s0,sp,376 -80014742: 8000 0x8000 -80014744: 1aa0 addi s0,sp,376 -80014746: 8000 0x8000 -80014748: 1f9c addi a5,sp,1008 -8001474a: 8000 0x8000 -8001474c: 1aa0 addi s0,sp,376 -8001474e: 8000 0x8000 -80014750: 1d68 addi a0,sp,700 -80014752: 8000 0x8000 -80014754: 1c00 addi s0,sp,560 -80014756: 8000 0x8000 -80014758: 1f9c addi a5,sp,1008 -8001475a: 8000 0x8000 -8001475c: 1f9c addi a5,sp,1008 -8001475e: 8000 0x8000 -80014760: 1f9c addi a5,sp,1008 -80014762: 8000 0x8000 -80014764: 1be8 addi a0,sp,508 -80014766: 8000 0x8000 -80014768: 1c00 addi s0,sp,560 -8001476a: 8000 0x8000 -8001476c: 18c4 addi s1,sp,116 -8001476e: 8000 0x8000 -80014770: 1aa0 addi s0,sp,376 -80014772: 8000 0x8000 -80014774: 1bd0 addi a2,sp,500 -80014776: 8000 0x8000 -80014778: 1aa0 addi s0,sp,376 -8001477a: 8000 0x8000 -8001477c: 1b5c addi a5,sp,436 -8001477e: 8000 0x8000 -80014780: 23c8 fld fa0,128(a5) -80014782: 8000 0x8000 -80014784: 2330 fld fa2,64(a4) -80014786: 8000 0x8000 -80014788: 18c4 addi s1,sp,116 -8001478a: 8000 0x8000 -8001478c: 1aa0 addi s0,sp,376 -8001478e: 8000 0x8000 -80014790: 1cb0 addi a2,sp,632 -80014792: 8000 0x8000 -80014794: 18bc addi a5,sp,120 -80014796: 8000 0x8000 -80014798: 2404 fld fs1,8(s0) -8001479a: 8000 0x8000 -8001479c: 1aa0 addi s0,sp,376 -8001479e: 8000 0x8000 -800147a0: 1aa0 addi s0,sp,376 -800147a2: 8000 0x8000 -800147a4: 19c4 addi s1,sp,244 -800147a6: 8000 0x8000 -800147a8: 1aa0 addi s0,sp,376 -800147aa: 8000 0x8000 -800147ac: 18bc addi a5,sp,120 -800147ae: 8000 0x8000 - -800147b0 : -800147b0: 2020 fld fs0,64(s0) -800147b2: 2020 fld fs0,64(s0) -800147b4: 2020 fld fs0,64(s0) -800147b6: 2020 fld fs0,64(s0) -800147b8: 2020 fld fs0,64(s0) -800147ba: 2020 fld fs0,64(s0) -800147bc: 2020 fld fs0,64(s0) -800147be: 2020 fld fs0,64(s0) - -800147c0 : -800147c0: 3030 fld fa2,96(s0) -800147c2: 3030 fld fa2,96(s0) -800147c4: 3030 fld fa2,96(s0) -800147c6: 3030 fld fa2,96(s0) -800147c8: 3030 fld fa2,96(s0) -800147ca: 3030 fld fa2,96(s0) -800147cc: 3030 fld fa2,96(s0) -800147ce: 3030 fld fa2,96(s0) -800147d0: 4e49 li t3,18 -800147d2: 0046 c.slli zero,0x11 -800147d4: 6e69 lui t3,0x1a -800147d6: 0066 c.slli zero,0x19 -800147d8: 414e lw sp,208(sp) -800147da: 004e c.slli zero,0x13 -800147dc: 616e flw ft2,216(sp) -800147de: 006e c.slli zero,0x1b -800147e0: 3130 fld fa2,96(a0) -800147e2: 3332 fld ft6,296(sp) -800147e4: 3534 fld fa3,104(a0) -800147e6: 3736 fld fa4,360(sp) -800147e8: 3938 fld fa4,112(a0) -800147ea: 6261 lui tp,0x18 -800147ec: 66656463 bltu a0,t1,80014e54 -800147f0: 0000 unimp -800147f2: 0000 unimp -800147f4: 3130 fld fa2,96(a0) -800147f6: 3332 fld ft6,296(sp) -800147f8: 3534 fld fa3,104(a0) -800147fa: 3736 fld fa4,360(sp) -800147fc: 3938 fld fa4,112(a0) -800147fe: 4241 li tp,16 -80014800: 46454443 fmadd.q fs0,fa0,ft4,fs0,rmm -80014804: 0000 unimp -80014806: 0000 unimp -80014808: 6e28 flw fa0,88(a2) -8001480a: 6c75 lui s8,0x1d -8001480c: 296c fld fa1,208(a0) -8001480e: 0000 unimp -80014810: 0030 addi a2,sp,8 - ... - -80014814 : - ... - -80014828 : - ... -80014838: 8000 0x8000 -8001483a: 3fff 0x3fff - -8001483c : -8001483c: 6576 flw fa0,92(sp) -8001483e: 4a92 lw s5,4(sp) -80014840: 804a c.mv zero,s2 -80014842: c94c153f 8a20979a 0x8a20979ac94c153f -8001484a: 5202 lw tp,32(sp) -8001484c: c460 sw s0,76(s0) -8001484e: 7525 lui a0,0xfffe9 -80014850: 6a32 flw fs4,12(sp) -80014852: ce52 sw s4,28(sp) -80014854: 329a fld ft5,416(sp) -80014856: 28ce fld fa7,208(sp) -80014858: a74d j 80014ffa <_ctype_+0x11a> -8001485a: 5de4 lw s1,124(a1) -8001485c: c53d beqz a0,800148ca -8001485e: 3b5d jal 80014614 <__clzsi2+0x118> -80014860: 5a929e8b 0x5a929e8b -80014864: 526c lw a1,100(a2) -80014866: 50ce lw ra,240(sp) -80014868: 3d28f18b 0x3d28f18b -8001486c: 650d lui a0,0x3 -8001486e: 81750c17 auipc s8,0x81750 -80014872: 7586 flw fa1,96(sp) -80014874: c976 sw t4,144(sp) -80014876: 4d48 lw a0,28(a0) -80014878: 9c66 add s8,s8,s9 -8001487a: 58f8 lw a4,116(s1) -8001487c: bc50 fsd fa2,184(s0) -8001487e: 5c54 lw a3,60(s0) -80014880: cc65 beqz s0,80014978 -80014882: 91c6 add gp,gp,a7 -80014884: a60e fsd ft3,264(sp) -80014886: a0ae fsd fa1,64(sp) -80014888: e319 bnez a4,8001488e -8001488a: 851e46a3 0x851e46a3 -8001488e: 98feeab7 lui s5,0x98fee -80014892: ddbb901b 0xddbb901b -80014896: de8d beqz a3,800147d0 -80014898: 9df9 0x9df9 -8001489a: aa7eebfb 0xaa7eebfb -8001489e: 4351 li t1,20 -800148a0: 0235 addi tp,tp,13 -800148a2: 36b10137 lui sp,0x36b10 -800148a6: 336c fld fa1,224(a4) -800148a8: 8cdfc66f jal a2,80011174 <__muldf3+0x2c4> -800148ac: 80e9 srli s1,s1,0x1a -800148ae: 47c9 li a5,18 -800148b0: 93ba add t2,t2,a4 -800148b2: 41a8 lw a0,64(a1) -800148b4: 50f8 lw a4,100(s1) -800148b6: c76b25fb 0xc76b25fb -800148ba: 6b71 lui s6,0x1c -800148bc: a6d53cbf 1f49ffcf 0x1f49ffcfa6d53cbf -800148c4: c278 sw a4,68(a2) -800148c6: 000040d3 fadd.s ft1,ft0,ft0,rmm -800148ca: 0000 unimp -800148cc: 0000 unimp -800148ce: 0000 unimp -800148d0: f020 fsw fs0,96(s0) -800148d2: b59d j 80014738 <__clzsi2+0x23c> -800148d4: 2b70 fld fa2,208(a4) -800148d6: ada8 fsd fa0,88(a1) -800148d8: 9dc5 0x9dc5 -800148da: 4069 c.li zero,26 - ... -800148e8: 0400 addi s0,sp,512 -800148ea: 8e1bc9bf 00004034 0x40348e1bc9bf - ... -800148fe: 2000 fld fs0,0(s0) -80014900: bebc fsd fa5,120(a3) -80014902: 4019 c.li zero,6 - ... -80014914: 9c40 0x9c40 -80014916: 400c lw a1,0(s0) - ... -80014928: c800 sw s0,16(s0) -8001492a: 4005 c.li zero,1 - ... -8001493c: a000 fsd fs0,0(s0) -8001493e: 4002 0x4002 - -80014940 : -80014940: 2030 fld fa2,64(s0) -80014942: cffc sw a5,92(a5) -80014944: 8123a1c3 fmadd.s ft3,ft7,fs2,fa6,rdn -80014948: 9fde2de3 0x9fde2de3 -8001494c: d2ce sw s3,100(sp) -8001494e: 04c8 addi a0,sp,580 -80014950: a6dd j 80014d36 -80014952: 0ad8 addi a4,sp,340 -80014954: 8264 0x8264 -80014956: f2ead2cb fnmsub.d ft5,fs5,fa4,ft10,unknown -8001495a: 12d4 addi a3,sp,356 -8001495c: 4925 li s2,9 -8001495e: 2de4 fld fs1,216(a1) -80014960: 3436 fld fs0,360(sp) -80014962: ceae534f fnmadd.q ft6,ft8,fa0,fs9,unknown -80014966: f53f256b 0xf53f256b -8001496a: f698 fsw fa4,40(a3) -8001496c: 01586bd3 fadd.s fs7,fa6,fs5,unknown -80014970: 87a6 mv a5,s1 -80014972: c0bd beqz s1,800149d8 -80014974: 82a5da57 vfdiv.vf v20,v10,fa1 -80014978: a2a6 fsd fs1,320(sp) -8001497a: 32b5 jal 800142e6 <__trunctfdf2+0x11e> -8001497c: e731 bnez a4,800149c8 -8001497e: 04d4 addi a3,sp,580 -80014980: e3f2 fsw ft8,196(sp) -80014982: d332 sw a2,164(sp) -80014984: 7132 flw ft2,44(sp) -80014986: d21c sw a5,32(a2) -80014988: ee32db23 0xee32db23 -8001498c: 9049 srli s0,s0,0x32 -8001498e: 395a fld fs2,432(sp) -80014990: a23e fsd fa5,256(sp) -80014992: 5308 lw a0,32(a4) -80014994: 1155fefb 0x1155fefb -80014998: fa91 bnez a3,800148ac -8001499a: 1939 addi s2,s2,-18 -8001499c: 637a flw ft6,156(sp) -8001499e: 4325 li t1,9 -800149a0: c031 beqz s0,800149e4 -800149a2: 3cac fld fa1,120(s1) -800149a4: e26d bnez a2,80014a86 -800149a6: dbde sw s7,244(sp) -800149a8: d05d beqz s0,8001494e -800149aa: b3f6 fsd ft9,480(sp) -800149ac: ac7c fsd fa5,216(s0) -800149ae: e4a0 fsw fs0,72(s1) -800149b0: 64bc flw fa5,72(s1) -800149b2: 467c lw a5,76(a2) -800149b4: ddd0 sw a2,60(a1) -800149b6: 3e55 jal 8001456a <__clzsi2+0x6e> -800149b8: 2a20 fld fs0,80(a2) -800149ba: 6224 flw fs1,64(a2) -800149bc: 98d747b3 0x98d747b3 -800149c0: e9a53f23 0xe9a53f23 -800149c4: a539 j 80014fd2 <_ctype_+0xf2> -800149c6: a87fea27 vssseg6w.v v20,(t6),t2,v0.t -800149ca: 3f2a fld ft10,168(sp) -800149cc: 4af20b5b 0x4af20b5b -800149d0: a581 j 80015010 <_ctype_+0x130> -800149d2: 18ed addi a7,a7,-5 -800149d4: 67de flw fa5,212(sp) -800149d6: 94ba add s1,s1,a4 -800149d8: 4539 li a0,14 -800149da: 1ead addi t4,t4,-21 -800149dc: cfb1 beqz a5,80014a38 -800149de: 3f94 fld fa3,56(a5) -800149e0: bf71 j 8001497c -800149e2: 7989a9b3 0x7989a9b3 -800149e6: be68 fsd fa0,248(a2) -800149e8: 4c2e lw s8,200(sp) -800149ea: c44de15b 0xc44de15b -800149ee: 94be add s1,s1,a5 -800149f0: e695 bnez a3,80014a1c -800149f2: 3fc9 jal 800149c4 -800149f4: 3d4d jal 800148a6 -800149f6: 7c3d lui s8,0xfffef -800149f8: 36ba fld fa3,424(sp) -800149fa: fdc20d2b 0xfdc20d2b -800149fe: cefc sw a5,92(a3) -80014a00: 8461 srai s0,s0,0x18 -80014a02: 7711 lui a4,0xfffe4 -80014a04: abcc fsd fa1,144(a5) -80014a06: 3fe4 fld fs1,248(a5) -80014a08: c155 beqz a0,80014aac -80014a0a: a4a8 fsd fa0,72(s1) -80014a0c: 404e 0x404e -80014a0e: d3c36113 ori sp,t1,-708 -80014a12: e219652b 0xe219652b -80014a16: 1758 addi a4,sp,932 -80014a18: 3ff1d1b7 lui gp,0x3ff1d -80014a1c: d70a sw sp,172(sp) -80014a1e: 0a3d70a3 0xa3d70a3 -80014a22: 3d70a3d7 0x3d70a3d7 -80014a26: d70a sw sp,172(sp) -80014a28: 0a3d70a3 0xa3d70a3 -80014a2c: 3ff8a3d7 0x3ff8a3d7 -80014a30: cccd beqz s1,80014aea <__mprec_tens+0x3a> -80014a32: cccc sw a1,28(s1) -80014a34: cccc sw a1,28(s1) -80014a36: cccc sw a1,28(s1) -80014a38: cccc sw a1,28(s1) -80014a3a: cccc sw a1,28(s1) -80014a3c: cccc sw a1,28(s1) -80014a3e: cccc sw a1,28(s1) -80014a40: cccc sw a1,28(s1) -80014a42: 0xffff3ffb - -80014a44 : -80014a44: ffff 0xffff -80014a46: fffe fsw ft11,252(sp) -80014a48: fffc fsw fa5,124(a5) -80014a4a: fff8 fsw fa4,124(a5) -80014a4c: fff0 fsw fa2,124(a5) -80014a4e: ffe0 fsw fs0,124(a5) -80014a50: ffc0 fsw fs0,60(a5) -80014a52: ff80 fsw fs0,56(a5) -80014a54: ff00 fsw fs0,56(a4) -80014a56: fe00 fsw fs0,56(a2) -80014a58: fc00 fsw fs0,56(s0) -80014a5a: f800 fsw fs0,48(s0) -80014a5c: f000 fsw fs0,32(s0) -80014a5e: e000 fsw fs0,0(s0) -80014a60: c000 sw s0,0(s0) -80014a62: 8000 0x8000 -80014a64: 0000 unimp -80014a66: 0000 unimp -80014a68: 4e20 lw s0,88(a2) -80014a6a: 4e61 li t3,24 -80014a6c: 0020 addi s0,sp,8 -80014a6e: 0000 unimp -80014a70: 2d20 fld fs0,88(a0) -80014a72: 6e49 lui t3,0x12 -80014a74: 6966 flw fs2,88(sp) -80014a76: 696e flw fs2,216(sp) -80014a78: 7974 flw fa3,116(a0) -80014a7a: 0020 addi s0,sp,8 -80014a7c: 4920 lw s0,80(a0) -80014a7e: 666e flw fa2,216(sp) -80014a80: 6e69 lui t3,0x1a -80014a82: 7469 lui s0,0xffffa -80014a84: 2079 jal 80014b12 <__mprec_tens+0x62> -80014a86: 0000 unimp -80014a88: 614e flw ft2,208(sp) -80014a8a: 004e c.slli zero,0x13 -80014a8c: 2545 jal 8001512c <_ctype_+0x24c> -80014a8e: 0064 addi s1,sp,12 -80014a90: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne -80014a94: 4f50 lw a2,28(a4) -80014a96: 00584953 fadd.s fs2,fa6,ft5,rmm -80014a9a: 0000 unimp -80014a9c: 002e c.slli zero,0xb - ... - -80014aa0 : -80014aa0: 0005 c.nop 1 -80014aa2: 0000 unimp -80014aa4: 0019 c.nop 6 -80014aa6: 0000 unimp -80014aa8: 007d c.nop 31 -80014aaa: 0000 unimp -80014aac: 0000 unimp - ... - -80014ab0 <__mprec_tens>: -80014ab0: 0000 unimp -80014ab2: 0000 unimp -80014ab4: 0000 unimp -80014ab6: 3ff0 fld fa2,248(a5) -80014ab8: 0000 unimp -80014aba: 0000 unimp -80014abc: 0000 unimp -80014abe: 4024 lw s1,64(s0) -80014ac0: 0000 unimp -80014ac2: 0000 unimp -80014ac4: 0000 unimp -80014ac6: 4059 c.li zero,22 -80014ac8: 0000 unimp -80014aca: 0000 unimp -80014acc: 4000 lw s0,0(s0) -80014ace: 0000408f 0x408f -80014ad2: 0000 unimp -80014ad4: 8800 0x8800 -80014ad6: 000040c3 fmadd.s ft1,ft0,ft0,ft0,rmm -80014ada: 0000 unimp -80014adc: 6a00 flw fs0,16(a2) -80014ade: 40f8 lw a4,68(s1) -80014ae0: 0000 unimp -80014ae2: 0000 unimp -80014ae4: 8480 0x8480 -80014ae6: 412e lw sp,200(sp) -80014ae8: 0000 unimp -80014aea: 0000 unimp -80014aec: 12d0 addi a2,sp,356 -80014aee: 00004163 bltz zero,80014af0 <__mprec_tens+0x40> -80014af2: 0000 unimp -80014af4: d784 sw s1,40(a5) -80014af6: 00004197 auipc gp,0x4 -80014afa: 0000 unimp -80014afc: cd65 beqz a0,80014bf4 <__mprec_bigtens+0x54> -80014afe: 41cd li gp,19 -80014b00: 0000 unimp -80014b02: 2000 fld fs0,0(s0) -80014b04: a05f 4202 0000 0x4202a05f -80014b0a: e800 fsw fs0,16(s0) -80014b0c: 4876 lw a6,92(sp) -80014b0e: 00004237 lui tp,0x4 -80014b12: a200 fsd fs0,0(a2) -80014b14: 1a94 addi a3,sp,368 -80014b16: 426d li tp,27 -80014b18: 0000 unimp -80014b1a: e540 fsw fs0,12(a0) -80014b1c: 309c fld fa5,32(s1) -80014b1e: 42a2 lw t0,8(sp) -80014b20: 0000 unimp -80014b22: 1e90 addi a2,sp,880 -80014b24: bcc4 fsd fs1,184(s1) -80014b26: 42d6 lw t0,84(sp) -80014b28: 0000 unimp -80014b2a: 2634 fld fa3,72(a2) -80014b2c: 6bf5 lui s7,0x1d -80014b2e: 430c lw a1,0(a4) -80014b30: 8000 0x8000 -80014b32: 37e0 fld fs0,232(a5) -80014b34: c379 beqz a4,80014bfa <__mprec_bigtens+0x5a> -80014b36: 4341 li t1,16 -80014b38: a000 fsd fs0,0(s0) -80014b3a: 85d8 0x85d8 -80014b3c: 43763457 vadc.vim v8,v23,12,v0 -80014b40: c800 sw s0,16(s0) -80014b42: 674e flw fa4,208(sp) -80014b44: c16d beqz a0,80014c26 <__mprec_bigtens+0x86> -80014b46: 3d0043ab 0x3d0043ab -80014b4a: 6091 lui ra,0x4 -80014b4c: 58e4 lw s1,116(s1) -80014b4e: 43e1 li t2,24 -80014b50: 8c40 0x8c40 -80014b52: 78b5 lui a7,0xfffed -80014b54: af1d j 8001528a <__clz_tab+0x66> -80014b56: 4415 li s0,5 -80014b58: ef50 fsw fa2,28(a4) -80014b5a: d6e2 sw s8,108(sp) -80014b5c: 1ae4 addi s1,sp,380 -80014b5e: d592444b 0xd592444b -80014b62: 064d addi a2,a2,19 -80014b64: 4480f0cf 0x4480f0cf -80014b68: 4af6 lw s5,92(sp) -80014b6a: c7e1 beqz a5,80014c32 <__mprec_bigtens+0x92> -80014b6c: 2d02 fld fs10,0(sp) -80014b6e: 44b5 li s1,13 -80014b70: 9db4 0x9db4 -80014b72: 79d9 lui s3,0xffff6 -80014b74: 44ea7843 0x44ea7843 - -80014b78 <__mprec_tinytens>: -80014b78: 89bc 0x89bc -80014b7a: 97d8 0x97d8 -80014b7c: d2b2 sw a2,100(sp) -80014b7e: 3c9c fld fa5,56(s1) -80014b80: d5a8a733 0xd5a8a733 -80014b84: 3949f623 0x3949f623 -80014b88: a73d j 800152b6 <__clz_tab+0x92> -80014b8a: 44f4 lw a3,76(s1) -80014b8c: 0ffd addi t6,t6,31 -80014b8e: 32a5 jal 800144f6 <__trunctfdf2+0x32e> -80014b90: 979d srai a5,a5,0x27 -80014b92: cf8c sw a1,24(a5) -80014b94: ba08 fsd fa0,48(a2) -80014b96: 6f43255b 0x6f43255b -80014b9a: 64ac flw fa1,72(s1) -80014b9c: 0628 addi a0,sp,776 -80014b9e: 0ac8 addi a0,sp,340 - -80014ba0 <__mprec_bigtens>: -80014ba0: 8000 0x8000 -80014ba2: 37e0 fld fs0,232(a5) -80014ba4: c379 beqz a4,80014c6a <__mprec_bigtens+0xca> -80014ba6: 4341 li t1,16 -80014ba8: b5056e17 auipc t3,0xb5056 -80014bac: b8b5 j 80014428 <__trunctfdf2+0x260> -80014bae: f9f54693 xori a3,a0,-97 -80014bb2: 4f03e93f 1d324d38 0x1d324d384f03e93f -80014bba: f930 fsw fa2,112(a0) -80014bbc: 7748 flw fa0,44(a4) -80014bbe: 5a82 lw s5,32(sp) -80014bc0: bf3c fsd fa5,120(a4) -80014bc2: 4fdd7f73 csrrci t5,0x4fd,26 -80014bc6: 7515 lui a0,0xfffe5 -80014bc8: a454 fsd fa3,136(s0) -80014bca: 8000 0x8000 -80014bcc: 9ae0 0x9ae0 -80014bce: 8000 0x8000 -80014bd0: 9ae0 0x9ae0 -80014bd2: 8000 0x8000 -80014bd4: a448 fsd fa0,136(s0) -80014bd6: 8000 0x8000 -80014bd8: 9ae0 0x9ae0 -80014bda: 8000 0x8000 -80014bdc: 9ae0 0x9ae0 -80014bde: 8000 0x8000 -80014be0: 9ae0 0x9ae0 -80014be2: 8000 0x8000 -80014be4: 9914 0x9914 -80014be6: 8000 0x8000 -80014be8: 9ae0 0x9ae0 -80014bea: 8000 0x8000 -80014bec: 9ae0 0x9ae0 -80014bee: 8000 0x8000 -80014bf0: a3d4 fsd fa3,128(a5) -80014bf2: 8000 0x8000 -80014bf4: a3c4 fsd fs1,128(a5) -80014bf6: 8000 0x8000 -80014bf8: 9ae0 0x9ae0 -80014bfa: 8000 0x8000 -80014bfc: 9b4c 0x9b4c -80014bfe: 8000 0x8000 -80014c00: a404 fsd fs1,8(s0) -80014c02: 8000 0x8000 -80014c04: 9ae0 0x9ae0 -80014c06: 8000 0x8000 -80014c08: a3f8 fsd fa4,192(a5) -80014c0a: 8000 0x8000 -80014c0c: 9ab0 0x9ab0 -80014c0e: 8000 0x8000 -80014c10: 9ab0 0x9ab0 -80014c12: 8000 0x8000 -80014c14: 9ab0 0x9ab0 -80014c16: 8000 0x8000 -80014c18: 9ab0 0x9ab0 -80014c1a: 8000 0x8000 -80014c1c: 9ab0 0x9ab0 -80014c1e: 8000 0x8000 -80014c20: 9ab0 0x9ab0 -80014c22: 8000 0x8000 -80014c24: 9ab0 0x9ab0 -80014c26: 8000 0x8000 -80014c28: 9ab0 0x9ab0 -80014c2a: 8000 0x8000 -80014c2c: 9ab0 0x9ab0 -80014c2e: 8000 0x8000 -80014c30: 9ae0 0x9ae0 -80014c32: 8000 0x8000 -80014c34: 9ae0 0x9ae0 -80014c36: 8000 0x8000 -80014c38: 9ae0 0x9ae0 -80014c3a: 8000 0x8000 -80014c3c: 9ae0 0x9ae0 -80014c3e: 8000 0x8000 -80014c40: 9ae0 0x9ae0 -80014c42: 8000 0x8000 -80014c44: 9ae0 0x9ae0 -80014c46: 8000 0x8000 -80014c48: 9ae0 0x9ae0 -80014c4a: 8000 0x8000 -80014c4c: 9c84 0x9c84 -80014c4e: 8000 0x8000 -80014c50: 9ae0 0x9ae0 -80014c52: 8000 0x8000 -80014c54: a0b4 fsd fa3,64(s1) -80014c56: 8000 0x8000 -80014c58: a058 fsd fa4,128(s0) -80014c5a: 8000 0x8000 -80014c5c: 9c84 0x9c84 -80014c5e: 8000 0x8000 -80014c60: 9c84 0x9c84 -80014c62: 8000 0x8000 -80014c64: 9c84 0x9c84 -80014c66: 8000 0x8000 -80014c68: 9ae0 0x9ae0 -80014c6a: 8000 0x8000 -80014c6c: 9ae0 0x9ae0 -80014c6e: 8000 0x8000 -80014c70: 9ae0 0x9ae0 -80014c72: 8000 0x8000 -80014c74: 9ae0 0x9ae0 -80014c76: 8000 0x8000 -80014c78: a04c fsd fa1,128(s0) -80014c7a: 8000 0x8000 -80014c7c: 9ae0 0x9ae0 -80014c7e: 8000 0x8000 -80014c80: 9ae0 0x9ae0 -80014c82: 8000 0x8000 -80014c84: a020 fsd fs0,64(s0) -80014c86: 8000 0x8000 -80014c88: 9ae0 0x9ae0 -80014c8a: 8000 0x8000 -80014c8c: 9ae0 0x9ae0 -80014c8e: 8000 0x8000 -80014c90: 9ae0 0x9ae0 -80014c92: 8000 0x8000 -80014c94: 9fa4 0x9fa4 -80014c96: 8000 0x8000 -80014c98: 9ae0 0x9ae0 -80014c9a: 8000 0x8000 -80014c9c: 9f74 0x9f74 -80014c9e: 8000 0x8000 -80014ca0: 9ae0 0x9ae0 -80014ca2: 8000 0x8000 -80014ca4: 9ae0 0x9ae0 -80014ca6: 8000 0x8000 -80014ca8: 9afc 0x9afc -80014caa: 8000 0x8000 -80014cac: 9ae0 0x9ae0 -80014cae: 8000 0x8000 -80014cb0: 9ae0 0x9ae0 -80014cb2: 8000 0x8000 -80014cb4: 9ae0 0x9ae0 -80014cb6: 8000 0x8000 -80014cb8: 9ae0 0x9ae0 -80014cba: 8000 0x8000 -80014cbc: 9ae0 0x9ae0 -80014cbe: 8000 0x8000 -80014cc0: 9ae0 0x9ae0 -80014cc2: 8000 0x8000 -80014cc4: 9ae0 0x9ae0 -80014cc6: 8000 0x8000 -80014cc8: 9ae0 0x9ae0 -80014cca: 8000 0x8000 -80014ccc: 9c84 0x9c84 -80014cce: 8000 0x8000 -80014cd0: 9ae0 0x9ae0 -80014cd2: 8000 0x8000 -80014cd4: a0b4 fsd fa3,64(s1) -80014cd6: 8000 0x8000 -80014cd8: a2e8 fsd fa0,192(a3) -80014cda: 8000 0x8000 -80014cdc: 9c84 0x9c84 -80014cde: 8000 0x8000 -80014ce0: 9c84 0x9c84 -80014ce2: 8000 0x8000 -80014ce4: 9c84 0x9c84 -80014ce6: 8000 0x8000 -80014ce8: 9c2c 0x9c2c -80014cea: 8000 0x8000 -80014cec: a2e8 fsd fa0,192(a3) -80014cee: 8000 0x8000 -80014cf0: 9954 0x9954 -80014cf2: 8000 0x8000 -80014cf4: 9ae0 0x9ae0 -80014cf6: 8000 0x8000 -80014cf8: 9c14 0x9c14 -80014cfa: 8000 0x8000 -80014cfc: 9ae0 0x9ae0 -80014cfe: 8000 0x8000 -80014d00: 9b98 0x9b98 -80014d02: 8000 0x8000 -80014d04: 9b58 0x9b58 -80014d06: 8000 0x8000 -80014d08: 9c44 0x9c44 -80014d0a: 8000 0x8000 -80014d0c: 9954 0x9954 -80014d0e: 8000 0x8000 -80014d10: 9ae0 0x9ae0 -80014d12: 8000 0x8000 -80014d14: 9fa4 0x9fa4 -80014d16: 8000 0x8000 -80014d18: 994c 0x994c -80014d1a: 8000 0x8000 -80014d1c: a46c fsd fa1,200(s0) -80014d1e: 8000 0x8000 -80014d20: 9ae0 0x9ae0 -80014d22: 8000 0x8000 -80014d24: 9ae0 0x9ae0 -80014d26: 8000 0x8000 -80014d28: 9a04 0x9a04 -80014d2a: 8000 0x8000 -80014d2c: 9ae0 0x9ae0 -80014d2e: 8000 0x8000 -80014d30: 994c 0x994c -80014d32: 8000 0x8000 - -80014d34 : -80014d34: 2020 fld fs0,64(s0) -80014d36: 2020 fld fs0,64(s0) -80014d38: 2020 fld fs0,64(s0) -80014d3a: 2020 fld fs0,64(s0) -80014d3c: 2020 fld fs0,64(s0) -80014d3e: 2020 fld fs0,64(s0) -80014d40: 2020 fld fs0,64(s0) -80014d42: 2020 fld fs0,64(s0) - -80014d44 : -80014d44: 3030 fld fa2,96(s0) -80014d46: 3030 fld fa2,96(s0) -80014d48: 3030 fld fa2,96(s0) -80014d4a: 3030 fld fa2,96(s0) -80014d4c: 3030 fld fa2,96(s0) -80014d4e: 3030 fld fa2,96(s0) -80014d50: 3030 fld fa2,96(s0) -80014d52: 3030 fld fa2,96(s0) -80014d54: ca9c sw a5,16(a3) -80014d56: 8000 0x8000 -80014d58: c71c sw a5,8(a4) -80014d5a: 8000 0x8000 -80014d5c: c71c sw a5,8(a4) -80014d5e: 8000 0x8000 -80014d60: cae8 sw a0,84(a3) -80014d62: 8000 0x8000 -80014d64: c71c sw a5,8(a4) -80014d66: 8000 0x8000 -80014d68: c71c sw a5,8(a4) -80014d6a: 8000 0x8000 -80014d6c: c71c sw a5,8(a4) -80014d6e: 8000 0x8000 -80014d70: c54c sw a1,12(a0) -80014d72: 8000 0x8000 -80014d74: c71c sw a5,8(a4) -80014d76: 8000 0x8000 -80014d78: c71c sw a5,8(a4) -80014d7a: 8000 0x8000 -80014d7c: cac4 sw s1,20(a3) -80014d7e: 8000 0x8000 -80014d80: cab4 sw a3,80(a3) -80014d82: 8000 0x8000 -80014d84: c71c sw a5,8(a4) -80014d86: 8000 0x8000 -80014d88: cb34 sw a3,80(a4) -80014d8a: 8000 0x8000 -80014d8c: caf4 sw a3,84(a3) -80014d8e: 8000 0x8000 -80014d90: c71c sw a5,8(a4) -80014d92: 8000 0x8000 -80014d94: c8b8 sw a4,80(s1) -80014d96: 8000 0x8000 -80014d98: c6ec sw a1,76(a3) -80014d9a: 8000 0x8000 -80014d9c: c6ec sw a1,76(a3) -80014d9e: 8000 0x8000 -80014da0: c6ec sw a1,76(a3) -80014da2: 8000 0x8000 -80014da4: c6ec sw a1,76(a3) -80014da6: 8000 0x8000 -80014da8: c6ec sw a1,76(a3) -80014daa: 8000 0x8000 -80014dac: c6ec sw a1,76(a3) -80014dae: 8000 0x8000 -80014db0: c6ec sw a1,76(a3) -80014db2: 8000 0x8000 -80014db4: c6ec sw a1,76(a3) -80014db6: 8000 0x8000 -80014db8: c6ec sw a1,76(a3) -80014dba: 8000 0x8000 -80014dbc: c71c sw a5,8(a4) -80014dbe: 8000 0x8000 -80014dc0: c71c sw a5,8(a4) -80014dc2: 8000 0x8000 -80014dc4: c71c sw a5,8(a4) -80014dc6: 8000 0x8000 -80014dc8: c71c sw a5,8(a4) -80014dca: 8000 0x8000 -80014dcc: c71c sw a5,8(a4) -80014dce: 8000 0x8000 -80014dd0: c71c sw a5,8(a4) -80014dd2: 8000 0x8000 -80014dd4: c71c sw a5,8(a4) -80014dd6: 8000 0x8000 -80014dd8: c71c sw a5,8(a4) -80014dda: 8000 0x8000 -80014ddc: c71c sw a5,8(a4) -80014dde: 8000 0x8000 -80014de0: c99c sw a5,16(a1) -80014de2: 8000 0x8000 -80014de4: c930 sw a2,80(a0) -80014de6: 8000 0x8000 -80014de8: c71c sw a5,8(a4) -80014dea: 8000 0x8000 -80014dec: c71c sw a5,8(a4) -80014dee: 8000 0x8000 -80014df0: c71c sw a5,8(a4) -80014df2: 8000 0x8000 -80014df4: c71c sw a5,8(a4) -80014df6: 8000 0x8000 -80014df8: c71c sw a5,8(a4) -80014dfa: 8000 0x8000 -80014dfc: c71c sw a5,8(a4) -80014dfe: 8000 0x8000 -80014e00: c71c sw a5,8(a4) -80014e02: 8000 0x8000 -80014e04: c71c sw a5,8(a4) -80014e06: 8000 0x8000 -80014e08: c71c sw a5,8(a4) -80014e0a: 8000 0x8000 -80014e0c: c71c sw a5,8(a4) -80014e0e: 8000 0x8000 -80014e10: c908 sw a0,16(a0) -80014e12: 8000 0x8000 -80014e14: c71c sw a5,8(a4) -80014e16: 8000 0x8000 -80014e18: c71c sw a5,8(a4) -80014e1a: 8000 0x8000 -80014e1c: c71c sw a5,8(a4) -80014e1e: 8000 0x8000 -80014e20: c8c4 sw s1,20(s1) -80014e22: 8000 0x8000 -80014e24: c71c sw a5,8(a4) -80014e26: 8000 0x8000 -80014e28: c88c sw a1,16(s1) -80014e2a: 8000 0x8000 -80014e2c: c71c sw a5,8(a4) -80014e2e: 8000 0x8000 -80014e30: c71c sw a5,8(a4) -80014e32: 8000 0x8000 -80014e34: c654 sw a3,12(a2) -80014e36: 8000 0x8000 -80014e38: c71c sw a5,8(a4) -80014e3a: 8000 0x8000 -80014e3c: c71c sw a5,8(a4) -80014e3e: 8000 0x8000 -80014e40: c71c sw a5,8(a4) -80014e42: 8000 0x8000 -80014e44: c71c sw a5,8(a4) -80014e46: 8000 0x8000 -80014e48: c71c sw a5,8(a4) -80014e4a: 8000 0x8000 -80014e4c: c71c sw a5,8(a4) -80014e4e: 8000 0x8000 -80014e50: c71c sw a5,8(a4) -80014e52: 8000 0x8000 -80014e54: c71c sw a5,8(a4) -80014e56: 8000 0x8000 -80014e58: c71c sw a5,8(a4) -80014e5a: 8000 0x8000 -80014e5c: c71c sw a5,8(a4) -80014e5e: 8000 0x8000 -80014e60: c99c sw a5,16(a1) -80014e62: 8000 0x8000 -80014e64: cca0 sw s0,88(s1) -80014e66: 8000 0x8000 -80014e68: c71c sw a5,8(a4) -80014e6a: 8000 0x8000 -80014e6c: c71c sw a5,8(a4) -80014e6e: 8000 0x8000 -80014e70: c71c sw a5,8(a4) -80014e72: 8000 0x8000 -80014e74: cc8c sw a1,24(s1) -80014e76: 8000 0x8000 -80014e78: cca0 sw s0,88(s1) -80014e7a: 8000 0x8000 -80014e7c: c58c sw a1,8(a1) -80014e7e: 8000 0x8000 -80014e80: c71c sw a5,8(a4) -80014e82: 8000 0x8000 -80014e84: cc78 sw a4,92(s0) -80014e86: 8000 0x8000 -80014e88: c71c sw a5,8(a4) -80014e8a: 8000 0x8000 -80014e8c: cc38 sw a4,88(s0) -80014e8e: 8000 0x8000 -80014e90: cbfc sw a5,84(a5) -80014e92: 8000 0x8000 -80014e94: cbc4 sw s1,20(a5) -80014e96: 8000 0x8000 -80014e98: c58c sw a1,8(a1) -80014e9a: 8000 0x8000 -80014e9c: c71c sw a5,8(a4) -80014e9e: 8000 0x8000 -80014ea0: c8c4 sw s1,20(s1) -80014ea2: 8000 0x8000 -80014ea4: c584 sw s1,8(a1) -80014ea6: 8000 0x8000 -80014ea8: cb40 sw s0,20(a4) -80014eaa: 8000 0x8000 -80014eac: c71c sw a5,8(a4) -80014eae: 8000 0x8000 -80014eb0: c71c sw a5,8(a4) -80014eb2: 8000 0x8000 -80014eb4: cb80 sw s0,16(a5) -80014eb6: 8000 0x8000 -80014eb8: c71c sw a5,8(a4) -80014eba: 8000 0x8000 -80014ebc: c584 sw s1,8(a1) -80014ebe: 8000 0x8000 - -80014ec0 : -80014ec0: 2020 fld fs0,64(s0) -80014ec2: 2020 fld fs0,64(s0) -80014ec4: 2020 fld fs0,64(s0) -80014ec6: 2020 fld fs0,64(s0) -80014ec8: 2020 fld fs0,64(s0) -80014eca: 2020 fld fs0,64(s0) -80014ecc: 2020 fld fs0,64(s0) -80014ece: 2020 fld fs0,64(s0) - -80014ed0 : -80014ed0: 3030 fld fa2,96(s0) -80014ed2: 3030 fld fa2,96(s0) -80014ed4: 3030 fld fa2,96(s0) -80014ed6: 3030 fld fa2,96(s0) -80014ed8: 3030 fld fa2,96(s0) -80014eda: 3030 fld fa2,96(s0) -80014edc: 3030 fld fa2,96(s0) -80014ede: 3030 fld fa2,96(s0) - -80014ee0 <_ctype_>: -80014ee0: 2000 fld fs0,0(s0) -80014ee2: 2020 fld fs0,64(s0) -80014ee4: 2020 fld fs0,64(s0) -80014ee6: 2020 fld fs0,64(s0) -80014ee8: 2020 fld fs0,64(s0) -80014eea: 2828 fld fa0,80(s0) -80014eec: 2828 fld fa0,80(s0) -80014eee: 2028 fld fa0,64(s0) -80014ef0: 2020 fld fs0,64(s0) -80014ef2: 2020 fld fs0,64(s0) -80014ef4: 2020 fld fs0,64(s0) -80014ef6: 2020 fld fs0,64(s0) -80014ef8: 2020 fld fs0,64(s0) -80014efa: 2020 fld fs0,64(s0) -80014efc: 2020 fld fs0,64(s0) -80014efe: 2020 fld fs0,64(s0) -80014f00: 8820 0x8820 -80014f02: 1010 addi a2,sp,32 -80014f04: 1010 addi a2,sp,32 -80014f06: 1010 addi a2,sp,32 -80014f08: 1010 addi a2,sp,32 -80014f0a: 1010 addi a2,sp,32 -80014f0c: 1010 addi a2,sp,32 -80014f0e: 1010 addi a2,sp,32 -80014f10: 0410 addi a2,sp,512 -80014f12: 0404 addi s1,sp,512 -80014f14: 0404 addi s1,sp,512 -80014f16: 0404 addi s1,sp,512 -80014f18: 0404 addi s1,sp,512 -80014f1a: 1004 addi s1,sp,32 -80014f1c: 1010 addi a2,sp,32 -80014f1e: 1010 addi a2,sp,32 -80014f20: 1010 addi a2,sp,32 -80014f22: 4141 li sp,16 -80014f24: 4141 li sp,16 -80014f26: 4141 li sp,16 -80014f28: 0101 addi sp,sp,0 -80014f2a: 0101 addi sp,sp,0 -80014f2c: 0101 addi sp,sp,0 -80014f2e: 0101 addi sp,sp,0 -80014f30: 0101 addi sp,sp,0 -80014f32: 0101 addi sp,sp,0 -80014f34: 0101 addi sp,sp,0 -80014f36: 0101 addi sp,sp,0 -80014f38: 0101 addi sp,sp,0 -80014f3a: 0101 addi sp,sp,0 -80014f3c: 1010 addi a2,sp,32 -80014f3e: 1010 addi a2,sp,32 -80014f40: 1010 addi a2,sp,32 -80014f42: 4242 lw tp,16(sp) -80014f44: 4242 lw tp,16(sp) -80014f46: 4242 lw tp,16(sp) -80014f48: 0202 c.slli64 tp -80014f4a: 0202 c.slli64 tp -80014f4c: 0202 c.slli64 tp -80014f4e: 0202 c.slli64 tp -80014f50: 0202 c.slli64 tp -80014f52: 0202 c.slli64 tp -80014f54: 0202 c.slli64 tp -80014f56: 0202 c.slli64 tp -80014f58: 0202 c.slli64 tp -80014f5a: 0202 c.slli64 tp -80014f5c: 1010 addi a2,sp,32 -80014f5e: 1010 addi a2,sp,32 -80014f60: 0020 addi s0,sp,8 - ... -80014fe2: 0000 unimp -80014fe4: f260 fsw fs0,100(a2) -80014fe6: 8000 0x8000 -80014fe8: eec0 fsw fs0,28(a3) -80014fea: 8000 0x8000 -80014fec: eec0 fsw fs0,28(a3) -80014fee: 8000 0x8000 -80014ff0: f254 fsw fa3,36(a2) -80014ff2: 8000 0x8000 -80014ff4: eec0 fsw fs0,28(a3) -80014ff6: 8000 0x8000 -80014ff8: eec0 fsw fs0,28(a3) -80014ffa: 8000 0x8000 -80014ffc: eec0 fsw fs0,28(a3) -80014ffe: 8000 0x8000 -80015000: ed18 fsw fa4,24(a0) -80015002: 8000 0x8000 -80015004: eec0 fsw fs0,28(a3) -80015006: 8000 0x8000 -80015008: eec0 fsw fs0,28(a3) -8001500a: 8000 0x8000 -8001500c: f0f4 fsw fa3,100(s1) -8001500e: 8000 0x8000 -80015010: f0e4 fsw fs1,100(s1) -80015012: 8000 0x8000 -80015014: eec0 fsw fs0,28(a3) -80015016: 8000 0x8000 -80015018: f0d8 fsw fa4,36(s1) -8001501a: 8000 0x8000 -8001501c: f098 fsw fa4,32(s1) -8001501e: 8000 0x8000 -80015020: eec0 fsw fs0,28(a3) -80015022: 8000 0x8000 -80015024: f08c fsw fa1,32(s1) -80015026: 8000 0x8000 -80015028: ee90 fsw fa2,24(a3) -8001502a: 8000 0x8000 -8001502c: ee90 fsw fa2,24(a3) -8001502e: 8000 0x8000 -80015030: ee90 fsw fa2,24(a3) -80015032: 8000 0x8000 -80015034: ee90 fsw fa2,24(a3) -80015036: 8000 0x8000 -80015038: ee90 fsw fa2,24(a3) -8001503a: 8000 0x8000 -8001503c: ee90 fsw fa2,24(a3) -8001503e: 8000 0x8000 -80015040: ee90 fsw fa2,24(a3) -80015042: 8000 0x8000 -80015044: ee90 fsw fa2,24(a3) -80015046: 8000 0x8000 -80015048: ee90 fsw fa2,24(a3) -8001504a: 8000 0x8000 -8001504c: eec0 fsw fs0,28(a3) -8001504e: 8000 0x8000 -80015050: eec0 fsw fs0,28(a3) -80015052: 8000 0x8000 -80015054: eec0 fsw fs0,28(a3) -80015056: 8000 0x8000 -80015058: eec0 fsw fs0,28(a3) -8001505a: 8000 0x8000 -8001505c: eec0 fsw fs0,28(a3) -8001505e: 8000 0x8000 -80015060: eec0 fsw fs0,28(a3) -80015062: 8000 0x8000 -80015064: eec0 fsw fs0,28(a3) -80015066: 8000 0x8000 -80015068: eec0 fsw fs0,28(a3) -8001506a: 8000 0x8000 -8001506c: eec0 fsw fs0,28(a3) -8001506e: 8000 0x8000 -80015070: f184 fsw fs1,32(a1) -80015072: 8000 0x8000 -80015074: f118 fsw fa4,32(a0) -80015076: 8000 0x8000 -80015078: eec0 fsw fs0,28(a3) -8001507a: 8000 0x8000 -8001507c: eec0 fsw fs0,28(a3) -8001507e: 8000 0x8000 -80015080: eec0 fsw fs0,28(a3) -80015082: 8000 0x8000 -80015084: eec0 fsw fs0,28(a3) -80015086: 8000 0x8000 -80015088: eec0 fsw fs0,28(a3) -8001508a: 8000 0x8000 -8001508c: eec0 fsw fs0,28(a3) -8001508e: 8000 0x8000 -80015090: eec0 fsw fs0,28(a3) -80015092: 8000 0x8000 -80015094: eec0 fsw fs0,28(a3) -80015096: 8000 0x8000 -80015098: eec0 fsw fs0,28(a3) -8001509a: 8000 0x8000 -8001509c: eec0 fsw fs0,28(a3) -8001509e: 8000 0x8000 -800150a0: f030 fsw fa2,96(s0) -800150a2: 8000 0x8000 -800150a4: eec0 fsw fs0,28(a3) -800150a6: 8000 0x8000 -800150a8: eec0 fsw fs0,28(a3) -800150aa: 8000 0x8000 -800150ac: eec0 fsw fs0,28(a3) -800150ae: 8000 0x8000 -800150b0: efe4 fsw fs1,92(a5) -800150b2: 8000 0x8000 -800150b4: eec0 fsw fs0,28(a3) -800150b6: 8000 0x8000 -800150b8: f05c fsw fa5,36(s0) -800150ba: 8000 0x8000 -800150bc: eec0 fsw fs0,28(a3) -800150be: 8000 0x8000 -800150c0: eec0 fsw fs0,28(a3) -800150c2: 8000 0x8000 -800150c4: edf0 fsw fa2,92(a1) -800150c6: 8000 0x8000 -800150c8: eec0 fsw fs0,28(a3) -800150ca: 8000 0x8000 -800150cc: eec0 fsw fs0,28(a3) -800150ce: 8000 0x8000 -800150d0: eec0 fsw fs0,28(a3) -800150d2: 8000 0x8000 -800150d4: eec0 fsw fs0,28(a3) -800150d6: 8000 0x8000 -800150d8: eec0 fsw fs0,28(a3) -800150da: 8000 0x8000 -800150dc: eec0 fsw fs0,28(a3) -800150de: 8000 0x8000 -800150e0: eec0 fsw fs0,28(a3) -800150e2: 8000 0x8000 -800150e4: eec0 fsw fs0,28(a3) -800150e6: 8000 0x8000 -800150e8: eec0 fsw fs0,28(a3) -800150ea: 8000 0x8000 -800150ec: eec0 fsw fs0,28(a3) -800150ee: 8000 0x8000 -800150f0: f184 fsw fs1,32(a1) -800150f2: 8000 0x8000 -800150f4: f3e8 fsw fa0,100(a5) -800150f6: 8000 0x8000 -800150f8: eec0 fsw fs0,28(a3) -800150fa: 8000 0x8000 -800150fc: eec0 fsw fs0,28(a3) -800150fe: 8000 0x8000 -80015100: eec0 fsw fs0,28(a3) -80015102: 8000 0x8000 -80015104: f3d4 fsw fa3,36(a5) -80015106: 8000 0x8000 -80015108: f3e8 fsw fa0,100(a5) -8001510a: 8000 0x8000 -8001510c: ed54 fsw fa3,28(a0) -8001510e: 8000 0x8000 -80015110: eec0 fsw fs0,28(a3) -80015112: 8000 0x8000 -80015114: f3c0 fsw fs0,36(a5) -80015116: 8000 0x8000 -80015118: eec0 fsw fs0,28(a3) -8001511a: 8000 0x8000 -8001511c: f380 fsw fs0,32(a5) -8001511e: 8000 0x8000 -80015120: f340 fsw fs0,36(a4) -80015122: 8000 0x8000 -80015124: f304 fsw fs1,32(a4) -80015126: 8000 0x8000 -80015128: ed54 fsw fa3,28(a0) -8001512a: 8000 0x8000 -8001512c: eec0 fsw fs0,28(a3) -8001512e: 8000 0x8000 -80015130: efe4 fsw fs1,92(a5) -80015132: 8000 0x8000 -80015134: ed4c fsw fa1,28(a0) -80015136: 8000 0x8000 -80015138: f278 fsw fa4,100(a2) -8001513a: 8000 0x8000 -8001513c: eec0 fsw fs0,28(a3) -8001513e: 8000 0x8000 -80015140: eec0 fsw fs0,28(a3) -80015142: 8000 0x8000 -80015144: f2bc fsw fa5,96(a3) -80015146: 8000 0x8000 -80015148: eec0 fsw fs0,28(a3) -8001514a: 8000 0x8000 -8001514c: ed4c fsw fa1,28(a0) -8001514e: 8000 0x8000 - -80015150 : -80015150: 2020 fld fs0,64(s0) -80015152: 2020 fld fs0,64(s0) -80015154: 2020 fld fs0,64(s0) -80015156: 2020 fld fs0,64(s0) -80015158: 2020 fld fs0,64(s0) -8001515a: 2020 fld fs0,64(s0) -8001515c: 2020 fld fs0,64(s0) -8001515e: 2020 fld fs0,64(s0) - -80015160 : -80015160: 3030 fld fa2,96(s0) -80015162: 3030 fld fa2,96(s0) -80015164: 3030 fld fa2,96(s0) -80015166: 3030 fld fa2,96(s0) -80015168: 3030 fld fa2,96(s0) -8001516a: 3030 fld fa2,96(s0) -8001516c: 3030 fld fa2,96(s0) -8001516e: 3030 fld fa2,96(s0) -80015170: 0e84 addi s1,sp,848 -80015172: 8001 c.srli64 s0 -80015174: 0d98 addi a4,sp,720 -80015176: 8001 c.srli64 s0 -80015178: 0da4 addi s1,sp,728 -8001517a: 8001 c.srli64 s0 -8001517c: 0d98 addi a4,sp,720 -8001517e: 8001 c.srli64 s0 -80015180: 0e70 addi a2,sp,796 -80015182: 8001 c.srli64 s0 -80015184: 0d98 addi a4,sp,720 -80015186: 8001 c.srli64 s0 -80015188: 0da4 addi s1,sp,728 -8001518a: 8001 c.srli64 s0 -8001518c: 0e84 addi s1,sp,848 -8001518e: 8001 c.srli64 s0 -80015190: 0e84 addi s1,sp,848 -80015192: 8001 c.srli64 s0 -80015194: 0e70 addi a2,sp,796 -80015196: 8001 c.srli64 s0 -80015198: 0da4 addi s1,sp,728 -8001519a: 8001 c.srli64 s0 -8001519c: 0d70 addi a2,sp,668 -8001519e: 8001 c.srli64 s0 -800151a0: 0d70 addi a2,sp,668 -800151a2: 8001 c.srli64 s0 -800151a4: 0d70 addi a2,sp,668 -800151a6: 8001 c.srli64 s0 -800151a8: 0dac addi a1,sp,728 -800151aa: 8001 c.srli64 s0 -800151ac: 1350 addi a2,sp,420 -800151ae: 8001 c.srli64 s0 -800151b0: 1350 addi a2,sp,420 -800151b2: 8001 c.srli64 s0 -800151b4: 1374 addi a3,sp,428 -800151b6: 8001 c.srli64 s0 -800151b8: 1344 addi s1,sp,420 -800151ba: 8001 c.srli64 s0 -800151bc: 1344 addi s1,sp,420 -800151be: 8001 c.srli64 s0 -800151c0: 1434 addi a3,sp,552 -800151c2: 8001 c.srli64 s0 -800151c4: 1374 addi a3,sp,428 -800151c6: 8001 c.srli64 s0 -800151c8: 1344 addi s1,sp,420 -800151ca: 8001 c.srli64 s0 -800151cc: 1434 addi a3,sp,552 -800151ce: 8001 c.srli64 s0 -800151d0: 1344 addi s1,sp,420 -800151d2: 8001 c.srli64 s0 -800151d4: 1374 addi a3,sp,428 -800151d6: 8001 c.srli64 s0 -800151d8: 1340 addi s0,sp,420 -800151da: 8001 c.srli64 s0 -800151dc: 1340 addi s0,sp,420 -800151de: 8001 c.srli64 s0 -800151e0: 1340 addi s0,sp,420 -800151e2: 8001 c.srli64 s0 -800151e4: 1434 addi a3,sp,552 -800151e6: 8001 c.srli64 s0 -800151e8: 253c fld fa5,72(a0) -800151ea: 8001 c.srli64 s0 -800151ec: 253c fld fa5,72(a0) -800151ee: 8001 c.srli64 s0 -800151f0: 2538 fld fa4,72(a0) -800151f2: 8001 c.srli64 s0 -800151f4: 24ec fld fa1,200(s1) -800151f6: 8001 c.srli64 s0 -800151f8: 24ec fld fa1,200(s1) -800151fa: 8001 c.srli64 s0 -800151fc: 27a4 fld fs1,72(a5) -800151fe: 8001 c.srli64 s0 -80015200: 2538 fld fa4,72(a0) -80015202: 8001 c.srli64 s0 -80015204: 24ec fld fa1,200(s1) -80015206: 8001 c.srli64 s0 -80015208: 27a4 fld fs1,72(a5) -8001520a: 8001 c.srli64 s0 -8001520c: 24ec fld fa1,200(s1) -8001520e: 8001 c.srli64 s0 -80015210: 2538 fld fa4,72(a0) -80015212: 8001 c.srli64 s0 -80015214: 24e8 fld fa0,200(s1) -80015216: 8001 c.srli64 s0 -80015218: 24e8 fld fa0,200(s1) -8001521a: 8001 c.srli64 s0 -8001521c: 24e8 fld fa0,200(s1) -8001521e: 8001 c.srli64 s0 -80015220: 27a4 fld fs1,72(a5) -80015222: 8001 c.srli64 s0 - -80015224 <__clz_tab>: -80015224: 0100 addi s0,sp,128 -80015226: 0202 c.slli64 tp -80015228: 03030303 lb t1,48(t1) -8001522c: 0404 addi s1,sp,512 -8001522e: 0404 addi s1,sp,512 -80015230: 0404 addi s1,sp,512 -80015232: 0404 addi s1,sp,512 -80015234: 0505 addi a0,a0,1 -80015236: 0505 addi a0,a0,1 -80015238: 0505 addi a0,a0,1 -8001523a: 0505 addi a0,a0,1 -8001523c: 0505 addi a0,a0,1 -8001523e: 0505 addi a0,a0,1 -80015240: 0505 addi a0,a0,1 -80015242: 0505 addi a0,a0,1 -80015244: 0606 slli a2,a2,0x1 -80015246: 0606 slli a2,a2,0x1 -80015248: 0606 slli a2,a2,0x1 -8001524a: 0606 slli a2,a2,0x1 -8001524c: 0606 slli a2,a2,0x1 -8001524e: 0606 slli a2,a2,0x1 -80015250: 0606 slli a2,a2,0x1 -80015252: 0606 slli a2,a2,0x1 -80015254: 0606 slli a2,a2,0x1 -80015256: 0606 slli a2,a2,0x1 -80015258: 0606 slli a2,a2,0x1 -8001525a: 0606 slli a2,a2,0x1 -8001525c: 0606 slli a2,a2,0x1 -8001525e: 0606 slli a2,a2,0x1 -80015260: 0606 slli a2,a2,0x1 -80015262: 0606 slli a2,a2,0x1 -80015264: 07070707 0x7070707 -80015268: 07070707 0x7070707 -8001526c: 07070707 0x7070707 -80015270: 07070707 0x7070707 -80015274: 07070707 0x7070707 -80015278: 07070707 0x7070707 -8001527c: 07070707 0x7070707 -80015280: 07070707 0x7070707 -80015284: 07070707 0x7070707 -80015288: 07070707 0x7070707 -8001528c: 07070707 0x7070707 -80015290: 07070707 0x7070707 -80015294: 07070707 0x7070707 -80015298: 07070707 0x7070707 -8001529c: 07070707 0x7070707 -800152a0: 07070707 0x7070707 -800152a4: 0808 addi a0,sp,16 -800152a6: 0808 addi a0,sp,16 -800152a8: 0808 addi a0,sp,16 -800152aa: 0808 addi a0,sp,16 -800152ac: 0808 addi a0,sp,16 -800152ae: 0808 addi a0,sp,16 -800152b0: 0808 addi a0,sp,16 -800152b2: 0808 addi a0,sp,16 -800152b4: 0808 addi a0,sp,16 -800152b6: 0808 addi a0,sp,16 -800152b8: 0808 addi a0,sp,16 -800152ba: 0808 addi a0,sp,16 -800152bc: 0808 addi a0,sp,16 -800152be: 0808 addi a0,sp,16 -800152c0: 0808 addi a0,sp,16 -800152c2: 0808 addi a0,sp,16 -800152c4: 0808 addi a0,sp,16 -800152c6: 0808 addi a0,sp,16 -800152c8: 0808 addi a0,sp,16 -800152ca: 0808 addi a0,sp,16 -800152cc: 0808 addi a0,sp,16 -800152ce: 0808 addi a0,sp,16 -800152d0: 0808 addi a0,sp,16 -800152d2: 0808 addi a0,sp,16 -800152d4: 0808 addi a0,sp,16 -800152d6: 0808 addi a0,sp,16 -800152d8: 0808 addi a0,sp,16 -800152da: 0808 addi a0,sp,16 -800152dc: 0808 addi a0,sp,16 -800152de: 0808 addi a0,sp,16 -800152e0: 0808 addi a0,sp,16 -800152e2: 0808 addi a0,sp,16 -800152e4: 0808 addi a0,sp,16 -800152e6: 0808 addi a0,sp,16 -800152e8: 0808 addi a0,sp,16 -800152ea: 0808 addi a0,sp,16 -800152ec: 0808 addi a0,sp,16 -800152ee: 0808 addi a0,sp,16 -800152f0: 0808 addi a0,sp,16 -800152f2: 0808 addi a0,sp,16 -800152f4: 0808 addi a0,sp,16 -800152f6: 0808 addi a0,sp,16 -800152f8: 0808 addi a0,sp,16 -800152fa: 0808 addi a0,sp,16 -800152fc: 0808 addi a0,sp,16 -800152fe: 0808 addi a0,sp,16 -80015300: 0808 addi a0,sp,16 -80015302: 0808 addi a0,sp,16 -80015304: 0808 addi a0,sp,16 -80015306: 0808 addi a0,sp,16 -80015308: 0808 addi a0,sp,16 -8001530a: 0808 addi a0,sp,16 -8001530c: 0808 addi a0,sp,16 -8001530e: 0808 addi a0,sp,16 -80015310: 0808 addi a0,sp,16 -80015312: 0808 addi a0,sp,16 -80015314: 0808 addi a0,sp,16 -80015316: 0808 addi a0,sp,16 -80015318: 0808 addi a0,sp,16 -8001531a: 0808 addi a0,sp,16 -8001531c: 0808 addi a0,sp,16 -8001531e: 0808 addi a0,sp,16 -80015320: 0808 addi a0,sp,16 -80015322: 0808 addi a0,sp,16 - -Disassembly of section .eh_frame: - -80015324 <.eh_frame>: -80015324: 0010 0x10 -80015326: 0000 unimp -80015328: 0000 unimp -8001532a: 0000 unimp -8001532c: 7a01 lui s4,0xfffe0 -8001532e: 0052 c.slli zero,0x14 -80015330: 7c01 lui s8,0xfffe0 -80015332: 0101 addi sp,sp,0 -80015334: 00020d1b 0x20d1b -80015338: 0010 0x10 -8001533a: 0000 unimp -8001533c: 0018 0x18 -8001533e: 0000 unimp -80015340: ac64 fsd fs1,216(s0) -80015342: ffff 0xffff -80015344: 0434 addi a3,sp,520 -80015346: 0000 unimp -80015348: 0000 unimp -8001534a: 0000 unimp -8001534c: 0010 0x10 -8001534e: 0000 unimp -80015350: 002c addi a1,sp,8 -80015352: 0000 unimp -80015354: b084 fsd fs1,32(s1) -80015356: ffff 0xffff -80015358: 0410 addi a2,sp,512 -8001535a: 0000 unimp -8001535c: 0000 unimp - ... - -Disassembly of section .init_array: - -80016360 <__init_array_start>: -80016360: 0048 addi a0,sp,4 -80016362: 8000 0x8000 - -Disassembly of section .data: - -80016368 <__DATA_BEGIN__>: -80016368: 0000 unimp -8001636a: 0000 unimp -8001636c: 6654 flw fa3,12(a2) -8001636e: 8001 c.srli64 s0 -80016370: 66bc flw fa5,72(a3) -80016372: 8001 c.srli64 s0 -80016374: 6724 flw fs1,72(a4) -80016376: 8001 c.srli64 s0 - ... -80016410: 0001 nop -80016412: 0000 unimp -80016414: 0000 unimp -80016416: 0000 unimp -80016418: 330e fld ft6,224(sp) -8001641a: abcd j 80016a0c <__malloc_av_+0x27c> -8001641c: 1234 addi a3,sp,296 -8001641e: e66d bnez a2,80016508 <__DATA_BEGIN__+0x1a0> -80016420: deec sw a1,124(a3) -80016422: 0005 c.nop 1 -80016424: 0000000b 0xb - ... - -80016790 <__malloc_av_>: - ... -80016798: 6790 flw fa2,8(a5) -8001679a: 8001 c.srli64 s0 -8001679c: 6790 flw fa2,8(a5) -8001679e: 8001 c.srli64 s0 -800167a0: 6798 flw fa4,8(a5) -800167a2: 8001 c.srli64 s0 -800167a4: 6798 flw fa4,8(a5) -800167a6: 8001 c.srli64 s0 -800167a8: 67a0 flw fs0,72(a5) -800167aa: 8001 c.srli64 s0 -800167ac: 67a0 flw fs0,72(a5) -800167ae: 8001 c.srli64 s0 -800167b0: 67a8 flw fa0,72(a5) -800167b2: 8001 c.srli64 s0 -800167b4: 67a8 flw fa0,72(a5) -800167b6: 8001 c.srli64 s0 -800167b8: 67b0 flw fa2,72(a5) -800167ba: 8001 c.srli64 s0 -800167bc: 67b0 flw fa2,72(a5) -800167be: 8001 c.srli64 s0 -800167c0: 67b8 flw fa4,72(a5) -800167c2: 8001 c.srli64 s0 -800167c4: 67b8 flw fa4,72(a5) -800167c6: 8001 c.srli64 s0 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flw fa2,84(a4) -80016b7a: 8001 c.srli64 s0 -80016b7c: 6b70 flw fa2,84(a4) -80016b7e: 8001 c.srli64 s0 -80016b80: 6b78 flw fa4,84(a4) -80016b82: 8001 c.srli64 s0 -80016b84: 6b78 flw fa4,84(a4) -80016b86: 8001 c.srli64 s0 -80016b88: 6b80 flw fs0,16(a5) -80016b8a: 8001 c.srli64 s0 -80016b8c: 6b80 flw fs0,16(a5) -80016b8e: 8001 c.srli64 s0 -80016b90: 6b88 flw fa0,16(a5) -80016b92: 8001 c.srli64 s0 -80016b94: 6b88 flw fa0,16(a5) -80016b96: 8001 c.srli64 s0 - -80016b98 <__global_locale>: -80016b98: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016bb8: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016bd8: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016bf8: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016c18: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016c38: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016c58: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016c78: d714 sw a3,40(a4) -80016c7a: 8000 0x8000 -80016c7c: 7fc4 flw fs1,60(a5) -80016c7e: 8000 0x8000 -80016c80: 0000 unimp -80016c82: 0000 unimp -80016c84: 4ee0 lw s0,92(a3) -80016c86: 8001 c.srli64 s0 -80016c88: 4a9c lw a5,16(a3) -80016c8a: 8001 c.srli64 s0 -80016c8c: 4804 lw s1,16(s0) -80016c8e: 8001 c.srli64 s0 -80016c90: 4804 lw s1,16(s0) -80016c92: 8001 c.srli64 s0 -80016c94: 4804 lw s1,16(s0) -80016c96: 8001 c.srli64 s0 -80016c98: 4804 lw s1,16(s0) -80016c9a: 8001 c.srli64 s0 -80016c9c: 4804 lw s1,16(s0) -80016c9e: 8001 c.srli64 s0 -80016ca0: 4804 lw s1,16(s0) -80016ca2: 8001 c.srli64 s0 -80016ca4: 4804 lw s1,16(s0) -80016ca6: 8001 c.srli64 s0 -80016ca8: 4804 lw s1,16(s0) -80016caa: 8001 c.srli64 s0 -80016cac: 4804 lw s1,16(s0) -80016cae: 8001 c.srli64 s0 -80016cb0: ffff 0xffff -80016cb2: ffff 0xffff -80016cb4: ffff 0xffff -80016cb6: ffff 0xffff -80016cb8: ffff 0xffff -80016cba: ffff 0xffff -80016cbc: ffff 0xffff -80016cbe: 0000 unimp -80016cc0: 0001 nop -80016cc2: 5341 li t1,-16 -80016cc4: 00494943 fmadd.s fs2,fs2,ft4,ft0,rmm - ... -80016ce0: 0000 unimp -80016ce2: 5341 li t1,-16 -80016ce4: 00494943 fmadd.s fs2,fs2,ft4,ft0,rmm - ... - -Disassembly of section .sdata: - -80016d08 <__SDATA_BEGIN__>: -80016d08: 0000 unimp -80016d0a: 0000 unimp -80016d0c: 0000 unimp -80016d0e: 3ff0 fld fa2,248(a5) -80016d10: 0000 unimp -80016d12: 0000 unimp -80016d14: 0000 unimp -80016d16: 4024 lw s1,64(s0) -80016d18: 0000 unimp -80016d1a: 0000 unimp -80016d1c: 0000 unimp -80016d1e: 4350 lw a2,4(a4) - -80016d20 <_global_impure_ptr>: -80016d20: 6368 flw fa0,68(a4) -80016d22: 8001 c.srli64 s0 - -80016d24 : -80016d24: 0000 unimp -80016d26: 7000 flw fs0,32(s0) - -80016d28 : -80016d28: 0000 unimp -80016d2a: 1000 addi s0,sp,32 - -80016d2c : -80016d2c: 0000 unimp -80016d2e: 2000 fld fs0,0(s0) - -80016d30 <_impure_ptr>: -80016d30: 6368 flw fa0,68(a4) -80016d32: 8001 c.srli64 s0 - -80016d34 <__malloc_sbrk_base>: -80016d34: ffff 0xffff -80016d36: ffff 0xffff - -80016d38 <__malloc_trim_threshold>: -80016d38: 0000 unimp -80016d3a: 0002 c.slli64 zero - -Disassembly of section .sbss: - -80016d3c <__malloc_max_total_mem>: -80016d3c: 0000 unimp - ... - -80016d40 <__malloc_max_sbrked_mem>: -80016d40: 0000 unimp - ... - -80016d44 <__malloc_top_pad>: -80016d44: 0000 unimp - ... - -Disassembly of section .bss: - -80016d48 : -80016d48: 0000 unimp - ... - -80016d4c <__malloc_current_mallinfo>: - ... - -80016d74 : -80016d74: 0000 unimp - ... - -Disassembly of section .comment: - -00000000 <.comment>: - 0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm - 4: 2820 fld fs0,80(s0) - 6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm - a: 3820 fld fs0,112(s0) - c: 332e fld ft6,232(sp) - e: 302e fld ft0,232(sp) - ... - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2341 jal 580 <_start-0x7ffffa80> - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <_start-0x7fffffec> - c: 0019 c.nop 6 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3376 fld ft6,376(sp) - 14: 6932 flw fs2,12(sp) - 16: 7032 flw ft0,44(sp) - 18: 5f30 lw a2,120(a4) - 1a: 326d jal fffff9c4 <__BSS_END__+0x7ffe8c4c> - 1c: 3070 fld fa2,224(s0) - 1e: 765f 7032 0030 0x307032765f - -Disassembly of section .debug_aranges: - -00000000 <.debug_aranges>: - 0: 001c 0x1c - 2: 0000 unimp - 4: 0002 c.slli64 zero - 6: 0000 unimp - 8: 0000 unimp - a: 0004 0x4 - c: 0000 unimp - e: 0000 unimp - 10: ffa4 fsw fs1,120(a5) - 12: 8000 0x8000 - 14: 0434 addi a3,sp,520 - ... - 1e: 0000 unimp - 20: 001c 0x1c - 22: 0000 unimp - 24: 0002 c.slli64 zero - 26: 121a slli tp,tp,0x26 - 28: 0000 unimp - 2a: 0004 0x4 - 2c: 0000 unimp - 2e: 0000 unimp - 30: 03d8 addi a4,sp,452 - 32: 8001 c.srli64 s0 - 34: 0410 addi a2,sp,512 - ... - 3e: 0000 unimp - 40: 001c 0x1c - 42: 0000 unimp - 44: 0002 c.slli64 zero - 46: 2492 fld fs1,256(sp) - 48: 0000 unimp - 4a: 0004 0x4 - 4c: 0000 unimp - 4e: 0000 unimp - 50: 07e8 addi a0,sp,972 - 52: 8001 c.srli64 s0 - 54: 06c8 addi a0,sp,836 - ... - 5e: 0000 unimp - 60: 001c 0x1c - 62: 0000 unimp - 64: 0002 c.slli64 zero - 66: 2bc6 fld fs7,80(sp) - 68: 0000 unimp - 6a: 0004 0x4 - 6c: 0000 unimp - 6e: 0000 unimp - 70: 0eb0 addi a2,sp,856 - 72: 8001 c.srli64 s0 - 74: 05b8 addi a4,sp,712 - ... - 7e: 0000 unimp - 80: 001c 0x1c - 82: 0000 unimp - 84: 0002 c.slli64 zero - 86: 3332 fld ft6,296(sp) - 88: 0000 unimp - 8a: 0004 0x4 - 8c: 0000 unimp - 8e: 0000 unimp - 90: 1468 addi a0,sp,556 - 92: 8001 c.srli64 s0 - 94: 00cc addi a1,sp,68 - ... - 9e: 0000 unimp - a0: 001c 0x1c - a2: 0000 unimp - a4: 0002 c.slli64 zero - a6: 35ca fld fa1,176(sp) - a8: 0000 unimp - aa: 0004 0x4 - ac: 0000 unimp - ae: 0000 unimp - b0: 1534 addi a3,sp,680 - b2: 8001 c.srli64 s0 - b4: 0144 addi s1,sp,132 - ... - be: 0000 unimp - c0: 001c 0x1c - c2: 0000 unimp - c4: 0002 c.slli64 zero - c6: 3860 fld fs0,240(s0) - c8: 0000 unimp - ca: 0004 0x4 - cc: 0000 unimp - ce: 0000 unimp - d0: 1678 addi a4,sp,812 - d2: 8001 c.srli64 s0 - d4: 0144 addi s1,sp,132 - ... - de: 0000 unimp - e0: 001c 0x1c - e2: 0000 unimp - e4: 0002 c.slli64 zero - e6: 3af6 fld fs5,376(sp) - e8: 0000 unimp - ea: 0004 0x4 - ec: 0000 unimp - ee: 0000 unimp - f0: 17bc addi a5,sp,1000 - f2: 8001 c.srli64 s0 - f4: 1008 addi a0,sp,32 - ... - fe: 0000 unimp - 100: 001c 0x1c - 102: 0000 unimp - 104: 0002 c.slli64 zero - 106: 4d62 lw s10,24(sp) - 108: 0000 unimp - 10a: 0004 0x4 - 10c: 0000 unimp - 10e: 0000 unimp - 110: 27c4 fld fs1,136(a5) - 112: 8001 c.srli64 s0 - 114: 1520 addi s0,sp,680 - ... - 11e: 0000 unimp - 120: 001c 0x1c - 122: 0000 unimp - 124: 0002 c.slli64 zero - 126: 5ae5 li s5,-7 - 128: 0000 unimp - 12a: 0004 0x4 - 12c: 0000 unimp - 12e: 0000 unimp - 130: 3ce4 fld fs1,248(s1) - 132: 8001 c.srli64 s0 - 134: 0150 addi a2,sp,132 - ... - 13e: 0000 unimp - 140: 001c 0x1c - 142: 0000 unimp - 144: 0002 c.slli64 zero - 146: 5daa lw s11,168(sp) - 148: 0000 unimp - 14a: 0004 0x4 - 14c: 0000 unimp - 14e: 0000 unimp - 150: 3e34 fld fa3,120(a2) - 152: 8001 c.srli64 s0 - 154: 0188 addi a0,sp,192 - ... - 15e: 0000 unimp - 160: 001c 0x1c - 162: 0000 unimp - 164: 0002 c.slli64 zero - 166: 6170 flw fa2,68(a0) - 168: 0000 unimp - 16a: 0004 0x4 - 16c: 0000 unimp - 16e: 0000 unimp - 170: 3fbc fld fa5,120(a5) - 172: 8001 c.srli64 s0 - 174: 020c addi a1,sp,256 - ... - 17e: 0000 unimp - 180: 001c 0x1c - 182: 0000 unimp - 184: 0002 c.slli64 zero - 186: 655f 0000 0004 0x40000655f - 18c: 0000 unimp - 18e: 0000 unimp - 190: 41c8 lw a0,4(a1) - 192: 8001 c.srli64 s0 - 194: 0334 addi a3,sp,392 - ... - 19e: 0000 unimp - 1a0: 0014 0x14 - 1a2: 0000 unimp - 1a4: 0002 c.slli64 zero - 1a6: 6a9a flw fs5,132(sp) - 1a8: 0000 unimp - 1aa: 0004 0x4 - ... - 1b8: 001c 0x1c - 1ba: 0000 unimp - 1bc: 0002 c.slli64 zero - 1be: 75d9 lui a1,0xffff6 - 1c0: 0000 unimp - 1c2: 0004 0x4 - 1c4: 0000 unimp - 1c6: 0000 unimp - 1c8: 44fc lw a5,76(s1) - 1ca: 8001 c.srli64 s0 - 1cc: 004c addi a1,sp,4 - ... - -Disassembly of section .debug_info: - -00000000 <.debug_info>: - 0: 1216 slli tp,tp,0x25 - 2: 0000 unimp - 4: 0004 0x4 - 6: 0000 unimp - 8: 0000 unimp - a: 0104 addi s1,sp,128 - c: 00e5 addi ra,ra,25 - e: 0000 unimp - 10: f90c fsw fa1,48(a0) - 12: 0004 0x4 - 14: fc00 fsw fs0,56(s0) - 16: 0002 c.slli64 zero - 18: a400 fsd fs0,8(s0) - 1a: 00ff 0xff - 1c: 3480 fld fs0,40(s1) - 1e: 0004 0x4 - 20: 0000 unimp - 22: 0000 unimp - 24: 0200 addi s0,sp,256 - 26: 0708 addi a0,sp,896 - 28: 0364 addi s1,sp,396 - 2a: 0000 unimp - 2c: 0402 c.slli64 s0 - 2e: 00036e07 vlwu.v v28,(t1),v0.t - 32: 0300 addi s0,sp,384 - 34: 0504 addi s1,sp,640 - 36: 6e69 lui t3,0x1a - 38: 0074 addi a3,sp,12 - 3a: 0802 c.slli64 a6 - 3c: 1d05 addi s10,s10,-31 - 3e: 0002 c.slli64 zero - 40: 0200 addi s0,sp,256 - 42: 0410 addi a2,sp,512 - 44: 009d addi ra,ra,7 - 46: 0000 unimp - 48: 0102 c.slli64 sp - 4a: 6906 flw fs2,64(sp) - 4c: 0006 c.slli zero,0x1 - 4e: 0200 addi s0,sp,256 - 50: 0801 addi a6,a6,0 - 52: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 56: 0202 c.slli64 tp - 58: 0005 c.nop 1 - 5a: 0000 unimp - 5c: 0200 addi s0,sp,256 - 5e: 0702 c.slli64 a4 - 60: 0384 addi s1,sp,448 - 62: 0000 unimp - 64: 0402 c.slli64 s0 - 66: 2205 jal 186 <_start-0x7ffffe7a> - 68: 0002 c.slli64 zero - 6a: 0200 addi s0,sp,256 - 6c: 0704 addi s1,sp,896 - 6e: 0369 addi t1,t1,26 - 70: 0000 unimp - 72: e104 fsw fs1,0(a0) - 74: 0004 0x4 - 76: 0200 addi s0,sp,256 - 78: 0d0c addi a1,sp,656 - 7a: 00000033 add zero,zero,zero - 7e: b104 fsd fs1,32(a0) - 80: 0004 0x4 - 82: 0300 addi s0,sp,384 - 84: 0e2c addi a1,sp,792 - 86: 0064 addi s1,sp,12 - 88: 0000 unimp - 8a: fa04 fsw fs1,48(a2) - 8c: 0005 c.nop 1 - 8e: 0300 addi s0,sp,384 - 90: 0e72 slli t3,t3,0x1c - 92: 0064 addi s1,sp,12 - 94: 0000 unimp - 96: d104 sw s1,32(a0) - 98: 0006 c.slli zero,0x1 - 9a: 0300 addi s0,sp,384 - 9c: 1791 addi a5,a5,-28 - 9e: 00000033 add zero,zero,zero - a2: e405 bnez s0,ca <_start-0x7fffff36> - a4: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - a8: 0165 addi sp,sp,25 - aa: 00002c17 auipc s8,0x2 - ae: 0600 addi s0,sp,768 - b0: 0304 addi s1,sp,384 - b2: 03a6 slli t2,t2,0x9 - b4: 00d1 addi ra,ra,20 - b6: 0000 unimp - b8: 0003cb07 flq fs6,0(t2) - bc: 0300 addi s0,sp,384 - be: 0ca8 addi a0,sp,600 - c0: 00a2 slli ra,ra,0x8 - c2: 0000 unimp - c4: 0002d507 vlhu.v v10,(t0),v0.t - c8: 0300 addi s0,sp,384 - ca: 13a9 addi t2,t2,-22 - cc: 00d1 addi ra,ra,20 - ce: 0000 unimp - d0: 0800 addi s0,sp,16 - d2: 0000004f fnmadd.s ft0,ft0,ft0,ft0,rne - d6: 00e1 addi ra,ra,24 - d8: 0000 unimp - da: 2c09 jal 2ec <_start-0x7ffffd14> - dc: 0000 unimp - de: 0300 addi s0,sp,384 - e0: 0a00 addi s0,sp,272 - e2: 0308 addi a0,sp,384 - e4: 010509a3 sb a6,19(a0) # fffe5013 <__BSS_END__+0x7ffce29b> - e8: 0000 unimp - ea: 0004350b 0x4350b - ee: 0300 addi s0,sp,384 - f0: 07a5 addi a5,a5,9 - f2: 00000033 add zero,zero,zero - f6: 0b00 addi s0,sp,400 - f8: 05ec addi a1,sp,716 - fa: 0000 unimp - fc: af05aa03 lw s4,-1296(a1) # ffff5af0 <__BSS_END__+0x7ffded78> - 100: 0000 unimp - 102: 0400 addi s0,sp,512 - 104: 0400 addi s0,sp,512 - 106: 04d6 slli s1,s1,0x15 - 108: 0000 unimp - 10a: e103ab03 lw s6,-496(t2) - 10e: 0000 unimp - 110: 0400 addi s0,sp,512 - 112: 00000557 vadd.vv v10,v0,v0,v0.t - 116: 721baf03 lw t5,1825(s7) # 1d721 <_start-0x7ffe28df> - 11a: 0000 unimp - 11c: 0c00 addi s0,sp,528 - 11e: 0404 addi s1,sp,512 - 120: 067a slli a2,a2,0x1e - 122: 0000 unimp - 124: 1605 addi a2,a2,-31 - 126: 6b19 lui s6,0x6 - 128: 0000 unimp - 12a: 0d00 addi s0,sp,656 - 12c: 046e slli s0,s0,0x1b - 12e: 0000 unimp - 130: 0518 addi a4,sp,640 - 132: 0185082f 0x185082f - 136: 0000 unimp - 138: 0007910b 0x7910b - 13c: 0500 addi s0,sp,640 - 13e: 1331 addi t1,t1,-20 - 140: 0185 addi gp,gp,1 - 142: 0000 unimp - 144: 0e00 addi s0,sp,784 - 146: 6b5f 0500 0732 0x73205006b5f - 14c: 00000033 add zero,zero,zero - 150: 0b04 addi s1,sp,400 - 152: 05c9 addi a1,a1,18 - 154: 0000 unimp - 156: 3205 jal fffffa76 <__BSS_END__+0x7ffe8cfe> - 158: 0000330b 0x330b - 15c: 0800 addi s0,sp,16 - 15e: 0002790b 0x2790b - 162: 0500 addi s0,sp,640 - 164: 1432 slli s0,s0,0x2c - 166: 00000033 add zero,zero,zero - 16a: 0b0c addi a1,sp,400 - 16c: 01ff 0x1ff - 16e: 0000 unimp - 170: 3205 jal fffffa90 <__BSS_END__+0x7ffe8d18> - 172: 0000331b 0x331b - 176: 1000 addi s0,sp,32 - 178: 5f0e lw t5,224(sp) - 17a: 0078 addi a4,sp,12 - 17c: 3305 jal fffffe9c <__BSS_END__+0x7ffe9124> - 17e: 00018b0b 0x18b0b - 182: 1400 addi s0,sp,544 - 184: 0f00 addi s0,sp,912 - 186: 2b04 fld fs1,16(a4) - 188: 0001 nop - 18a: 0800 addi s0,sp,16 - 18c: 011f 0000 019b 0x19b0000011f - 192: 0000 unimp - 194: 2c09 jal 3a6 <_start-0x7ffffc5a> - 196: 0000 unimp - 198: 0000 unimp - 19a: 0d00 addi s0,sp,656 - 19c: 02b8 addi a4,sp,328 - 19e: 0000 unimp - 1a0: 0524 addi s1,sp,648 - 1a2: 021e0837 lui a6,0x21e0 - 1a6: 0000 unimp - 1a8: 0000d50b 0xd50b - 1ac: 0500 addi s0,sp,640 - 1ae: 0939 addi s2,s2,14 - 1b0: 00000033 add zero,zero,zero - 1b4: 0b00 addi s0,sp,400 - 1b6: 0000072f 0x72f - 1ba: 3a05 jal fffffaea <__BSS_END__+0x7ffe8d72> - 1bc: 3309 jal fffffebe <__BSS_END__+0x7ffe9146> - 1be: 0000 unimp - 1c0: 0400 addi s0,sp,512 - 1c2: 0001b50b 0x1b50b - 1c6: 0500 addi s0,sp,640 - 1c8: 0033093b 0x33093b - 1cc: 0000 unimp - 1ce: 0b08 addi a0,sp,400 - 1d0: 0782 c.slli64 a5 - 1d2: 0000 unimp - 1d4: 3c05 jal fffffc04 <__BSS_END__+0x7ffe8e8c> - 1d6: 3309 jal fffffed8 <__BSS_END__+0x7ffe9160> - 1d8: 0000 unimp - 1da: 0c00 addi s0,sp,528 - 1dc: 00048b0b 0x48b0b - 1e0: 0500 addi s0,sp,640 - 1e2: 093d addi s2,s2,15 - 1e4: 00000033 add zero,zero,zero - 1e8: 0b10 addi a2,sp,400 - 1ea: 0000042b 0x42b - 1ee: 3e05 jal fffffd1e <__BSS_END__+0x7ffe8fa6> - 1f0: 3309 jal fffffef2 <__BSS_END__+0x7ffe917a> - 1f2: 0000 unimp - 1f4: 1400 addi s0,sp,544 - 1f6: 0006ba0b 0x6ba0b - 1fa: 0500 addi s0,sp,640 - 1fc: 0033093f 0b180000 0xb1800000033093f - 204: 0560 addi s0,sp,652 - 206: 0000 unimp - 208: 4005 c.li zero,1 - 20a: 3309 jal ffffff0c <__BSS_END__+0x7ffe9194> - 20c: 0000 unimp - 20e: 1c00 addi s0,sp,560 - 210: 0007150b 0x7150b - 214: 0500 addi s0,sp,640 - 216: 0941 addi s2,s2,16 - 218: 00000033 add zero,zero,zero - 21c: 0020 addi s0,sp,8 - 21e: d210 sw a2,32(a2) - 220: 0001 nop - 222: 0800 addi s0,sp,16 - 224: 0501 addi a0,a0,0 - 226: 084a slli a6,a6,0x12 - 228: 00000263 beqz zero,22c <_start-0x7ffffdd4> - 22c: 00026c0b 0x26c0b - 230: 0500 addi s0,sp,640 - 232: 02630a4b fnmsub.d fs4,ft6,ft6,ft0,rne - 236: 0000 unimp - 238: 0b00 addi s0,sp,400 - 23a: 00000533 add a0,zero,zero - 23e: 4c05 li s8,1 - 240: 6309 lui t1,0x2 - 242: 0002 c.slli64 zero - 244: 8000 0x8000 - 246: 5e11 li t3,-28 - 248: 0006 c.slli zero,0x1 - 24a: 0500 addi s0,sp,640 - 24c: 0a4e slli s4,s4,0x13 - 24e: 011f 0000 0100 0x1000000011f - 254: f711 bnez a4,160 <_start-0x7ffffea0> - 256: 0001 nop - 258: 0500 addi s0,sp,640 - 25a: 0a51 addi s4,s4,20 - 25c: 011f 0000 0104 0x1040000011f - 262: 0800 addi s0,sp,16 - 264: 011d addi sp,sp,7 - 266: 0000 unimp - 268: 00000273 0x273 - 26c: 2c09 jal 47e <_start-0x7ffffb82> - 26e: 0000 unimp - 270: 1f00 addi s0,sp,944 - 272: 1000 addi s0,sp,32 - 274: 0494 addi a3,sp,576 - 276: 0000 unimp - 278: 0190 addi a2,sp,192 - 27a: 5d05 li s10,-31 - 27c: b608 fsd fa0,40(a2) - 27e: 0002 c.slli64 zero - 280: 0b00 addi s0,sp,400 - 282: 0791 addi a5,a5,4 - 284: 0000 unimp - 286: 5e05 li t3,-31 - 288: b612 fsd ft4,296(sp) - 28a: 0002 c.slli64 zero - 28c: 0000 unimp - 28e: 0005b00b 0x5b00b - 292: 0500 addi s0,sp,640 - 294: 065f 0033 0000 0x33065f - 29a: 0b04 addi s1,sp,400 - 29c: 0274 addi a3,sp,268 - 29e: 0000 unimp - 2a0: 6105 addi sp,sp,32 - 2a2: bc09 j fffffcb4 <__BSS_END__+0x7ffe8f3c> - 2a4: 0002 c.slli64 zero - 2a6: 0800 addi s0,sp,16 - 2a8: 0001d20b 0x1d20b - 2ac: 0500 addi s0,sp,640 - 2ae: 1e62 slli t3,t3,0x38 - 2b0: 021e slli tp,tp,0x7 - 2b2: 0000 unimp - 2b4: 0088 addi a0,sp,64 - 2b6: 0273040f 0x273040f - 2ba: 0000 unimp - 2bc: cc08 sw a0,24(s0) - 2be: 0002 c.slli64 zero - 2c0: cc00 sw s0,24(s0) - 2c2: 0002 c.slli64 zero - 2c4: 0900 addi s0,sp,144 - 2c6: 002c addi a1,sp,8 - 2c8: 0000 unimp - 2ca: 001f 040f 02d2 0x2d2040f001f - 2d0: 0000 unimp - 2d2: 0d12 slli s10,s10,0x4 - 2d4: 0000077b 0x77b - 2d8: 0508 addi a0,sp,640 - 2da: 0875 addi a6,a6,29 - 2dc: 000002fb 0x2fb - 2e0: 0001af0b 0x1af0b - 2e4: 0500 addi s0,sp,640 - 2e6: 1176 slli sp,sp,0x3d - 2e8: 000002fb 0x2fb - 2ec: 0b00 addi s0,sp,400 - 2ee: 0000060b 0x60b - 2f2: 7705 lui a4,0xfffe1 - 2f4: 3306 fld ft6,96(sp) - 2f6: 0000 unimp - 2f8: 0400 addi s0,sp,512 - 2fa: 0f00 addi s0,sp,912 - 2fc: 4f04 lw s1,24(a4) - 2fe: 0000 unimp - 300: 0d00 addi s0,sp,656 - 302: 058c addi a1,sp,704 - 304: 0000 unimp - 306: 0568 addi a0,sp,652 - 308: 08b5 addi a7,a7,13 - 30a: 0444 addi s1,sp,516 - 30c: 0000 unimp - 30e: 5f0e lw t5,224(sp) - 310: 0070 addi a2,sp,12 - 312: b605 j fffffe32 <__BSS_END__+0x7ffe90ba> - 314: fb12 fsw ft4,180(sp) - 316: 0002 c.slli64 zero - 318: 0000 unimp - 31a: 5f0e lw t5,224(sp) - 31c: 0072 c.slli zero,0x1c - 31e: b705 j 23e <_start-0x7ffffdc2> - 320: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 324: 0400 addi s0,sp,512 - 326: 5f0e lw t5,224(sp) - 328: b8050077 0xb8050077 - 32c: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 330: 0800 addi s0,sp,16 - 332: 0001f00b 0x1f00b - 336: 0500 addi s0,sp,640 - 338: 09b9 addi s3,s3,14 - 33a: 0056 c.slli zero,0x15 - 33c: 0000 unimp - 33e: 0b0c addi a1,sp,400 - 340: 02e4 addi s1,sp,332 - 342: 0000 unimp - 344: ba05 j fffffc74 <__BSS_END__+0x7ffe8efc> - 346: 5609 li a2,-30 - 348: 0000 unimp - 34a: 0e00 addi s0,sp,784 - 34c: 5f0e lw t5,224(sp) - 34e: 6662 flw fa2,24(sp) - 350: 0500 addi s0,sp,640 - 352: 02d311bb 0x2d311bb - 356: 0000 unimp - 358: 0b10 addi a2,sp,400 - 35a: 0085 addi ra,ra,1 - 35c: 0000 unimp - 35e: bc05 j fffffd8e <__BSS_END__+0x7ffe9016> - 360: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 364: 1800 addi s0,sp,48 - 366: 0001e00b 0x1e00b - 36a: 0500 addi s0,sp,640 - 36c: 011d0ac3 fmadd.s fs5,fs10,fa7,ft0,rne - 370: 0000 unimp - 372: 0b1c addi a5,sp,400 - 374: 000004f3 0x4f3 - 378: c505 beqz a0,3a0 <_start-0x7ffffc60> - 37a: c81d beqz s0,3b0 <_start-0x7ffffc50> - 37c: 0005 c.nop 1 - 37e: 2000 fld fs0,0(s0) - 380: 0004240b 0x4240b - 384: 0500 addi s0,sp,640 - 386: 05f71dc7 0x5f71dc7 - 38a: 0000 unimp - 38c: 0b24 addi s1,sp,408 - 38e: 05f4 addi a3,sp,716 - 390: 0000 unimp - 392: ca05 beqz a2,3c2 <_start-0x7ffffc3e> - 394: 1b0d addi s6,s6,-29 - 396: 0006 c.slli zero,0x1 - 398: 2800 fld fs0,16(s0) - 39a: 0000de0b 0xde0b - 39e: 0500 addi s0,sp,640 - 3a0: 063509cb fnmsub.q fs3,fa0,ft3,ft0,rne - 3a4: 0000 unimp - 3a6: 0e2c addi a1,sp,792 - 3a8: 755f 0062 ce05 0xce050062755f - 3ae: d311 beqz a4,2b2 <_start-0x7ffffd4e> - 3b0: 0002 c.slli64 zero - 3b2: 3000 fld fs0,32(s0) - 3b4: 5f0e lw t5,224(sp) - 3b6: 7075 c.lui zero,0xffffd - 3b8: 0500 addi s0,sp,640 - 3ba: 02fb12cf fnmadd.d ft5,fs6,fa5,ft0,rtz - 3be: 0000 unimp - 3c0: 0e38 addi a4,sp,792 - 3c2: 755f 0072 d005 0xd0050072755f - 3c8: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 3cc: 3c00 fld fs0,56(s0) - 3ce: 0001a90b 0x1a90b - 3d2: 0500 addi s0,sp,640 - 3d4: 063b11d3 fadd.q ft3,fs6,ft3,rtz - 3d8: 0000 unimp - 3da: 0b40 addi s0,sp,404 - 3dc: 06fd addi a3,a3,31 - 3de: 0000 unimp - 3e0: d405 beqz s0,308 <_start-0x7ffffcf8> - 3e2: 4b11 li s6,4 - 3e4: 0006 c.slli zero,0x1 - 3e6: 4300 lw s0,0(a4) - 3e8: 5f0e lw t5,224(sp) - 3ea: 626c flw fa1,68(a2) - 3ec: 0500 addi s0,sp,640 - 3ee: 02d311d7 vfadd.vv v3,v13,v6 - 3f2: 0000 unimp - 3f4: 0b44 addi s1,sp,404 - 3f6: 0602 c.slli64 a2 - 3f8: 0000 unimp - 3fa: da05 beqz a2,32a <_start-0x7ffffcd6> - 3fc: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 400: 4c00 lw s0,24(s0) - 402: 0004660b 0x4660b - 406: 0500 addi s0,sp,640 - 408: 007e0adb 0x7e0adb - 40c: 0000 unimp - 40e: 0b50 addi a2,sp,404 - 410: 0055 c.nop 21 - 412: 0000 unimp - 414: de05 beqz a2,34c <_start-0x7ffffcb4> - 416: 6212 flw ft4,4(sp) - 418: 0004 0x4 - 41a: 5400 lw s0,40(s0) - 41c: 0003eb0b 0x3eb0b - 420: 0500 addi s0,sp,640 - 422: 0ce2 slli s9,s9,0x18 - 424: 0111 addi sp,sp,4 - 426: 0000 unimp - 428: 0b58 addi a4,sp,404 - 42a: 02cc addi a1,sp,324 - 42c: 0000 unimp - 42e: e405 bnez s0,456 <_start-0x7ffffbaa> - 430: 050e slli a0,a0,0x3 - 432: 0001 nop - 434: 5c00 lw s0,56(s0) - 436: 00056a0b 0x56a0b - 43a: 0500 addi s0,sp,640 - 43c: 09e5 addi s3,s3,25 - 43e: 00000033 add zero,zero,zero - 442: 0064 addi s1,sp,12 - 444: 00009613 slli a2,ra,0x0 - 448: 6200 flw fs0,0(a2) - 44a: 0004 0x4 - 44c: 1400 addi s0,sp,544 - 44e: 0462 slli s0,s0,0x18 - 450: 0000 unimp - 452: 1d14 addi a3,sp,688 - 454: 0001 nop - 456: 1400 addi s0,sp,544 - 458: 05b6 slli a1,a1,0xd - 45a: 0000 unimp - 45c: 3314 fld fa3,32(a4) - 45e: 0000 unimp - 460: 0000 unimp - 462: 046d040f 0x46d040f - 466: 0000 unimp - 468: 6215 lui tp,0x5 - 46a: 0004 0x4 - 46c: 1600 addi s0,sp,800 - 46e: 05d1 addi a1,a1,20 - 470: 0000 unimp - 472: 0428 addi a0,sp,520 - 474: 6005 c.lui zero,0x1 - 476: 0802 c.slli64 a6 - 478: 05b6 slli a1,a1,0xd - 47a: 0000 unimp - 47c: 00055017 auipc zero,0x55 - 480: 0500 addi s0,sp,640 - 482: 0262 slli tp,tp,0x18 - 484: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 488: 0000 unimp - 48a: 0006ca17 auipc s4,0x6c - 48e: 0500 addi s0,sp,640 - 490: a70b0267 jalr tp,-1424(s6) # 5a70 <_start-0x7fffa590> - 494: 0006 c.slli zero,0x1 - 496: 0400 addi s0,sp,512 - 498: 0006b217 auipc tp,0x6b - 49c: 0500 addi s0,sp,640 - 49e: a7140267 jalr tp,-1423(s0) # ffff9a71 <__BSS_END__+0x7ffe2cf9> - 4a2: 0006 c.slli zero,0x1 - 4a4: 0800 addi s0,sp,16 - 4a6: 00027f17 auipc t5,0x27 - 4aa: 0500 addi s0,sp,640 - 4ac: a71e0267 jalr tp,-1423(t3) # 19a71 <_start-0x7ffe658f> - 4b0: 0006 c.slli zero,0x1 - 4b2: 0c00 addi s0,sp,528 - 4b4: 0005ab17 auipc s6,0x5a - 4b8: 0500 addi s0,sp,640 - 4ba: 0269 addi tp,tp,26 - 4bc: 3308 fld fa0,32(a4) - 4be: 0000 unimp - 4c0: 1000 addi s0,sp,32 - 4c2: 00002417 auipc s0,0x2 - 4c6: 0500 addi s0,sp,640 - 4c8: 026a slli tp,tp,0x1a - 4ca: a708 fsd fa0,8(a4) - 4cc: 0008 0x8 - 4ce: 1400 addi s0,sp,544 - 4d0: 00029f17 auipc t5,0x29 - 4d4: 0500 addi s0,sp,640 - 4d6: 026d addi tp,tp,27 - 4d8: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 4dc: 3000 fld fs0,32(s0) - 4de: 00076b17 auipc s6,0x76 - 4e2: 0500 addi s0,sp,640 - 4e4: 026e slli tp,tp,0x1b - 4e6: bc16 fsd ft5,56(sp) - 4e8: 0008 0x8 - 4ea: 3400 fld fs0,40(s0) - 4ec: 0004a617 auipc a2,0x4a - 4f0: 0500 addi s0,sp,640 - 4f2: 0270 addi a2,sp,268 - 4f4: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 4f8: 3800 fld fs0,48(s0) - 4fa: 0005bf17 auipc t5,0x5b - 4fe: 0500 addi s0,sp,640 - 500: 0272 slli tp,tp,0x1c - 502: cd0a sw sp,152(sp) - 504: 0008 0x8 - 506: 3c00 fld fs0,56(s0) - 508: 0003c317 auipc t1,0x3c - 50c: 0500 addi s0,sp,640 - 50e: 0275 addi tp,tp,29 - 510: 00018513 mv a0,gp - 514: 4000 lw s0,0(s0) - 516: 00020b17 auipc s6,0x20 - 51a: 0500 addi s0,sp,640 - 51c: 0276 slli tp,tp,0x1d - 51e: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 522: 4400 lw s0,8(s0) - 524: 00076617 auipc a2,0x76 - 528: 0500 addi s0,sp,640 - 52a: 85130277 0x85130277 - 52e: 0001 nop - 530: 4800 lw s0,16(s0) - 532: 0004c217 auipc tp,0x4c - 536: 0500 addi s0,sp,640 - 538: 0278 addi a4,sp,268 - 53a: d314 sw a3,32(a4) - 53c: 0008 0x8 - 53e: 4c00 lw s0,24(s0) - 540: 0002dc17 auipc s8,0x2d - 544: 0500 addi s0,sp,640 - 546: 3307027b 0x3307027b - 54a: 0000 unimp - 54c: 5000 lw s0,32(s0) - 54e: 00023817 auipc a6,0x23 - 552: 0500 addi s0,sp,640 - 554: 027c addi a5,sp,268 - 556: b609 j 58 <_start-0x7fffffa8> - 558: 0005 c.nop 1 - 55a: 5400 lw s0,40(s0) - 55c: 00054917 auipc s2,0x54 - 560: 0500 addi s0,sp,640 - 562: 029f 8207 0008 0x88207029f - 568: 5800 lw s0,48(s0) - 56a: 9418 0x9418 - 56c: 0004 0x4 - 56e: 0500 addi s0,sp,640 - 570: b61302a3 sb ra,-1179(t1) # 3c06d <_start-0x7ffc3f93> - 574: 0002 c.slli64 zero - 576: 4800 lw s0,16(s0) - 578: 1801 addi a6,a6,-32 - 57a: 03a1 addi t2,t2,8 - 57c: 0000 unimp - 57e: a405 j 79e <_start-0x7ffff862> - 580: 1202 slli tp,tp,0x20 - 582: 00000273 0x273 - 586: 014c addi a1,sp,132 - 588: e418 fsw fa4,8(s0) - 58a: 0006 c.slli zero,0x1 - 58c: 0500 addi s0,sp,640 - 58e: 02a8 addi a0,sp,328 - 590: e40c fsw fa1,8(s0) - 592: 0008 0x8 - 594: dc00 sw s0,56(s0) - 596: 1802 slli a6,a6,0x20 - 598: 01e8 addi a0,sp,204 - 59a: 0000 unimp - 59c: ad05 j bcc <_start-0x7ffff434> - 59e: 1002 c.slli zero,0x20 - 5a0: 0668 addi a0,sp,780 - 5a2: 0000 unimp - 5a4: 02e0 addi s0,sp,332 - 5a6: cd18 sw a4,24(a0) - 5a8: 0001 nop - 5aa: 0500 addi s0,sp,640 - 5ac: f00a02af 0xf00a02af - 5b0: 0008 0x8 - 5b2: ec00 fsw fs0,24(s0) - 5b4: 0002 c.slli64 zero - 5b6: 05bc040f 0x5bc040f - 5ba: 0000 unimp - 5bc: 0102 c.slli64 sp - 5be: 7008 flw fa0,32(s0) - 5c0: 0006 c.slli zero,0x1 - 5c2: 1500 addi s0,sp,672 - 5c4: 05bc addi a5,sp,712 - 5c6: 0000 unimp - 5c8: 0444040f 0x444040f - 5cc: 0000 unimp - 5ce: 00009613 slli a2,ra,0x0 - 5d2: ec00 fsw fs0,24(s0) - 5d4: 0005 c.nop 1 - 5d6: 1400 addi s0,sp,544 - 5d8: 0462 slli s0,s0,0x18 - 5da: 0000 unimp - 5dc: 1d14 addi a3,sp,688 - 5de: 0001 nop - 5e0: 1400 addi s0,sp,544 - 5e2: 05ec addi a1,sp,716 - 5e4: 0000 unimp - 5e6: 3314 fld fa3,32(a4) - 5e8: 0000 unimp - 5ea: 0000 unimp - 5ec: 05c3040f 0x5c3040f - 5f0: 0000 unimp - 5f2: ec15 bnez s0,62e <_start-0x7ffff9d2> - 5f4: 0005 c.nop 1 - 5f6: 0f00 addi s0,sp,912 - 5f8: ce04 sw s1,24(a2) - 5fa: 0005 c.nop 1 - 5fc: 1300 addi s0,sp,416 - 5fe: 008a slli ra,ra,0x2 - 600: 0000 unimp - 602: 0000061b 0x61b - 606: 6214 flw fa3,0(a2) - 608: 0004 0x4 - 60a: 1400 addi s0,sp,544 - 60c: 011d addi sp,sp,7 - 60e: 0000 unimp - 610: 8a14 0x8a14 - 612: 0000 unimp - 614: 1400 addi s0,sp,544 - 616: 00000033 add zero,zero,zero - 61a: 0f00 addi s0,sp,912 - 61c: fd04 fsw fs1,56(a0) - 61e: 0005 c.nop 1 - 620: 1300 addi s0,sp,416 - 622: 00000033 add zero,zero,zero - 626: 0635 addi a2,a2,13 - 628: 0000 unimp - 62a: 6214 flw fa3,0(a2) - 62c: 0004 0x4 - 62e: 1400 addi s0,sp,544 - 630: 011d addi sp,sp,7 - 632: 0000 unimp - 634: 0f00 addi s0,sp,912 - 636: 2104 fld fs1,0(a0) - 638: 0006 c.slli zero,0x1 - 63a: 0800 addi s0,sp,16 - 63c: 0000004f fnmadd.s ft0,ft0,ft0,ft0,rne - 640: 0000064b fnmsub.s fa2,ft0,ft0,ft0,rne - 644: 2c09 jal 856 <_start-0x7ffff7aa> - 646: 0000 unimp - 648: 0200 addi s0,sp,256 - 64a: 0800 addi s0,sp,16 - 64c: 0000004f fnmadd.s ft0,ft0,ft0,ft0,rne - 650: 0000065b 0x65b - 654: 2c09 jal 866 <_start-0x7ffff79a> - 656: 0000 unimp - 658: 0000 unimp - 65a: 0500 addi s0,sp,640 - 65c: 0204 addi s1,sp,256 - 65e: 0000 unimp - 660: 1f05 addi t5,t5,-31 - 662: 1a01 addi s4,s4,-32 - 664: 0301 addi t1,t1,0 - 666: 0000 unimp - 668: c419 beqz s0,676 <_start-0x7ffff98a> - 66a: 0006 c.slli zero,0x1 - 66c: 0c00 addi s0,sp,528 - 66e: 2305 jal b8e <_start-0x7ffff472> - 670: 0801 addi a6,a6,0 - 672: 06a1 addi a3,a3,8 - 674: 0000 unimp - 676: 00079117 auipc sp,0x79 - 67a: 0500 addi s0,sp,640 - 67c: 0125 addi sp,sp,9 - 67e: a111 j a82 <_start-0x7ffff57e> - 680: 0006 c.slli zero,0x1 - 682: 0000 unimp - 684: 00035d17 auipc s10,0x35 - 688: 0500 addi s0,sp,640 - 68a: 0126 slli sp,sp,0x9 - 68c: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> - 690: 0400 addi s0,sp,512 - 692: 00057217 auipc tp,0x57 - 696: 0500 addi s0,sp,640 - 698: a70b0127 0xa70b0127 - 69c: 0006 c.slli zero,0x1 - 69e: 0800 addi s0,sp,16 - 6a0: 0f00 addi s0,sp,912 - 6a2: 6804 flw fs1,16(s0) - 6a4: 0006 c.slli zero,0x1 - 6a6: 0f00 addi s0,sp,912 - 6a8: 5b04 lw s1,48(a4) - 6aa: 0006 c.slli zero,0x1 - 6ac: 1900 addi s0,sp,176 - 6ae: 001c 0x1c - 6b0: 0000 unimp - 6b2: 050e slli a0,a0,0x3 - 6b4: e608013f 17000006 0x17000006e608013f - 6bc: 062e slli a2,a2,0xb - 6be: 0000 unimp - 6c0: 4005 c.li zero,1 - 6c2: 1201 addi tp,tp,-32 - 6c4: 06e6 slli a3,a3,0x19 - 6c6: 0000 unimp - 6c8: 1700 addi s0,sp,928 - 6ca: 0401 addi s0,s0,0 - 6cc: 0000 unimp - 6ce: 4105 li sp,1 - 6d0: 1201 addi tp,tp,-32 - 6d2: 06e6 slli a3,a3,0x19 - 6d4: 0000 unimp - 6d6: 1706 slli a4,a4,0x21 - 6d8: 0675 addi a2,a2,29 - 6da: 0000 unimp - 6dc: 4205 li tp,1 - 6de: 1201 addi tp,tp,-32 - 6e0: 005d c.nop 23 - 6e2: 0000 unimp - 6e4: 000c 0xc - 6e6: 5d08 lw a0,56(a0) - 6e8: 0000 unimp - 6ea: f600 fsw fs0,40(a2) - 6ec: 0006 c.slli zero,0x1 - 6ee: 0900 addi s0,sp,144 - 6f0: 002c addi a1,sp,8 - 6f2: 0000 unimp - 6f4: 0002 c.slli64 zero - 6f6: d01a sw t1,32(sp) - 6f8: 8005 srli s0,s0,0x1 - 6fa: 0702 c.slli64 a4 - 6fc: 0000080b 0x80b - 700: 00043d17 auipc s10,0x43 - 704: 0500 addi s0,sp,640 - 706: 0282 c.slli64 t0 - 708: 2c18 fld fa4,24(s0) - 70a: 0000 unimp - 70c: 0000 unimp - 70e: 00064a17 auipc s4,0x64 - 712: 0500 addi s0,sp,640 - 714: b6120283 lb t0,-1183(tp) # 571f3 <_start-0x7ffa8e0d> - 718: 0005 c.nop 1 - 71a: 0400 addi s0,sp,512 - 71c: 0003b617 auipc a2,0x3b - 720: 0500 addi s0,sp,640 - 722: 0284 addi s1,sp,320 - 724: 0b10 addi a2,sp,400 - 726: 0008 0x8 - 728: 0800 addi s0,sp,16 - 72a: 00072017 auipc zero,0x72 - 72e: 0500 addi s0,sp,640 - 730: 0285 addi t0,t0,1 - 732: 00019b17 auipc s6,0x19 - 736: 2400 fld fs0,8(s0) - 738: 00028717 auipc a4,0x28 - 73c: 0500 addi s0,sp,640 - 73e: 0286 slli t0,t0,0x1 - 740: 0000330f 0x330f - 744: 4800 lw s0,16(s0) - 746: 00078c17 auipc s8,0x78 - 74a: 0500 addi s0,sp,640 - 74c: 252c0287 0x252c0287 - 750: 0000 unimp - 752: 5000 lw s0,32(s0) - 754: 00073817 auipc a6,0x73 - 758: 0500 addi s0,sp,640 - 75a: 0288 addi a0,sp,320 - 75c: ad1a fsd ft6,152(sp) - 75e: 0006 c.slli zero,0x1 - 760: 5800 lw s0,48(s0) - 762: 00059e17 auipc t3,0x59 - 766: 0500 addi s0,sp,640 - 768: 0289 addi t0,t0,2 - 76a: 0516 slli a0,a0,0x5 - 76c: 0001 nop - 76e: 6800 flw fs0,16(s0) - 770: 00075817 auipc a6,0x75 - 774: 0500 addi s0,sp,640 - 776: 028a slli t0,t0,0x2 - 778: 0516 slli a0,a0,0x5 - 77a: 0001 nop - 77c: 7000 flw fs0,32(s0) - 77e: 0001bf17 auipc t5,0x1b - 782: 0500 addi s0,sp,640 - 784: 0516028b 0x516028b - 788: 0001 nop - 78a: 7800 flw fs0,48(s0) - 78c: 0006da17 auipc s4,0x6d - 790: 0500 addi s0,sp,640 - 792: 028c addi a1,sp,320 - 794: 1b10 addi a2,sp,432 - 796: 0008 0x8 - 798: 8000 0x8000 - 79a: 0003aa17 auipc s4,0x3a - 79e: 0500 addi s0,sp,640 - 7a0: 028d addi t0,t0,3 - 7a2: 2b10 fld fa2,16(a4) - 7a4: 0008 0x8 - 7a6: 8800 0x8800 - 7a8: 00004817 auipc a6,0x4 - 7ac: 0500 addi s0,sp,640 - 7ae: 028e slli t0,t0,0x3 - 7b0: 0000330f 0x330f - 7b4: a000 fsd fs0,0(s0) - 7b6: 00025117 auipc sp,0x25 - 7ba: 0500 addi s0,sp,640 - 7bc: 0516028f 0x516028f - 7c0: 0001 nop - 7c2: a400 fsd fs0,8(s0) - 7c4: 0000be17 auipc t3,0xb - 7c8: 0500 addi s0,sp,640 - 7ca: 0290 addi a2,sp,320 - 7cc: 0516 slli a0,a0,0x5 - 7ce: 0001 nop - 7d0: ac00 fsd fs0,24(s0) - 7d2: 00024017 auipc zero,0x24 - 7d6: 0500 addi s0,sp,640 - 7d8: 0291 addi t0,t0,4 - 7da: 0516 slli a0,a0,0x5 - 7dc: 0001 nop - 7de: b400 fsd fs0,40(s0) - 7e0: 00005b17 auipc s6,0x5 - 7e4: 0500 addi s0,sp,640 - 7e6: 0292 slli t0,t0,0x4 - 7e8: 0516 slli a0,a0,0x5 - 7ea: 0001 nop - 7ec: bc00 fsd fs0,56(s0) - 7ee: 00006a17 auipc s4,0x6 - 7f2: 0500 addi s0,sp,640 - 7f4: 05160293 addi t0,a2,81 # 3b76d <_start-0x7ffc4893> - 7f8: 0001 nop - 7fa: c400 sw s0,8(s0) - 7fc: 00054e17 auipc t3,0x54 - 800: 0500 addi s0,sp,640 - 802: 0294 addi a3,sp,320 - 804: 3308 fld fa0,32(a4) - 806: 0000 unimp - 808: cc00 sw s0,24(s0) - 80a: 0800 addi s0,sp,16 - 80c: 05bc addi a5,sp,712 - 80e: 0000 unimp - 810: 0000081b 0x81b - 814: 2c09 jal a26 <_start-0x7ffff5da> - 816: 0000 unimp - 818: 1900 addi s0,sp,176 - 81a: 0800 addi s0,sp,16 - 81c: 05bc addi a5,sp,712 - 81e: 0000 unimp - 820: 0000082b 0x82b - 824: 2c09 jal a36 <_start-0x7ffff5ca> - 826: 0000 unimp - 828: 0700 addi s0,sp,896 - 82a: 0800 addi s0,sp,16 - 82c: 05bc addi a5,sp,712 - 82e: 0000 unimp - 830: 0000083b 0x83b - 834: 2c09 jal a46 <_start-0x7ffff5ba> - 836: 0000 unimp - 838: 1700 addi s0,sp,928 - 83a: 1a00 addi s0,sp,304 - 83c: 05f0 addi a2,sp,716 - 83e: 0299 addi t0,t0,6 - 840: 00086207 vlwu.v v4,(a6),v0.t - 844: 1700 addi s0,sp,928 - 846: 0476 slli s0,s0,0x1d - 848: 0000 unimp - 84a: 9c05 0x9c05 - 84c: 1b02 slli s6,s6,0x20 - 84e: 0862 slli a6,a6,0x18 - 850: 0000 unimp - 852: 1700 addi s0,sp,928 - 854: 0296 slli t0,t0,0x5 - 856: 0000 unimp - 858: 9d05 0x9d05 - 85a: 1802 slli a6,a6,0x20 - 85c: 0872 slli a6,a6,0x1c - 85e: 0000 unimp - 860: 0078 addi a4,sp,12 - 862: fb08 fsw fa0,48(a4) - 864: 0002 c.slli64 zero - 866: 7200 flw fs0,32(a2) - 868: 0008 0x8 - 86a: 0900 addi s0,sp,144 - 86c: 002c addi a1,sp,8 - 86e: 0000 unimp - 870: 001d c.nop 7 - 872: 2c08 fld fa0,24(s0) - 874: 0000 unimp - 876: 8200 0x8200 - 878: 0008 0x8 - 87a: 0900 addi s0,sp,144 - 87c: 002c addi a1,sp,8 - 87e: 0000 unimp - 880: 001d c.nop 7 - 882: 7e05f01b 0x7e05f01b - 886: 0302 c.slli64 t1 - 888: 000008a7 vsb.v v17,(zero),v0.t - 88c: d11c sw a5,32(a0) - 88e: 0005 c.nop 1 - 890: 0500 addi s0,sp,640 - 892: 0295 addi t0,t0,5 - 894: 0006f60b 0x6f60b - 898: 1c00 addi s0,sp,560 - 89a: 00000703 lb a4,0(zero) # 0 <_start-0x80000000> - 89e: 9e05 0x9e05 - 8a0: 0b02 c.slli64 s6 - 8a2: 0000083b 0x83b - 8a6: 0800 addi s0,sp,16 - 8a8: 05bc addi a5,sp,712 - 8aa: 0000 unimp - 8ac: 000008b7 lui a7,0x0 - 8b0: 2c09 jal ac2 <_start-0x7ffff53e> - 8b2: 0000 unimp - 8b4: 1800 addi s0,sp,48 - 8b6: 1d00 addi s0,sp,688 - 8b8: 000000b3 add ra,zero,zero - 8bc: 08b7040f 0x8b7040f - 8c0: 0000 unimp - 8c2: cd1e sw t2,152(sp) - 8c4: 0008 0x8 - 8c6: 1400 addi s0,sp,544 - 8c8: 0462 slli s0,s0,0x18 - 8ca: 0000 unimp - 8cc: 0f00 addi s0,sp,912 - 8ce: c204 sw s1,0(a2) - 8d0: 0008 0x8 - 8d2: 0f00 addi s0,sp,912 - 8d4: 8504 0x8504 - 8d6: 0001 nop - 8d8: 1e00 addi s0,sp,816 - 8da: 08e4 addi s1,sp,92 - 8dc: 0000 unimp - 8de: 3314 fld fa3,32(a4) - 8e0: 0000 unimp - 8e2: 0000 unimp - 8e4: 08ea040f 0x8ea040f - 8e8: 0000 unimp - 8ea: 08d9040f 0x8d9040f - 8ee: 0000 unimp - 8f0: 5b08 lw a0,48(a4) - 8f2: 0006 c.slli zero,0x1 - 8f4: 0000 unimp - 8f6: 0009 c.nop 2 - 8f8: 0900 addi s0,sp,144 - 8fa: 002c addi a1,sp,8 - 8fc: 0000 unimp - 8fe: 0002 c.slli64 zero - 900: 9e1f 0006 0500 0x50000069e1f - 906: 032e slli t1,t1,0xb - 908: 00046217 auipc tp,0x46 - 90c: 1f00 addi s0,sp,944 - 90e: 00000697 auipc a3,0x0 - 912: 2f05 jal 1042 <_start-0x7fffefbe> - 914: 04681d03 lh s10,70(a6) # 47ee <_start-0x7fffb812> - 918: 0000 unimp - 91a: f208 fsw fa0,32(a2) - 91c: 0005 c.nop 1 - 91e: 2500 fld fs0,8(a0) - 920: 0009 c.nop 2 - 922: 2000 fld fs0,0(s0) - 924: 1500 addi s0,sp,672 - 926: 091a slli s2,s2,0x6 - 928: 0000 unimp - 92a: 2b21 jal e42 <_start-0x7ffff1be> - 92c: 0002 c.slli64 zero - 92e: 0600 addi s0,sp,768 - 930: 2414 fld fa3,8(s0) - 932: 0925 addi s2,s2,9 - 934: 0000 unimp - 936: 9421 srai s0,s0,0x28 - 938: 0005 c.nop 1 - 93a: 0600 addi s0,sp,768 - 93c: 1515 addi a0,a0,-27 - 93e: 00000033 add zero,zero,zero - 942: 0948040f 0x948040f - 946: 0000 unimp - 948: 00003313 sltiu t1,zero,0 - 94c: 5c00 lw s0,56(s0) - 94e: 0009 c.nop 2 - 950: 1400 addi s0,sp,544 - 952: 095c addi a5,sp,148 - 954: 0000 unimp - 956: 5c14 lw a3,56(s0) - 958: 0009 c.nop 2 - 95a: 0000 unimp - 95c: 0962040f 0x962040f - 960: 0000 unimp - 962: 2122 fld ft2,8(sp) - 964: 049c addi a5,sp,576 - 966: 0000 unimp - 968: b60e6707 0xb60e6707 - 96c: 0005 c.nop 1 - 96e: 2100 fld fs0,0(a0) - 970: 03dc addi a5,sp,452 - 972: 0000 unimp - 974: 1008 addi a0,sp,32 - 976: 00097b0f 0x97b0f - 97a: 0f00 addi s0,sp,912 - 97c: b604 fsd fs1,40(a2) - 97e: 0005 c.nop 1 - 980: 2100 fld fs0,0(a0) - 982: 049f 0000 fc08 0xfc080000049f - 988: b60e fsd ft3,296(sp) - 98a: 0005 c.nop 1 - 98c: 2100 fld fs0,0(a0) - 98e: 008e slli ra,ra,0x3 - 990: 0000 unimp - 992: fd08 fsw fa0,56(a0) - 994: 330c fld fa1,32(a4) - 996: 0000 unimp - 998: 2100 fld fs0,0(a0) - 99a: 0634 addi a3,sp,776 - 99c: 0000 unimp - 99e: fd08 fsw fa0,56(a0) - 9a0: 3314 fld fa3,32(a4) - 9a2: 0000 unimp - 9a4: 2100 fld fs0,0(a0) - 9a6: 00000747 fmsub.s fa4,ft0,ft0,ft0,rne - 9aa: fd08 fsw fa0,56(a0) - 9ac: 331c fld fa5,32(a4) - 9ae: 0000 unimp - 9b0: 2100 fld fs0,0(a0) - 9b2: 0000041b 0x41b - 9b6: ff08 fsw fa0,56(a4) - 9b8: 330c fld fa1,32(a4) - 9ba: 0000 unimp - 9bc: 2100 fld fs0,0(a0) - 9be: 04cc addi a1,sp,580 - 9c0: 0000 unimp - 9c2: 9a09 andi a2,a2,-30 - 9c4: 6416 flw fs0,68(sp) - 9c6: 0000 unimp - 9c8: 2100 fld fs0,0(a0) - 9ca: 0000002f 0x2f - 9ce: 9b09 andi a4,a4,-30 - 9d0: 3315 jal 6f4 <_start-0x7ffff90c> - 9d2: 0000 unimp - 9d4: 0800 addi s0,sp,16 - 9d6: 05b6 slli a1,a1,0xd - 9d8: 0000 unimp - 9da: 09e5 addi s3,s3,25 - 9dc: 0000 unimp - 9de: 2c09 jal bf0 <_start-0x7ffff410> - 9e0: 0000 unimp - 9e2: 0100 addi s0,sp,128 - 9e4: 2100 fld fs0,0(a0) - 9e6: 00cd addi ra,ra,19 - 9e8: 0000 unimp - 9ea: 9e09 0x9e09 - 9ec: 0009d517 auipc a0,0x9d - 9f0: 0400 addi s0,sp,512 - 9f2: 02ea slli t0,t0,0x1a - 9f4: 0000 unimp - 9f6: 2a0a fld fs4,128(sp) - 9f8: 2c16 fld fs8,320(sp) - 9fa: 0000 unimp - 9fc: 0400 addi s0,sp,512 - 9fe: 0582 c.slli64 a1 - a00: 0000 unimp - a02: 2f0a fld ft10,128(sp) - a04: 0915 addi s2,s2,5 - a06: 000a c.slli zero,0x2 - a08: 0f00 addi s0,sp,912 - a0a: 0f04 addi s1,sp,912 - a0c: 000a c.slli zero,0x2 - a0e: 1300 addi s0,sp,416 - a10: 09f1 addi s3,s3,28 - a12: 0000 unimp - a14: 0a1e slli s4,s4,0x7 - a16: 0000 unimp - a18: 5c14 lw a3,56(s0) - a1a: 0009 c.nop 2 - a1c: 0000 unimp - a1e: 9704 0x9704 - a20: 0a000007 vlsbu.v v0,(zero),zero - a24: 0f36 slli t5,t5,0xd - a26: 0942 slli s2,s2,0x10 - a28: 0000 unimp - a2a: 0a21 addi s4,s4,8 - a2c: 0000 unimp - a2e: 0a00 addi s0,sp,272 - a30: 09fd12bb 0x9fd12bb - a34: 0000 unimp - a36: 8221 srli a2,a2,0x8 - a38: 0006 c.slli zero,0x1 - a3a: 0a00 addi s0,sp,272 - a3c: 10be slli ra,ra,0x2f - a3e: 0a1e slli s4,s4,0x7 - a40: 0000 unimp - a42: 0002bd23 0x2bd23 - a46: 0700 addi s0,sp,896 - a48: 2c04 fld fs1,24(s0) - a4a: 0000 unimp - a4c: 0b00 addi s0,sp,400 - a4e: 0618 addi a4,sp,768 - a50: 0a7f 0xa7f - a52: 0000 unimp - a54: 2924 fld fs1,80(a0) - a56: 0005 c.nop 1 - a58: 0000 unimp - a5a: f624 fsw fs1,104(a2) - a5c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - a60: d124 sw s1,96(a0) - a62: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - a66: 4a24 lw s1,80(a2) - a68: 0004 0x4 - a6a: 0300 addi s0,sp,384 - a6c: 2024 fld fs1,64(s0) - a6e: 0005 c.nop 1 - a70: 0400 addi s0,sp,512 - a72: 4e24 lw s1,88(a2) - a74: 05000007 0x5000007 - a78: 3d24 fld fs1,120(a0) - a7a: 06000007 0x6000007 - a7e: 2100 fld fs0,0(a0) - a80: 00a9 addi ra,ra,10 - a82: 0000 unimp - a84: 421c210b 0x421c210b - a88: 000a c.slli zero,0x2 - a8a: 2300 fld fs0,0(a4) - a8c: 0455 addi s0,s0,21 - a8e: 0000 unimp - a90: 002c0407 0x2c0407 - a94: 0000 unimp - a96: b006230b 0xb006230b - a9a: 000a c.slli zero,0x2 - a9c: 2400 fld fs0,8(s0) - a9e: 0578 addi a4,sp,652 - aa0: 0000 unimp - aa2: 2400 fld fs0,8(s0) - aa4: 0000053f 06572401 0x65724010000053f - aac: 0000 unimp - aae: 0002 c.slli64 zero - ab0: 5f21 li t5,-24 - ab2: 0002 c.slli64 zero - ab4: 0b00 addi s0,sp,400 - ab6: 1e28 addi a0,sp,824 - ab8: 00000a8b 0xa8b - abc: 0c21 addi s8,s8,8 - abe: 0004 0x4 - ac0: 0c00 addi s0,sp,528 - ac2: 1a29 addi s4,s4,-22 - ac4: 0925 addi s2,s2,9 - ac6: 0000 unimp - ac8: 1e21 addi t3,t3,-24 - aca: 0006 c.slli zero,0x1 - acc: 0c00 addi s0,sp,528 - ace: 1a38 addi a4,sp,312 - ad0: 0925 addi s2,s2,9 - ad2: 0000 unimp - ad4: 7304 flw fs1,32(a4) - ad6: 0d000007 vlxbu.v v0,(zero),v16,v0.t - ada: 004f167b 0x4f167b - ade: 0000 unimp - ae0: d415 beqz s0,a0c <_start-0x7ffff5f4> - ae2: 000a c.slli zero,0x2 - ae4: 0400 addi s0,sp,512 - ae6: 0216 slli tp,tp,0x5 - ae8: 0000 unimp - aea: 800d srli s0,s0,0x3 - aec: 0000330f 0x330f - af0: 0400 addi s0,sp,512 - af2: 0215 addi tp,tp,5 - af4: 0000 unimp - af6: 810d srli a0,a0,0x3 - af8: 2c16 fld fs8,320(sp) - afa: 0000 unimp - afc: 0400 addi s0,sp,512 - afe: 000006ab 0x6ab - b02: 840d srai s0,s0,0x3 - b04: 00003a0f 0x3a0f - b08: 0400 addi s0,sp,512 - b0a: 06aa slli a3,a3,0xa - b0c: 0000 unimp - b0e: 850d srai a0,a0,0x3 - b10: 2516 fld fa0,320(sp) - b12: 0000 unimp - b14: 0200 addi s0,sp,256 - b16: 0404 addi s1,sp,512 - b18: 0485 addi s1,s1,1 - b1a: 0000 unimp - b1c: 0802 c.slli64 a6 - b1e: 00047d03 0x47d03 - b22: 0200 addi s0,sp,256 - b24: 0408 addi a0,sp,512 - b26: 00a2 slli ra,ra,0x8 - b28: 0000 unimp - b2a: 1002 c.slli zero,0x20 - b2c: 00003903 0x3903 - b30: 0200 addi s0,sp,256 - b32: 0320 addi s0,sp,392 - b34: 0095 addi ra,ra,5 - b36: 0000 unimp - b38: 7b19 lui s6,0xfffe6 - b3a: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - b3e: ed0d bnez a0,b78 <_start-0x7ffff488> - b40: 0a01 addi s4,s4,0 - b42: 00000b63 beqz zero,b58 <_start-0x7ffff4a8> - b46: 6c25 lui s8,0x9 - b48: 0d00776f jal a4,7c18 <_start-0x7fff83e8> - b4c: 01ed addi gp,gp,27 - b4e: e51a fsw ft6,136(sp) - b50: 000a c.slli zero,0x2 - b52: 0000 unimp - b54: 00063b17 auipc s6,0x63 - b58: 0d00 addi s0,sp,656 - b5a: 01ed addi gp,gp,27 - b5c: e51f 000a 0400 0x400000ae51f - b62: 1b00 addi s0,sp,432 - b64: 0d08 addi a0,sp,656 - b66: 01f4 addi a3,sp,204 - b68: 8509 srai a0,a0,0x2 - b6a: 2600000b 0x2600000b - b6e: f60d0073 0xf60d0073 - b72: 1301 addi t1,t1,-32 - b74: 0b38 addi a4,sp,408 - b76: 0000 unimp - b78: 6c26 flw fs8,72(sp) - b7a: 006c addi a1,sp,12 - b7c: f70d bnez a4,aa6 <_start-0x7ffff55a> - b7e: 0a01 addi s4,s4,0 - b80: 0afd addi s5,s5,31 - b82: 0000 unimp - b84: 0500 addi s0,sp,640 - b86: 02f4 addi a3,sp,332 - b88: 0000 unimp - b8a: f80d bnez s0,abc <_start-0x7ffff544> - b8c: 0301 addi t1,t1,0 - b8e: 00000b63 beqz zero,ba4 <_start-0x7ffff45c> - b92: 8515 srai a0,a0,0x5 - b94: 0800000b 0x800000b - b98: 0ae0 addi s0,sp,348 - b9a: 0000 unimp - b9c: 00000ba7 vsb.v v23,(zero),v0.t - ba0: 2c09 jal db2 <_start-0x7ffff24e> - ba2: 0000 unimp - ba4: ff00 fsw fs0,56(a4) - ba6: 1500 addi s0,sp,672 - ba8: 00000b97 auipc s7,0x0 - bac: ee1f 0006 0d00 0xd000006ee1f - bb2: 01fc addi a5,sp,204 - bb4: a716 fsd ft5,392(sp) - bb6: 1f00000b 0x1f00000b - bba: 00000397 auipc t2,0x0 - bbe: 020d addi tp,tp,3 - bc0: 1602 slli a2,a2,0x20 - bc2: 00000ba7 vsb.v v23,(zero),v0.t - bc6: 0005b527 fsd ft0,10(a1) - bca: 0100 addi s0,sp,128 - bcc: 0526 slli a0,a0,0x9 - bce: 0901 addi s2,s2,0 - bd0: a400000b 0xa400000b - bd4: 00ff 0xff - bd6: 3480 fld fs0,40(s1) - bd8: 0004 0x4 - bda: 0100 addi s0,sp,128 - bdc: a29c fsd fa5,0(a3) - bde: 000e c.slli zero,0x3 - be0: 2800 fld fs0,16(s0) - be2: 006e c.slli zero,0x1b - be4: 2601 jal ee4 <_start-0x7ffff11c> - be6: 1405 addi s0,s0,-31 - be8: 0b09 addi s6,s6,2 - bea: 0000 unimp - bec: 0000 unimp - bee: 0000 unimp - bf0: 6428 flw fa0,72(s0) - bf2: 0100 addi s0,sp,128 - bf4: 0526 slli a0,a0,0x9 - bf6: 091f 000b b800 0xb800000b091f - bfc: 0000 unimp - bfe: 2900 fld fs0,16(a0) - c00: 0ea2 slli t4,t4,0x8 - c02: 0000 unimp - c04: ffa4 fsw fs1,120(a5) - c06: 8000 0x8000 - c08: 0000 unimp - c0a: 0000 unimp - c0c: 2801 jal c1c <_start-0x7ffff3e4> - c0e: 0a05 addi s4,s4,1 - c10: ca2a sw a0,20(sp) - c12: 000e c.slli zero,0x3 - c14: 5000 lw s0,32(s0) - c16: 0001 nop - c18: 2a00 fld fs0,16(a2) - c1a: 00000ebf 00000170 0x17000000ebf - c22: b42a fsd fa0,40(sp) - c24: 000e c.slli zero,0x3 - c26: 0800 addi s0,sp,16 - c28: 0002 c.slli64 zero - c2a: 2b00 fld fs0,16(a4) - c2c: 0000 unimp - c2e: 0000 unimp - c30: d62c sw a1,104(a2) - c32: 000e c.slli zero,0x3 - c34: 2c00 fld fs0,24(s0) - c36: 0ee2 slli t4,t4,0x18 - c38: 0000 unimp - c3a: ee2c fsw fa1,88(a2) - c3c: 000e c.slli zero,0x3 - c3e: 2d00 fld fs0,24(a0) - c40: 0efa slli t4,t4,0x1e - c42: 0000 unimp - c44: 02c0 addi s0,sp,324 - c46: 0000 unimp - c48: 062d addi a2,a2,11 - c4a: 5b00000f 0x5b00000f - c4e: 2d000003 lb zero,720(zero) # 2d0 <_start-0x7ffffd30> - c52: 0f12 slli t5,t5,0x4 - c54: 0000 unimp - c56: 03d1 addi t2,t2,20 - c58: 0000 unimp - c5a: 1e2d addi t3,t3,-21 - c5c: 4100000f 0x4100000f - c60: 0004 0x4 - c62: 2d00 fld fs0,24(a0) - c64: 0f2a slli t5,t5,0xa - c66: 0000 unimp - c68: 04ee slli s1,s1,0x1b - c6a: 0000 unimp - c6c: 362d jal 796 <_start-0x7ffff86a> - c6e: 0c00000f fence io,unknown - c72: 0005 c.nop 1 - c74: 2d00 fld fs0,24(a0) - c76: 0f42 slli t5,t5,0x10 - c78: 0000 unimp - c7a: 052a slli a0,a0,0xa - c7c: 0000 unimp - c7e: 4e2d li t3,11 - c80: 5400000f 0x5400000f - c84: 0005 c.nop 1 - c86: 2d00 fld fs0,24(a0) - c88: 0f59 addi t5,t5,22 - c8a: 0000 unimp - c8c: 0572 slli a0,a0,0x1c - c8e: 0000 unimp - c90: 652c flw fa1,72(a0) - c92: 2e00000f 0x2e00000f - c96: 0f71 addi t5,t5,28 - c98: 0000 unimp - c9a: 0028 addi a0,sp,8 - c9c: 0000 unimp - c9e: 0cb5 addi s9,s9,13 - ca0: 0000 unimp - ca2: 762d lui a2,0xfffeb - ca4: b100000f 0xb100000f - ca8: 0005 c.nop 1 - caa: 2d00 fld fs0,24(a0) - cac: 00000f83 lb t6,0(zero) # 0 <_start-0x80000000> - cb0: 05ed addi a1,a1,27 - cb2: 0000 unimp - cb4: 2f00 fld fs0,24(a4) - cb6: 0f91 addi t6,t6,4 - cb8: 0000 unimp - cba: 0008 0x8 - cbc: 8001 c.srli64 s0 - cbe: 0088 addi a0,sp,64 - cc0: 0000 unimp - cc2: 0d06 slli s10,s10,0x1 - cc4: 0000 unimp - cc6: 962d srai a2,a2,0x2b - cc8: 0000000f fence unknown,unknown - ccc: 0006 c.slli zero,0x1 - cce: 2d00 fld fs0,24(a0) - cd0: 00000fa3 sb zero,31(zero) # 1f <_start-0x7fffffe1> - cd4: 0622 slli a2,a2,0x8 - cd6: 0000 unimp - cd8: b02d j 502 <_start-0x7ffffafe> - cda: 3500000f 0x3500000f - cde: 0006 c.slli zero,0x1 - ce0: 2d00 fld fs0,24(a0) - ce2: 0fbd addi t6,t6,15 - ce4: 0000 unimp - ce6: 00000653 fadd.s fa2,ft0,ft0,rne - cea: ca2d beqz a2,d5c <_start-0x7ffff2a4> - cec: 7100000f 0x7100000f - cf0: 0006 c.slli zero,0x1 - cf2: 2d00 fld fs0,24(a0) - cf4: 00000fd7 vadd.vv v31,v0,v0,v0.t - cf8: 069a slli a3,a3,0x6 - cfa: 0000 unimp - cfc: e42d bnez s0,d66 <_start-0x7ffff29a> - cfe: b800000f 0xb800000f - d02: 0006 c.slli zero,0x1 - d04: 0000 unimp - d06: 072e slli a4,a4,0xb - d08: 0011 c.nop 4 - d0a: 4000 lw s0,0(s0) - d0c: 0000 unimp - d0e: c500 sw s0,8(a0) - d10: 000d c.nop 3 - d12: 2d00 fld fs0,24(a0) - d14: 1108 addi a0,sp,160 - d16: 0000 unimp - d18: 06e6 slli a3,a3,0x19 - d1a: 0000 unimp - d1c: 142d addi s0,s0,-21 - d1e: 0011 c.nop 4 - d20: f900 fsw fs0,48(a0) - d22: 0006 c.slli zero,0x1 - d24: 2e00 fld fs0,24(a2) - d26: 1120 addi s0,sp,168 - d28: 0000 unimp - d2a: 0058 addi a4,sp,4 - d2c: 0000 unimp - d2e: 0d72 slli s10,s10,0x1c - d30: 0000 unimp - d32: 252d jal 135c <_start-0x7fffeca4> - d34: 0011 c.nop 4 - d36: 3a00 fld fs0,48(a2) - d38: 2d000007 vlxseg2bu.v v0,(zero),v16,v0.t - d3c: 1132 slli sp,sp,0x2c - d3e: 0000 unimp - d40: 075c addi a5,sp,900 - d42: 0000 unimp - d44: 3f2d jal c7e <_start-0x7ffff382> - d46: 0011 c.nop 4 - d48: 8000 0x8000 - d4a: 2d000007 vlxseg2bu.v v0,(zero),v16,v0.t - d4e: 114c addi a1,sp,164 - d50: 0000 unimp - d52: 079e slli a5,a5,0x7 - d54: 0000 unimp - d56: 592d li s2,-21 - d58: 0011 c.nop 4 - d5a: bc00 fsd fs0,56(s0) - d5c: 2d000007 vlxseg2bu.v v0,(zero),v16,v0.t - d60: 1166 slli sp,sp,0x39 - d62: 0000 unimp - d64: 000007f7 0x7f7 - d68: 732d lui t1,0xfffeb - d6a: 0011 c.nop 4 - d6c: 3400 fld fs0,40(s0) - d6e: 0008 0x8 - d70: 0000 unimp - d72: 8130 0x8130 - d74: 0011 c.nop 4 - d76: 8800 0x8800 - d78: 0000 unimp - d7a: 2d00 fld fs0,24(a0) - d7c: 1186 slli gp,gp,0x21 - d7e: 0000 unimp - d80: 0866 slli a6,a6,0x19 - d82: 0000 unimp - d84: 932d srli a4,a4,0x2b - d86: 0011 c.nop 4 - d88: 7900 flw fs0,48(a0) - d8a: 0008 0x8 - d8c: 2d00 fld fs0,24(a0) - d8e: 11a0 addi s0,sp,232 - d90: 0000 unimp - d92: 08cc addi a1,sp,84 - d94: 0000 unimp - d96: ad2d j 13d0 <_start-0x7fffec30> - d98: 0011 c.nop 4 - d9a: df00 sw s0,56(a4) - d9c: 0008 0x8 - d9e: 2d00 fld fs0,24(a0) - da0: 11ba slli gp,gp,0x2e - da2: 0000 unimp - da4: 08f2 slli a7,a7,0x1c - da6: 0000 unimp - da8: c72d beqz a4,e12 <_start-0x7ffff1ee> - daa: 0011 c.nop 4 - dac: 4500 lw s0,8(a0) - dae: 0009 c.nop 2 - db0: 2d00 fld fs0,24(a0) - db2: 11d4 addi a3,sp,228 - db4: 0000 unimp - db6: 0958 addi a4,sp,148 - db8: 0000 unimp - dba: e12d bnez a0,e1c <_start-0x7ffff1e4> - dbc: 0011 c.nop 4 - dbe: 8900 0x8900 - dc0: 0009 c.nop 2 - dc2: 0000 unimp - dc4: 2e00 fld fs0,24(a2) - dc6: 0ff2 slli t6,t6,0x1c - dc8: 0000 unimp - dca: 00b0 addi a2,sp,72 - dcc: 0000 unimp - dce: 0de5 addi s11,s11,25 - dd0: 0000 unimp - dd2: f72d bnez a4,d3c <_start-0x7ffff2c4> - dd4: 9c00000f 0x9c00000f - dd8: 0009 c.nop 2 - dda: 2d00 fld fs0,24(a0) - ddc: 1004 addi s1,sp,32 - dde: 0000 unimp - de0: 09d8 addi a4,sp,212 - de2: 0000 unimp - de4: 2f00 fld fs0,24(a4) - de6: 00001073 csrw ustatus,zero - dea: 00f0 addi a2,sp,76 - dec: 8001 c.srli64 s0 - dee: 0088 addi a0,sp,64 - df0: 0000 unimp - df2: 0e36 slli t3,t3,0xd - df4: 0000 unimp - df6: 782d lui a6,0xfffeb - df8: 0010 0x10 - dfa: f600 fsw fs0,40(a2) - dfc: 0009 c.nop 2 - dfe: 2d00 fld fs0,24(a0) - e00: 1085 addi ra,ra,-31 - e02: 0000 unimp - e04: 0a09 addi s4,s4,2 - e06: 0000 unimp - e08: 922d srli a2,a2,0x2b - e0a: 0010 0x10 - e0c: 2d00 fld fs0,24(a0) - e0e: 000a c.slli zero,0x2 - e10: 2d00 fld fs0,24(a0) - e12: 109f 0000 0a4b 0xa4b0000109f - e18: 0000 unimp - e1a: ac2d j 1054 <_start-0x7fffefac> - e1c: 0010 0x10 - e1e: 6900 flw fs0,16(a0) - e20: 000a c.slli zero,0x2 - e22: 2d00 fld fs0,24(a0) - e24: 10b9 addi ra,ra,-18 - e26: 0000 unimp - e28: 0a92 slli s5,s5,0x4 - e2a: 0000 unimp - e2c: c62d beqz a2,e96 <_start-0x7ffff16a> - e2e: 0010 0x10 - e30: b000 fsd fs0,32(s0) - e32: 000a c.slli zero,0x2 - e34: 0000 unimp - e36: 122e slli tp,tp,0x2b - e38: 0010 0x10 - e3a: c800 sw s0,16(s0) - e3c: 0000 unimp - e3e: 8300 0x8300 - e40: 000e c.slli zero,0x3 - e42: 2d00 fld fs0,24(a0) - e44: 00001017 auipc zero,0x1 - e48: 0ace slli s5,s5,0x13 - e4a: 0000 unimp - e4c: 242d jal 1076 <_start-0x7fffef8a> - e4e: 0010 0x10 - e50: e100 fsw fs0,0(a0) - e52: 000a c.slli zero,0x2 - e54: 2d00 fld fs0,24(a0) - e56: 1031 c.nop -20 - e58: 0000 unimp - e5a: 0b05 addi s6,s6,1 - e5c: 0000 unimp - e5e: 3e2d jal 998 <_start-0x7ffff668> - e60: 0010 0x10 - e62: 2300 fld fs0,0(a4) - e64: 2d00000b 0x2d00000b - e68: 0000104b fnmsub.s ft0,ft0,ft0,ft0,rtz - e6c: 0b41 addi s6,s6,16 - e6e: 0000 unimp - e70: 582d li a6,-21 - e72: 0010 0x10 - e74: 7500 flw fs0,40(a0) - e76: 2d00000b 0x2d00000b - e7a: 1065 c.nop -7 - e7c: 0000 unimp - e7e: 0b9e slli s7,s7,0x7 - e80: 0000 unimp - e82: 3000 fld fs0,32(s0) - e84: 10d4 addi a3,sp,100 - e86: 0000 unimp - e88: 00e8 addi a0,sp,76 - e8a: 0000 unimp - e8c: d92d beqz a0,dfe <_start-0x7ffff202> - e8e: 0010 0x10 - e90: e000 fsw fs0,0(s0) - e92: 2d00000b 0x2d00000b - e96: 10e6 slli ra,ra,0x39 - e98: 0000 unimp - e9a: 0bfe slli s7,s7,0x1f - e9c: 0000 unimp - e9e: 0000 unimp - ea0: 0000 unimp - ea2: 1131 addi sp,sp,-20 - ea4: 0006 c.slli zero,0x1 - ea6: 0100 addi s0,sp,128 - ea8: 090103f7 0x90103f7 - eac: 0300000b 0x300000b - eb0: 00001213 slli tp,zero,0x0 - eb4: 6e32 flw ft8,12(sp) - eb6: 0100 addi s0,sp,128 - eb8: 091703f7 0x91703f7 - ebc: 3200000b 0x3200000b - ec0: 0064 addi s1,sp,12 - ec2: f701 bnez a4,dca <_start-0x7ffff236> - ec4: 0b092203 lw tp,176(s2) # 5460c <_start-0x7ffab9f4> - ec8: 0000 unimp - eca: 7232 flw ft4,44(sp) - ecc: 0070 addi a2,sp,12 - ece: f701 bnez a4,dd6 <_start-0x7ffff22a> - ed0: 12132e03 lw t3,289(t1) # fffeb121 <__BSS_END__+0x7ffd43a9> - ed4: 0000 unimp - ed6: 006e6e33 or t3,t3,t1 - eda: f901 bnez a0,dea <_start-0x7ffff216> - edc: 0b921103 lh sp,185(tp) # 469c1 <_start-0x7ffb963f> - ee0: 0000 unimp - ee2: 00646433 or s0,s0,t1 - ee6: fa01 bnez a2,df6 <_start-0x7ffff20a> - ee8: 0b921103 lh sp,185(tp) # b9 <_start-0x7fffff47> - eec: 0000 unimp - eee: 00727233 and tp,tp,t2 - ef2: fb01 bnez a4,e02 <_start-0x7ffff1fe> - ef4: 0b850b03 lb s6,184(a0) # 9daa4 <_start-0x7ff6255c> - ef8: 0000 unimp - efa: 00306433 or s0,zero,gp - efe: fc01 bnez s0,e16 <_start-0x7ffff1ea> - f00: 0af10a03 lb s4,175(sp) # 25865 <_start-0x7ffda79b> - f04: 0000 unimp - f06: 00316433 or s0,sp,gp - f0a: fc01 bnez s0,e22 <_start-0x7ffff1de> - f0c: 0af10e03 lb t3,175(sp) - f10: 0000 unimp - f12: 00306e33 or t3,zero,gp - f16: fc01 bnez s0,e2e <_start-0x7ffff1d2> - f18: 0af11203 lh tp,175(sp) - f1c: 0000 unimp - f1e: 00316e33 or t3,sp,gp - f22: fc01 bnez s0,e3a <_start-0x7ffff1c6> - f24: 0af11603 lh a2,175(sp) - f28: 0000 unimp - f2a: 00326e33 or t3,tp,gp - f2e: fc01 bnez s0,e46 <_start-0x7ffff1ba> - f30: 0af11a03 lh s4,175(sp) - f34: 0000 unimp - f36: 00307133 and sp,zero,gp - f3a: fd01 bnez a0,e52 <_start-0x7ffff1ae> - f3c: 0af10a03 lb s4,175(sp) - f40: 0000 unimp - f42: 00317133 and sp,sp,gp - f46: fd01 bnez a0,e5e <_start-0x7ffff1a2> - f48: 0af10e03 lb t3,175(sp) - f4c: 0000 unimp - f4e: 01006233 or tp,zero,a6 - f52: 03fe slli t2,t2,0x1f - f54: f10a fsw ft2,160(sp) - f56: 000a c.slli zero,0x2 - f58: 3300 fld fs0,32(a4) - f5a: 6d62 flw fs10,24(sp) - f5c: 0100 addi s0,sp,128 - f5e: 03fe slli t2,t2,0x1f - f60: f10d bnez a0,e82 <_start-0x7ffff17e> - f62: 000a c.slli zero,0x2 - f64: 3300 fld fs0,32(a4) - f66: 01007777 0x1007777 - f6a: 921104c7 fmsub.d fs1,ft2,ft1,fs2,rne - f6e: 3400000b 0x3400000b - f72: 0f91 addi t6,t6,4 - f74: 0000 unimp - f76: 9235 srli a2,a2,0x2d - f78: 0006 c.slli zero,0x1 - f7a: 0100 addi s0,sp,128 - f7c: 042e slli s0,s0,0xb - f7e: f104 fsw fs1,32(a0) - f80: 000a c.slli zero,0x2 - f82: 3300 fld fs0,32(a4) - f84: 5f5f 0061 2e01 0x2e0100615f5f - f8a: 0404 addi s1,sp,512 - f8c: 0af1 addi s5,s5,28 - f8e: 0000 unimp - f90: 3400 fld fs0,40(s0) - f92: 0ff2 slli t6,t6,0x1c - f94: 0000 unimp - f96: 8035 srli s0,s0,0xd - f98: 0000 unimp - f9a: 0100 addi s0,sp,128 - f9c: 043a slli s0,s0,0xe - f9e: f104 fsw fs1,32(a0) - fa0: 000a c.slli zero,0x2 - fa2: 3500 fld fs0,40(a0) - fa4: 0000007b 0x7b - fa8: 3a01 jal 8b8 <_start-0x7ffff748> - faa: 0404 addi s1,sp,512 - fac: 0af1 addi s5,s5,28 - fae: 0000 unimp - fb0: 4535 li a0,13 - fb2: 0006 c.slli zero,0x1 - fb4: 0100 addi s0,sp,128 - fb6: 043a slli s0,s0,0xe - fb8: f104 fsw fs1,32(a0) - fba: 000a c.slli zero,0x2 - fbc: 3500 fld fs0,40(a0) - fbe: 0640 addi s0,sp,772 - fc0: 0000 unimp - fc2: 3a01 jal 8d2 <_start-0x7ffff72e> - fc4: 0404 addi s1,sp,512 - fc6: 0af1 addi s5,s5,28 - fc8: 0000 unimp - fca: 1035 c.nop -19 - fcc: 01000007 vlbuff.v v0,(zero),v0.t - fd0: 043a slli s0,s0,0xe - fd2: f104 fsw fs1,32(a0) - fd4: 000a c.slli zero,0x2 - fd6: 3500 fld fs0,40(a0) - fd8: 0000070b 0x70b - fdc: 3a01 jal 8ec <_start-0x7ffff714> - fde: 0404 addi s1,sp,512 - fe0: 0af1 addi s5,s5,28 - fe2: 0000 unimp - fe4: 6d5f5f33 0x6d5f5f33 - fe8: 0100 addi s0,sp,128 - fea: 043a slli s0,s0,0xe - fec: f104 fsw fs1,32(a0) - fee: 000a c.slli zero,0x2 - ff0: 0000 unimp - ff2: 1234 addi a3,sp,296 - ff4: 0010 0x10 - ff6: 3500 fld fs0,40(a0) - ff8: 0692 slli a3,a3,0x4 - ffa: 0000 unimp - ffc: 4601 li a2,0 - ffe: 0404 addi s1,sp,512 - 1000: 0af1 addi s5,s5,28 - 1002: 0000 unimp - 1004: 615f5f33 0x615f5f33 - 1008: 0100 addi s0,sp,128 - 100a: 0446 slli s0,s0,0x11 - 100c: f104 fsw fs1,32(a0) - 100e: 000a c.slli zero,0x2 - 1010: 0000 unimp - 1012: 7334 flw fa3,96(a4) - 1014: 0010 0x10 - 1016: 3500 fld fs0,40(a0) - 1018: 0080 addi s0,sp,64 - 101a: 0000 unimp - 101c: 5f01 li t5,-32 - 101e: 0804 addi s1,sp,16 - 1020: 0af1 addi s5,s5,28 - 1022: 0000 unimp - 1024: 7b35 lui s6,0xfffed - 1026: 0000 unimp - 1028: 0100 addi s0,sp,128 - 102a: 045f f108 000a 0xaf108045f - 1030: 3500 fld fs0,40(a0) - 1032: 0645 addi a2,a2,17 - 1034: 0000 unimp - 1036: 5f01 li t5,-32 - 1038: 0804 addi s1,sp,16 - 103a: 0af1 addi s5,s5,28 - 103c: 0000 unimp - 103e: 4035 c.li zero,13 - 1040: 0006 c.slli zero,0x1 - 1042: 0100 addi s0,sp,128 - 1044: 045f f108 000a 0xaf108045f - 104a: 3500 fld fs0,40(a0) - 104c: 0710 addi a2,sp,896 - 104e: 0000 unimp - 1050: 5f01 li t5,-32 - 1052: 0804 addi s1,sp,16 - 1054: 0af1 addi s5,s5,28 - 1056: 0000 unimp - 1058: 0b35 addi s6,s6,13 - 105a: 01000007 vlbuff.v v0,(zero),v0.t - 105e: 045f f108 000a 0xaf108045f - 1064: 3300 fld fs0,32(a4) - 1066: 5f5f 006d 5f01 0x5f01006d5f5f - 106c: 0804 addi s1,sp,16 - 106e: 0af1 addi s5,s5,28 - 1070: 0000 unimp - 1072: 3400 fld fs0,40(s0) - 1074: 10d4 addi a3,sp,100 - 1076: 0000 unimp - 1078: 8035 srli s0,s0,0xd - 107a: 0000 unimp - 107c: 0100 addi s0,sp,128 - 107e: 0464 addi s1,sp,524 - 1080: f104 fsw fs1,32(a0) - 1082: 000a c.slli zero,0x2 - 1084: 3500 fld fs0,40(a0) - 1086: 0000007b 0x7b - 108a: 6401 0x6401 - 108c: 0404 addi s1,sp,512 - 108e: 0af1 addi s5,s5,28 - 1090: 0000 unimp - 1092: 4535 li a0,13 - 1094: 0006 c.slli zero,0x1 - 1096: 0100 addi s0,sp,128 - 1098: 0464 addi s1,sp,524 - 109a: f104 fsw fs1,32(a0) - 109c: 000a c.slli zero,0x2 - 109e: 3500 fld fs0,40(a0) - 10a0: 0640 addi s0,sp,772 - 10a2: 0000 unimp - 10a4: 6401 0x6401 - 10a6: 0404 addi s1,sp,512 - 10a8: 0af1 addi s5,s5,28 - 10aa: 0000 unimp - 10ac: 1035 c.nop -19 - 10ae: 01000007 vlbuff.v v0,(zero),v0.t - 10b2: 0464 addi s1,sp,524 - 10b4: f104 fsw fs1,32(a0) - 10b6: 000a c.slli zero,0x2 - 10b8: 3500 fld fs0,40(a0) - 10ba: 0000070b 0x70b - 10be: 6401 0x6401 - 10c0: 0404 addi s1,sp,512 - 10c2: 0af1 addi s5,s5,28 - 10c4: 0000 unimp - 10c6: 6d5f5f33 0x6d5f5f33 - 10ca: 0100 addi s0,sp,128 - 10cc: 0464 addi s1,sp,524 - 10ce: f104 fsw fs1,32(a0) - 10d0: 000a c.slli zero,0x2 - 10d2: 0000 unimp - 10d4: f434 fsw fa3,104(s0) - 10d6: 0010 0x10 - 10d8: 3500 fld fs0,40(a0) - 10da: 0692 slli a3,a3,0x4 - 10dc: 0000 unimp - 10de: 8701 c.srai64 a4 - 10e0: 0404 addi s1,sp,512 - 10e2: 0af1 addi s5,s5,28 - 10e4: 0000 unimp - 10e6: 615f5f33 0x615f5f33 - 10ea: 0100 addi s0,sp,128 - 10ec: f1040487 vlseg8bff.v v9,(s0),v0.t - 10f0: 000a c.slli zero,0x2 - 10f2: 0000 unimp - 10f4: 0734 addi a3,sp,904 - 10f6: 0011 c.nop 4 - 10f8: 3300 fld fs0,32(a4) - 10fa: 5f5f 0078 9501 0x950100785f5f - 1100: 0504 addi s1,sp,640 - 1102: 0af1 addi s5,s5,28 - 1104: 0000 unimp - 1106: 3600 fld fs0,40(a2) - 1108: 00316d33 or s10,sp,gp - 110c: a501 j 170c <_start-0x7fffe8f4> - 110e: 0f04 addi s1,sp,912 - 1110: 0af1 addi s5,s5,28 - 1112: 0000 unimp - 1114: 00306d33 or s10,zero,gp - 1118: a501 j 1718 <_start-0x7fffe8e8> - 111a: 1304 addi s1,sp,416 - 111c: 0af1 addi s5,s5,28 - 111e: 0000 unimp - 1120: 8134 0x8134 - 1122: 0011 c.nop 4 - 1124: 3500 fld fs0,40(a0) - 1126: 0080 addi s0,sp,64 - 1128: 0000 unimp - 112a: b001 j 92a <_start-0x7ffff6d6> - 112c: 0804 addi s1,sp,16 - 112e: 0af1 addi s5,s5,28 - 1130: 0000 unimp - 1132: 7b35 lui s6,0xfffed - 1134: 0000 unimp - 1136: 0100 addi s0,sp,128 - 1138: 04b0 addi a2,sp,584 - 113a: f108 fsw fa0,32(a0) - 113c: 000a c.slli zero,0x2 - 113e: 3500 fld fs0,40(a0) - 1140: 0645 addi a2,a2,17 - 1142: 0000 unimp - 1144: b001 j 944 <_start-0x7ffff6bc> - 1146: 0804 addi s1,sp,16 - 1148: 0af1 addi s5,s5,28 - 114a: 0000 unimp - 114c: 4035 c.li zero,13 - 114e: 0006 c.slli zero,0x1 - 1150: 0100 addi s0,sp,128 - 1152: 04b0 addi a2,sp,584 - 1154: f108 fsw fa0,32(a0) - 1156: 000a c.slli zero,0x2 - 1158: 3500 fld fs0,40(a0) - 115a: 0710 addi a2,sp,896 - 115c: 0000 unimp - 115e: b001 j 95e <_start-0x7ffff6a2> - 1160: 0804 addi s1,sp,16 - 1162: 0af1 addi s5,s5,28 - 1164: 0000 unimp - 1166: 0b35 addi s6,s6,13 - 1168: 01000007 vlbuff.v v0,(zero),v0.t - 116c: 04b0 addi a2,sp,584 - 116e: f108 fsw fa0,32(a0) - 1170: 000a c.slli zero,0x2 - 1172: 3300 fld fs0,32(a4) - 1174: 5f5f 006d b001 0xb001006d5f5f - 117a: 0804 addi s1,sp,16 - 117c: 0af1 addi s5,s5,28 - 117e: 0000 unimp - 1180: 3400 fld fs0,40(s0) - 1182: 000011ef jal gp,2182 <_start-0x7fffde7e> - 1186: d835 beqz s0,10fa <_start-0x7fffef06> - 1188: 0005 c.nop 1 - 118a: 0100 addi s0,sp,128 - 118c: 04b1 addi s1,s1,12 - 118e: f108 fsw fa0,32(a0) - 1190: 000a c.slli zero,0x2 - 1192: 3500 fld fs0,40(a0) - 1194: 05dd addi a1,a1,23 - 1196: 0000 unimp - 1198: b101 j d98 <_start-0x7ffff268> - 119a: 0804 addi s1,sp,16 - 119c: 0af1 addi s5,s5,28 - 119e: 0000 unimp - 11a0: e235 bnez a2,1204 <_start-0x7fffedfc> - 11a2: 0005 c.nop 1 - 11a4: 0100 addi s0,sp,128 - 11a6: 04b1 addi s1,s1,12 - 11a8: f108 fsw fa0,32(a0) - 11aa: 000a c.slli zero,0x2 - 11ac: 3500 fld fs0,40(a0) - 11ae: 000005e7 jalr a1,zero # 0 <_start-0x80000000> - 11b2: b101 j db2 <_start-0x7ffff24e> - 11b4: 0804 addi s1,sp,16 - 11b6: 0af1 addi s5,s5,28 - 11b8: 0000 unimp - 11ba: 0735 addi a4,a4,13 - 11bc: 0004 0x4 - 11be: 0100 addi s0,sp,128 - 11c0: 04b1 addi s1,s1,12 - 11c2: f108 fsw fa0,32(a0) - 11c4: 000a c.slli zero,0x2 - 11c6: 3500 fld fs0,40(a0) - 11c8: 04bd addi s1,s1,15 - 11ca: 0000 unimp - 11cc: b101 j dcc <_start-0x7ffff234> - 11ce: 0804 addi s1,sp,16 - 11d0: 0af1 addi s5,s5,28 - 11d2: 0000 unimp - 11d4: f135 bnez a0,1138 <_start-0x7fffeec8> - 11d6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 11da: 04b1 addi s1,s1,12 - 11dc: f108 fsw fa0,32(a0) - 11de: 000a c.slli zero,0x2 - 11e0: 3500 fld fs0,40(a0) - 11e2: 04b8 addi a4,sp,584 - 11e4: 0000 unimp - 11e6: b101 j de6 <_start-0x7ffff21a> - 11e8: 0804 addi s1,sp,16 - 11ea: 0af1 addi s5,s5,28 - 11ec: 0000 unimp - 11ee: 3400 fld fs0,40(s0) - 11f0: 1202 slli tp,tp,0x20 - 11f2: 0000 unimp - 11f4: 785f5f33 0x785f5f33 - 11f8: 0100 addi s0,sp,128 - 11fa: 04b6 slli s1,s1,0xd - 11fc: f105 bnez a0,111c <_start-0x7fffeee4> - 11fe: 000a c.slli zero,0x2 - 1200: 0000 unimp - 1202: 3336 fld ft6,360(sp) - 1204: 5f5f 0078 be01 0xbe0100785f5f - 120a: 0504 addi s1,sp,640 - 120c: 0af1 addi s5,s5,28 - 120e: 0000 unimp - 1210: 0000 unimp - 1212: 0f00 addi s0,sp,912 - 1214: 0904 addi s1,sp,144 - 1216: 0000000b 0xb - 121a: 1274 addi a3,sp,300 - 121c: 0000 unimp - 121e: 0004 0x4 - 1220: 02cc addi a1,sp,324 - 1222: 0000 unimp - 1224: 0104 addi s1,sp,128 - 1226: 00e5 addi ra,ra,25 - 1228: 0000 unimp - 122a: f90c fsw fa1,48(a0) - 122c: 0004 0x4 - 122e: fc00 fsw fs0,56(s0) - 1230: 0002 c.slli64 zero - 1232: d800 sw s0,48(s0) - 1234: 10800103 lb sp,264(zero) # 108 <_start-0x7ffffef8> - 1238: 0004 0x4 - 123a: de00 sw s0,56(a2) - 123c: 0008 0x8 - 123e: 0200 addi s0,sp,256 - 1240: 0708 addi a0,sp,896 - 1242: 0364 addi s1,sp,396 - 1244: 0000 unimp - 1246: 69050403 lb s0,1680(a0) - 124a: 746e flw fs0,248(sp) - 124c: 0200 addi s0,sp,256 - 124e: 0704 addi s1,sp,896 - 1250: 036e slli t1,t1,0x1b - 1252: 0000 unimp - 1254: 0802 c.slli64 a6 - 1256: 1d05 addi s10,s10,-31 - 1258: 0002 c.slli64 zero - 125a: 0200 addi s0,sp,256 - 125c: 0410 addi a2,sp,512 - 125e: 009d addi ra,ra,7 - 1260: 0000 unimp - 1262: 0102 c.slli64 sp - 1264: 6906 flw fs2,64(sp) - 1266: 0006 c.slli zero,0x1 - 1268: 0200 addi s0,sp,256 - 126a: 0801 addi a6,a6,0 - 126c: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 1270: 0202 c.slli64 tp - 1272: 0005 c.nop 1 - 1274: 0000 unimp - 1276: 0200 addi s0,sp,256 - 1278: 0702 c.slli64 a4 - 127a: 0384 addi s1,sp,448 - 127c: 0000 unimp - 127e: 0402 c.slli64 s0 - 1280: 2205 jal 13a0 <_start-0x7fffec60> - 1282: 0002 c.slli64 zero - 1284: 0200 addi s0,sp,256 - 1286: 0704 addi s1,sp,896 - 1288: 0369 addi t1,t1,26 - 128a: 0000 unimp - 128c: e104 fsw fs1,0(a0) - 128e: 0004 0x4 - 1290: 0200 addi s0,sp,256 - 1292: 0d0c addi a1,sp,656 - 1294: 002c addi a1,sp,8 - 1296: 0000 unimp - 1298: b104 fsd fs1,32(a0) - 129a: 0004 0x4 - 129c: 0300 addi s0,sp,384 - 129e: 0e2c addi a1,sp,792 - 12a0: 0064 addi s1,sp,12 - 12a2: 0000 unimp - 12a4: fa04 fsw fs1,48(a2) - 12a6: 0005 c.nop 1 - 12a8: 0300 addi s0,sp,384 - 12aa: 0e72 slli t3,t3,0x1c - 12ac: 0064 addi s1,sp,12 - 12ae: 0000 unimp - 12b0: d104 sw s1,32(a0) - 12b2: 0006 c.slli zero,0x1 - 12b4: 0300 addi s0,sp,384 - 12b6: 1791 addi a5,a5,-28 - 12b8: 002c addi a1,sp,8 - 12ba: 0000 unimp - 12bc: e405 bnez s0,12e4 <_start-0x7fffed1c> - 12be: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - 12c2: 0165 addi sp,sp,25 - 12c4: 00003317 auipc t1,0x3 - 12c8: 0600 addi s0,sp,768 - 12ca: 0304 addi s1,sp,384 - 12cc: 03a6 slli t2,t2,0x9 - 12ce: 00d1 addi ra,ra,20 - 12d0: 0000 unimp - 12d2: 0003cb07 flq fs6,0(t2) # bba <_start-0x7ffff446> - 12d6: 0300 addi s0,sp,384 - 12d8: 0ca8 addi a0,sp,600 - 12da: 00a2 slli ra,ra,0x8 - 12dc: 0000 unimp - 12de: 0002d507 vlhu.v v10,(t0),v0.t - 12e2: 0300 addi s0,sp,384 - 12e4: 13a9 addi t2,t2,-22 - 12e6: 00d1 addi ra,ra,20 - 12e8: 0000 unimp - 12ea: 0800 addi s0,sp,16 - 12ec: 0000004f fnmadd.s ft0,ft0,ft0,ft0,rne - 12f0: 00e1 addi ra,ra,24 - 12f2: 0000 unimp - 12f4: 3309 jal ff6 <_start-0x7ffff00a> - 12f6: 0000 unimp - 12f8: 0300 addi s0,sp,384 - 12fa: 0a00 addi s0,sp,272 - 12fc: 0308 addi a0,sp,384 - 12fe: 010509a3 sb a6,19(a0) - 1302: 0000 unimp - 1304: 0004350b 0x4350b - 1308: 0300 addi s0,sp,384 - 130a: 07a5 addi a5,a5,9 - 130c: 002c addi a1,sp,8 - 130e: 0000 unimp - 1310: 0b00 addi s0,sp,400 - 1312: 05ec addi a1,sp,716 - 1314: 0000 unimp - 1316: af05aa03 lw s4,-1296(a1) - 131a: 0000 unimp - 131c: 0400 addi s0,sp,512 - 131e: 0400 addi s0,sp,512 - 1320: 04d6 slli s1,s1,0x15 - 1322: 0000 unimp - 1324: e103ab03 lw s6,-496(t2) - 1328: 0000 unimp - 132a: 0400 addi s0,sp,512 - 132c: 00000557 vadd.vv v10,v0,v0,v0.t - 1330: 721baf03 lw t5,1825(s7) # 12c9 <_start-0x7fffed37> - 1334: 0000 unimp - 1336: 0c00 addi s0,sp,528 - 1338: 0404 addi s1,sp,512 - 133a: 067a slli a2,a2,0x1e - 133c: 0000 unimp - 133e: 1605 addi a2,a2,-31 - 1340: 6b19 lui s6,0x6 - 1342: 0000 unimp - 1344: 0d00 addi s0,sp,656 - 1346: 046e slli s0,s0,0x1b - 1348: 0000 unimp - 134a: 0518 addi a4,sp,640 - 134c: 0185082f 0x185082f - 1350: 0000 unimp - 1352: 0007910b 0x7910b - 1356: 0500 addi s0,sp,640 - 1358: 1331 addi t1,t1,-20 - 135a: 0185 addi gp,gp,1 - 135c: 0000 unimp - 135e: 0e00 addi s0,sp,784 - 1360: 6b5f 0500 0732 0x73205006b5f - 1366: 002c addi a1,sp,8 - 1368: 0000 unimp - 136a: 0b04 addi s1,sp,400 - 136c: 05c9 addi a1,a1,18 - 136e: 0000 unimp - 1370: 3205 jal c90 <_start-0x7ffff370> - 1372: 00002c0b 0x2c0b - 1376: 0800 addi s0,sp,16 - 1378: 0002790b 0x2790b - 137c: 0500 addi s0,sp,640 - 137e: 1432 slli s0,s0,0x2c - 1380: 002c addi a1,sp,8 - 1382: 0000 unimp - 1384: 0b0c addi a1,sp,400 - 1386: 01ff 0x1ff - 1388: 0000 unimp - 138a: 3205 jal caa <_start-0x7ffff356> - 138c: 00002c1b 0x2c1b - 1390: 1000 addi s0,sp,32 - 1392: 5f0e lw t5,224(sp) - 1394: 0078 addi a4,sp,12 - 1396: 3305 jal 10b6 <_start-0x7fffef4a> - 1398: 00018b0b 0x18b0b - 139c: 1400 addi s0,sp,544 - 139e: 0f00 addi s0,sp,912 - 13a0: 2b04 fld fs1,16(a4) - 13a2: 0001 nop - 13a4: 0800 addi s0,sp,16 - 13a6: 011f 0000 019b 0x19b0000011f - 13ac: 0000 unimp - 13ae: 3309 jal 10b0 <_start-0x7fffef50> - 13b0: 0000 unimp - 13b2: 0000 unimp - 13b4: 0d00 addi s0,sp,656 - 13b6: 02b8 addi a4,sp,328 - 13b8: 0000 unimp - 13ba: 0524 addi s1,sp,648 - 13bc: 021e0837 lui a6,0x21e0 - 13c0: 0000 unimp - 13c2: 0000d50b 0xd50b - 13c6: 0500 addi s0,sp,640 - 13c8: 0939 addi s2,s2,14 - 13ca: 002c addi a1,sp,8 - 13cc: 0000 unimp - 13ce: 0b00 addi s0,sp,400 - 13d0: 0000072f 0x72f - 13d4: 3a05 jal d04 <_start-0x7ffff2fc> - 13d6: 2c09 jal 15e8 <_start-0x7fffea18> - 13d8: 0000 unimp - 13da: 0400 addi s0,sp,512 - 13dc: 0001b50b 0x1b50b - 13e0: 0500 addi s0,sp,640 - 13e2: 002c093b 0x2c093b - 13e6: 0000 unimp - 13e8: 0b08 addi a0,sp,400 - 13ea: 0782 c.slli64 a5 - 13ec: 0000 unimp - 13ee: 3c05 jal e1e <_start-0x7ffff1e2> - 13f0: 2c09 jal 1602 <_start-0x7fffe9fe> - 13f2: 0000 unimp - 13f4: 0c00 addi s0,sp,528 - 13f6: 00048b0b 0x48b0b - 13fa: 0500 addi s0,sp,640 - 13fc: 093d addi s2,s2,15 - 13fe: 002c addi a1,sp,8 - 1400: 0000 unimp - 1402: 0b10 addi a2,sp,400 - 1404: 0000042b 0x42b - 1408: 3e05 jal f38 <_start-0x7ffff0c8> - 140a: 2c09 jal 161c <_start-0x7fffe9e4> - 140c: 0000 unimp - 140e: 1400 addi s0,sp,544 - 1410: 0006ba0b 0x6ba0b - 1414: 0500 addi s0,sp,640 - 1416: 002c093f 0b180000 0xb180000002c093f - 141e: 0560 addi s0,sp,652 - 1420: 0000 unimp - 1422: 4005 c.li zero,1 - 1424: 2c09 jal 1636 <_start-0x7fffe9ca> - 1426: 0000 unimp - 1428: 1c00 addi s0,sp,560 - 142a: 0007150b 0x7150b - 142e: 0500 addi s0,sp,640 - 1430: 0941 addi s2,s2,16 - 1432: 002c addi a1,sp,8 - 1434: 0000 unimp - 1436: 0020 addi s0,sp,8 - 1438: d210 sw a2,32(a2) - 143a: 0001 nop - 143c: 0800 addi s0,sp,16 - 143e: 0501 addi a0,a0,0 - 1440: 084a slli a6,a6,0x12 - 1442: 00000263 beqz zero,1446 <_start-0x7fffebba> - 1446: 00026c0b 0x26c0b - 144a: 0500 addi s0,sp,640 - 144c: 02630a4b fnmsub.d fs4,ft6,ft6,ft0,rne - 1450: 0000 unimp - 1452: 0b00 addi s0,sp,400 - 1454: 00000533 add a0,zero,zero - 1458: 4c05 li s8,1 - 145a: 6309 lui t1,0x2 - 145c: 0002 c.slli64 zero - 145e: 8000 0x8000 - 1460: 5e11 li t3,-28 - 1462: 0006 c.slli zero,0x1 - 1464: 0500 addi s0,sp,640 - 1466: 0a4e slli s4,s4,0x13 - 1468: 011f 0000 0100 0x1000000011f - 146e: f711 bnez a4,137a <_start-0x7fffec86> - 1470: 0001 nop - 1472: 0500 addi s0,sp,640 - 1474: 0a51 addi s4,s4,20 - 1476: 011f 0000 0104 0x1040000011f - 147c: 0800 addi s0,sp,16 - 147e: 011d addi sp,sp,7 - 1480: 0000 unimp - 1482: 00000273 0x273 - 1486: 3309 jal 1188 <_start-0x7fffee78> - 1488: 0000 unimp - 148a: 1f00 addi s0,sp,944 - 148c: 1000 addi s0,sp,32 - 148e: 0494 addi a3,sp,576 - 1490: 0000 unimp - 1492: 0190 addi a2,sp,192 - 1494: 5d05 li s10,-31 - 1496: b608 fsd fa0,40(a2) - 1498: 0002 c.slli64 zero - 149a: 0b00 addi s0,sp,400 - 149c: 0791 addi a5,a5,4 - 149e: 0000 unimp - 14a0: 5e05 li t3,-31 - 14a2: b612 fsd ft4,296(sp) - 14a4: 0002 c.slli64 zero - 14a6: 0000 unimp - 14a8: 0005b00b 0x5b00b - 14ac: 0500 addi s0,sp,640 - 14ae: 065f 002c 0000 0x2c065f - 14b4: 0b04 addi s1,sp,400 - 14b6: 0274 addi a3,sp,268 - 14b8: 0000 unimp - 14ba: 6105 addi sp,sp,32 - 14bc: bc09 j ece <_start-0x7ffff132> - 14be: 0002 c.slli64 zero - 14c0: 0800 addi s0,sp,16 - 14c2: 0001d20b 0x1d20b - 14c6: 0500 addi s0,sp,640 - 14c8: 1e62 slli t3,t3,0x38 - 14ca: 021e slli tp,tp,0x7 - 14cc: 0000 unimp - 14ce: 0088 addi a0,sp,64 - 14d0: 0273040f 0x273040f - 14d4: 0000 unimp - 14d6: cc08 sw a0,24(s0) - 14d8: 0002 c.slli64 zero - 14da: cc00 sw s0,24(s0) - 14dc: 0002 c.slli64 zero - 14de: 0900 addi s0,sp,144 - 14e0: 00000033 add zero,zero,zero - 14e4: 001f 040f 02d2 0x2d2040f001f - 14ea: 0000 unimp - 14ec: 0d12 slli s10,s10,0x4 - 14ee: 0000077b 0x77b - 14f2: 0508 addi a0,sp,640 - 14f4: 0875 addi a6,a6,29 - 14f6: 000002fb 0x2fb - 14fa: 0001af0b 0x1af0b - 14fe: 0500 addi s0,sp,640 - 1500: 1176 slli sp,sp,0x3d - 1502: 000002fb 0x2fb - 1506: 0b00 addi s0,sp,400 - 1508: 0000060b 0x60b - 150c: 7705 lui a4,0xfffe1 - 150e: 2c06 fld fs8,64(sp) - 1510: 0000 unimp - 1512: 0400 addi s0,sp,512 - 1514: 0f00 addi s0,sp,912 - 1516: 4f04 lw s1,24(a4) - 1518: 0000 unimp - 151a: 0d00 addi s0,sp,656 - 151c: 058c addi a1,sp,704 - 151e: 0000 unimp - 1520: 0568 addi a0,sp,652 - 1522: 08b5 addi a7,a7,13 - 1524: 0444 addi s1,sp,516 - 1526: 0000 unimp - 1528: 5f0e lw t5,224(sp) - 152a: 0070 addi a2,sp,12 - 152c: b605 j 104c <_start-0x7fffefb4> - 152e: fb12 fsw ft4,180(sp) - 1530: 0002 c.slli64 zero - 1532: 0000 unimp - 1534: 5f0e lw t5,224(sp) - 1536: 0072 c.slli zero,0x1c - 1538: b705 j 1458 <_start-0x7fffeba8> - 153a: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 153e: 0400 addi s0,sp,512 - 1540: 5f0e lw t5,224(sp) - 1542: b8050077 0xb8050077 - 1546: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 154a: 0800 addi s0,sp,16 - 154c: 0001f00b 0x1f00b - 1550: 0500 addi s0,sp,640 - 1552: 09b9 addi s3,s3,14 - 1554: 0056 c.slli zero,0x15 - 1556: 0000 unimp - 1558: 0b0c addi a1,sp,400 - 155a: 02e4 addi s1,sp,332 - 155c: 0000 unimp - 155e: ba05 j e8e <_start-0x7ffff172> - 1560: 5609 li a2,-30 - 1562: 0000 unimp - 1564: 0e00 addi s0,sp,784 - 1566: 5f0e lw t5,224(sp) - 1568: 6662 flw fa2,24(sp) - 156a: 0500 addi s0,sp,640 - 156c: 02d311bb 0x2d311bb - 1570: 0000 unimp - 1572: 0b10 addi a2,sp,400 - 1574: 0085 addi ra,ra,1 - 1576: 0000 unimp - 1578: bc05 j fa8 <_start-0x7ffff058> - 157a: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 157e: 1800 addi s0,sp,48 - 1580: 0001e00b 0x1e00b - 1584: 0500 addi s0,sp,640 - 1586: 011d0ac3 fmadd.s fs5,fs10,fa7,ft0,rne - 158a: 0000 unimp - 158c: 0b1c addi a5,sp,400 - 158e: 000004f3 0x4f3 - 1592: c505 beqz a0,15ba <_start-0x7fffea46> - 1594: c81d beqz s0,15ca <_start-0x7fffea36> - 1596: 0005 c.nop 1 - 1598: 2000 fld fs0,0(s0) - 159a: 0004240b 0x4240b - 159e: 0500 addi s0,sp,640 - 15a0: 05f71dc7 0x5f71dc7 - 15a4: 0000 unimp - 15a6: 0b24 addi s1,sp,408 - 15a8: 05f4 addi a3,sp,716 - 15aa: 0000 unimp - 15ac: ca05 beqz a2,15dc <_start-0x7fffea24> - 15ae: 1b0d addi s6,s6,-29 - 15b0: 0006 c.slli zero,0x1 - 15b2: 2800 fld fs0,16(s0) - 15b4: 0000de0b 0xde0b - 15b8: 0500 addi s0,sp,640 - 15ba: 063509cb fnmsub.q fs3,fa0,ft3,ft0,rne - 15be: 0000 unimp - 15c0: 0e2c addi a1,sp,792 - 15c2: 755f 0062 ce05 0xce050062755f - 15c8: d311 beqz a4,14cc <_start-0x7fffeb34> - 15ca: 0002 c.slli64 zero - 15cc: 3000 fld fs0,32(s0) - 15ce: 5f0e lw t5,224(sp) - 15d0: 7075 c.lui zero,0xffffd - 15d2: 0500 addi s0,sp,640 - 15d4: 02fb12cf fnmadd.d ft5,fs6,fa5,ft0,rtz - 15d8: 0000 unimp - 15da: 0e38 addi a4,sp,792 - 15dc: 755f 0072 d005 0xd0050072755f - 15e2: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 15e6: 3c00 fld fs0,56(s0) - 15e8: 0001a90b 0x1a90b - 15ec: 0500 addi s0,sp,640 - 15ee: 063b11d3 fadd.q ft3,fs6,ft3,rtz - 15f2: 0000 unimp - 15f4: 0b40 addi s0,sp,404 - 15f6: 06fd addi a3,a3,31 - 15f8: 0000 unimp - 15fa: d405 beqz s0,1522 <_start-0x7fffeade> - 15fc: 4b11 li s6,4 - 15fe: 0006 c.slli zero,0x1 - 1600: 4300 lw s0,0(a4) - 1602: 5f0e lw t5,224(sp) - 1604: 626c flw fa1,68(a2) - 1606: 0500 addi s0,sp,640 - 1608: 02d311d7 vfadd.vv v3,v13,v6 - 160c: 0000 unimp - 160e: 0b44 addi s1,sp,404 - 1610: 0602 c.slli64 a2 - 1612: 0000 unimp - 1614: da05 beqz a2,1544 <_start-0x7fffeabc> - 1616: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 161a: 4c00 lw s0,24(s0) - 161c: 0004660b 0x4660b - 1620: 0500 addi s0,sp,640 - 1622: 007e0adb 0x7e0adb - 1626: 0000 unimp - 1628: 0b50 addi a2,sp,404 - 162a: 0055 c.nop 21 - 162c: 0000 unimp - 162e: de05 beqz a2,1566 <_start-0x7fffea9a> - 1630: 6212 flw ft4,4(sp) - 1632: 0004 0x4 - 1634: 5400 lw s0,40(s0) - 1636: 0003eb0b 0x3eb0b - 163a: 0500 addi s0,sp,640 - 163c: 0ce2 slli s9,s9,0x18 - 163e: 0111 addi sp,sp,4 - 1640: 0000 unimp - 1642: 0b58 addi a4,sp,404 - 1644: 02cc addi a1,sp,324 - 1646: 0000 unimp - 1648: e405 bnez s0,1670 <_start-0x7fffe990> - 164a: 050e slli a0,a0,0x3 - 164c: 0001 nop - 164e: 5c00 lw s0,56(s0) - 1650: 00056a0b 0x56a0b - 1654: 0500 addi s0,sp,640 - 1656: 09e5 addi s3,s3,25 - 1658: 002c addi a1,sp,8 - 165a: 0000 unimp - 165c: 0064 addi s1,sp,12 - 165e: 00009613 slli a2,ra,0x0 - 1662: 6200 flw fs0,0(a2) - 1664: 0004 0x4 - 1666: 1400 addi s0,sp,544 - 1668: 0462 slli s0,s0,0x18 - 166a: 0000 unimp - 166c: 1d14 addi a3,sp,688 - 166e: 0001 nop - 1670: 1400 addi s0,sp,544 - 1672: 05b6 slli a1,a1,0xd - 1674: 0000 unimp - 1676: 2c14 fld fa3,24(s0) - 1678: 0000 unimp - 167a: 0000 unimp - 167c: 046d040f 0x46d040f - 1680: 0000 unimp - 1682: 6215 lui tp,0x5 - 1684: 0004 0x4 - 1686: 1600 addi s0,sp,800 - 1688: 05d1 addi a1,a1,20 - 168a: 0000 unimp - 168c: 0428 addi a0,sp,520 - 168e: 6005 c.lui zero,0x1 - 1690: 0802 c.slli64 a6 - 1692: 05b6 slli a1,a1,0xd - 1694: 0000 unimp - 1696: 00055017 auipc zero,0x55 - 169a: 0500 addi s0,sp,640 - 169c: 0262 slli tp,tp,0x18 - 169e: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 16a2: 0000 unimp - 16a4: 0006ca17 auipc s4,0x6c - 16a8: 0500 addi s0,sp,640 - 16aa: a70b0267 jalr tp,-1424(s6) # 5a70 <_start-0x7fffa590> - 16ae: 0006 c.slli zero,0x1 - 16b0: 0400 addi s0,sp,512 - 16b2: 0006b217 auipc tp,0x6b - 16b6: 0500 addi s0,sp,640 - 16b8: a7140267 jalr tp,-1423(s0) # 1f33 <_start-0x7fffe0cd> - 16bc: 0006 c.slli zero,0x1 - 16be: 0800 addi s0,sp,16 - 16c0: 00027f17 auipc t5,0x27 - 16c4: 0500 addi s0,sp,640 - 16c6: a71e0267 jalr tp,-1423(t3) # 5426d <_start-0x7ffabd93> - 16ca: 0006 c.slli zero,0x1 - 16cc: 0c00 addi s0,sp,528 - 16ce: 0005ab17 auipc s6,0x5a - 16d2: 0500 addi s0,sp,640 - 16d4: 0269 addi tp,tp,26 - 16d6: 2c08 fld fa0,24(s0) - 16d8: 0000 unimp - 16da: 1000 addi s0,sp,32 - 16dc: 00002417 auipc s0,0x2 - 16e0: 0500 addi s0,sp,640 - 16e2: 026a slli tp,tp,0x1a - 16e4: a708 fsd fa0,8(a4) - 16e6: 0008 0x8 - 16e8: 1400 addi s0,sp,544 - 16ea: 00029f17 auipc t5,0x29 - 16ee: 0500 addi s0,sp,640 - 16f0: 026d addi tp,tp,27 - 16f2: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 16f6: 3000 fld fs0,32(s0) - 16f8: 00076b17 auipc s6,0x76 - 16fc: 0500 addi s0,sp,640 - 16fe: 026e slli tp,tp,0x1b - 1700: bc16 fsd ft5,56(sp) - 1702: 0008 0x8 - 1704: 3400 fld fs0,40(s0) - 1706: 0004a617 auipc a2,0x4a - 170a: 0500 addi s0,sp,640 - 170c: 0270 addi a2,sp,268 - 170e: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 1712: 3800 fld fs0,48(s0) - 1714: 0005bf17 auipc t5,0x5b - 1718: 0500 addi s0,sp,640 - 171a: 0272 slli tp,tp,0x1c - 171c: cd0a sw sp,152(sp) - 171e: 0008 0x8 - 1720: 3c00 fld fs0,56(s0) - 1722: 0003c317 auipc t1,0x3c - 1726: 0500 addi s0,sp,640 - 1728: 0275 addi tp,tp,29 - 172a: 00018513 mv a0,gp - 172e: 4000 lw s0,0(s0) - 1730: 00020b17 auipc s6,0x20 - 1734: 0500 addi s0,sp,640 - 1736: 0276 slli tp,tp,0x1d - 1738: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 173c: 4400 lw s0,8(s0) - 173e: 00076617 auipc a2,0x76 - 1742: 0500 addi s0,sp,640 - 1744: 85130277 0x85130277 - 1748: 0001 nop - 174a: 4800 lw s0,16(s0) - 174c: 0004c217 auipc tp,0x4c - 1750: 0500 addi s0,sp,640 - 1752: 0278 addi a4,sp,268 - 1754: d314 sw a3,32(a4) - 1756: 0008 0x8 - 1758: 4c00 lw s0,24(s0) - 175a: 0002dc17 auipc s8,0x2d - 175e: 0500 addi s0,sp,640 - 1760: 2c07027b 0x2c07027b - 1764: 0000 unimp - 1766: 5000 lw s0,32(s0) - 1768: 00023817 auipc a6,0x23 - 176c: 0500 addi s0,sp,640 - 176e: 027c addi a5,sp,268 - 1770: b609 j 1272 <_start-0x7fffed8e> - 1772: 0005 c.nop 1 - 1774: 5400 lw s0,40(s0) - 1776: 00054917 auipc s2,0x54 - 177a: 0500 addi s0,sp,640 - 177c: 029f 8207 0008 0x88207029f - 1782: 5800 lw s0,48(s0) - 1784: 9418 0x9418 - 1786: 0004 0x4 - 1788: 0500 addi s0,sp,640 - 178a: b61302a3 sb ra,-1179(t1) # 3d287 <_start-0x7ffc2d79> - 178e: 0002 c.slli64 zero - 1790: 4800 lw s0,16(s0) - 1792: 1801 addi a6,a6,-32 - 1794: 03a1 addi t2,t2,8 - 1796: 0000 unimp - 1798: a405 j 19b8 <_start-0x7fffe648> - 179a: 1202 slli tp,tp,0x20 - 179c: 00000273 0x273 - 17a0: 014c addi a1,sp,132 - 17a2: e418 fsw fa4,8(s0) - 17a4: 0006 c.slli zero,0x1 - 17a6: 0500 addi s0,sp,640 - 17a8: 02a8 addi a0,sp,328 - 17aa: e40c fsw fa1,8(s0) - 17ac: 0008 0x8 - 17ae: dc00 sw s0,56(s0) - 17b0: 1802 slli a6,a6,0x20 - 17b2: 01e8 addi a0,sp,204 - 17b4: 0000 unimp - 17b6: ad05 j 1de6 <_start-0x7fffe21a> - 17b8: 1002 c.slli zero,0x20 - 17ba: 0668 addi a0,sp,780 - 17bc: 0000 unimp - 17be: 02e0 addi s0,sp,332 - 17c0: cd18 sw a4,24(a0) - 17c2: 0001 nop - 17c4: 0500 addi s0,sp,640 - 17c6: f00a02af 0xf00a02af - 17ca: 0008 0x8 - 17cc: ec00 fsw fs0,24(s0) - 17ce: 0002 c.slli64 zero - 17d0: 05bc040f 0x5bc040f - 17d4: 0000 unimp - 17d6: 0102 c.slli64 sp - 17d8: 7008 flw fa0,32(s0) - 17da: 0006 c.slli zero,0x1 - 17dc: 1500 addi s0,sp,672 - 17de: 05bc addi a5,sp,712 - 17e0: 0000 unimp - 17e2: 0444040f 0x444040f - 17e6: 0000 unimp - 17e8: 00009613 slli a2,ra,0x0 - 17ec: ec00 fsw fs0,24(s0) - 17ee: 0005 c.nop 1 - 17f0: 1400 addi s0,sp,544 - 17f2: 0462 slli s0,s0,0x18 - 17f4: 0000 unimp - 17f6: 1d14 addi a3,sp,688 - 17f8: 0001 nop - 17fa: 1400 addi s0,sp,544 - 17fc: 05ec addi a1,sp,716 - 17fe: 0000 unimp - 1800: 2c14 fld fa3,24(s0) - 1802: 0000 unimp - 1804: 0000 unimp - 1806: 05c3040f 0x5c3040f - 180a: 0000 unimp - 180c: ec15 bnez s0,1848 <_start-0x7fffe7b8> - 180e: 0005 c.nop 1 - 1810: 0f00 addi s0,sp,912 - 1812: ce04 sw s1,24(a2) - 1814: 0005 c.nop 1 - 1816: 1300 addi s0,sp,416 - 1818: 008a slli ra,ra,0x2 - 181a: 0000 unimp - 181c: 0000061b 0x61b - 1820: 6214 flw fa3,0(a2) - 1822: 0004 0x4 - 1824: 1400 addi s0,sp,544 - 1826: 011d addi sp,sp,7 - 1828: 0000 unimp - 182a: 8a14 0x8a14 - 182c: 0000 unimp - 182e: 1400 addi s0,sp,544 - 1830: 002c addi a1,sp,8 - 1832: 0000 unimp - 1834: 0f00 addi s0,sp,912 - 1836: fd04 fsw fs1,56(a0) - 1838: 0005 c.nop 1 - 183a: 1300 addi s0,sp,416 - 183c: 002c addi a1,sp,8 - 183e: 0000 unimp - 1840: 0635 addi a2,a2,13 - 1842: 0000 unimp - 1844: 6214 flw fa3,0(a2) - 1846: 0004 0x4 - 1848: 1400 addi s0,sp,544 - 184a: 011d addi sp,sp,7 - 184c: 0000 unimp - 184e: 0f00 addi s0,sp,912 - 1850: 2104 fld fs1,0(a0) - 1852: 0006 c.slli zero,0x1 - 1854: 0800 addi s0,sp,16 - 1856: 0000004f fnmadd.s ft0,ft0,ft0,ft0,rne - 185a: 0000064b fnmsub.s fa2,ft0,ft0,ft0,rne - 185e: 3309 jal 1560 <_start-0x7fffeaa0> - 1860: 0000 unimp - 1862: 0200 addi s0,sp,256 - 1864: 0800 addi s0,sp,16 - 1866: 0000004f fnmadd.s ft0,ft0,ft0,ft0,rne - 186a: 0000065b 0x65b - 186e: 3309 jal 1570 <_start-0x7fffea90> - 1870: 0000 unimp - 1872: 0000 unimp - 1874: 0500 addi s0,sp,640 - 1876: 0204 addi s1,sp,256 - 1878: 0000 unimp - 187a: 1f05 addi t5,t5,-31 - 187c: 1a01 addi s4,s4,-32 - 187e: 0301 addi t1,t1,0 - 1880: 0000 unimp - 1882: c419 beqz s0,1890 <_start-0x7fffe770> - 1884: 0006 c.slli zero,0x1 - 1886: 0c00 addi s0,sp,528 - 1888: 2305 jal 1da8 <_start-0x7fffe258> - 188a: 0801 addi a6,a6,0 - 188c: 06a1 addi a3,a3,8 - 188e: 0000 unimp - 1890: 00079117 auipc sp,0x79 - 1894: 0500 addi s0,sp,640 - 1896: 0125 addi sp,sp,9 - 1898: a111 j 1c9c <_start-0x7fffe364> - 189a: 0006 c.slli zero,0x1 - 189c: 0000 unimp - 189e: 00035d17 auipc s10,0x35 - 18a2: 0500 addi s0,sp,640 - 18a4: 0126 slli sp,sp,0x9 - 18a6: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> - 18aa: 0400 addi s0,sp,512 - 18ac: 00057217 auipc tp,0x57 - 18b0: 0500 addi s0,sp,640 - 18b2: a70b0127 0xa70b0127 - 18b6: 0006 c.slli zero,0x1 - 18b8: 0800 addi s0,sp,16 - 18ba: 0f00 addi s0,sp,912 - 18bc: 6804 flw fs1,16(s0) - 18be: 0006 c.slli zero,0x1 - 18c0: 0f00 addi s0,sp,912 - 18c2: 5b04 lw s1,48(a4) - 18c4: 0006 c.slli zero,0x1 - 18c6: 1900 addi s0,sp,176 - 18c8: 001c 0x1c - 18ca: 0000 unimp - 18cc: 050e slli a0,a0,0x3 - 18ce: e608013f 17000006 0x17000006e608013f - 18d6: 062e slli a2,a2,0xb - 18d8: 0000 unimp - 18da: 4005 c.li zero,1 - 18dc: 1201 addi tp,tp,-32 - 18de: 06e6 slli a3,a3,0x19 - 18e0: 0000 unimp - 18e2: 1700 addi s0,sp,928 - 18e4: 0401 addi s0,s0,0 - 18e6: 0000 unimp - 18e8: 4105 li sp,1 - 18ea: 1201 addi tp,tp,-32 - 18ec: 06e6 slli a3,a3,0x19 - 18ee: 0000 unimp - 18f0: 1706 slli a4,a4,0x21 - 18f2: 0675 addi a2,a2,29 - 18f4: 0000 unimp - 18f6: 4205 li tp,1 - 18f8: 1201 addi tp,tp,-32 - 18fa: 005d c.nop 23 - 18fc: 0000 unimp - 18fe: 000c 0xc - 1900: 5d08 lw a0,56(a0) - 1902: 0000 unimp - 1904: f600 fsw fs0,40(a2) - 1906: 0006 c.slli zero,0x1 - 1908: 0900 addi s0,sp,144 - 190a: 00000033 add zero,zero,zero - 190e: 0002 c.slli64 zero - 1910: d01a sw t1,32(sp) - 1912: 8005 srli s0,s0,0x1 - 1914: 0702 c.slli64 a4 - 1916: 0000080b 0x80b - 191a: 00043d17 auipc s10,0x43 - 191e: 0500 addi s0,sp,640 - 1920: 0282 c.slli64 t0 - 1922: 3318 fld fa4,32(a4) - 1924: 0000 unimp - 1926: 0000 unimp - 1928: 00064a17 auipc s4,0x64 - 192c: 0500 addi s0,sp,640 - 192e: b6120283 lb t0,-1183(tp) # 5840d <_start-0x7ffa7bf3> - 1932: 0005 c.nop 1 - 1934: 0400 addi s0,sp,512 - 1936: 0003b617 auipc a2,0x3b - 193a: 0500 addi s0,sp,640 - 193c: 0284 addi s1,sp,320 - 193e: 0b10 addi a2,sp,400 - 1940: 0008 0x8 - 1942: 0800 addi s0,sp,16 - 1944: 00072017 auipc zero,0x72 - 1948: 0500 addi s0,sp,640 - 194a: 0285 addi t0,t0,1 - 194c: 00019b17 auipc s6,0x19 - 1950: 2400 fld fs0,8(s0) - 1952: 00028717 auipc a4,0x28 - 1956: 0500 addi s0,sp,640 - 1958: 0286 slli t0,t0,0x1 - 195a: 00002c0f 0x2c0f - 195e: 4800 lw s0,16(s0) - 1960: 00078c17 auipc s8,0x78 - 1964: 0500 addi s0,sp,640 - 1966: 252c0287 0x252c0287 - 196a: 0000 unimp - 196c: 5000 lw s0,32(s0) - 196e: 00073817 auipc a6,0x73 - 1972: 0500 addi s0,sp,640 - 1974: 0288 addi a0,sp,320 - 1976: ad1a fsd ft6,152(sp) - 1978: 0006 c.slli zero,0x1 - 197a: 5800 lw s0,48(s0) - 197c: 00059e17 auipc t3,0x59 - 1980: 0500 addi s0,sp,640 - 1982: 0289 addi t0,t0,2 - 1984: 0516 slli a0,a0,0x5 - 1986: 0001 nop - 1988: 6800 flw fs0,16(s0) - 198a: 00075817 auipc a6,0x75 - 198e: 0500 addi s0,sp,640 - 1990: 028a slli t0,t0,0x2 - 1992: 0516 slli a0,a0,0x5 - 1994: 0001 nop - 1996: 7000 flw fs0,32(s0) - 1998: 0001bf17 auipc t5,0x1b - 199c: 0500 addi s0,sp,640 - 199e: 0516028b 0x516028b - 19a2: 0001 nop - 19a4: 7800 flw fs0,48(s0) - 19a6: 0006da17 auipc s4,0x6d - 19aa: 0500 addi s0,sp,640 - 19ac: 028c addi a1,sp,320 - 19ae: 1b10 addi a2,sp,432 - 19b0: 0008 0x8 - 19b2: 8000 0x8000 - 19b4: 0003aa17 auipc s4,0x3a - 19b8: 0500 addi s0,sp,640 - 19ba: 028d addi t0,t0,3 - 19bc: 2b10 fld fa2,16(a4) - 19be: 0008 0x8 - 19c0: 8800 0x8800 - 19c2: 00004817 auipc a6,0x4 - 19c6: 0500 addi s0,sp,640 - 19c8: 028e slli t0,t0,0x3 - 19ca: 00002c0f 0x2c0f - 19ce: a000 fsd fs0,0(s0) - 19d0: 00025117 auipc sp,0x25 - 19d4: 0500 addi s0,sp,640 - 19d6: 0516028f 0x516028f - 19da: 0001 nop - 19dc: a400 fsd fs0,8(s0) - 19de: 0000be17 auipc t3,0xb - 19e2: 0500 addi s0,sp,640 - 19e4: 0290 addi a2,sp,320 - 19e6: 0516 slli a0,a0,0x5 - 19e8: 0001 nop - 19ea: ac00 fsd fs0,24(s0) - 19ec: 00024017 auipc zero,0x24 - 19f0: 0500 addi s0,sp,640 - 19f2: 0291 addi t0,t0,4 - 19f4: 0516 slli a0,a0,0x5 - 19f6: 0001 nop - 19f8: b400 fsd fs0,40(s0) - 19fa: 00005b17 auipc s6,0x5 - 19fe: 0500 addi s0,sp,640 - 1a00: 0292 slli t0,t0,0x4 - 1a02: 0516 slli a0,a0,0x5 - 1a04: 0001 nop - 1a06: bc00 fsd fs0,56(s0) - 1a08: 00006a17 auipc s4,0x6 - 1a0c: 0500 addi s0,sp,640 - 1a0e: 05160293 addi t0,a2,81 # 3c987 <_start-0x7ffc3679> - 1a12: 0001 nop - 1a14: c400 sw s0,8(s0) - 1a16: 00054e17 auipc t3,0x54 - 1a1a: 0500 addi s0,sp,640 - 1a1c: 0294 addi a3,sp,320 - 1a1e: 2c08 fld fa0,24(s0) - 1a20: 0000 unimp - 1a22: cc00 sw s0,24(s0) - 1a24: 0800 addi s0,sp,16 - 1a26: 05bc addi a5,sp,712 - 1a28: 0000 unimp - 1a2a: 0000081b 0x81b - 1a2e: 3309 jal 1730 <_start-0x7fffe8d0> - 1a30: 0000 unimp - 1a32: 1900 addi s0,sp,176 - 1a34: 0800 addi s0,sp,16 - 1a36: 05bc addi a5,sp,712 - 1a38: 0000 unimp - 1a3a: 0000082b 0x82b - 1a3e: 3309 jal 1740 <_start-0x7fffe8c0> - 1a40: 0000 unimp - 1a42: 0700 addi s0,sp,896 - 1a44: 0800 addi s0,sp,16 - 1a46: 05bc addi a5,sp,712 - 1a48: 0000 unimp - 1a4a: 0000083b 0x83b - 1a4e: 3309 jal 1750 <_start-0x7fffe8b0> - 1a50: 0000 unimp - 1a52: 1700 addi s0,sp,928 - 1a54: 1a00 addi s0,sp,304 - 1a56: 05f0 addi a2,sp,716 - 1a58: 0299 addi t0,t0,6 - 1a5a: 00086207 vlwu.v v4,(a6),v0.t - 1a5e: 1700 addi s0,sp,928 - 1a60: 0476 slli s0,s0,0x1d - 1a62: 0000 unimp - 1a64: 9c05 0x9c05 - 1a66: 1b02 slli s6,s6,0x20 - 1a68: 0862 slli a6,a6,0x18 - 1a6a: 0000 unimp - 1a6c: 1700 addi s0,sp,928 - 1a6e: 0296 slli t0,t0,0x5 - 1a70: 0000 unimp - 1a72: 9d05 0x9d05 - 1a74: 1802 slli a6,a6,0x20 - 1a76: 0872 slli a6,a6,0x1c - 1a78: 0000 unimp - 1a7a: 0078 addi a4,sp,12 - 1a7c: fb08 fsw fa0,48(a4) - 1a7e: 0002 c.slli64 zero - 1a80: 7200 flw fs0,32(a2) - 1a82: 0008 0x8 - 1a84: 0900 addi s0,sp,144 - 1a86: 00000033 add zero,zero,zero - 1a8a: 001d c.nop 7 - 1a8c: 3308 fld fa0,32(a4) - 1a8e: 0000 unimp - 1a90: 8200 0x8200 - 1a92: 0008 0x8 - 1a94: 0900 addi s0,sp,144 - 1a96: 00000033 add zero,zero,zero - 1a9a: 001d c.nop 7 - 1a9c: 7e05f01b 0x7e05f01b - 1aa0: 0302 c.slli64 t1 - 1aa2: 000008a7 vsb.v v17,(zero),v0.t - 1aa6: d11c sw a5,32(a0) - 1aa8: 0005 c.nop 1 - 1aaa: 0500 addi s0,sp,640 - 1aac: 0295 addi t0,t0,5 - 1aae: 0006f60b 0x6f60b - 1ab2: 1c00 addi s0,sp,560 - 1ab4: 00000703 lb a4,0(zero) # 0 <_start-0x80000000> - 1ab8: 9e05 0x9e05 - 1aba: 0b02 c.slli64 s6 - 1abc: 0000083b 0x83b - 1ac0: 0800 addi s0,sp,16 - 1ac2: 05bc addi a5,sp,712 - 1ac4: 0000 unimp - 1ac6: 000008b7 lui a7,0x0 - 1aca: 3309 jal 17cc <_start-0x7fffe834> - 1acc: 0000 unimp - 1ace: 1800 addi s0,sp,48 - 1ad0: 1d00 addi s0,sp,688 - 1ad2: 000000b3 add ra,zero,zero - 1ad6: 08b7040f 0x8b7040f - 1ada: 0000 unimp - 1adc: cd1e sw t2,152(sp) - 1ade: 0008 0x8 - 1ae0: 1400 addi s0,sp,544 - 1ae2: 0462 slli s0,s0,0x18 - 1ae4: 0000 unimp - 1ae6: 0f00 addi s0,sp,912 - 1ae8: c204 sw s1,0(a2) - 1aea: 0008 0x8 - 1aec: 0f00 addi s0,sp,912 - 1aee: 8504 0x8504 - 1af0: 0001 nop - 1af2: 1e00 addi s0,sp,816 - 1af4: 08e4 addi s1,sp,92 - 1af6: 0000 unimp - 1af8: 2c14 fld fa3,24(s0) - 1afa: 0000 unimp - 1afc: 0000 unimp - 1afe: 08ea040f 0x8ea040f - 1b02: 0000 unimp - 1b04: 08d9040f 0x8d9040f - 1b08: 0000 unimp - 1b0a: 5b08 lw a0,48(a4) - 1b0c: 0006 c.slli zero,0x1 - 1b0e: 0000 unimp - 1b10: 0009 c.nop 2 - 1b12: 0900 addi s0,sp,144 - 1b14: 00000033 add zero,zero,zero - 1b18: 0002 c.slli64 zero - 1b1a: 9e1f 0006 0500 0x50000069e1f - 1b20: 032e slli t1,t1,0xb - 1b22: 00046217 auipc tp,0x46 - 1b26: 1f00 addi s0,sp,944 - 1b28: 00000697 auipc a3,0x0 - 1b2c: 2f05 jal 225c <_start-0x7fffdda4> - 1b2e: 04681d03 lh s10,70(a6) # 5a08 <_start-0x7fffa5f8> - 1b32: 0000 unimp - 1b34: f208 fsw fa0,32(a2) - 1b36: 0005 c.nop 1 - 1b38: 2500 fld fs0,8(a0) - 1b3a: 0009 c.nop 2 - 1b3c: 2000 fld fs0,0(s0) - 1b3e: 1500 addi s0,sp,672 - 1b40: 091a slli s2,s2,0x6 - 1b42: 0000 unimp - 1b44: 2b21 jal 205c <_start-0x7fffdfa4> - 1b46: 0002 c.slli64 zero - 1b48: 0600 addi s0,sp,768 - 1b4a: 2414 fld fa3,8(s0) - 1b4c: 0925 addi s2,s2,9 - 1b4e: 0000 unimp - 1b50: 9421 srai s0,s0,0x28 - 1b52: 0005 c.nop 1 - 1b54: 0600 addi s0,sp,768 - 1b56: 1515 addi a0,a0,-27 - 1b58: 002c addi a1,sp,8 - 1b5a: 0000 unimp - 1b5c: 0948040f 0x948040f - 1b60: 0000 unimp - 1b62: 00002c13 slti s8,zero,0 - 1b66: 5c00 lw s0,56(s0) - 1b68: 0009 c.nop 2 - 1b6a: 1400 addi s0,sp,544 - 1b6c: 095c addi a5,sp,148 - 1b6e: 0000 unimp - 1b70: 5c14 lw a3,56(s0) - 1b72: 0009 c.nop 2 - 1b74: 0000 unimp - 1b76: 0962040f 0x962040f - 1b7a: 0000 unimp - 1b7c: 2122 fld ft2,8(sp) - 1b7e: 049c addi a5,sp,576 - 1b80: 0000 unimp - 1b82: b60e6707 0xb60e6707 - 1b86: 0005 c.nop 1 - 1b88: 2100 fld fs0,0(a0) - 1b8a: 03dc addi a5,sp,452 - 1b8c: 0000 unimp - 1b8e: 1008 addi a0,sp,32 - 1b90: 00097b0f 0x97b0f - 1b94: 0f00 addi s0,sp,912 - 1b96: b604 fsd fs1,40(a2) - 1b98: 0005 c.nop 1 - 1b9a: 2100 fld fs0,0(a0) - 1b9c: 049f 0000 fc08 0xfc080000049f - 1ba2: b60e fsd ft3,296(sp) - 1ba4: 0005 c.nop 1 - 1ba6: 2100 fld fs0,0(a0) - 1ba8: 008e slli ra,ra,0x3 - 1baa: 0000 unimp - 1bac: fd08 fsw fa0,56(a0) - 1bae: 2c0c fld fa1,24(s0) - 1bb0: 0000 unimp - 1bb2: 2100 fld fs0,0(a0) - 1bb4: 0634 addi a3,sp,776 - 1bb6: 0000 unimp - 1bb8: fd08 fsw fa0,56(a0) - 1bba: 2c14 fld fa3,24(s0) - 1bbc: 0000 unimp - 1bbe: 2100 fld fs0,0(a0) - 1bc0: 00000747 fmsub.s fa4,ft0,ft0,ft0,rne - 1bc4: fd08 fsw fa0,56(a0) - 1bc6: 2c1c fld fa5,24(s0) - 1bc8: 0000 unimp - 1bca: 2100 fld fs0,0(a0) - 1bcc: 0000041b 0x41b - 1bd0: ff08 fsw fa0,56(a4) - 1bd2: 2c0c fld fa1,24(s0) - 1bd4: 0000 unimp - 1bd6: 2100 fld fs0,0(a0) - 1bd8: 04cc addi a1,sp,580 - 1bda: 0000 unimp - 1bdc: 9a09 andi a2,a2,-30 - 1bde: 6416 flw fs0,68(sp) - 1be0: 0000 unimp - 1be2: 2100 fld fs0,0(a0) - 1be4: 0000002f 0x2f - 1be8: 9b09 andi a4,a4,-30 - 1bea: 2c15 jal 1e1e <_start-0x7fffe1e2> - 1bec: 0000 unimp - 1bee: 0800 addi s0,sp,16 - 1bf0: 05b6 slli a1,a1,0xd - 1bf2: 0000 unimp - 1bf4: 09e5 addi s3,s3,25 - 1bf6: 0000 unimp - 1bf8: 3309 jal 18fa <_start-0x7fffe706> - 1bfa: 0000 unimp - 1bfc: 0100 addi s0,sp,128 - 1bfe: 2100 fld fs0,0(a0) - 1c00: 00cd addi ra,ra,19 - 1c02: 0000 unimp - 1c04: 9e09 0x9e09 - 1c06: 0009d517 auipc a0,0x9d - 1c0a: 0400 addi s0,sp,512 - 1c0c: 02ea slli t0,t0,0x1a - 1c0e: 0000 unimp - 1c10: 2a0a fld fs4,128(sp) - 1c12: 3316 fld ft6,352(sp) - 1c14: 0000 unimp - 1c16: 0400 addi s0,sp,512 - 1c18: 0582 c.slli64 a1 - 1c1a: 0000 unimp - 1c1c: 2f0a fld ft10,128(sp) - 1c1e: 0915 addi s2,s2,5 - 1c20: 000a c.slli zero,0x2 - 1c22: 0f00 addi s0,sp,912 - 1c24: 0f04 addi s1,sp,912 - 1c26: 000a c.slli zero,0x2 - 1c28: 1300 addi s0,sp,416 - 1c2a: 09f1 addi s3,s3,28 - 1c2c: 0000 unimp - 1c2e: 0a1e slli s4,s4,0x7 - 1c30: 0000 unimp - 1c32: 5c14 lw a3,56(s0) - 1c34: 0009 c.nop 2 - 1c36: 0000 unimp - 1c38: 9704 0x9704 - 1c3a: 0a000007 vlsbu.v v0,(zero),zero - 1c3e: 0f36 slli t5,t5,0xd - 1c40: 0942 slli s2,s2,0x10 - 1c42: 0000 unimp - 1c44: 0a21 addi s4,s4,8 - 1c46: 0000 unimp - 1c48: 0a00 addi s0,sp,272 - 1c4a: 09fd12bb 0x9fd12bb - 1c4e: 0000 unimp - 1c50: 8221 srli a2,a2,0x8 - 1c52: 0006 c.slli zero,0x1 - 1c54: 0a00 addi s0,sp,272 - 1c56: 10be slli ra,ra,0x2f - 1c58: 0a1e slli s4,s4,0x7 - 1c5a: 0000 unimp - 1c5c: 0002bd23 0x2bd23 - 1c60: 0700 addi s0,sp,896 - 1c62: 3304 fld fs1,32(a4) - 1c64: 0000 unimp - 1c66: 0b00 addi s0,sp,400 - 1c68: 0618 addi a4,sp,768 - 1c6a: 0a7f 0xa7f - 1c6c: 0000 unimp - 1c6e: 2924 fld fs1,80(a0) - 1c70: 0005 c.nop 1 - 1c72: 0000 unimp - 1c74: f624 fsw fs1,104(a2) - 1c76: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1c7a: d124 sw s1,96(a0) - 1c7c: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 1c80: 4a24 lw s1,80(a2) - 1c82: 0004 0x4 - 1c84: 0300 addi s0,sp,384 - 1c86: 2024 fld fs1,64(s0) - 1c88: 0005 c.nop 1 - 1c8a: 0400 addi s0,sp,512 - 1c8c: 4e24 lw s1,88(a2) - 1c8e: 05000007 0x5000007 - 1c92: 3d24 fld fs1,120(a0) - 1c94: 06000007 0x6000007 - 1c98: 2100 fld fs0,0(a0) - 1c9a: 00a9 addi ra,ra,10 - 1c9c: 0000 unimp - 1c9e: 421c210b 0x421c210b - 1ca2: 000a c.slli zero,0x2 - 1ca4: 2300 fld fs0,0(a4) - 1ca6: 0455 addi s0,s0,21 - 1ca8: 0000 unimp - 1caa: 00330407 0x330407 - 1cae: 0000 unimp - 1cb0: b006230b 0xb006230b - 1cb4: 000a c.slli zero,0x2 - 1cb6: 2400 fld fs0,8(s0) - 1cb8: 0578 addi a4,sp,652 - 1cba: 0000 unimp - 1cbc: 2400 fld fs0,8(s0) - 1cbe: 0000053f 06572401 0x65724010000053f - 1cc6: 0000 unimp - 1cc8: 0002 c.slli64 zero - 1cca: 5f21 li t5,-24 - 1ccc: 0002 c.slli64 zero - 1cce: 0b00 addi s0,sp,400 - 1cd0: 1e28 addi a0,sp,824 - 1cd2: 00000a8b 0xa8b - 1cd6: 0c21 addi s8,s8,8 - 1cd8: 0004 0x4 - 1cda: 0c00 addi s0,sp,528 - 1cdc: 1a29 addi s4,s4,-22 - 1cde: 0925 addi s2,s2,9 - 1ce0: 0000 unimp - 1ce2: 1e21 addi t3,t3,-24 - 1ce4: 0006 c.slli zero,0x1 - 1ce6: 0c00 addi s0,sp,528 - 1ce8: 1a38 addi a4,sp,312 - 1cea: 0925 addi s2,s2,9 - 1cec: 0000 unimp - 1cee: 7304 flw fs1,32(a4) - 1cf0: 0d000007 vlxbu.v v0,(zero),v16,v0.t - 1cf4: 004f167b 0x4f167b - 1cf8: 0000 unimp - 1cfa: d415 beqz s0,1c26 <_start-0x7fffe3da> - 1cfc: 000a c.slli zero,0x2 - 1cfe: 0400 addi s0,sp,512 - 1d00: 0216 slli tp,tp,0x5 - 1d02: 0000 unimp - 1d04: 800d srli s0,s0,0x3 - 1d06: 00002c0f 0x2c0f - 1d0a: 0400 addi s0,sp,512 - 1d0c: 0215 addi tp,tp,5 - 1d0e: 0000 unimp - 1d10: 810d srli a0,a0,0x3 - 1d12: 3316 fld ft6,352(sp) - 1d14: 0000 unimp - 1d16: 0400 addi s0,sp,512 - 1d18: 000006ab 0x6ab - 1d1c: 840d srai s0,s0,0x3 - 1d1e: 00003a0f 0x3a0f - 1d22: 0400 addi s0,sp,512 - 1d24: 06aa slli a3,a3,0xa - 1d26: 0000 unimp - 1d28: 850d srai a0,a0,0x3 - 1d2a: 2516 fld fa0,320(sp) - 1d2c: 0000 unimp - 1d2e: 0200 addi s0,sp,256 - 1d30: 0404 addi s1,sp,512 - 1d32: 0485 addi s1,s1,1 - 1d34: 0000 unimp - 1d36: 0802 c.slli64 a6 - 1d38: 00047d03 0x47d03 - 1d3c: 0200 addi s0,sp,256 - 1d3e: 0408 addi a0,sp,512 - 1d40: 00a2 slli ra,ra,0x8 - 1d42: 0000 unimp - 1d44: 1002 c.slli zero,0x20 - 1d46: 00003903 0x3903 - 1d4a: 0200 addi s0,sp,256 - 1d4c: 0320 addi s0,sp,392 - 1d4e: 0095 addi ra,ra,5 - 1d50: 0000 unimp - 1d52: 7b19 lui s6,0xfffe6 - 1d54: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - 1d58: ed0d bnez a0,1d92 <_start-0x7fffe26e> - 1d5a: 0a01 addi s4,s4,0 - 1d5c: 00000b63 beqz zero,1d72 <_start-0x7fffe28e> - 1d60: 6c25 lui s8,0x9 - 1d62: 0d00776f jal a4,8e32 <_start-0x7fff71ce> - 1d66: 01ed addi gp,gp,27 - 1d68: e51a fsw ft6,136(sp) - 1d6a: 000a c.slli zero,0x2 - 1d6c: 0000 unimp - 1d6e: 00063b17 auipc s6,0x63 - 1d72: 0d00 addi s0,sp,656 - 1d74: 01ed addi gp,gp,27 - 1d76: e51f 000a 0400 0x400000ae51f - 1d7c: 1b00 addi s0,sp,432 - 1d7e: 0d08 addi a0,sp,656 - 1d80: 01f4 addi a3,sp,204 - 1d82: 8509 srai a0,a0,0x2 - 1d84: 2600000b 0x2600000b - 1d88: f60d0073 0xf60d0073 - 1d8c: 1301 addi t1,t1,-32 - 1d8e: 0b38 addi a4,sp,408 - 1d90: 0000 unimp - 1d92: 6c26 flw fs8,72(sp) - 1d94: 006c addi a1,sp,12 - 1d96: f70d bnez a4,1cc0 <_start-0x7fffe340> - 1d98: 0a01 addi s4,s4,0 - 1d9a: 0afd addi s5,s5,31 - 1d9c: 0000 unimp - 1d9e: 0500 addi s0,sp,640 - 1da0: 02f4 addi a3,sp,332 - 1da2: 0000 unimp - 1da4: f80d bnez s0,1cd6 <_start-0x7fffe32a> - 1da6: 0301 addi t1,t1,0 - 1da8: 00000b63 beqz zero,1dbe <_start-0x7fffe242> - 1dac: 8515 srai a0,a0,0x5 - 1dae: 0800000b 0x800000b - 1db2: 0ae0 addi s0,sp,348 - 1db4: 0000 unimp - 1db6: 00000ba7 vsb.v v23,(zero),v0.t - 1dba: 3309 jal 1abc <_start-0x7fffe544> - 1dbc: 0000 unimp - 1dbe: ff00 fsw fs0,56(a4) - 1dc0: 1500 addi s0,sp,672 - 1dc2: 00000b97 auipc s7,0x0 - 1dc6: ee1f 0006 0d00 0xd000006ee1f - 1dcc: 01fc addi a5,sp,204 - 1dce: a716 fsd ft5,392(sp) - 1dd0: 1f00000b 0x1f00000b - 1dd4: 00000397 auipc t2,0x0 - 1dd8: 020d addi tp,tp,3 - 1dda: 1602 slli a2,a2,0x20 - 1ddc: 00000ba7 vsb.v v23,(zero),v0.t - 1de0: 00079f27 0x79f27 - 1de4: 0100 addi s0,sp,128 - 1de6: 051a slli a0,a0,0x6 - 1de8: 0901 addi s2,s2,0 - 1dea: d800000b 0xd800000b - 1dee: 10800103 lb sp,264(zero) # 108 <_start-0x7ffffef8> - 1df2: 0004 0x4 - 1df4: 0100 addi s0,sp,128 - 1df6: 009c addi a5,sp,64 - 1df8: 2800000f 0x2800000f - 1dfc: 0075 c.nop 29 - 1dfe: 1a01 addi s4,s4,-32 - 1e00: 1405 addi s0,s0,-31 - 1e02: 0b09 addi s6,s6,2 - 1e04: 0000 unimp - 1e06: 0c1c addi a5,sp,528 - 1e08: 0000 unimp - 1e0a: 7628 flw fa0,104(a2) - 1e0c: 0100 addi s0,sp,128 - 1e0e: 051a slli a0,a0,0x6 - 1e10: 091f 000b c400 0xc400000b091f - 1e16: 000c 0xc - 1e18: 2900 fld fs0,16(a0) - 1e1a: 1c010077 0x1c010077 - 1e1e: 0b05 addi s6,s6,1 - 1e20: 0b09 addi s6,s6,2 - 1e22: 0000 unimp - 1e24: 0d2c addi a1,sp,664 - 1e26: 0000 unimp - 1e28: 002a c.slli zero,0xa - 1e2a: d800000f 0xd800000f - 1e2e: 00800103 lb sp,8(zero) # 8 <_start-0x7ffffff8> - 1e32: 0001 nop - 1e34: 0100 addi s0,sp,128 - 1e36: 051e slli a0,a0,0x7 - 1e38: 2b0a fld fs6,128(sp) - 1e3a: 0f28 addi a0,sp,920 - 1e3c: 0000 unimp - 1e3e: 0d44 addi s1,sp,660 - 1e40: 0000 unimp - 1e42: 000f1d2b 0xf1d2b - 1e46: 6c00 flw fs0,24(s0) - 1e48: 000d c.nop 3 - 1e4a: 2b00 fld fs0,16(a4) - 1e4c: 0f12 slli t5,t5,0x4 - 1e4e: 0000 unimp - 1e50: 0dd4 addi a3,sp,724 - 1e52: 0000 unimp - 1e54: 002c addi a1,sp,8 - 1e56: 0001 nop - 1e58: 2d00 fld fs0,24(a0) - 1e5a: 0f34 addi a3,sp,920 - 1e5c: 0000 unimp - 1e5e: 402d c.li zero,11 - 1e60: 2d00000f 0x2d00000f - 1e64: 0f4c addi a1,sp,916 - 1e66: 0000 unimp - 1e68: 582e lw a6,232(sp) - 1e6a: 4c00000f 0x4c00000f - 1e6e: 000e c.slli zero,0x3 - 1e70: 2e00 fld fs0,24(a2) - 1e72: 0f64 addi s1,sp,924 - 1e74: 0000 unimp - 1e76: 00000e8b 0xe8b - 1e7a: 702e flw ft0,232(sp) - 1e7c: e000000f 0xe000000f - 1e80: 000e c.slli zero,0x3 - 1e82: 2e00 fld fs0,24(a2) - 1e84: 0f7c addi a5,sp,924 - 1e86: 0000 unimp - 1e88: 0f56 slli t5,t5,0x15 - 1e8a: 0000 unimp - 1e8c: 882e mv a6,a1 - 1e8e: e200000f 0xe200000f - 1e92: 2e00000f 0x2e00000f - 1e96: 0f94 addi a3,sp,976 - 1e98: 0000 unimp - 1e9a: 1000 addi s0,sp,32 - 1e9c: 0000 unimp - 1e9e: a02e fsd fa1,0(sp) - 1ea0: 1400000f 0x1400000f - 1ea4: 0010 0x10 - 1ea6: 2e00 fld fs0,24(a2) - 1ea8: 0fac addi a1,sp,984 - 1eaa: 0000 unimp - 1eac: 1034 addi a3,sp,40 - 1eae: 0000 unimp - 1eb0: b72e fsd fa1,424(sp) - 1eb2: 5200000f 0x5200000f - 1eb6: 0010 0x10 - 1eb8: 2d00 fld fs0,24(a0) - 1eba: 00000fc3 fmadd.s ft11,ft0,ft0,ft0,rne - 1ebe: 000fcf2f 0xfcf2f - 1ec2: 1800 addi s0,sp,48 - 1ec4: 0001 nop - 1ec6: c400 sw s0,8(s0) - 1ec8: 000c 0xc - 1eca: 2e00 fld fs0,24(a2) - 1ecc: 0fd4 addi a3,sp,980 - 1ece: 0000 unimp - 1ed0: 1091 addi ra,ra,-28 - 1ed2: 0000 unimp - 1ed4: e12e fsw fa1,128(sp) - 1ed6: af00000f 0xaf00000f - 1eda: 0010 0x10 - 1edc: 0000 unimp - 1ede: ef30 fsw fa2,88(a4) - 1ee0: 3c00000f 0x3c00000f - 1ee4: 0104 addi s1,sp,128 - 1ee6: 7080 flw fs0,32(s1) - 1ee8: 0000 unimp - 1eea: 1100 addi s0,sp,160 - 1eec: 000d c.nop 3 - 1eee: 2e00 fld fs0,24(a2) - 1ef0: 0ff4 addi a3,sp,988 - 1ef2: 0000 unimp - 1ef4: 10c2 slli ra,ra,0x30 - 1ef6: 0000 unimp - 1ef8: 012e slli sp,sp,0xb - 1efa: 0010 0x10 - 1efc: d500 sw s0,40(a0) - 1efe: 0010 0x10 - 1f00: 2d00 fld fs0,24(a0) - 1f02: 100e c.slli zero,0x23 - 1f04: 0000 unimp - 1f06: 1b2e slli s6,s6,0x2b - 1f08: 0010 0x10 - 1f0a: f900 fsw fs0,48(a0) - 1f0c: 0010 0x10 - 1f0e: 2e00 fld fs0,24(a2) - 1f10: 1028 addi a0,sp,40 - 1f12: 0000 unimp - 1f14: 110c addi a1,sp,160 - 1f16: 0000 unimp - 1f18: 352e fld fa0,232(sp) - 1f1a: 0010 0x10 - 1f1c: 2a00 fld fs0,16(a2) - 1f1e: 0011 c.nop 4 - 1f20: 2e00 fld fs0,24(a2) - 1f22: 1042 c.slli zero,0x30 - 1f24: 0000 unimp - 1f26: 1148 addi a0,sp,164 - 1f28: 0000 unimp - 1f2a: 2f00 fld fs0,24(a4) - 1f2c: 1050 addi a2,sp,36 - 1f2e: 0000 unimp - 1f30: 0130 addi a2,sp,136 - 1f32: 0000 unimp - 1f34: 0d31 addi s10,s10,12 - 1f36: 0000 unimp - 1f38: 552e lw a0,232(sp) - 1f3a: 0010 0x10 - 1f3c: 6600 flw fs0,8(a2) - 1f3e: 0011 c.nop 4 - 1f40: 2e00 fld fs0,24(a2) - 1f42: 1062 c.slli zero,0x38 - 1f44: 0000 unimp - 1f46: 1184 addi s1,sp,224 - 1f48: 0000 unimp - 1f4a: 3000 fld fs0,32(s0) - 1f4c: 10d1 addi ra,ra,-12 - 1f4e: 0000 unimp - 1f50: 050c addi a1,sp,640 - 1f52: 8001 c.srli64 s0 - 1f54: 0074 addi a3,sp,12 - 1f56: 0000 unimp - 1f58: 0d82 c.slli64 s11 - 1f5a: 0000 unimp - 1f5c: d62e sw a1,44(sp) - 1f5e: 0010 0x10 - 1f60: a200 fsd fs0,0(a2) - 1f62: 0011 c.nop 4 - 1f64: 2e00 fld fs0,24(a2) - 1f66: 000010e3 bnez zero,2766 <_start-0x7fffd89a> - 1f6a: 11b5 addi gp,gp,-19 - 1f6c: 0000 unimp - 1f6e: f02e fsw fa1,32(sp) - 1f70: 0010 0x10 - 1f72: d900 sw s0,48(a0) - 1f74: 0011 c.nop 4 - 1f76: 2e00 fld fs0,24(a2) - 1f78: 10fd addi ra,ra,-1 - 1f7a: 0000 unimp - 1f7c: 11ec addi a1,sp,236 - 1f7e: 0000 unimp - 1f80: 0a2e slli s4,s4,0xb - 1f82: 0011 c.nop 4 - 1f84: ff00 fsw fs0,56(a4) - 1f86: 0011 c.nop 4 - 1f88: 2e00 fld fs0,24(a2) - 1f8a: 00001117 auipc sp,0x1 - 1f8e: 1228 addi a0,sp,296 - 1f90: 0000 unimp - 1f92: 242e fld fs0,200(sp) - 1f94: 0011 c.nop 4 - 1f96: 4600 lw s0,8(a2) - 1f98: 0012 c.slli zero,0x4 - 1f9a: 0000 unimp - 1f9c: 0010702f vamoadde.v zero,v1,(zero),v0,v0.t - 1fa0: 4800 lw s0,16(s0) - 1fa2: 0001 nop - 1fa4: cf00 sw s0,24(a4) - 1fa6: 000d c.nop 3 - 1fa8: 2e00 fld fs0,24(a2) - 1faa: 1075 c.nop -3 - 1fac: 0000 unimp - 1fae: 1264 addi s1,sp,300 - 1fb0: 0000 unimp - 1fb2: 822e mv tp,a1 - 1fb4: 0010 0x10 - 1fb6: 7700 flw fs0,40(a4) - 1fb8: 0012 c.slli zero,0x4 - 1fba: 2e00 fld fs0,24(a2) - 1fbc: 0000108f 0x108f - 1fc0: 0000129b 0x129b - 1fc4: 9c2e add s8,s8,a1 - 1fc6: 0010 0x10 - 1fc8: ae00 fsd fs0,24(a2) - 1fca: 0012 c.slli zero,0x4 - 1fcc: 2e00 fld fs0,24(a2) - 1fce: 10a9 addi ra,ra,-22 - 1fd0: 0000 unimp - 1fd2: 12c1 addi t0,t0,-16 - 1fd4: 0000 unimp - 1fd6: b62e fsd fa1,296(sp) - 1fd8: 0010 0x10 - 1fda: ea00 fsw fs0,16(a2) - 1fdc: 0012 c.slli zero,0x4 - 1fde: 2e00 fld fs0,24(a2) - 1fe0: 000010c3 fmadd.s ft1,ft0,ft0,ft0,rtz - 1fe4: 1308 addi a0,sp,416 - 1fe6: 0000 unimp - 1fe8: 2f00 fld fs0,24(a4) - 1fea: 1132 slli sp,sp,0x2c - 1fec: 0000 unimp - 1fee: 0160 addi s0,sp,140 - 1ff0: 0000 unimp - 1ff2: 00000def jal s11,1ff2 <_start-0x7fffe00e> - 1ff6: 372e fld fa4,232(sp) - 1ff8: 0011 c.nop 4 - 1ffa: 2600 fld fs0,8(a2) - 1ffc: 2e000013 li zero,736 - 2000: 1144 addi s1,sp,164 - 2002: 0000 unimp - 2004: 1339 addi t1,t1,-18 - 2006: 0000 unimp - 2008: 3000 fld fs0,32(s0) - 200a: 1152 slli sp,sp,0x34 - 200c: 0000 unimp - 200e: 0664 addi s1,sp,780 - 2010: 8001 c.srli64 s0 - 2012: 0010 0x10 - 2014: 0000 unimp - 2016: 0e0a slli t3,t3,0x2 - 2018: 0000 unimp - 201a: 572e lw a4,232(sp) - 201c: 0011 c.nop 4 - 201e: 5700 lw s0,40(a4) - 2020: 00000013 nop - 2024: 6531 lui a0,0xc - 2026: 0011 c.nop 4 - 2028: 9400 0x9400 - 202a: 0106 slli sp,sp,0x1 - 202c: 5080 lw s0,32(s1) - 202e: 0001 nop - 2030: 2e00 fld fs0,24(a2) - 2032: 1166 slli sp,sp,0x39 - 2034: 0000 unimp - 2036: 136a slli t1,t1,0x3a - 2038: 0000 unimp - 203a: 722e flw ft4,232(sp) - 203c: 0011 c.nop 4 - 203e: 7d00 flw fs0,56(a0) - 2040: 2f000013 li zero,752 - 2044: 117e slli sp,sp,0x3f - 2046: 0000 unimp - 2048: 0178 addi a4,sp,140 - 204a: 0000 unimp - 204c: 0e76 slli t3,t3,0x1d - 204e: 0000 unimp - 2050: 832e mv t1,a1 - 2052: 0011 c.nop 4 - 2054: a600 fsd fs0,8(a2) - 2056: 2e000013 li zero,736 - 205a: 1190 addi a2,sp,224 - 205c: 0000 unimp - 205e: 13c8 addi a0,sp,484 - 2060: 0000 unimp - 2062: 9d2e add s10,s10,a1 - 2064: 0011 c.nop 4 - 2066: ec00 fsw fs0,24(s0) - 2068: 2e000013 li zero,736 - 206c: 11aa slli gp,gp,0x2a - 206e: 0000 unimp - 2070: 140a slli s0,s0,0x22 - 2072: 0000 unimp - 2074: b72e fsd fa1,424(sp) - 2076: 0011 c.nop 4 - 2078: 2800 fld fs0,16(s0) - 207a: 0014 0x14 - 207c: 2e00 fld fs0,24(a2) - 207e: 11c4 addi s1,sp,228 - 2080: 0000 unimp - 2082: 1451 addi s0,s0,-12 - 2084: 0000 unimp - 2086: d12e sw a1,160(sp) - 2088: 0011 c.nop 4 - 208a: 7a00 flw fs0,48(a2) - 208c: 0014 0x14 - 208e: 0000 unimp - 2090: 0011df2f 0x11df2f - 2094: b000 fsd fs0,32(s0) - 2096: 0001 nop - 2098: ca00 sw s0,16(a2) - 209a: 000e c.slli zero,0x3 - 209c: 2e00 fld fs0,24(a2) - 209e: 11e4 addi s1,sp,236 - 20a0: 0000 unimp - 20a2: 14a8 addi a0,sp,616 - 20a4: 0000 unimp - 20a6: f12e fsw fa1,160(sp) - 20a8: 0011 c.nop 4 - 20aa: bb00 fsd fs0,48(a4) - 20ac: 0014 0x14 - 20ae: 2e00 fld fs0,24(a2) - 20b0: 11fe slli gp,gp,0x3f - 20b2: 0000 unimp - 20b4: 14e0 addi s0,sp,620 - 20b6: 0000 unimp - 20b8: 0b2e slli s6,s6,0xb - 20ba: 0012 c.slli zero,0x4 - 20bc: f300 fsw fs0,32(a4) - 20be: 0014 0x14 - 20c0: 2e00 fld fs0,24(a2) - 20c2: 1218 addi a4,sp,288 - 20c4: 0000 unimp - 20c6: 1506 slli a0,a0,0x21 - 20c8: 0000 unimp - 20ca: 252e fld fa0,200(sp) - 20cc: 0012 c.slli zero,0x4 - 20ce: 1900 addi s0,sp,176 - 20d0: 0015 c.nop 5 - 20d2: 2e00 fld fs0,24(a2) - 20d4: 1232 slli tp,tp,0x2c - 20d6: 0000 unimp - 20d8: 154c addi a1,sp,676 - 20da: 0000 unimp - 20dc: 3f32 fld ft10,296(sp) - 20de: 0012 c.slli zero,0x4 - 20e0: 0100 addi s0,sp,128 - 20e2: 0060 addi s0,sp,12 - 20e4: 4d30 lw a2,88(a0) - 20e6: 0012 c.slli zero,0x4 - 20e8: b000 fsd fs0,32(s0) - 20ea: 14800107 0x14800107 - 20ee: 0000 unimp - 20f0: e500 fsw fs0,8(a0) - 20f2: 000e c.slli zero,0x3 - 20f4: 2e00 fld fs0,24(a2) - 20f6: 1252 slli tp,tp,0x34 - 20f8: 0000 unimp - 20fa: 155f 0000 3100 0x31000000155f - 2100: 1260 addi s0,sp,300 - 2102: 0000 unimp - 2104: 07c4 addi s1,sp,964 - 2106: 8001 c.srli64 s0 - 2108: 0010 0x10 - 210a: 0000 unimp - 210c: 612e flw ft2,200(sp) - 210e: 0012 c.slli zero,0x4 - 2110: 7200 flw fs0,32(a2) - 2112: 0015 c.nop 5 - 2114: 0000 unimp - 2116: 0000 unimp - 2118: 0000 unimp - 211a: 00061133 sll sp,a2,zero - 211e: 0100 addi s0,sp,128 - 2120: 090103f7 0x90103f7 - 2124: 0300000b 0x300000b - 2128: 1271 addi tp,tp,-4 - 212a: 0000 unimp - 212c: 6e34 flw fa3,88(a2) - 212e: 0100 addi s0,sp,128 - 2130: 091703f7 0x91703f7 - 2134: 3400000b 0x3400000b - 2138: 0064 addi s1,sp,12 - 213a: f701 bnez a4,2042 <_start-0x7fffdfbe> - 213c: 0b092203 lw tp,176(s2) # 55826 <_start-0x7ffaa7da> - 2140: 0000 unimp - 2142: 7234 flw fa3,96(a2) - 2144: 0070 addi a2,sp,12 - 2146: f701 bnez a4,204e <_start-0x7fffdfb2> - 2148: 12712e03 lw t3,295(sp) # 30b1 <_start-0x7fffcf4f> - 214c: 0000 unimp - 214e: 6e35 lui t3,0xd - 2150: 006e c.slli zero,0x1b - 2152: f901 bnez a0,2062 <_start-0x7fffdf9e> - 2154: 0b921103 lh sp,185(tp) # 47bdb <_start-0x7ffb8425> - 2158: 0000 unimp - 215a: 6435 lui s0,0xd - 215c: 0064 addi s1,sp,12 - 215e: fa01 bnez a2,206e <_start-0x7fffdf92> - 2160: 0b921103 lh sp,185(tp) # b9 <_start-0x7fffff47> - 2164: 0000 unimp - 2166: 7235 lui tp,0xfffed - 2168: 0072 c.slli zero,0x1c - 216a: fb01 bnez a4,207a <_start-0x7fffdf86> - 216c: 0b850b03 lb s6,184(a0) # c0b8 <_start-0x7fff3f48> - 2170: 0000 unimp - 2172: 6435 lui s0,0xd - 2174: 0030 addi a2,sp,8 - 2176: fc01 bnez s0,208e <_start-0x7fffdf72> - 2178: 0af10a03 lb s4,175(sp) - 217c: 0000 unimp - 217e: 6435 lui s0,0xd - 2180: 0031 c.nop 12 - 2182: fc01 bnez s0,209a <_start-0x7fffdf66> - 2184: 0af10e03 lb t3,175(sp) - 2188: 0000 unimp - 218a: 6e35 lui t3,0xd - 218c: 0030 addi a2,sp,8 - 218e: fc01 bnez s0,20a6 <_start-0x7fffdf5a> - 2190: 0af11203 lh tp,175(sp) - 2194: 0000 unimp - 2196: 6e35 lui t3,0xd - 2198: 0031 c.nop 12 - 219a: fc01 bnez s0,20b2 <_start-0x7fffdf4e> - 219c: 0af11603 lh a2,175(sp) - 21a0: 0000 unimp - 21a2: 6e35 lui t3,0xd - 21a4: 0032 c.slli zero,0xc - 21a6: fc01 bnez s0,20be <_start-0x7fffdf42> - 21a8: 0af11a03 lh s4,175(sp) - 21ac: 0000 unimp - 21ae: 7135 addi sp,sp,-160 - 21b0: 0030 addi a2,sp,8 - 21b2: fd01 bnez a0,20ca <_start-0x7fffdf36> - 21b4: 0af10a03 lb s4,175(sp) - 21b8: 0000 unimp - 21ba: 7135 addi sp,sp,-160 - 21bc: 0031 c.nop 12 - 21be: fd01 bnez a0,20d6 <_start-0x7fffdf2a> - 21c0: 0af10e03 lb t3,175(sp) - 21c4: 0000 unimp - 21c6: 6235 lui tp,0xd - 21c8: 0100 addi s0,sp,128 - 21ca: 03fe slli t2,t2,0x1f - 21cc: f10a fsw ft2,160(sp) - 21ce: 000a c.slli zero,0x2 - 21d0: 3500 fld fs0,40(a0) - 21d2: 6d62 flw fs10,24(sp) - 21d4: 0100 addi s0,sp,128 - 21d6: 03fe slli t2,t2,0x1f - 21d8: f10d bnez a0,20fa <_start-0x7fffdf06> - 21da: 000a c.slli zero,0x2 - 21dc: 3500 fld fs0,40(a0) - 21de: 01007777 0x1007777 - 21e2: 921104c7 fmsub.d fs1,ft2,ft1,fs2,rne - 21e6: 3600000b 0x3600000b - 21ea: 00000fef jal t6,21ea <_start-0x7fffde16> - 21ee: 00069237 lui tp,0x69 - 21f2: 0100 addi s0,sp,128 - 21f4: 042e slli s0,s0,0xb - 21f6: f104 fsw fs1,32(a0) - 21f8: 000a c.slli zero,0x2 - 21fa: 3500 fld fs0,40(a0) - 21fc: 5f5f 0061 2e01 0x2e0100615f5f - 2202: 0404 addi s1,sp,512 - 2204: 0af1 addi s5,s5,28 - 2206: 0000 unimp - 2208: 3600 fld fs0,40(a2) - 220a: 1050 addi a2,sp,36 - 220c: 0000 unimp - 220e: 00008037 lui zero,0x8 - 2212: 0100 addi s0,sp,128 - 2214: 043a slli s0,s0,0xe - 2216: f104 fsw fs1,32(a0) - 2218: 000a c.slli zero,0x2 - 221a: 3700 fld fs0,40(a4) - 221c: 0000007b 0x7b - 2220: 3a01 jal 1b30 <_start-0x7fffe4d0> - 2222: 0404 addi s1,sp,512 - 2224: 0af1 addi s5,s5,28 - 2226: 0000 unimp - 2228: 00064537 lui a0,0x64 - 222c: 0100 addi s0,sp,128 - 222e: 043a slli s0,s0,0xe - 2230: f104 fsw fs1,32(a0) - 2232: 000a c.slli zero,0x2 - 2234: 3700 fld fs0,40(a4) - 2236: 0640 addi s0,sp,772 - 2238: 0000 unimp - 223a: 3a01 jal 1b4a <_start-0x7fffe4b6> - 223c: 0404 addi s1,sp,512 - 223e: 0af1 addi s5,s5,28 - 2240: 0000 unimp - 2242: 00071037 lui zero,0x71 - 2246: 0100 addi s0,sp,128 - 2248: 043a slli s0,s0,0xe - 224a: f104 fsw fs1,32(a0) - 224c: 000a c.slli zero,0x2 - 224e: 3700 fld fs0,40(a4) - 2250: 0000070b 0x70b - 2254: 3a01 jal 1b64 <_start-0x7fffe49c> - 2256: 0404 addi s1,sp,512 - 2258: 0af1 addi s5,s5,28 - 225a: 0000 unimp - 225c: 5f35 li t5,-19 - 225e: 6d5f 0100 043a 0x43a01006d5f - 2264: f104 fsw fs1,32(a0) - 2266: 000a c.slli zero,0x2 - 2268: 0000 unimp - 226a: 7036 flw ft0,108(sp) - 226c: 0010 0x10 - 226e: 3700 fld fs0,40(a4) - 2270: 0692 slli a3,a3,0x4 - 2272: 0000 unimp - 2274: 4601 li a2,0 - 2276: 0404 addi s1,sp,512 - 2278: 0af1 addi s5,s5,28 - 227a: 0000 unimp - 227c: 5f35 li t5,-19 - 227e: 615f 0100 0446 0x4460100615f - 2284: f104 fsw fs1,32(a0) - 2286: 000a c.slli zero,0x2 - 2288: 0000 unimp - 228a: d136 sw a3,160(sp) - 228c: 0010 0x10 - 228e: 3700 fld fs0,40(a4) - 2290: 0080 addi s0,sp,64 - 2292: 0000 unimp - 2294: 5f01 li t5,-32 - 2296: 0804 addi s1,sp,16 - 2298: 0af1 addi s5,s5,28 - 229a: 0000 unimp - 229c: 00007b37 lui s6,0x7 - 22a0: 0100 addi s0,sp,128 - 22a2: 045f f108 000a 0xaf108045f - 22a8: 3700 fld fs0,40(a4) - 22aa: 0645 addi a2,a2,17 - 22ac: 0000 unimp - 22ae: 5f01 li t5,-32 - 22b0: 0804 addi s1,sp,16 - 22b2: 0af1 addi s5,s5,28 - 22b4: 0000 unimp - 22b6: 00064037 lui zero,0x64 - 22ba: 0100 addi s0,sp,128 - 22bc: 045f f108 000a 0xaf108045f - 22c2: 3700 fld fs0,40(a4) - 22c4: 0710 addi a2,sp,896 - 22c6: 0000 unimp - 22c8: 5f01 li t5,-32 - 22ca: 0804 addi s1,sp,16 - 22cc: 0af1 addi s5,s5,28 - 22ce: 0000 unimp - 22d0: 00070b37 lui s6,0x70 - 22d4: 0100 addi s0,sp,128 - 22d6: 045f f108 000a 0xaf108045f - 22dc: 3500 fld fs0,40(a0) - 22de: 5f5f 006d 5f01 0x5f01006d5f5f - 22e4: 0804 addi s1,sp,16 - 22e6: 0af1 addi s5,s5,28 - 22e8: 0000 unimp - 22ea: 3600 fld fs0,40(a2) - 22ec: 1132 slli sp,sp,0x2c - 22ee: 0000 unimp - 22f0: 00008037 lui zero,0x8 - 22f4: 0100 addi s0,sp,128 - 22f6: 0464 addi s1,sp,524 - 22f8: f104 fsw fs1,32(a0) - 22fa: 000a c.slli zero,0x2 - 22fc: 3700 fld fs0,40(a4) - 22fe: 0000007b 0x7b - 2302: 6401 0x6401 - 2304: 0404 addi s1,sp,512 - 2306: 0af1 addi s5,s5,28 - 2308: 0000 unimp - 230a: 00064537 lui a0,0x64 - 230e: 0100 addi s0,sp,128 - 2310: 0464 addi s1,sp,524 - 2312: f104 fsw fs1,32(a0) - 2314: 000a c.slli zero,0x2 - 2316: 3700 fld fs0,40(a4) - 2318: 0640 addi s0,sp,772 - 231a: 0000 unimp - 231c: 6401 0x6401 - 231e: 0404 addi s1,sp,512 - 2320: 0af1 addi s5,s5,28 - 2322: 0000 unimp - 2324: 00071037 lui zero,0x71 - 2328: 0100 addi s0,sp,128 - 232a: 0464 addi s1,sp,524 - 232c: f104 fsw fs1,32(a0) - 232e: 000a c.slli zero,0x2 - 2330: 3700 fld fs0,40(a4) - 2332: 0000070b 0x70b - 2336: 6401 0x6401 - 2338: 0404 addi s1,sp,512 - 233a: 0af1 addi s5,s5,28 - 233c: 0000 unimp - 233e: 5f35 li t5,-19 - 2340: 6d5f 0100 0464 0x46401006d5f - 2346: f104 fsw fs1,32(a0) - 2348: 000a c.slli zero,0x2 - 234a: 0000 unimp - 234c: 5236 lw tp,108(sp) - 234e: 0011 c.nop 4 - 2350: 3700 fld fs0,40(a4) - 2352: 0692 slli a3,a3,0x4 - 2354: 0000 unimp - 2356: 8701 c.srai64 a4 - 2358: 0404 addi s1,sp,512 - 235a: 0af1 addi s5,s5,28 - 235c: 0000 unimp - 235e: 5f35 li t5,-19 - 2360: 615f 0100 0487 0x4870100615f - 2366: f104 fsw fs1,32(a0) - 2368: 000a c.slli zero,0x2 - 236a: 0000 unimp - 236c: 6536 flw fa0,76(sp) - 236e: 0011 c.nop 4 - 2370: 3500 fld fs0,40(a0) - 2372: 5f5f 0078 9501 0x950100785f5f - 2378: 0504 addi s1,sp,640 - 237a: 0af1 addi s5,s5,28 - 237c: 0000 unimp - 237e: 3800 fld fs0,48(s0) - 2380: 6d35 lui s10,0xd - 2382: 0031 c.nop 12 - 2384: a501 j 2984 <_start-0x7fffd67c> - 2386: 0f04 addi s1,sp,912 - 2388: 0af1 addi s5,s5,28 - 238a: 0000 unimp - 238c: 6d35 lui s10,0xd - 238e: 0030 addi a2,sp,8 - 2390: a501 j 2990 <_start-0x7fffd670> - 2392: 1304 addi s1,sp,416 - 2394: 0af1 addi s5,s5,28 - 2396: 0000 unimp - 2398: df36 sw a3,188(sp) - 239a: 0011 c.nop 4 - 239c: 3700 fld fs0,40(a4) - 239e: 0080 addi s0,sp,64 - 23a0: 0000 unimp - 23a2: b001 j 1ba2 <_start-0x7fffe45e> - 23a4: 0804 addi s1,sp,16 - 23a6: 0af1 addi s5,s5,28 - 23a8: 0000 unimp - 23aa: 00007b37 lui s6,0x7 - 23ae: 0100 addi s0,sp,128 - 23b0: 04b0 addi a2,sp,584 - 23b2: f108 fsw fa0,32(a0) - 23b4: 000a c.slli zero,0x2 - 23b6: 3700 fld fs0,40(a4) - 23b8: 0645 addi a2,a2,17 - 23ba: 0000 unimp - 23bc: b001 j 1bbc <_start-0x7fffe444> - 23be: 0804 addi s1,sp,16 - 23c0: 0af1 addi s5,s5,28 - 23c2: 0000 unimp - 23c4: 00064037 lui zero,0x64 - 23c8: 0100 addi s0,sp,128 - 23ca: 04b0 addi a2,sp,584 - 23cc: f108 fsw fa0,32(a0) - 23ce: 000a c.slli zero,0x2 - 23d0: 3700 fld fs0,40(a4) - 23d2: 0710 addi a2,sp,896 - 23d4: 0000 unimp - 23d6: b001 j 1bd6 <_start-0x7fffe42a> - 23d8: 0804 addi s1,sp,16 - 23da: 0af1 addi s5,s5,28 - 23dc: 0000 unimp - 23de: 00070b37 lui s6,0x70 - 23e2: 0100 addi s0,sp,128 - 23e4: 04b0 addi a2,sp,584 - 23e6: f108 fsw fa0,32(a0) - 23e8: 000a c.slli zero,0x2 - 23ea: 3500 fld fs0,40(a0) - 23ec: 5f5f 006d b001 0xb001006d5f5f - 23f2: 0804 addi s1,sp,16 - 23f4: 0af1 addi s5,s5,28 - 23f6: 0000 unimp - 23f8: 3600 fld fs0,40(a2) - 23fa: 124d addi tp,tp,-13 - 23fc: 0000 unimp - 23fe: 0005d837 lui a6,0x5d - 2402: 0100 addi s0,sp,128 - 2404: 04b1 addi s1,s1,12 - 2406: f108 fsw fa0,32(a0) - 2408: 000a c.slli zero,0x2 - 240a: 3700 fld fs0,40(a4) - 240c: 05dd addi a1,a1,23 - 240e: 0000 unimp - 2410: b101 j 2010 <_start-0x7fffdff0> - 2412: 0804 addi s1,sp,16 - 2414: 0af1 addi s5,s5,28 - 2416: 0000 unimp - 2418: 0005e237 lui tp,0x5e - 241c: 0100 addi s0,sp,128 - 241e: 04b1 addi s1,s1,12 - 2420: f108 fsw fa0,32(a0) - 2422: 000a c.slli zero,0x2 - 2424: 3700 fld fs0,40(a4) - 2426: 000005e7 jalr a1,zero # 0 <_start-0x80000000> - 242a: b101 j 202a <_start-0x7fffdfd6> - 242c: 0804 addi s1,sp,16 - 242e: 0af1 addi s5,s5,28 - 2430: 0000 unimp - 2432: 00040737 lui a4,0x40 - 2436: 0100 addi s0,sp,128 - 2438: 04b1 addi s1,s1,12 - 243a: f108 fsw fa0,32(a0) - 243c: 000a c.slli zero,0x2 - 243e: 3700 fld fs0,40(a4) - 2440: 04bd addi s1,s1,15 - 2442: 0000 unimp - 2444: b101 j 2044 <_start-0x7fffdfbc> - 2446: 0804 addi s1,sp,16 - 2448: 0af1 addi s5,s5,28 - 244a: 0000 unimp - 244c: 0003f137 lui sp,0x3f - 2450: 0100 addi s0,sp,128 - 2452: 04b1 addi s1,s1,12 - 2454: f108 fsw fa0,32(a0) - 2456: 000a c.slli zero,0x2 - 2458: 3700 fld fs0,40(a4) - 245a: 04b8 addi a4,sp,584 - 245c: 0000 unimp - 245e: b101 j 205e <_start-0x7fffdfa2> - 2460: 0804 addi s1,sp,16 - 2462: 0af1 addi s5,s5,28 - 2464: 0000 unimp - 2466: 3600 fld fs0,40(a2) - 2468: 1260 addi s0,sp,300 - 246a: 0000 unimp - 246c: 5f35 li t5,-19 - 246e: 785f 0100 04b6 0x4b60100785f - 2474: f105 bnez a0,2394 <_start-0x7fffdc6c> - 2476: 000a c.slli zero,0x2 - 2478: 0000 unimp - 247a: 3538 fld fa4,104(a0) - 247c: 5f5f 0078 be01 0xbe0100785f5f - 2482: 0504 addi s1,sp,640 - 2484: 0af1 addi s5,s5,28 - 2486: 0000 unimp - 2488: 0000 unimp - 248a: 0f00 addi s0,sp,912 - 248c: 0904 addi s1,sp,144 - 248e: 0000000b 0xb - 2492: 0730 addi a2,sp,904 - 2494: 0000 unimp - 2496: 0004 0x4 - 2498: 05b4 addi a3,sp,712 - 249a: 0000 unimp - 249c: 0104 addi s1,sp,128 - 249e: 07f2 slli a5,a5,0x1c - 24a0: 0000 unimp - 24a2: f70c fsw fa1,40(a4) - 24a4: 0009 c.nop 2 - 24a6: fc00 fsw fs0,56(s0) - 24a8: 0002 c.slli64 zero - 24aa: e800 fsw fs0,16(s0) - 24ac: c8800107 vlsseg7bu.v v2,(zero),s0,v0.t - 24b0: 0006 c.slli zero,0x1 - 24b2: 6c00 flw fs0,24(s0) - 24b4: 0012 c.slli zero,0x4 - 24b6: 0200 addi s0,sp,256 - 24b8: 0408 addi a0,sp,512 - 24ba: 00a2 slli ra,ra,0x8 - 24bc: 0000 unimp - 24be: 69050403 lb s0,1680(a0) # 64690 <_start-0x7ff9b970> - 24c2: 746e flw fs0,248(sp) - 24c4: 0200 addi s0,sp,256 - 24c6: 0601 addi a2,a2,0 - 24c8: 0669 addi a2,a2,26 - 24ca: 0000 unimp - 24cc: 0802 c.slli64 a6 - 24ce: 1d05 addi s10,s10,-31 - 24d0: 0002 c.slli64 zero - 24d2: 0400 addi s0,sp,512 - 24d4: 00000773 0x773 - 24d8: 4a02 lw s4,0(sp) - 24da: 1601 addi a2,a2,-32 - 24dc: 00000053 fadd.s ft0,ft0,ft0,rne - 24e0: 4105 li sp,1 - 24e2: 0000 unimp - 24e4: 0200 addi s0,sp,256 - 24e6: 0801 addi a6,a6,0 - 24e8: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 24ec: 0402 c.slli64 s0 - 24ee: 00036e07 vlwu.v v28,(t1),v0.t - 24f2: 0200 addi s0,sp,256 - 24f4: 0708 addi a0,sp,896 - 24f6: 0364 addi s1,sp,396 - 24f8: 0000 unimp - 24fa: 9c04 0x9c04 - 24fc: 0008 0x8 - 24fe: 0200 addi s0,sp,256 - 2500: 014e slli sp,sp,0x13 - 2502: 7516 flw fa0,100(sp) - 2504: 0000 unimp - 2506: 0200 addi s0,sp,256 - 2508: 0702 c.slli64 a4 - 250a: 0384 addi s1,sp,448 - 250c: 0000 unimp - 250e: 4e06 lw t3,64(sp) - 2510: 0000 unimp - 2512: 8c00 0x8c00 - 2514: 0000 unimp - 2516: 0700 addi s0,sp,896 - 2518: 005a c.slli zero,0x16 - 251a: 0000 unimp - 251c: 00ff 0xff - 251e: 7c05 lui s8,0xfffe1 - 2520: 0000 unimp - 2522: 0800 addi s0,sp,16 - 2524: 00000397 auipc t2,0x0 - 2528: 3c04 fld fs1,56(s0) - 252a: 8c16 mv s8,t0 - 252c: 0000 unimp - 252e: 0900 addi s0,sp,144 - 2530: 08dc addi a5,sp,84 - 2532: 0000 unimp - 2534: 250f4803 lbu a6,592(t5) # 1cbe8 <_start-0x7ffe3418> - 2538: 0000 unimp - 253a: 0a00 addi s0,sp,272 - 253c: 0308 addi a0,sp,384 - 253e: 00f3034f fnmadd.s ft6,ft6,fa5,ft0,rne - 2542: 0000 unimp - 2544: 0008bd0b 0x8bd0b - 2548: 0300 addi s0,sp,384 - 254a: 005a0e57 vadd.vv v28,v5,v20,v0.t - 254e: 0000 unimp - 2550: 2004 fld fs1,0(s0) - 2552: 0000 unimp - 2554: 0008c30b 0x8c30b - 2558: 0300 addi s0,sp,384 - 255a: 0e58 addi a4,sp,788 - 255c: 005a c.slli zero,0x16 - 255e: 0000 unimp - 2560: 1404 addi s1,sp,544 - 2562: 040c addi a1,sp,512 - 2564: 650c flw fa1,8(a0) - 2566: 7078 flw fa4,100(s0) - 2568: 0300 addi s0,sp,384 - 256a: 0e59 addi t3,t3,22 - 256c: 005a c.slli zero,0x16 - 256e: 0000 unimp - 2570: 0b04 addi s1,sp,400 - 2572: 0401 addi s0,s0,0 - 2574: 00027a0b 0x27a0b - 2578: 0300 addi s0,sp,384 - 257a: 0e5a slli t3,t3,0x16 - 257c: 005a c.slli zero,0x16 - 257e: 0000 unimp - 2580: 0104 addi s1,sp,128 - 2582: 0400 addi s0,sp,512 - 2584: 0d00 addi s0,sp,656 - 2586: 0a25 addi s4,s4,9 - 2588: 0000 unimp - 258a: 0308 addi a0,sp,384 - 258c: 074c addi a1,sp,900 - 258e: 0119 addi sp,sp,6 - 2590: 0000 unimp - 2592: 660e flw fa2,192(sp) - 2594: 746c flw fa1,108(s0) - 2596: 0300 addi s0,sp,384 - 2598: 0a4e slli s4,s4,0x13 - 259a: 009d addi ra,ra,7 - 259c: 0000 unimp - 259e: 000a480f 0xa480f - 25a2: 0300 addi s0,sp,384 - 25a4: 055c addi a5,sp,644 - 25a6: 00a9 addi ra,ra,10 - 25a8: 0000 unimp - 25aa: 1000 addi s0,sp,32 - 25ac: 00000893 li a7,0 - 25b0: 2301 jal 2ab0 <_start-0x7fffd550> - 25b2: 9d01 0x9d01 - 25b4: 0000 unimp - 25b6: e800 fsw fs0,16(s0) - 25b8: c8800107 vlsseg7bu.v v2,(zero),s0,v0.t - 25bc: 0006 c.slli zero,0x1 - 25be: 0100 addi s0,sp,128 - 25c0: 259c fld fa5,8(a1) - 25c2: 11000007 vlbff.v v0,(zero),v0.t - 25c6: 0061 c.nop 24 - 25c8: 2301 jal 2ac8 <_start-0x7fffd538> - 25ca: 9d12 add s10,s10,tp - 25cc: 0000 unimp - 25ce: 8500 0x8500 - 25d0: 0015 c.nop 5 - 25d2: 1100 addi s0,sp,160 - 25d4: 0062 c.slli zero,0x18 - 25d6: 2301 jal 2ad6 <_start-0x7fffd52a> - 25d8: 9d1c 0x9d1c - 25da: 0000 unimp - 25dc: 0d00 addi s0,sp,656 - 25de: 0016 c.slli zero,0x5 - 25e0: 1200 addi s0,sp,288 - 25e2: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 25e6: 2501 jal 2be6 <_start-0x7fffd41a> - 25e8: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> - 25ec: 9500 0x9500 - 25ee: 0016 c.slli zero,0x5 - 25f0: 1300 addi s0,sp,416 - 25f2: 0a4d addi s4,s4,19 - 25f4: 0000 unimp - 25f6: 2501 jal 2bf6 <_start-0x7fffd40a> - 25f8: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> - 25fc: 0000 unimp - 25fe: 4114 lw a3,0(a0) - 2600: 635f 0100 0326 0x3260100635f - 2606: 0725 addi a4,a4,9 - 2608: 0000 unimp - 260a: 16b5 addi a3,a3,-19 - 260c: 0000 unimp - 260e: 4114 lw a3,0(a0) - 2610: 735f 0100 0326 0x3260100735f - 2616: 0725 addi a4,a4,9 - 2618: 0000 unimp - 261a: 16ea slli a3,a3,0x3a - 261c: 0000 unimp - 261e: 4114 lw a3,0(a0) - 2620: 655f 0100 0326 0x3260100655f - 2626: 0725 addi a4,a4,9 - 2628: 0000 unimp - 262a: 1712 slli a4,a4,0x24 - 262c: 0000 unimp - 262e: e812 fsw ft4,16(sp) - 2630: 0009 c.nop 2 - 2632: 0100 addi s0,sp,128 - 2634: 0326 slli t1,t1,0x9 - 2636: 072c addi a1,sp,904 - 2638: 0000 unimp - 263a: 177f 0x177f - 263c: 0000 unimp - 263e: 4a12 lw s4,4(sp) - 2640: 0009 c.nop 2 - 2642: 0100 addi s0,sp,128 - 2644: 0326 slli t1,t1,0x9 - 2646: 072c addi a1,sp,904 - 2648: 0000 unimp - 264a: 00001817 auipc a6,0x1 - 264e: 4214 lw a3,0(a2) - 2650: 635f 0100 0327 0x3270100635f - 2656: 0725 addi a4,a4,9 - 2658: 0000 unimp - 265a: 18be slli a7,a7,0x2f - 265c: 0000 unimp - 265e: 4214 lw a3,0(a2) - 2660: 735f 0100 0327 0x3270100735f - 2666: 0725 addi a4,a4,9 - 2668: 0000 unimp - 266a: 1909 addi s2,s2,-30 - 266c: 0000 unimp - 266e: 4214 lw a3,0(a2) - 2670: 655f 0100 0327 0x3270100655f - 2676: 0725 addi a4,a4,9 - 2678: 0000 unimp - 267a: 1941 addi s2,s2,-16 - 267c: 0000 unimp - 267e: ed12 fsw ft4,152(sp) - 2680: 0009 c.nop 2 - 2682: 0100 addi s0,sp,128 - 2684: 072c0327 0x72c0327 - 2688: 0000 unimp - 268a: 19c4 addi s1,sp,244 - 268c: 0000 unimp - 268e: f212 fsw ft4,36(sp) - 2690: 0009 c.nop 2 - 2692: 0100 addi s0,sp,128 - 2694: 072c0327 0x72c0327 - 2698: 0000 unimp - 269a: 1a51 addi s4,s4,-12 - 269c: 0000 unimp - 269e: 5214 lw a3,32(a2) - 26a0: 635f 0100 0328 0x3280100635f - 26a6: 0725 addi a4,a4,9 - 26a8: 0000 unimp - 26aa: 00001ae3 bnez zero,2ebe <_start-0x7fffd142> - 26ae: 5214 lw a3,32(a2) - 26b0: 735f 0100 0328 0x3280100735f - 26b6: 0725 addi a4,a4,9 - 26b8: 0000 unimp - 26ba: 1b30 addi a2,sp,440 - 26bc: 0000 unimp - 26be: 5214 lw a3,32(a2) - 26c0: 655f 0100 0328 0x3280100655f - 26c6: 0725 addi a4,a4,9 - 26c8: 0000 unimp - 26ca: 1bb5 addi s7,s7,-19 - 26cc: 0000 unimp - 26ce: 3012 fld ft0,288(sp) - 26d0: 0009 c.nop 2 - 26d2: 0100 addi s0,sp,128 - 26d4: 0328 addi a0,sp,392 - 26d6: 072c addi a1,sp,904 - 26d8: 0000 unimp - 26da: 00001c37 lui s8,0x1 - 26de: 5212 lw tp,36(sp) - 26e0: 000a c.slli zero,0x2 - 26e2: 0100 addi s0,sp,128 - 26e4: 0328 addi a0,sp,392 - 26e6: 072c addi a1,sp,904 - 26e8: 0000 unimp - 26ea: 00001d67 0x1d67 - 26ee: 7215 lui tp,0xfffe5 - 26f0: 0100 addi s0,sp,128 - 26f2: 0a29 addi s4,s4,10 - 26f4: 009d addi ra,ra,7 - 26f6: 0000 unimp - 26f8: d016 sw t0,32(sp) - 26fa: 0001 nop - 26fc: 7c00 flw fs0,56(s0) - 26fe: 0002 c.slli64 zero - 2700: 1700 addi s0,sp,928 - 2702: 0935 addi s2,s2,13 - 2704: 0000 unimp - 2706: 2c01 jal 2916 <_start-0x7fffd6ea> - 2708: 0000f303 0xf303 - 270c: 0000 unimp - 270e: 1016 c.slli zero,0x25 - 2710: 0002 c.slli64 zero - 2712: 9600 0x9600 - 2714: 0002 c.slli64 zero - 2716: 1200 addi s0,sp,288 - 2718: 000008e3 beqz zero,2f28 <_start-0x7fffd0d8> - 271c: 2c01 jal 292c <_start-0x7fffd6d4> - 271e: 00072503 lw a0,0(a4) # 40000 <_start-0x7ffc0000> - 2722: 1900 addi s0,sp,176 - 2724: 001e c.slli zero,0x7 - 2726: 0000 unimp - 2728: 2816 fld fa6,320(sp) - 272a: 0002 c.slli64 zero - 272c: ac00 fsd fs0,24(s0) - 272e: 0002 c.slli64 zero - 2730: 1700 addi s0,sp,928 - 2732: 0935 addi s2,s2,13 - 2734: 0000 unimp - 2736: 2d01 jal 2d46 <_start-0x7fffd2ba> - 2738: 0000f303 0xf303 - 273c: 0000 unimp - 273e: 4016 0x4016 - 2740: 0002 c.slli64 zero - 2742: c600 sw s0,8(a2) - 2744: 0002 c.slli64 zero - 2746: 1200 addi s0,sp,288 - 2748: 000008e3 beqz zero,2f58 <_start-0x7fffd0a8> - 274c: 2d01 jal 2d5c <_start-0x7fffd2a4> - 274e: 00072503 lw a0,0(a4) - 2752: 4d00 lw s0,24(a0) - 2754: 001e c.slli zero,0x7 - 2756: 0000 unimp - 2758: 5816 lw a6,100(sp) - 275a: 0002 c.slli64 zero - 275c: d200 sw s0,32(a2) - 275e: 0005 c.nop 1 - 2760: 1200 addi s0,sp,288 - 2762: 0986 slli s3,s3,0x1 - 2764: 0000 unimp - 2766: 2e01 jal 2a76 <_start-0x7fffd58a> - 2768: 00072c03 lw s8,0(a4) - 276c: 8100 0x8100 - 276e: 001e c.slli zero,0x7 - 2770: 1200 addi s0,sp,288 - 2772: 096d addi s2,s2,27 - 2774: 0000 unimp - 2776: 2e01 jal 2a86 <_start-0x7fffd57a> - 2778: 00072c03 lw s8,0(a4) - 277c: ae00 fsd fs0,24(a2) - 277e: 001e c.slli zero,0x7 - 2780: 1200 addi s0,sp,288 - 2782: 0954 addi a3,sp,148 - 2784: 0000 unimp - 2786: 2e01 jal 2a96 <_start-0x7fffd56a> - 2788: 00072c03 lw s8,0(a4) - 278c: dc00 sw s0,56(s0) - 278e: 001e c.slli zero,0x7 - 2790: 1200 addi s0,sp,288 - 2792: 00000917 auipc s2,0x0 - 2796: 2e01 jal 2aa6 <_start-0x7fffd55a> - 2798: 00072c03 lw s8,0(a4) - 279c: fb00 fsw fs0,48(a4) - 279e: 001e c.slli zero,0x7 - 27a0: 1200 addi s0,sp,288 - 27a2: 08fe slli a7,a7,0x1f - 27a4: 0000 unimp - 27a6: 2e01 jal 2ab6 <_start-0x7fffd54a> - 27a8: 00072c03 lw s8,0(a4) - 27ac: 5000 lw s0,32(s0) - 27ae: 001f 1200 08a4 0x8a41200001f - 27b4: 0000 unimp - 27b6: 2e01 jal 2ac6 <_start-0x7fffd53a> - 27b8: 00072c03 lw s8,0(a4) - 27bc: bc00 fsd fs0,56(s0) - 27be: 001f 1200 07d9 0x7d91200001f - 27c4: 0000 unimp - 27c6: 2e01 jal 2ad6 <_start-0x7fffd52a> - 27c8: 00072c03 lw s8,0(a4) - 27cc: e500 fsw fs0,8(a0) - 27ce: 001f 1600 0278 0x2781600001f - 27d4: 0000 unimp - 27d6: 03b9 addi t2,t2,14 - 27d8: 0000 unimp - 27da: 8012 c.mv zero,tp - 27dc: 0000 unimp - 27de: 0100 addi s0,sp,128 - 27e0: 032e slli t1,t1,0xb - 27e2: 072c addi a1,sp,904 - 27e4: 0000 unimp - 27e6: 20a6 fld ft1,72(sp) - 27e8: 0000 unimp - 27ea: 7b12 flw fs6,36(sp) - 27ec: 0000 unimp - 27ee: 0100 addi s0,sp,128 - 27f0: 032e slli t1,t1,0xb - 27f2: 072c addi a1,sp,904 - 27f4: 0000 unimp - 27f6: 000020d7 vredsum.vs v1,v0,v0,v0.t - 27fa: 4512 lw a0,4(sp) - 27fc: 0006 c.slli zero,0x1 - 27fe: 0100 addi s0,sp,128 - 2800: 032e slli t1,t1,0xb - 2802: 072c addi a1,sp,904 - 2804: 0000 unimp - 2806: 210c fld fa1,0(a0) - 2808: 0000 unimp - 280a: 4012 0x4012 - 280c: 0006 c.slli zero,0x1 - 280e: 0100 addi s0,sp,128 - 2810: 032e slli t1,t1,0xb - 2812: 072c addi a1,sp,904 - 2814: 0000 unimp - 2816: 212a fld ft2,136(sp) - 2818: 0000 unimp - 281a: 1012 c.slli zero,0x24 - 281c: 01000007 vlbuff.v v0,(zero),v0.t - 2820: 032e slli t1,t1,0xb - 2822: 072c addi a1,sp,904 - 2824: 0000 unimp - 2826: 2148 fld fa0,128(a0) - 2828: 0000 unimp - 282a: 0b12 slli s6,s6,0x4 - 282c: 01000007 vlbuff.v v0,(zero),v0.t - 2830: 032e slli t1,t1,0xb - 2832: 072c addi a1,sp,904 - 2834: 0000 unimp - 2836: 00002193 slti gp,zero,0 - 283a: 5f14 lw a3,56(a4) - 283c: 6d5f 0100 032e 0x32e01006d5f - 2842: 072c addi a1,sp,904 - 2844: 0000 unimp - 2846: 000021d7 vredsum.vs v3,v0,v0,v0.t - 284a: 1800 addi s0,sp,48 - 284c: 0ad4 addi a3,sp,340 - 284e: 8001 c.srli64 s0 - 2850: 0058 addi a4,sp,4 - 2852: 0000 unimp - 2854: 00000447 fmsub.s fs0,ft0,ft0,ft0,rne - 2858: d812 sw tp,48(sp) - 285a: 0005 c.nop 1 - 285c: 0100 addi s0,sp,128 - 285e: 032e slli t1,t1,0xb - 2860: 072c addi a1,sp,904 - 2862: 0000 unimp - 2864: 2215 jal 2988 <_start-0x7fffd678> - 2866: 0000 unimp - 2868: dd12 sw tp,184(sp) - 286a: 0005 c.nop 1 - 286c: 0100 addi s0,sp,128 - 286e: 032e slli t1,t1,0xb - 2870: 072c addi a1,sp,904 - 2872: 0000 unimp - 2874: 228d jal 29d6 <_start-0x7fffd62a> - 2876: 0000 unimp - 2878: e212 fsw ft4,4(sp) - 287a: 0005 c.nop 1 - 287c: 0100 addi s0,sp,128 - 287e: 032e slli t1,t1,0xb - 2880: 072c addi a1,sp,904 - 2882: 0000 unimp - 2884: 2369 jal 2e0e <_start-0x7fffd1f2> - 2886: 0000 unimp - 2888: e712 fsw ft4,140(sp) - 288a: 0005 c.nop 1 - 288c: 0100 addi s0,sp,128 - 288e: 032e slli t1,t1,0xb - 2890: 072c addi a1,sp,904 - 2892: 0000 unimp - 2894: 23dc fld fa5,128(a5) - 2896: 0000 unimp - 2898: 0712 slli a4,a4,0x4 - 289a: 0004 0x4 - 289c: 0100 addi s0,sp,128 - 289e: 032e slli t1,t1,0xb - 28a0: 0068 addi a0,sp,12 - 28a2: 0000 unimp - 28a4: 000023ef jal t2,48a4 <_start-0x7fffb75c> - 28a8: bd12 fsd ft4,184(sp) - 28aa: 0004 0x4 - 28ac: 0100 addi s0,sp,128 - 28ae: 032e slli t1,t1,0xb - 28b0: 0068 addi a0,sp,12 - 28b2: 0000 unimp - 28b4: 240d jal 2ad6 <_start-0x7fffd52a> - 28b6: 0000 unimp - 28b8: f112 fsw ft4,160(sp) - 28ba: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 28be: 032e slli t1,t1,0xb - 28c0: 0068 addi a0,sp,12 - 28c2: 0000 unimp - 28c4: 0000242b 0x242b - 28c8: b812 fsd ft4,48(sp) - 28ca: 0004 0x4 - 28cc: 0100 addi s0,sp,128 - 28ce: 032e slli t1,t1,0xb - 28d0: 0068 addi a0,sp,12 - 28d2: 0000 unimp - 28d4: 247a fld fs0,408(sp) - 28d6: 0000 unimp - 28d8: 1600 addi s0,sp,800 - 28da: 0298 addi a4,sp,320 - 28dc: 0000 unimp - 28de: 0461 addi s0,s0,24 - 28e0: 0000 unimp - 28e2: 5f14 lw a3,56(a4) - 28e4: 785f 0100 032e 0x32e0100785f - 28ea: 072c addi a1,sp,904 - 28ec: 0000 unimp - 28ee: 000024ab 0x24ab - 28f2: 1600 addi s0,sp,800 - 28f4: 02b0 addi a2,sp,328 - 28f6: 0000 unimp - 28f8: 0000047b 0x47b - 28fc: 5f14 lw a3,56(a4) - 28fe: 785f 0100 032e 0x32e0100785f - 2904: 072c addi a1,sp,904 - 2906: 0000 unimp - 2908: 24be fld fs1,456(sp) - 290a: 0000 unimp - 290c: 1800 addi s0,sp,48 - 290e: 0b7c addi a5,sp,412 - 2910: 8001 c.srli64 s0 - 2912: 0010 0x10 - 2914: 0000 unimp - 2916: 0499 addi s1,s1,6 - 2918: 0000 unimp - 291a: 5f14 lw a3,56(a4) - 291c: 785f 0100 032e 0x32e0100785f - 2922: 072c addi a1,sp,904 - 2924: 0000 unimp - 2926: 24d1 jal 2bea <_start-0x7fffd416> - 2928: 0000 unimp - 292a: 1600 addi s0,sp,800 - 292c: 02c8 addi a0,sp,324 - 292e: 0000 unimp - 2930: 00000513 li a0,0 - 2934: 8012 c.mv zero,tp - 2936: 0000 unimp - 2938: 0100 addi s0,sp,128 - 293a: 032e slli t1,t1,0xb - 293c: 072c addi a1,sp,904 - 293e: 0000 unimp - 2940: 24e4 fld fs1,200(s1) - 2942: 0000 unimp - 2944: 7b12 flw fs6,36(sp) - 2946: 0000 unimp - 2948: 0100 addi s0,sp,128 - 294a: 032e slli t1,t1,0xb - 294c: 072c addi a1,sp,904 - 294e: 0000 unimp - 2950: 2515 jal 2f74 <_start-0x7fffd08c> - 2952: 0000 unimp - 2954: 4512 lw a0,4(sp) - 2956: 0006 c.slli zero,0x1 - 2958: 0100 addi s0,sp,128 - 295a: 032e slli t1,t1,0xb - 295c: 072c addi a1,sp,904 - 295e: 0000 unimp - 2960: 254a fld fa0,144(sp) - 2962: 0000 unimp - 2964: 4012 0x4012 - 2966: 0006 c.slli zero,0x1 - 2968: 0100 addi s0,sp,128 - 296a: 032e slli t1,t1,0xb - 296c: 072c addi a1,sp,904 - 296e: 0000 unimp - 2970: 2568 fld fa0,200(a0) - 2972: 0000 unimp - 2974: 1012 c.slli zero,0x24 - 2976: 01000007 vlbuff.v v0,(zero),v0.t - 297a: 032e slli t1,t1,0xb - 297c: 072c addi a1,sp,904 - 297e: 0000 unimp - 2980: 2586 fld fa1,64(sp) - 2982: 0000 unimp - 2984: 0b12 slli s6,s6,0x4 - 2986: 01000007 vlbuff.v v0,(zero),v0.t - 298a: 032e slli t1,t1,0xb - 298c: 072c addi a1,sp,904 - 298e: 0000 unimp - 2990: 000025bf 6d5f5f14 0x6d5f5f14000025bf - 2998: 0100 addi s0,sp,128 - 299a: 032e slli t1,t1,0xb - 299c: 072c addi a1,sp,904 - 299e: 0000 unimp - 29a0: 25f8 fld fa4,200(a1) - 29a2: 0000 unimp - 29a4: 1800 addi s0,sp,48 - 29a6: 0c20 addi s0,sp,536 - 29a8: 8001 c.srli64 s0 - 29aa: 004c addi a1,sp,4 - 29ac: 0000 unimp - 29ae: 05a1 addi a1,a1,8 - 29b0: 0000 unimp - 29b2: d812 sw tp,48(sp) - 29b4: 0005 c.nop 1 - 29b6: 0100 addi s0,sp,128 - 29b8: 032e slli t1,t1,0xb - 29ba: 072c addi a1,sp,904 - 29bc: 0000 unimp - 29be: 262a fld fa2,136(sp) - 29c0: 0000 unimp - 29c2: dd12 sw tp,184(sp) - 29c4: 0005 c.nop 1 - 29c6: 0100 addi s0,sp,128 - 29c8: 032e slli t1,t1,0xb - 29ca: 072c addi a1,sp,904 - 29cc: 0000 unimp - 29ce: 0000266b 0x266b - 29d2: e212 fsw ft4,4(sp) - 29d4: 0005 c.nop 1 - 29d6: 0100 addi s0,sp,128 - 29d8: 032e slli t1,t1,0xb - 29da: 072c addi a1,sp,904 - 29dc: 0000 unimp - 29de: 000026db 0x26db - 29e2: e712 fsw ft4,140(sp) - 29e4: 0005 c.nop 1 - 29e6: 0100 addi s0,sp,128 - 29e8: 032e slli t1,t1,0xb - 29ea: 072c addi a1,sp,904 - 29ec: 0000 unimp - 29ee: 2718 fld fa4,8(a4) - 29f0: 0000 unimp - 29f2: 0712 slli a4,a4,0x4 - 29f4: 0004 0x4 - 29f6: 0100 addi s0,sp,128 - 29f8: 032e slli t1,t1,0xb - 29fa: 0068 addi a0,sp,12 - 29fc: 0000 unimp - 29fe: 0000272b 0x272b - 2a02: bd12 fsd ft4,184(sp) - 2a04: 0004 0x4 - 2a06: 0100 addi s0,sp,128 - 2a08: 032e slli t1,t1,0xb - 2a0a: 0068 addi a0,sp,12 - 2a0c: 0000 unimp - 2a0e: 2749 jal 3190 <_start-0x7fffce70> - 2a10: 0000 unimp - 2a12: f112 fsw ft4,160(sp) - 2a14: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 2a18: 032e slli t1,t1,0xb - 2a1a: 0068 addi a0,sp,12 - 2a1c: 0000 unimp - 2a1e: 00002767 0x2767 - 2a22: b812 fsd ft4,48(sp) - 2a24: 0004 0x4 - 2a26: 0100 addi s0,sp,128 - 2a28: 032e slli t1,t1,0xb - 2a2a: 0068 addi a0,sp,12 - 2a2c: 0000 unimp - 2a2e: 2798 fld fa4,8(a5) - 2a30: 0000 unimp - 2a32: 1600 addi s0,sp,800 - 2a34: 02e0 addi s0,sp,332 - 2a36: 0000 unimp - 2a38: 000005bb 0x5bb - 2a3c: 5f14 lw a3,56(a4) - 2a3e: 785f 0100 032e 0x32e0100785f - 2a44: 072c addi a1,sp,904 - 2a46: 0000 unimp - 2a48: 27c9 jal 320a <_start-0x7fffcdf6> - 2a4a: 0000 unimp - 2a4c: 1900 addi s0,sp,176 - 2a4e: 02f8 addi a4,sp,332 - 2a50: 0000 unimp - 2a52: 5f14 lw a3,56(a4) - 2a54: 785f 0100 032e 0x32e0100785f - 2a5a: 072c addi a1,sp,904 - 2a5c: 0000 unimp - 2a5e: 000027e7 0x27e7 - 2a62: 0000 unimp - 2a64: d418 sw a4,40(s0) - 2a66: 010c addi a1,sp,128 - 2a68: 1080 addi s0,sp,96 - 2a6a: 0000 unimp - 2a6c: f000 fsw fs0,32(s0) - 2a6e: 0005 c.nop 1 - 2a70: 1400 addi s0,sp,544 - 2a72: 5f5f 0078 2f01 0x2f0100785f5f - 2a78: 00072c03 lw s8,0(a4) - 2a7c: fa00 fsw fs0,48(a2) - 2a7e: 00000027 vsb.v v0,(zero),v0.t - 2a82: 021a slli tp,tp,0x6 - 2a84: 0006 c.slli zero,0x1 - 2a86: 1500 addi s0,sp,672 - 2a88: 5f5f 0078 2f01 0x2f0100785f5f - 2a8e: 00072c03 lw s8,0(a4) - 2a92: 0000 unimp - 2a94: 141a slli s0,s0,0x26 - 2a96: 0006 c.slli zero,0x1 - 2a98: 1500 addi s0,sp,672 - 2a9a: 5f5f 0078 2f01 0x2f0100785f5f - 2aa0: 00072c03 lw s8,0(a4) - 2aa4: 0000 unimp - 2aa6: 3016 fld ft0,352(sp) - 2aa8: 12000003 lb zero,288(zero) # 120 <_start-0x7ffffee0> - 2aac: 17000007 0x17000007 - 2ab0: 09b6 slli s3,s3,0xd - 2ab2: 0000 unimp - 2ab4: 2f01 jal 31c4 <_start-0x7fffce3c> - 2ab6: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> - 2aba: 1a00 addi s0,sp,304 - 2abc: 069d addi a3,a3,7 - 2abe: 0000 unimp - 2ac0: 0009d117 auipc sp,0x9d - 2ac4: 0100 addi s0,sp,128 - 2ac6: 0725032f 0x725032f - 2aca: 0000 unimp - 2acc: 00099f17 auipc t5,0x99 - 2ad0: 0100 addi s0,sp,128 - 2ad2: 0725032f 0x725032f - 2ad6: 0000 unimp - 2ad8: 000a3117 auipc sp,0xa3 - 2adc: 0100 addi s0,sp,128 - 2ade: 0725032f 0x725032f - 2ae2: 0000 unimp - 2ae4: 0007a917 auipc s2,0x7a - 2ae8: 0100 addi s0,sp,128 - 2aea: 072c032f 0x72c032f - 2aee: 0000 unimp - 2af0: 0007c117 auipc sp,0x7c - 2af4: 0100 addi s0,sp,128 - 2af6: 072c032f 0x72c032f - 2afa: 0000 unimp - 2afc: 7c1a flw fs8,164(sp) - 2afe: 0006 c.slli zero,0x1 - 2b00: 1500 addi s0,sp,672 - 2b02: 5f5f 0078 2f01 0x2f0100785f5f - 2b08: 00072c03 lw s8,0(a4) - 2b0c: 0000 unimp - 2b0e: 8e1a mv t3,t1 - 2b10: 0006 c.slli zero,0x1 - 2b12: 1500 addi s0,sp,672 - 2b14: 5f5f 0078 2f01 0x2f0100785f5f - 2b1a: 00072c03 lw s8,0(a4) - 2b1e: 0000 unimp - 2b20: 5f5f151b 0x5f5f151b - 2b24: 0078 addi a4,sp,12 - 2b26: 2f01 jal 3236 <_start-0x7fffcdca> - 2b28: 00072c03 lw s8,0(a4) - 2b2c: 0000 unimp - 2b2e: 1800 addi s0,sp,48 - 2b30: 0e0c addi a1,sp,784 - 2b32: 8001 c.srli64 s0 - 2b34: 0010 0x10 - 2b36: 0000 unimp - 2b38: 000006bb 0x6bb - 2b3c: 5f14 lw a3,56(a4) - 2b3e: 785f 0100 032f 0x32f0100785f - 2b44: 072c addi a1,sp,904 - 2b46: 0000 unimp - 2b48: 280d jal 2b7a <_start-0x7fffd486> - 2b4a: 0000 unimp - 2b4c: 1a00 addi s0,sp,304 - 2b4e: 06cd addi a3,a3,19 - 2b50: 0000 unimp - 2b52: 5f15 li t5,-27 - 2b54: 785f 0100 032f 0x32f0100785f - 2b5a: 072c addi a1,sp,904 - 2b5c: 0000 unimp - 2b5e: 1a00 addi s0,sp,304 - 2b60: 06df 0000 5f15 0x5f15000006df - 2b66: 785f 0100 032f 0x32f0100785f - 2b6c: 072c addi a1,sp,904 - 2b6e: 0000 unimp - 2b70: 1a00 addi s0,sp,304 - 2b72: 06f1 addi a3,a3,28 - 2b74: 0000 unimp - 2b76: 5f15 li t5,-27 - 2b78: 785f 0100 032f 0x32f0100785f - 2b7e: 072c addi a1,sp,904 - 2b80: 0000 unimp - 2b82: 1a00 addi s0,sp,304 - 2b84: 00000703 lb a4,0(zero) # 0 <_start-0x80000000> - 2b88: 5f15 li t5,-27 - 2b8a: 785f 0100 032f 0x32f0100785f - 2b90: 072c addi a1,sp,904 - 2b92: 0000 unimp - 2b94: 1b00 addi s0,sp,432 - 2b96: 5f15 li t5,-27 - 2b98: 785f 0100 032f 0x32f0100785f - 2b9e: 072c addi a1,sp,904 - 2ba0: 0000 unimp - 2ba2: 0000 unimp - 2ba4: 1819 addi a6,a6,-26 - 2ba6: 17000003 lb zero,368(zero) # 170 <_start-0x7ffffe90> - 2baa: 08c9 addi a7,a7,18 - 2bac: 0000 unimp - 2bae: 2f01 jal 32be <_start-0x7fffcd42> - 2bb0: 0000f303 0xf303 - 2bb4: 0000 unimp - 2bb6: 0200 addi s0,sp,256 - 2bb8: 0504 addi s1,sp,640 - 2bba: 0222 slli tp,tp,0x8 - 2bbc: 0000 unimp - 2bbe: 0402 c.slli64 s0 - 2bc0: 00036907 vlwu.v v18,(t1),v0.t - 2bc4: 0000 unimp - 2bc6: 0768 addi a0,sp,908 - 2bc8: 0000 unimp - 2bca: 0004 0x4 - 2bcc: 0000073b 0x73b - 2bd0: 0104 addi s1,sp,128 - 2bd2: 07f2 slli a5,a5,0x1c - 2bd4: 0000 unimp - 2bd6: 560c lw a1,40(a2) - 2bd8: fc00000b 0xfc00000b - 2bdc: 0002 c.slli64 zero - 2bde: b000 fsd fs0,32(s0) - 2be0: 010e slli sp,sp,0x3 - 2be2: b880 fsd fs0,48(s1) - 2be4: 0005 c.nop 1 - 2be6: 9b00 0x9b00 - 2be8: 0020 addi s0,sp,8 - 2bea: 0200 addi s0,sp,256 - 2bec: 0408 addi a0,sp,512 - 2bee: 00a2 slli ra,ra,0x8 - 2bf0: 0000 unimp - 2bf2: 69050403 lb s0,1680(a0) - 2bf6: 746e flw fs0,248(sp) - 2bf8: 0200 addi s0,sp,256 - 2bfa: 0601 addi a2,a2,0 - 2bfc: 0669 addi a2,a2,26 - 2bfe: 0000 unimp - 2c00: 0802 c.slli64 a6 - 2c02: 1d05 addi s10,s10,-31 - 2c04: 0002 c.slli64 zero - 2c06: 0400 addi s0,sp,512 - 2c08: 00000773 0x773 - 2c0c: 4a02 lw s4,0(sp) - 2c0e: 1601 addi a2,a2,-32 - 2c10: 00000053 fadd.s ft0,ft0,ft0,rne - 2c14: 4105 li sp,1 - 2c16: 0000 unimp - 2c18: 0200 addi s0,sp,256 - 2c1a: 0801 addi a6,a6,0 - 2c1c: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 2c20: 0402 c.slli64 s0 - 2c22: 00036e07 vlwu.v v28,(t1),v0.t - 2c26: 0200 addi s0,sp,256 - 2c28: 0708 addi a0,sp,896 - 2c2a: 0364 addi s1,sp,396 - 2c2c: 0000 unimp - 2c2e: 9c04 0x9c04 - 2c30: 0008 0x8 - 2c32: 0200 addi s0,sp,256 - 2c34: 014e slli sp,sp,0x13 - 2c36: 7516 flw fa0,100(sp) - 2c38: 0000 unimp - 2c3a: 0200 addi s0,sp,256 - 2c3c: 0702 c.slli64 a4 - 2c3e: 0384 addi s1,sp,448 - 2c40: 0000 unimp - 2c42: 4e06 lw t3,64(sp) - 2c44: 0000 unimp - 2c46: 8c00 0x8c00 - 2c48: 0000 unimp - 2c4a: 0700 addi s0,sp,896 - 2c4c: 005a c.slli zero,0x16 - 2c4e: 0000 unimp - 2c50: 00ff 0xff - 2c52: 7c05 lui s8,0xfffe1 - 2c54: 0000 unimp - 2c56: 0800 addi s0,sp,16 - 2c58: 00000397 auipc t2,0x0 - 2c5c: 3c04 fld fs1,56(s0) - 2c5e: 8c16 mv s8,t0 - 2c60: 0000 unimp - 2c62: 0900 addi s0,sp,144 - 2c64: 08dc addi a5,sp,84 - 2c66: 0000 unimp - 2c68: 250f4803 lbu a6,592(t5) # 9bd1c <_start-0x7ff642e4> - 2c6c: 0000 unimp - 2c6e: 0a00 addi s0,sp,272 - 2c70: 0308 addi a0,sp,384 - 2c72: 00f3034f fnmadd.s ft6,ft6,fa5,ft0,rne - 2c76: 0000 unimp - 2c78: 0008bd0b 0x8bd0b - 2c7c: 0300 addi s0,sp,384 - 2c7e: 005a0e57 vadd.vv v28,v5,v20,v0.t - 2c82: 0000 unimp - 2c84: 2004 fld fs1,0(s0) - 2c86: 0000 unimp - 2c88: 0008c30b 0x8c30b - 2c8c: 0300 addi s0,sp,384 - 2c8e: 0e58 addi a4,sp,788 - 2c90: 005a c.slli zero,0x16 - 2c92: 0000 unimp - 2c94: 1404 addi s1,sp,544 - 2c96: 040c addi a1,sp,512 - 2c98: 650c flw fa1,8(a0) - 2c9a: 7078 flw fa4,100(s0) - 2c9c: 0300 addi s0,sp,384 - 2c9e: 0e59 addi t3,t3,22 - 2ca0: 005a c.slli zero,0x16 - 2ca2: 0000 unimp - 2ca4: 0b04 addi s1,sp,400 - 2ca6: 0401 addi s0,s0,0 - 2ca8: 00027a0b 0x27a0b - 2cac: 0300 addi s0,sp,384 - 2cae: 0e5a slli t3,t3,0x16 - 2cb0: 005a c.slli zero,0x16 - 2cb2: 0000 unimp - 2cb4: 0104 addi s1,sp,128 - 2cb6: 0400 addi s0,sp,512 - 2cb8: 0d00 addi s0,sp,656 - 2cba: 0a25 addi s4,s4,9 - 2cbc: 0000 unimp - 2cbe: 0308 addi a0,sp,384 - 2cc0: 074c addi a1,sp,900 - 2cc2: 0119 addi sp,sp,6 - 2cc4: 0000 unimp - 2cc6: 660e flw fa2,192(sp) - 2cc8: 746c flw fa1,108(s0) - 2cca: 0300 addi s0,sp,384 - 2ccc: 0a4e slli s4,s4,0x13 - 2cce: 009d addi ra,ra,7 - 2cd0: 0000 unimp - 2cd2: 000a480f 0xa480f - 2cd6: 0300 addi s0,sp,384 - 2cd8: 055c addi a5,sp,644 - 2cda: 00a9 addi ra,ra,10 - 2cdc: 0000 unimp - 2cde: 1000 addi s0,sp,32 - 2ce0: 0aea slli s5,s5,0x1a - 2ce2: 0000 unimp - 2ce4: 2301 jal 31e4 <_start-0x7fffce1c> - 2ce6: 9d01 0x9d01 - 2ce8: 0000 unimp - 2cea: b000 fsd fs0,32(s0) - 2cec: 010e slli sp,sp,0x3 - 2cee: b880 fsd fs0,48(s1) - 2cf0: 0005 c.nop 1 - 2cf2: 0100 addi s0,sp,128 - 2cf4: 519c lw a5,32(a1) - 2cf6: 11000007 vlbff.v v0,(zero),v0.t - 2cfa: 0061 c.nop 24 - 2cfc: 2301 jal 31fc <_start-0x7fffce04> - 2cfe: 9d12 add s10,s10,tp - 2d00: 0000 unimp - 2d02: 2000 fld fs0,0(s0) - 2d04: 0028 addi a0,sp,8 - 2d06: 1100 addi s0,sp,160 - 2d08: 0062 c.slli zero,0x18 - 2d0a: 2301 jal 320a <_start-0x7fffcdf6> - 2d0c: 9d1c 0x9d1c - 2d0e: 0000 unimp - 2d10: a800 fsd fs0,16(s0) - 2d12: 0028 addi a0,sp,8 - 2d14: 1200 addi s0,sp,288 - 2d16: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 2d1a: 2501 jal 331a <_start-0x7fffcce6> - 2d1c: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> - 2d20: 3000 fld fs0,32(s0) - 2d22: 0029 c.nop 10 - 2d24: 1300 addi s0,sp,416 - 2d26: 0a4d addi s4,s4,19 - 2d28: 0000 unimp - 2d2a: 2501 jal 332a <_start-0x7fffccd6> - 2d2c: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> - 2d30: 0000 unimp - 2d32: 4114 lw a3,0(a0) - 2d34: 635f 0100 0326 0x3260100635f - 2d3a: 0751 addi a4,a4,20 - 2d3c: 0000 unimp - 2d3e: 2950 fld fa2,144(a0) - 2d40: 0000 unimp - 2d42: 4114 lw a3,0(a0) - 2d44: 735f 0100 0326 0x3260100735f - 2d4a: 0751 addi a4,a4,20 - 2d4c: 0000 unimp - 2d4e: 2985 jal 31be <_start-0x7fffce42> - 2d50: 0000 unimp - 2d52: 4114 lw a3,0(a0) - 2d54: 655f 0100 0326 0x3260100655f - 2d5a: 0751 addi a4,a4,20 - 2d5c: 0000 unimp - 2d5e: 29ad jal 31d8 <_start-0x7fffce28> - 2d60: 0000 unimp - 2d62: e812 fsw ft4,16(sp) - 2d64: 0009 c.nop 2 - 2d66: 0100 addi s0,sp,128 - 2d68: 0326 slli t1,t1,0x9 - 2d6a: 0758 addi a4,sp,900 - 2d6c: 0000 unimp - 2d6e: 2a7a fld fs4,408(sp) - 2d70: 0000 unimp - 2d72: 4a12 lw s4,4(sp) - 2d74: 0009 c.nop 2 - 2d76: 0100 addi s0,sp,128 - 2d78: 0326 slli t1,t1,0x9 - 2d7a: 0758 addi a4,sp,900 - 2d7c: 0000 unimp - 2d7e: 2afc fld fa5,208(a3) - 2d80: 0000 unimp - 2d82: 4214 lw a3,0(a2) - 2d84: 635f 0100 0327 0x3270100635f - 2d8a: 0751 addi a4,a4,20 - 2d8c: 0000 unimp - 2d8e: 00002baf amoadd.w s7,zero,(zero) - 2d92: 4214 lw a3,0(a2) - 2d94: 735f 0100 0327 0x3270100735f - 2d9a: 0751 addi a4,a4,20 - 2d9c: 0000 unimp - 2d9e: 00002bef jal s7,4d9e <_start-0x7fffb262> - 2da2: 4214 lw a3,0(a2) - 2da4: 655f 0100 0327 0x3270100655f - 2daa: 0751 addi a4,a4,20 - 2dac: 0000 unimp - 2dae: 00002c27 fsw ft0,24(zero) # 18 <_start-0x7fffffe8> - 2db2: ed12 fsw ft4,152(sp) - 2db4: 0009 c.nop 2 - 2db6: 0100 addi s0,sp,128 - 2db8: 07580327 0x7580327 - 2dbc: 0000 unimp - 2dbe: 2cb2 fld fs9,264(sp) - 2dc0: 0000 unimp - 2dc2: f212 fsw ft4,36(sp) - 2dc4: 0009 c.nop 2 - 2dc6: 0100 addi s0,sp,128 - 2dc8: 07580327 0x7580327 - 2dcc: 0000 unimp - 2dce: 2d29 jal 33e8 <_start-0x7fffcc18> - 2dd0: 0000 unimp - 2dd2: 5214 lw a3,32(a2) - 2dd4: 635f 0100 0328 0x3280100635f - 2dda: 0751 addi a4,a4,20 - 2ddc: 0000 unimp - 2dde: 2da5 jal 3456 <_start-0x7fffcbaa> - 2de0: 0000 unimp - 2de2: 5214 lw a3,32(a2) - 2de4: 735f 0100 0328 0x3280100735f - 2dea: 0751 addi a4,a4,20 - 2dec: 0000 unimp - 2dee: 2dd0 fld fa2,152(a1) - 2df0: 0000 unimp - 2df2: 5214 lw a3,32(a2) - 2df4: 655f 0100 0328 0x3280100655f - 2dfa: 0751 addi a4,a4,20 - 2dfc: 0000 unimp - 2dfe: 2e3a fld ft8,392(sp) - 2e00: 0000 unimp - 2e02: 3012 fld ft0,288(sp) - 2e04: 0009 c.nop 2 - 2e06: 0100 addi s0,sp,128 - 2e08: 0328 addi a0,sp,392 - 2e0a: 0758 addi a4,sp,900 - 2e0c: 0000 unimp - 2e0e: 2ec9 jal 31e0 <_start-0x7fffce20> - 2e10: 0000 unimp - 2e12: 5212 lw tp,36(sp) - 2e14: 000a c.slli zero,0x2 - 2e16: 0100 addi s0,sp,128 - 2e18: 0328 addi a0,sp,392 - 2e1a: 0758 addi a4,sp,900 - 2e1c: 0000 unimp - 2e1e: 2fcd jal 3610 <_start-0x7fffc9f0> - 2e20: 0000 unimp - 2e22: 7215 lui tp,0xfffe5 - 2e24: 0100 addi s0,sp,128 - 2e26: 0a29 addi s4,s4,10 - 2e28: 009d addi ra,ra,7 - 2e2a: 0000 unimp - 2e2c: 5016 0x5016 - 2e2e: 7c000003 lb zero,1984(zero) # 7c0 <_start-0x7ffff840> - 2e32: 0002 c.slli64 zero - 2e34: 1700 addi s0,sp,928 - 2e36: 0935 addi s2,s2,13 - 2e38: 0000 unimp - 2e3a: 2c01 jal 304a <_start-0x7fffcfb6> - 2e3c: 0000f303 0xf303 - 2e40: 0000 unimp - 2e42: 8816 mv a6,t0 - 2e44: 96000003 lb zero,-1696(zero) # fffff960 <__BSS_END__+0x7ffe8be8> - 2e48: 0002 c.slli64 zero - 2e4a: 1200 addi s0,sp,288 - 2e4c: 000008e3 beqz zero,365c <_start-0x7fffc9a4> - 2e50: 2c01 jal 3060 <_start-0x7fffcfa0> - 2e52: 00075103 lhu sp,0(a4) - 2e56: 3200 fld fs0,32(a2) - 2e58: 0030 addi a2,sp,8 - 2e5a: 0000 unimp - 2e5c: a016 fsd ft5,0(sp) - 2e5e: ac000003 lb zero,-1344(zero) # fffffac0 <__BSS_END__+0x7ffe8d48> - 2e62: 0002 c.slli64 zero - 2e64: 1700 addi s0,sp,928 - 2e66: 0935 addi s2,s2,13 - 2e68: 0000 unimp - 2e6a: 2d01 jal 347a <_start-0x7fffcb86> - 2e6c: 0000f303 0xf303 - 2e70: 0000 unimp - 2e72: b816 fsd ft5,48(sp) - 2e74: c6000003 lb zero,-928(zero) # fffffc60 <__BSS_END__+0x7ffe8ee8> - 2e78: 0002 c.slli64 zero - 2e7a: 1200 addi s0,sp,288 - 2e7c: 000008e3 beqz zero,368c <_start-0x7fffc974> - 2e80: 2d01 jal 3490 <_start-0x7fffcb70> - 2e82: 00075103 lhu sp,0(a4) - 2e86: 6600 flw fs0,8(a2) - 2e88: 0030 addi a2,sp,8 - 2e8a: 0000 unimp - 2e8c: d818 sw a4,48(s0) - 2e8e: 0110 addi a2,sp,128 - 2e90: 9c80 0x9c80 - 2e92: 0001 nop - 2e94: fa00 fsw fs0,48(a2) - 2e96: 0005 c.nop 1 - 2e98: 1700 addi s0,sp,928 - 2e9a: 0b3e slli s6,s6,0xf - 2e9c: 0000 unimp - 2e9e: 2e01 jal 31ae <_start-0x7fffce52> - 2ea0: 00075f03 lhu t5,0(a4) - 2ea4: 1600 addi s0,sp,800 - 2ea6: 03d0 addi a2,sp,452 - 2ea8: 0000 unimp - 2eaa: 058d addi a1,a1,3 - 2eac: 0000 unimp - 2eae: 9712 add a4,a4,tp - 2eb0: 0100000b 0x100000b - 2eb4: 032e slli t1,t1,0xb - 2eb6: 0758 addi a4,sp,900 - 2eb8: 0000 unimp - 2eba: 309a fld ft1,416(sp) - 2ebc: 0000 unimp - 2ebe: bb12 fsd ft4,432(sp) - 2ec0: 000a c.slli zero,0x2 - 2ec2: 0100 addi s0,sp,128 - 2ec4: 032e slli t1,t1,0xb - 2ec6: 0758 addi a4,sp,900 - 2ec8: 0000 unimp - 2eca: 30ad jal 2734 <_start-0x7fffd8cc> - 2ecc: 0000 unimp - 2ece: f312 fsw ft4,164(sp) - 2ed0: 000a c.slli zero,0x2 - 2ed2: 0100 addi s0,sp,128 - 2ed4: 032e slli t1,t1,0xb - 2ed6: 0758 addi a4,sp,900 - 2ed8: 0000 unimp - 2eda: 000030cb fnmsub.s ft1,ft0,ft0,ft0,rup - 2ede: 0f12 slli t5,t5,0x4 - 2ee0: 0100000b 0x100000b - 2ee4: 032e slli t1,t1,0xb - 2ee6: 0758 addi a4,sp,900 - 2ee8: 0000 unimp - 2eea: 30de fld ft1,496(sp) - 2eec: 0000 unimp - 2eee: e816 fsw ft5,16(sp) - 2ef0: b2000003 lb zero,-1248(zero) # fffffb20 <__BSS_END__+0x7ffe8da8> - 2ef4: 12000003 lb zero,288(zero) # 120 <_start-0x7ffffee0> - 2ef8: 05d8 addi a4,sp,708 - 2efa: 0000 unimp - 2efc: 2e01 jal 320c <_start-0x7fffcdf4> - 2efe: 00075803 lhu a6,0(a4) - 2f02: fc00 fsw fs0,56(s0) - 2f04: 0030 addi a2,sp,8 - 2f06: 1200 addi s0,sp,288 - 2f08: 05dd addi a1,a1,23 - 2f0a: 0000 unimp - 2f0c: 2e01 jal 321c <_start-0x7fffcde4> - 2f0e: 00075803 lhu a6,0(a4) - 2f12: 1f00 addi s0,sp,944 - 2f14: 0031 c.nop 12 - 2f16: 1200 addi s0,sp,288 - 2f18: 05e2 slli a1,a1,0x18 - 2f1a: 0000 unimp - 2f1c: 2e01 jal 322c <_start-0x7fffcdd4> - 2f1e: 00075803 lhu a6,0(a4) - 2f22: 7400 flw fs0,40(s0) - 2f24: 0031 c.nop 12 - 2f26: 1200 addi s0,sp,288 - 2f28: 000005e7 jalr a1,zero # 0 <_start-0x80000000> - 2f2c: 2e01 jal 323c <_start-0x7fffcdc4> - 2f2e: 00075803 lhu a6,0(a4) - 2f32: 8700 0x8700 - 2f34: 0031 c.nop 12 - 2f36: 1200 addi s0,sp,288 - 2f38: 00000407 vlbu.v v8,(zero),v0.t - 2f3c: 2e01 jal 324c <_start-0x7fffcdb4> - 2f3e: 00006803 0x6803 - 2f42: 9a00 0x9a00 - 2f44: 0031 c.nop 12 - 2f46: 1200 addi s0,sp,288 - 2f48: 04bd addi s1,s1,15 - 2f4a: 0000 unimp - 2f4c: 2e01 jal 325c <_start-0x7fffcda4> - 2f4e: 00006803 0x6803 - 2f52: ad00 fsd fs0,24(a0) - 2f54: 0031 c.nop 12 - 2f56: 1200 addi s0,sp,288 - 2f58: 03f1 addi t2,t2,28 - 2f5a: 0000 unimp - 2f5c: 2e01 jal 326c <_start-0x7fffcd94> - 2f5e: 00006803 0x6803 - 2f62: c000 sw s0,0(s0) - 2f64: 0031 c.nop 12 - 2f66: 1200 addi s0,sp,288 - 2f68: 04b8 addi a4,sp,584 - 2f6a: 0000 unimp - 2f6c: 2e01 jal 327c <_start-0x7fffcd84> - 2f6e: 00006803 0x6803 - 2f72: d300 sw s0,32(a4) - 2f74: 0031 c.nop 12 - 2f76: 0000 unimp - 2f78: 0016 c.slli zero,0x5 - 2f7a: 0004 0x4 - 2f7c: 3800 fld fs0,48(s0) - 2f7e: 0004 0x4 - 2f80: 1200 addi s0,sp,288 - 2f82: 05d8 addi a4,sp,708 - 2f84: 0000 unimp - 2f86: 2e01 jal 3296 <_start-0x7fffcd6a> - 2f88: 00075803 lhu a6,0(a4) - 2f8c: e600 fsw fs0,8(a2) - 2f8e: 0031 c.nop 12 - 2f90: 1200 addi s0,sp,288 - 2f92: 05dd addi a1,a1,23 - 2f94: 0000 unimp - 2f96: 2e01 jal 32a6 <_start-0x7fffcd5a> - 2f98: 00075803 lhu a6,0(a4) - 2f9c: f900 fsw fs0,48(a0) - 2f9e: 0031 c.nop 12 - 2fa0: 1200 addi s0,sp,288 - 2fa2: 05e2 slli a1,a1,0x18 - 2fa4: 0000 unimp - 2fa6: 2e01 jal 32b6 <_start-0x7fffcd4a> - 2fa8: 00075803 lhu a6,0(a4) - 2fac: 2700 fld fs0,8(a4) - 2fae: 0032 c.slli zero,0xc - 2fb0: 1200 addi s0,sp,288 - 2fb2: 000005e7 jalr a1,zero # 0 <_start-0x80000000> - 2fb6: 2e01 jal 32c6 <_start-0x7fffcd3a> - 2fb8: 00075803 lhu a6,0(a4) - 2fbc: 3a00 fld fs0,48(a2) - 2fbe: 0032 c.slli zero,0xc - 2fc0: 1700 addi s0,sp,928 - 2fc2: 00000407 vlbu.v v8,(zero),v0.t - 2fc6: 2e01 jal 32d6 <_start-0x7fffcd2a> - 2fc8: 00006803 0x6803 - 2fcc: 1200 addi s0,sp,288 - 2fce: 04bd addi s1,s1,15 - 2fd0: 0000 unimp - 2fd2: 2e01 jal 32e2 <_start-0x7fffcd1e> - 2fd4: 00006803 0x6803 - 2fd8: 4d00 lw s0,24(a0) - 2fda: 0032 c.slli zero,0xc - 2fdc: 1200 addi s0,sp,288 - 2fde: 03f1 addi t2,t2,28 - 2fe0: 0000 unimp - 2fe2: 2e01 jal 32f2 <_start-0x7fffcd0e> - 2fe4: 00006803 0x6803 - 2fe8: 6000 flw fs0,0(s0) - 2fea: 0032 c.slli zero,0xc - 2fec: 1200 addi s0,sp,288 - 2fee: 04b8 addi a4,sp,584 - 2ff0: 0000 unimp - 2ff2: 2e01 jal 3302 <_start-0x7fffccfe> - 2ff4: 00006803 0x6803 - 2ff8: 7300 flw fs0,32(a4) - 2ffa: 0032 c.slli zero,0xc - 2ffc: 0000 unimp - 2ffe: 2016 fld ft0,320(sp) - 3000: 0004 0x4 - 3002: ba00 fsd fs0,48(a2) - 3004: 0004 0x4 - 3006: 1200 addi s0,sp,288 - 3008: 05d8 addi a4,sp,708 - 300a: 0000 unimp - 300c: 2e01 jal 331c <_start-0x7fffcce4> - 300e: 00075803 lhu a6,0(a4) - 3012: 8600 0x8600 - 3014: 0032 c.slli zero,0xc - 3016: 1200 addi s0,sp,288 - 3018: 05dd addi a1,a1,23 - 301a: 0000 unimp - 301c: 2e01 jal 332c <_start-0x7fffccd4> - 301e: 00075803 lhu a6,0(a4) - 3022: 9900 0x9900 - 3024: 0032 c.slli zero,0xc - 3026: 1200 addi s0,sp,288 - 3028: 05e2 slli a1,a1,0x18 - 302a: 0000 unimp - 302c: 2e01 jal 333c <_start-0x7fffccc4> - 302e: 00075803 lhu a6,0(a4) - 3032: d900 sw s0,48(a0) - 3034: 0032 c.slli zero,0xc - 3036: 1200 addi s0,sp,288 - 3038: 000005e7 jalr a1,zero # 0 <_start-0x80000000> - 303c: 2e01 jal 334c <_start-0x7fffccb4> - 303e: 00075803 lhu a6,0(a4) - 3042: ec00 fsw fs0,24(s0) - 3044: 0032 c.slli zero,0xc - 3046: 1700 addi s0,sp,928 - 3048: 00000407 vlbu.v v8,(zero),v0.t - 304c: 2e01 jal 335c <_start-0x7fffcca4> - 304e: 00006803 0x6803 - 3052: 1700 addi s0,sp,928 - 3054: 04bd addi s1,s1,15 - 3056: 0000 unimp - 3058: 2e01 jal 3368 <_start-0x7fffcc98> - 305a: 00006803 0x6803 - 305e: 1200 addi s0,sp,288 - 3060: 03f1 addi t2,t2,28 - 3062: 0000 unimp - 3064: 2e01 jal 3374 <_start-0x7fffcc8c> - 3066: 00006803 0x6803 - 306a: ff00 fsw fs0,56(a4) - 306c: 0032 c.slli zero,0xc - 306e: 1200 addi s0,sp,288 - 3070: 04b8 addi a4,sp,584 - 3072: 0000 unimp - 3074: 2e01 jal 3384 <_start-0x7fffcc7c> - 3076: 00006803 0x6803 - 307a: 1200 addi s0,sp,288 - 307c: 00000033 add zero,zero,zero - 3080: 4816 lw a6,68(sp) - 3082: 0004 0x4 - 3084: 3c00 fld fs0,56(s0) - 3086: 0005 c.nop 1 - 3088: 1200 addi s0,sp,288 - 308a: 05d8 addi a4,sp,708 - 308c: 0000 unimp - 308e: 2e01 jal 339e <_start-0x7fffcc62> - 3090: 00075803 lhu a6,0(a4) - 3094: 2500 fld fs0,8(a0) - 3096: 12000033 0x12000033 - 309a: 05dd addi a1,a1,23 - 309c: 0000 unimp - 309e: 2e01 jal 33ae <_start-0x7fffcc52> - 30a0: 00075803 lhu a6,0(a4) - 30a4: 3800 fld fs0,48(s0) - 30a6: 12000033 0x12000033 - 30aa: 05e2 slli a1,a1,0x18 - 30ac: 0000 unimp - 30ae: 2e01 jal 33be <_start-0x7fffcc42> - 30b0: 00075803 lhu a6,0(a4) - 30b4: 6600 flw fs0,8(a2) - 30b6: 12000033 0x12000033 - 30ba: 000005e7 jalr a1,zero # 0 <_start-0x80000000> - 30be: 2e01 jal 33ce <_start-0x7fffcc32> - 30c0: 00075803 lhu a6,0(a4) - 30c4: 7900 flw fs0,48(a0) - 30c6: 17000033 0x17000033 - 30ca: 00000407 vlbu.v v8,(zero),v0.t - 30ce: 2e01 jal 33de <_start-0x7fffcc22> - 30d0: 00006803 0x6803 - 30d4: 1700 addi s0,sp,928 - 30d6: 04bd addi s1,s1,15 - 30d8: 0000 unimp - 30da: 2e01 jal 33ea <_start-0x7fffcc16> - 30dc: 00006803 0x6803 - 30e0: 1200 addi s0,sp,288 - 30e2: 03f1 addi t2,t2,28 - 30e4: 0000 unimp - 30e6: 2e01 jal 33f6 <_start-0x7fffcc0a> - 30e8: 00006803 0x6803 - 30ec: 9700 0x9700 - 30ee: 12000033 0x12000033 - 30f2: 04b8 addi a4,sp,584 - 30f4: 0000 unimp - 30f6: 2e01 jal 3406 <_start-0x7fffcbfa> - 30f8: 00006803 0x6803 - 30fc: aa00 fsd fs0,16(a2) - 30fe: 00000033 add zero,zero,zero - 3102: 7816 flw fa6,100(sp) - 3104: 0004 0x4 - 3106: 6600 flw fs0,8(a2) - 3108: 0005 c.nop 1 - 310a: 1200 addi s0,sp,288 - 310c: 0b84 addi s1,sp,464 - 310e: 0000 unimp - 3110: 2e01 jal 3420 <_start-0x7fffcbe0> - 3112: 00075803 lhu a6,0(a4) - 3116: bd00 fsd fs0,56(a0) - 3118: 12000033 0x12000033 - 311c: 00000b2b 0xb2b - 3120: 2e01 jal 3430 <_start-0x7fffcbd0> - 3122: 00075803 lhu a6,0(a4) - 3126: db00 sw s0,48(a4) - 3128: 00000033 add zero,zero,zero - 312c: a019 j 3132 <_start-0x7fffcece> - 312e: 0004 0x4 - 3130: 1200 addi s0,sp,288 - 3132: 0b84 addi s1,sp,464 - 3134: 0000 unimp - 3136: 2e01 jal 3446 <_start-0x7fffcbba> - 3138: 00075803 lhu a6,0(a4) - 313c: 2700 fld fs0,8(a4) - 313e: 0034 addi a3,sp,8 - 3140: 1200 addi s0,sp,288 - 3142: 00000b2b 0xb2b - 3146: 2e01 jal 3456 <_start-0x7fffcbaa> - 3148: 00075803 lhu a6,0(a4) - 314c: 3a00 fld fs0,48(a2) - 314e: 0034 addi a3,sp,8 - 3150: 0000 unimp - 3152: 1900 addi s0,sp,176 - 3154: 04b8 addi a4,sp,584 - 3156: 0000 unimp - 3158: 5712 lw a4,36(sp) - 315a: 000a c.slli zero,0x2 - 315c: 0100 addi s0,sp,128 - 315e: 032e slli t1,t1,0xb - 3160: 002c addi a1,sp,8 - 3162: 0000 unimp - 3164: 3486 fld fs1,96(sp) - 3166: 0000 unimp - 3168: d019 beqz s0,306e <_start-0x7fffcf92> - 316a: 0004 0x4 - 316c: 1200 addi s0,sp,288 - 316e: 00000ad7 vadd.vv v21,v0,v0,v0.t - 3172: 2e01 jal 3482 <_start-0x7fffcb7e> - 3174: 00075103 lhu sp,0(a4) - 3178: a500 fsd fs0,8(a0) - 317a: 0034 addi a3,sp,8 - 317c: 1200 addi s0,sp,288 - 317e: 0a6d addi s4,s4,27 - 3180: 0000 unimp - 3182: 2e01 jal 3492 <_start-0x7fffcb6e> - 3184: 00075103 lhu sp,0(a4) - 3188: c500 sw s0,8(a0) - 318a: 0034 addi a3,sp,8 - 318c: 1200 addi s0,sp,288 - 318e: 0a94 addi a3,sp,336 - 3190: 0000 unimp - 3192: 2e01 jal 34a2 <_start-0x7fffcb5e> - 3194: 00075103 lhu sp,0(a4) - 3198: e500 fsw fs0,8(a0) - 319a: 0034 addi a3,sp,8 - 319c: 1200 addi s0,sp,288 - 319e: 0a82 c.slli64 s5 - 31a0: 0000 unimp - 31a2: 2e01 jal 34b2 <_start-0x7fffcb4e> - 31a4: 00075103 lhu sp,0(a4) - 31a8: 0500 addi s0,sp,640 - 31aa: 0035 c.nop 13 - 31ac: 1200 addi s0,sp,288 - 31ae: 0aa9 addi s5,s5,10 - 31b0: 0000 unimp - 31b2: 2e01 jal 34c2 <_start-0x7fffcb3e> - 31b4: 00075803 lhu a6,0(a4) - 31b8: 3100 fld fs0,32(a0) - 31ba: 0035 c.nop 13 - 31bc: 0000 unimp - 31be: 0000 unimp - 31c0: b018 fsd fa4,32(s0) - 31c2: 0112 slli sp,sp,0x4 - 31c4: 1080 addi s0,sp,96 - 31c6: 0000 unimp - 31c8: 1800 addi s0,sp,48 - 31ca: 0006 c.slli zero,0x1 - 31cc: 1400 addi s0,sp,544 - 31ce: 5f5f 0078 2f01 0x2f0100785f5f - 31d4: 00075803 lhu a6,0(a4) - 31d8: 6800 flw fs0,16(s0) - 31da: 0035 c.nop 13 - 31dc: 0000 unimp - 31de: 2a1a fld fs4,384(sp) - 31e0: 0006 c.slli zero,0x1 - 31e2: 1500 addi s0,sp,672 - 31e4: 5f5f 0078 2f01 0x2f0100785f5f - 31ea: 00075803 lhu a6,0(a4) - 31ee: 0000 unimp - 31f0: 3c1a fld fs8,416(sp) - 31f2: 0006 c.slli zero,0x1 - 31f4: 1500 addi s0,sp,672 - 31f6: 5f5f 0078 2f01 0x2f0100785f5f - 31fc: 00075803 lhu a6,0(a4) - 3200: 0000 unimp - 3202: f016 fsw ft5,32(sp) - 3204: 0004 0x4 - 3206: 3a00 fld fs0,48(a2) - 3208: 17000007 0x17000007 - 320c: 09b6 slli s3,s3,0xd - 320e: 0000 unimp - 3210: 2f01 jal 3920 <_start-0x7fffc6e0> - 3212: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> - 3216: 1a00 addi s0,sp,304 - 3218: 06c5 addi a3,a3,17 - 321a: 0000 unimp - 321c: 0009d117 auipc sp,0x9d - 3220: 0100 addi s0,sp,128 - 3222: 0751032f 0x751032f - 3226: 0000 unimp - 3228: 00099f17 auipc t5,0x99 - 322c: 0100 addi s0,sp,128 - 322e: 0751032f 0x751032f - 3232: 0000 unimp - 3234: 000a3117 auipc sp,0xa3 - 3238: 0100 addi s0,sp,128 - 323a: 0751032f 0x751032f - 323e: 0000 unimp - 3240: 0007a917 auipc s2,0x7a - 3244: 0100 addi s0,sp,128 - 3246: 0758032f 0x758032f - 324a: 0000 unimp - 324c: 0007c117 auipc sp,0x7c - 3250: 0100 addi s0,sp,128 - 3252: 0758032f 0x758032f - 3256: 0000 unimp - 3258: a41a fsd ft6,8(sp) - 325a: 0006 c.slli zero,0x1 - 325c: 1500 addi s0,sp,672 - 325e: 5f5f 0078 2f01 0x2f0100785f5f - 3264: 00075803 lhu a6,0(a4) - 3268: 0000 unimp - 326a: b61a fsd ft6,296(sp) - 326c: 0006 c.slli zero,0x1 - 326e: 1500 addi s0,sp,672 - 3270: 5f5f 0078 2f01 0x2f0100785f5f - 3276: 00075803 lhu a6,0(a4) - 327a: 0000 unimp - 327c: 5f5f151b 0x5f5f151b - 3280: 0078 addi a4,sp,12 - 3282: 2f01 jal 3992 <_start-0x7fffc66e> - 3284: 00075803 lhu a6,0(a4) - 3288: 0000 unimp - 328a: 1800 addi s0,sp,48 - 328c: 13d0 addi a2,sp,484 - 328e: 8001 c.srli64 s0 - 3290: 0010 0x10 - 3292: 0000 unimp - 3294: 000006e3 beqz zero,3aa0 <_start-0x7fffc560> - 3298: 5f14 lw a3,56(a4) - 329a: 785f 0100 032f 0x32f0100785f - 32a0: 0758 addi a4,sp,900 - 32a2: 0000 unimp - 32a4: 0000357b 0x357b - 32a8: 1a00 addi s0,sp,304 - 32aa: 06f5 addi a3,a3,29 - 32ac: 0000 unimp - 32ae: 5f15 li t5,-27 - 32b0: 785f 0100 032f 0x32f0100785f - 32b6: 0758 addi a4,sp,900 - 32b8: 0000 unimp - 32ba: 1a00 addi s0,sp,304 - 32bc: 00000707 vlbu.v v14,(zero),v0.t - 32c0: 5f15 li t5,-27 - 32c2: 785f 0100 032f 0x32f0100785f - 32c8: 0758 addi a4,sp,900 - 32ca: 0000 unimp - 32cc: 1a00 addi s0,sp,304 - 32ce: 0719 addi a4,a4,6 - 32d0: 0000 unimp - 32d2: 5f15 li t5,-27 - 32d4: 785f 0100 032f 0x32f0100785f - 32da: 0758 addi a4,sp,900 - 32dc: 0000 unimp - 32de: 1a00 addi s0,sp,304 - 32e0: 0000072b 0x72b - 32e4: 5f15 li t5,-27 - 32e6: 785f 0100 032f 0x32f0100785f - 32ec: 0758 addi a4,sp,900 - 32ee: 0000 unimp - 32f0: 1b00 addi s0,sp,432 - 32f2: 5f15 li t5,-27 - 32f4: 785f 0100 032f 0x32f0100785f - 32fa: 0758 addi a4,sp,900 - 32fc: 0000 unimp - 32fe: 0000 unimp - 3300: f01c fsw fa5,32(s0) - 3302: 0112 slli sp,sp,0x4 - 3304: 1c80 addi s0,sp,624 - 3306: 0000 unimp - 3308: 1700 addi s0,sp,928 - 330a: 08c9 addi a7,a7,18 - 330c: 0000 unimp - 330e: 2f01 jal 3a1e <_start-0x7fffc5e2> - 3310: 0000f303 0xf303 - 3314: 0000 unimp - 3316: 0200 addi s0,sp,256 - 3318: 0504 addi s1,sp,640 - 331a: 0222 slli tp,tp,0x8 - 331c: 0000 unimp - 331e: 0402 c.slli64 s0 - 3320: 00036907 vlwu.v v18,(t1),v0.t - 3324: 1d00 addi s0,sp,688 - 3326: 0758 addi a4,sp,900 - 3328: 0000 unimp - 332a: 00005a07 vlhu.v v20,(zero),v0.t - 332e: 0300 addi s0,sp,384 - 3330: 0000 unimp - 3332: 0294 addi a3,sp,320 - 3334: 0000 unimp - 3336: 0004 0x4 - 3338: 08d2 slli a7,a7,0x14 - 333a: 0000 unimp - 333c: 0104 addi s1,sp,128 - 333e: 07f2 slli a5,a5,0x1c - 3340: 0000 unimp - 3342: c80c sw a1,16(s0) - 3344: fc00000b 0xfc00000b - 3348: 0002 c.slli64 zero - 334a: 6800 flw fs0,16(s0) - 334c: 0114 addi a3,sp,128 - 334e: cc80 sw s0,24(s1) - 3350: 0000 unimp - 3352: 8d00 0x8d00 - 3354: 002c addi a1,sp,8 - 3356: 0200 addi s0,sp,256 - 3358: 0c08 addi a0,sp,528 - 335a: 0000 unimp - 335c: 5002 0x5002 - 335e: 310d jal 2f80 <_start-0x7fffd080> - 3360: 0000 unimp - 3362: 0300 addi s0,sp,384 - 3364: 0504 addi s1,sp,640 - 3366: 6e69 lui t3,0x1a - 3368: 0074 addi a3,sp,12 - 336a: 0104 addi s1,sp,128 - 336c: 6906 flw fs2,64(sp) - 336e: 0006 c.slli zero,0x1 - 3370: 0400 addi s0,sp,512 - 3372: 0508 addi a0,sp,640 - 3374: 021d addi tp,tp,7 - 3376: 0000 unimp - 3378: 7305 lui t1,0xfffe1 - 337a: 03000007 vlbuff.v v0,(zero) - 337e: 014a slli sp,sp,0x12 - 3380: 5816 lw a6,100(sp) - 3382: 0000 unimp - 3384: 0600 addi s0,sp,768 - 3386: 0046 c.slli zero,0x11 - 3388: 0000 unimp - 338a: 0104 addi s1,sp,128 - 338c: 6708 flw fa0,8(a4) - 338e: 0006 c.slli zero,0x1 - 3390: 0400 addi s0,sp,512 - 3392: 0704 addi s1,sp,896 - 3394: 036e slli t1,t1,0x1b - 3396: 0000 unimp - 3398: 0804 addi s1,sp,16 - 339a: 00036407 vlwu.v v8,(t1),v0.t - 339e: 0400 addi s0,sp,512 - 33a0: 0702 c.slli64 a4 - 33a2: 0384 addi s1,sp,448 - 33a4: 0000 unimp - 33a6: 00005307 vlhu.v v6,(zero),v0.t - 33aa: 8400 0x8400 - 33ac: 0000 unimp - 33ae: 0800 addi s0,sp,16 - 33b0: 005f 0000 00ff 0xff0000005f - 33b6: 7406 flw fs0,96(sp) - 33b8: 0000 unimp - 33ba: 0900 addi s0,sp,144 - 33bc: 00000397 auipc t2,0x0 - 33c0: 3c05 jal 2df0 <_start-0x7fffd210> - 33c2: 8416 mv s0,t0 - 33c4: 0000 unimp - 33c6: 0200 addi s0,sp,256 - 33c8: 0c01 addi s8,s8,0 - 33ca: 0000 unimp - 33cc: 4804 lw s1,16(s0) - 33ce: 0000a10f 0xa10f - 33d2: 0400 addi s0,sp,512 - 33d4: 0410 addi a2,sp,512 - 33d6: 009d addi ra,ra,7 - 33d8: 0000 unimp - 33da: 100a c.slli zero,0x22 - 33dc: 4f04 lw s1,24(a4) - 33de: 00011203 lh tp,0(sp) # 7f24c <_start-0x7ff80db4> - 33e2: 0b00 addi s0,sp,400 - 33e4: 08bd addi a7,a7,15 - 33e6: 0000 unimp - 33e8: 5904 lw s1,48(a0) - 33ea: 00011213 slli tp,sp,0x0 - 33ee: 0400 addi s0,sp,512 - 33f0: 0020 addi s0,sp,8 - 33f2: 0b00 addi s0,sp,400 - 33f4: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne - 33f8: 5a04 lw s1,48(a2) - 33fa: 00011213 slli tp,sp,0x0 - 33fe: 0400 addi s0,sp,512 - 3400: 0020 addi s0,sp,8 - 3402: 0b04 addi s1,sp,400 - 3404: 0bf5 addi s7,s7,29 - 3406: 0000 unimp - 3408: 5b04 lw s1,48(a4) - 340a: 00011213 slli tp,sp,0x0 - 340e: 0400 addi s0,sp,512 - 3410: 0020 addi s0,sp,8 - 3412: 0b08 addi a0,sp,400 - 3414: 00000bfb 0xbfb - 3418: 5c04 lw s1,56(s0) - 341a: 00011213 slli tp,sp,0x0 - 341e: 0400 addi s0,sp,512 - 3420: 1010 addi a2,sp,32 - 3422: 0c0c addi a1,sp,528 - 3424: 7865 lui a6,0xffff9 - 3426: 0070 addi a2,sp,12 - 3428: 5d04 lw s1,56(a0) - 342a: 5f0e lw t5,224(sp) - 342c: 0000 unimp - 342e: 0400 addi s0,sp,512 - 3430: 0b0c010f 0xb0c010f - 3434: 027a slli tp,tp,0x1e - 3436: 0000 unimp - 3438: 5e04 lw s1,56(a2) - 343a: 5f0e lw t5,224(sp) - 343c: 0000 unimp - 343e: 0400 addi s0,sp,512 - 3440: 0001 nop - 3442: 000c 0xc - 3444: 0404 addi s1,sp,512 - 3446: 00036907 vlwu.v v18,(t1),v0.t - 344a: 0d00 addi s0,sp,656 - 344c: 00000c2f 0xc2f - 3450: 0410 addi a2,sp,512 - 3452: 074c addi a1,sp,900 - 3454: 0000013f 746c660e 0x746c660e0000013f - 345c: 0400 addi s0,sp,512 - 345e: 0a4e slli s4,s4,0x13 - 3460: 0095 addi ra,ra,5 - 3462: 0000 unimp - 3464: 000a480f 0xa480f - 3468: 0400 addi s0,sp,512 - 346a: 0560 addi s0,sp,652 - 346c: 00a8 addi a0,sp,72 - 346e: 0000 unimp - 3470: 1000 addi s0,sp,32 - 3472: 00000c27 vsb.v v24,(zero),v0.t - 3476: 2301 jal 3976 <_start-0x7fffc68a> - 3478: 2501 jal 3a78 <_start-0x7fffc588> - 347a: 0000 unimp - 347c: 6800 flw fs0,16(s0) - 347e: 0114 addi a3,sp,128 - 3480: cc80 sw s0,24(s1) - 3482: 0000 unimp - 3484: 0100 addi s0,sp,128 - 3486: 849c 0x849c - 3488: 0002 c.slli64 zero - 348a: 1100 addi s0,sp,160 - 348c: 0061 c.nop 24 - 348e: 2301 jal 398e <_start-0x7fffc672> - 3490: 9511 srai a0,a0,0x24 - 3492: 0000 unimp - 3494: 1100 addi s0,sp,160 - 3496: 0062 c.slli zero,0x18 - 3498: 2301 jal 3998 <_start-0x7fffc668> - 349a: 0000951b 0x951b - 349e: 1200 addi s0,sp,288 - 34a0: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 34a4: 2501 jal 3aa4 <_start-0x7fffc55c> - 34a6: 00003103 0x3103 - 34aa: 0000 unimp - 34ac: 4d12 lw s10,4(sp) - 34ae: 000a c.slli zero,0x2 - 34b0: 0100 addi s0,sp,128 - 34b2: 0325 addi t1,t1,9 - 34b4: 0031 c.nop 12 - 34b6: 0000 unimp - 34b8: 1300 addi s0,sp,416 - 34ba: 5f41 li t5,-16 - 34bc: 26010063 beqz sp,371c <_start-0x7fffc8e4> - 34c0: 00028403 lb s0,0(t0) - 34c4: 1400 addi s0,sp,544 - 34c6: 5f41 li t5,-16 - 34c8: 26010073 0x26010073 - 34cc: 00028403 lb s0,0(t0) - 34d0: 0600 addi s0,sp,768 - 34d2: 007c addi a5,sp,12 - 34d4: ff08 fsw fa0,56(a4) - 34d6: 9f1a add t5,t5,t1 - 34d8: 4114 lw a3,0(a0) - 34da: 655f 0100 0326 0x3260100655f - 34e0: 0284 addi s1,sp,320 - 34e2: 0000 unimp - 34e4: 5d01 li s10,-32 - 34e6: 4115 li sp,5 - 34e8: 665f 0100 0326 0x3260100665f - 34ee: 0000028b 0x28b - 34f2: 358e fld fa1,224(sp) - 34f4: 0000 unimp - 34f6: 635f4213 xori tp,t5,1589 - 34fa: 0100 addi s0,sp,128 - 34fc: 02840327 0x2840327 - 3500: 0000 unimp - 3502: 4214 lw a3,0(a2) - 3504: 735f 0100 0327 0x3270100735f - 350a: 0284 addi s1,sp,320 - 350c: 0000 unimp - 350e: 7b06 flw fs6,96(sp) - 3510: 0800 addi s0,sp,16 - 3512: 1aff 0x1aff - 3514: 149f 5f42 0065 0x655f42149f - 351a: 2701 jal 3c1a <_start-0x7fffc3e6> - 351c: 00028403 lb s0,0(t0) - 3520: 0100 addi s0,sp,128 - 3522: 155f 5f42 0066 0x665f42155f - 3528: 2701 jal 3c28 <_start-0x7fffc3d8> - 352a: 00028b03 lb s6,0(t0) - 352e: e200 fsw fs0,0(a2) - 3530: 0035 c.nop 13 - 3532: 1400 addi s0,sp,544 - 3534: 0072 c.slli zero,0x1c - 3536: 2801 jal 3546 <_start-0x7fffcaba> - 3538: 0000250b 0x250b - 353c: 0100 addi s0,sp,128 - 353e: 165a slli a2,a2,0x36 - 3540: 0510 addi a2,sp,640 - 3542: 0000 unimp - 3544: 0226 slli tp,tp,0x9 - 3546: 0000 unimp - 3548: 000bb317 auipc t1,0xbb - 354c: 0100 addi s0,sp,128 - 354e: 0119032b 0x119032b - 3552: 0000 unimp - 3554: 9102 jalr sp - 3556: 0070 addi a2,sp,12 - 3558: 4816 lw a6,68(sp) - 355a: 0005 c.nop 1 - 355c: 3f00 fld fs0,56(a4) - 355e: 0002 c.slli64 zero - 3560: 1700 addi s0,sp,928 - 3562: 00000bb3 add s7,zero,zero - 3566: 2c01 jal 3776 <_start-0x7fffc88a> - 3568: 00011903 lh s2,0(sp) - 356c: 0200 addi s0,sp,256 - 356e: 7091 lui ra,0xfffe4 - 3570: 1800 addi s0,sp,48 - 3572: 0251 addi tp,tp,20 - 3574: 0000 unimp - 3576: 1619 addi a2,a2,-26 - 3578: 000c 0xc - 357a: 0100 addi s0,sp,128 - 357c: 032d addi t1,t1,11 - 357e: 0031 c.nop 12 - 3580: 0000 unimp - 3582: 1800 addi s0,sp,48 - 3584: 00000263 beqz zero,3588 <_start-0x7fffca78> - 3588: 1619 addi a2,a2,-26 - 358a: 000c 0xc - 358c: 0100 addi s0,sp,128 - 358e: 032d addi t1,t1,11 - 3590: 0031 c.nop 12 - 3592: 0000 unimp - 3594: 1800 addi s0,sp,48 - 3596: 0275 addi tp,tp,29 - 3598: 0000 unimp - 359a: 1619 addi a2,a2,-26 - 359c: 000c 0xc - 359e: 0100 addi s0,sp,128 - 35a0: 032d addi t1,t1,11 - 35a2: 0031 c.nop 12 - 35a4: 0000 unimp - 35a6: 1a00 addi s0,sp,304 - 35a8: 1619 addi a2,a2,-26 - 35aa: 000c 0xc - 35ac: 0100 addi s0,sp,128 - 35ae: 032d addi t1,t1,11 - 35b0: 0031 c.nop 12 - 35b2: 0000 unimp - 35b4: 0000 unimp - 35b6: 0404 addi s1,sp,512 - 35b8: 2205 jal 36d8 <_start-0x7fffc928> - 35ba: 0002 c.slli64 zero - 35bc: 1b00 addi s0,sp,432 - 35be: 0112 slli sp,sp,0x4 - 35c0: 0000 unimp - 35c2: 5f08 lw a0,56(a4) - 35c4: 0000 unimp - 35c6: 0300 addi s0,sp,384 - 35c8: 0000 unimp - 35ca: 0292 slli t0,t0,0x4 - 35cc: 0000 unimp - 35ce: 0004 0x4 - 35d0: 0a5d addi s4,s4,23 - 35d2: 0000 unimp - 35d4: 0104 addi s1,sp,128 - 35d6: 07f2 slli a5,a5,0x1c - 35d8: 0000 unimp - 35da: 430c lw a1,0(a4) - 35dc: 000c 0xc - 35de: fc00 fsw fs0,56(s0) - 35e0: 0002 c.slli64 zero - 35e2: 3400 fld fs0,40(s0) - 35e4: 0115 addi sp,sp,5 - 35e6: 4480 lw s0,8(s1) - 35e8: 0001 nop - 35ea: 3300 fld fs0,32(a4) - 35ec: 0200002f 0x200002f - 35f0: 0c08 addi a0,sp,528 - 35f2: 0000 unimp - 35f4: 5002 0x5002 - 35f6: 310d jal 3218 <_start-0x7fffcde8> - 35f8: 0000 unimp - 35fa: 0300 addi s0,sp,384 - 35fc: 0504 addi s1,sp,640 - 35fe: 6e69 lui t3,0x1a - 3600: 0074 addi a3,sp,12 - 3602: 0104 addi s1,sp,128 - 3604: 6906 flw fs2,64(sp) - 3606: 0006 c.slli zero,0x1 - 3608: 0400 addi s0,sp,512 - 360a: 0508 addi a0,sp,640 - 360c: 021d addi tp,tp,7 - 360e: 0000 unimp - 3610: 7305 lui t1,0xfffe1 - 3612: 03000007 vlbuff.v v0,(zero) - 3616: 014a slli sp,sp,0x12 - 3618: 5816 lw a6,100(sp) - 361a: 0000 unimp - 361c: 0600 addi s0,sp,768 - 361e: 0046 c.slli zero,0x11 - 3620: 0000 unimp - 3622: 0104 addi s1,sp,128 - 3624: 6708 flw fa0,8(a4) - 3626: 0006 c.slli zero,0x1 - 3628: 0400 addi s0,sp,512 - 362a: 0704 addi s1,sp,896 - 362c: 036e slli t1,t1,0x1b - 362e: 0000 unimp - 3630: 0804 addi s1,sp,16 - 3632: 00036407 vlwu.v v8,(t1),v0.t - 3636: 0400 addi s0,sp,512 - 3638: 0702 c.slli64 a4 - 363a: 0384 addi s1,sp,448 - 363c: 0000 unimp - 363e: 00005307 vlhu.v v6,(zero),v0.t - 3642: 8400 0x8400 - 3644: 0000 unimp - 3646: 0800 addi s0,sp,16 - 3648: 005f 0000 00ff 0xff0000005f - 364e: 7406 flw fs0,96(sp) - 3650: 0000 unimp - 3652: 0900 addi s0,sp,144 - 3654: 00000397 auipc t2,0x0 - 3658: 3c05 jal 3088 <_start-0x7fffcf78> - 365a: 8416 mv s0,t0 - 365c: 0000 unimp - 365e: 0200 addi s0,sp,256 - 3660: 0c01 addi s8,s8,0 - 3662: 0000 unimp - 3664: 4804 lw s1,16(s0) - 3666: 0000a10f 0xa10f - 366a: 0400 addi s0,sp,512 - 366c: 0410 addi a2,sp,512 - 366e: 009d addi ra,ra,7 - 3670: 0000 unimp - 3672: 100a c.slli zero,0x22 - 3674: 4f04 lw s1,24(a4) - 3676: 00011203 lh tp,0(sp) - 367a: 0b00 addi s0,sp,400 - 367c: 08bd addi a7,a7,15 - 367e: 0000 unimp - 3680: 5904 lw s1,48(a0) - 3682: 00011213 slli tp,sp,0x0 - 3686: 0400 addi s0,sp,512 - 3688: 0020 addi s0,sp,8 - 368a: 0b00 addi s0,sp,400 - 368c: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne - 3690: 5a04 lw s1,48(a2) - 3692: 00011213 slli tp,sp,0x0 - 3696: 0400 addi s0,sp,512 - 3698: 0020 addi s0,sp,8 - 369a: 0b04 addi s1,sp,400 - 369c: 0bf5 addi s7,s7,29 - 369e: 0000 unimp - 36a0: 5b04 lw s1,48(a4) - 36a2: 00011213 slli tp,sp,0x0 - 36a6: 0400 addi s0,sp,512 - 36a8: 0020 addi s0,sp,8 - 36aa: 0b08 addi a0,sp,400 - 36ac: 00000bfb 0xbfb - 36b0: 5c04 lw s1,56(s0) - 36b2: 00011213 slli tp,sp,0x0 - 36b6: 0400 addi s0,sp,512 - 36b8: 1010 addi a2,sp,32 - 36ba: 0c0c addi a1,sp,528 - 36bc: 7865 lui a6,0xffff9 - 36be: 0070 addi a2,sp,12 - 36c0: 5d04 lw s1,56(a0) - 36c2: 5f0e lw t5,224(sp) - 36c4: 0000 unimp - 36c6: 0400 addi s0,sp,512 - 36c8: 0b0c010f 0xb0c010f - 36cc: 027a slli tp,tp,0x1e - 36ce: 0000 unimp - 36d0: 5e04 lw s1,56(a2) - 36d2: 5f0e lw t5,224(sp) - 36d4: 0000 unimp - 36d6: 0400 addi s0,sp,512 - 36d8: 0001 nop - 36da: 000c 0xc - 36dc: 0404 addi s1,sp,512 - 36de: 00036907 vlwu.v v18,(t1),v0.t - 36e2: 0d00 addi s0,sp,656 - 36e4: 00000c2f 0xc2f - 36e8: 0410 addi a2,sp,512 - 36ea: 074c addi a1,sp,900 - 36ec: 0000013f 746c660e 0x746c660e0000013f - 36f4: 0400 addi s0,sp,512 - 36f6: 0a4e slli s4,s4,0x13 - 36f8: 0095 addi ra,ra,5 - 36fa: 0000 unimp - 36fc: 000a480f 0xa480f - 3700: 0400 addi s0,sp,512 - 3702: 0560 addi s0,sp,652 - 3704: 00a8 addi a0,sp,72 - 3706: 0000 unimp - 3708: 1000 addi s0,sp,32 - 370a: 00000c3b 0xc3b - 370e: 2301 jal 3c0e <_start-0x7fffc3f2> - 3710: 2501 jal 3d10 <_start-0x7fffc2f0> - 3712: 0000 unimp - 3714: 3400 fld fs0,40(s0) - 3716: 0115 addi sp,sp,5 - 3718: 4480 lw s0,8(s1) - 371a: 0001 nop - 371c: 0100 addi s0,sp,128 - 371e: 829c 0x829c - 3720: 0002 c.slli64 zero - 3722: 1100 addi s0,sp,160 - 3724: 0061 c.nop 24 - 3726: 2301 jal 3c26 <_start-0x7fffc3da> - 3728: 9511 srai a0,a0,0x24 - 372a: 0000 unimp - 372c: 1100 addi s0,sp,160 - 372e: 0062 c.slli zero,0x18 - 3730: 2301 jal 3c30 <_start-0x7fffc3d0> - 3732: 0000951b 0x951b - 3736: 1200 addi s0,sp,288 - 3738: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 373c: 2501 jal 3d3c <_start-0x7fffc2c4> - 373e: 00003103 0x3103 - 3742: 0000 unimp - 3744: 4d12 lw s10,4(sp) - 3746: 000a c.slli zero,0x2 - 3748: 0100 addi s0,sp,128 - 374a: 0325 addi t1,t1,9 - 374c: 0031 c.nop 12 - 374e: 0000 unimp - 3750: 1300 addi s0,sp,416 - 3752: 5f41 li t5,-16 - 3754: 26010063 beqz sp,39b4 <_start-0x7fffc64c> - 3758: 00028203 lb tp,0(t0) - 375c: 1400 addi s0,sp,544 - 375e: 5f41 li t5,-16 - 3760: 26010073 0x26010073 - 3764: 00028203 lb tp,0(t0) - 3768: 1500 addi s0,sp,672 - 376a: 0036 c.slli zero,0xd - 376c: 1500 addi s0,sp,672 - 376e: 5f41 li t5,-16 - 3770: 0065 c.nop 25 - 3772: 2601 jal 3a72 <_start-0x7fffc58e> - 3774: 00028203 lb tp,0(t0) - 3778: 0100 addi s0,sp,128 - 377a: 145d addi s0,s0,-9 - 377c: 5f41 li t5,-16 - 377e: 0066 c.slli zero,0x19 - 3780: 2601 jal 3a80 <_start-0x7fffc580> - 3782: 00028903 lb s2,0(t0) - 3786: 5f00 lw s0,56(a4) - 3788: 0036 c.slli zero,0xd - 378a: 1300 addi s0,sp,416 - 378c: 5f42 lw t5,48(sp) - 378e: 27010063 beq sp,a6,39ee <_start-0x7fffc612> - 3792: 00028203 lb tp,0(t0) - 3796: 1500 addi s0,sp,672 - 3798: 5f42 lw t5,48(sp) - 379a: 27010073 0x27010073 - 379e: 00028203 lb tp,0(t0) - 37a2: 0100 addi s0,sp,128 - 37a4: 155c addi a5,sp,676 - 37a6: 5f42 lw t5,48(sp) - 37a8: 0065 c.nop 25 - 37aa: 2701 jal 3eaa <_start-0x7fffc156> - 37ac: 00028203 lb tp,0(t0) - 37b0: 0100 addi s0,sp,128 - 37b2: 145e slli s0,s0,0x37 - 37b4: 5f42 lw t5,48(sp) - 37b6: 0066 c.slli zero,0x19 - 37b8: 2701 jal 3eb8 <_start-0x7fffc148> - 37ba: 00028903 lb s2,0(t0) - 37be: b300 fsd fs0,32(a4) - 37c0: 0036 c.slli zero,0xd - 37c2: 1500 addi s0,sp,672 - 37c4: 0072 c.slli zero,0x1c - 37c6: 2801 jal 37d6 <_start-0x7fffc82a> - 37c8: 0000250b 0x250b - 37cc: 0100 addi s0,sp,128 - 37ce: 165a slli a2,a2,0x36 - 37d0: 0568 addi a0,sp,652 - 37d2: 0000 unimp - 37d4: 021e slli tp,tp,0x7 - 37d6: 0000 unimp - 37d8: 000bb317 auipc t1,0xbb - 37dc: 0100 addi s0,sp,128 - 37de: 0119032b 0x119032b - 37e2: 0000 unimp - 37e4: 9102 jalr sp - 37e6: 0070 addi a2,sp,12 - 37e8: a816 fsd ft5,16(sp) - 37ea: 0005 c.nop 1 - 37ec: 3700 fld fs0,40(a4) - 37ee: 0002 c.slli64 zero - 37f0: 1700 addi s0,sp,928 - 37f2: 00000bb3 add s7,zero,zero - 37f6: 2c01 jal 3a06 <_start-0x7fffc5fa> - 37f8: 00011903 lh s2,0(sp) - 37fc: 0200 addi s0,sp,256 - 37fe: 7091 lui ra,0xfffe4 - 3800: 1800 addi s0,sp,48 - 3802: 0249 addi tp,tp,18 - 3804: 0000 unimp - 3806: 1619 addi a2,a2,-26 - 3808: 000c 0xc - 380a: 0100 addi s0,sp,128 - 380c: 032d addi t1,t1,11 - 380e: 0031 c.nop 12 - 3810: 0000 unimp - 3812: 1800 addi s0,sp,48 - 3814: 0000025b 0x25b - 3818: 1619 addi a2,a2,-26 - 381a: 000c 0xc - 381c: 0100 addi s0,sp,128 - 381e: 032d addi t1,t1,11 - 3820: 0031 c.nop 12 - 3822: 0000 unimp - 3824: 1a00 addi s0,sp,304 - 3826: 05c0 addi s0,sp,708 - 3828: 0000 unimp - 382a: 000c701b 0xc701b - 382e: 0100 addi s0,sp,128 - 3830: 032d addi t1,t1,11 - 3832: 0031 c.nop 12 - 3834: 0000 unimp - 3836: 36e6 fld fa3,120(sp) - 3838: 0000 unimp - 383a: 000c821b 0xc821b - 383e: 0100 addi s0,sp,128 - 3840: 032d addi t1,t1,11 - 3842: 0031 c.nop 12 - 3844: 0000 unimp - 3846: 3705 jal 3766 <_start-0x7fffc89a> - 3848: 0000 unimp - 384a: 0000 unimp - 384c: 0404 addi s1,sp,512 - 384e: 2205 jal 396e <_start-0x7fffc692> - 3850: 0002 c.slli64 zero - 3852: 1c00 addi s0,sp,560 - 3854: 0112 slli sp,sp,0x4 - 3856: 0000 unimp - 3858: 5f08 lw a0,56(a4) - 385a: 0000 unimp - 385c: 0300 addi s0,sp,384 - 385e: 0000 unimp - 3860: 0292 slli t0,t0,0x4 - 3862: 0000 unimp - 3864: 0004 0x4 - 3866: 00000bfb 0xbfb - 386a: 0104 addi s1,sp,128 - 386c: 07f2 slli a5,a5,0x1c - 386e: 0000 unimp - 3870: 9c0c 0x9c0c - 3872: 000c 0xc - 3874: fc00 fsw fs0,56(s0) - 3876: 0002 c.slli64 zero - 3878: 7800 flw fs0,48(s0) - 387a: 0116 slli sp,sp,0x5 - 387c: 4480 lw s0,8(s1) - 387e: 0001 nop - 3880: c000 sw s0,0(s0) - 3882: 0032 c.slli zero,0xc - 3884: 0200 addi s0,sp,256 - 3886: 0c08 addi a0,sp,528 - 3888: 0000 unimp - 388a: 5002 0x5002 - 388c: 310d jal 34ae <_start-0x7fffcb52> - 388e: 0000 unimp - 3890: 0300 addi s0,sp,384 - 3892: 0504 addi s1,sp,640 - 3894: 6e69 lui t3,0x1a - 3896: 0074 addi a3,sp,12 - 3898: 0104 addi s1,sp,128 - 389a: 6906 flw fs2,64(sp) - 389c: 0006 c.slli zero,0x1 - 389e: 0400 addi s0,sp,512 - 38a0: 0508 addi a0,sp,640 - 38a2: 021d addi tp,tp,7 - 38a4: 0000 unimp - 38a6: 7305 lui t1,0xfffe1 - 38a8: 03000007 vlbuff.v v0,(zero) - 38ac: 014a slli sp,sp,0x12 - 38ae: 5816 lw a6,100(sp) - 38b0: 0000 unimp - 38b2: 0600 addi s0,sp,768 - 38b4: 0046 c.slli zero,0x11 - 38b6: 0000 unimp - 38b8: 0104 addi s1,sp,128 - 38ba: 6708 flw fa0,8(a4) - 38bc: 0006 c.slli zero,0x1 - 38be: 0400 addi s0,sp,512 - 38c0: 0704 addi s1,sp,896 - 38c2: 036e slli t1,t1,0x1b - 38c4: 0000 unimp - 38c6: 0804 addi s1,sp,16 - 38c8: 00036407 vlwu.v v8,(t1),v0.t - 38cc: 0400 addi s0,sp,512 - 38ce: 0702 c.slli64 a4 - 38d0: 0384 addi s1,sp,448 - 38d2: 0000 unimp - 38d4: 00005307 vlhu.v v6,(zero),v0.t - 38d8: 8400 0x8400 - 38da: 0000 unimp - 38dc: 0800 addi s0,sp,16 - 38de: 005f 0000 00ff 0xff0000005f - 38e4: 7406 flw fs0,96(sp) - 38e6: 0000 unimp - 38e8: 0900 addi s0,sp,144 - 38ea: 00000397 auipc t2,0x0 - 38ee: 3c05 jal 331e <_start-0x7fffcce2> - 38f0: 8416 mv s0,t0 - 38f2: 0000 unimp - 38f4: 0200 addi s0,sp,256 - 38f6: 0c01 addi s8,s8,0 - 38f8: 0000 unimp - 38fa: 4804 lw s1,16(s0) - 38fc: 0000a10f 0xa10f - 3900: 0400 addi s0,sp,512 - 3902: 0410 addi a2,sp,512 - 3904: 009d addi ra,ra,7 - 3906: 0000 unimp - 3908: 100a c.slli zero,0x22 - 390a: 4f04 lw s1,24(a4) - 390c: 00011203 lh tp,0(sp) - 3910: 0b00 addi s0,sp,400 - 3912: 08bd addi a7,a7,15 - 3914: 0000 unimp - 3916: 5904 lw s1,48(a0) - 3918: 00011213 slli tp,sp,0x0 - 391c: 0400 addi s0,sp,512 - 391e: 0020 addi s0,sp,8 - 3920: 0b00 addi s0,sp,400 - 3922: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne - 3926: 5a04 lw s1,48(a2) - 3928: 00011213 slli tp,sp,0x0 - 392c: 0400 addi s0,sp,512 - 392e: 0020 addi s0,sp,8 - 3930: 0b04 addi s1,sp,400 - 3932: 0bf5 addi s7,s7,29 - 3934: 0000 unimp - 3936: 5b04 lw s1,48(a4) - 3938: 00011213 slli tp,sp,0x0 - 393c: 0400 addi s0,sp,512 - 393e: 0020 addi s0,sp,8 - 3940: 0b08 addi a0,sp,400 - 3942: 00000bfb 0xbfb - 3946: 5c04 lw s1,56(s0) - 3948: 00011213 slli tp,sp,0x0 - 394c: 0400 addi s0,sp,512 - 394e: 1010 addi a2,sp,32 - 3950: 0c0c addi a1,sp,528 - 3952: 7865 lui a6,0xffff9 - 3954: 0070 addi a2,sp,12 - 3956: 5d04 lw s1,56(a0) - 3958: 5f0e lw t5,224(sp) - 395a: 0000 unimp - 395c: 0400 addi s0,sp,512 - 395e: 0b0c010f 0xb0c010f - 3962: 027a slli tp,tp,0x1e - 3964: 0000 unimp - 3966: 5e04 lw s1,56(a2) - 3968: 5f0e lw t5,224(sp) - 396a: 0000 unimp - 396c: 0400 addi s0,sp,512 - 396e: 0001 nop - 3970: 000c 0xc - 3972: 0404 addi s1,sp,512 - 3974: 00036907 vlwu.v v18,(t1),v0.t - 3978: 0d00 addi s0,sp,656 - 397a: 00000c2f 0xc2f - 397e: 0410 addi a2,sp,512 - 3980: 074c addi a1,sp,900 - 3982: 0000013f 746c660e 0x746c660e0000013f - 398a: 0400 addi s0,sp,512 - 398c: 0a4e slli s4,s4,0x13 - 398e: 0095 addi ra,ra,5 - 3990: 0000 unimp - 3992: 000a480f 0xa480f - 3996: 0400 addi s0,sp,512 - 3998: 0560 addi s0,sp,652 - 399a: 00a8 addi a0,sp,72 - 399c: 0000 unimp - 399e: 1000 addi s0,sp,32 - 39a0: 0c94 addi a3,sp,592 - 39a2: 0000 unimp - 39a4: 2301 jal 3ea4 <_start-0x7fffc15c> - 39a6: 2501 jal 3fa6 <_start-0x7fffc05a> - 39a8: 0000 unimp - 39aa: 7800 flw fs0,48(s0) - 39ac: 0116 slli sp,sp,0x5 - 39ae: 4480 lw s0,8(s1) - 39b0: 0001 nop - 39b2: 0100 addi s0,sp,128 - 39b4: 829c 0x829c - 39b6: 0002 c.slli64 zero - 39b8: 1100 addi s0,sp,160 - 39ba: 0061 c.nop 24 - 39bc: 2301 jal 3ebc <_start-0x7fffc144> - 39be: 9511 srai a0,a0,0x24 - 39c0: 0000 unimp - 39c2: 1100 addi s0,sp,160 - 39c4: 0062 c.slli zero,0x18 - 39c6: 2301 jal 3ec6 <_start-0x7fffc13a> - 39c8: 0000951b 0x951b - 39cc: 1200 addi s0,sp,288 - 39ce: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 39d2: 2501 jal 3fd2 <_start-0x7fffc02e> - 39d4: 00003103 0x3103 - 39d8: 0000 unimp - 39da: 4d12 lw s10,4(sp) - 39dc: 000a c.slli zero,0x2 - 39de: 0100 addi s0,sp,128 - 39e0: 0325 addi t1,t1,9 - 39e2: 0031 c.nop 12 - 39e4: 0000 unimp - 39e6: 1300 addi s0,sp,416 - 39e8: 5f41 li t5,-16 - 39ea: 26010063 beqz sp,3c4a <_start-0x7fffc3b6> - 39ee: 00028203 lb tp,0(t0) - 39f2: 1400 addi s0,sp,544 - 39f4: 5f41 li t5,-16 - 39f6: 26010073 0x26010073 - 39fa: 00028203 lb tp,0(t0) - 39fe: 4900 lw s0,16(a0) - 3a00: 15000037 lui zero,0x15000 - 3a04: 5f41 li t5,-16 - 3a06: 0065 c.nop 25 - 3a08: 2601 jal 3d08 <_start-0x7fffc2f8> - 3a0a: 00028203 lb tp,0(t0) - 3a0e: 0100 addi s0,sp,128 - 3a10: 145d addi s0,s0,-9 - 3a12: 5f41 li t5,-16 - 3a14: 0066 c.slli zero,0x19 - 3a16: 2601 jal 3d16 <_start-0x7fffc2ea> - 3a18: 00028903 lb s2,0(t0) - 3a1c: 9300 0x9300 - 3a1e: 13000037 lui zero,0x13000 - 3a22: 5f42 lw t5,48(sp) - 3a24: 27010063 beq sp,a6,3c84 <_start-0x7fffc37c> - 3a28: 00028203 lb tp,0(t0) - 3a2c: 1500 addi s0,sp,672 - 3a2e: 5f42 lw t5,48(sp) - 3a30: 27010073 0x27010073 - 3a34: 00028203 lb tp,0(t0) - 3a38: 0100 addi s0,sp,128 - 3a3a: 155c addi a5,sp,676 - 3a3c: 5f42 lw t5,48(sp) - 3a3e: 0065 c.nop 25 - 3a40: 2701 jal 4140 <_start-0x7fffbec0> - 3a42: 00028203 lb tp,0(t0) - 3a46: 0100 addi s0,sp,128 - 3a48: 145e slli s0,s0,0x37 - 3a4a: 5f42 lw t5,48(sp) - 3a4c: 0066 c.slli zero,0x19 - 3a4e: 2701 jal 414e <_start-0x7fffbeb2> - 3a50: 00028903 lb s2,0(t0) - 3a54: e700 fsw fs0,8(a4) - 3a56: 15000037 lui zero,0x15000 - 3a5a: 0072 c.slli zero,0x1c - 3a5c: 2801 jal 3a6c <_start-0x7fffc594> - 3a5e: 0000250b 0x250b - 3a62: 0100 addi s0,sp,128 - 3a64: 165a slli a2,a2,0x36 - 3a66: 05e0 addi s0,sp,716 - 3a68: 0000 unimp - 3a6a: 021e slli tp,tp,0x7 - 3a6c: 0000 unimp - 3a6e: 000bb317 auipc t1,0xbb - 3a72: 0100 addi s0,sp,128 - 3a74: 0119032b 0x119032b - 3a78: 0000 unimp - 3a7a: 9102 jalr sp - 3a7c: 0070 addi a2,sp,12 - 3a7e: 2016 fld ft0,320(sp) - 3a80: 0006 c.slli zero,0x1 - 3a82: 3700 fld fs0,40(a4) - 3a84: 0002 c.slli64 zero - 3a86: 1700 addi s0,sp,928 - 3a88: 00000bb3 add s7,zero,zero - 3a8c: 2c01 jal 3c9c <_start-0x7fffc364> - 3a8e: 00011903 lh s2,0(sp) - 3a92: 0200 addi s0,sp,256 - 3a94: 7091 lui ra,0xfffe4 - 3a96: 1800 addi s0,sp,48 - 3a98: 0249 addi tp,tp,18 - 3a9a: 0000 unimp - 3a9c: 1619 addi a2,a2,-26 - 3a9e: 000c 0xc - 3aa0: 0100 addi s0,sp,128 - 3aa2: 032d addi t1,t1,11 - 3aa4: 0031 c.nop 12 - 3aa6: 0000 unimp - 3aa8: 1800 addi s0,sp,48 - 3aaa: 0000025b 0x25b - 3aae: 1619 addi a2,a2,-26 - 3ab0: 000c 0xc - 3ab2: 0100 addi s0,sp,128 - 3ab4: 032d addi t1,t1,11 - 3ab6: 0031 c.nop 12 - 3ab8: 0000 unimp - 3aba: 1a00 addi s0,sp,304 - 3abc: 0638 addi a4,sp,776 - 3abe: 0000 unimp - 3ac0: 000c701b 0xc701b - 3ac4: 0100 addi s0,sp,128 - 3ac6: 032d addi t1,t1,11 - 3ac8: 0031 c.nop 12 - 3aca: 0000 unimp - 3acc: 381a fld fa6,416(sp) - 3ace: 0000 unimp - 3ad0: 000c821b 0xc821b - 3ad4: 0100 addi s0,sp,128 - 3ad6: 032d addi t1,t1,11 - 3ad8: 0031 c.nop 12 - 3ada: 0000 unimp - 3adc: 3839 jal 32fa <_start-0x7fffcd06> - 3ade: 0000 unimp - 3ae0: 0000 unimp - 3ae2: 0404 addi s1,sp,512 - 3ae4: 2205 jal 3c04 <_start-0x7fffc3fc> - 3ae6: 0002 c.slli64 zero - 3ae8: 1c00 addi s0,sp,560 - 3aea: 0112 slli sp,sp,0x4 - 3aec: 0000 unimp - 3aee: 5f08 lw a0,56(a4) - 3af0: 0000 unimp - 3af2: 0300 addi s0,sp,384 - 3af4: 0000 unimp - 3af6: 1268 addi a0,sp,300 - 3af8: 0000 unimp - 3afa: 0004 0x4 - 3afc: 0d99 addi s11,s11,6 - 3afe: 0000 unimp - 3b00: 0104 addi s1,sp,128 - 3b02: 07f2 slli a5,a5,0x1c - 3b04: 0000 unimp - 3b06: c30c sw a1,0(a4) - 3b08: 000e c.slli zero,0x3 - 3b0a: fc00 fsw fs0,56(s0) - 3b0c: 0002 c.slli64 zero - 3b0e: bc00 fsd fs0,56(s0) - 3b10: 08800117 auipc sp,0x8800 - 3b14: 0010 0x10 - 3b16: 4d00 lw s0,24(a0) - 3b18: 0036 c.slli zero,0xd - 3b1a: 0200 addi s0,sp,256 - 3b1c: 0504 addi s1,sp,640 - 3b1e: 6e69 lui t3,0x1a - 3b20: 0074 addi a3,sp,12 - 3b22: 69060103 lb sp,1680(a2) - 3b26: 0006 c.slli zero,0x1 - 3b28: 0300 addi s0,sp,384 - 3b2a: 0508 addi a0,sp,640 - 3b2c: 021d addi tp,tp,7 - 3b2e: 0000 unimp - 3b30: 7304 flw fs1,32(a4) - 3b32: 02000007 vlbu.v v0,(zero) - 3b36: 014a slli sp,sp,0x12 - 3b38: 4c16 lw s8,68(sp) - 3b3a: 0000 unimp - 3b3c: 0500 addi s0,sp,640 - 3b3e: 003a c.slli zero,0xe - 3b40: 0000 unimp - 3b42: 67080103 lb sp,1648(a6) # ffff9670 <__BSS_END__+0x7ffe28f8> - 3b46: 0006 c.slli zero,0x1 - 3b48: 0300 addi s0,sp,384 - 3b4a: 0704 addi s1,sp,896 - 3b4c: 036e slli t1,t1,0x1b - 3b4e: 0000 unimp - 3b50: 64070803 lb a6,1600(a4) - 3b54: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - 3b58: 089c addi a5,sp,80 - 3b5a: 0000 unimp - 3b5c: 4e02 lw t3,0(sp) - 3b5e: 1601 addi a2,a2,-32 - 3b60: 006e c.slli zero,0x1b - 3b62: 0000 unimp - 3b64: 84070203 lb tp,-1984(a4) - 3b68: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 3b6c: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne - 3b70: 0085 addi ra,ra,1 - 3b72: 0000 unimp - 3b74: 00005307 vlhu.v v6,(zero),v0.t - 3b78: ff00 fsw fs0,56(a4) - 3b7a: 0500 addi s0,sp,640 - 3b7c: 0075 c.nop 29 - 3b7e: 0000 unimp - 3b80: 9708 0x9708 - 3b82: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - 3b86: 163c addi a5,sp,808 - 3b88: 0085 addi ra,ra,1 - 3b8a: 0000 unimp - 3b8c: 0109 addi sp,sp,2 - 3b8e: 000c 0xc - 3b90: 0300 addi s0,sp,384 - 3b92: 0f48 addi a0,sp,916 - 3b94: 00a2 slli ra,ra,0x8 - 3b96: 0000 unimp - 3b98: 9d041003 lh zero,-1584(s0) # c9d0 <_start-0x7fff3630> - 3b9c: 0000 unimp - 3b9e: 0a00 addi s0,sp,272 - 3ba0: 0310 addi a2,sp,384 - 3ba2: 0113034f fnmadd.s ft6,ft6,fa7,ft0,rne - 3ba6: 0000 unimp - 3ba8: 0008bd0b 0x8bd0b - 3bac: 0300 addi s0,sp,384 - 3bae: 1359 addi t1,t1,-10 - 3bb0: 00000113 li sp,0 - 3bb4: 2004 fld fs1,0(s0) - 3bb6: 0000 unimp - 3bb8: 0008c30b 0x8c30b - 3bbc: 0300 addi s0,sp,384 - 3bbe: 135a slli t1,t1,0x36 - 3bc0: 00000113 li sp,0 - 3bc4: 2004 fld fs1,0(s0) - 3bc6: 0400 addi s0,sp,512 - 3bc8: 000bf50b 0xbf50b - 3bcc: 0300 addi s0,sp,384 - 3bce: 0113135b 0x113135b - 3bd2: 0000 unimp - 3bd4: 2004 fld fs1,0(s0) - 3bd6: 0800 addi s0,sp,16 - 3bd8: 000bfb0b 0xbfb0b - 3bdc: 0300 addi s0,sp,384 - 3bde: 135c addi a5,sp,420 - 3be0: 00000113 li sp,0 - 3be4: 1004 addi s1,sp,32 - 3be6: 0c10 addi a2,sp,528 - 3be8: 650c flw fa1,8(a0) - 3bea: 7078 flw fa4,100(s0) - 3bec: 0300 addi s0,sp,384 - 3bee: 0e5d addi t3,t3,23 - 3bf0: 00000053 fadd.s ft0,ft0,ft0,rne - 3bf4: 0f04 addi s1,sp,912 - 3bf6: 0c01 addi s8,s8,0 - 3bf8: 00027a0b 0x27a0b - 3bfc: 0300 addi s0,sp,384 - 3bfe: 0e5e slli t3,t3,0x17 - 3c00: 00000053 fadd.s ft0,ft0,ft0,rne - 3c04: 0104 addi s1,sp,128 - 3c06: 0c00 addi s0,sp,528 - 3c08: 0300 addi s0,sp,384 - 3c0a: 0704 addi s1,sp,896 - 3c0c: 0369 addi t1,t1,26 - 3c0e: 0000 unimp - 3c10: 2f0d jal 4342 <_start-0x7fffbcbe> - 3c12: 000c 0xc - 3c14: 1000 addi s0,sp,32 - 3c16: 40074c03 lbu s8,1024(a4) - 3c1a: 0001 nop - 3c1c: 0e00 addi s0,sp,784 - 3c1e: 6c66 flw fs8,88(sp) - 3c20: 0074 addi a3,sp,12 - 3c22: 960a4e03 lbu t3,-1696(s4) # 7368 <_start-0x7fff8c98> - 3c26: 0000 unimp - 3c28: 0f00 addi s0,sp,912 - 3c2a: 0a48 addi a0,sp,276 - 3c2c: 0000 unimp - 3c2e: a9056003 0xa9056003 - 3c32: 0000 unimp - 3c34: 0000 unimp - 3c36: 3510 fld fa2,40(a0) - 3c38: 000d c.nop 3 - 3c3a: 0100 addi s0,sp,128 - 3c3c: 00960123 sb s1,2(a2) - 3c40: 0000 unimp - 3c42: 17bc addi a5,sp,1000 - 3c44: 8001 c.srli64 s0 - 3c46: 1008 addi a0,sp,32 - 3c48: 0000 unimp - 3c4a: 9c01 0x9c01 - 3c4c: 1248 addi a0,sp,292 - 3c4e: 0000 unimp - 3c50: 6111 addi sp,sp,256 - 3c52: 0100 addi s0,sp,128 - 3c54: 00961223 sh s1,4(a2) - 3c58: 0000 unimp - 3c5a: 6211 lui tp,0x4 - 3c5c: 0100 addi s0,sp,128 - 3c5e: 00961c23 sh s1,24(a2) - 3c62: 0000 unimp - 3c64: 4f12 lw t5,4(sp) - 3c66: 0009 c.nop 2 - 3c68: 0100 addi s0,sp,128 - 3c6a: 0325 addi t1,t1,9 - 3c6c: 0025 c.nop 9 - 3c6e: 0000 unimp - 3c70: 387d jal 352e <_start-0x7fffcad2> - 3c72: 0000 unimp - 3c74: 000a4d13 xori s10,s4,0 - 3c78: 0100 addi s0,sp,128 - 3c7a: 0325 addi t1,t1,9 - 3c7c: 0025 c.nop 9 - 3c7e: 0000 unimp - 3c80: 1400 addi s0,sp,544 - 3c82: 5f41 li t5,-16 - 3c84: 26010063 beqz sp,3ee4 <_start-0x7fffc11c> - 3c88: 00124803 lbu a6,1(tp) # 4001 <_start-0x7fffbfff> - 3c8c: 9d00 0x9d00 - 3c8e: 0038 addi a4,sp,8 - 3c90: 1400 addi s0,sp,544 - 3c92: 5f41 li t5,-16 - 3c94: 26010073 0x26010073 - 3c98: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3c9c: dd00 sw s0,56(a0) - 3c9e: 0038 addi a4,sp,8 - 3ca0: 1400 addi s0,sp,544 - 3ca2: 5f41 li t5,-16 - 3ca4: 0065 c.nop 25 - 3ca6: 2601 jal 3fa6 <_start-0x7fffc05a> - 3ca8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3cac: 1500 addi s0,sp,672 - 3cae: 0039 c.nop 14 - 3cb0: 1500 addi s0,sp,672 - 3cb2: 5f41 li t5,-16 - 3cb4: 0066 c.slli zero,0x19 - 3cb6: 2601 jal 3fb6 <_start-0x7fffc04a> - 3cb8: 00124f03 lbu t5,1(tp) # 1 <_start-0x7fffffff> - 3cbc: 0300 addi s0,sp,384 - 3cbe: f091 bnez s1,3bc2 <_start-0x7fffc43e> - 3cc0: 147e slli s0,s0,0x3f - 3cc2: 5f42 lw t5,48(sp) - 3cc4: 27010063 beq sp,a6,3f24 <_start-0x7fffc0dc> - 3cc8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3ccc: a600 fsd fs0,8(a2) - 3cce: 0039 c.nop 14 - 3cd0: 1400 addi s0,sp,544 - 3cd2: 5f42 lw t5,48(sp) - 3cd4: 27010073 0x27010073 - 3cd8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3cdc: e600 fsw fs0,8(a2) - 3cde: 0039 c.nop 14 - 3ce0: 1400 addi s0,sp,544 - 3ce2: 5f42 lw t5,48(sp) - 3ce4: 0065 c.nop 25 - 3ce6: 2701 jal 43e6 <_start-0x7fffbc1a> - 3ce8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3cec: 3f00 fld fs0,56(a4) - 3cee: 003a c.slli zero,0xe - 3cf0: 1500 addi s0,sp,672 - 3cf2: 5f42 lw t5,48(sp) - 3cf4: 0066 c.slli zero,0x19 - 3cf6: 2701 jal 43f6 <_start-0x7fffbc0a> - 3cf8: 00124f03 lbu t5,1(tp) # 1 <_start-0x7fffffff> - 3cfc: 0300 addi s0,sp,384 - 3cfe: 8091 srli s1,s1,0x4 - 3d00: 147f 0x147f - 3d02: 5f52 lw t5,52(sp) - 3d04: 28010063 beqz sp,3f84 <_start-0x7fffc07c> - 3d08: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3d0c: 5200 lw s0,32(a2) - 3d0e: 1400003b 0x1400003b - 3d12: 5f52 lw t5,52(sp) - 3d14: 28010073 0x28010073 - 3d18: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3d1c: 9f00 0x9f00 - 3d1e: 1400003b 0x1400003b - 3d22: 5f52 lw t5,52(sp) - 3d24: 0065 c.nop 25 - 3d26: 2801 jal 3d36 <_start-0x7fffc2ca> - 3d28: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3d2c: f200 fsw fs0,32(a2) - 3d2e: 1500003b 0x1500003b - 3d32: 5f52 lw t5,52(sp) - 3d34: 0066 c.slli zero,0x19 - 3d36: 2801 jal 3d46 <_start-0x7fffc2ba> - 3d38: 00124f03 lbu t5,1(tp) # 1 <_start-0x7fffffff> - 3d3c: 0300 addi s0,sp,384 - 3d3e: 9091 srli s1,s1,0x24 - 3d40: 147f 0x147f - 3d42: 0072 c.slli zero,0x1c - 3d44: 2901 jal 4154 <_start-0x7fffbeac> - 3d46: 960a add a2,a2,sp - 3d48: 0000 unimp - 3d4a: ec00 fsw fs0,24(s0) - 3d4c: 003c addi a5,sp,8 - 3d4e: 1600 addi s0,sp,800 - 3d50: 0658 addi a4,sp,772 - 3d52: 0000 unimp - 3d54: 00000273 0x273 - 3d58: 000bb317 auipc t1,0xbb - 3d5c: 0100 addi s0,sp,128 - 3d5e: 032c addi a1,sp,392 - 3d60: 011a slli sp,sp,0x6 - 3d62: 0000 unimp - 3d64: 7fa09103 lh sp,2042(ra) # fffe47fa <__BSS_END__+0x7ffcda82> - 3d68: 1600 addi s0,sp,800 - 3d6a: 0688 addi a0,sp,832 - 3d6c: 0000 unimp - 3d6e: 02bd addi t0,t0,15 - 3d70: 0000 unimp - 3d72: 3c12 fld fs8,288(sp) - 3d74: 0100000f fence w,unknown - 3d78: 032c addi a1,sp,392 - 3d7a: 1248 addi a0,sp,292 - 3d7c: 0000 unimp - 3d7e: 3d2a fld fs10,168(sp) - 3d80: 0000 unimp - 3d82: 7712 flw fa4,36(sp) - 3d84: 000d c.nop 3 - 3d86: 0100 addi s0,sp,128 - 3d88: 032c addi a1,sp,392 - 3d8a: 1248 addi a0,sp,292 - 3d8c: 0000 unimp - 3d8e: 3d3e fld fs10,488(sp) - 3d90: 0000 unimp - 3d92: 6312 flw ft6,4(sp) - 3d94: 000d c.nop 3 - 3d96: 0100 addi s0,sp,128 - 3d98: 032c addi a1,sp,392 - 3d9a: 1248 addi a0,sp,292 - 3d9c: 0000 unimp - 3d9e: 3d52 fld fs10,304(sp) - 3da0: 0000 unimp - 3da2: c912 sw tp,144(sp) - 3da4: 000d c.nop 3 - 3da6: 0100 addi s0,sp,128 - 3da8: 032c addi a1,sp,392 - 3daa: 1248 addi a0,sp,292 - 3dac: 0000 unimp - 3dae: 3d66 fld fs10,120(sp) - 3db0: 0000 unimp - 3db2: 1600 addi s0,sp,800 - 3db4: 06a0 addi s0,sp,840 - 3db6: 0000 unimp - 3db8: 031d addi t1,t1,7 - 3dba: 0000 unimp - 3dbc: e312 fsw ft4,132(sp) - 3dbe: 0008 0x8 - 3dc0: 0100 addi s0,sp,128 - 3dc2: 032c addi a1,sp,392 - 3dc4: 1248 addi a0,sp,292 - 3dc6: 0000 unimp - 3dc8: 00003d87 fld fs11,0(zero) # 0 <_start-0x80000000> - 3dcc: b818 fsd fa4,48(s0) - 3dce: 0006 c.slli zero,0x1 - 3dd0: 1200 addi s0,sp,288 - 3dd2: 0f3c addi a5,sp,920 - 3dd4: 0000 unimp - 3dd6: 2c01 jal 3fe6 <_start-0x7fffc01a> - 3dd8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3ddc: ca00 sw s0,16(a2) - 3dde: 003d c.nop 15 - 3de0: 1200 addi s0,sp,288 - 3de2: 00000d77 0xd77 - 3de6: 2c01 jal 3ff6 <_start-0x7fffc00a> - 3de8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3dec: 2000 fld fs0,0(s0) - 3dee: 003e c.slli zero,0xf - 3df0: 1200 addi s0,sp,288 - 3df2: 00000d63 beqz zero,3e0c <_start-0x7fffc1f4> - 3df6: 2c01 jal 4006 <_start-0x7fffbffa> - 3df8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3dfc: 9400 0x9400 - 3dfe: 003e c.slli zero,0xf - 3e00: 1200 addi s0,sp,288 - 3e02: 0dc9 addi s11,s11,18 - 3e04: 0000 unimp - 3e06: 2c01 jal 4016 <_start-0x7fffbfea> - 3e08: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3e0c: f500 fsw fs0,40(a0) - 3e0e: 003e c.slli zero,0xf - 3e10: 0000 unimp - 3e12: 1600 addi s0,sp,800 - 3e14: 06d0 addi a2,sp,836 - 3e16: 0000 unimp - 3e18: 00000337 lui t1,0x0 - 3e1c: 000bb317 auipc t1,0xbb - 3e20: 0100 addi s0,sp,128 - 3e22: 032d addi t1,t1,11 - 3e24: 011a slli sp,sp,0x6 - 3e26: 0000 unimp - 3e28: 7fa09103 lh sp,2042(ra) - 3e2c: 1600 addi s0,sp,800 - 3e2e: 06e8 addi a0,sp,844 - 3e30: 0000 unimp - 3e32: 0381 addi t2,t2,0 - 3e34: 0000 unimp - 3e36: 3c12 fld fs8,288(sp) - 3e38: 0100000f fence w,unknown - 3e3c: 032d addi t1,t1,11 - 3e3e: 1248 addi a0,sp,292 - 3e40: 0000 unimp - 3e42: 3f1e fld ft10,480(sp) - 3e44: 0000 unimp - 3e46: 7712 flw fa4,36(sp) - 3e48: 000d c.nop 3 - 3e4a: 0100 addi s0,sp,128 - 3e4c: 032d addi t1,t1,11 - 3e4e: 1248 addi a0,sp,292 - 3e50: 0000 unimp - 3e52: 3f32 fld ft10,296(sp) - 3e54: 0000 unimp - 3e56: 6312 flw ft6,4(sp) - 3e58: 000d c.nop 3 - 3e5a: 0100 addi s0,sp,128 - 3e5c: 032d addi t1,t1,11 - 3e5e: 1248 addi a0,sp,292 - 3e60: 0000 unimp - 3e62: 3f46 fld ft10,112(sp) - 3e64: 0000 unimp - 3e66: c912 sw tp,144(sp) - 3e68: 000d c.nop 3 - 3e6a: 0100 addi s0,sp,128 - 3e6c: 032d addi t1,t1,11 - 3e6e: 1248 addi a0,sp,292 - 3e70: 0000 unimp - 3e72: 3f5a fld ft10,432(sp) - 3e74: 0000 unimp - 3e76: 1600 addi s0,sp,800 - 3e78: 0700 addi s0,sp,896 - 3e7a: 0000 unimp - 3e7c: 03e1 addi t2,t2,24 - 3e7e: 0000 unimp - 3e80: e312 fsw ft4,132(sp) - 3e82: 0008 0x8 - 3e84: 0100 addi s0,sp,128 - 3e86: 032d addi t1,t1,11 - 3e88: 1248 addi a0,sp,292 - 3e8a: 0000 unimp - 3e8c: 00003f7b 0x3f7b - 3e90: 1818 addi a4,sp,48 - 3e92: 12000007 vlb.v v0,(zero) - 3e96: 0f3c addi a5,sp,920 - 3e98: 0000 unimp - 3e9a: 2d01 jal 44aa <_start-0x7fffbb56> - 3e9c: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3ea0: be00 fsd fs0,56(a2) - 3ea2: 1200003f 00000d77 0xd771200003f - 3eaa: 2d01 jal 44ba <_start-0x7fffbb46> - 3eac: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3eb0: 1400 addi s0,sp,544 - 3eb2: 0040 addi s0,sp,4 - 3eb4: 1200 addi s0,sp,288 - 3eb6: 00000d63 beqz zero,3ed0 <_start-0x7fffc130> - 3eba: 2d01 jal 44ca <_start-0x7fffbb36> - 3ebc: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3ec0: 9800 0x9800 - 3ec2: 0040 addi s0,sp,4 - 3ec4: 1200 addi s0,sp,288 - 3ec6: 0dc9 addi s11,s11,18 - 3ec8: 0000 unimp - 3eca: 2d01 jal 44da <_start-0x7fffbb26> - 3ecc: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 3ed0: f900 fsw fs0,48(a0) - 3ed2: 0040 addi s0,sp,4 - 3ed4: 0000 unimp - 3ed6: 1600 addi s0,sp,800 - 3ed8: 0730 addi a2,sp,904 - 3eda: 0000 unimp - 3edc: 0f89 addi t6,t6,2 - 3ede: 0000 unimp - 3ee0: 000cc917 auipc s2,0xcc - 3ee4: 0100 addi s0,sp,128 - 3ee6: 032e slli t1,t1,0xb - 3ee8: 125f 0000 9103 0x91030000125f - 3eee: 7fa0 flw fs0,120(a5) - 3ef0: 4816 lw a6,68(sp) - 3ef2: 32000007 vlseg2b.v v0,(zero) - 3ef6: 1200000f 0x1200000f - 3efa: 0e60 addi s0,sp,796 - 3efc: 0000 unimp - 3efe: 2e01 jal 420e <_start-0x7fffbdf2> - 3f00: 00011303 lh t1,0(sp) # 8803b10 <_start-0x777fc4f0> - 3f04: 2200 fld fs0,0(a2) - 3f06: 0041 c.nop 16 - 3f08: 1200 addi s0,sp,288 - 3f0a: 0e7c addi a5,sp,796 - 3f0c: 0000 unimp - 3f0e: 2e01 jal 421e <_start-0x7fffbde2> - 3f10: 00011303 lh t1,0(sp) - 3f14: a400 fsd fs0,8(s0) - 3f16: 0044 addi s1,sp,4 - 3f18: 1200 addi s0,sp,288 - 3f1a: 0ce1 addi s9,s9,24 - 3f1c: 0000 unimp - 3f1e: 2e01 jal 422e <_start-0x7fffbdd2> - 3f20: 00011303 lh t1,0(sp) - 3f24: 3900 fld fs0,48(a0) - 3f26: 0045 c.nop 17 - 3f28: 1200 addi s0,sp,288 - 3f2a: 0cfd addi s9,s9,31 - 3f2c: 0000 unimp - 3f2e: 2e01 jal 423e <_start-0x7fffbdc2> - 3f30: 00011303 lh t1,0(sp) - 3f34: 8200 0x8200 - 3f36: 0049 c.nop 18 - 3f38: 1200 addi s0,sp,288 - 3f3a: 00000d8b 0xd8b - 3f3e: 2e01 jal 424e <_start-0x7fffbdb2> - 3f40: 00011303 lh t1,0(sp) - 3f44: b800 fsd fs0,48(s0) - 3f46: 0049 c.nop 18 - 3f48: 1200 addi s0,sp,288 - 3f4a: 0d19 addi s10,s10,6 - 3f4c: 0000 unimp - 3f4e: 2e01 jal 425e <_start-0x7fffbda2> - 3f50: 00011303 lh t1,0(sp) - 3f54: 6800 flw fs0,16(s0) - 3f56: 004d c.nop 19 - 3f58: 1200 addi s0,sp,288 - 3f5a: 0e16 slli t3,t3,0x5 - 3f5c: 0000 unimp - 3f5e: 2e01 jal 426e <_start-0x7fffbd92> - 3f60: 00011303 lh t1,0(sp) - 3f64: b600 fsd fs0,40(a2) - 3f66: 004d c.nop 19 - 3f68: 1200 addi s0,sp,288 - 3f6a: 0e32 slli t3,t3,0xc - 3f6c: 0000 unimp - 3f6e: 2e01 jal 427e <_start-0x7fffbd82> - 3f70: 00011303 lh t1,0(sp) - 3f74: a800 fsd fs0,16(s0) - 3f76: 0052 c.slli zero,0x14 - 3f78: 1200 addi s0,sp,288 - 3f7a: 0ef1 addi t4,t4,28 - 3f7c: 0000 unimp - 3f7e: 2e01 jal 428e <_start-0x7fffbd72> - 3f80: 00011303 lh t1,0(sp) - 3f84: de00 sw s0,56(a2) - 3f86: 0052 c.slli zero,0x14 - 3f88: 1200 addi s0,sp,288 - 3f8a: 0f0d addi t5,t5,3 - 3f8c: 0000 unimp - 3f8e: 2e01 jal 429e <_start-0x7fffbd62> - 3f90: 00011303 lh t1,0(sp) - 3f94: ee00 fsw fs0,24(a2) - 3f96: 16000057 vmin.vv v0,v0,v0 - 3f9a: 0770 addi a2,sp,908 - 3f9c: 0000 unimp - 3f9e: 052d addi a0,a0,11 - 3fa0: 0000 unimp - 3fa2: d812 sw tp,48(sp) - 3fa4: 0005 c.nop 1 - 3fa6: 0100 addi s0,sp,128 - 3fa8: 032e slli t1,t1,0xb - 3faa: 00000113 li sp,0 - 3fae: 580c lw a1,48(s0) - 3fb0: 0000 unimp - 3fb2: dd12 sw tp,184(sp) - 3fb4: 0005 c.nop 1 - 3fb6: 0100 addi s0,sp,128 - 3fb8: 032e slli t1,t1,0xb - 3fba: 00000113 li sp,0 - 3fbe: 599a lw s3,164(sp) - 3fc0: 0000 unimp - 3fc2: e212 fsw ft4,4(sp) - 3fc4: 0005 c.nop 1 - 3fc6: 0100 addi s0,sp,128 - 3fc8: 032e slli t1,t1,0xb - 3fca: 00000113 li sp,0 - 3fce: 5da6 lw s11,104(sp) - 3fd0: 0000 unimp - 3fd2: e712 fsw ft4,140(sp) - 3fd4: 0005 c.nop 1 - 3fd6: 0100 addi s0,sp,128 - 3fd8: 032e slli t1,t1,0xb - 3fda: 00000113 li sp,0 - 3fde: 5f24 lw s1,120(a4) - 3fe0: 0000 unimp - 3fe2: 0712 slli a4,a4,0x4 - 3fe4: 0004 0x4 - 3fe6: 0100 addi s0,sp,128 - 3fe8: 032e slli t1,t1,0xb - 3fea: 0061 c.nop 24 - 3fec: 0000 unimp - 3fee: 00005f37 lui t5,0x5 - 3ff2: bd12 fsd ft4,184(sp) - 3ff4: 0004 0x4 - 3ff6: 0100 addi s0,sp,128 - 3ff8: 032e slli t1,t1,0xb - 3ffa: 0061 c.nop 24 - 3ffc: 0000 unimp - 3ffe: 5f64 lw s1,124(a4) - 4000: 0000 unimp - 4002: f112 fsw ft4,160(sp) - 4004: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4008: 032e slli t1,t1,0xb - 400a: 0061 c.nop 24 - 400c: 0000 unimp - 400e: 5f91 li t6,-28 - 4010: 0000 unimp - 4012: b812 fsd ft4,48(sp) - 4014: 0004 0x4 - 4016: 0100 addi s0,sp,128 - 4018: 032e slli t1,t1,0xb - 401a: 0061 c.nop 24 - 401c: 0000 unimp - 401e: 5fbe lw t6,236(sp) - 4020: 0000 unimp - 4022: 1600 addi s0,sp,800 - 4024: 0790 addi a2,sp,960 - 4026: 0000 unimp - 4028: 000005b3 add a1,zero,zero - 402c: d812 sw tp,48(sp) - 402e: 0005 c.nop 1 - 4030: 0100 addi s0,sp,128 - 4032: 032e slli t1,t1,0xb - 4034: 00000113 li sp,0 - 4038: 00005feb 0x5feb - 403c: dd12 sw tp,184(sp) - 403e: 0005 c.nop 1 - 4040: 0100 addi s0,sp,128 - 4042: 032e slli t1,t1,0xb - 4044: 00000113 li sp,0 - 4048: 6159 addi sp,sp,400 - 404a: 0000 unimp - 404c: e212 fsw ft4,4(sp) - 404e: 0005 c.nop 1 - 4050: 0100 addi s0,sp,128 - 4052: 032e slli t1,t1,0xb - 4054: 00000113 li sp,0 - 4058: 64f8 flw fa4,76(s1) - 405a: 0000 unimp - 405c: e712 fsw ft4,140(sp) - 405e: 0005 c.nop 1 - 4060: 0100 addi s0,sp,128 - 4062: 032e slli t1,t1,0xb - 4064: 00000113 li sp,0 - 4068: 65de flw fa1,212(sp) - 406a: 0000 unimp - 406c: 0712 slli a4,a4,0x4 - 406e: 0004 0x4 - 4070: 0100 addi s0,sp,128 - 4072: 032e slli t1,t1,0xb - 4074: 0061 c.nop 24 - 4076: 0000 unimp - 4078: 65f1 lui a1,0x1c - 407a: 0000 unimp - 407c: bd19 j 3e92 <_start-0x7fffc16e> - 407e: 0004 0x4 - 4080: 0100 addi s0,sp,128 - 4082: 032e slli t1,t1,0xb - 4084: 0061 c.nop 24 - 4086: 0000 unimp - 4088: f112 fsw ft4,160(sp) - 408a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 408e: 032e slli t1,t1,0xb - 4090: 0061 c.nop 24 - 4092: 0000 unimp - 4094: 00006613 ori a2,zero,0 - 4098: b812 fsd ft4,48(sp) - 409a: 0004 0x4 - 409c: 0100 addi s0,sp,128 - 409e: 032e slli t1,t1,0xb - 40a0: 0061 c.nop 24 - 40a2: 0000 unimp - 40a4: 6640 flw fs0,12(a2) - 40a6: 0000 unimp - 40a8: 1600 addi s0,sp,800 - 40aa: 07c0 addi s0,sp,964 - 40ac: 0000 unimp - 40ae: 0639 addi a2,a2,14 - 40b0: 0000 unimp - 40b2: d812 sw tp,48(sp) - 40b4: 0005 c.nop 1 - 40b6: 0100 addi s0,sp,128 - 40b8: 032e slli t1,t1,0xb - 40ba: 00000113 li sp,0 - 40be: 666d lui a2,0x1b - 40c0: 0000 unimp - 40c2: dd12 sw tp,184(sp) - 40c4: 0005 c.nop 1 - 40c6: 0100 addi s0,sp,128 - 40c8: 032e slli t1,t1,0xb - 40ca: 00000113 li sp,0 - 40ce: 67e0 flw fs0,76(a5) - 40d0: 0000 unimp - 40d2: e212 fsw ft4,4(sp) - 40d4: 0005 c.nop 1 - 40d6: 0100 addi s0,sp,128 - 40d8: 032e slli t1,t1,0xb - 40da: 00000113 li sp,0 - 40de: 00006b93 ori s7,zero,0 - 40e2: e712 fsw ft4,140(sp) - 40e4: 0005 c.nop 1 - 40e6: 0100 addi s0,sp,128 - 40e8: 032e slli t1,t1,0xb - 40ea: 00000113 li sp,0 - 40ee: 6cfe flw fs9,220(sp) - 40f0: 0000 unimp - 40f2: 0719 addi a4,a4,6 - 40f4: 0004 0x4 - 40f6: 0100 addi s0,sp,128 - 40f8: 032e slli t1,t1,0xb - 40fa: 0061 c.nop 24 - 40fc: 0000 unimp - 40fe: bd12 fsd ft4,184(sp) - 4100: 0004 0x4 - 4102: 0100 addi s0,sp,128 - 4104: 032e slli t1,t1,0xb - 4106: 0061 c.nop 24 - 4108: 0000 unimp - 410a: 6d11 lui s10,0x4 - 410c: 0000 unimp - 410e: f112 fsw ft4,160(sp) - 4110: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4114: 032e slli t1,t1,0xb - 4116: 0061 c.nop 24 - 4118: 0000 unimp - 411a: 00006d33 or s10,zero,zero - 411e: b812 fsd ft4,48(sp) - 4120: 0004 0x4 - 4122: 0100 addi s0,sp,128 - 4124: 032e slli t1,t1,0xb - 4126: 0061 c.nop 24 - 4128: 0000 unimp - 412a: 6d60 flw fs0,92(a0) - 412c: 0000 unimp - 412e: 1600 addi s0,sp,800 - 4130: 07e8 addi a0,sp,972 - 4132: 0000 unimp - 4134: 06b9 addi a3,a3,14 - 4136: 0000 unimp - 4138: d812 sw tp,48(sp) - 413a: 0005 c.nop 1 - 413c: 0100 addi s0,sp,128 - 413e: 032e slli t1,t1,0xb - 4140: 00000113 li sp,0 - 4144: 6d8d lui s11,0x3 - 4146: 0000 unimp - 4148: dd12 sw tp,184(sp) - 414a: 0005 c.nop 1 - 414c: 0100 addi s0,sp,128 - 414e: 032e slli t1,t1,0xb - 4150: 00000113 li sp,0 - 4154: 6e90 flw fa2,24(a3) - 4156: 0000 unimp - 4158: 0005e217 auipc tp,0x5e - 415c: 0100 addi s0,sp,128 - 415e: 032e slli t1,t1,0xb - 4160: 00000113 li sp,0 - 4164: 5f01 li t5,-32 - 4166: e712 fsw ft4,140(sp) - 4168: 0005 c.nop 1 - 416a: 0100 addi s0,sp,128 - 416c: 032e slli t1,t1,0xb - 416e: 00000113 li sp,0 - 4172: 7134 flw fa3,96(a0) - 4174: 0000 unimp - 4176: 0719 addi a4,a4,6 - 4178: 0004 0x4 - 417a: 0100 addi s0,sp,128 - 417c: 032e slli t1,t1,0xb - 417e: 0061 c.nop 24 - 4180: 0000 unimp - 4182: bd19 j 3f98 <_start-0x7fffc068> - 4184: 0004 0x4 - 4186: 0100 addi s0,sp,128 - 4188: 032e slli t1,t1,0xb - 418a: 0061 c.nop 24 - 418c: 0000 unimp - 418e: f112 fsw ft4,160(sp) - 4190: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4194: 032e slli t1,t1,0xb - 4196: 0061 c.nop 24 - 4198: 0000 unimp - 419a: 00007147 fmsub.s ft2,ft0,ft0,ft0 - 419e: b812 fsd ft4,48(sp) - 41a0: 0004 0x4 - 41a2: 0100 addi s0,sp,128 - 41a4: 032e slli t1,t1,0xb - 41a6: 0061 c.nop 24 - 41a8: 0000 unimp - 41aa: 7174 flw fa3,100(a0) - 41ac: 0000 unimp - 41ae: 1600 addi s0,sp,800 - 41b0: 0808 addi a0,sp,16 - 41b2: 0000 unimp - 41b4: 0000073f 0005d812 0x5d8120000073f - 41bc: 0100 addi s0,sp,128 - 41be: 032e slli t1,t1,0xb - 41c0: 00000113 li sp,0 - 41c4: 71a1 lui gp,0xfffe8 - 41c6: 0000 unimp - 41c8: dd12 sw tp,184(sp) - 41ca: 0005 c.nop 1 - 41cc: 0100 addi s0,sp,128 - 41ce: 032e slli t1,t1,0xb - 41d0: 00000113 li sp,0 - 41d4: 730a flw ft6,160(sp) - 41d6: 0000 unimp - 41d8: e212 fsw ft4,4(sp) - 41da: 0005 c.nop 1 - 41dc: 0100 addi s0,sp,128 - 41de: 032e slli t1,t1,0xb - 41e0: 00000113 li sp,0 - 41e4: 7659 lui a2,0xffff6 - 41e6: 0000 unimp - 41e8: e712 fsw ft4,140(sp) - 41ea: 0005 c.nop 1 - 41ec: 0100 addi s0,sp,128 - 41ee: 032e slli t1,t1,0xb - 41f0: 00000113 li sp,0 - 41f4: 7726 flw fa4,104(sp) - 41f6: 0000 unimp - 41f8: 0712 slli a4,a4,0x4 - 41fa: 0004 0x4 - 41fc: 0100 addi s0,sp,128 - 41fe: 032e slli t1,t1,0xb - 4200: 0061 c.nop 24 - 4202: 0000 unimp - 4204: 7739 lui a4,0xfffee - 4206: 0000 unimp - 4208: bd19 j 401e <_start-0x7fffbfe2> - 420a: 0004 0x4 - 420c: 0100 addi s0,sp,128 - 420e: 032e slli t1,t1,0xb - 4210: 0061 c.nop 24 - 4212: 0000 unimp - 4214: f112 fsw ft4,160(sp) - 4216: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 421a: 032e slli t1,t1,0xb - 421c: 0061 c.nop 24 - 421e: 0000 unimp - 4220: 0000775b 0x775b - 4224: b812 fsd ft4,48(sp) - 4226: 0004 0x4 - 4228: 0100 addi s0,sp,128 - 422a: 032e slli t1,t1,0xb - 422c: 0061 c.nop 24 - 422e: 0000 unimp - 4230: 7788 flw fa0,40(a5) - 4232: 0000 unimp - 4234: 1600 addi s0,sp,800 - 4236: 0838 addi a4,sp,24 - 4238: 0000 unimp - 423a: 07c9 addi a5,a5,18 - 423c: 0000 unimp - 423e: d812 sw tp,48(sp) - 4240: 0005 c.nop 1 - 4242: 0100 addi s0,sp,128 - 4244: 032e slli t1,t1,0xb - 4246: 00000113 li sp,0 - 424a: 77a6 flw fa5,104(sp) - 424c: 0000 unimp - 424e: dd12 sw tp,184(sp) - 4250: 0005 c.nop 1 - 4252: 0100 addi s0,sp,128 - 4254: 032e slli t1,t1,0xb - 4256: 00000113 li sp,0 - 425a: 0000790f 0x790f - 425e: e212 fsw ft4,4(sp) - 4260: 0005 c.nop 1 - 4262: 0100 addi s0,sp,128 - 4264: 032e slli t1,t1,0xb - 4266: 00000113 li sp,0 - 426a: 7c9c flw fa5,56(s1) - 426c: 0000 unimp - 426e: e712 fsw ft4,140(sp) - 4270: 0005 c.nop 1 - 4272: 0100 addi s0,sp,128 - 4274: 032e slli t1,t1,0xb - 4276: 00000113 li sp,0 - 427a: 7dff 0x7dff - 427c: 0000 unimp - 427e: 0712 slli a4,a4,0x4 - 4280: 0004 0x4 - 4282: 0100 addi s0,sp,128 - 4284: 032e slli t1,t1,0xb - 4286: 0061 c.nop 24 - 4288: 0000 unimp - 428a: 7e12 flw ft8,36(sp) - 428c: 0000 unimp - 428e: bd12 fsd ft4,184(sp) - 4290: 0004 0x4 - 4292: 0100 addi s0,sp,128 - 4294: 032e slli t1,t1,0xb - 4296: 0061 c.nop 24 - 4298: 0000 unimp - 429a: 00007e3f 0003f112 0x3f11200007e3f - 42a2: 0100 addi s0,sp,128 - 42a4: 032e slli t1,t1,0xb - 42a6: 0061 c.nop 24 - 42a8: 0000 unimp - 42aa: 7e61 lui t3,0xffff8 - 42ac: 0000 unimp - 42ae: b812 fsd ft4,48(sp) - 42b0: 0004 0x4 - 42b2: 0100 addi s0,sp,128 - 42b4: 032e slli t1,t1,0xb - 42b6: 0061 c.nop 24 - 42b8: 0000 unimp - 42ba: 7e8e flw ft9,224(sp) - 42bc: 0000 unimp - 42be: 1600 addi s0,sp,800 - 42c0: 0878 addi a4,sp,28 - 42c2: 0000 unimp - 42c4: 000007f3 0x7f3 - 42c8: 8412 mv s0,tp - 42ca: 0100000b 0x100000b - 42ce: 032e slli t1,t1,0xb - 42d0: 00000113 li sp,0 - 42d4: 00007ebb 0x7ebb - 42d8: 2b12 fld fs6,256(sp) - 42da: 0100000b 0x100000b - 42de: 032e slli t1,t1,0xb - 42e0: 00000113 li sp,0 - 42e4: 7f05 lui t5,0xfffe1 - 42e6: 0000 unimp - 42e8: 1600 addi s0,sp,800 - 42ea: 08b0 addi a2,sp,88 - 42ec: 0000 unimp - 42ee: 081d addi a6,a6,7 - 42f0: 0000 unimp - 42f2: 8412 mv s0,tp - 42f4: 0100000b 0x100000b - 42f8: 032e slli t1,t1,0xb - 42fa: 00000113 li sp,0 - 42fe: 7f6d lui t5,0xffffb - 4300: 0000 unimp - 4302: 2b12 fld fs6,256(sp) - 4304: 0100000b 0x100000b - 4308: 032e slli t1,t1,0xb - 430a: 00000113 li sp,0 - 430e: 857a mv a0,t5 - 4310: 0000 unimp - 4312: 1600 addi s0,sp,800 - 4314: 08d0 addi a2,sp,84 - 4316: 0000 unimp - 4318: 00000847 fmsub.s fa6,ft0,ft0,ft0,rne - 431c: 8412 mv s0,tp - 431e: 0100000b 0x100000b - 4322: 032e slli t1,t1,0xb - 4324: 00000113 li sp,0 - 4328: 85c6 mv a1,a7 - 432a: 0000 unimp - 432c: 2b12 fld fs6,256(sp) - 432e: 0100000b 0x100000b - 4332: 032e slli t1,t1,0xb - 4334: 00000113 li sp,0 - 4338: 8632 mv a2,a2 - 433a: 0000 unimp - 433c: 1600 addi s0,sp,800 - 433e: 0900 addi s0,sp,144 - 4340: 0000 unimp - 4342: 0871 addi a6,a6,28 - 4344: 0000 unimp - 4346: 8412 mv s0,tp - 4348: 0100000b 0x100000b - 434c: 032e slli t1,t1,0xb - 434e: 00000113 li sp,0 - 4352: 867e mv a2,t6 - 4354: 0000 unimp - 4356: 2b12 fld fs6,256(sp) - 4358: 0100000b 0x100000b - 435c: 032e slli t1,t1,0xb - 435e: 00000113 li sp,0 - 4362: 8846 mv a6,a7 - 4364: 0000 unimp - 4366: 1600 addi s0,sp,800 - 4368: 0940 addi s0,sp,148 - 436a: 0000 unimp - 436c: 0000089b 0x89b - 4370: 8412 mv s0,tp - 4372: 0100000b 0x100000b - 4376: 032e slli t1,t1,0xb - 4378: 00000113 li sp,0 - 437c: 8f41 or a4,a4,s0 - 437e: 0000 unimp - 4380: 2b12 fld fs6,256(sp) - 4382: 0100000b 0x100000b - 4386: 032e slli t1,t1,0xb - 4388: 00000113 li sp,0 - 438c: 9528 0x9528 - 438e: 0000 unimp - 4390: 1600 addi s0,sp,800 - 4392: 0978 addi a4,sp,156 - 4394: 0000 unimp - 4396: 0921 addi s2,s2,8 - 4398: 0000 unimp - 439a: d812 sw tp,48(sp) - 439c: 0005 c.nop 1 - 439e: 0100 addi s0,sp,128 - 43a0: 032e slli t1,t1,0xb - 43a2: 00000113 li sp,0 - 43a6: 9574 0x9574 - 43a8: 0000 unimp - 43aa: dd12 sw tp,184(sp) - 43ac: 0005 c.nop 1 - 43ae: 0100 addi s0,sp,128 - 43b0: 032e slli t1,t1,0xb - 43b2: 00000113 li sp,0 - 43b6: 96be add a3,a3,a5 - 43b8: 0000 unimp - 43ba: e212 fsw ft4,4(sp) - 43bc: 0005 c.nop 1 - 43be: 0100 addi s0,sp,128 - 43c0: 032e slli t1,t1,0xb - 43c2: 00000113 li sp,0 - 43c6: 99f1 andi a1,a1,-4 - 43c8: 0000 unimp - 43ca: e712 fsw ft4,140(sp) - 43cc: 0005 c.nop 1 - 43ce: 0100 addi s0,sp,128 - 43d0: 032e slli t1,t1,0xb - 43d2: 00000113 li sp,0 - 43d6: 00009a63 bnez ra,43ea <_start-0x7fffbc16> - 43da: 0712 slli a4,a4,0x4 - 43dc: 0004 0x4 - 43de: 0100 addi s0,sp,128 - 43e0: 032e slli t1,t1,0xb - 43e2: 0061 c.nop 24 - 43e4: 0000 unimp - 43e6: 9a76 add s4,s4,t4 - 43e8: 0000 unimp - 43ea: bd19 j 4200 <_start-0x7fffbe00> - 43ec: 0004 0x4 - 43ee: 0100 addi s0,sp,128 - 43f0: 032e slli t1,t1,0xb - 43f2: 0061 c.nop 24 - 43f4: 0000 unimp - 43f6: f112 fsw ft4,160(sp) - 43f8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 43fc: 032e slli t1,t1,0xb - 43fe: 0061 c.nop 24 - 4400: 0000 unimp - 4402: 9a98 0x9a98 - 4404: 0000 unimp - 4406: b812 fsd ft4,48(sp) - 4408: 0004 0x4 - 440a: 0100 addi s0,sp,128 - 440c: 032e slli t1,t1,0xb - 440e: 0061 c.nop 24 - 4410: 0000 unimp - 4412: 9ac5 andi a3,a3,-15 - 4414: 0000 unimp - 4416: 1600 addi s0,sp,800 - 4418: 09b8 addi a4,sp,216 - 441a: 0000 unimp - 441c: 000009a7 vsb.v v19,(zero),v0.t - 4420: d812 sw tp,48(sp) - 4422: 0005 c.nop 1 - 4424: 0100 addi s0,sp,128 - 4426: 032e slli t1,t1,0xb - 4428: 00000113 li sp,0 - 442c: 9af2 add s5,s5,t3 - 442e: 0000 unimp - 4430: dd12 sw tp,184(sp) - 4432: 0005 c.nop 1 - 4434: 0100 addi s0,sp,128 - 4436: 032e slli t1,t1,0xb - 4438: 00000113 li sp,0 - 443c: 9c3c 0x9c3c - 443e: 0000 unimp - 4440: e212 fsw ft4,4(sp) - 4442: 0005 c.nop 1 - 4444: 0100 addi s0,sp,128 - 4446: 032e slli t1,t1,0xb - 4448: 00000113 li sp,0 - 444c: 9f36 add t5,t5,a3 - 444e: 0000 unimp - 4450: e712 fsw ft4,140(sp) - 4452: 0005 c.nop 1 - 4454: 0100 addi s0,sp,128 - 4456: 032e slli t1,t1,0xb - 4458: 00000113 li sp,0 - 445c: a07d j 450a <_start-0x7fffbaf6> - 445e: 0000 unimp - 4460: 0719 addi a4,a4,6 - 4462: 0004 0x4 - 4464: 0100 addi s0,sp,128 - 4466: 032e slli t1,t1,0xb - 4468: 0061 c.nop 24 - 446a: 0000 unimp - 446c: bd12 fsd ft4,184(sp) - 446e: 0004 0x4 - 4470: 0100 addi s0,sp,128 - 4472: 032e slli t1,t1,0xb - 4474: 0061 c.nop 24 - 4476: 0000 unimp - 4478: a090 fsd fa2,0(s1) - 447a: 0000 unimp - 447c: f112 fsw ft4,160(sp) - 447e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4482: 032e slli t1,t1,0xb - 4484: 0061 c.nop 24 - 4486: 0000 unimp - 4488: a0b2 fsd fa2,64(sp) - 448a: 0000 unimp - 448c: b812 fsd ft4,48(sp) - 448e: 0004 0x4 - 4490: 0100 addi s0,sp,128 - 4492: 032e slli t1,t1,0xb - 4494: 0061 c.nop 24 - 4496: 0000 unimp - 4498: a0df 0000 1600 0x16000000a0df - 449e: 09e0 addi s0,sp,220 - 44a0: 0000 unimp - 44a2: 00000a27 vsb.v v20,(zero),v0.t - 44a6: d812 sw tp,48(sp) - 44a8: 0005 c.nop 1 - 44aa: 0100 addi s0,sp,128 - 44ac: 032e slli t1,t1,0xb - 44ae: 00000113 li sp,0 - 44b2: a10c fsd fa1,0(a0) - 44b4: 0000 unimp - 44b6: dd12 sw tp,184(sp) - 44b8: 0005 c.nop 1 - 44ba: 0100 addi s0,sp,128 - 44bc: 032e slli t1,t1,0xb - 44be: 00000113 li sp,0 - 44c2: a20a fsd ft2,256(sp) - 44c4: 0000 unimp - 44c6: 0005e217 auipc tp,0x5e - 44ca: 0100 addi s0,sp,128 - 44cc: 032e slli t1,t1,0xb - 44ce: 00000113 li sp,0 - 44d2: 6c01 0x6c01 - 44d4: e712 fsw ft4,140(sp) - 44d6: 0005 c.nop 1 - 44d8: 0100 addi s0,sp,128 - 44da: 032e slli t1,t1,0xb - 44dc: 00000113 li sp,0 - 44e0: a456 fsd fs5,8(sp) - 44e2: 0000 unimp - 44e4: 0719 addi a4,a4,6 - 44e6: 0004 0x4 - 44e8: 0100 addi s0,sp,128 - 44ea: 032e slli t1,t1,0xb - 44ec: 0061 c.nop 24 - 44ee: 0000 unimp - 44f0: bd19 j 4306 <_start-0x7fffbcfa> - 44f2: 0004 0x4 - 44f4: 0100 addi s0,sp,128 - 44f6: 032e slli t1,t1,0xb - 44f8: 0061 c.nop 24 - 44fa: 0000 unimp - 44fc: f112 fsw ft4,160(sp) - 44fe: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4502: 032e slli t1,t1,0xb - 4504: 0061 c.nop 24 - 4506: 0000 unimp - 4508: a469 j 4792 <_start-0x7fffb86e> - 450a: 0000 unimp - 450c: b812 fsd ft4,48(sp) - 450e: 0004 0x4 - 4510: 0100 addi s0,sp,128 - 4512: 032e slli t1,t1,0xb - 4514: 0061 c.nop 24 - 4516: 0000 unimp - 4518: a496 fsd ft5,72(sp) - 451a: 0000 unimp - 451c: 1600 addi s0,sp,800 - 451e: 09f8 addi a4,sp,220 - 4520: 0000 unimp - 4522: 00000aab 0xaab - 4526: d812 sw tp,48(sp) - 4528: 0005 c.nop 1 - 452a: 0100 addi s0,sp,128 - 452c: 032e slli t1,t1,0xb - 452e: 00000113 li sp,0 - 4532: a4b4 fsd fa3,72(s1) - 4534: 0000 unimp - 4536: dd12 sw tp,184(sp) - 4538: 0005 c.nop 1 - 453a: 0100 addi s0,sp,128 - 453c: 032e slli t1,t1,0xb - 453e: 00000113 li sp,0 - 4542: a59d j 4ba8 <_start-0x7fffb458> - 4544: 0000 unimp - 4546: 0005e217 auipc tp,0x5e - 454a: 0100 addi s0,sp,128 - 454c: 032e slli t1,t1,0xb - 454e: 00000113 li sp,0 - 4552: 6c01 0x6c01 - 4554: e712 fsw ft4,140(sp) - 4556: 0005 c.nop 1 - 4558: 0100 addi s0,sp,128 - 455a: 032e slli t1,t1,0xb - 455c: 00000113 li sp,0 - 4560: a822 fsd fs0,16(sp) - 4562: 0000 unimp - 4564: 0712 slli a4,a4,0x4 - 4566: 0004 0x4 - 4568: 0100 addi s0,sp,128 - 456a: 032e slli t1,t1,0xb - 456c: 0061 c.nop 24 - 456e: 0000 unimp - 4570: a835 j 45ac <_start-0x7fffba54> - 4572: 0000 unimp - 4574: bd19 j 438a <_start-0x7fffbc76> - 4576: 0004 0x4 - 4578: 0100 addi s0,sp,128 - 457a: 032e slli t1,t1,0xb - 457c: 0061 c.nop 24 - 457e: 0000 unimp - 4580: f112 fsw ft4,160(sp) - 4582: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4586: 032e slli t1,t1,0xb - 4588: 0061 c.nop 24 - 458a: 0000 unimp - 458c: 0000a857 vredsum.vs v16,v0,v1,v0.t - 4590: b812 fsd ft4,48(sp) - 4592: 0004 0x4 - 4594: 0100 addi s0,sp,128 - 4596: 032e slli t1,t1,0xb - 4598: 0061 c.nop 24 - 459a: 0000 unimp - 459c: a884 fsd fs1,16(s1) - 459e: 0000 unimp - 45a0: 1600 addi s0,sp,800 - 45a2: 0a28 addi a0,sp,280 - 45a4: 0000 unimp - 45a6: 0acd addi s5,s5,19 - 45a8: 0000 unimp - 45aa: 8419 srai s0,s0,0x6 - 45ac: 0100000b 0x100000b - 45b0: 032e slli t1,t1,0xb - 45b2: 00000113 li sp,0 - 45b6: 2b19 jal 4acc <_start-0x7fffb534> - 45b8: 0100000b 0x100000b - 45bc: 032e slli t1,t1,0xb - 45be: 00000113 li sp,0 - 45c2: 1600 addi s0,sp,800 - 45c4: 0a60 addi s0,sp,284 - 45c6: 0000 unimp - 45c8: 00000aef jal s5,45c8 <_start-0x7fffba38> - 45cc: 8419 srai s0,s0,0x6 - 45ce: 0100000b 0x100000b - 45d2: 032e slli t1,t1,0xb - 45d4: 00000113 li sp,0 - 45d8: 2b19 jal 4aee <_start-0x7fffb512> - 45da: 0100000b 0x100000b - 45de: 032e slli t1,t1,0xb - 45e0: 00000113 li sp,0 - 45e4: 1600 addi s0,sp,800 - 45e6: 0aa8 addi a0,sp,344 - 45e8: 0000 unimp - 45ea: 0b19 addi s6,s6,6 - 45ec: 0000 unimp - 45ee: 8412 mv s0,tp - 45f0: 0100000b 0x100000b - 45f4: 032e slli t1,t1,0xb - 45f6: 00000113 li sp,0 - 45fa: a8b1 j 4656 <_start-0x7fffb9aa> - 45fc: 0000 unimp - 45fe: 2b12 fld fs6,256(sp) - 4600: 0100000b 0x100000b - 4604: 032e slli t1,t1,0xb - 4606: 00000113 li sp,0 - 460a: a8c4 fsd fs1,144(s1) - 460c: 0000 unimp - 460e: 1600 addi s0,sp,800 - 4610: 0ae8 addi a0,sp,348 - 4612: 0000 unimp - 4614: 00000b3b 0xb3b - 4618: 8419 srai s0,s0,0x6 - 461a: 0100000b 0x100000b - 461e: 032e slli t1,t1,0xb - 4620: 00000113 li sp,0 - 4624: 2b19 jal 4b3a <_start-0x7fffb4c6> - 4626: 0100000b 0x100000b - 462a: 032e slli t1,t1,0xb - 462c: 00000113 li sp,0 - 4630: 1600 addi s0,sp,800 - 4632: 0b18 addi a4,sp,400 - 4634: 0000 unimp - 4636: 00000bbf 0005d812 0x5d81200000bbf - 463e: 0100 addi s0,sp,128 - 4640: 032e slli t1,t1,0xb - 4642: 00000113 li sp,0 - 4646: a921 j 4a5e <_start-0x7fffb5a2> - 4648: 0000 unimp - 464a: dd12 sw tp,184(sp) - 464c: 0005 c.nop 1 - 464e: 0100 addi s0,sp,128 - 4650: 032e slli t1,t1,0xb - 4652: 00000113 li sp,0 - 4656: a9f5 j 4b52 <_start-0x7fffb4ae> - 4658: 0000 unimp - 465a: 0005e217 auipc tp,0x5e - 465e: 0100 addi s0,sp,128 - 4660: 032e slli t1,t1,0xb - 4662: 00000113 li sp,0 - 4666: 6401 0x6401 - 4668: e712 fsw ft4,140(sp) - 466a: 0005 c.nop 1 - 466c: 0100 addi s0,sp,128 - 466e: 032e slli t1,t1,0xb - 4670: 00000113 li sp,0 - 4674: abe9 j 4c4e <_start-0x7fffb3b2> - 4676: 0000 unimp - 4678: 0712 slli a4,a4,0x4 - 467a: 0004 0x4 - 467c: 0100 addi s0,sp,128 - 467e: 032e slli t1,t1,0xb - 4680: 0061 c.nop 24 - 4682: 0000 unimp - 4684: abfc fsd fa5,208(a5) - 4686: 0000 unimp - 4688: bd19 j 449e <_start-0x7fffbb62> - 468a: 0004 0x4 - 468c: 0100 addi s0,sp,128 - 468e: 032e slli t1,t1,0xb - 4690: 0061 c.nop 24 - 4692: 0000 unimp - 4694: f112 fsw ft4,160(sp) - 4696: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 469a: 032e slli t1,t1,0xb - 469c: 0061 c.nop 24 - 469e: 0000 unimp - 46a0: ac1e fsd ft7,24(sp) - 46a2: 0000 unimp - 46a4: b812 fsd ft4,48(sp) - 46a6: 0004 0x4 - 46a8: 0100 addi s0,sp,128 - 46aa: 032e slli t1,t1,0xb - 46ac: 0061 c.nop 24 - 46ae: 0000 unimp - 46b0: 0000ac4b fnmsub.s fs8,ft1,ft0,ft0,rdn - 46b4: 1600 addi s0,sp,800 - 46b6: 0b38 addi a4,sp,408 - 46b8: 0000 unimp - 46ba: 0c41 addi s8,s8,16 - 46bc: 0000 unimp - 46be: d812 sw tp,48(sp) - 46c0: 0005 c.nop 1 - 46c2: 0100 addi s0,sp,128 - 46c4: 032e slli t1,t1,0xb - 46c6: 00000113 li sp,0 - 46ca: ac69 j 4964 <_start-0x7fffb69c> - 46cc: 0000 unimp - 46ce: dd12 sw tp,184(sp) - 46d0: 0005 c.nop 1 - 46d2: 0100 addi s0,sp,128 - 46d4: 032e slli t1,t1,0xb - 46d6: 00000113 li sp,0 - 46da: 0000ad33 sltz s10,ra - 46de: e212 fsw ft4,4(sp) - 46e0: 0005 c.nop 1 - 46e2: 0100 addi s0,sp,128 - 46e4: 032e slli t1,t1,0xb - 46e6: 00000113 li sp,0 - 46ea: af36 fsd fa3,408(sp) - 46ec: 0000 unimp - 46ee: e712 fsw ft4,140(sp) - 46f0: 0005 c.nop 1 - 46f2: 0100 addi s0,sp,128 - 46f4: 032e slli t1,t1,0xb - 46f6: 00000113 li sp,0 - 46fa: afa8 fsd fa0,88(a5) - 46fc: 0000 unimp - 46fe: 0719 addi a4,a4,6 - 4700: 0004 0x4 - 4702: 0100 addi s0,sp,128 - 4704: 032e slli t1,t1,0xb - 4706: 0061 c.nop 24 - 4708: 0000 unimp - 470a: bd19 j 4520 <_start-0x7fffbae0> - 470c: 0004 0x4 - 470e: 0100 addi s0,sp,128 - 4710: 032e slli t1,t1,0xb - 4712: 0061 c.nop 24 - 4714: 0000 unimp - 4716: f112 fsw ft4,160(sp) - 4718: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 471c: 032e slli t1,t1,0xb - 471e: 0061 c.nop 24 - 4720: 0000 unimp - 4722: 0000afbb 0xafbb - 4726: b812 fsd ft4,48(sp) - 4728: 0004 0x4 - 472a: 0100 addi s0,sp,128 - 472c: 032e slli t1,t1,0xb - 472e: 0061 c.nop 24 - 4730: 0000 unimp - 4732: afe8 fsd fa0,216(a5) - 4734: 0000 unimp - 4736: 1600 addi s0,sp,800 - 4738: 0b58 addi a4,sp,404 - 473a: 0000 unimp - 473c: 00000cc3 fmadd.s fs9,ft0,ft0,ft0,rne - 4740: d812 sw tp,48(sp) - 4742: 0005 c.nop 1 - 4744: 0100 addi s0,sp,128 - 4746: 032e slli t1,t1,0xb - 4748: 00000113 li sp,0 - 474c: b015 j 3f70 <_start-0x7fffc090> - 474e: 0000 unimp - 4750: dd12 sw tp,184(sp) - 4752: 0005 c.nop 1 - 4754: 0100 addi s0,sp,128 - 4756: 032e slli t1,t1,0xb - 4758: 00000113 li sp,0 - 475c: b0ca fsd fs2,96(sp) - 475e: 0000 unimp - 4760: e212 fsw ft4,4(sp) - 4762: 0005 c.nop 1 - 4764: 0100 addi s0,sp,128 - 4766: 032e slli t1,t1,0xb - 4768: 00000113 li sp,0 - 476c: b2a5 j 40d4 <_start-0x7fffbf2c> - 476e: 0000 unimp - 4770: e712 fsw ft4,140(sp) - 4772: 0005 c.nop 1 - 4774: 0100 addi s0,sp,128 - 4776: 032e slli t1,t1,0xb - 4778: 00000113 li sp,0 - 477c: 0000b357 vadd.vi v6,v0,1,v0.t - 4780: 0719 addi a4,a4,6 - 4782: 0004 0x4 - 4784: 0100 addi s0,sp,128 - 4786: 032e slli t1,t1,0xb - 4788: 0061 c.nop 24 - 478a: 0000 unimp - 478c: bd19 j 45a2 <_start-0x7fffba5e> - 478e: 0004 0x4 - 4790: 0100 addi s0,sp,128 - 4792: 032e slli t1,t1,0xb - 4794: 0061 c.nop 24 - 4796: 0000 unimp - 4798: f112 fsw ft4,160(sp) - 479a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 479e: 032e slli t1,t1,0xb - 47a0: 0061 c.nop 24 - 47a2: 0000 unimp - 47a4: b36a fsd fs10,416(sp) - 47a6: 0000 unimp - 47a8: b812 fsd ft4,48(sp) - 47aa: 0004 0x4 - 47ac: 0100 addi s0,sp,128 - 47ae: 032e slli t1,t1,0xb - 47b0: 0061 c.nop 24 - 47b2: 0000 unimp - 47b4: 0000b397 auipc t2,0xb - 47b8: 1600 addi s0,sp,800 - 47ba: 0b78 addi a4,sp,412 - 47bc: 0000 unimp - 47be: 0d49 addi s10,s10,18 - 47c0: 0000 unimp - 47c2: d812 sw tp,48(sp) - 47c4: 0005 c.nop 1 - 47c6: 0100 addi s0,sp,128 - 47c8: 032e slli t1,t1,0xb - 47ca: 00000113 li sp,0 - 47ce: b3c4 fsd fs1,160(a5) - 47d0: 0000 unimp - 47d2: dd12 sw tp,184(sp) - 47d4: 0005 c.nop 1 - 47d6: 0100 addi s0,sp,128 - 47d8: 032e slli t1,t1,0xb - 47da: 00000113 li sp,0 - 47de: b479 j 426c <_start-0x7fffbd94> - 47e0: 0000 unimp - 47e2: e212 fsw ft4,4(sp) - 47e4: 0005 c.nop 1 - 47e6: 0100 addi s0,sp,128 - 47e8: 032e slli t1,t1,0xb - 47ea: 00000113 li sp,0 - 47ee: b650 fsd fa2,168(a2) - 47f0: 0000 unimp - 47f2: e712 fsw ft4,140(sp) - 47f4: 0005 c.nop 1 - 47f6: 0100 addi s0,sp,128 - 47f8: 032e slli t1,t1,0xb - 47fa: 00000113 li sp,0 - 47fe: b6c2 fsd fa6,360(sp) - 4800: 0000 unimp - 4802: 0712 slli a4,a4,0x4 - 4804: 0004 0x4 - 4806: 0100 addi s0,sp,128 - 4808: 032e slli t1,t1,0xb - 480a: 0061 c.nop 24 - 480c: 0000 unimp - 480e: b6d5 j 43f2 <_start-0x7fffbc0e> - 4810: 0000 unimp - 4812: bd19 j 4628 <_start-0x7fffb9d8> - 4814: 0004 0x4 - 4816: 0100 addi s0,sp,128 - 4818: 032e slli t1,t1,0xb - 481a: 0061 c.nop 24 - 481c: 0000 unimp - 481e: f112 fsw ft4,160(sp) - 4820: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4824: 032e slli t1,t1,0xb - 4826: 0061 c.nop 24 - 4828: 0000 unimp - 482a: 0000b6f7 0xb6f7 - 482e: b812 fsd ft4,48(sp) - 4830: 0004 0x4 - 4832: 0100 addi s0,sp,128 - 4834: 032e slli t1,t1,0xb - 4836: 0061 c.nop 24 - 4838: 0000 unimp - 483a: b724 fsd fs1,104(a4) - 483c: 0000 unimp - 483e: 1600 addi s0,sp,800 - 4840: 0b90 addi a2,sp,464 - 4842: 0000 unimp - 4844: 00000dcb fnmsub.s fs11,ft0,ft0,ft0,rne - 4848: d812 sw tp,48(sp) - 484a: 0005 c.nop 1 - 484c: 0100 addi s0,sp,128 - 484e: 032e slli t1,t1,0xb - 4850: 00000113 li sp,0 - 4854: b751 j 47d8 <_start-0x7fffb828> - 4856: 0000 unimp - 4858: dd12 sw tp,184(sp) - 485a: 0005 c.nop 1 - 485c: 0100 addi s0,sp,128 - 485e: 032e slli t1,t1,0xb - 4860: 00000113 li sp,0 - 4864: b7dc fsd fa5,168(a5) - 4866: 0000 unimp - 4868: e212 fsw ft4,4(sp) - 486a: 0005 c.nop 1 - 486c: 0100 addi s0,sp,128 - 486e: 032e slli t1,t1,0xb - 4870: 00000113 li sp,0 - 4874: b8f4 fsd fa3,240(s1) - 4876: 0000 unimp - 4878: e712 fsw ft4,140(sp) - 487a: 0005 c.nop 1 - 487c: 0100 addi s0,sp,128 - 487e: 032e slli t1,t1,0xb - 4880: 00000113 li sp,0 - 4884: b97c fsd fa5,240(a0) - 4886: 0000 unimp - 4888: 0719 addi a4,a4,6 - 488a: 0004 0x4 - 488c: 0100 addi s0,sp,128 - 488e: 032e slli t1,t1,0xb - 4890: 0061 c.nop 24 - 4892: 0000 unimp - 4894: bd19 j 46aa <_start-0x7fffb956> - 4896: 0004 0x4 - 4898: 0100 addi s0,sp,128 - 489a: 032e slli t1,t1,0xb - 489c: 0061 c.nop 24 - 489e: 0000 unimp - 48a0: f112 fsw ft4,160(sp) - 48a2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 48a6: 032e slli t1,t1,0xb - 48a8: 0061 c.nop 24 - 48aa: 0000 unimp - 48ac: 0000b98f 0xb98f - 48b0: b812 fsd ft4,48(sp) - 48b2: 0004 0x4 - 48b4: 0100 addi s0,sp,128 - 48b6: 032e slli t1,t1,0xb - 48b8: 0061 c.nop 24 - 48ba: 0000 unimp - 48bc: b9bc fsd fa5,112(a1) - 48be: 0000 unimp - 48c0: 1600 addi s0,sp,800 - 48c2: 0bc0 addi s0,sp,468 - 48c4: 0000 unimp - 48c6: 0df5 addi s11,s11,29 - 48c8: 0000 unimp - 48ca: 8412 mv s0,tp - 48cc: 0100000b 0x100000b - 48d0: 032e slli t1,t1,0xb - 48d2: 00000113 li sp,0 - 48d6: b9da fsd fs6,240(sp) - 48d8: 0000 unimp - 48da: 2b12 fld fs6,256(sp) - 48dc: 0100000b 0x100000b - 48e0: 032e slli t1,t1,0xb - 48e2: 00000113 li sp,0 - 48e6: b9ed j 45e0 <_start-0x7fffba20> - 48e8: 0000 unimp - 48ea: 1600 addi s0,sp,800 - 48ec: 0c00 addi s0,sp,528 - 48ee: 0000 unimp - 48f0: 0e1f 0000 8412 0x841200000e1f - 48f6: 0100000b 0x100000b - 48fa: 032e slli t1,t1,0xb - 48fc: 00000113 li sp,0 - 4900: ba1e fsd ft7,304(sp) - 4902: 0000 unimp - 4904: 2b12 fld fs6,256(sp) - 4906: 0100000b 0x100000b - 490a: 032e slli t1,t1,0xb - 490c: 00000113 li sp,0 - 4910: ba31 j 422c <_start-0x7fffbdd4> - 4912: 0000 unimp - 4914: 1600 addi s0,sp,800 - 4916: 0c40 addi s0,sp,532 - 4918: 0000 unimp - 491a: 0e49 addi t3,t3,18 - 491c: 0000 unimp - 491e: 8412 mv s0,tp - 4920: 0100000b 0x100000b - 4924: 032e slli t1,t1,0xb - 4926: 00000113 li sp,0 - 492a: ba7d j 42e8 <_start-0x7fffbd18> - 492c: 0000 unimp - 492e: 2b12 fld fs6,256(sp) - 4930: 0100000b 0x100000b - 4934: 032e slli t1,t1,0xb - 4936: 00000113 li sp,0 - 493a: 0000bc0f 0xbc0f - 493e: 1600 addi s0,sp,800 - 4940: 0c70 addi a2,sp,540 - 4942: 0000 unimp - 4944: 00000e73 0xe73 - 4948: 8412 mv s0,tp - 494a: 0100000b 0x100000b - 494e: 032e slli t1,t1,0xb - 4950: 00000113 li sp,0 - 4954: bea1 j 44ac <_start-0x7fffbb54> - 4956: 0000 unimp - 4958: 2b12 fld fs6,256(sp) - 495a: 0100000b 0x100000b - 495e: 032e slli t1,t1,0xb - 4960: 00000113 li sp,0 - 4964: 0000c1bf 0cc81600 0xcc816000000c1bf - 496c: 0000 unimp - 496e: 0e99 addi t4,t4,6 - 4970: 0000 unimp - 4972: 8419 srai s0,s0,0x6 - 4974: 0100000b 0x100000b - 4978: 032e slli t1,t1,0xb - 497a: 00000113 li sp,0 - 497e: 2b12 fld fs6,256(sp) - 4980: 0100000b 0x100000b - 4984: 032e slli t1,t1,0xb - 4986: 00000113 li sp,0 - 498a: c1ed beqz a1,4a6c <_start-0x7fffb594> - 498c: 0000 unimp - 498e: 1600 addi s0,sp,800 - 4990: 0ca0 addi s0,sp,600 - 4992: 0000 unimp - 4994: 00000f1b 0xf1b - 4998: d812 sw tp,48(sp) - 499a: 0005 c.nop 1 - 499c: 0100 addi s0,sp,128 - 499e: 032e slli t1,t1,0xb - 49a0: 00000113 li sp,0 - 49a4: c200 sw s0,0(a2) - 49a6: 0000 unimp - 49a8: dd12 sw tp,184(sp) - 49aa: 0005 c.nop 1 - 49ac: 0100 addi s0,sp,128 - 49ae: 032e slli t1,t1,0xb - 49b0: 00000113 li sp,0 - 49b4: c21e sw t2,4(sp) - 49b6: 0000 unimp - 49b8: e212 fsw ft4,4(sp) - 49ba: 0005 c.nop 1 - 49bc: 0100 addi s0,sp,128 - 49be: 032e slli t1,t1,0xb - 49c0: 00000113 li sp,0 - 49c4: c285 beqz a3,49e4 <_start-0x7fffb61c> - 49c6: 0000 unimp - 49c8: e712 fsw ft4,140(sp) - 49ca: 0005 c.nop 1 - 49cc: 0100 addi s0,sp,128 - 49ce: 032e slli t1,t1,0xb - 49d0: 00000113 li sp,0 - 49d4: 0000c2a3 0xc2a3 - 49d8: 0719 addi a4,a4,6 - 49da: 0004 0x4 - 49dc: 0100 addi s0,sp,128 - 49de: 032e slli t1,t1,0xb - 49e0: 0061 c.nop 24 - 49e2: 0000 unimp - 49e4: bd19 j 47fa <_start-0x7fffb806> - 49e6: 0004 0x4 - 49e8: 0100 addi s0,sp,128 - 49ea: 032e slli t1,t1,0xb - 49ec: 0061 c.nop 24 - 49ee: 0000 unimp - 49f0: f112 fsw ft4,160(sp) - 49f2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 49f6: 032e slli t1,t1,0xb - 49f8: 0061 c.nop 24 - 49fa: 0000 unimp - 49fc: c2b6 sw a3,68(sp) - 49fe: 0000 unimp - 4a00: b812 fsd ft4,48(sp) - 4a02: 0004 0x4 - 4a04: 0100 addi s0,sp,128 - 4a06: 032e slli t1,t1,0xb - 4a08: 0061 c.nop 24 - 4a0a: 0000 unimp - 4a0c: 0000c2e3 bltz ra,5210 <_start-0x7fffadf0> - 4a10: 1800 addi s0,sp,48 - 4a12: 0cf0 addi a2,sp,604 - 4a14: 0000 unimp - 4a16: 5f14 lw a3,56(a4) - 4a18: 785f 0100 032e 0x32e0100785f - 4a1e: 00000113 li sp,0 - 4a22: c310 sw a2,0(a4) - 4a24: 0000 unimp - 4a26: 0000 unimp - 4a28: 2018 fld fa4,0(s0) - 4a2a: 000d c.nop 3 - 4a2c: 1200 addi s0,sp,288 - 4a2e: 0d51 addi s10,s10,20 - 4a30: 0000 unimp - 4a32: 2e01 jal 4d42 <_start-0x7fffb2be> - 4a34: 00124803 lbu a6,1(tp) # 6265b <_start-0x7ff9d9a5> - 4a38: 2300 fld fs0,0(a4) - 4a3a: 120000c3 fmadd.d ft1,ft0,ft0,ft2,rne - 4a3e: 0e98 addi a4,sp,848 - 4a40: 0000 unimp - 4a42: 2e01 jal 4d52 <_start-0x7fffb2ae> - 4a44: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4a48: 4300 lw s0,0(a4) - 4a4a: 120000c3 fmadd.d ft1,ft0,ft0,ft2,rne - 4a4e: 0dda slli s11,s11,0x16 - 4a50: 0000 unimp - 4a52: 2e01 jal 4d62 <_start-0x7fffb29e> - 4a54: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4a58: 6300 flw fs0,0(a4) - 4a5a: 120000c3 fmadd.d ft1,ft0,ft0,ft2,rne - 4a5e: 0f4e slli t5,t5,0x13 - 4a60: 0000 unimp - 4a62: 2e01 jal 4d72 <_start-0x7fffb28e> - 4a64: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4a68: 8300 0x8300 - 4a6a: 120000c3 fmadd.d ft1,ft0,ft0,ft2,rne - 4a6e: 0db8 addi a4,sp,728 - 4a70: 0000 unimp - 4a72: 2e01 jal 4d82 <_start-0x7fffb27e> - 4a74: 00011303 lh t1,0(sp) - 4a78: bb00 fsd fs0,48(a4) - 4a7a: 000000c3 fmadd.s ft1,ft0,ft0,ft0,rne - 4a7e: 1a00 addi s0,sp,304 - 4a80: 2338 fld fa4,64(a4) - 4a82: 8001 c.srli64 s0 - 4a84: 0048 addi a0,sp,4 - 4a86: 0000 unimp - 4a88: 0ffd addi t6,t6,31 - 4a8a: 0000 unimp - 4a8c: 5719 li a4,-26 - 4a8e: 000a c.slli zero,0x2 - 4a90: 0100 addi s0,sp,128 - 4a92: 032e slli t1,t1,0xb - 4a94: 0025 c.nop 9 - 4a96: 0000 unimp - 4a98: 0123381b 0x123381b - 4a9c: 3c80 fld fs0,56(s1) - 4a9e: 0000 unimp - 4aa0: 1200 addi s0,sp,288 - 4aa2: 00000ad7 vadd.vv v21,v0,v0,v0.t - 4aa6: 2e01 jal 4db6 <_start-0x7fffb24a> - 4aa8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4aac: d900 sw s0,48(a0) - 4aae: 120000c3 fmadd.d ft1,ft0,ft0,ft2,rne - 4ab2: 0a6d addi s4,s4,27 - 4ab4: 0000 unimp - 4ab6: 2e01 jal 4dc6 <_start-0x7fffb23a> - 4ab8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4abc: ed00 fsw fs0,24(a0) - 4abe: 120000c3 fmadd.d ft1,ft0,ft0,ft2,rne - 4ac2: 0a94 addi a3,sp,336 - 4ac4: 0000 unimp - 4ac6: 2e01 jal 4dd6 <_start-0x7fffb22a> - 4ac8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4acc: 0100 addi s0,sp,128 - 4ace: 00c4 addi s1,sp,68 - 4ad0: 1200 addi s0,sp,288 - 4ad2: 0a82 c.slli64 s5 - 4ad4: 0000 unimp - 4ad6: 2e01 jal 4de6 <_start-0x7fffb21a> - 4ad8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4adc: 1500 addi s0,sp,672 - 4ade: 00c4 addi s1,sp,68 - 4ae0: 1200 addi s0,sp,288 - 4ae2: 0aa9 addi s5,s5,10 - 4ae4: 0000 unimp - 4ae6: 2e01 jal 4df6 <_start-0x7fffb20a> - 4ae8: 00011303 lh t1,0(sp) - 4aec: 3500 fld fs0,40(a0) - 4aee: 00c4 addi s1,sp,68 - 4af0: 0000 unimp - 4af2: 1a00 addi s0,sp,304 - 4af4: 23ac fld fa1,64(a5) - 4af6: 8001 c.srli64 s0 - 4af8: 0038 addi a4,sp,8 - 4afa: 0000 unimp - 4afc: 0000101b 0x101b - 4b00: 2912 fld fs2,256(sp) - 4b02: 0100000f fence w,unknown - 4b06: 0113032f 0x113032f - 4b0a: 0000 unimp - 4b0c: c454 sw a3,12(s0) - 4b0e: 0000 unimp - 4b10: 1c00 addi s0,sp,560 - 4b12: 102d c.nop -21 - 4b14: 0000 unimp - 4b16: 2919 jal 4f2c <_start-0x7fffb0d4> - 4b18: 0100000f fence w,unknown - 4b1c: 0113032f 0x113032f - 4b20: 0000 unimp - 4b22: 1c00 addi s0,sp,560 - 4b24: 0000103f 000f2919 0xf29190000103f - 4b2c: 0100 addi s0,sp,128 - 4b2e: 0113032f 0x113032f - 4b32: 0000 unimp - 4b34: 1600 addi s0,sp,800 - 4b36: 0d50 addi a2,sp,660 - 4b38: 0000 unimp - 4b3a: 1089 addi ra,ra,-30 - 4b3c: 0000 unimp - 4b3e: 4e12 lw t3,4(sp) - 4b40: 000e c.slli zero,0x3 - 4b42: 0100 addi s0,sp,128 - 4b44: 1248032f 0x1248032f - 4b48: 0000 unimp - 4b4a: c4ce sw s3,72(sp) - 4b4c: 0000 unimp - 4b4e: ee12 fsw ft4,28(sp) - 4b50: 000d c.nop 3 - 4b52: 0100 addi s0,sp,128 - 4b54: 1248032f 0x1248032f - 4b58: 0000 unimp - 4b5a: c4ee sw s11,72(sp) - 4b5c: 0000 unimp - 4b5e: 0212 slli tp,tp,0x4 - 4b60: 000e c.slli zero,0x3 - 4b62: 0100 addi s0,sp,128 - 4b64: 1248032f 0x1248032f - 4b68: 0000 unimp - 4b6a: c50e sw gp,136(sp) - 4b6c: 0000 unimp - 4b6e: a712 fsd ft4,392(sp) - 4b70: 000d c.nop 3 - 4b72: 0100 addi s0,sp,128 - 4b74: 1248032f 0x1248032f - 4b78: 0000 unimp - 4b7a: c52e sw a1,136(sp) - 4b7c: 0000 unimp - 4b7e: 1600 addi s0,sp,800 - 4b80: 0d80 addi s0,sp,720 - 4b82: 0000 unimp - 4b84: 1231 addi tp,tp,-20 - 4b86: 0000 unimp - 4b88: b619 j 468e <_start-0x7fffb972> - 4b8a: 0009 c.nop 2 - 4b8c: 0100 addi s0,sp,128 - 4b8e: 0025032f 0x25032f - 4b92: 0000 unimp - 4b94: 061c addi a5,sp,768 - 4b96: 0011 c.nop 4 - 4b98: 1900 addi s0,sp,176 - 4b9a: 09d1 addi s3,s3,20 - 4b9c: 0000 unimp - 4b9e: 2f01 jal 52ae <_start-0x7fffad52> - 4ba0: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4ba4: 1900 addi s0,sp,176 - 4ba6: 099f 0000 2f01 0x2f010000099f - 4bac: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4bb0: 1900 addi s0,sp,176 - 4bb2: 0a31 addi s4,s4,12 - 4bb4: 0000 unimp - 4bb6: 2f01 jal 52c6 <_start-0x7fffad3a> - 4bb8: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4bbc: 1900 addi s0,sp,176 - 4bbe: 0eac addi a1,sp,856 - 4bc0: 0000 unimp - 4bc2: 2f01 jal 52d2 <_start-0x7fffad2e> - 4bc4: 00124f03 lbu t5,1(tp) # 1 <_start-0x7fffffff> - 4bc8: 1c00 addi s0,sp,560 - 4bca: 10e5 addi ra,ra,-7 - 4bcc: 0000 unimp - 4bce: 2919 jal 4fe4 <_start-0x7fffb01c> - 4bd0: 0100000f fence w,unknown - 4bd4: 0113032f 0x113032f - 4bd8: 0000 unimp - 4bda: 1c00 addi s0,sp,560 - 4bdc: 000010f7 0x10f7 - 4be0: 2919 jal 4ff6 <_start-0x7fffb00a> - 4be2: 0100000f fence w,unknown - 4be6: 0113032f 0x113032f - 4bea: 0000 unimp - 4bec: 1d00 addi s0,sp,688 - 4bee: 2919 jal 5004 <_start-0x7fffaffc> - 4bf0: 0100000f fence w,unknown - 4bf4: 0113032f 0x113032f - 4bf8: 0000 unimp - 4bfa: 0000 unimp - 4bfc: 981a add a6,a6,t1 - 4bfe: 0125 addi sp,sp,9 - 4c00: 1080 addi s0,sp,96 - 4c02: 0001 nop - 4c04: 7a00 flw fs0,48(a2) - 4c06: 0011 c.nop 4 - 4c08: 1200 addi s0,sp,288 - 4c0a: 00000a57 vadd.vv v20,v0,v0,v0.t - 4c0e: 2f01 jal 531e <_start-0x7ffface2> - 4c10: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 4c14: 5a00 lw s0,48(a2) - 4c16: 00c5 addi ra,ra,17 - 4c18: 1800 addi s0,sp,48 - 4c1a: 0da0 addi s0,sp,728 - 4c1c: 0000 unimp - 4c1e: d712 sw tp,172(sp) - 4c20: 000a c.slli zero,0x2 - 4c22: 0100 addi s0,sp,128 - 4c24: 1248032f 0x1248032f - 4c28: 0000 unimp - 4c2a: c574 sw a3,76(a0) - 4c2c: 0000 unimp - 4c2e: 6d12 flw fs10,4(sp) - 4c30: 000a c.slli zero,0x2 - 4c32: 0100 addi s0,sp,128 - 4c34: 1248032f 0x1248032f - 4c38: 0000 unimp - 4c3a: 0000c627 fsq ft0,12(ra) - 4c3e: 9412 add s0,s0,tp - 4c40: 000a c.slli zero,0x2 - 4c42: 0100 addi s0,sp,128 - 4c44: 1248032f 0x1248032f - 4c48: 0000 unimp - 4c4a: c6bc sw a5,72(a3) - 4c4c: 0000 unimp - 4c4e: 8212 mv tp,tp - 4c50: 000a c.slli zero,0x2 - 4c52: 0100 addi s0,sp,128 - 4c54: 1248032f 0x1248032f - 4c58: 0000 unimp - 4c5a: 0000c6cf fnmadd.s fa3,ft1,ft0,ft0,rmm - 4c5e: a912 fsd ft4,144(sp) - 4c60: 000a c.slli zero,0x2 - 4c62: 0100 addi s0,sp,128 - 4c64: 0113032f 0x113032f - 4c68: 0000 unimp - 4c6a: c77d beqz a4,4d58 <_start-0x7fffb2a8> - 4c6c: 0000 unimp - 4c6e: 0000 unimp - 4c70: b81a fsd ft6,48(sp) - 4c72: 0126 slli sp,sp,0x9 - 4c74: 3880 fld fs0,48(s1) - 4c76: 0000 unimp - 4c78: 9800 0x9800 - 4c7a: 0011 c.nop 4 - 4c7c: 1200 addi s0,sp,288 - 4c7e: 0f29 addi t5,t5,10 - 4c80: 0000 unimp - 4c82: 2f01 jal 5392 <_start-0x7fffac6e> - 4c84: 00011303 lh t1,0(sp) - 4c88: 9c00 0x9c00 - 4c8a: 000000c7 fmsub.s ft1,ft0,ft0,ft0,rne - 4c8e: aa1c fsd fa5,16(a2) - 4c90: 0011 c.nop 4 - 4c92: 1900 addi s0,sp,176 - 4c94: 0f29 addi t5,t5,10 - 4c96: 0000 unimp - 4c98: 2f01 jal 53a8 <_start-0x7fffac58> - 4c9a: 00011303 lh t1,0(sp) - 4c9e: 0000 unimp - 4ca0: bc1c fsd fa5,56(s0) - 4ca2: 0011 c.nop 4 - 4ca4: 1900 addi s0,sp,176 - 4ca6: 0f29 addi t5,t5,10 - 4ca8: 0000 unimp - 4caa: 2f01 jal 53ba <_start-0x7fffac46> - 4cac: 00011303 lh t1,0(sp) - 4cb0: 0000 unimp - 4cb2: 1c1a slli s8,s8,0x26 - 4cb4: 2c800127 vsxseg2b.v v2,(zero),v8,v0.t - 4cb8: 0000 unimp - 4cba: fe00 fsw fs0,56(a2) - 4cbc: 0011 c.nop 4 - 4cbe: 1900 addi s0,sp,176 - 4cc0: 0e4e slli t3,t3,0x13 - 4cc2: 0000 unimp - 4cc4: 2f01 jal 53d4 <_start-0x7fffac2c> - 4cc6: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4cca: 1900 addi s0,sp,176 - 4ccc: 0dee slli s11,s11,0x1b - 4cce: 0000 unimp - 4cd0: 2f01 jal 53e0 <_start-0x7fffac20> - 4cd2: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4cd6: 1900 addi s0,sp,176 - 4cd8: 0e02 c.slli64 t3 - 4cda: 0000 unimp - 4cdc: 2f01 jal 53ec <_start-0x7fffac14> - 4cde: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4ce2: 1200 addi s0,sp,288 - 4ce4: 00000da7 vsb.v v27,(zero),v0.t - 4ce8: 2f01 jal 53f8 <_start-0x7fffac08> - 4cea: 00124803 lbu a6,1(tp) # 1 <_start-0x7fffffff> - 4cee: 1600 addi s0,sp,800 - 4cf0: 00c8 addi a0,sp,68 - 4cf2: 0000 unimp - 4cf4: 101c addi a5,sp,32 - 4cf6: 0012 c.slli zero,0x4 - 4cf8: 1900 addi s0,sp,176 - 4cfa: 0f29 addi t5,t5,10 - 4cfc: 0000 unimp - 4cfe: 2f01 jal 540e <_start-0x7fffabf2> - 4d00: 00011303 lh t1,0(sp) - 4d04: 0000 unimp - 4d06: 221c fld fa5,0(a2) - 4d08: 0012 c.slli zero,0x4 - 4d0a: 1900 addi s0,sp,176 - 4d0c: 0f29 addi t5,t5,10 - 4d0e: 0000 unimp - 4d10: 2f01 jal 5420 <_start-0x7fffabe0> - 4d12: 00011303 lh t1,0(sp) - 4d16: 0000 unimp - 4d18: 191d addi s2,s2,-25 - 4d1a: 0f29 addi t5,t5,10 - 4d1c: 0000 unimp - 4d1e: 2f01 jal 542e <_start-0x7fffabd2> - 4d20: 00011303 lh t1,0(sp) - 4d24: 0000 unimp - 4d26: 1800 addi s0,sp,48 - 4d28: 0d68 addi a0,sp,668 - 4d2a: 0000 unimp - 4d2c: 000d3e17 auipc t3,0xd3 - 4d30: 0100 addi s0,sp,128 - 4d32: 011a032f 0x11a032f - 4d36: 0000 unimp - 4d38: 7fa09103 lh sp,2042(ra) - 4d3c: 0000 unimp - 4d3e: 22050403 lb s0,544(a0) - 4d42: 0002 c.slli64 zero - 4d44: 0600 addi s0,sp,768 - 4d46: 00000113 li sp,0 - 4d4a: 125f 0000 5307 0x53070000125f - 4d50: 0000 unimp - 4d52: 0300 addi s0,sp,384 - 4d54: 1e00 addi s0,sp,816 - 4d56: 00000113 li sp,0 - 4d5a: 00005307 vlhu.v v6,(zero),v0.t - 4d5e: 0700 addi s0,sp,896 - 4d60: 0000 unimp - 4d62: 0d7f 0xd7f - 4d64: 0000 unimp - 4d66: 0004 0x4 - 4d68: 0f41 addi t5,t5,16 - 4d6a: 0000 unimp - 4d6c: 0104 addi s1,sp,128 - 4d6e: 07f2 slli a5,a5,0x1c - 4d70: 0000 unimp - 4d72: a80c fsd fa1,16(s0) - 4d74: fc00000f 0xfc00000f - 4d78: 0002 c.slli64 zero - 4d7a: c400 sw s0,8(s0) - 4d7c: 20800127 0x20800127 - 4d80: 0015 c.nop 5 - 4d82: 9e00 0x9e00 - 4d84: 0054 addi a3,sp,4 - 4d86: 0200 addi s0,sp,256 - 4d88: 0504 addi s1,sp,640 - 4d8a: 6e69 lui t3,0x1a - 4d8c: 0074 addi a3,sp,12 - 4d8e: 69060103 lb sp,1680(a2) # ffff6690 <__BSS_END__+0x7ffdf918> - 4d92: 0006 c.slli zero,0x1 - 4d94: 0300 addi s0,sp,384 - 4d96: 0508 addi a0,sp,640 - 4d98: 021d addi tp,tp,7 - 4d9a: 0000 unimp - 4d9c: 7304 flw fs1,32(a4) - 4d9e: 02000007 vlbu.v v0,(zero) - 4da2: 014a slli sp,sp,0x12 - 4da4: 4c16 lw s8,68(sp) - 4da6: 0000 unimp - 4da8: 0500 addi s0,sp,640 - 4daa: 003a c.slli zero,0xe - 4dac: 0000 unimp - 4dae: 67080103 lb sp,1648(a6) - 4db2: 0006 c.slli zero,0x1 - 4db4: 0300 addi s0,sp,384 - 4db6: 0704 addi s1,sp,896 - 4db8: 036e slli t1,t1,0x1b - 4dba: 0000 unimp - 4dbc: 64070803 lb a6,1600(a4) # fffee640 <__BSS_END__+0x7ffd78c8> - 4dc0: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 4dc4: 0702 c.slli64 a4 - 4dc6: 0384 addi s1,sp,448 - 4dc8: 0000 unimp - 4dca: 4706 lw a4,64(sp) - 4dcc: 0000 unimp - 4dce: 7800 flw fs0,48(s0) - 4dd0: 0000 unimp - 4dd2: 0700 addi s0,sp,896 - 4dd4: 00000053 fadd.s ft0,ft0,ft0,rne - 4dd8: 00ff 0xff - 4dda: 6805 lui a6,0x1 - 4ddc: 0000 unimp - 4dde: 0800 addi s0,sp,16 - 4de0: 00000397 auipc t2,0x0 - 4de4: 3c04 fld fs1,56(s0) - 4de6: 7816 flw fa6,100(sp) - 4de8: 0000 unimp - 4dea: 0900 addi s0,sp,144 - 4dec: 0c01 addi s8,s8,0 - 4dee: 0000 unimp - 4df0: 950f4803 lbu a6,-1712(t5) # ffffa950 <__BSS_END__+0x7ffe3bd8> - 4df4: 0000 unimp - 4df6: 0300 addi s0,sp,384 - 4df8: 0410 addi a2,sp,512 - 4dfa: 009d addi ra,ra,7 - 4dfc: 0000 unimp - 4dfe: 100a c.slli zero,0x22 - 4e00: 06034f03 lbu t5,96(t1) # bee7c <_start-0x7ff41184> - 4e04: 0001 nop - 4e06: 0b00 addi s0,sp,400 - 4e08: 08bd addi a7,a7,15 - 4e0a: 0000 unimp - 4e0c: 06135903 lhu s2,97(t1) - 4e10: 0001 nop - 4e12: 0400 addi s0,sp,512 - 4e14: 0020 addi s0,sp,8 - 4e16: 0b00 addi s0,sp,400 - 4e18: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne - 4e1c: 06135a03 lhu s4,97(t1) - 4e20: 0001 nop - 4e22: 0400 addi s0,sp,512 - 4e24: 0020 addi s0,sp,8 - 4e26: 0b04 addi s1,sp,400 - 4e28: 0bf5 addi s7,s7,29 - 4e2a: 0000 unimp - 4e2c: 06135b03 lhu s6,97(t1) - 4e30: 0001 nop - 4e32: 0400 addi s0,sp,512 - 4e34: 0020 addi s0,sp,8 - 4e36: 0b08 addi a0,sp,400 - 4e38: 00000bfb 0xbfb - 4e3c: 06135c03 lhu s8,97(t1) - 4e40: 0001 nop - 4e42: 0400 addi s0,sp,512 - 4e44: 1010 addi a2,sp,32 - 4e46: 0c0c addi a1,sp,528 - 4e48: 7865 lui a6,0xffff9 - 4e4a: 0070 addi a2,sp,12 - 4e4c: 530e5d03 lhu s10,1328(t3) # 1a530 <_start-0x7ffe5ad0> - 4e50: 0000 unimp - 4e52: 0400 addi s0,sp,512 - 4e54: 0b0c010f 0xb0c010f - 4e58: 027a slli tp,tp,0x1e - 4e5a: 0000 unimp - 4e5c: 530e5e03 lhu t3,1328(t3) - 4e60: 0000 unimp - 4e62: 0400 addi s0,sp,512 - 4e64: 0001 nop - 4e66: 000c 0xc - 4e68: 69070403 lb s0,1680(a4) - 4e6c: 0d000003 lb zero,208(zero) # d0 <_start-0x7fffff30> - 4e70: 00000c2f 0xc2f - 4e74: 0310 addi a2,sp,384 - 4e76: 074c addi a1,sp,900 - 4e78: 00000133 add sp,zero,zero - 4e7c: 660e flw fa2,192(sp) - 4e7e: 746c flw fa1,108(s0) - 4e80: 0300 addi s0,sp,384 - 4e82: 0a4e slli s4,s4,0x13 - 4e84: 0089 addi ra,ra,2 - 4e86: 0000 unimp - 4e88: 000a480f 0xa480f - 4e8c: 0300 addi s0,sp,384 - 4e8e: 0560 addi s0,sp,652 - 4e90: 009c addi a5,sp,64 - 4e92: 0000 unimp - 4e94: 1000 addi s0,sp,32 - 4e96: 0f5f 0000 2301 0x230100000f5f - 4e9c: 8901 andi a0,a0,0 - 4e9e: 0000 unimp - 4ea0: c400 sw s0,8(s0) - 4ea2: 20800127 0x20800127 - 4ea6: 0015 c.nop 5 - 4ea8: 0100 addi s0,sp,128 - 4eaa: 6f9c flw fa5,24(a5) - 4eac: 000d c.nop 3 - 4eae: 1100 addi s0,sp,160 - 4eb0: 0061 c.nop 24 - 4eb2: 2301 jal 53b2 <_start-0x7fffac4e> - 4eb4: 8912 mv s2,tp - 4eb6: 0000 unimp - 4eb8: 1100 addi s0,sp,160 - 4eba: 0062 c.slli zero,0x18 - 4ebc: 2301 jal 53bc <_start-0x7fffac44> - 4ebe: 891c 0x891c - 4ec0: 0000 unimp - 4ec2: 1200 addi s0,sp,288 - 4ec4: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 4ec8: 2501 jal 54c8 <_start-0x7fffab38> - 4eca: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 4ece: 2a00 fld fs0,16(a2) - 4ed0: 00c8 addi a0,sp,68 - 4ed2: 1300 addi s0,sp,416 - 4ed4: 0a4d addi s4,s4,19 - 4ed6: 0000 unimp - 4ed8: 2501 jal 54d8 <_start-0x7fffab28> - 4eda: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 4ede: 0000 unimp - 4ee0: 4114 lw a3,0(a0) - 4ee2: 635f 0100 0326 0x3260100635f - 4ee8: 00000d6f jal s10,4ee8 <_start-0x7fffb118> - 4eec: 4115 li sp,5 - 4eee: 735f 0100 0326 0x3260100735f - 4ef4: 00000d6f jal s10,4ef4 <_start-0x7fffb10c> - 4ef8: c892 sw tp,80(sp) - 4efa: 0000 unimp - 4efc: 4115 li sp,5 - 4efe: 655f 0100 0326 0x3260100655f - 4f04: 00000d6f jal s10,4f04 <_start-0x7fffb0fc> - 4f08: c91e sw t2,144(sp) - 4f0a: 0000 unimp - 4f0c: 4116 lw sp,68(sp) - 4f0e: 665f 0100 0326 0x3260100665f - 4f14: 0d76 slli s10,s10,0x1d - 4f16: 0000 unimp - 4f18: 7fb09103 lh sp,2043(ra) - 4f1c: 4214 lw a3,0(a2) - 4f1e: 635f 0100 0327 0x3270100635f - 4f24: 00000d6f jal s10,4f24 <_start-0x7fffb0dc> - 4f28: 4215 li tp,5 - 4f2a: 735f 0100 0327 0x3270100735f - 4f30: 00000d6f jal s10,4f30 <_start-0x7fffb0d0> - 4f34: ca1e sw t2,20(sp) - 4f36: 0000 unimp - 4f38: 4215 li tp,5 - 4f3a: 655f 0100 0327 0x3270100655f - 4f40: 00000d6f jal s10,4f40 <_start-0x7fffb0c0> - 4f44: caa4 sw s1,80(a3) - 4f46: 0000 unimp - 4f48: 4216 lw tp,68(sp) - 4f4a: 665f 0100 0327 0x3270100665f - 4f50: 0d76 slli s10,s10,0x1d - 4f52: 0000 unimp - 4f54: 9102 jalr sp - 4f56: 1540 addi s0,sp,676 - 4f58: 5f52 lw t5,52(sp) - 4f5a: 28010063 beqz sp,51da <_start-0x7fffae26> - 4f5e: 000d6f03 0xd6f03 - 4f62: f900 fsw fs0,48(a0) - 4f64: 00cc addi a1,sp,68 - 4f66: 1500 addi s0,sp,672 - 4f68: 5f52 lw t5,52(sp) - 4f6a: 28010073 0x28010073 - 4f6e: 000d6f03 0xd6f03 - 4f72: 1900 addi s0,sp,176 - 4f74: 00cd addi ra,ra,19 - 4f76: 1500 addi s0,sp,672 - 4f78: 5f52 lw t5,52(sp) - 4f7a: 0065 c.nop 25 - 4f7c: 2801 jal 4f8c <_start-0x7fffb074> - 4f7e: 000d6f03 0xd6f03 - 4f82: eb00 fsw fs0,16(a4) - 4f84: 00cd addi ra,ra,19 - 4f86: 1600 addi s0,sp,800 - 4f88: 5f52 lw t5,52(sp) - 4f8a: 0066 c.slli zero,0x19 - 4f8c: 2801 jal 4f9c <_start-0x7fffb064> - 4f8e: 000d7603 0xd7603 - 4f92: 0200 addi s0,sp,256 - 4f94: 5091 li ra,-28 - 4f96: 7215 lui tp,0xfffe5 - 4f98: 0100 addi s0,sp,128 - 4f9a: 0a29 addi s4,s4,10 - 4f9c: 0089 addi ra,ra,2 - 4f9e: 0000 unimp - 4fa0: 0000cf33 xor t5,ra,zero - 4fa4: 000db817 auipc a6,0xdb - 4fa8: 5b00 lw s0,48(a4) - 4faa: 0002 c.slli64 zero - 4fac: 1800 addi s0,sp,48 - 4fae: 00000bb3 add s7,zero,zero - 4fb2: 2c01 jal 51c2 <_start-0x7fffae3e> - 4fb4: 00010d03 lb s10,0(sp) - 4fb8: 0200 addi s0,sp,256 - 4fba: 5091 li ra,-28 - 4fbc: 1700 addi s0,sp,928 - 4fbe: 0de8 addi a0,sp,732 - 4fc0: 0000 unimp - 4fc2: 029c addi a5,sp,320 - 4fc4: 0000 unimp - 4fc6: 000f3c13 sltiu s8,t5,0 - 4fca: 0100 addi s0,sp,128 - 4fcc: 032c addi a1,sp,392 - 4fce: 00000d6f jal s10,4fce <_start-0x7fffb032> - 4fd2: 0d771303 lh t1,215(a4) - 4fd6: 0000 unimp - 4fd8: 2c01 jal 51e8 <_start-0x7fffae18> - 4fda: 000d6f03 0xd6f03 - 4fde: 1d00 addi s0,sp,688 - 4fe0: 000d6313 ori t1,s10,0 - 4fe4: 0100 addi s0,sp,128 - 4fe6: 032c addi a1,sp,392 - 4fe8: 00000d6f jal s10,4fe8 <_start-0x7fffb018> - 4fec: 1200 addi s0,sp,288 - 4fee: 0dc9 addi s11,s11,18 - 4ff0: 0000 unimp - 4ff2: 2c01 jal 5202 <_start-0x7fffadfe> - 4ff4: 000d6f03 0xd6f03 - 4ff8: b900 fsd fs0,48(a0) - 4ffa: 000000cf fnmadd.s ft1,ft0,ft0,ft0,rne - 4ffe: 000e0817 auipc a6,0xe0 - 5002: b500 fsd fs0,40(a0) - 5004: 0002 c.slli64 zero - 5006: 1800 addi s0,sp,48 - 5008: 00000bb3 add s7,zero,zero - 500c: 2d01 jal 561c <_start-0x7fffa9e4> - 500e: 00010d03 lb s10,0(sp) - 5012: 0200 addi s0,sp,256 - 5014: 5091 li ra,-28 - 5016: 1700 addi s0,sp,928 - 5018: 0e48 addi a0,sp,788 - 501a: 0000 unimp - 501c: 02f6 slli t0,t0,0x1d - 501e: 0000 unimp - 5020: 000f3c13 sltiu s8,t5,0 - 5024: 0100 addi s0,sp,128 - 5026: 032d addi t1,t1,11 - 5028: 00000d6f jal s10,5028 <_start-0x7fffafd8> - 502c: 0d771303 lh t1,215(a4) - 5030: 0000 unimp - 5032: 2d01 jal 5642 <_start-0x7fffa9be> - 5034: 000d6f03 0xd6f03 - 5038: 1d00 addi s0,sp,688 - 503a: 000d6313 ori t1,s10,0 - 503e: 0100 addi s0,sp,128 - 5040: 032d addi t1,t1,11 - 5042: 00000d6f jal s10,5042 <_start-0x7fffafbe> - 5046: 1200 addi s0,sp,288 - 5048: 0dc9 addi s11,s11,18 - 504a: 0000 unimp - 504c: 2d01 jal 565c <_start-0x7fffa9a4> - 504e: 000d6f03 0xd6f03 - 5052: da00 sw s0,48(a2) - 5054: 000000cf fnmadd.s ft1,ft0,ft0,ft0,rne - 5058: 000e6017 auipc zero,0xe6 - 505c: 2600 fld fs0,8(a2) - 505e: 19000007 vlsb.v v0,(zero),a6,v0.t - 5062: 10b5 addi ra,ra,-19 - 5064: 0000 unimp - 5066: 2e01 jal 5376 <_start-0x7fffac8a> - 5068: 012a1803 lh a6,18(s4) - 506c: 1980 addi s0,sp,240 - 506e: 00000f7b 0xf7b - 5072: 2e01 jal 5382 <_start-0x7fffac7e> - 5074: 012e9403 lh s0,18(t4) - 5078: 1980 addi s0,sp,240 - 507a: 10ba slli ra,ra,0x2e - 507c: 0000 unimp - 507e: 2e01 jal 538e <_start-0x7fffac72> - 5080: 012b8803 lb a6,18(s7) # 1dd4 <_start-0x7fffe22c> - 5084: 1980 addi s0,sp,240 - 5086: 0f80 addi s0,sp,976 - 5088: 0000 unimp - 508a: 2e01 jal 539a <_start-0x7fffac66> - 508c: 012c5c03 lhu s8,18(s8) # fffe1012 <__BSS_END__+0x7ffca29a> - 5090: 1280 addi s0,sp,352 - 5092: 1082 slli ra,ra,0x20 - 5094: 0000 unimp - 5096: 2e01 jal 53a6 <_start-0x7fffac5a> - 5098: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 509c: fb00 fsw fs0,48(a4) - 509e: 1a0000cf fnmadd.d ft1,ft0,ft0,ft3,rne - 50a2: 2954 fld fa3,144(a0) - 50a4: 8001 c.srli64 s0 - 50a6: 0054 addi a3,sp,4 - 50a8: 0000 unimp - 50aa: 037d addi t1,t1,31 - 50ac: 0000 unimp - 50ae: eb12 fsw ft4,148(sp) - 50b0: 0100000f fence w,unknown - 50b4: 032e slli t1,t1,0xb - 50b6: 0106 slli sp,sp,0x1 - 50b8: 0000 unimp - 50ba: d17e sw t6,160(sp) - 50bc: 0000 unimp - 50be: fe12 fsw ft4,60(sp) - 50c0: 0100000f fence w,unknown - 50c4: 032e slli t1,t1,0xb - 50c6: 0106 slli sp,sp,0x1 - 50c8: 0000 unimp - 50ca: 0000d1ab 0xd1ab - 50ce: 1112 slli sp,sp,0x24 - 50d0: 0010 0x10 - 50d2: 0100 addi s0,sp,128 - 50d4: 032e slli t1,t1,0xb - 50d6: 0106 slli sp,sp,0x1 - 50d8: 0000 unimp - 50da: d22c sw a1,96(a2) - 50dc: 0000 unimp - 50de: 1a00 addi s0,sp,304 - 50e0: 2a24 fld fs1,80(a2) - 50e2: 8001 c.srli64 s0 - 50e4: 00fc addi a5,sp,76 - 50e6: 0000 unimp - 50e8: 03f1 addi t2,t2,28 - 50ea: 0000 unimp - 50ec: 5712 lw a4,36(sp) - 50ee: 000a c.slli zero,0x2 - 50f0: 0100 addi s0,sp,128 - 50f2: 032e slli t1,t1,0xb - 50f4: 0025 c.nop 9 - 50f6: 0000 unimp - 50f8: d26c sw a1,100(a2) - 50fa: 0000 unimp - 50fc: 000ea81b 0xea81b - 5100: 1200 addi s0,sp,288 - 5102: 00000ad7 vadd.vv v21,v0,v0,v0.t - 5106: 2e01 jal 5416 <_start-0x7fffabea> - 5108: 000d6f03 0xd6f03 - 510c: 8600 0x8600 - 510e: 00d2 slli ra,ra,0x14 - 5110: 1200 addi s0,sp,288 - 5112: 0a6d addi s4,s4,27 - 5114: 0000 unimp - 5116: 2e01 jal 5426 <_start-0x7fffabda> - 5118: 000d6f03 0xd6f03 - 511c: be00 fsd fs0,56(a2) - 511e: 00d2 slli ra,ra,0x14 - 5120: 1200 addi s0,sp,288 - 5122: 0a94 addi a3,sp,336 - 5124: 0000 unimp - 5126: 2e01 jal 5436 <_start-0x7fffabca> - 5128: 000d6f03 0xd6f03 - 512c: e700 fsw fs0,8(a4) - 512e: 00d2 slli ra,ra,0x14 - 5130: 1200 addi s0,sp,288 - 5132: 0a82 c.slli64 s5 - 5134: 0000 unimp - 5136: 2e01 jal 5446 <_start-0x7fffabba> - 5138: 000d6f03 0xd6f03 - 513c: fa00 fsw fs0,48(a2) - 513e: 00d2 slli ra,ra,0x14 - 5140: 1200 addi s0,sp,288 - 5142: 0aa9 addi s5,s5,10 - 5144: 0000 unimp - 5146: 2e01 jal 5456 <_start-0x7fffabaa> - 5148: 00010603 lb a2,0(sp) - 514c: a800 fsd fs0,16(s0) - 514e: 000000d3 fadd.s ft1,ft0,ft0,rne - 5152: 1a00 addi s0,sp,304 - 5154: 2b20 fld fs0,80(a4) - 5156: 8001 c.srli64 s0 - 5158: 0068 addi a0,sp,12 - 515a: 0000 unimp - 515c: 0000042f 0x42f - 5160: eb12 fsw ft4,148(sp) - 5162: 0100000f fence w,unknown - 5166: 032e slli t1,t1,0xb - 5168: 0106 slli sp,sp,0x1 - 516a: 0000 unimp - 516c: 0000d3c7 fmsub.s ft7,ft1,ft0,ft0,unknown - 5170: fe12 fsw ft4,60(sp) - 5172: 0100000f fence w,unknown - 5176: 032e slli t1,t1,0xb - 5178: 0106 slli sp,sp,0x1 - 517a: 0000 unimp - 517c: d3f5 beqz a5,5160 <_start-0x7fffaea0> - 517e: 0000 unimp - 5180: 1112 slli sp,sp,0x24 - 5182: 0010 0x10 - 5184: 0100 addi s0,sp,128 - 5186: 032e slli t1,t1,0xb - 5188: 0106 slli sp,sp,0x1 - 518a: 0000 unimp - 518c: d4a0 sw s0,104(s1) - 518e: 0000 unimp - 5190: 1a00 addi s0,sp,304 - 5192: 2dd0 fld fa2,152(a1) - 5194: 8001 c.srli64 s0 - 5196: 0058 addi a4,sp,4 - 5198: 0000 unimp - 519a: 046d addi s0,s0,27 - 519c: 0000 unimp - 519e: eb12 fsw ft4,148(sp) - 51a0: 0100000f fence w,unknown - 51a4: 032e slli t1,t1,0xb - 51a6: 0106 slli sp,sp,0x1 - 51a8: 0000 unimp - 51aa: d4e0 sw s0,108(s1) - 51ac: 0000 unimp - 51ae: fe12 fsw ft4,60(sp) - 51b0: 0100000f fence w,unknown - 51b4: 032e slli t1,t1,0xb - 51b6: 0106 slli sp,sp,0x1 - 51b8: 0000 unimp - 51ba: d50d beqz a0,50e4 <_start-0x7fffaf1c> - 51bc: 0000 unimp - 51be: 1112 slli sp,sp,0x24 - 51c0: 0010 0x10 - 51c2: 0100 addi s0,sp,128 - 51c4: 032e slli t1,t1,0xb - 51c6: 0106 slli sp,sp,0x1 - 51c8: 0000 unimp - 51ca: 0000d58f 0xd58f - 51ce: 1a00 addi s0,sp,304 - 51d0: 2ea0 fld fs0,88(a3) - 51d2: 8001 c.srli64 s0 - 51d4: 0114 addi a3,sp,128 - 51d6: 0000 unimp - 51d8: 04e1 addi s1,s1,24 - 51da: 0000 unimp - 51dc: 5712 lw a4,36(sp) - 51de: 000a c.slli zero,0x2 - 51e0: 0100 addi s0,sp,128 - 51e2: 032e slli t1,t1,0xb - 51e4: 0025 c.nop 9 - 51e6: 0000 unimp - 51e8: d5ce sw s3,232(sp) - 51ea: 0000 unimp - 51ec: 000ef81b 0xef81b - 51f0: 1200 addi s0,sp,288 - 51f2: 00000ad7 vadd.vv v21,v0,v0,v0.t - 51f6: 2e01 jal 5506 <_start-0x7fffaafa> - 51f8: 000d6f03 0xd6f03 - 51fc: e800 fsw fs0,16(s0) - 51fe: 00d5 addi ra,ra,21 - 5200: 1200 addi s0,sp,288 - 5202: 0a6d addi s4,s4,27 - 5204: 0000 unimp - 5206: 2e01 jal 5516 <_start-0x7fffaaea> - 5208: 000d6f03 0xd6f03 - 520c: 2000 fld fs0,0(s0) - 520e: 00d6 slli ra,ra,0x15 - 5210: 1200 addi s0,sp,288 - 5212: 0a94 addi a3,sp,336 - 5214: 0000 unimp - 5216: 2e01 jal 5526 <_start-0x7fffaada> - 5218: 000d6f03 0xd6f03 - 521c: 4900 lw s0,16(a0) - 521e: 00d6 slli ra,ra,0x15 - 5220: 1200 addi s0,sp,288 - 5222: 0a82 c.slli64 s5 - 5224: 0000 unimp - 5226: 2e01 jal 5536 <_start-0x7fffaaca> - 5228: 000d6f03 0xd6f03 - 522c: 6700 flw fs0,8(a4) - 522e: 00d6 slli ra,ra,0x15 - 5230: 1200 addi s0,sp,288 - 5232: 0aa9 addi s5,s5,10 - 5234: 0000 unimp - 5236: 2e01 jal 5546 <_start-0x7fffaaba> - 5238: 00010603 lb a2,0(sp) - 523c: 1500 addi s0,sp,672 - 523e: 000000d7 vadd.vv v1,v0,v0,v0.t - 5242: 1700 addi s0,sp,928 - 5244: 0f10 addi a2,sp,912 - 5246: 0000 unimp - 5248: 0000051b 0x51b - 524c: eb12 fsw ft4,148(sp) - 524e: 0100000f fence w,unknown - 5252: 032e slli t1,t1,0xb - 5254: 0106 slli sp,sp,0x1 - 5256: 0000 unimp - 5258: d734 sw a3,104(a4) - 525a: 0000 unimp - 525c: fe12 fsw ft4,60(sp) - 525e: 0100000f fence w,unknown - 5262: 032e slli t1,t1,0xb - 5264: 0106 slli sp,sp,0x1 - 5266: 0000 unimp - 5268: d761 beqz a4,5230 <_start-0x7fffadd0> - 526a: 0000 unimp - 526c: 1112 slli sp,sp,0x24 - 526e: 0010 0x10 - 5270: 0100 addi s0,sp,128 - 5272: 032e slli t1,t1,0xb - 5274: 0106 slli sp,sp,0x1 - 5276: 0000 unimp - 5278: d808 sw a0,48(s0) - 527a: 0000 unimp - 527c: 1700 addi s0,sp,928 - 527e: 0f28 addi a0,sp,920 - 5280: 0000 unimp - 5282: 0555 addi a0,a0,21 - 5284: 0000 unimp - 5286: eb12 fsw ft4,148(sp) - 5288: 0100000f fence w,unknown - 528c: 032e slli t1,t1,0xb - 528e: 0106 slli sp,sp,0x1 - 5290: 0000 unimp - 5292: 0000d847 fmsub.s fa6,ft1,ft0,ft0,unknown - 5296: fe12 fsw ft4,60(sp) - 5298: 0100000f fence w,unknown - 529c: 032e slli t1,t1,0xb - 529e: 0106 slli sp,sp,0x1 - 52a0: 0000 unimp - 52a2: d875 beqz s0,5296 <_start-0x7fffad6a> - 52a4: 0000 unimp - 52a6: 1112 slli sp,sp,0x24 - 52a8: 0010 0x10 - 52aa: 0100 addi s0,sp,128 - 52ac: 032e slli t1,t1,0xb - 52ae: 0106 slli sp,sp,0x1 - 52b0: 0000 unimp - 52b2: d8ed beqz s1,52a4 <_start-0x7fffad5c> - 52b4: 0000 unimp - 52b6: 1c00 addi s0,sp,560 - 52b8: 0000058b 0x58b - 52bc: 4e1d li t3,7 - 52be: 000e c.slli zero,0x3 - 52c0: 0100 addi s0,sp,128 - 52c2: 032e slli t1,t1,0xb - 52c4: 00000d6f jal s10,52c4 <_start-0x7fffad3c> - 52c8: ee1d bnez a2,5306 <_start-0x7fffacfa> - 52ca: 000d c.nop 3 - 52cc: 0100 addi s0,sp,128 - 52ce: 032e slli t1,t1,0xb - 52d0: 00000d6f jal s10,52d0 <_start-0x7fffad30> - 52d4: 021d addi tp,tp,7 - 52d6: 000e c.slli zero,0x3 - 52d8: 0100 addi s0,sp,128 - 52da: 032e slli t1,t1,0xb - 52dc: 00000d6f jal s10,52dc <_start-0x7fffad24> - 52e0: a71d j 5a06 <_start-0x7fffa5fa> - 52e2: 000d c.nop 3 - 52e4: 0100 addi s0,sp,128 - 52e6: 032e slli t1,t1,0xb - 52e8: 00000d6f jal s10,52e8 <_start-0x7fffad18> - 52ec: 1c00 addi s0,sp,560 - 52ee: 05c1 addi a1,a1,16 - 52f0: 0000 unimp - 52f2: 4e1d li t3,7 - 52f4: 000e c.slli zero,0x3 - 52f6: 0100 addi s0,sp,128 - 52f8: 032e slli t1,t1,0xb - 52fa: 00000d6f jal s10,52fa <_start-0x7fffad06> - 52fe: ee1d bnez a2,533c <_start-0x7fffacc4> - 5300: 000d c.nop 3 - 5302: 0100 addi s0,sp,128 - 5304: 032e slli t1,t1,0xb - 5306: 00000d6f jal s10,5306 <_start-0x7fffacfa> - 530a: 021d addi tp,tp,7 - 530c: 000e c.slli zero,0x3 - 530e: 0100 addi s0,sp,128 - 5310: 032e slli t1,t1,0xb - 5312: 00000d6f jal s10,5312 <_start-0x7fffacee> - 5316: a71d j 5a3c <_start-0x7fffa5c4> - 5318: 000d c.nop 3 - 531a: 0100 addi s0,sp,128 - 531c: 032e slli t1,t1,0xb - 531e: 00000d6f jal s10,531e <_start-0x7ffface2> - 5322: 1a00 addi s0,sp,304 - 5324: 3160 fld fs0,224(a0) - 5326: 8001 c.srli64 s0 - 5328: 0024 addi s1,sp,8 - 532a: 0000 unimp - 532c: 0000060f 0x60f - 5330: 3c12 fld fs8,288(sp) - 5332: 0100000f fence w,unknown - 5336: 032e slli t1,t1,0xb - 5338: 00000d6f jal s10,5338 <_start-0x7fffacc8> - 533c: d910 sw a2,48(a0) - 533e: 0000 unimp - 5340: 7712 flw fa4,36(sp) - 5342: 000d c.nop 3 - 5344: 0100 addi s0,sp,128 - 5346: 032e slli t1,t1,0xb - 5348: 00000d6f jal s10,5348 <_start-0x7fffacb8> - 534c: d924 sw s1,112(a0) - 534e: 0000 unimp - 5350: 6312 flw ft6,4(sp) - 5352: 000d c.nop 3 - 5354: 0100 addi s0,sp,128 - 5356: 032e slli t1,t1,0xb - 5358: 00000d6f jal s10,5358 <_start-0x7fffaca8> - 535c: d938 sw a4,112(a0) - 535e: 0000 unimp - 5360: c912 sw tp,144(sp) - 5362: 000d c.nop 3 - 5364: 0100 addi s0,sp,128 - 5366: 032e slli t1,t1,0xb - 5368: 00000d6f jal s10,5368 <_start-0x7fffac98> - 536c: d94c sw a1,52(a0) - 536e: 0000 unimp - 5370: 1a00 addi s0,sp,304 - 5372: 31a0 fld fs0,96(a1) - 5374: 8001 c.srli64 s0 - 5376: 0048 addi a0,sp,4 - 5378: 0000 unimp - 537a: 0649 addi a2,a2,18 - 537c: 0000 unimp - 537e: eb12 fsw ft4,148(sp) - 5380: 0100000f fence w,unknown - 5384: 032e slli t1,t1,0xb - 5386: 0106 slli sp,sp,0x1 - 5388: 0000 unimp - 538a: d960 sw s0,116(a0) - 538c: 0000 unimp - 538e: fe12 fsw ft4,60(sp) - 5390: 0100000f fence w,unknown - 5394: 032e slli t1,t1,0xb - 5396: 0106 slli sp,sp,0x1 - 5398: 0000 unimp - 539a: d9ae sw a1,240(sp) - 539c: 0000 unimp - 539e: 111d addi sp,sp,-25 - 53a0: 0010 0x10 - 53a2: 0100 addi s0,sp,128 - 53a4: 032e slli t1,t1,0xb - 53a6: 0106 slli sp,sp,0x1 - 53a8: 0000 unimp - 53aa: 1700 addi s0,sp,928 - 53ac: 0f40 addi s0,sp,916 - 53ae: 0000 unimp - 53b0: 06b9 addi a3,a3,14 - 53b2: 0000 unimp - 53b4: 5712 lw a4,36(sp) - 53b6: 000a c.slli zero,0x2 - 53b8: 0100 addi s0,sp,128 - 53ba: 032e slli t1,t1,0xb - 53bc: 0025 c.nop 9 - 53be: 0000 unimp - 53c0: d9f1 beqz a1,5394 <_start-0x7fffac6c> - 53c2: 0000 unimp - 53c4: 000f401b 0xf401b - 53c8: 1200 addi s0,sp,288 - 53ca: 00000ad7 vadd.vv v21,v0,v0,v0.t - 53ce: 2e01 jal 56de <_start-0x7fffa922> - 53d0: 000d6f03 0xd6f03 - 53d4: 0500 addi s0,sp,640 - 53d6: 00da slli ra,ra,0x16 - 53d8: 1200 addi s0,sp,288 - 53da: 0a6d addi s4,s4,27 - 53dc: 0000 unimp - 53de: 2e01 jal 56ee <_start-0x7fffa912> - 53e0: 000d6f03 0xd6f03 - 53e4: 1900 addi s0,sp,176 - 53e6: 00da slli ra,ra,0x16 - 53e8: 1200 addi s0,sp,288 - 53ea: 0a94 addi a3,sp,336 - 53ec: 0000 unimp - 53ee: 2e01 jal 56fe <_start-0x7fffa902> - 53f0: 000d6f03 0xd6f03 - 53f4: 2d00 fld fs0,24(a0) - 53f6: 00da slli ra,ra,0x16 - 53f8: 1200 addi s0,sp,288 - 53fa: 0a82 c.slli64 s5 - 53fc: 0000 unimp - 53fe: 2e01 jal 570e <_start-0x7fffa8f2> - 5400: 000d6f03 0xd6f03 - 5404: 4100 lw s0,0(a0) - 5406: 00da slli ra,ra,0x16 - 5408: 1200 addi s0,sp,288 - 540a: 0aa9 addi s5,s5,10 - 540c: 0000 unimp - 540e: 2e01 jal 571e <_start-0x7fffa8e2> - 5410: 00010603 lb a2,0(sp) - 5414: 2d00 fld fs0,24(a0) - 5416: 00da slli ra,ra,0x16 - 5418: 0000 unimp - 541a: 1b00 addi s0,sp,432 - 541c: 0ec0 addi s0,sp,852 - 541e: 0000 unimp - 5420: 5712 lw a4,36(sp) - 5422: 000a c.slli zero,0x2 - 5424: 0100 addi s0,sp,128 - 5426: 032e slli t1,t1,0xb - 5428: 0025 c.nop 9 - 542a: 0000 unimp - 542c: da61 beqz a2,53fc <_start-0x7fffac04> - 542e: 0000 unimp - 5430: 000ed81b 0xed81b - 5434: 1200 addi s0,sp,288 - 5436: 00000ad7 vadd.vv v21,v0,v0,v0.t - 543a: 2e01 jal 574a <_start-0x7fffa8b6> - 543c: 000d6f03 0xd6f03 - 5440: 7b00 flw fs0,48(a4) - 5442: 00da slli ra,ra,0x16 - 5444: 1200 addi s0,sp,288 - 5446: 0a6d addi s4,s4,27 - 5448: 0000 unimp - 544a: 2e01 jal 575a <_start-0x7fffa8a6> - 544c: 000d6f03 0xd6f03 - 5450: 8f00 0x8f00 - 5452: 00da slli ra,ra,0x16 - 5454: 1200 addi s0,sp,288 - 5456: 0a94 addi a3,sp,336 - 5458: 0000 unimp - 545a: 2e01 jal 576a <_start-0x7fffa896> - 545c: 000d6f03 0xd6f03 - 5460: a300 fsd fs0,0(a4) - 5462: 00da slli ra,ra,0x16 - 5464: 1200 addi s0,sp,288 - 5466: 0a82 c.slli64 s5 - 5468: 0000 unimp - 546a: 2e01 jal 577a <_start-0x7fffa886> - 546c: 000d6f03 0xd6f03 - 5470: b700 fsd fs0,40(a4) - 5472: 00da slli ra,ra,0x16 - 5474: 1200 addi s0,sp,288 - 5476: 0aa9 addi s5,s5,10 - 5478: 0000 unimp - 547a: 2e01 jal 578a <_start-0x7fffa876> - 547c: 00010603 lb a2,0(sp) - 5480: d700 sw s0,40(a4) - 5482: 00da slli ra,ra,0x16 - 5484: 0000 unimp - 5486: 0000 unimp - 5488: 000f5817 auipc a6,0xf5 - 548c: 1800 addi s0,sp,48 - 548e: 000c 0xc - 5490: 1900 addi s0,sp,176 - 5492: 00000fa3 sb zero,31(zero) # 1f <_start-0x7fffffe1> - 5496: 2e01 jal 57a6 <_start-0x7fffa85a> - 5498: 01332403 lw s0,19(t1) - 549c: 1980 addi s0,sp,240 - 549e: 0f89 addi t6,t6,2 - 54a0: 0000 unimp - 54a2: 2e01 jal 57b2 <_start-0x7fffa84e> - 54a4: 0135f803 0x135f803 - 54a8: 1980 addi s0,sp,240 - 54aa: 107d c.nop -1 - 54ac: 0000 unimp - 54ae: 2e01 jal 57be <_start-0x7fffa842> - 54b0: 0134a403 lw s0,19(s1) - 54b4: 1980 addi s0,sp,240 - 54b6: 000010bf 64032e01 0x64032e01000010bf - 54be: 013a slli sp,sp,0xe - 54c0: 1980 addi s0,sp,240 - 54c2: 1099 addi ra,ra,-26 - 54c4: 0000 unimp - 54c6: 2e01 jal 57d6 <_start-0x7fffa82a> - 54c8: 012c5c03 lhu s8,18(s8) - 54cc: 1280 addi s0,sp,352 - 54ce: 1082 slli ra,ra,0x20 - 54d0: 0000 unimp - 54d2: 2e01 jal 57e2 <_start-0x7fffa81e> - 54d4: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 54d8: f600 fsw fs0,40(a2) - 54da: 00da slli ra,ra,0x16 - 54dc: 1a00 addi s0,sp,304 - 54de: 326c fld fa1,224(a2) - 54e0: 8001 c.srli64 s0 - 54e2: 0068 addi a0,sp,12 - 54e4: 0000 unimp - 54e6: 07b9 addi a5,a5,14 - 54e8: 0000 unimp - 54ea: a212 fsd ft4,256(sp) - 54ec: 0010 0x10 - 54ee: 0100 addi s0,sp,128 - 54f0: 032e slli t1,t1,0xb - 54f2: 0106 slli sp,sp,0x1 - 54f4: 0000 unimp - 54f6: dc7f 0xdc7f - 54f8: 0000 unimp - 54fa: c412 sw tp,8(sp) - 54fc: 0010 0x10 - 54fe: 0100 addi s0,sp,128 - 5500: 032e slli t1,t1,0xb - 5502: 0106 slli sp,sp,0x1 - 5504: 0000 unimp - 5506: dcdc sw a5,60(s1) - 5508: 0000 unimp - 550a: 6812 flw fa6,4(sp) - 550c: 0100000f fence w,unknown - 5510: 032e slli t1,t1,0xb - 5512: 0106 slli sp,sp,0x1 - 5514: 0000 unimp - 5516: dd06 sw ra,184(sp) - 5518: 0000 unimp - 551a: 1a00 addi s0,sp,304 - 551c: 3330 fld fa2,96(a4) - 551e: 8001 c.srli64 s0 - 5520: 00fc addi a5,sp,76 - 5522: 0000 unimp - 5524: 082d addi a6,a6,11 - 5526: 0000 unimp - 5528: 5712 lw a4,36(sp) - 552a: 000a c.slli zero,0x2 - 552c: 0100 addi s0,sp,128 - 552e: 032e slli t1,t1,0xb - 5530: 0025 c.nop 9 - 5532: 0000 unimp - 5534: 0000dd53 fadd.s fs10,ft1,ft0,unknown - 5538: 0010381b 0x10381b - 553c: 1200 addi s0,sp,288 - 553e: 00000ad7 vadd.vv v21,v0,v0,v0.t - 5542: 2e01 jal 5852 <_start-0x7fffa7ae> - 5544: 000d6f03 0xd6f03 - 5548: 6d00 flw fs0,24(a0) - 554a: 00dd addi ra,ra,23 - 554c: 1200 addi s0,sp,288 - 554e: 0a6d addi s4,s4,27 - 5550: 0000 unimp - 5552: 2e01 jal 5862 <_start-0x7fffa79e> - 5554: 000d6f03 0xd6f03 - 5558: a500 fsd fs0,8(a0) - 555a: 00dd addi ra,ra,23 - 555c: 1200 addi s0,sp,288 - 555e: 0a94 addi a3,sp,336 - 5560: 0000 unimp - 5562: 2e01 jal 5872 <_start-0x7fffa78e> - 5564: 000d6f03 0xd6f03 - 5568: ce00 sw s0,24(a2) - 556a: 00dd addi ra,ra,23 - 556c: 1200 addi s0,sp,288 - 556e: 0a82 c.slli64 s5 - 5570: 0000 unimp - 5572: 2e01 jal 5882 <_start-0x7fffa77e> - 5574: 000d6f03 0xd6f03 - 5578: e100 fsw fs0,0(a0) - 557a: 00dd addi ra,ra,23 - 557c: 1200 addi s0,sp,288 - 557e: 0aa9 addi s5,s5,10 - 5580: 0000 unimp - 5582: 2e01 jal 5892 <_start-0x7fffa76e> - 5584: 00010603 lb a2,0(sp) - 5588: 8f00 0x8f00 - 558a: 00de slli ra,ra,0x17 - 558c: 0000 unimp - 558e: 1a00 addi s0,sp,304 - 5590: 342c fld fa1,104(s0) - 5592: 8001 c.srli64 s0 - 5594: 0078 addi a4,sp,12 - 5596: 0000 unimp - 5598: 0000086b 0x86b - 559c: a212 fsd ft4,256(sp) - 559e: 0010 0x10 - 55a0: 0100 addi s0,sp,128 - 55a2: 032e slli t1,t1,0xb - 55a4: 0106 slli sp,sp,0x1 - 55a6: 0000 unimp - 55a8: deae sw a1,124(sp) - 55aa: 0000 unimp - 55ac: c412 sw tp,8(sp) - 55ae: 0010 0x10 - 55b0: 0100 addi s0,sp,128 - 55b2: 032e slli t1,t1,0xb - 55b4: 0106 slli sp,sp,0x1 - 55b6: 0000 unimp - 55b8: 0000df0b 0xdf0b - 55bc: 6812 flw fa6,4(sp) - 55be: 0100000f fence w,unknown - 55c2: 032e slli t1,t1,0xb - 55c4: 0106 slli sp,sp,0x1 - 55c6: 0000 unimp - 55c8: df35 beqz a4,5544 <_start-0x7fffaabc> - 55ca: 0000 unimp - 55cc: 1700 addi s0,sp,928 - 55ce: 1050 addi a2,sp,36 - 55d0: 0000 unimp - 55d2: 08a5 addi a7,a7,9 - 55d4: 0000 unimp - 55d6: a212 fsd ft4,256(sp) - 55d8: 0010 0x10 - 55da: 0100 addi s0,sp,128 - 55dc: 032e slli t1,t1,0xb - 55de: 0106 slli sp,sp,0x1 - 55e0: 0000 unimp - 55e2: 0000df63 bgez ra,5600 <_start-0x7fffaa00> - 55e6: c412 sw tp,8(sp) - 55e8: 0010 0x10 - 55ea: 0100 addi s0,sp,128 - 55ec: 032e slli t1,t1,0xb - 55ee: 0106 slli sp,sp,0x1 - 55f0: 0000 unimp - 55f2: 0000dfbf 000f6812 0xf68120000dfbf - 55fa: 0100 addi s0,sp,128 - 55fc: 032e slli t1,t1,0xb - 55fe: 0106 slli sp,sp,0x1 - 5600: 0000 unimp - 5602: dfe9 beqz a5,55dc <_start-0x7fffaa24> - 5604: 0000 unimp - 5606: 1700 addi s0,sp,928 - 5608: 1068 addi a0,sp,44 - 560a: 0000 unimp - 560c: 0915 addi s2,s2,5 - 560e: 0000 unimp - 5610: 5712 lw a4,36(sp) - 5612: 000a c.slli zero,0x2 - 5614: 0100 addi s0,sp,128 - 5616: 032e slli t1,t1,0xb - 5618: 0025 c.nop 9 - 561a: 0000 unimp - 561c: 0000e017 auipc zero,0xe - 5620: 0010801b 0x10801b - 5624: 1200 addi s0,sp,288 - 5626: 00000ad7 vadd.vv v21,v0,v0,v0.t - 562a: 2e01 jal 593a <_start-0x7fffa6c6> - 562c: 000d6f03 0xd6f03 - 5630: 3100 fld fs0,32(a0) - 5632: 00e0 addi s0,sp,76 - 5634: 1200 addi s0,sp,288 - 5636: 0a6d addi s4,s4,27 - 5638: 0000 unimp - 563a: 2e01 jal 594a <_start-0x7fffa6b6> - 563c: 000d6f03 0xd6f03 - 5640: 6900 flw fs0,16(a0) - 5642: 00e0 addi s0,sp,76 - 5644: 1200 addi s0,sp,288 - 5646: 0a94 addi a3,sp,336 - 5648: 0000 unimp - 564a: 2e01 jal 595a <_start-0x7fffa6a6> - 564c: 000d6f03 0xd6f03 - 5650: 9200 0x9200 - 5652: 00e0 addi s0,sp,76 - 5654: 1200 addi s0,sp,288 - 5656: 0a82 c.slli64 s5 - 5658: 0000 unimp - 565a: 2e01 jal 596a <_start-0x7fffa696> - 565c: 000d6f03 0xd6f03 - 5660: b000 fsd fs0,32(s0) - 5662: 00e0 addi s0,sp,76 - 5664: 1200 addi s0,sp,288 - 5666: 0aa9 addi s5,s5,10 - 5668: 0000 unimp - 566a: 2e01 jal 597a <_start-0x7fffa686> - 566c: 00010603 lb a2,0(sp) - 5670: 5e00 lw s0,56(a2) - 5672: 00e1 addi ra,ra,24 - 5674: 0000 unimp - 5676: 1700 addi s0,sp,928 - 5678: 10a0 addi s0,sp,104 - 567a: 0000 unimp - 567c: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 5680: a212 fsd ft4,256(sp) - 5682: 0010 0x10 - 5684: 0100 addi s0,sp,128 - 5686: 032e slli t1,t1,0xb - 5688: 0106 slli sp,sp,0x1 - 568a: 0000 unimp - 568c: e188 fsw fa0,0(a1) - 568e: 0000 unimp - 5690: c412 sw tp,8(sp) - 5692: 0010 0x10 - 5694: 0100 addi s0,sp,128 - 5696: 032e slli t1,t1,0xb - 5698: 0106 slli sp,sp,0x1 - 569a: 0000 unimp - 569c: e1e4 fsw fs1,68(a1) - 569e: 0000 unimp - 56a0: 6812 flw fa6,4(sp) - 56a2: 0100000f fence w,unknown - 56a6: 032e slli t1,t1,0xb - 56a8: 0106 slli sp,sp,0x1 - 56aa: 0000 unimp - 56ac: e20e fsw ft3,4(sp) - 56ae: 0000 unimp - 56b0: 1a00 addi s0,sp,304 - 56b2: 3828 fld fa0,112(s0) - 56b4: 8001 c.srli64 s0 - 56b6: 005c addi a5,sp,4 - 56b8: 0000 unimp - 56ba: 098d addi s3,s3,3 - 56bc: 0000 unimp - 56be: a212 fsd ft4,256(sp) - 56c0: 0010 0x10 - 56c2: 0100 addi s0,sp,128 - 56c4: 032e slli t1,t1,0xb - 56c6: 0106 slli sp,sp,0x1 - 56c8: 0000 unimp - 56ca: e23c fsw fa5,64(a2) - 56cc: 0000 unimp - 56ce: c412 sw tp,8(sp) - 56d0: 0010 0x10 - 56d2: 0100 addi s0,sp,128 - 56d4: 032e slli t1,t1,0xb - 56d6: 0106 slli sp,sp,0x1 - 56d8: 0000 unimp - 56da: 0000e2f3 csrrsi t0,ustatus,1 - 56de: 6812 flw fa6,4(sp) - 56e0: 0100000f fence w,unknown - 56e4: 032e slli t1,t1,0xb - 56e6: 0106 slli sp,sp,0x1 - 56e8: 0000 unimp - 56ea: e31d bnez a4,5710 <_start-0x7fffa8f0> - 56ec: 0000 unimp - 56ee: 1a00 addi s0,sp,304 - 56f0: 388c fld fa1,48(s1) - 56f2: 8001 c.srli64 s0 - 56f4: 005c addi a5,sp,4 - 56f6: 0000 unimp - 56f8: 000009cb fnmsub.s fs3,ft0,ft0,ft0,rne - 56fc: a212 fsd ft4,256(sp) - 56fe: 0010 0x10 - 5700: 0100 addi s0,sp,128 - 5702: 032e slli t1,t1,0xb - 5704: 0106 slli sp,sp,0x1 - 5706: 0000 unimp - 5708: 0000e34b fnmsub.s ft6,ft1,ft0,ft0,unknown - 570c: c412 sw tp,8(sp) - 570e: 0010 0x10 - 5710: 0100 addi s0,sp,128 - 5712: 032e slli t1,t1,0xb - 5714: 0106 slli sp,sp,0x1 - 5716: 0000 unimp - 5718: e38a fsw ft2,196(sp) - 571a: 0000 unimp - 571c: 6812 flw fa6,4(sp) - 571e: 0100000f fence w,unknown - 5722: 032e slli t1,t1,0xb - 5724: 0106 slli sp,sp,0x1 - 5726: 0000 unimp - 5728: e3a9 bnez a5,576a <_start-0x7fffa896> - 572a: 0000 unimp - 572c: 1a00 addi s0,sp,304 - 572e: 3914 fld fa3,48(a0) - 5730: 8001 c.srli64 s0 - 5732: 0028 addi a0,sp,8 - 5734: 0000 unimp - 5736: 0a19 addi s4,s4,6 - 5738: 0000 unimp - 573a: 3c12 fld fs8,288(sp) - 573c: 0100000f fence w,unknown - 5740: 032e slli t1,t1,0xb - 5742: 00000d6f jal s10,5742 <_start-0x7fffa8be> - 5746: 0000e3d7 0xe3d7 - 574a: 7712 flw fa4,36(sp) - 574c: 000d c.nop 3 - 574e: 0100 addi s0,sp,128 - 5750: 032e slli t1,t1,0xb - 5752: 00000d6f jal s10,5752 <_start-0x7fffa8ae> - 5756: 0000e3eb 0xe3eb - 575a: 6312 flw ft6,4(sp) - 575c: 000d c.nop 3 - 575e: 0100 addi s0,sp,128 - 5760: 032e slli t1,t1,0xb - 5762: 00000d6f jal s10,5762 <_start-0x7fffa89e> - 5766: e3ff 0xe3ff - 5768: 0000 unimp - 576a: c912 sw tp,144(sp) - 576c: 000d c.nop 3 - 576e: 0100 addi s0,sp,128 - 5770: 032e slli t1,t1,0xb - 5772: 00000d6f jal s10,5772 <_start-0x7fffa88e> - 5776: 0000e413 ori s0,ra,0 - 577a: 1c00 addi s0,sp,560 - 577c: 00000a4f fnmadd.s fs4,ft0,ft0,ft0,rne - 5780: 4e1d li t3,7 - 5782: 000e c.slli zero,0x3 - 5784: 0100 addi s0,sp,128 - 5786: 032e slli t1,t1,0xb - 5788: 00000d6f jal s10,5788 <_start-0x7fffa878> - 578c: ee1d bnez a2,57ca <_start-0x7fffa836> - 578e: 000d c.nop 3 - 5790: 0100 addi s0,sp,128 - 5792: 032e slli t1,t1,0xb - 5794: 00000d6f jal s10,5794 <_start-0x7fffa86c> - 5798: 021d addi tp,tp,7 - 579a: 000e c.slli zero,0x3 - 579c: 0100 addi s0,sp,128 - 579e: 032e slli t1,t1,0xb - 57a0: 00000d6f jal s10,57a0 <_start-0x7fffa860> - 57a4: a71d j 5eca <_start-0x7fffa136> - 57a6: 000d c.nop 3 - 57a8: 0100 addi s0,sp,128 - 57aa: 032e slli t1,t1,0xb - 57ac: 00000d6f jal s10,57ac <_start-0x7fffa854> - 57b0: 1c00 addi s0,sp,560 - 57b2: 0a85 addi s5,s5,1 - 57b4: 0000 unimp - 57b6: 4e1d li t3,7 - 57b8: 000e c.slli zero,0x3 - 57ba: 0100 addi s0,sp,128 - 57bc: 032e slli t1,t1,0xb - 57be: 00000d6f jal s10,57be <_start-0x7fffa842> - 57c2: ee1d bnez a2,5800 <_start-0x7fffa800> - 57c4: 000d c.nop 3 - 57c6: 0100 addi s0,sp,128 - 57c8: 032e slli t1,t1,0xb - 57ca: 00000d6f jal s10,57ca <_start-0x7fffa836> - 57ce: 021d addi tp,tp,7 - 57d0: 000e c.slli zero,0x3 - 57d2: 0100 addi s0,sp,128 - 57d4: 032e slli t1,t1,0xb - 57d6: 00000d6f jal s10,57d6 <_start-0x7fffa82a> - 57da: a71d j 5f00 <_start-0x7fffa100> - 57dc: 000d c.nop 3 - 57de: 0100 addi s0,sp,128 - 57e0: 032e slli t1,t1,0xb - 57e2: 00000d6f jal s10,57e2 <_start-0x7fffa81e> - 57e6: 1700 addi s0,sp,928 - 57e8: 1010 addi a2,sp,32 - 57ea: 0000 unimp - 57ec: 00000acf fnmadd.s fs5,ft0,ft0,ft0,rne - 57f0: 3c12 fld fs8,288(sp) - 57f2: 0100000f fence w,unknown - 57f6: 032e slli t1,t1,0xb - 57f8: 00000d6f jal s10,57f8 <_start-0x7fffa808> - 57fc: 0000e427 vsw.v v8,(ra),v0.t - 5800: 7712 flw fa4,36(sp) - 5802: 000d c.nop 3 - 5804: 0100 addi s0,sp,128 - 5806: 032e slli t1,t1,0xb - 5808: 00000d6f jal s10,5808 <_start-0x7fffa7f8> - 580c: 0000e43b 0xe43b - 5810: 6312 flw ft6,4(sp) - 5812: 000d c.nop 3 - 5814: 0100 addi s0,sp,128 - 5816: 032e slli t1,t1,0xb - 5818: 00000d6f jal s10,5818 <_start-0x7fffa7e8> - 581c: 0000e44f fnmadd.s fs0,ft1,ft0,ft0,unknown - 5820: c912 sw tp,144(sp) - 5822: 000d c.nop 3 - 5824: 0100 addi s0,sp,128 - 5826: 032e slli t1,t1,0xb - 5828: 00000d6f jal s10,5828 <_start-0x7fffa7d8> - 582c: 0000e463 bltu ra,zero,5834 <_start-0x7fffa7cc> - 5830: 1a00 addi s0,sp,304 - 5832: 39a8 fld fa0,112(a1) - 5834: 8001 c.srli64 s0 - 5836: 005c addi a5,sp,4 - 5838: 0000 unimp - 583a: 0b0d addi s6,s6,3 - 583c: 0000 unimp - 583e: a212 fsd ft4,256(sp) - 5840: 0010 0x10 - 5842: 0100 addi s0,sp,128 - 5844: 032e slli t1,t1,0xb - 5846: 0106 slli sp,sp,0x1 - 5848: 0000 unimp - 584a: e484 fsw fs1,8(s1) - 584c: 0000 unimp - 584e: c412 sw tp,8(sp) - 5850: 0010 0x10 - 5852: 0100 addi s0,sp,128 - 5854: 032e slli t1,t1,0xb - 5856: 0106 slli sp,sp,0x1 - 5858: 0000 unimp - 585a: e55e fsw fs7,136(sp) - 585c: 0000 unimp - 585e: 6812 flw fa6,4(sp) - 5860: 0100000f fence w,unknown - 5864: 032e slli t1,t1,0xb - 5866: 0106 slli sp,sp,0x1 - 5868: 0000 unimp - 586a: e588 fsw fa0,8(a1) - 586c: 0000 unimp - 586e: 1a00 addi s0,sp,304 - 5870: 3a0c fld fa1,48(a2) - 5872: 8001 c.srli64 s0 - 5874: 0054 addi a3,sp,4 - 5876: 0000 unimp - 5878: 00000b4b fnmsub.s fs6,ft0,ft0,ft0,rne - 587c: a212 fsd ft4,256(sp) - 587e: 0010 0x10 - 5880: 0100 addi s0,sp,128 - 5882: 032e slli t1,t1,0xb - 5884: 0106 slli sp,sp,0x1 - 5886: 0000 unimp - 5888: e5c1 bnez a1,5910 <_start-0x7fffa6f0> - 588a: 0000 unimp - 588c: c412 sw tp,8(sp) - 588e: 0010 0x10 - 5890: 0100 addi s0,sp,128 - 5892: 032e slli t1,t1,0xb - 5894: 0106 slli sp,sp,0x1 - 5896: 0000 unimp - 5898: e61d bnez a2,58c6 <_start-0x7fffa73a> - 589a: 0000 unimp - 589c: 6812 flw fa6,4(sp) - 589e: 0100000f fence w,unknown - 58a2: 032e slli t1,t1,0xb - 58a4: 0106 slli sp,sp,0x1 - 58a6: 0000 unimp - 58a8: e63c fsw fa5,72(a2) - 58aa: 0000 unimp - 58ac: 1b00 addi s0,sp,432 - 58ae: 0fa0 addi s0,sp,984 - 58b0: 0000 unimp - 58b2: 6712 flw fa4,4(sp) - 58b4: 0010 0x10 - 58b6: 0100 addi s0,sp,128 - 58b8: 032e slli t1,t1,0xb - 58ba: 0025 c.nop 9 - 58bc: 0000 unimp - 58be: e67a fsw ft10,12(sp) - 58c0: 0000 unimp - 58c2: 000fc817 auipc a6,0xfc - 58c6: aa00 fsd fs0,16(a2) - 58c8: 1200000b 0x1200000b - 58cc: 0f3c addi a5,sp,920 - 58ce: 0000 unimp - 58d0: 2e01 jal 5be0 <_start-0x7fffa420> - 58d2: 000d6f03 0xd6f03 - 58d6: c400 sw s0,8(s0) - 58d8: 00e6 slli ra,ra,0x19 - 58da: 1200 addi s0,sp,288 - 58dc: 00000d77 0xd77 - 58e0: 2e01 jal 5bf0 <_start-0x7fffa410> - 58e2: 000d6f03 0xd6f03 - 58e6: 3200 fld fs0,32(a2) - 58e8: 120000e7 jalr 288(zero) # 0 <_start-0x80000000> - 58ec: 00000d63 beqz zero,5906 <_start-0x7fffa6fa> - 58f0: 2e01 jal 5c00 <_start-0x7fffa400> - 58f2: 000d6f03 0xd6f03 - 58f6: cc00 sw s0,24(s0) - 58f8: 120000e7 jalr 288(zero) # 0 <_start-0x80000000> - 58fc: 0dc9 addi s11,s11,18 - 58fe: 0000 unimp - 5900: 2e01 jal 5c10 <_start-0x7fffa3f0> - 5902: 000d6f03 0xd6f03 - 5906: 4f00 lw s0,24(a4) - 5908: 00e8 addi a0,sp,76 - 590a: 0000 unimp - 590c: 000fe01b 0xfe01b - 5910: 1200 addi s0,sp,288 - 5912: 00000a57 vadd.vv v20,v0,v0,v0.t - 5916: 2e01 jal 5c26 <_start-0x7fffa3da> - 5918: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 591c: 8300 0x8300 - 591e: 00e8 addi a0,sp,76 - 5920: 1b00 addi s0,sp,432 - 5922: 0ff8 addi a4,sp,988 - 5924: 0000 unimp - 5926: d712 sw tp,172(sp) - 5928: 000a c.slli zero,0x2 - 592a: 0100 addi s0,sp,128 - 592c: 032e slli t1,t1,0xb - 592e: 00000d6f jal s10,592e <_start-0x7fffa6d2> - 5932: e89d bnez s1,5968 <_start-0x7fffa698> - 5934: 0000 unimp - 5936: 6d12 flw fs10,4(sp) - 5938: 000a c.slli zero,0x2 - 593a: 0100 addi s0,sp,128 - 593c: 032e slli t1,t1,0xb - 593e: 00000d6f jal s10,593e <_start-0x7fffa6c2> - 5942: e8d5 bnez s1,59f6 <_start-0x7fffa60a> - 5944: 0000 unimp - 5946: 9412 add s0,s0,tp - 5948: 000a c.slli zero,0x2 - 594a: 0100 addi s0,sp,128 - 594c: 032e slli t1,t1,0xb - 594e: 00000d6f jal s10,594e <_start-0x7fffa6b2> - 5952: e8fe fsw ft11,80(sp) - 5954: 0000 unimp - 5956: 8212 mv tp,tp - 5958: 000a c.slli zero,0x2 - 595a: 0100 addi s0,sp,128 - 595c: 032e slli t1,t1,0xb - 595e: 00000d6f jal s10,595e <_start-0x7fffa6a2> - 5962: e932 fsw fa2,144(sp) - 5964: 0000 unimp - 5966: a912 fsd ft4,144(sp) - 5968: 000a c.slli zero,0x2 - 596a: 0100 addi s0,sp,128 - 596c: 032e slli t1,t1,0xb - 596e: 0106 slli sp,sp,0x1 - 5970: 0000 unimp - 5972: e9d4 fsw fa3,20(a1) - 5974: 0000 unimp - 5976: 0000 unimp - 5978: 0000 unimp - 597a: 0010b817 auipc a6,0x10b - 597e: 5800 lw s0,48(s0) - 5980: 000d c.nop 3 - 5982: 1200 addi s0,sp,288 - 5984: 1039 c.nop -18 - 5986: 0000 unimp - 5988: 2f01 jal 6098 <_start-0x7fff9f68> - 598a: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 598e: e700 fsw fs0,8(a4) - 5990: 00e9 addi ra,ra,26 - 5992: 1c00 addi s0,sp,560 - 5994: 00000ccf fnmadd.s fs9,ft0,ft0,ft0,rne - 5998: 8e1d sub a2,a2,a5 - 599a: 0100000f fence w,unknown - 599e: 0d6f032f 0xd6f032f - 59a2: 0000 unimp - 59a4: d61d beqz a2,58d2 <_start-0x7fffa72e> - 59a6: 0100000f fence w,unknown - 59aa: 0d6f032f 0xd6f032f - 59ae: 0000 unimp - 59b0: 241d jal 5bd6 <_start-0x7fffa42a> - 59b2: 0010 0x10 - 59b4: 0100 addi s0,sp,128 - 59b6: 0d6f032f 0xd6f032f - 59ba: 0000 unimp - 59bc: 521d li tp,-25 - 59be: 0010 0x10 - 59c0: 0100 addi s0,sp,128 - 59c2: 0d76032f 0xd76032f - 59c6: 0000 unimp - 59c8: 9c1c 0x9c1c - 59ca: 000c 0xc - 59cc: 1d00 addi s0,sp,688 - 59ce: 0f3c addi a5,sp,920 - 59d0: 0000 unimp - 59d2: 2f01 jal 60e2 <_start-0x7fff9f1e> - 59d4: 000d6f03 0xd6f03 - 59d8: 1d00 addi s0,sp,688 - 59da: 00000d77 0xd77 - 59de: 2f01 jal 60ee <_start-0x7fff9f12> - 59e0: 000d6f03 0xd6f03 - 59e4: 1d00 addi s0,sp,688 - 59e6: 00000d63 beqz zero,5a00 <_start-0x7fffa600> - 59ea: 2f01 jal 60fa <_start-0x7fff9f06> - 59ec: 000d6f03 0xd6f03 - 59f0: 1d00 addi s0,sp,688 - 59f2: 0dc9 addi s11,s11,18 - 59f4: 0000 unimp - 59f6: 2f01 jal 6106 <_start-0x7fff9efa> - 59f8: 000d6f03 0xd6f03 - 59fc: 0000 unimp - 59fe: ae1c fsd fa5,24(a2) - 5a00: 000c 0xc - 5a02: 1d00 addi s0,sp,688 - 5a04: 0f29 addi t5,t5,10 - 5a06: 0000 unimp - 5a08: 2f01 jal 6118 <_start-0x7fff9ee8> - 5a0a: 00010603 lb a2,0(sp) - 5a0e: 0000 unimp - 5a10: c01c sw a5,0(s0) - 5a12: 000c 0xc - 5a14: 1d00 addi s0,sp,688 - 5a16: 0f29 addi t5,t5,10 - 5a18: 0000 unimp - 5a1a: 2f01 jal 612a <_start-0x7fff9ed6> - 5a1c: 00010603 lb a2,0(sp) - 5a20: 0000 unimp - 5a22: 1d1e slli s10,s10,0x27 - 5a24: 0f29 addi t5,t5,10 - 5a26: 0000 unimp - 5a28: 2f01 jal 6138 <_start-0x7fff9ec8> - 5a2a: 00010603 lb a2,0(sp) - 5a2e: 0000 unimp - 5a30: 1a00 addi s0,sp,304 - 5a32: 2c74 fld fa3,216(s0) - 5a34: 8001 c.srli64 s0 - 5a36: 0038 addi a4,sp,8 - 5a38: 0000 unimp - 5a3a: 0ced addi s9,s9,27 - 5a3c: 0000 unimp - 5a3e: 2912 fld fs2,256(sp) - 5a40: 0100000f fence w,unknown - 5a44: 0106032f 0x106032f - 5a48: 0000 unimp - 5a4a: 0000ea07 vlwu.v v20,(ra),v0.t - 5a4e: 1c00 addi s0,sp,560 - 5a50: 0cff 0xcff - 5a52: 0000 unimp - 5a54: 291d jal 5e8a <_start-0x7fffa176> - 5a56: 0100000f fence w,unknown - 5a5a: 0106032f 0x106032f - 5a5e: 0000 unimp - 5a60: 1c00 addi s0,sp,560 - 5a62: 0d11 addi s10,s10,4 - 5a64: 0000 unimp - 5a66: 291d jal 5e9c <_start-0x7fffa164> - 5a68: 0100000f fence w,unknown - 5a6c: 0106032f 0x106032f - 5a70: 0000 unimp - 5a72: 1b00 addi s0,sp,432 - 5a74: 10d0 addi a2,sp,100 - 5a76: 0000 unimp - 5a78: 4e12 lw t3,4(sp) - 5a7a: 000e c.slli zero,0x3 - 5a7c: 0100 addi s0,sp,128 - 5a7e: 0d6f032f 0xd6f032f - 5a82: 0000 unimp - 5a84: ea7d bnez a2,5b7a <_start-0x7fffa486> - 5a86: 0000 unimp - 5a88: ee12 fsw ft4,28(sp) - 5a8a: 000d c.nop 3 - 5a8c: 0100 addi s0,sp,128 - 5a8e: 0d6f032f 0xd6f032f - 5a92: 0000 unimp - 5a94: ea91 bnez a3,5aa8 <_start-0x7fffa558> - 5a96: 0000 unimp - 5a98: 0212 slli tp,tp,0x4 - 5a9a: 000e c.slli zero,0x3 - 5a9c: 0100 addi s0,sp,128 - 5a9e: 0d6f032f 0xd6f032f - 5aa2: 0000 unimp - 5aa4: eaa5 bnez a3,5b14 <_start-0x7fffa4ec> - 5aa6: 0000 unimp - 5aa8: a712 fsd ft4,392(sp) - 5aaa: 000d c.nop 3 - 5aac: 0100 addi s0,sp,128 - 5aae: 0d6f032f 0xd6f032f - 5ab2: 0000 unimp - 5ab4: eab9 bnez a3,5b0a <_start-0x7fffa4f6> - 5ab6: 0000 unimp - 5ab8: 0000 unimp - 5aba: 0010e81b 0x10e81b - 5abe: 1800 addi s0,sp,48 - 5ac0: 0d3e slli s10,s10,0xf - 5ac2: 0000 unimp - 5ac4: 2f01 jal 61d4 <_start-0x7fff9e2c> - 5ac6: 00010d03 lb s10,0(sp) - 5aca: 0300 addi s0,sp,384 - 5acc: a091 j 5b10 <_start-0x7fffa4f0> - 5ace: 007f 0x7f - 5ad0: 0300 addi s0,sp,384 - 5ad2: 0504 addi s1,sp,640 - 5ad4: 0222 slli tp,tp,0x8 - 5ad6: 0000 unimp - 5ad8: 061f 0001 0700 0x7000001061f - 5ade: 00000053 fadd.s ft0,ft0,ft0,rne - 5ae2: c1000003 lb zero,-1008(zero) # fffffc10 <__BSS_END__+0x7ffe8e98> - 5ae6: 0002 c.slli64 zero - 5ae8: 0400 addi s0,sp,512 - 5aea: fe00 fsw fs0,56(a2) - 5aec: 0010 0x10 - 5aee: 0400 addi s0,sp,512 - 5af0: f201 bnez a2,59f0 <_start-0x7fffa610> - 5af2: 0c000007 vlxbu.v v0,(zero),v0,v0.t - 5af6: 10ea slli ra,ra,0x3a - 5af8: 0000 unimp - 5afa: 02fc addi a5,sp,332 - 5afc: 0000 unimp - 5afe: 3ce4 fld fs1,248(s1) - 5b00: 8001 c.srli64 s0 - 5b02: 0150 addi a2,sp,132 - 5b04: 0000 unimp - 5b06: 7619 lui a2,0xfffe6 - 5b08: 0000 unimp - 5b0a: 0402 c.slli64 s0 - 5b0c: 6905 lui s2,0x1 - 5b0e: 746e flw fs0,248(sp) - 5b10: 0300 addi s0,sp,384 - 5b12: 0601 addi a2,a2,0 - 5b14: 0669 addi a2,a2,26 - 5b16: 0000 unimp - 5b18: 1604 addi s1,sp,800 - 5b1a: 0002 c.slli64 zero - 5b1c: 0200 addi s0,sp,256 - 5b1e: 0148 addi a0,sp,132 - 5b20: 250d jal 6142 <_start-0x7fff9ebe> - 5b22: 0000 unimp - 5b24: 0300 addi s0,sp,384 - 5b26: 0508 addi a0,sp,640 - 5b28: 021d addi tp,tp,7 - 5b2a: 0000 unimp - 5b2c: 7304 flw fs1,32(a4) - 5b2e: 02000007 vlbu.v v0,(zero) - 5b32: 014a slli sp,sp,0x12 - 5b34: 5916 lw s2,100(sp) - 5b36: 0000 unimp - 5b38: 0500 addi s0,sp,640 - 5b3a: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne - 5b3e: 67080103 lb sp,1648(a6) # 110fea <_start-0x7feef016> - 5b42: 0006 c.slli zero,0x1 - 5b44: 0400 addi s0,sp,512 - 5b46: 0215 addi tp,tp,5 - 5b48: 0000 unimp - 5b4a: 4b02 lw s6,0(sp) - 5b4c: 1601 addi a2,a2,-32 - 5b4e: 006d c.nop 27 - 5b50: 0000 unimp - 5b52: 6e070403 lb s0,1760(a4) - 5b56: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 5b5a: 0708 addi a0,sp,896 - 5b5c: 0364 addi s1,sp,396 - 5b5e: 0000 unimp - 5b60: 84070203 lb tp,-1984(a4) - 5b64: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 5b68: 0054 addi a3,sp,4 - 5b6a: 0000 unimp - 5b6c: 0092 slli ra,ra,0x4 - 5b6e: 0000 unimp - 5b70: 00006d07 vlwu.v v26,(zero),v0.t - 5b74: ff00 fsw fs0,56(a4) - 5b76: 0500 addi s0,sp,640 - 5b78: 0082 c.slli64 ra - 5b7a: 0000 unimp - 5b7c: 9708 0x9708 - 5b7e: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - 5b82: 163c addi a5,sp,808 - 5b84: 0092 slli ra,ra,0x4 - 5b86: 0000 unimp - 5b88: 0109 addi sp,sp,2 - 5b8a: 000c 0xc - 5b8c: 0300 addi s0,sp,384 - 5b8e: 0f48 addi a0,sp,916 - 5b90: 000000af 0xaf - 5b94: 9d041003 lh zero,-1584(s0) - 5b98: 0000 unimp - 5b9a: 0a00 addi s0,sp,272 - 5b9c: 0310 addi a2,sp,384 - 5b9e: 0120034f fnmadd.s ft6,ft0,fs2,ft0,rne - 5ba2: 0000 unimp - 5ba4: 0008bd0b 0x8bd0b - 5ba8: 0300 addi s0,sp,384 - 5baa: 1359 addi t1,t1,-10 - 5bac: 0120 addi s0,sp,136 - 5bae: 0000 unimp - 5bb0: 2004 fld fs1,0(s0) - 5bb2: 0000 unimp - 5bb4: 0008c30b 0x8c30b - 5bb8: 0300 addi s0,sp,384 - 5bba: 135a slli t1,t1,0x36 - 5bbc: 0120 addi s0,sp,136 - 5bbe: 0000 unimp - 5bc0: 2004 fld fs1,0(s0) - 5bc2: 0400 addi s0,sp,512 - 5bc4: 000bf50b 0xbf50b - 5bc8: 0300 addi s0,sp,384 - 5bca: 0120135b 0x120135b - 5bce: 0000 unimp - 5bd0: 2004 fld fs1,0(s0) - 5bd2: 0800 addi s0,sp,16 - 5bd4: 000bfb0b 0xbfb0b - 5bd8: 0300 addi s0,sp,384 - 5bda: 135c addi a5,sp,420 - 5bdc: 0120 addi s0,sp,136 - 5bde: 0000 unimp - 5be0: 1004 addi s1,sp,32 - 5be2: 0c10 addi a2,sp,528 - 5be4: 650c flw fa1,8(a0) - 5be6: 7078 flw fa4,100(s0) - 5be8: 0300 addi s0,sp,384 - 5bea: 0e5d addi t3,t3,23 - 5bec: 006d c.nop 27 - 5bee: 0000 unimp - 5bf0: 0f04 addi s1,sp,912 - 5bf2: 0c01 addi s8,s8,0 - 5bf4: 00027a0b 0x27a0b - 5bf8: 0300 addi s0,sp,384 - 5bfa: 0e5e slli t3,t3,0x17 - 5bfc: 006d c.nop 27 - 5bfe: 0000 unimp - 5c00: 0104 addi s1,sp,128 - 5c02: 0c00 addi s0,sp,528 - 5c04: 0300 addi s0,sp,384 - 5c06: 0704 addi s1,sp,896 - 5c08: 0369 addi t1,t1,26 - 5c0a: 0000 unimp - 5c0c: 2f0d jal 633e <_start-0x7fff9cc2> - 5c0e: 000c 0xc - 5c10: 1000 addi s0,sp,32 - 5c12: 4d074c03 lbu s8,1232(a4) - 5c16: 0001 nop - 5c18: 0e00 addi s0,sp,784 - 5c1a: 6c66 flw fs8,88(sp) - 5c1c: 0074 addi a3,sp,12 - 5c1e: a30a4e03 lbu t3,-1488(s4) - 5c22: 0000 unimp - 5c24: 0f00 addi s0,sp,912 - 5c26: 0a48 addi a0,sp,276 - 5c28: 0000 unimp - 5c2a: b6056003 0xb6056003 - 5c2e: 0000 unimp - 5c30: 0000 unimp - 5c32: 1910 addi a2,sp,176 - 5c34: 0011 c.nop 4 - 5c36: 0100 addi s0,sp,128 - 5c38: 00330123 sb gp,2(t1) - 5c3c: 0000 unimp - 5c3e: 3ce4 fld fs1,248(s1) - 5c40: 8001 c.srli64 s0 - 5c42: 0150 addi a2,sp,132 - 5c44: 0000 unimp - 5c46: 9c01 0x9c01 - 5c48: 02b1 addi t0,t0,12 - 5c4a: 0000 unimp - 5c4c: 6111 addi sp,sp,256 - 5c4e: 0100 addi s0,sp,128 - 5c50: 00a31323 sh a0,6(t1) - 5c54: 0000 unimp - 5c56: 4f12 lw t5,4(sp) - 5c58: 0009 c.nop 2 - 5c5a: 0100 addi s0,sp,128 - 5c5c: 0325 addi t1,t1,9 - 5c5e: 0025 c.nop 9 - 5c60: 0000 unimp - 5c62: 1200 addi s0,sp,288 - 5c64: 0a4d addi s4,s4,19 - 5c66: 0000 unimp - 5c68: 2501 jal 6268 <_start-0x7fff9d98> - 5c6a: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 5c6e: 0000 unimp - 5c70: 635f4113 xori sp,t5,1589 - 5c74: 0100 addi s0,sp,128 - 5c76: 0326 slli t1,t1,0x9 - 5c78: 02b1 addi t0,t0,12 - 5c7a: 0000 unimp - 5c7c: 4114 lw a3,0(a0) - 5c7e: 735f 0100 0326 0x3260100735f - 5c84: 02b1 addi t0,t0,12 - 5c86: 0000 unimp - 5c88: 8006 c.mv zero,ra - 5c8a: 0800 addi s0,sp,16 - 5c8c: 1aff 0x1aff - 5c8e: 159f 5f41 0065 0x655f41159f - 5c94: 2601 jal 5f94 <_start-0x7fffa06c> - 5c96: 0002b103 0x2b103 - 5c9a: d900 sw s0,48(a0) - 5c9c: 00ea slli ra,ra,0x1a - 5c9e: 1400 addi s0,sp,544 - 5ca0: 5f41 li t5,-16 - 5ca2: 0066 c.slli zero,0x19 - 5ca4: 2601 jal 5fa4 <_start-0x7fffa05c> - 5ca6: 0002b803 0x2b803 - 5caa: 0200 addi s0,sp,256 - 5cac: 7091 lui ra,0xfffe4 - 5cae: 7215 lui tp,0xfffe5 - 5cb0: 0100 addi s0,sp,128 - 5cb2: 00600b27 0x600b27 - 5cb6: 0000 unimp - 5cb8: eb6e fsw fs11,148(sp) - 5cba: 0000 unimp - 5cbc: 0816 slli a6,a6,0x5 - 5cbe: 0011 c.nop 4 - 5cc0: f000 fsw fs0,32(s0) - 5cc2: 0001 nop - 5cc4: 1700 addi s0,sp,928 - 5cc6: 00000bb3 add s7,zero,zero - 5cca: 2a01 jal 5dda <_start-0x7fffa226> - 5ccc: 00012703 lw a4,0(sp) - 5cd0: 0200 addi s0,sp,256 - 5cd2: 6091 lui ra,0x4 - 5cd4: 1800 addi s0,sp,48 - 5cd6: 0240 addi s0,sp,260 - 5cd8: 0000 unimp - 5cda: d719 beqz a4,5be8 <_start-0x7fffa418> - 5cdc: 0010 0x10 - 5cde: 0100 addi s0,sp,128 - 5ce0: 0025032b 0x25032b - 5ce4: 0000 unimp - 5ce6: 191a slli s2,s2,0x26 - 5ce8: 00000ad7 vadd.vv v21,v0,v0,v0.t - 5cec: 2b01 jal 61fc <_start-0x7fff9e04> - 5cee: 0002b103 0x2b103 - 5cf2: 1900 addi s0,sp,176 - 5cf4: 0a6d addi s4,s4,27 - 5cf6: 0000 unimp - 5cf8: 2b01 jal 6208 <_start-0x7fff9df8> - 5cfa: 0002b103 0x2b103 - 5cfe: 1900 addi s0,sp,176 - 5d00: 0a94 addi a3,sp,336 - 5d02: 0000 unimp - 5d04: 2b01 jal 6214 <_start-0x7fff9dec> - 5d06: 0002b103 0x2b103 - 5d0a: 1900 addi s0,sp,176 - 5d0c: 0a82 c.slli64 s5 - 5d0e: 0000 unimp - 5d10: 2b01 jal 6220 <_start-0x7fff9de0> - 5d12: 0002b103 0x2b103 - 5d16: 1900 addi s0,sp,176 - 5d18: 0aa9 addi s5,s5,10 - 5d1a: 0000 unimp - 5d1c: 2b01 jal 622c <_start-0x7fff9dd4> - 5d1e: 00012003 lw zero,0(sp) - 5d22: 0000 unimp - 5d24: 1b00 addi s0,sp,432 - 5d26: 3d50 fld fa2,184(a0) - 5d28: 8001 c.srli64 s0 - 5d2a: 00e4 addi s1,sp,76 - 5d2c: 0000 unimp - 5d2e: d71c sw a5,40(a4) - 5d30: 0010 0x10 - 5d32: 0100 addi s0,sp,128 - 5d34: 0025032b 0x25032b - 5d38: 0000 unimp - 5d3a: 0000eb9b 0xeb9b - 5d3e: 281d jal 5d74 <_start-0x7fffa28c> - 5d40: 0011 c.nop 4 - 5d42: 1c00 addi s0,sp,560 - 5d44: 00000ad7 vadd.vv v21,v0,v0,v0.t - 5d48: 2b01 jal 6258 <_start-0x7fff9da8> - 5d4a: 0002b103 0x2b103 - 5d4e: bb00 fsd fs0,48(a4) - 5d50: 1c0000eb 0x1c0000eb - 5d54: 0a6d addi s4,s4,27 - 5d56: 0000 unimp - 5d58: 2b01 jal 6268 <_start-0x7fff9d98> - 5d5a: 0002b103 0x2b103 - 5d5e: 5a00 lw s0,48(a2) - 5d60: 00ec addi a1,sp,76 - 5d62: 1c00 addi s0,sp,560 - 5d64: 0a94 addi a3,sp,336 - 5d66: 0000 unimp - 5d68: 2b01 jal 6278 <_start-0x7fff9d88> - 5d6a: 0002b103 0x2b103 - 5d6e: de00 sw s0,56(a2) - 5d70: 00ec addi a1,sp,76 - 5d72: 1c00 addi s0,sp,560 - 5d74: 0a82 c.slli64 s5 - 5d76: 0000 unimp - 5d78: 2b01 jal 6288 <_start-0x7fff9d78> - 5d7a: 0002b103 0x2b103 - 5d7e: 5700 lw s0,40(a4) - 5d80: 00ed addi ra,ra,27 - 5d82: 1c00 addi s0,sp,560 - 5d84: 0aa9 addi s5,s5,10 - 5d86: 0000 unimp - 5d88: 2b01 jal 6298 <_start-0x7fff9d68> - 5d8a: 00012003 lw zero,0(sp) - 5d8e: bb00 fsd fs0,48(a4) - 5d90: 00ed addi ra,ra,27 - 5d92: 0000 unimp - 5d94: 0000 unimp - 5d96: 22050403 lb s0,544(a0) - 5d9a: 0002 c.slli64 zero - 5d9c: 1e00 addi s0,sp,816 - 5d9e: 0120 addi s0,sp,136 - 5da0: 0000 unimp - 5da2: 00006d07 vlwu.v v26,(zero),v0.t - 5da6: 0300 addi s0,sp,384 - 5da8: 0000 unimp - 5daa: 03c2 slli t2,t2,0x10 - 5dac: 0000 unimp - 5dae: 0004 0x4 - 5db0: 12aa slli t0,t0,0x2a - 5db2: 0000 unimp - 5db4: 0104 addi s1,sp,128 - 5db6: 07f2 slli a5,a5,0x1c - 5db8: 0000 unimp - 5dba: 230c fld fa1,0(a4) - 5dbc: 0011 c.nop 4 - 5dbe: fc00 fsw fs0,56(s0) - 5dc0: 0002 c.slli64 zero - 5dc2: 3400 fld fs0,40(s0) - 5dc4: 013e slli sp,sp,0xf - 5dc6: 8880 0x8880 - 5dc8: 0001 nop - 5dca: ca00 sw s0,16(a2) - 5dcc: 0078 addi a4,sp,12 - 5dce: 0200 addi s0,sp,256 - 5dd0: 0504 addi s1,sp,640 - 5dd2: 6e69 lui t3,0x1a - 5dd4: 0074 addi a3,sp,12 - 5dd6: 69060103 lb sp,1680(a2) # fffe6690 <__BSS_END__+0x7ffcf918> - 5dda: 0006 c.slli zero,0x1 - 5ddc: 0400 addi s0,sp,512 - 5dde: 0216 slli tp,tp,0x5 - 5de0: 0000 unimp - 5de2: 4802 lw a6,0(sp) - 5de4: 0d01 addi s10,s10,0 - 5de6: 0025 c.nop 9 - 5de8: 0000 unimp - 5dea: 1d050803 lb a6,464(a0) - 5dee: 0002 c.slli64 zero - 5df0: 0400 addi s0,sp,512 - 5df2: 00000773 0x773 - 5df6: 4a02 lw s4,0(sp) - 5df8: 1601 addi a2,a2,-32 - 5dfa: 0059 c.nop 22 - 5dfc: 0000 unimp - 5dfe: 4705 li a4,1 - 5e00: 0000 unimp - 5e02: 0300 addi s0,sp,384 - 5e04: 0801 addi a6,a6,0 - 5e06: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 5e0a: 1504 addi s1,sp,672 - 5e0c: 0002 c.slli64 zero - 5e0e: 0200 addi s0,sp,256 - 5e10: 6d16014b 0x6d16014b - 5e14: 0000 unimp - 5e16: 0300 addi s0,sp,384 - 5e18: 0704 addi s1,sp,896 - 5e1a: 036e slli t1,t1,0x1b - 5e1c: 0000 unimp - 5e1e: 64070803 lb a6,1600(a4) - 5e22: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 5e26: 0702 c.slli64 a4 - 5e28: 0384 addi s1,sp,448 - 5e2a: 0000 unimp - 5e2c: 5406 lw s0,96(sp) - 5e2e: 0000 unimp - 5e30: 9200 0x9200 - 5e32: 0000 unimp - 5e34: 0700 addi s0,sp,896 - 5e36: 006d c.nop 27 - 5e38: 0000 unimp - 5e3a: 00ff 0xff - 5e3c: 8205 srli a2,a2,0x1 - 5e3e: 0000 unimp - 5e40: 0800 addi s0,sp,16 - 5e42: 00000397 auipc t2,0x0 - 5e46: 3c04 fld fs1,56(s0) - 5e48: 9216 add tp,tp,t0 - 5e4a: 0000 unimp - 5e4c: 0900 addi s0,sp,144 - 5e4e: 0c01 addi s8,s8,0 - 5e50: 0000 unimp - 5e52: af0f4803 lbu a6,-1296(t5) - 5e56: 0000 unimp - 5e58: 0300 addi s0,sp,384 - 5e5a: 0410 addi a2,sp,512 - 5e5c: 009d addi ra,ra,7 - 5e5e: 0000 unimp - 5e60: 100a c.slli zero,0x22 - 5e62: 20034f03 lbu t5,512(t1) - 5e66: 0001 nop - 5e68: 0b00 addi s0,sp,400 - 5e6a: 08bd addi a7,a7,15 - 5e6c: 0000 unimp - 5e6e: 20135903 lhu s2,513(t1) - 5e72: 0001 nop - 5e74: 0400 addi s0,sp,512 - 5e76: 0020 addi s0,sp,8 - 5e78: 0b00 addi s0,sp,400 - 5e7a: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne - 5e7e: 20135a03 lhu s4,513(t1) - 5e82: 0001 nop - 5e84: 0400 addi s0,sp,512 - 5e86: 0020 addi s0,sp,8 - 5e88: 0b04 addi s1,sp,400 - 5e8a: 0bf5 addi s7,s7,29 - 5e8c: 0000 unimp - 5e8e: 20135b03 lhu s6,513(t1) - 5e92: 0001 nop - 5e94: 0400 addi s0,sp,512 - 5e96: 0020 addi s0,sp,8 - 5e98: 0b08 addi a0,sp,400 - 5e9a: 00000bfb 0xbfb - 5e9e: 20135c03 lhu s8,513(t1) - 5ea2: 0001 nop - 5ea4: 0400 addi s0,sp,512 - 5ea6: 1010 addi a2,sp,32 - 5ea8: 0c0c addi a1,sp,528 - 5eaa: 7865 lui a6,0xffff9 - 5eac: 0070 addi a2,sp,12 - 5eae: 6d0e5d03 lhu s10,1744(t3) # 1a6d0 <_start-0x7ffe5930> - 5eb2: 0000 unimp - 5eb4: 0400 addi s0,sp,512 - 5eb6: 0b0c010f 0xb0c010f - 5eba: 027a slli tp,tp,0x1e - 5ebc: 0000 unimp - 5ebe: 6d0e5e03 lhu t3,1744(t3) - 5ec2: 0000 unimp - 5ec4: 0400 addi s0,sp,512 - 5ec6: 0001 nop - 5ec8: 000c 0xc - 5eca: 69070403 lb s0,1680(a4) - 5ece: 0d000003 lb zero,208(zero) # d0 <_start-0x7fffff30> - 5ed2: 00000c2f 0xc2f - 5ed6: 0310 addi a2,sp,384 - 5ed8: 074c addi a1,sp,900 - 5eda: 014d addi sp,sp,19 - 5edc: 0000 unimp - 5ede: 660e flw fa2,192(sp) - 5ee0: 746c flw fa1,108(s0) - 5ee2: 0300 addi s0,sp,384 - 5ee4: 0a4e slli s4,s4,0x13 - 5ee6: 000000a3 sb zero,1(zero) # 1 <_start-0x7fffffff> - 5eea: 000a480f 0xa480f - 5eee: 0300 addi s0,sp,384 - 5ef0: 0560 addi s0,sp,652 - 5ef2: 00b6 slli ra,ra,0xd - 5ef4: 0000 unimp - 5ef6: 1000 addi s0,sp,32 - 5ef8: 1161 addi sp,sp,-8 - 5efa: 0000 unimp - 5efc: 2401 jal 60fc <_start-0x7fff9f04> - 5efe: a301 j 63fe <_start-0x7fff9c02> - 5f00: 0000 unimp - 5f02: 3400 fld fs0,40(s0) - 5f04: 013e slli sp,sp,0xf - 5f06: 8880 0x8880 - 5f08: 0001 nop - 5f0a: 0100 addi s0,sp,128 - 5f0c: b29c fsd fa5,32(a3) - 5f0e: 11000003 lb zero,272(zero) # 110 <_start-0x7ffffef0> - 5f12: 0069 c.nop 26 - 5f14: 2401 jal 6114 <_start-0x7fff9eec> - 5f16: 3315 jal 5c3a <_start-0x7fffa3c6> - 5f18: 0000 unimp - 5f1a: db00 sw s0,48(a4) - 5f1c: 00ed addi ra,ra,27 - 5f1e: 1200 addi s0,sp,288 - 5f20: 5f41 li t5,-16 - 5f22: 26010063 beqz sp,6182 <_start-0x7fff9e7e> - 5f26: 0003b203 0x3b203 - 5f2a: 1300 addi s0,sp,416 - 5f2c: 5f41 li t5,-16 - 5f2e: 26010073 0x26010073 - 5f32: 0003b203 0x3b203 - 5f36: 0700 addi s0,sp,896 - 5f38: 00ee slli ra,ra,0x1b - 5f3a: 1300 addi s0,sp,416 - 5f3c: 5f41 li t5,-16 - 5f3e: 0065 c.nop 25 - 5f40: 2601 jal 6240 <_start-0x7fff9dc0> - 5f42: 0003b203 0x3b203 - 5f46: 2600 fld fs0,8(a2) - 5f48: 00ee slli ra,ra,0x1b - 5f4a: 1400 addi s0,sp,544 - 5f4c: 5f41 li t5,-16 - 5f4e: 0066 c.slli zero,0x19 - 5f50: 2601 jal 6250 <_start-0x7fff9db0> - 5f52: 0003b903 0x3b903 - 5f56: 0200 addi s0,sp,256 - 5f58: 6091 lui ra,0x4 - 5f5a: 01006113 ori sp,zero,16 - 5f5e: 00a30a27 0xa30a27 - 5f62: 0000 unimp - 5f64: ee45 bnez a2,601c <_start-0x7fff9fe4> - 5f66: 0000 unimp - 5f68: 4815 li a6,5 - 5f6a: 0011 c.nop 4 - 5f6c: 9c00 0x9c00 - 5f6e: 16000003 lb zero,352(zero) # 160 <_start-0x7ffffea0> - 5f72: 1154 addi a3,sp,164 - 5f74: 0000 unimp - 5f76: 2901 jal 6386 <_start-0x7fff9c7a> - 5f78: 3e501703 lh a4,997(zero) # 3e5 <_start-0x7ffffc1b> - 5f7c: 8001 c.srli64 s0 - 5f7e: 00e4 addi s1,sp,76 - 5f80: 0000 unimp - 5f82: 6d18 flw fa4,24(a0) - 5f84: 0011 c.nop 4 - 5f86: 0100 addi s0,sp,128 - 5f88: 0329 addi t1,t1,10 - 5f8a: 0060 addi s0,sp,12 - 5f8c: 0000 unimp - 5f8e: ee7d bnez a2,608c <_start-0x7fff9f74> - 5f90: 0000 unimp - 5f92: 6815 lui a6,0x5 - 5f94: 0011 c.nop 4 - 5f96: 0200 addi s0,sp,256 - 5f98: 0002 c.slli64 zero - 5f9a: 1800 addi s0,sp,48 - 5f9c: 117d addi sp,sp,-1 - 5f9e: 0000 unimp - 5fa0: 2901 jal 63b0 <_start-0x7fff9c50> - 5fa2: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 5fa6: e600 fsw fs0,8(a2) - 5fa8: 00ee slli ra,ra,0x1b - 5faa: 0000 unimp - 5fac: 8819 andi s0,s0,6 - 5fae: 013e slli sp,sp,0xf - 5fb0: ac80 fsd fs0,24(s1) - 5fb2: 0000 unimp - 5fb4: 5000 lw s0,32(s0) - 5fb6: 0002 c.slli64 zero - 5fb8: 1800 addi s0,sp,48 - 5fba: 0f3c addi a5,sp,920 - 5fbc: 0000 unimp - 5fbe: 2901 jal 63ce <_start-0x7fff9c32> - 5fc0: 0003b203 0x3b203 - 5fc4: 0700 addi s0,sp,896 - 5fc6: 180000ef jal ra,6146 <_start-0x7fff9eba> - 5fca: 00000d77 0xd77 - 5fce: 2901 jal 63de <_start-0x7fff9c22> - 5fd0: 0003b203 0x3b203 - 5fd4: 2900 fld fs0,16(a0) - 5fd6: 180000ef jal ra,6156 <_start-0x7fff9eaa> - 5fda: 00000d63 beqz zero,5ff4 <_start-0x7fffa00c> - 5fde: 2901 jal 63ee <_start-0x7fff9c12> - 5fe0: 0003b203 0x3b203 - 5fe4: 6e00 flw fs0,24(a2) - 5fe6: 180000ef jal ra,6166 <_start-0x7fff9e9a> - 5fea: 0dc9 addi s11,s11,18 - 5fec: 0000 unimp - 5fee: 2901 jal 63fe <_start-0x7fff9c02> - 5ff0: 0003b203 0x3b203 - 5ff4: 8500 0x8500 - 5ff6: 000000ef jal ra,5ff6 <_start-0x7fffa00a> - 5ffa: 861a mv a2,t1 - 5ffc: 0002 c.slli64 zero - 5ffe: 1b00 addi s0,sp,432 - 6000: 0f3c addi a5,sp,920 - 6002: 0000 unimp - 6004: 2901 jal 6414 <_start-0x7fff9bec> - 6006: 0003b203 0x3b203 - 600a: 1b00 addi s0,sp,432 - 600c: 00000d77 0xd77 - 6010: 2901 jal 6420 <_start-0x7fff9be0> - 6012: 0003b203 0x3b203 - 6016: 1b00 addi s0,sp,432 - 6018: 00000d63 beqz zero,6032 <_start-0x7fff9fce> - 601c: 2901 jal 642c <_start-0x7fff9bd4> - 601e: 0003b203 0x3b203 - 6022: 1b00 addi s0,sp,432 - 6024: 0dc9 addi s11,s11,18 - 6026: 0000 unimp - 6028: 2901 jal 6438 <_start-0x7fff9bc8> - 602a: 0003b203 0x3b203 - 602e: 0000 unimp - 6030: 1b1c addi a5,sp,432 - 6032: 1039 c.nop -18 - 6034: 0000 unimp - 6036: 2901 jal 6446 <_start-0x7fff9bba> - 6038: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 603c: 1a00 addi s0,sp,304 - 603e: 0331 addi t1,t1,12 - 6040: 0000 unimp - 6042: 000f8e1b 0xf8e1b - 6046: 0100 addi s0,sp,128 - 6048: 0329 addi t1,t1,10 - 604a: 03b2 slli t2,t2,0xc - 604c: 0000 unimp - 604e: 000fd61b 0xfd61b - 6052: 0100 addi s0,sp,128 - 6054: 0329 addi t1,t1,10 - 6056: 03b2 slli t2,t2,0xc - 6058: 0000 unimp - 605a: 0010241b 0x10241b - 605e: 0100 addi s0,sp,128 - 6060: 0329 addi t1,t1,10 - 6062: 03b2 slli t2,t2,0xc - 6064: 0000 unimp - 6066: 0010521b 0x10521b - 606a: 0100 addi s0,sp,128 - 606c: 0329 addi t1,t1,10 - 606e: 03b9 addi t2,t2,14 - 6070: 0000 unimp - 6072: fe1a fsw ft6,60(sp) - 6074: 0002 c.slli64 zero - 6076: 1b00 addi s0,sp,432 - 6078: 0f3c addi a5,sp,920 - 607a: 0000 unimp - 607c: 2901 jal 648c <_start-0x7fff9b74> - 607e: 0003b203 0x3b203 - 6082: 1b00 addi s0,sp,432 - 6084: 00000d77 0xd77 - 6088: 2901 jal 6498 <_start-0x7fff9b68> - 608a: 0003b203 0x3b203 - 608e: 1b00 addi s0,sp,432 - 6090: 00000d63 beqz zero,60aa <_start-0x7fff9f56> - 6094: 2901 jal 64a4 <_start-0x7fff9b5c> - 6096: 0003b203 0x3b203 - 609a: 1b00 addi s0,sp,432 - 609c: 0dc9 addi s11,s11,18 - 609e: 0000 unimp - 60a0: 2901 jal 64b0 <_start-0x7fff9b50> - 60a2: 0003b203 0x3b203 - 60a6: 0000 unimp - 60a8: 101a c.slli zero,0x26 - 60aa: 1b000003 lb zero,432(zero) # 1b0 <_start-0x7ffffe50> - 60ae: 0f29 addi t5,t5,10 - 60b0: 0000 unimp - 60b2: 2901 jal 64c2 <_start-0x7fff9b3e> - 60b4: 00012003 lw zero,0(sp) - 60b8: 0000 unimp - 60ba: 221a fld ft4,384(sp) - 60bc: 1b000003 lb zero,432(zero) # 1b0 <_start-0x7ffffe50> - 60c0: 0f29 addi t5,t5,10 - 60c2: 0000 unimp - 60c4: 2901 jal 64d4 <_start-0x7fff9b2c> - 60c6: 00012003 lw zero,0(sp) - 60ca: 0000 unimp - 60cc: 1b1c addi a5,sp,432 - 60ce: 0f29 addi t5,t5,10 - 60d0: 0000 unimp - 60d2: 2901 jal 64e2 <_start-0x7fff9b1e> - 60d4: 00012003 lw zero,0(sp) - 60d8: 0000 unimp - 60da: 1a00 addi s0,sp,304 - 60dc: 00000343 fmadd.s ft6,ft0,ft0,ft0,rne - 60e0: 000f291b 0xf291b - 60e4: 0100 addi s0,sp,128 - 60e6: 0329 addi t1,t1,10 - 60e8: 0120 addi s0,sp,136 - 60ea: 0000 unimp - 60ec: 1a00 addi s0,sp,304 - 60ee: 0355 addi t1,t1,21 - 60f0: 0000 unimp - 60f2: 000f291b 0xf291b - 60f6: 0100 addi s0,sp,128 - 60f8: 0329 addi t1,t1,10 - 60fa: 0120 addi s0,sp,136 - 60fc: 0000 unimp - 60fe: 1a00 addi s0,sp,304 - 6100: 00000367 jalr t1,zero # 0 <_start-0x80000000> - 6104: 000f291b 0xf291b - 6108: 0100 addi s0,sp,128 - 610a: 0329 addi t1,t1,10 - 610c: 0120 addi s0,sp,136 - 610e: 0000 unimp - 6110: 1c00 addi s0,sp,560 - 6112: 000e4e1b 0xe4e1b - 6116: 0100 addi s0,sp,128 - 6118: 0329 addi t1,t1,10 - 611a: 03b2 slli t2,t2,0xc - 611c: 0000 unimp - 611e: 000dee1b 0xdee1b - 6122: 0100 addi s0,sp,128 - 6124: 0329 addi t1,t1,10 - 6126: 03b2 slli t2,t2,0xc - 6128: 0000 unimp - 612a: 000e021b 0xe021b - 612e: 0100 addi s0,sp,128 - 6130: 0329 addi t1,t1,10 - 6132: 03b2 slli t2,t2,0xc - 6134: 0000 unimp - 6136: 000da71b 0xda71b - 613a: 0100 addi s0,sp,128 - 613c: 0329 addi t1,t1,10 - 613e: 03b2 slli t2,t2,0xc - 6140: 0000 unimp - 6142: 0000 unimp - 6144: 0000 unimp - 6146: 801d srli s0,s0,0x7 - 6148: 0011 c.nop 4 - 614a: 1e00 addi s0,sp,816 - 614c: 0d3e slli s10,s10,0xf - 614e: 0000 unimp - 6150: 2a01 jal 6260 <_start-0x7fff9da0> - 6152: 00012703 lw a4,0(sp) - 6156: 0200 addi s0,sp,256 - 6158: 5091 li ra,-28 - 615a: 0000 unimp - 615c: 22050403 lb s0,544(a0) - 6160: 0002 c.slli64 zero - 6162: 1f00 addi s0,sp,944 - 6164: 0120 addi s0,sp,136 - 6166: 0000 unimp - 6168: 00006d07 vlwu.v v26,(zero),v0.t - 616c: 0300 addi s0,sp,384 - 616e: 0000 unimp - 6170: 000003eb 0x3eb - 6174: 0004 0x4 - 6176: 145f 0000 0104 0x1040000145f - 617c: 07f2 slli a5,a5,0x1c - 617e: 0000 unimp - 6180: 9a0c 0x9a0c - 6182: 0011 c.nop 4 - 6184: fc00 fsw fs0,56(s0) - 6186: 0002 c.slli64 zero - 6188: bc00 fsd fs0,56(s0) - 618a: 0c80013f 9a000002 0x9a0000020c80013f - 6192: 0200007b 0x200007b - 6196: 0408 addi a0,sp,512 - 6198: 00a2 slli ra,ra,0x8 - 619a: 0000 unimp - 619c: 69050403 lb s0,1680(a0) - 61a0: 746e flw fs0,248(sp) - 61a2: 0200 addi s0,sp,256 - 61a4: 0601 addi a2,a2,0 - 61a6: 0669 addi a2,a2,26 - 61a8: 0000 unimp - 61aa: 0802 c.slli64 a6 - 61ac: 1d05 addi s10,s10,-31 - 61ae: 0002 c.slli64 zero - 61b0: 0400 addi s0,sp,512 - 61b2: 00000773 0x773 - 61b6: 4a02 lw s4,0(sp) - 61b8: 1601 addi a2,a2,-32 - 61ba: 00000053 fadd.s ft0,ft0,ft0,rne - 61be: 4105 li sp,1 - 61c0: 0000 unimp - 61c2: 0200 addi s0,sp,256 - 61c4: 0801 addi a6,a6,0 - 61c6: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 61ca: 0402 c.slli64 s0 - 61cc: 00036e07 vlwu.v v28,(t1),v0.t - 61d0: 0200 addi s0,sp,256 - 61d2: 0708 addi a0,sp,896 - 61d4: 0364 addi s1,sp,396 - 61d6: 0000 unimp - 61d8: 0202 c.slli64 tp - 61da: 00038407 vlbu.v v8,(t2),v0.t - 61de: 0600 addi s0,sp,768 - 61e0: 004e c.slli zero,0x13 - 61e2: 0000 unimp - 61e4: 007f 0x7f - 61e6: 0000 unimp - 61e8: 00005a07 vlhu.v v20,(zero),v0.t - 61ec: ff00 fsw fs0,56(a4) - 61ee: 0500 addi s0,sp,640 - 61f0: 0000006f j 61f0 <_start-0x7fff9e10> - 61f4: 9708 0x9708 - 61f6: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - 61fa: 163c addi a5,sp,808 - 61fc: 007f 0x7f - 61fe: 0000 unimp - 6200: dc09 beqz s0,611a <_start-0x7fff9ee6> - 6202: 0008 0x8 - 6204: 0300 addi s0,sp,384 - 6206: 0f48 addi a0,sp,916 - 6208: 0025 c.nop 9 - 620a: 0000 unimp - 620c: 080a slli a6,a6,0x2 - 620e: e6034f03 lbu t5,-416(t1) - 6212: 0000 unimp - 6214: 0b00 addi s0,sp,400 - 6216: 08bd addi a7,a7,15 - 6218: 0000 unimp - 621a: 5a0e5703 lhu a4,1440(t3) - 621e: 0000 unimp - 6220: 0400 addi s0,sp,512 - 6222: 0020 addi s0,sp,8 - 6224: 0b00 addi s0,sp,400 - 6226: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne - 622a: 5a0e5803 lhu a6,1440(t3) - 622e: 0000 unimp - 6230: 0400 addi s0,sp,512 - 6232: 0c14 addi a3,sp,528 - 6234: 0c04 addi s1,sp,528 - 6236: 7865 lui a6,0xffff9 - 6238: 0070 addi a2,sp,12 - 623a: 5a0e5903 lhu s2,1440(t3) - 623e: 0000 unimp - 6240: 0400 addi s0,sp,512 - 6242: 0b04010b 0xb04010b - 6246: 027a slli tp,tp,0x1e - 6248: 0000 unimp - 624a: 5a0e5a03 lhu s4,1440(t3) - 624e: 0000 unimp - 6250: 0400 addi s0,sp,512 - 6252: 0001 nop - 6254: 0004 0x4 - 6256: 250d jal 6878 <_start-0x7fff9788> - 6258: 000a c.slli zero,0x2 - 625a: 0800 addi s0,sp,16 - 625c: 0c074c03 lbu s8,192(a4) - 6260: 0001 nop - 6262: 0e00 addi s0,sp,784 - 6264: 6c66 flw fs8,88(sp) - 6266: 0074 addi a3,sp,12 - 6268: 900a4e03 lbu t3,-1792(s4) - 626c: 0000 unimp - 626e: 0f00 addi s0,sp,912 - 6270: 0a48 addi a0,sp,276 - 6272: 0000 unimp - 6274: 9c055c03 lhu s8,-1600(a0) - 6278: 0000 unimp - 627a: 0000 unimp - 627c: 0109 addi sp,sp,2 - 627e: 000c 0xc - 6280: 0400 addi s0,sp,512 - 6282: 0f48 addi a0,sp,916 - 6284: 0118 addi a4,sp,128 - 6286: 0000 unimp - 6288: 1002 c.slli zero,0x20 - 628a: 9d04 0x9d04 - 628c: 0000 unimp - 628e: 0a00 addi s0,sp,272 - 6290: 0410 addi a2,sp,512 - 6292: 0189034f fnmadd.s ft6,fs2,fs8,ft0,rne - 6296: 0000 unimp - 6298: 0008bd0b 0x8bd0b - 629c: 0400 addi s0,sp,512 - 629e: 1359 addi t1,t1,-10 - 62a0: 0189 addi gp,gp,2 - 62a2: 0000 unimp - 62a4: 2004 fld fs1,0(s0) - 62a6: 0000 unimp - 62a8: 0008c30b 0x8c30b - 62ac: 0400 addi s0,sp,512 - 62ae: 135a slli t1,t1,0x36 - 62b0: 0189 addi gp,gp,2 - 62b2: 0000 unimp - 62b4: 2004 fld fs1,0(s0) - 62b6: 0400 addi s0,sp,512 - 62b8: 000bf50b 0xbf50b - 62bc: 0400 addi s0,sp,512 - 62be: 0189135b 0x189135b - 62c2: 0000 unimp - 62c4: 2004 fld fs1,0(s0) - 62c6: 0800 addi s0,sp,16 - 62c8: 000bfb0b 0xbfb0b - 62cc: 0400 addi s0,sp,512 - 62ce: 135c addi a5,sp,420 - 62d0: 0189 addi gp,gp,2 - 62d2: 0000 unimp - 62d4: 1004 addi s1,sp,32 - 62d6: 0c10 addi a2,sp,528 - 62d8: 650c flw fa1,8(a0) - 62da: 7078 flw fa4,100(s0) - 62dc: 0400 addi s0,sp,512 - 62de: 0e5d addi t3,t3,23 - 62e0: 005a c.slli zero,0x16 - 62e2: 0000 unimp - 62e4: 0f04 addi s1,sp,912 - 62e6: 0c01 addi s8,s8,0 - 62e8: 00027a0b 0x27a0b - 62ec: 0400 addi s0,sp,512 - 62ee: 0e5e slli t3,t3,0x17 - 62f0: 005a c.slli zero,0x16 - 62f2: 0000 unimp - 62f4: 0104 addi s1,sp,128 - 62f6: 0c00 addi s0,sp,528 - 62f8: 0200 addi s0,sp,256 - 62fa: 0704 addi s1,sp,896 - 62fc: 0369 addi t1,t1,26 - 62fe: 0000 unimp - 6300: 2f0d jal 6a32 <_start-0x7fff95ce> - 6302: 000c 0xc - 6304: 1000 addi s0,sp,32 - 6306: 4c04 lw s1,24(s0) - 6308: 0001b607 fld fa2,0(gp) # fffe8000 <__BSS_END__+0x7ffd1288> - 630c: 0e00 addi s0,sp,784 - 630e: 6c66 flw fs8,88(sp) - 6310: 0074 addi a3,sp,12 - 6312: 4e04 lw s1,24(a2) - 6314: 0c0a slli s8,s8,0x2 - 6316: 0001 nop - 6318: 0f00 addi s0,sp,912 - 631a: 0a48 addi a0,sp,276 - 631c: 0000 unimp - 631e: 6004 flw fs1,0(s0) - 6320: 1f05 addi t5,t5,-31 - 6322: 0001 nop - 6324: 0000 unimp - 6326: cd10 sw a2,24(a0) - 6328: 0011 c.nop 4 - 632a: 0100 addi s0,sp,128 - 632c: 0125 addi sp,sp,9 - 632e: 010c addi a1,sp,128 - 6330: 0000 unimp - 6332: 3fbc fld fa5,120(a5) - 6334: 8001 c.srli64 s0 - 6336: 020c addi a1,sp,256 - 6338: 0000 unimp - 633a: 9c01 0x9c01 - 633c: 000003db 0x3db - 6340: 6111 addi sp,sp,256 - 6342: 0100 addi s0,sp,128 - 6344: 1725 addi a4,a4,-23 - 6346: 0090 addi a2,sp,64 - 6348: 0000 unimp - 634a: 0000efd3 fadd.s ft11,ft1,ft0,unknown - 634e: 4f12 lw t5,4(sp) - 6350: 0009 c.nop 2 - 6352: 0100 addi s0,sp,128 - 6354: 002c0327 0x2c0327 - 6358: 0000 unimp - 635a: 1200 addi s0,sp,288 - 635c: 0a4d addi s4,s4,19 - 635e: 0000 unimp - 6360: 2701 jal 6a60 <_start-0x7fff95a0> - 6362: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> - 6366: 0000 unimp - 6368: 635f4113 xori sp,t5,1589 - 636c: 0100 addi s0,sp,128 - 636e: 0328 addi a0,sp,392 - 6370: 000003db 0x3db - 6374: 4114 lw a3,0(a0) - 6376: 735f 0100 0328 0x3280100735f - 637c: 000003db 0x3db - 6380: 0000f05b 0xf05b - 6384: 4114 lw a3,0(a0) - 6386: 655f 0100 0328 0x3280100655f - 638c: 000003db 0x3db - 6390: 0000f083 0xf083 - 6394: e815 bnez s0,63c8 <_start-0x7fff9c38> - 6396: 0009 c.nop 2 - 6398: 0100 addi s0,sp,128 - 639a: 0328 addi a0,sp,392 - 639c: 0189 addi gp,gp,2 - 639e: 0000 unimp - 63a0: f0d9 bnez s1,6326 <_start-0x7fff9cda> - 63a2: 0000 unimp - 63a4: 4a15 li s4,5 - 63a6: 0009 c.nop 2 - 63a8: 0100 addi s0,sp,128 - 63aa: 0328 addi a0,sp,392 - 63ac: 0189 addi gp,gp,2 - 63ae: 0000 unimp - 63b0: f125 bnez a0,6310 <_start-0x7fff9cf0> - 63b2: 0000 unimp - 63b4: 635f5213 0x635f5213 - 63b8: 0100 addi s0,sp,128 - 63ba: 0329 addi t1,t1,10 - 63bc: 000003db 0x3db - 63c0: 5214 lw a3,32(a2) - 63c2: 735f 0100 0329 0x3290100735f - 63c8: 000003db 0x3db - 63cc: 0000f05b 0xf05b - 63d0: 5214 lw a3,32(a2) - 63d2: 655f 0100 0329 0x3290100655f - 63d8: 000003db 0x3db - 63dc: 0000f193 andi gp,ra,0 - 63e0: 5216 lw tp,100(sp) - 63e2: 665f 0100 0329 0x3290100665f - 63e8: 03e2 slli t2,t2,0x18 - 63ea: 0000 unimp - 63ec: 9102 jalr sp - 63ee: 1460 addi s0,sp,556 - 63f0: 0072 c.slli zero,0x1c - 63f2: 2a01 jal 6502 <_start-0x7fff9afe> - 63f4: 0c0a slli s8,s8,0x2 - 63f6: 0001 nop - 63f8: bf00 fsd fs0,56(a4) - 63fa: 00f1 addi ra,ra,28 - 63fc: 1700 addi s0,sp,928 - 63fe: 11a0 addi s0,sp,232 - 6400: 0000 unimp - 6402: 000002a3 sb zero,5(zero) # 5 <_start-0x7ffffffb> - 6406: 3518 fld fa4,40(a0) - 6408: 0009 c.nop 2 - 640a: 0100 addi s0,sp,128 - 640c: 032d addi t1,t1,11 - 640e: 00e6 slli ra,ra,0x19 - 6410: 0000 unimp - 6412: 1700 addi s0,sp,928 - 6414: 11c0 addi s0,sp,228 - 6416: 0000 unimp - 6418: 02ed addi t0,t0,27 - 641a: 0000 unimp - 641c: 3c15 jal 5e50 <_start-0x7fffa1b0> - 641e: 0100000f fence w,unknown - 6422: 03db032f 0x3db032f - 6426: 0000 unimp - 6428: f210 fsw fa2,32(a2) - 642a: 0000 unimp - 642c: 7715 lui a4,0xfffe5 - 642e: 000d c.nop 3 - 6430: 0100 addi s0,sp,128 - 6432: 03db032f 0x3db032f - 6436: 0000 unimp - 6438: f224 fsw fs1,96(a2) - 643a: 0000 unimp - 643c: 6315 lui t1,0x5 - 643e: 000d c.nop 3 - 6440: 0100 addi s0,sp,128 - 6442: 03db032f 0x3db032f - 6446: 0000 unimp - 6448: f238 fsw fa4,96(a2) - 644a: 0000 unimp - 644c: c915 beqz a0,6480 <_start-0x7fff9b80> - 644e: 000d c.nop 3 - 6450: 0100 addi s0,sp,128 - 6452: 03db032f 0x3db032f - 6456: 0000 unimp - 6458: f24c fsw fa1,36(a2) - 645a: 0000 unimp - 645c: 1900 addi s0,sp,176 - 645e: 00000323 sb zero,6(zero) # 6 <_start-0x7ffffffa> - 6462: 3c18 fld fa4,56(s0) - 6464: 0100000f fence w,unknown - 6468: 03db032f 0x3db032f - 646c: 0000 unimp - 646e: 7718 flw fa4,40(a4) - 6470: 000d c.nop 3 - 6472: 0100 addi s0,sp,128 - 6474: 03db032f 0x3db032f - 6478: 0000 unimp - 647a: 6318 flw fa4,0(a4) - 647c: 000d c.nop 3 - 647e: 0100 addi s0,sp,128 - 6480: 03db032f 0x3db032f - 6484: 0000 unimp - 6486: c918 sw a4,16(a0) - 6488: 000d c.nop 3 - 648a: 0100 addi s0,sp,128 - 648c: 03db032f 0x3db032f - 6490: 0000 unimp - 6492: 1a00 addi s0,sp,304 - 6494: 40a8 lw a0,64(s1) - 6496: 8001 c.srli64 s0 - 6498: 00e4 addi s1,sp,76 - 649a: 0000 unimp - 649c: 00000387 vlbu.v v7,(zero),v0.t - 64a0: 8d15 sub a0,a0,a3 - 64a2: 0011 c.nop 4 - 64a4: 0100 addi s0,sp,128 - 64a6: 002c032f 0x2c032f - 64aa: 0000 unimp - 64ac: f278 fsw fa4,100(a2) - 64ae: 0000 unimp - 64b0: 0011f81b 0x11f81b - 64b4: 1500 addi s0,sp,672 - 64b6: 0f3c addi a5,sp,920 - 64b8: 0000 unimp - 64ba: 2f01 jal 6bca <_start-0x7fff9436> - 64bc: 0003db03 lhu s6,0(t2) # 5e42 <_start-0x7fffa1be> - 64c0: 9600 0x9600 - 64c2: 00f2 slli ra,ra,0x1c - 64c4: 1500 addi s0,sp,672 - 64c6: 00000d77 0xd77 - 64ca: 2f01 jal 6bda <_start-0x7fff9426> - 64cc: 0003db03 lhu s6,0(t2) - 64d0: dd00 sw s0,56(a0) - 64d2: 00f2 slli ra,ra,0x1c - 64d4: 1500 addi s0,sp,672 - 64d6: 00000d63 beqz zero,64f0 <_start-0x7fff9b10> - 64da: 2f01 jal 6bea <_start-0x7fff9416> - 64dc: 0003db03 lhu s6,0(t2) - 64e0: 4f00 lw s0,24(a4) - 64e2: 150000f3 0x150000f3 - 64e6: 0dc9 addi s11,s11,18 - 64e8: 0000 unimp - 64ea: 2f01 jal 6bfa <_start-0x7fff9406> - 64ec: 0003db03 lhu s6,0(t2) - 64f0: 9400 0x9400 - 64f2: 000000f3 0xf3 - 64f6: 1700 addi s0,sp,928 - 64f8: 1218 addi a4,sp,288 - 64fa: 0000 unimp - 64fc: 03c5 addi t2,t2,17 - 64fe: 0000 unimp - 6500: 3c18 fld fa4,56(s0) - 6502: 0100000f fence w,unknown - 6506: 03db032f 0x3db032f - 650a: 0000 unimp - 650c: 7718 flw fa4,40(a4) - 650e: 000d c.nop 3 - 6510: 0100 addi s0,sp,128 - 6512: 03db032f 0x3db032f - 6516: 0000 unimp - 6518: 6318 flw fa4,0(a4) - 651a: 000d c.nop 3 - 651c: 0100 addi s0,sp,128 - 651e: 03db032f 0x3db032f - 6522: 0000 unimp - 6524: c915 beqz a0,6558 <_start-0x7fff9aa8> - 6526: 000d c.nop 3 - 6528: 0100 addi s0,sp,128 - 652a: 03db032f 0x3db032f - 652e: 0000 unimp - 6530: f3bd bnez a5,6496 <_start-0x7fff9b6a> - 6532: 0000 unimp - 6534: 1b00 addi s0,sp,432 - 6536: 11d8 addi a4,sp,228 - 6538: 0000 unimp - 653a: 3e1c fld fa5,56(a2) - 653c: 000d c.nop 3 - 653e: 0100 addi s0,sp,128 - 6540: 01900333 add t1,zero,s9 - 6544: 0000 unimp - 6546: 9102 jalr sp - 6548: 0050 addi a2,sp,4 - 654a: 0200 addi s0,sp,256 - 654c: 0504 addi s1,sp,640 - 654e: 0222 slli tp,tp,0x8 - 6550: 0000 unimp - 6552: 891d andi a0,a0,7 - 6554: 0001 nop - 6556: 0700 addi s0,sp,896 - 6558: 005a c.slli zero,0x16 - 655a: 0000 unimp - 655c: 37000003 lb zero,880(zero) # 370 <_start-0x7ffffc90> - 6560: 0005 c.nop 1 - 6562: 0400 addi s0,sp,512 - 6564: 0a00 addi s0,sp,272 - 6566: 0016 c.slli zero,0x5 - 6568: 0400 addi s0,sp,512 - 656a: f201 bnez a2,646a <_start-0x7fff9b96> - 656c: 0c000007 vlxbu.v v0,(zero),v0,v0.t - 6570: 000011db 0x11db - 6574: 02fc addi a5,sp,332 - 6576: 0000 unimp - 6578: 41c8 lw a0,4(a1) - 657a: 8001 c.srli64 s0 - 657c: 0334 addi a3,sp,392 - 657e: 0000 unimp - 6580: 7ffc flw fa5,124(a5) - 6582: 0000 unimp - 6584: 0402 c.slli64 s0 - 6586: 6905 lui s2,0x1 - 6588: 746e flw fs0,248(sp) - 658a: 0300 addi s0,sp,384 - 658c: 0601 addi a2,a2,0 - 658e: 0669 addi a2,a2,26 - 6590: 0000 unimp - 6592: 1d050803 lb a6,464(a0) - 6596: 0002 c.slli64 zero - 6598: 0400 addi s0,sp,512 - 659a: 00000773 0x773 - 659e: 4a02 lw s4,0(sp) - 65a0: 1601 addi a2,a2,-32 - 65a2: 004c addi a1,sp,4 - 65a4: 0000 unimp - 65a6: 3a05 jal 5ed6 <_start-0x7fffa12a> - 65a8: 0000 unimp - 65aa: 0300 addi s0,sp,384 - 65ac: 0801 addi a6,a6,0 - 65ae: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 65b2: 6e070403 lb s0,1760(a4) # fffe56e0 <__BSS_END__+0x7ffce968> - 65b6: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 65ba: 0708 addi a0,sp,896 - 65bc: 0364 addi s1,sp,396 - 65be: 0000 unimp - 65c0: 84070203 lb tp,-1984(a4) - 65c4: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 65c8: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne - 65cc: 0078 addi a4,sp,12 - 65ce: 0000 unimp - 65d0: 00005307 vlhu.v v6,(zero),v0.t - 65d4: ff00 fsw fs0,56(a4) - 65d6: 0500 addi s0,sp,640 - 65d8: 0068 addi a0,sp,12 - 65da: 0000 unimp - 65dc: 9708 0x9708 - 65de: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - 65e2: 163c addi a5,sp,808 - 65e4: 0078 addi a4,sp,12 - 65e6: 0000 unimp - 65e8: dc09 beqz s0,6502 <_start-0x7fff9afe> - 65ea: 0008 0x8 - 65ec: 0300 addi s0,sp,384 - 65ee: 0f48 addi a0,sp,916 - 65f0: 0095 addi ra,ra,5 - 65f2: 0000 unimp - 65f4: a2040803 lb a6,-1504(s0) - 65f8: 0000 unimp - 65fa: 0a00 addi s0,sp,272 - 65fc: 0308 addi a0,sp,384 - 65fe: 00e6034f fnmadd.s ft6,fa2,fa4,ft0,rne - 6602: 0000 unimp - 6604: 0008bd0b 0x8bd0b - 6608: 0300 addi s0,sp,384 - 660a: 00530e57 vadd.vv v28,v5,v6,v0.t - 660e: 0000 unimp - 6610: 2004 fld fs1,0(s0) - 6612: 0000 unimp - 6614: 0008c30b 0x8c30b - 6618: 0300 addi s0,sp,384 - 661a: 0e58 addi a4,sp,788 - 661c: 00000053 fadd.s ft0,ft0,ft0,rne - 6620: 1404 addi s1,sp,544 - 6622: 040c addi a1,sp,512 - 6624: 650c flw fa1,8(a0) - 6626: 7078 flw fa4,100(s0) - 6628: 0300 addi s0,sp,384 - 662a: 0e59 addi t3,t3,22 - 662c: 00000053 fadd.s ft0,ft0,ft0,rne - 6630: 0b04 addi s1,sp,400 - 6632: 0401 addi s0,s0,0 - 6634: 00027a0b 0x27a0b - 6638: 0300 addi s0,sp,384 - 663a: 0e5a slli t3,t3,0x16 - 663c: 00000053 fadd.s ft0,ft0,ft0,rne - 6640: 0104 addi s1,sp,128 - 6642: 0400 addi s0,sp,512 - 6644: 0d00 addi s0,sp,656 - 6646: 0a25 addi s4,s4,9 - 6648: 0000 unimp - 664a: 0308 addi a0,sp,384 - 664c: 074c addi a1,sp,900 - 664e: 010c addi a1,sp,128 - 6650: 0000 unimp - 6652: 660e flw fa2,192(sp) - 6654: 746c flw fa1,108(s0) - 6656: 0300 addi s0,sp,384 - 6658: 0a4e slli s4,s4,0x13 - 665a: 0089 addi ra,ra,2 - 665c: 0000 unimp - 665e: 000a480f 0xa480f - 6662: 0300 addi s0,sp,384 - 6664: 055c addi a5,sp,644 - 6666: 009c addi a5,sp,64 - 6668: 0000 unimp - 666a: 0900 addi s0,sp,144 - 666c: 0c01 addi s8,s8,0 - 666e: 0000 unimp - 6670: 4804 lw s1,16(s0) - 6672: 0001180f 0x1180f - 6676: 0300 addi s0,sp,384 - 6678: 0410 addi a2,sp,512 - 667a: 009d addi ra,ra,7 - 667c: 0000 unimp - 667e: 100a c.slli zero,0x22 - 6680: 4f04 lw s1,24(a4) - 6682: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 6686: 0b00 addi s0,sp,400 - 6688: 08bd addi a7,a7,15 - 668a: 0000 unimp - 668c: 5904 lw s1,48(a0) - 668e: 00018913 mv s2,gp - 6692: 0400 addi s0,sp,512 - 6694: 0020 addi s0,sp,8 - 6696: 0b00 addi s0,sp,400 - 6698: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne - 669c: 5a04 lw s1,48(a2) - 669e: 00018913 mv s2,gp - 66a2: 0400 addi s0,sp,512 - 66a4: 0020 addi s0,sp,8 - 66a6: 0b04 addi s1,sp,400 - 66a8: 0bf5 addi s7,s7,29 - 66aa: 0000 unimp - 66ac: 5b04 lw s1,48(a4) - 66ae: 00018913 mv s2,gp - 66b2: 0400 addi s0,sp,512 - 66b4: 0020 addi s0,sp,8 - 66b6: 0b08 addi a0,sp,400 - 66b8: 00000bfb 0xbfb - 66bc: 5c04 lw s1,56(s0) - 66be: 00018913 mv s2,gp - 66c2: 0400 addi s0,sp,512 - 66c4: 1010 addi a2,sp,32 - 66c6: 0c0c addi a1,sp,528 - 66c8: 7865 lui a6,0xffff9 - 66ca: 0070 addi a2,sp,12 - 66cc: 5d04 lw s1,56(a0) - 66ce: 530e lw t1,224(sp) - 66d0: 0000 unimp - 66d2: 0400 addi s0,sp,512 - 66d4: 0b0c010f 0xb0c010f - 66d8: 027a slli tp,tp,0x1e - 66da: 0000 unimp - 66dc: 5e04 lw s1,56(a2) - 66de: 530e lw t1,224(sp) - 66e0: 0000 unimp - 66e2: 0400 addi s0,sp,512 - 66e4: 0001 nop - 66e6: 000c 0xc - 66e8: 69070403 lb s0,1680(a4) - 66ec: 0d000003 lb zero,208(zero) # d0 <_start-0x7fffff30> - 66f0: 00000c2f 0xc2f - 66f4: 0410 addi a2,sp,512 - 66f6: 074c addi a1,sp,900 - 66f8: 01b6 slli gp,gp,0xd - 66fa: 0000 unimp - 66fc: 660e flw fa2,192(sp) - 66fe: 746c flw fa1,108(s0) - 6700: 0400 addi s0,sp,512 - 6702: 0a4e slli s4,s4,0x13 - 6704: 010c addi a1,sp,128 - 6706: 0000 unimp - 6708: 000a480f 0xa480f - 670c: 0400 addi s0,sp,512 - 670e: 0560 addi s0,sp,652 - 6710: 011f 0000 1000 0x10000000011f - 6716: 1239 addi tp,tp,-18 - 6718: 0000 unimp - 671a: 2401 jal 691a <_start-0x7fff96e6> - 671c: 8901 andi a0,a0,0 - 671e: 0000 unimp - 6720: c800 sw s0,16(s0) - 6722: 0141 addi sp,sp,16 - 6724: 3480 fld fs0,40(s1) - 6726: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 672a: 279c fld fa5,8(a5) - 672c: 0005 c.nop 1 - 672e: 1100 addi s0,sp,160 - 6730: 0061 c.nop 24 - 6732: 2401 jal 6932 <_start-0x7fff96ce> - 6734: 0c16 slli s8,s8,0x5 - 6736: 0001 nop - 6738: 1200 addi s0,sp,288 - 673a: 0000094f fnmadd.s fs2,ft0,ft0,ft0,rne - 673e: 2601 jal 6a3e <_start-0x7fff95c2> - 6740: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 6744: ea00 fsw fs0,16(a2) - 6746: 130000f3 0x130000f3 - 674a: 0a4d addi s4,s4,19 - 674c: 0000 unimp - 674e: 2601 jal 6a4e <_start-0x7fff95b2> - 6750: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> - 6754: 0000 unimp - 6756: 4114 lw a3,0(a0) - 6758: 635f 0100 0327 0x3270100635f - 675e: 00000527 vsb.v v10,(zero),v0.t - 6762: 4115 li sp,5 - 6764: 735f 0100 0327 0x3270100735f - 676a: 00000527 vsb.v v10,(zero),v0.t - 676e: f416 fsw ft5,40(sp) - 6770: 0000 unimp - 6772: 4115 li sp,5 - 6774: 655f 0100 0327 0x3270100655f - 677a: 00000527 vsb.v v10,(zero),v0.t - 677e: f454 fsw fa3,44(s0) - 6780: 0000 unimp - 6782: 4116 lw sp,68(sp) - 6784: 665f 0100 0327 0x3270100665f - 678a: 052e slli a0,a0,0xb - 678c: 0000 unimp - 678e: 9102 jalr sp - 6790: 1470 addi a2,sp,556 - 6792: 5f52 lw t5,52(sp) - 6794: 28010063 beqz sp,6a14 <_start-0x7fff95ec> - 6798: 00052703 lw a4,0(a0) - 679c: 1500 addi s0,sp,672 - 679e: 5f52 lw t5,52(sp) - 67a0: 28010073 0x28010073 - 67a4: 00052703 lw a4,0(a0) - 67a8: 1c00 addi s0,sp,560 - 67aa: 00f5 addi ra,ra,29 - 67ac: 1500 addi s0,sp,672 - 67ae: 5f52 lw t5,52(sp) - 67b0: 0065 c.nop 25 - 67b2: 2801 jal 67c2 <_start-0x7fff983e> - 67b4: 00052703 lw a4,0(a0) - 67b8: 3a00 fld fs0,48(a2) - 67ba: 00f5 addi ra,ra,29 - 67bc: 1200 addi s0,sp,288 - 67be: 0930 addi a2,sp,152 - 67c0: 0000 unimp - 67c2: 2801 jal 67d2 <_start-0x7fff982e> - 67c4: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 67c8: 3300 fld fs0,32(a4) - 67ca: 00f6 slli ra,ra,0x1d - 67cc: 1200 addi s0,sp,288 - 67ce: 0a52 slli s4,s4,0x14 - 67d0: 0000 unimp - 67d2: 2801 jal 67e2 <_start-0x7fff981e> - 67d4: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 67d8: d400 sw s0,40(s0) - 67da: 00f6 slli ra,ra,0x1d - 67dc: 1400 addi s0,sp,544 - 67de: 0072 c.slli zero,0x1c - 67e0: 2901 jal 6bf0 <_start-0x7fff9410> - 67e2: 890a mv s2,sp - 67e4: 0000 unimp - 67e6: 1700 addi s0,sp,928 - 67e8: 1238 addi a4,sp,296 - 67ea: 0000 unimp - 67ec: 02a1 addi t0,t0,8 - 67ee: 0000 unimp - 67f0: b318 fsd fa4,32(a4) - 67f2: 0100000b 0x100000b - 67f6: 032c addi a1,sp,392 - 67f8: 0190 addi a2,sp,192 - 67fa: 0000 unimp - 67fc: 9102 jalr sp - 67fe: 0060 addi s0,sp,12 - 6800: 00125017 auipc zero,0x125 - 6804: e200 fsw fs0,0(a2) - 6806: 0002 c.slli64 zero - 6808: 1300 addi s0,sp,416 - 680a: 0f3c addi a5,sp,920 - 680c: 0000 unimp - 680e: 2c01 jal 6a1e <_start-0x7fff95e2> - 6810: 00052703 lw a4,0(a0) - 6814: 0300 addi s0,sp,384 - 6816: 000d7713 andi a4,s10,0 - 681a: 0100 addi s0,sp,128 - 681c: 032c addi a1,sp,392 - 681e: 00000527 vsb.v v10,(zero),v0.t - 6822: 131d addi t1,t1,-25 - 6824: 00000d63 beqz zero,683e <_start-0x7fff97c2> - 6828: 2c01 jal 6a38 <_start-0x7fff95c8> - 682a: 00052703 lw a4,0(a0) - 682e: 0000 unimp - 6830: c912 sw tp,144(sp) - 6832: 000d c.nop 3 - 6834: 0100 addi s0,sp,128 - 6836: 032c addi a1,sp,392 - 6838: 00000527 vsb.v v10,(zero),v0.t - 683c: f799 bnez a5,674a <_start-0x7fff98b6> - 683e: 0000 unimp - 6840: 1700 addi s0,sp,928 - 6842: 12a8 addi a0,sp,360 - 6844: 0000 unimp - 6846: 0352 slli t1,t1,0x14 - 6848: 0000 unimp - 684a: 5712 lw a4,36(sp) - 684c: 000a c.slli zero,0x2 - 684e: 0100 addi s0,sp,128 - 6850: 032e slli t1,t1,0xb - 6852: 0025 c.nop 9 - 6854: 0000 unimp - 6856: f7ba fsw fa4,236(sp) - 6858: 0000 unimp - 685a: c819 beqz s0,6870 <_start-0x7fff9790> - 685c: 0012 c.slli zero,0x4 - 685e: 1200 addi s0,sp,288 - 6860: 00000ad7 vadd.vv v21,v0,v0,v0.t - 6864: 2e01 jal 6b74 <_start-0x7fff948c> - 6866: 00052703 lw a4,0(a0) - 686a: d400 sw s0,40(s0) - 686c: 120000f7 0x120000f7 - 6870: 0a6d addi s4,s4,27 - 6872: 0000 unimp - 6874: 2e01 jal 6b84 <_start-0x7fff947c> - 6876: 00052703 lw a4,0(a0) - 687a: 4200 lw s0,0(a2) - 687c: 00f8 addi a4,sp,76 - 687e: 1200 addi s0,sp,288 - 6880: 0a94 addi a3,sp,336 - 6882: 0000 unimp - 6884: 2e01 jal 6b94 <_start-0x7fff946c> - 6886: 00052703 lw a4,0(a0) - 688a: 9b00 0x9b00 - 688c: 00f8 addi a4,sp,76 - 688e: 1200 addi s0,sp,288 - 6890: 0a82 c.slli64 s5 - 6892: 0000 unimp - 6894: 2e01 jal 6ba4 <_start-0x7fff945c> - 6896: 00052703 lw a4,0(a0) - 689a: d100 sw s0,32(a0) - 689c: 00f8 addi a4,sp,76 - 689e: 1200 addi s0,sp,288 - 68a0: 0aa9 addi s5,s5,10 - 68a2: 0000 unimp - 68a4: 2e01 jal 6bb4 <_start-0x7fff944c> - 68a6: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 68aa: 7400 flw fs0,40(s0) - 68ac: 00f9 addi ra,ra,30 - 68ae: 0000 unimp - 68b0: 1a00 addi s0,sp,304 - 68b2: 4270 lw a2,68(a2) - 68b4: 8001 c.srli64 s0 - 68b6: 003c addi a5,sp,8 - 68b8: 0000 unimp - 68ba: 03b6 slli t2,t2,0xd - 68bc: 0000 unimp - 68be: 000a571b 0xa571b - 68c2: 0100 addi s0,sp,128 - 68c4: 032e slli t1,t1,0xb - 68c6: 0025 c.nop 9 - 68c8: 0000 unimp - 68ca: 7019 c.lui zero,0xfffe6 - 68cc: 0012 c.slli zero,0x4 - 68ce: 1b00 addi s0,sp,432 - 68d0: 00000ad7 vadd.vv v21,v0,v0,v0.t - 68d4: 2e01 jal 6be4 <_start-0x7fff941c> - 68d6: 00052703 lw a4,0(a0) - 68da: 1b00 addi s0,sp,432 - 68dc: 0a6d addi s4,s4,27 - 68de: 0000 unimp - 68e0: 2e01 jal 6bf0 <_start-0x7fff9410> - 68e2: 00052703 lw a4,0(a0) - 68e6: 1b00 addi s0,sp,432 - 68e8: 0a94 addi a3,sp,336 - 68ea: 0000 unimp - 68ec: 2e01 jal 6bfc <_start-0x7fff9404> - 68ee: 00052703 lw a4,0(a0) - 68f2: 1200 addi s0,sp,288 - 68f4: 0a82 c.slli64 s5 - 68f6: 0000 unimp - 68f8: 2e01 jal 6c08 <_start-0x7fff93f8> - 68fa: 00052703 lw a4,0(a0) - 68fe: 9300 0x9300 - 6900: 00f9 addi ra,ra,30 - 6902: 1200 addi s0,sp,288 - 6904: 0aa9 addi s5,s5,10 - 6906: 0000 unimp - 6908: 2e01 jal 6c18 <_start-0x7fff93e8> - 690a: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 690e: b300 fsd fs0,32(a4) - 6910: 00f9 addi ra,ra,30 - 6912: 0000 unimp - 6914: 1c00 addi s0,sp,560 - 6916: 0406 slli s0,s0,0x1 - 6918: 0000 unimp - 691a: 000a571b 0xa571b - 691e: 0100 addi s0,sp,128 - 6920: 032e slli t1,t1,0xb - 6922: 0025 c.nop 9 - 6924: 0000 unimp - 6926: 1b1d addi s6,s6,-25 - 6928: 00000ad7 vadd.vv v21,v0,v0,v0.t - 692c: 2e01 jal 6c3c <_start-0x7fff93c4> - 692e: 00052703 lw a4,0(a0) - 6932: 1b00 addi s0,sp,432 - 6934: 0a6d addi s4,s4,27 - 6936: 0000 unimp - 6938: 2e01 jal 6c48 <_start-0x7fff93b8> - 693a: 00052703 lw a4,0(a0) - 693e: 1b00 addi s0,sp,432 - 6940: 0a94 addi a3,sp,336 - 6942: 0000 unimp - 6944: 2e01 jal 6c54 <_start-0x7fff93ac> - 6946: 00052703 lw a4,0(a0) - 694a: 1b00 addi s0,sp,432 - 694c: 0a82 c.slli64 s5 - 694e: 0000 unimp - 6950: 2e01 jal 6c60 <_start-0x7fff93a0> - 6952: 00052703 lw a4,0(a0) - 6956: 1b00 addi s0,sp,432 - 6958: 0aa9 addi s5,s5,10 - 695a: 0000 unimp - 695c: 2e01 jal 6c6c <_start-0x7fff9394> - 695e: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 6962: 0000 unimp - 6964: 1700 addi s0,sp,928 - 6966: 12f0 addi a2,sp,364 - 6968: 0000 unimp - 696a: 0444 addi s1,sp,516 - 696c: 0000 unimp - 696e: 000e4e1b 0xe4e1b - 6972: 0100 addi s0,sp,128 - 6974: 032e slli t1,t1,0xb - 6976: 00000527 vsb.v v10,(zero),v0.t - 697a: 000dee1b 0xdee1b - 697e: 0100 addi s0,sp,128 - 6980: 032e slli t1,t1,0xb - 6982: 00000527 vsb.v v10,(zero),v0.t - 6986: 000e021b 0xe021b - 698a: 0100 addi s0,sp,128 - 698c: 032e slli t1,t1,0xb - 698e: 00000527 vsb.v v10,(zero),v0.t - 6992: a712 fsd ft4,392(sp) - 6994: 000d c.nop 3 - 6996: 0100 addi s0,sp,128 - 6998: 032e slli t1,t1,0xb - 699a: 00000527 vsb.v v10,(zero),v0.t - 699e: f9f6 fsw ft9,240(sp) - 69a0: 0000 unimp - 69a2: 1700 addi s0,sp,928 - 69a4: 1288 addi a0,sp,352 - 69a6: 0000 unimp - 69a8: 0510 addi a2,sp,640 - 69aa: 0000 unimp - 69ac: 3912 fld fs2,288(sp) - 69ae: 0010 0x10 - 69b0: 0100 addi s0,sp,128 - 69b2: 0332 slli t1,t1,0xc - 69b4: 0025 c.nop 9 - 69b6: 0000 unimp - 69b8: fa0a fsw ft2,52(sp) - 69ba: 0000 unimp - 69bc: d11c sw a5,32(a0) - 69be: 0004 0x4 - 69c0: 1b00 addi s0,sp,432 - 69c2: 0f8e slli t6,t6,0x3 - 69c4: 0000 unimp - 69c6: 3201 jal 62c6 <_start-0x7fff9d3a> - 69c8: 00052703 lw a4,0(a0) - 69cc: 1b00 addi s0,sp,432 - 69ce: 0fd6 slli t6,t6,0x15 - 69d0: 0000 unimp - 69d2: 3201 jal 62d2 <_start-0x7fff9d2e> - 69d4: 00052703 lw a4,0(a0) - 69d8: 1b00 addi s0,sp,432 - 69da: 1024 addi s1,sp,40 - 69dc: 0000 unimp - 69de: 3201 jal 62de <_start-0x7fff9d22> - 69e0: 00052703 lw a4,0(a0) - 69e4: 1b00 addi s0,sp,432 - 69e6: 120d addi tp,tp,-29 - 69e8: 0000 unimp - 69ea: 3201 jal 62ea <_start-0x7fff9d16> - 69ec: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 69f0: 1b00 addi s0,sp,432 - 69f2: 00001223 sh zero,4(zero) # 4 <_start-0x7ffffffc> - 69f6: 3201 jal 62f6 <_start-0x7fff9d0a> - 69f8: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 69fc: 1c00 addi s0,sp,560 - 69fe: 04b0 addi a2,sp,584 - 6a00: 0000 unimp - 6a02: 5f14 lw a3,56(a4) - 6a04: 785f 0100 0332 0x3320100785f - 6a0a: 0189 addi gp,gp,2 - 6a0c: 0000 unimp - 6a0e: 1c00 addi s0,sp,560 - 6a10: 04c2 slli s1,s1,0x10 - 6a12: 0000 unimp - 6a14: 5f14 lw a3,56(a4) - 6a16: 785f 0100 0332 0x3320100785f - 6a1c: 0189 addi gp,gp,2 - 6a1e: 0000 unimp - 6a20: 1d00 addi s0,sp,688 - 6a22: 5f14 lw a3,56(a4) - 6a24: 785f 0100 0332 0x3320100785f - 6a2a: 0189 addi gp,gp,2 - 6a2c: 0000 unimp - 6a2e: 0000 unimp - 6a30: c81a sw t1,16(sp) - 6a32: 0142 slli sp,sp,0x10 - 6a34: 1480 addi s0,sp,608 - 6a36: 0000 unimp - 6a38: ef00 fsw fs0,24(a4) - 6a3a: 0004 0x4 - 6a3c: 1500 addi s0,sp,672 - 6a3e: 5f5f 0078 3201 0x320100785f5f - 6a44: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 6a48: 1e00 addi s0,sp,816 - 6a4a: 00fa slli ra,ra,0x1e - 6a4c: 0000 unimp - 6a4e: 011c addi a5,sp,128 - 6a50: 0005 c.nop 1 - 6a52: 1400 addi s0,sp,544 - 6a54: 5f5f 0078 3201 0x320100785f5f - 6a5a: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 6a5e: 0000 unimp - 6a60: 141d addi s0,s0,-25 - 6a62: 5f5f 0078 3201 0x320100785f5f - 6a68: 00018903 lb s2,0(gp) # 80016b68 <__global_pointer$> - 6a6c: 0000 unimp - 6a6e: 1e00 addi s0,sp,816 - 6a70: 44bc lw a5,72(s1) - 6a72: 8001 c.srli64 s0 - 6a74: 001c 0x1c - 6a76: 0000 unimp - 6a78: 0008c91b 0x8c91b - 6a7c: 0100 addi s0,sp,128 - 6a7e: 0332 slli t1,t1,0xc - 6a80: 00e6 slli ra,ra,0x19 - 6a82: 0000 unimp - 6a84: 0000 unimp - 6a86: 22050403 lb s0,544(a0) - 6a8a: 0002 c.slli64 zero - 6a8c: 1f00 addi s0,sp,944 - 6a8e: 0189 addi gp,gp,2 - 6a90: 0000 unimp - 6a92: 00005307 vlhu.v v6,(zero),v0.t - 6a96: 0300 addi s0,sp,384 - 6a98: 0000 unimp - 6a9a: 00000b3b 0xb3b - 6a9e: 0004 0x4 - 6aa0: 17c1 addi a5,a5,-16 - 6aa2: 0000 unimp - 6aa4: 0104 addi s1,sp,128 - 6aa6: 07f2 slli a5,a5,0x1c - 6aa8: 0000 unimp - 6aaa: f90c fsw fa1,48(a0) - 6aac: 0004 0x4 - 6aae: fc00 fsw fs0,56(s0) - 6ab0: 0002 c.slli64 zero - 6ab2: 7a00 flw fs0,48(a2) - 6ab4: 0085 addi ra,ra,1 - 6ab6: 0200 addi s0,sp,256 - 6ab8: 0504 addi s1,sp,640 - 6aba: 6e69 lui t3,0x1a - 6abc: 0074 addi a3,sp,12 - 6abe: 6e070403 lb s0,1760(a4) - 6ac2: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 6ac6: 0508 addi a0,sp,640 - 6ac8: 021d addi tp,tp,7 - 6aca: 0000 unimp - 6acc: 9d041003 lh zero,-1584(s0) - 6ad0: 0000 unimp - 6ad2: 0300 addi s0,sp,384 - 6ad4: 0601 addi a2,a2,0 - 6ad6: 0669 addi a2,a2,26 - 6ad8: 0000 unimp - 6ada: 67080103 lb sp,1648(a6) # ffff9670 <__BSS_END__+0x7ffe28f8> - 6ade: 0006 c.slli zero,0x1 - 6ae0: 0300 addi s0,sp,384 - 6ae2: 0502 c.slli64 a0 - 6ae4: 0000 unimp - 6ae6: 0000 unimp - 6ae8: 84070203 lb tp,-1984(a4) - 6aec: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 6af0: 0504 addi s1,sp,640 - 6af2: 0222 slli tp,tp,0x8 - 6af4: 0000 unimp - 6af6: 69070403 lb s0,1680(a4) - 6afa: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 6afe: 0708 addi a0,sp,896 - 6b00: 0364 addi s1,sp,396 - 6b02: 0000 unimp - 6b04: e104 fsw fs1,0(a0) - 6b06: 0004 0x4 - 6b08: 0100 addi s0,sp,128 - 6b0a: 0d0c addi a1,sp,656 - 6b0c: 001d c.nop 7 - 6b0e: 0000 unimp - 6b10: b104 fsd fs1,32(a0) - 6b12: 0004 0x4 - 6b14: 0200 addi s0,sp,256 - 6b16: 0e2c addi a1,sp,792 - 6b18: 0055 c.nop 21 - 6b1a: 0000 unimp - 6b1c: fa04 fsw fs1,48(a2) - 6b1e: 0005 c.nop 1 - 6b20: 0200 addi s0,sp,256 - 6b22: 0e72 slli t3,t3,0x1c - 6b24: 0055 c.nop 21 - 6b26: 0000 unimp - 6b28: d104 sw s1,32(a0) - 6b2a: 0006 c.slli zero,0x1 - 6b2c: 0200 addi s0,sp,256 - 6b2e: 1791 addi a5,a5,-28 - 6b30: 001d c.nop 7 - 6b32: 0000 unimp - 6b34: e405 bnez s0,6b5c <_start-0x7fff94a4> - 6b36: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 6b3a: 0165 addi sp,sp,25 - 6b3c: 00002417 auipc s0,0x2 - 6b40: 0600 addi s0,sp,768 - 6b42: 0204 addi s1,sp,256 - 6b44: 03a6 slli t2,t2,0x9 - 6b46: 00c9 addi ra,ra,18 - 6b48: 0000 unimp - 6b4a: 0003cb07 flq fs6,0(t2) - 6b4e: 0200 addi s0,sp,256 - 6b50: 0ca8 addi a0,sp,600 - 6b52: 009a slli ra,ra,0x6 - 6b54: 0000 unimp - 6b56: 0002d507 vlhu.v v10,(t0),v0.t - 6b5a: 0200 addi s0,sp,256 - 6b5c: 13a9 addi t2,t2,-22 - 6b5e: 00c9 addi ra,ra,18 - 6b60: 0000 unimp - 6b62: 0800 addi s0,sp,16 - 6b64: 0040 addi s0,sp,4 - 6b66: 0000 unimp - 6b68: 00d9 addi ra,ra,22 - 6b6a: 0000 unimp - 6b6c: 2409 jal 6d6e <_start-0x7fff9292> - 6b6e: 0000 unimp - 6b70: 0300 addi s0,sp,384 - 6b72: 0a00 addi s0,sp,272 - 6b74: 0208 addi a0,sp,256 - 6b76: 00fd09a3 sb a5,19(s10) # 4013 <_start-0x7fffbfed> - 6b7a: 0000 unimp - 6b7c: 0004350b 0x4350b - 6b80: 0200 addi s0,sp,256 - 6b82: 07a5 addi a5,a5,9 - 6b84: 001d c.nop 7 - 6b86: 0000 unimp - 6b88: 0b00 addi s0,sp,400 - 6b8a: 05ec addi a1,sp,716 - 6b8c: 0000 unimp - 6b8e: aa02 fsd ft0,272(sp) - 6b90: a705 j 72b0 <_start-0x7fff8d50> - 6b92: 0000 unimp - 6b94: 0400 addi s0,sp,512 - 6b96: 0400 addi s0,sp,512 - 6b98: 04d6 slli s1,s1,0x15 - 6b9a: 0000 unimp - 6b9c: ab02 fsd ft0,400(sp) - 6b9e: 0000d903 lhu s2,0(ra) # 4000 <_start-0x7fffc000> - 6ba2: 0400 addi s0,sp,512 - 6ba4: 00000557 vadd.vv v10,v0,v0,v0.t - 6ba8: af02 fsd ft0,408(sp) - 6baa: 00006a1b 0x6a1b - 6bae: 0c00 addi s0,sp,528 - 6bb0: 0404 addi s1,sp,512 - 6bb2: 067a slli a2,a2,0x1e - 6bb4: 0000 unimp - 6bb6: 1604 addi s1,sp,800 - 6bb8: 5c19 li s8,-26 - 6bba: 0000 unimp - 6bbc: 0d00 addi s0,sp,656 - 6bbe: 046e slli s0,s0,0x1b - 6bc0: 0000 unimp - 6bc2: 0418 addi a4,sp,512 - 6bc4: 017d082f 0x17d082f - 6bc8: 0000 unimp - 6bca: 0007910b 0x7910b - 6bce: 0400 addi s0,sp,512 - 6bd0: 1331 addi t1,t1,-20 - 6bd2: 017d addi sp,sp,31 - 6bd4: 0000 unimp - 6bd6: 0e00 addi s0,sp,784 - 6bd8: 6b5f 0400 0732 0x73204006b5f - 6bde: 001d c.nop 7 - 6be0: 0000 unimp - 6be2: 0b04 addi s1,sp,400 - 6be4: 05c9 addi a1,a1,18 - 6be6: 0000 unimp - 6be8: 3204 fld fs1,32(a2) - 6bea: 00001d0b 0x1d0b - 6bee: 0800 addi s0,sp,16 - 6bf0: 0002790b 0x2790b - 6bf4: 0400 addi s0,sp,512 - 6bf6: 1432 slli s0,s0,0x2c - 6bf8: 001d c.nop 7 - 6bfa: 0000 unimp - 6bfc: 0b0c addi a1,sp,400 - 6bfe: 01ff 0x1ff - 6c00: 0000 unimp - 6c02: 3204 fld fs1,32(a2) - 6c04: 00001d1b 0x1d1b - 6c08: 1000 addi s0,sp,32 - 6c0a: 5f0e lw t5,224(sp) - 6c0c: 0078 addi a4,sp,12 - 6c0e: 3304 fld fs1,32(a4) - 6c10: 0001830b 0x1830b - 6c14: 1400 addi s0,sp,544 - 6c16: 0f00 addi s0,sp,912 - 6c18: 2304 fld fs1,0(a4) - 6c1a: 0001 nop - 6c1c: 0800 addi s0,sp,16 - 6c1e: 00000117 auipc sp,0x0 - 6c22: 00000193 li gp,0 - 6c26: 2409 jal 6e28 <_start-0x7fff91d8> - 6c28: 0000 unimp - 6c2a: 0000 unimp - 6c2c: 0d00 addi s0,sp,656 - 6c2e: 02b8 addi a4,sp,328 - 6c30: 0000 unimp - 6c32: 0424 addi s1,sp,520 - 6c34: 02160837 lui a6,0x2160 - 6c38: 0000 unimp - 6c3a: 0000d50b 0xd50b - 6c3e: 0400 addi s0,sp,512 - 6c40: 0939 addi s2,s2,14 - 6c42: 001d c.nop 7 - 6c44: 0000 unimp - 6c46: 0b00 addi s0,sp,400 - 6c48: 0000072f 0x72f - 6c4c: 3a04 fld fs1,48(a2) - 6c4e: 1d09 addi s10,s10,-30 - 6c50: 0000 unimp - 6c52: 0400 addi s0,sp,512 - 6c54: 0001b50b 0x1b50b - 6c58: 0400 addi s0,sp,512 - 6c5a: 001d093b 0x1d093b - 6c5e: 0000 unimp - 6c60: 0b08 addi a0,sp,400 - 6c62: 0782 c.slli64 a5 - 6c64: 0000 unimp - 6c66: 3c04 fld fs1,56(s0) - 6c68: 1d09 addi s10,s10,-30 - 6c6a: 0000 unimp - 6c6c: 0c00 addi s0,sp,528 - 6c6e: 00048b0b 0x48b0b - 6c72: 0400 addi s0,sp,512 - 6c74: 093d addi s2,s2,15 - 6c76: 001d c.nop 7 - 6c78: 0000 unimp - 6c7a: 0b10 addi a2,sp,400 - 6c7c: 0000042b 0x42b - 6c80: 3e04 fld fs1,56(a2) - 6c82: 1d09 addi s10,s10,-30 - 6c84: 0000 unimp - 6c86: 1400 addi s0,sp,544 - 6c88: 0006ba0b 0x6ba0b - 6c8c: 0400 addi s0,sp,512 - 6c8e: 001d093f 0b180000 0xb180000001d093f - 6c96: 0560 addi s0,sp,652 - 6c98: 0000 unimp - 6c9a: 4004 lw s1,0(s0) - 6c9c: 1d09 addi s10,s10,-30 - 6c9e: 0000 unimp - 6ca0: 1c00 addi s0,sp,560 - 6ca2: 0007150b 0x7150b - 6ca6: 0400 addi s0,sp,512 - 6ca8: 0941 addi s2,s2,16 - 6caa: 001d c.nop 7 - 6cac: 0000 unimp - 6cae: 0020 addi s0,sp,8 - 6cb0: d210 sw a2,32(a2) - 6cb2: 0001 nop - 6cb4: 0800 addi s0,sp,16 - 6cb6: 0401 addi s0,s0,0 - 6cb8: 084a slli a6,a6,0x12 - 6cba: 0000025b 0x25b - 6cbe: 00026c0b 0x26c0b - 6cc2: 0400 addi s0,sp,512 - 6cc4: 025b0a4b fnmsub.d fs4,fs6,ft5,ft0,rne - 6cc8: 0000 unimp - 6cca: 0b00 addi s0,sp,400 - 6ccc: 00000533 add a0,zero,zero - 6cd0: 4c04 lw s1,24(s0) - 6cd2: 5b09 li s6,-30 - 6cd4: 0002 c.slli64 zero - 6cd6: 8000 0x8000 - 6cd8: 5e11 li t3,-28 - 6cda: 0006 c.slli zero,0x1 - 6cdc: 0400 addi s0,sp,512 - 6cde: 0a4e slli s4,s4,0x13 - 6ce0: 00000117 auipc sp,0x0 - 6ce4: 0100 addi s0,sp,128 - 6ce6: f711 bnez a4,6bf2 <_start-0x7fff940e> - 6ce8: 0001 nop - 6cea: 0400 addi s0,sp,512 - 6cec: 0a51 addi s4,s4,20 - 6cee: 00000117 auipc sp,0x0 - 6cf2: 0104 addi s1,sp,128 - 6cf4: 0800 addi s0,sp,16 - 6cf6: 0115 addi sp,sp,5 - 6cf8: 0000 unimp - 6cfa: 0000026b 0x26b - 6cfe: 2409 jal 6f00 <_start-0x7fff9100> - 6d00: 0000 unimp - 6d02: 1f00 addi s0,sp,944 - 6d04: 1000 addi s0,sp,32 - 6d06: 0494 addi a3,sp,576 - 6d08: 0000 unimp - 6d0a: 0190 addi a2,sp,192 - 6d0c: 5d04 lw s1,56(a0) - 6d0e: ae08 fsd fa0,24(a2) - 6d10: 0002 c.slli64 zero - 6d12: 0b00 addi s0,sp,400 - 6d14: 0791 addi a5,a5,4 - 6d16: 0000 unimp - 6d18: 5e04 lw s1,56(a2) - 6d1a: ae12 fsd ft4,280(sp) - 6d1c: 0002 c.slli64 zero - 6d1e: 0000 unimp - 6d20: 0005b00b 0x5b00b - 6d24: 0400 addi s0,sp,512 - 6d26: 065f 001d 0000 0x1d065f - 6d2c: 0b04 addi s1,sp,400 - 6d2e: 0274 addi a3,sp,268 - 6d30: 0000 unimp - 6d32: 6104 flw fs1,0(a0) - 6d34: b409 j 6736 <_start-0x7fff98ca> - 6d36: 0002 c.slli64 zero - 6d38: 0800 addi s0,sp,16 - 6d3a: 0001d20b 0x1d20b - 6d3e: 0400 addi s0,sp,512 - 6d40: 1e62 slli t3,t3,0x38 - 6d42: 0216 slli tp,tp,0x5 - 6d44: 0000 unimp - 6d46: 0088 addi a0,sp,64 - 6d48: 026b040f 0x26b040f - 6d4c: 0000 unimp - 6d4e: c408 sw a0,8(s0) - 6d50: 0002 c.slli64 zero - 6d52: c400 sw s0,8(s0) - 6d54: 0002 c.slli64 zero - 6d56: 0900 addi s0,sp,144 - 6d58: 0024 addi s1,sp,8 - 6d5a: 0000 unimp - 6d5c: 001f 040f 02ca 0x2ca040f001f - 6d62: 0000 unimp - 6d64: 0d12 slli s10,s10,0x4 - 6d66: 0000077b 0x77b - 6d6a: 0408 addi a0,sp,512 - 6d6c: 0875 addi a6,a6,29 - 6d6e: 000002f3 0x2f3 - 6d72: 0001af0b 0x1af0b - 6d76: 0400 addi s0,sp,512 - 6d78: 1176 slli sp,sp,0x3d - 6d7a: 000002f3 0x2f3 - 6d7e: 0b00 addi s0,sp,400 - 6d80: 0000060b 0x60b - 6d84: 7704 flw fs1,40(a4) - 6d86: 1d06 slli s10,s10,0x21 - 6d88: 0000 unimp - 6d8a: 0400 addi s0,sp,512 - 6d8c: 0f00 addi s0,sp,912 - 6d8e: 4004 lw s1,0(s0) - 6d90: 0000 unimp - 6d92: 0d00 addi s0,sp,656 - 6d94: 058c addi a1,sp,704 - 6d96: 0000 unimp - 6d98: 0468 addi a0,sp,524 - 6d9a: 08b5 addi a7,a7,13 - 6d9c: 043c addi a5,sp,520 - 6d9e: 0000 unimp - 6da0: 5f0e lw t5,224(sp) - 6da2: 0070 addi a2,sp,12 - 6da4: b604 fsd fs1,40(a2) - 6da6: f312 fsw ft4,164(sp) - 6da8: 0002 c.slli64 zero - 6daa: 0000 unimp - 6dac: 5f0e lw t5,224(sp) - 6dae: 0072 c.slli zero,0x1c - 6db0: b704 fsd fs1,40(a4) - 6db2: 00001d07 0x1d07 - 6db6: 0400 addi s0,sp,512 - 6db8: 5f0e lw t5,224(sp) - 6dba: b8040077 0xb8040077 - 6dbe: 00001d07 0x1d07 - 6dc2: 0800 addi s0,sp,16 - 6dc4: 0001f00b 0x1f00b - 6dc8: 0400 addi s0,sp,512 - 6dca: 09b9 addi s3,s3,14 - 6dcc: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne - 6dd0: 0b0c addi a1,sp,400 - 6dd2: 02e4 addi s1,sp,332 - 6dd4: 0000 unimp - 6dd6: ba04 fsd fs1,48(a2) - 6dd8: 4709 li a4,2 - 6dda: 0000 unimp - 6ddc: 0e00 addi s0,sp,784 - 6dde: 5f0e lw t5,224(sp) - 6de0: 6662 flw fa2,24(sp) - 6de2: 0400 addi s0,sp,512 - 6de4: 02cb11bb 0x2cb11bb - 6de8: 0000 unimp - 6dea: 0b10 addi a2,sp,400 - 6dec: 0085 addi ra,ra,1 - 6dee: 0000 unimp - 6df0: bc04 fsd fs1,56(s0) - 6df2: 00001d07 0x1d07 - 6df6: 1800 addi s0,sp,48 - 6df8: 0001e00b 0x1e00b - 6dfc: 0400 addi s0,sp,512 - 6dfe: 01150ac3 fmadd.s fs5,fa0,fa7,ft0,rne - 6e02: 0000 unimp - 6e04: 0b1c addi a5,sp,400 - 6e06: 000004f3 0x4f3 - 6e0a: c504 sw s1,8(a0) - 6e0c: c01d beqz s0,6e32 <_start-0x7fff91ce> - 6e0e: 0005 c.nop 1 - 6e10: 2000 fld fs0,0(s0) - 6e12: 0004240b 0x4240b - 6e16: 0400 addi s0,sp,512 - 6e18: 05ef1dc7 0x5ef1dc7 - 6e1c: 0000 unimp - 6e1e: 0b24 addi s1,sp,408 - 6e20: 05f4 addi a3,sp,716 - 6e22: 0000 unimp - 6e24: ca04 sw s1,16(a2) - 6e26: 130d addi t1,t1,-29 - 6e28: 0006 c.slli zero,0x1 - 6e2a: 2800 fld fs0,16(s0) - 6e2c: 0000de0b 0xde0b - 6e30: 0400 addi s0,sp,512 - 6e32: 062d09cb fnmsub.q fs3,fs10,ft2,ft0,rne - 6e36: 0000 unimp - 6e38: 0e2c addi a1,sp,792 - 6e3a: 755f 0062 ce04 0xce040062755f - 6e40: cb11 beqz a4,6e54 <_start-0x7fff91ac> - 6e42: 0002 c.slli64 zero - 6e44: 3000 fld fs0,32(s0) - 6e46: 5f0e lw t5,224(sp) - 6e48: 7075 c.lui zero,0xffffd - 6e4a: 0400 addi s0,sp,512 - 6e4c: 02f312cf fnmadd.d ft5,ft6,fa5,ft0,rtz - 6e50: 0000 unimp - 6e52: 0e38 addi a4,sp,792 - 6e54: 755f 0072 d004 0xd0040072755f - 6e5a: 00001d07 0x1d07 - 6e5e: 3c00 fld fs0,56(s0) - 6e60: 0001a90b 0x1a90b - 6e64: 0400 addi s0,sp,512 - 6e66: 063311d3 fadd.q ft3,ft6,ft3,rtz - 6e6a: 0000 unimp - 6e6c: 0b40 addi s0,sp,404 - 6e6e: 06fd addi a3,a3,31 - 6e70: 0000 unimp - 6e72: d404 sw s1,40(s0) - 6e74: 4311 li t1,4 - 6e76: 0006 c.slli zero,0x1 - 6e78: 4300 lw s0,0(a4) - 6e7a: 5f0e lw t5,224(sp) - 6e7c: 626c flw fa1,68(a2) - 6e7e: 0400 addi s0,sp,512 - 6e80: 02cb11d7 vfadd.vv v3,v12,v22 - 6e84: 0000 unimp - 6e86: 0b44 addi s1,sp,404 - 6e88: 0602 c.slli64 a2 - 6e8a: 0000 unimp - 6e8c: da04 sw s1,48(a2) - 6e8e: 00001d07 0x1d07 - 6e92: 4c00 lw s0,24(s0) - 6e94: 0004660b 0x4660b - 6e98: 0400 addi s0,sp,512 - 6e9a: 00760adb 0x760adb - 6e9e: 0000 unimp - 6ea0: 0b50 addi a2,sp,404 - 6ea2: 0055 c.nop 21 - 6ea4: 0000 unimp - 6ea6: de04 sw s1,56(a2) - 6ea8: 5a12 lw s4,36(sp) - 6eaa: 0004 0x4 - 6eac: 5400 lw s0,40(s0) - 6eae: 0003eb0b 0x3eb0b - 6eb2: 0400 addi s0,sp,512 - 6eb4: 0ce2 slli s9,s9,0x18 - 6eb6: 0109 addi sp,sp,2 - 6eb8: 0000 unimp - 6eba: 0b58 addi a4,sp,404 - 6ebc: 02cc addi a1,sp,324 - 6ebe: 0000 unimp - 6ec0: e404 fsw fs1,8(s0) - 6ec2: fd0e fsw ft3,184(sp) - 6ec4: 0000 unimp - 6ec6: 5c00 lw s0,56(s0) - 6ec8: 00056a0b 0x56a0b - 6ecc: 0400 addi s0,sp,512 - 6ece: 09e5 addi s3,s3,25 - 6ed0: 001d c.nop 7 - 6ed2: 0000 unimp - 6ed4: 0064 addi s1,sp,12 - 6ed6: 00008e13 mv t3,ra - 6eda: 5a00 lw s0,48(a2) - 6edc: 0004 0x4 - 6ede: 1400 addi s0,sp,544 - 6ee0: 045a slli s0,s0,0x16 - 6ee2: 0000 unimp - 6ee4: 1514 addi a3,sp,672 - 6ee6: 0001 nop - 6ee8: 1400 addi s0,sp,544 - 6eea: 05ae slli a1,a1,0xb - 6eec: 0000 unimp - 6eee: 1d14 addi a3,sp,688 - 6ef0: 0000 unimp - 6ef2: 0000 unimp - 6ef4: 0465040f 0x465040f - 6ef8: 0000 unimp - 6efa: 5a15 li s4,-27 - 6efc: 0004 0x4 - 6efe: 1600 addi s0,sp,800 - 6f00: 05d1 addi a1,a1,20 - 6f02: 0000 unimp - 6f04: 0428 addi a0,sp,520 - 6f06: 6004 flw fs1,0(s0) - 6f08: 0802 c.slli64 a6 - 6f0a: 05ae slli a1,a1,0xb - 6f0c: 0000 unimp - 6f0e: 00055017 auipc zero,0x55 - 6f12: 0400 addi s0,sp,512 - 6f14: 0262 slli tp,tp,0x18 - 6f16: 00001d07 0x1d07 - 6f1a: 0000 unimp - 6f1c: 0006ca17 auipc s4,0x6c - 6f20: 0400 addi s0,sp,512 - 6f22: 9f0b0267 jalr tp,-1552(s6) # 6f9f0 <_start-0x7ff90610> - 6f26: 0006 c.slli zero,0x1 - 6f28: 0400 addi s0,sp,512 - 6f2a: 0006b217 auipc tp,0x6b - 6f2e: 0400 addi s0,sp,512 - 6f30: 9f140267 jalr tp,-1551(s0) # 852d <_start-0x7fff7ad3> - 6f34: 0006 c.slli zero,0x1 - 6f36: 0800 addi s0,sp,16 - 6f38: 00027f17 auipc t5,0x27 - 6f3c: 0400 addi s0,sp,512 - 6f3e: 9f1e0267 jalr tp,-1551(t3) # 199f1 <_start-0x7ffe660f> - 6f42: 0006 c.slli zero,0x1 - 6f44: 0c00 addi s0,sp,528 - 6f46: 0005ab17 auipc s6,0x5a - 6f4a: 0400 addi s0,sp,512 - 6f4c: 0269 addi tp,tp,26 - 6f4e: 1d08 addi a0,sp,688 - 6f50: 0000 unimp - 6f52: 1000 addi s0,sp,32 - 6f54: 00002417 auipc s0,0x2 - 6f58: 0400 addi s0,sp,512 - 6f5a: 026a slli tp,tp,0x1a - 6f5c: 9f08 0x9f08 - 6f5e: 0008 0x8 - 6f60: 1400 addi s0,sp,544 - 6f62: 00029f17 auipc t5,0x29 - 6f66: 0400 addi s0,sp,512 - 6f68: 026d addi tp,tp,27 - 6f6a: 00001d07 0x1d07 - 6f6e: 3000 fld fs0,32(s0) - 6f70: 00076b17 auipc s6,0x76 - 6f74: 0400 addi s0,sp,512 - 6f76: 026e slli tp,tp,0x1b - 6f78: b416 fsd ft5,40(sp) - 6f7a: 0008 0x8 - 6f7c: 3400 fld fs0,40(s0) - 6f7e: 0004a617 auipc a2,0x4a - 6f82: 0400 addi s0,sp,512 - 6f84: 0270 addi a2,sp,268 - 6f86: 00001d07 0x1d07 - 6f8a: 3800 fld fs0,48(s0) - 6f8c: 0005bf17 auipc t5,0x5b - 6f90: 0400 addi s0,sp,512 - 6f92: 0272 slli tp,tp,0x1c - 6f94: c50a sw sp,136(sp) - 6f96: 0008 0x8 - 6f98: 3c00 fld fs0,56(s0) - 6f9a: 0003c317 auipc t1,0x3c - 6f9e: 0400 addi s0,sp,512 - 6fa0: 0275 addi tp,tp,29 - 6fa2: 00017d13 andi s10,sp,0 - 6fa6: 4000 lw s0,0(s0) - 6fa8: 00020b17 auipc s6,0x20 - 6fac: 0400 addi s0,sp,512 - 6fae: 0276 slli tp,tp,0x1d - 6fb0: 00001d07 0x1d07 - 6fb4: 4400 lw s0,8(s0) - 6fb6: 00076617 auipc a2,0x76 - 6fba: 0400 addi s0,sp,512 - 6fbc: 7d130277 0x7d130277 - 6fc0: 0001 nop - 6fc2: 4800 lw s0,16(s0) - 6fc4: 0004c217 auipc tp,0x4c - 6fc8: 0400 addi s0,sp,512 - 6fca: 0278 addi a4,sp,268 - 6fcc: cb14 sw a3,16(a4) - 6fce: 0008 0x8 - 6fd0: 4c00 lw s0,24(s0) - 6fd2: 0002dc17 auipc s8,0x2d - 6fd6: 0400 addi s0,sp,512 - 6fd8: 1d07027b 0x1d07027b - 6fdc: 0000 unimp - 6fde: 5000 lw s0,32(s0) - 6fe0: 00023817 auipc a6,0x23 - 6fe4: 0400 addi s0,sp,512 - 6fe6: 027c addi a5,sp,268 - 6fe8: ae09 j 72fa <_start-0x7fff8d06> - 6fea: 0005 c.nop 1 - 6fec: 5400 lw s0,40(s0) - 6fee: 00054917 auipc s2,0x54 - 6ff2: 0400 addi s0,sp,512 - 6ff4: 029f 7a07 0008 0x87a07029f - 6ffa: 5800 lw s0,48(s0) - 6ffc: 9418 0x9418 - 6ffe: 0004 0x4 - 7000: 0400 addi s0,sp,512 - 7002: ae1302a3 sb ra,-1307(t1) # 42a7f <_start-0x7ffbd581> - 7006: 0002 c.slli64 zero - 7008: 4800 lw s0,16(s0) - 700a: 1801 addi a6,a6,-32 - 700c: 03a1 addi t2,t2,8 - 700e: 0000 unimp - 7010: a404 fsd fs1,8(s0) - 7012: 1202 slli tp,tp,0x20 - 7014: 0000026b 0x26b - 7018: 014c addi a1,sp,132 - 701a: e418 fsw fa4,8(s0) - 701c: 0006 c.slli zero,0x1 - 701e: 0400 addi s0,sp,512 - 7020: 02a8 addi a0,sp,328 - 7022: dc0c sw a1,56(s0) - 7024: 0008 0x8 - 7026: dc00 sw s0,56(s0) - 7028: 1802 slli a6,a6,0x20 - 702a: 01e8 addi a0,sp,204 - 702c: 0000 unimp - 702e: ad04 fsd fs1,24(a0) - 7030: 1002 c.slli zero,0x20 - 7032: 0660 addi s0,sp,780 - 7034: 0000 unimp - 7036: 02e0 addi s0,sp,332 - 7038: cd18 sw a4,24(a0) - 703a: 0001 nop - 703c: 0400 addi s0,sp,512 - 703e: e80a02af 0xe80a02af - 7042: 0008 0x8 - 7044: ec00 fsw fs0,24(s0) - 7046: 0002 c.slli64 zero - 7048: 05b4040f 0x5b4040f - 704c: 0000 unimp - 704e: 70080103 lb sp,1792(a6) # 2a6e0 <_start-0x7ffd5920> - 7052: 0006 c.slli zero,0x1 - 7054: 1500 addi s0,sp,672 - 7056: 05b4 addi a3,sp,712 - 7058: 0000 unimp - 705a: 043c040f 0x43c040f - 705e: 0000 unimp - 7060: 00008e13 mv t3,ra - 7064: e400 fsw fs0,8(s0) - 7066: 0005 c.nop 1 - 7068: 1400 addi s0,sp,544 - 706a: 045a slli s0,s0,0x16 - 706c: 0000 unimp - 706e: 1514 addi a3,sp,672 - 7070: 0001 nop - 7072: 1400 addi s0,sp,544 - 7074: 05e4 addi s1,sp,716 - 7076: 0000 unimp - 7078: 1d14 addi a3,sp,688 - 707a: 0000 unimp - 707c: 0000 unimp - 707e: 05bb040f 0x5bb040f - 7082: 0000 unimp - 7084: e415 bnez s0,70b0 <_start-0x7fff8f50> - 7086: 0005 c.nop 1 - 7088: 0f00 addi s0,sp,912 - 708a: c604 sw s1,8(a2) - 708c: 0005 c.nop 1 - 708e: 1300 addi s0,sp,416 - 7090: 0082 c.slli64 ra - 7092: 0000 unimp - 7094: 00000613 li a2,0 - 7098: 5a14 lw a3,48(a2) - 709a: 0004 0x4 - 709c: 1400 addi s0,sp,544 - 709e: 0115 addi sp,sp,5 - 70a0: 0000 unimp - 70a2: 8214 0x8214 - 70a4: 0000 unimp - 70a6: 1400 addi s0,sp,544 - 70a8: 001d c.nop 7 - 70aa: 0000 unimp - 70ac: 0f00 addi s0,sp,912 - 70ae: f504 fsw fs1,40(a0) - 70b0: 0005 c.nop 1 - 70b2: 1300 addi s0,sp,416 - 70b4: 001d c.nop 7 - 70b6: 0000 unimp - 70b8: 062d addi a2,a2,11 - 70ba: 0000 unimp - 70bc: 5a14 lw a3,48(a2) - 70be: 0004 0x4 - 70c0: 1400 addi s0,sp,544 - 70c2: 0115 addi sp,sp,5 - 70c4: 0000 unimp - 70c6: 0f00 addi s0,sp,912 - 70c8: 1904 addi s1,sp,176 - 70ca: 0006 c.slli zero,0x1 - 70cc: 0800 addi s0,sp,16 - 70ce: 0040 addi s0,sp,4 - 70d0: 0000 unimp - 70d2: 00000643 fmadd.s fa2,ft0,ft0,ft0,rne - 70d6: 2409 jal 72d8 <_start-0x7fff8d28> - 70d8: 0000 unimp - 70da: 0200 addi s0,sp,256 - 70dc: 0800 addi s0,sp,16 - 70de: 0040 addi s0,sp,4 - 70e0: 0000 unimp - 70e2: 00000653 fadd.s fa2,ft0,ft0,rne - 70e6: 2409 jal 72e8 <_start-0x7fff8d18> - 70e8: 0000 unimp - 70ea: 0000 unimp - 70ec: 0500 addi s0,sp,640 - 70ee: 0204 addi s1,sp,256 - 70f0: 0000 unimp - 70f2: 1f04 addi s1,sp,944 - 70f4: 1a01 addi s4,s4,-32 - 70f6: 02f9 addi t0,t0,30 - 70f8: 0000 unimp - 70fa: c419 beqz s0,7108 <_start-0x7fff8ef8> - 70fc: 0006 c.slli zero,0x1 - 70fe: 0c00 addi s0,sp,528 - 7100: 2304 fld fs1,0(a4) - 7102: 0801 addi a6,a6,0 - 7104: 0699 addi a3,a3,6 - 7106: 0000 unimp - 7108: 00079117 auipc sp,0x79 - 710c: 0400 addi s0,sp,512 - 710e: 0125 addi sp,sp,9 - 7110: 9911 andi a0,a0,-28 - 7112: 0006 c.slli zero,0x1 - 7114: 0000 unimp - 7116: 00035d17 auipc s10,0x35 - 711a: 0400 addi s0,sp,512 - 711c: 0126 slli sp,sp,0x9 - 711e: 00001d07 0x1d07 - 7122: 0400 addi s0,sp,512 - 7124: 00057217 auipc tp,0x57 - 7128: 0400 addi s0,sp,512 - 712a: 9f0b0127 0x9f0b0127 - 712e: 0006 c.slli zero,0x1 - 7130: 0800 addi s0,sp,16 - 7132: 0f00 addi s0,sp,912 - 7134: 6004 flw fs1,0(s0) - 7136: 0006 c.slli zero,0x1 - 7138: 0f00 addi s0,sp,912 - 713a: 5304 lw s1,32(a4) - 713c: 0006 c.slli zero,0x1 - 713e: 1900 addi s0,sp,176 - 7140: 001c 0x1c - 7142: 0000 unimp - 7144: 040e slli s0,s0,0x3 - 7146: de08013f 17000006 0x17000006de08013f - 714e: 062e slli a2,a2,0xb - 7150: 0000 unimp - 7152: 4004 lw s1,0(s0) - 7154: 1201 addi tp,tp,-32 - 7156: 06de slli a3,a3,0x17 - 7158: 0000 unimp - 715a: 1700 addi s0,sp,928 - 715c: 0401 addi s0,s0,0 - 715e: 0000 unimp - 7160: 4104 lw s1,0(a0) - 7162: 1201 addi tp,tp,-32 - 7164: 06de slli a3,a3,0x17 - 7166: 0000 unimp - 7168: 1706 slli a4,a4,0x21 - 716a: 0675 addi a2,a2,29 - 716c: 0000 unimp - 716e: 4204 lw s1,0(a2) - 7170: 1201 addi tp,tp,-32 - 7172: 004e c.slli zero,0x13 - 7174: 0000 unimp - 7176: 000c 0xc - 7178: 4e08 lw a0,24(a2) - 717a: 0000 unimp - 717c: ee00 fsw fs0,24(a2) - 717e: 0006 c.slli zero,0x1 - 7180: 0900 addi s0,sp,144 - 7182: 0024 addi s1,sp,8 - 7184: 0000 unimp - 7186: 0002 c.slli64 zero - 7188: d01a sw t1,32(sp) - 718a: 8004 0x8004 - 718c: 0702 c.slli64 a4 - 718e: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - 7192: 00043d17 auipc s10,0x43 - 7196: 0400 addi s0,sp,512 - 7198: 0282 c.slli64 t0 - 719a: 2418 fld fa4,8(s0) - 719c: 0000 unimp - 719e: 0000 unimp - 71a0: 00064a17 auipc s4,0x64 - 71a4: 0400 addi s0,sp,512 - 71a6: ae120283 lb t0,-1311(tp) # 5dc05 <_start-0x7ffa23fb> - 71aa: 0005 c.nop 1 - 71ac: 0400 addi s0,sp,512 - 71ae: 0003b617 auipc a2,0x3b - 71b2: 0400 addi s0,sp,512 - 71b4: 0284 addi s1,sp,320 - 71b6: 0310 addi a2,sp,384 - 71b8: 0008 0x8 - 71ba: 0800 addi s0,sp,16 - 71bc: 00072017 auipc zero,0x72 - 71c0: 0400 addi s0,sp,512 - 71c2: 0285 addi t0,t0,1 - 71c4: 00019317 auipc t1,0x19 - 71c8: 2400 fld fs0,8(s0) - 71ca: 00028717 auipc a4,0x28 - 71ce: 0400 addi s0,sp,512 - 71d0: 0286 slli t0,t0,0x1 - 71d2: 00001d0f 0x1d0f - 71d6: 4800 lw s0,16(s0) - 71d8: 00078c17 auipc s8,0x78 - 71dc: 0400 addi s0,sp,512 - 71de: 632c0287 0x632c0287 - 71e2: 0000 unimp - 71e4: 5000 lw s0,32(s0) - 71e6: 00073817 auipc a6,0x73 - 71ea: 0400 addi s0,sp,512 - 71ec: 0288 addi a0,sp,320 - 71ee: a51a fsd ft6,136(sp) - 71f0: 0006 c.slli zero,0x1 - 71f2: 5800 lw s0,48(s0) - 71f4: 00059e17 auipc t3,0x59 - 71f8: 0400 addi s0,sp,512 - 71fa: 0289 addi t0,t0,2 - 71fc: fd16 fsw ft5,184(sp) - 71fe: 0000 unimp - 7200: 6800 flw fs0,16(s0) - 7202: 00075817 auipc a6,0x75 - 7206: 0400 addi s0,sp,512 - 7208: 028a slli t0,t0,0x2 - 720a: fd16 fsw ft5,184(sp) - 720c: 0000 unimp - 720e: 7000 flw fs0,32(s0) - 7210: 0001bf17 auipc t5,0x1b - 7214: 0400 addi s0,sp,512 - 7216: fd16028b 0xfd16028b - 721a: 0000 unimp - 721c: 7800 flw fs0,48(s0) - 721e: 0006da17 auipc s4,0x6d - 7222: 0400 addi s0,sp,512 - 7224: 028c addi a1,sp,320 - 7226: 1310 addi a2,sp,416 - 7228: 0008 0x8 - 722a: 8000 0x8000 - 722c: 0003aa17 auipc s4,0x3a - 7230: 0400 addi s0,sp,512 - 7232: 028d addi t0,t0,3 - 7234: 2310 fld fa2,0(a4) - 7236: 0008 0x8 - 7238: 8800 0x8800 - 723a: 00004817 auipc a6,0x4 - 723e: 0400 addi s0,sp,512 - 7240: 028e slli t0,t0,0x3 - 7242: 00001d0f 0x1d0f - 7246: a000 fsd fs0,0(s0) - 7248: 00025117 auipc sp,0x25 - 724c: 0400 addi s0,sp,512 - 724e: fd16028f 0xfd16028f - 7252: 0000 unimp - 7254: a400 fsd fs0,8(s0) - 7256: 0000be17 auipc t3,0xb - 725a: 0400 addi s0,sp,512 - 725c: 0290 addi a2,sp,320 - 725e: fd16 fsw ft5,184(sp) - 7260: 0000 unimp - 7262: ac00 fsd fs0,24(s0) - 7264: 00024017 auipc zero,0x24 - 7268: 0400 addi s0,sp,512 - 726a: 0291 addi t0,t0,4 - 726c: fd16 fsw ft5,184(sp) - 726e: 0000 unimp - 7270: b400 fsd fs0,40(s0) - 7272: 00005b17 auipc s6,0x5 - 7276: 0400 addi s0,sp,512 - 7278: 0292 slli t0,t0,0x4 - 727a: fd16 fsw ft5,184(sp) - 727c: 0000 unimp - 727e: bc00 fsd fs0,56(s0) - 7280: 00006a17 auipc s4,0x6 - 7284: 0400 addi s0,sp,512 - 7286: fd160293 addi t0,a2,-47 # 4217f <_start-0x7ffbde81> - 728a: 0000 unimp - 728c: c400 sw s0,8(s0) - 728e: 00054e17 auipc t3,0x54 - 7292: 0400 addi s0,sp,512 - 7294: 0294 addi a3,sp,320 - 7296: 1d08 addi a0,sp,688 - 7298: 0000 unimp - 729a: cc00 sw s0,24(s0) - 729c: 0800 addi s0,sp,16 - 729e: 05b4 addi a3,sp,712 - 72a0: 0000 unimp - 72a2: 00000813 li a6,0 - 72a6: 2409 jal 74a8 <_start-0x7fff8b58> - 72a8: 0000 unimp - 72aa: 1900 addi s0,sp,176 - 72ac: 0800 addi s0,sp,16 - 72ae: 05b4 addi a3,sp,712 - 72b0: 0000 unimp - 72b2: 00000823 sb zero,16(zero) # 10 <_start-0x7ffffff0> - 72b6: 2409 jal 74b8 <_start-0x7fff8b48> - 72b8: 0000 unimp - 72ba: 0700 addi s0,sp,896 - 72bc: 0800 addi s0,sp,16 - 72be: 05b4 addi a3,sp,712 - 72c0: 0000 unimp - 72c2: 00000833 add a6,zero,zero - 72c6: 2409 jal 74c8 <_start-0x7fff8b38> - 72c8: 0000 unimp - 72ca: 1700 addi s0,sp,928 - 72cc: 1a00 addi s0,sp,304 - 72ce: 04f0 addi a2,sp,588 - 72d0: 0299 addi t0,t0,6 - 72d2: 00085a07 vlhu.v v20,(a6),v0.t - 72d6: 1700 addi s0,sp,928 - 72d8: 0476 slli s0,s0,0x1d - 72da: 0000 unimp - 72dc: 9c04 0x9c04 - 72de: 1b02 slli s6,s6,0x20 - 72e0: 085a slli a6,a6,0x16 - 72e2: 0000 unimp - 72e4: 1700 addi s0,sp,928 - 72e6: 0296 slli t0,t0,0x5 - 72e8: 0000 unimp - 72ea: 9d04 0x9d04 - 72ec: 1802 slli a6,a6,0x20 - 72ee: 086a slli a6,a6,0x1a - 72f0: 0000 unimp - 72f2: 0078 addi a4,sp,12 - 72f4: f308 fsw fa0,32(a4) - 72f6: 0002 c.slli64 zero - 72f8: 6a00 flw fs0,16(a2) - 72fa: 0008 0x8 - 72fc: 0900 addi s0,sp,144 - 72fe: 0024 addi s1,sp,8 - 7300: 0000 unimp - 7302: 001d c.nop 7 - 7304: 2408 fld fa0,8(s0) - 7306: 0000 unimp - 7308: 7a00 flw fs0,48(a2) - 730a: 0008 0x8 - 730c: 0900 addi s0,sp,144 - 730e: 0024 addi s1,sp,8 - 7310: 0000 unimp - 7312: 001d c.nop 7 - 7314: 7e04f01b 0x7e04f01b - 7318: 0302 c.slli64 t1 - 731a: 089f 0000 d11c 0xd11c0000089f - 7320: 0005 c.nop 1 - 7322: 0400 addi s0,sp,512 - 7324: 0295 addi t0,t0,5 - 7326: 0006ee0b 0x6ee0b - 732a: 1c00 addi s0,sp,560 - 732c: 00000703 lb a4,0(zero) # 0 <_start-0x80000000> - 7330: 9e04 0x9e04 - 7332: 0b02 c.slli64 s6 - 7334: 00000833 add a6,zero,zero - 7338: 0800 addi s0,sp,16 - 733a: 05b4 addi a3,sp,712 - 733c: 0000 unimp - 733e: 000008af 0x8af - 7342: 2409 jal 7544 <_start-0x7fff8abc> - 7344: 0000 unimp - 7346: 1800 addi s0,sp,48 - 7348: 1d00 addi s0,sp,688 - 734a: 000000b3 add ra,zero,zero - 734e: 08af040f 0x8af040f - 7352: 0000 unimp - 7354: c51e sw t2,136(sp) - 7356: 0008 0x8 - 7358: 1400 addi s0,sp,544 - 735a: 045a slli s0,s0,0x16 - 735c: 0000 unimp - 735e: 0f00 addi s0,sp,912 - 7360: ba04 fsd fs1,48(a2) - 7362: 0008 0x8 - 7364: 0f00 addi s0,sp,912 - 7366: 7d04 flw fs1,56(a0) - 7368: 0001 nop - 736a: 1e00 addi s0,sp,816 - 736c: 08dc addi a5,sp,84 - 736e: 0000 unimp - 7370: 1d14 addi a3,sp,688 - 7372: 0000 unimp - 7374: 0000 unimp - 7376: 08e2040f 0x8e2040f - 737a: 0000 unimp - 737c: 08d1040f 0x8d1040f - 7380: 0000 unimp - 7382: 5308 lw a0,32(a4) - 7384: 0006 c.slli zero,0x1 - 7386: f800 fsw fs0,48(s0) - 7388: 0008 0x8 - 738a: 0900 addi s0,sp,144 - 738c: 0024 addi s1,sp,8 - 738e: 0000 unimp - 7390: 0002 c.slli64 zero - 7392: 9e1f 0006 0400 0x40000069e1f - 7398: 032e slli t1,t1,0xb - 739a: 00045a17 auipc s4,0x45 - 739e: 1f00 addi s0,sp,944 - 73a0: 00000697 auipc a3,0x0 - 73a4: 2f04 fld fs1,24(a4) - 73a6: 04601d03 lh s10,70(zero) # 46 <_start-0x7fffffba> - 73aa: 0000 unimp - 73ac: ea08 fsw fa0,16(a2) - 73ae: 0005 c.nop 1 - 73b0: 1d00 addi s0,sp,688 - 73b2: 0009 c.nop 2 - 73b4: 2000 fld fs0,0(s0) - 73b6: 1500 addi s0,sp,672 - 73b8: 0912 slli s2,s2,0x4 - 73ba: 0000 unimp - 73bc: 2b21 jal 78d4 <_start-0x7fff872c> - 73be: 0002 c.slli64 zero - 73c0: 0500 addi s0,sp,640 - 73c2: 2414 fld fa3,8(s0) - 73c4: 091d addi s2,s2,7 - 73c6: 0000 unimp - 73c8: 9421 srai s0,s0,0x28 - 73ca: 0005 c.nop 1 - 73cc: 0500 addi s0,sp,640 - 73ce: 1515 addi a0,a0,-27 - 73d0: 001d c.nop 7 - 73d2: 0000 unimp - 73d4: 0940040f 0x940040f - 73d8: 0000 unimp - 73da: 00001d13 slli s10,zero,0x0 - 73de: 5400 lw s0,40(s0) - 73e0: 0009 c.nop 2 - 73e2: 1400 addi s0,sp,544 - 73e4: 0954 addi a3,sp,148 - 73e6: 0000 unimp - 73e8: 5414 lw a3,40(s0) - 73ea: 0009 c.nop 2 - 73ec: 0000 unimp - 73ee: 095a040f 0x95a040f - 73f2: 0000 unimp - 73f4: 2122 fld ft2,8(sp) - 73f6: 049c addi a5,sp,576 - 73f8: 0000 unimp - 73fa: 6706 flw fa4,64(sp) - 73fc: ae0e fsd ft3,280(sp) - 73fe: 0005 c.nop 1 - 7400: 2100 fld fs0,0(a0) - 7402: 03dc addi a5,sp,452 - 7404: 0000 unimp - 7406: 730f1007 0x730f1007 - 740a: 0009 c.nop 2 - 740c: 0f00 addi s0,sp,912 - 740e: ae04 fsd fs1,24(a2) - 7410: 0005 c.nop 1 - 7412: 2100 fld fs0,0(a0) - 7414: 049f 0000 fc07 0xfc070000049f - 741a: ae0e fsd ft3,280(sp) - 741c: 0005 c.nop 1 - 741e: 2100 fld fs0,0(a0) - 7420: 008e slli ra,ra,0x3 - 7422: 0000 unimp - 7424: 1d0cfd07 0x1d0cfd07 - 7428: 0000 unimp - 742a: 2100 fld fs0,0(a0) - 742c: 0634 addi a3,sp,776 - 742e: 0000 unimp - 7430: 1d14fd07 0x1d14fd07 - 7434: 0000 unimp - 7436: 2100 fld fs0,0(a0) - 7438: 00000747 fmsub.s fa4,ft0,ft0,ft0,rne - 743c: 1d1cfd07 0x1d1cfd07 - 7440: 0000 unimp - 7442: 2100 fld fs0,0(a0) - 7444: 0000041b 0x41b - 7448: 1d0cff07 0x1d0cff07 - 744c: 0000 unimp - 744e: 2100 fld fs0,0(a0) - 7450: 04cc addi a1,sp,580 - 7452: 0000 unimp - 7454: 9a08 0x9a08 - 7456: 5516 lw a0,100(sp) - 7458: 0000 unimp - 745a: 2100 fld fs0,0(a0) - 745c: 0000002f 0x2f - 7460: 9b08 0x9b08 - 7462: 1d15 addi s10,s10,-27 - 7464: 0000 unimp - 7466: 0800 addi s0,sp,16 - 7468: 05ae slli a1,a1,0xb - 746a: 0000 unimp - 746c: 09dd addi s3,s3,23 - 746e: 0000 unimp - 7470: 2409 jal 7672 <_start-0x7fff898e> - 7472: 0000 unimp - 7474: 0100 addi s0,sp,128 - 7476: 2100 fld fs0,0(a0) - 7478: 00cd addi ra,ra,19 - 747a: 0000 unimp - 747c: 9e08 0x9e08 - 747e: 0009cd17 auipc s10,0x9c - 7482: 0400 addi s0,sp,512 - 7484: 02ea slli t0,t0,0x1a - 7486: 0000 unimp - 7488: 2a09 jal 759a <_start-0x7fff8a66> - 748a: 2416 fld fs0,320(sp) - 748c: 0000 unimp - 748e: 0400 addi s0,sp,512 - 7490: 0582 c.slli64 a1 - 7492: 0000 unimp - 7494: 2f09 jal 7ba6 <_start-0x7fff845a> - 7496: 0115 addi sp,sp,5 - 7498: 000a c.slli zero,0x2 - 749a: 0f00 addi s0,sp,912 - 749c: 0704 addi s1,sp,896 - 749e: 000a c.slli zero,0x2 - 74a0: 1300 addi s0,sp,416 - 74a2: 09e9 addi s3,s3,26 - 74a4: 0000 unimp - 74a6: 0a16 slli s4,s4,0x5 - 74a8: 0000 unimp - 74aa: 5414 lw a3,40(s0) - 74ac: 0009 c.nop 2 - 74ae: 0000 unimp - 74b0: 9704 0x9704 - 74b2: 09000007 vlsbu.v v0,(zero),a6,v0.t - 74b6: 0f36 slli t5,t5,0xd - 74b8: 093a slli s2,s2,0xe - 74ba: 0000 unimp - 74bc: 0a21 addi s4,s4,8 - 74be: 0000 unimp - 74c0: 0900 addi s0,sp,144 - 74c2: 09f512bb 0x9f512bb - 74c6: 0000 unimp - 74c8: 8221 srli a2,a2,0x8 - 74ca: 0006 c.slli zero,0x1 - 74cc: 0900 addi s0,sp,144 - 74ce: 10be slli ra,ra,0x2f - 74d0: 0a16 slli s4,s4,0x5 - 74d2: 0000 unimp - 74d4: 0002bd23 0x2bd23 - 74d8: 0700 addi s0,sp,896 - 74da: 2404 fld fs1,8(s0) - 74dc: 0000 unimp - 74de: 0a00 addi s0,sp,272 - 74e0: 0618 addi a4,sp,768 - 74e2: 00000a77 0xa77 - 74e6: 2924 fld fs1,80(a0) - 74e8: 0005 c.nop 1 - 74ea: 0000 unimp - 74ec: f624 fsw fs1,104(a2) - 74ee: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 74f2: d124 sw s1,96(a0) - 74f4: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 74f8: 4a24 lw s1,80(a2) - 74fa: 0004 0x4 - 74fc: 0300 addi s0,sp,384 - 74fe: 2024 fld fs1,64(s0) - 7500: 0005 c.nop 1 - 7502: 0400 addi s0,sp,512 - 7504: 4e24 lw s1,88(a2) - 7506: 05000007 0x5000007 - 750a: 3d24 fld fs1,120(a0) - 750c: 06000007 0x6000007 - 7510: 2100 fld fs0,0(a0) - 7512: 00a9 addi ra,ra,10 - 7514: 0000 unimp - 7516: 210a fld ft2,128(sp) - 7518: 3a1c fld fa5,48(a2) - 751a: 000a c.slli zero,0x2 - 751c: 2300 fld fs0,0(a4) - 751e: 0455 addi s0,s0,21 - 7520: 0000 unimp - 7522: 00240407 0x240407 - 7526: 0000 unimp - 7528: 230a fld ft6,128(sp) - 752a: a806 fsd ft1,16(sp) - 752c: 000a c.slli zero,0x2 - 752e: 2400 fld fs0,8(s0) - 7530: 0578 addi a4,sp,652 - 7532: 0000 unimp - 7534: 2400 fld fs0,8(s0) - 7536: 0000053f 06572401 0x65724010000053f - 753e: 0000 unimp - 7540: 0002 c.slli64 zero - 7542: 5f21 li t5,-24 - 7544: 0002 c.slli64 zero - 7546: 0a00 addi s0,sp,272 - 7548: 1e28 addi a0,sp,824 - 754a: 00000a83 lb s5,0(zero) # 0 <_start-0x80000000> - 754e: 0c21 addi s8,s8,8 - 7550: 0004 0x4 - 7552: 0b00 addi s0,sp,400 - 7554: 1a29 addi s4,s4,-22 - 7556: 091d addi s2,s2,7 - 7558: 0000 unimp - 755a: 1e21 addi t3,t3,-24 - 755c: 0006 c.slli zero,0x1 - 755e: 0b00 addi s0,sp,400 - 7560: 1a38 addi a4,sp,312 - 7562: 091d addi s2,s2,7 - 7564: 0000 unimp - 7566: 7304 flw fs1,32(a4) - 7568: 0c000007 vlxbu.v v0,(zero),v0,v0.t - 756c: 0040167b 0x40167b - 7570: 0000 unimp - 7572: cc15 beqz s0,75ae <_start-0x7fff8a52> - 7574: 000a c.slli zero,0x2 - 7576: 0300 addi s0,sp,384 - 7578: 0404 addi s1,sp,512 - 757a: 0485 addi s1,s1,1 - 757c: 0000 unimp - 757e: 7d030803 lb a6,2000(t1) # 20994 <_start-0x7ffdf66c> - 7582: 0004 0x4 - 7584: 0300 addi s0,sp,384 - 7586: 0408 addi a0,sp,512 - 7588: 00a2 slli ra,ra,0x8 - 758a: 0000 unimp - 758c: 39031003 lh zero,912(t1) - 7590: 0000 unimp - 7592: 0300 addi s0,sp,384 - 7594: 0320 addi s0,sp,392 - 7596: 0095 addi ra,ra,5 - 7598: 0000 unimp - 759a: d808 sw a0,48(s0) - 759c: 000a c.slli zero,0x2 - 759e: 1000 addi s0,sp,32 - 75a0: 0900000b 0x900000b - 75a4: 0024 addi s1,sp,8 - 75a6: 0000 unimp - 75a8: 00ff 0xff - 75aa: 0015 c.nop 5 - 75ac: 1f00000b 0x1f00000b - 75b0: 06ee slli a3,a3,0x1b - 75b2: 0000 unimp - 75b4: fc0c fsw fa1,56(s0) - 75b6: 1601 addi a2,a2,-32 - 75b8: 0b10 addi a2,sp,400 - 75ba: 0000 unimp - 75bc: 971f 0003 0c00 0xc000003971f - 75c2: 0202 c.slli64 tp - 75c4: 1016 c.slli zero,0x25 - 75c6: 2500000b 0x2500000b - 75ca: 0b22 slli s6,s6,0x8 - 75cc: 0000 unimp - 75ce: b20d j 6ef0 <_start-0x7fff9110> - 75d0: 0f02 c.slli64 t5 - 75d2: 0305 addi t1,t1,1 - 75d4: 5224 lw s1,96(a2) - 75d6: 8001 c.srli64 s0 - 75d8: a800 fsd fs0,16(s0) - 75da: 0400000b 0x400000b - 75de: a900 fsd fs0,16(a0) - 75e0: 0019 c.nop 6 - 75e2: 0400 addi s0,sp,512 - 75e4: f201 bnez a2,74e4 <_start-0x7fff8b1c> - 75e6: 0c000007 vlxbu.v v0,(zero),v0,v0.t - 75ea: 04f9 addi s1,s1,30 - 75ec: 0000 unimp - 75ee: 02fc addi a5,sp,332 - 75f0: 0000 unimp - 75f2: 44fc lw a5,76(s1) - 75f4: 8001 c.srli64 s0 - 75f6: 004c addi a1,sp,4 - 75f8: 0000 unimp - 75fa: 8794 0x8794 - 75fc: 0000 unimp - 75fe: 0402 c.slli64 s0 - 7600: 6905 lui s2,0x1 - 7602: 746e flw fs0,248(sp) - 7604: 0300 addi s0,sp,384 - 7606: 0704 addi s1,sp,896 - 7608: 036e slli t1,t1,0x1b - 760a: 0000 unimp - 760c: 1d050803 lb a6,464(a0) - 7610: 0002 c.slli64 zero - 7612: 0300 addi s0,sp,384 - 7614: 0410 addi a2,sp,512 - 7616: 009d addi ra,ra,7 - 7618: 0000 unimp - 761a: 69060103 lb sp,1680(a2) - 761e: 0006 c.slli zero,0x1 - 7620: 0300 addi s0,sp,384 - 7622: 0801 addi a6,a6,0 - 7624: 00000667 jalr a2,zero # 0 <_start-0x80000000> - 7628: 00050203 lb tp,0(a0) - 762c: 0000 unimp - 762e: 0300 addi s0,sp,384 - 7630: 0702 c.slli64 a4 - 7632: 0384 addi s1,sp,448 - 7634: 0000 unimp - 7636: 22050403 lb s0,544(a0) - 763a: 0002 c.slli64 zero - 763c: 0300 addi s0,sp,384 - 763e: 0704 addi s1,sp,896 - 7640: 0369 addi t1,t1,26 - 7642: 0000 unimp - 7644: 64070803 lb a6,1600(a4) # 2f80a <_start-0x7ffd07f6> - 7648: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - 764c: 04e1 addi s1,s1,24 - 764e: 0000 unimp - 7650: 0c02 c.slli64 s8 - 7652: 250d jal 7c74 <_start-0x7fff838c> - 7654: 0000 unimp - 7656: 0400 addi s0,sp,512 - 7658: 04b1 addi s1,s1,12 - 765a: 0000 unimp - 765c: 5d0e2c03 lw s8,1488(t3) # 5b85e <_start-0x7ffa47a2> - 7660: 0000 unimp - 7662: 0400 addi s0,sp,512 - 7664: 05fa slli a1,a1,0x1e - 7666: 0000 unimp - 7668: 5d0e7203 0x5d0e7203 - 766c: 0000 unimp - 766e: 0400 addi s0,sp,512 - 7670: 06d1 addi a3,a3,20 - 7672: 0000 unimp - 7674: 25179103 lh sp,593(a5) - 7678: 0000 unimp - 767a: 0500 addi s0,sp,640 - 767c: 03e4 addi s1,sp,460 - 767e: 0000 unimp - 7680: 6504 flw fs1,8(a0) - 7682: 1701 addi a4,a4,-32 - 7684: 002c addi a1,sp,8 - 7686: 0000 unimp - 7688: 0406 slli s0,s0,0x1 - 768a: d103a603 lw a2,-752(t2) - 768e: 0000 unimp - 7690: 0700 addi s0,sp,896 - 7692: 000003cb fnmsub.s ft7,ft0,ft0,ft0,rne - 7696: a20ca803 lw a6,-1504(s9) - 769a: 0000 unimp - 769c: 0700 addi s0,sp,896 - 769e: 02d5 addi t0,t0,21 - 76a0: 0000 unimp - 76a2: d113a903 lw s2,-751(t2) - 76a6: 0000 unimp - 76a8: 0000 unimp - 76aa: 4808 lw a0,16(s0) - 76ac: 0000 unimp - 76ae: e100 fsw fs0,0(a0) - 76b0: 0000 unimp - 76b2: 0900 addi s0,sp,144 - 76b4: 002c addi a1,sp,8 - 76b6: 0000 unimp - 76b8: 080a0003 lb zero,128(s4) # 4c41a <_start-0x7ffb3be6> - 76bc: 0509a303 lw t1,80(s3) # ffff6050 <__BSS_END__+0x7ffdf2d8> - 76c0: 0001 nop - 76c2: 0b00 addi s0,sp,400 - 76c4: 0435 addi s0,s0,13 - 76c6: 0000 unimp - 76c8: 2507a503 lw a0,592(a5) - 76cc: 0000 unimp - 76ce: 0000 unimp - 76d0: 0005ec0b 0x5ec0b - 76d4: 0300 addi s0,sp,384 - 76d6: 05aa slli a1,a1,0xa - 76d8: 000000af 0xaf - 76dc: 0004 0x4 - 76de: d604 sw s1,40(a2) - 76e0: 0004 0x4 - 76e2: 0300 addi s0,sp,384 - 76e4: 00e103ab 0xe103ab - 76e8: 0000 unimp - 76ea: 5704 lw s1,40(a4) - 76ec: 0005 c.nop 1 - 76ee: 0300 addi s0,sp,384 - 76f0: 00721baf 0x721baf - 76f4: 0000 unimp - 76f6: 040c addi a1,sp,512 - 76f8: 7a04 flw fs1,48(a2) - 76fa: 0006 c.slli zero,0x1 - 76fc: 0500 addi s0,sp,640 - 76fe: 1916 slli s2,s2,0x25 - 7700: 0064 addi s1,sp,12 - 7702: 0000 unimp - 7704: 6e0d lui t3,0x3 - 7706: 0004 0x4 - 7708: 1800 addi s0,sp,48 - 770a: 2f05 jal 7e3a <_start-0x7fff81c6> - 770c: 8508 0x8508 - 770e: 0001 nop - 7710: 0b00 addi s0,sp,400 - 7712: 0791 addi a5,a5,4 - 7714: 0000 unimp - 7716: 3105 jal 7336 <_start-0x7fff8cca> - 7718: 00018513 mv a0,gp - 771c: 0000 unimp - 771e: 5f0e lw t5,224(sp) - 7720: 3205006b 0x3205006b - 7724: 00002507 flw fa0,0(zero) # 0 <_start-0x80000000> - 7728: 0400 addi s0,sp,512 - 772a: 0005c90b 0x5c90b - 772e: 0500 addi s0,sp,640 - 7730: 0b32 slli s6,s6,0xc - 7732: 0025 c.nop 9 - 7734: 0000 unimp - 7736: 0b08 addi a0,sp,400 - 7738: 0279 addi tp,tp,30 - 773a: 0000 unimp - 773c: 3205 jal 705c <_start-0x7fff8fa4> - 773e: 2514 fld fa3,8(a0) - 7740: 0000 unimp - 7742: 0c00 addi s0,sp,528 - 7744: 0001ff0b 0x1ff0b - 7748: 0500 addi s0,sp,640 - 774a: 1b32 slli s6,s6,0x2c - 774c: 0025 c.nop 9 - 774e: 0000 unimp - 7750: 0e10 addi a2,sp,784 - 7752: 785f 0500 0b33 0xb330500785f - 7758: 0000018b 0x18b - 775c: 0014 0x14 - 775e: 012b040f 0x12b040f - 7762: 0000 unimp - 7764: 1f08 addi a0,sp,944 - 7766: 0001 nop - 7768: 9b00 0x9b00 - 776a: 0001 nop - 776c: 0900 addi s0,sp,144 - 776e: 002c addi a1,sp,8 - 7770: 0000 unimp - 7772: 0000 unimp - 7774: b80d j 6fa6 <_start-0x7fff905a> - 7776: 0002 c.slli64 zero - 7778: 2400 fld fs0,8(s0) - 777a: 3705 jal 769a <_start-0x7fff8966> - 777c: 1e08 addi a0,sp,816 - 777e: 0002 c.slli64 zero - 7780: 0b00 addi s0,sp,400 - 7782: 00d5 addi ra,ra,21 - 7784: 0000 unimp - 7786: 3905 jal 73b6 <_start-0x7fff8c4a> - 7788: 2509 jal 7d8a <_start-0x7fff8276> - 778a: 0000 unimp - 778c: 0000 unimp - 778e: 00072f0b 0x72f0b - 7792: 0500 addi s0,sp,640 - 7794: 093a slli s2,s2,0xe - 7796: 0025 c.nop 9 - 7798: 0000 unimp - 779a: 0b04 addi s1,sp,400 - 779c: 01b5 addi gp,gp,13 - 779e: 0000 unimp - 77a0: 3b05 jal 74d0 <_start-0x7fff8b30> - 77a2: 2509 jal 7da4 <_start-0x7fff825c> - 77a4: 0000 unimp - 77a6: 0800 addi s0,sp,16 - 77a8: 0007820b 0x7820b - 77ac: 0500 addi s0,sp,640 - 77ae: 093c addi a5,sp,152 - 77b0: 0025 c.nop 9 - 77b2: 0000 unimp - 77b4: 0b0c addi a1,sp,400 - 77b6: 0000048b 0x48b - 77ba: 3d05 jal 75ea <_start-0x7fff8a16> - 77bc: 2509 jal 7dbe <_start-0x7fff8242> - 77be: 0000 unimp - 77c0: 1000 addi s0,sp,32 - 77c2: 00042b0b 0x42b0b - 77c6: 0500 addi s0,sp,640 - 77c8: 093e slli s2,s2,0xf - 77ca: 0025 c.nop 9 - 77cc: 0000 unimp - 77ce: 0b14 addi a3,sp,400 - 77d0: 06ba slli a3,a3,0xe - 77d2: 0000 unimp - 77d4: 3f05 jal 7704 <_start-0x7fff88fc> - 77d6: 2509 jal 7dd8 <_start-0x7fff8228> - 77d8: 0000 unimp - 77da: 1800 addi s0,sp,48 - 77dc: 0005600b 0x5600b - 77e0: 0500 addi s0,sp,640 - 77e2: 0940 addi s0,sp,148 - 77e4: 0025 c.nop 9 - 77e6: 0000 unimp - 77e8: 0b1c addi a5,sp,400 - 77ea: 0715 addi a4,a4,5 - 77ec: 0000 unimp - 77ee: 4105 li sp,1 - 77f0: 2509 jal 7df2 <_start-0x7fff820e> - 77f2: 0000 unimp - 77f4: 2000 fld fs0,0(s0) - 77f6: 1000 addi s0,sp,32 - 77f8: 01d2 slli gp,gp,0x14 - 77fa: 0000 unimp - 77fc: 0108 addi a0,sp,128 - 77fe: 4a05 li s4,1 - 7800: 6308 flw fa0,0(a4) - 7802: 0002 c.slli64 zero - 7804: 0b00 addi s0,sp,400 - 7806: 026c addi a1,sp,268 - 7808: 0000 unimp - 780a: 4b05 li s6,1 - 780c: 630a flw ft6,128(sp) - 780e: 0002 c.slli64 zero - 7810: 0000 unimp - 7812: 0005330b 0x5330b - 7816: 0500 addi s0,sp,640 - 7818: 094c addi a1,sp,148 - 781a: 00000263 beqz zero,781e <_start-0x7fff87e2> - 781e: 1180 addi s0,sp,224 - 7820: 065e slli a2,a2,0x17 - 7822: 0000 unimp - 7824: 4e05 li t3,1 - 7826: 1f0a slli t5,t5,0x22 - 7828: 0001 nop - 782a: 0000 unimp - 782c: 1101 addi sp,sp,-32 - 782e: 000001f7 0x1f7 - 7832: 5105 li sp,-31 - 7834: 1f0a slli t5,t5,0x22 - 7836: 0001 nop - 7838: 0400 addi s0,sp,512 - 783a: 0001 nop - 783c: 1d08 addi a0,sp,688 - 783e: 0001 nop - 7840: 7300 flw fs0,32(a4) - 7842: 0002 c.slli64 zero - 7844: 0900 addi s0,sp,144 - 7846: 002c addi a1,sp,8 - 7848: 0000 unimp - 784a: 001f 9410 0004 0x49410001f - 7850: 9000 0x9000 - 7852: 0501 addi a0,a0,0 - 7854: 085d addi a6,a6,23 - 7856: 02b6 slli t0,t0,0xd - 7858: 0000 unimp - 785a: 0007910b 0x7910b - 785e: 0500 addi s0,sp,640 - 7860: 125e slli tp,tp,0x37 - 7862: 02b6 slli t0,t0,0xd - 7864: 0000 unimp - 7866: 0b00 addi s0,sp,400 - 7868: 05b0 addi a2,sp,712 - 786a: 0000 unimp - 786c: 5f05 li t5,-31 - 786e: 2506 fld fa0,64(sp) - 7870: 0000 unimp - 7872: 0400 addi s0,sp,512 - 7874: 0002740b 0x2740b - 7878: 0500 addi s0,sp,640 - 787a: 0961 addi s2,s2,24 - 787c: 02bc addi a5,sp,328 - 787e: 0000 unimp - 7880: 0b08 addi a0,sp,400 - 7882: 01d2 slli gp,gp,0x14 - 7884: 0000 unimp - 7886: 6205 lui tp,0x1 - 7888: 1e1e slli t3,t3,0x27 - 788a: 0002 c.slli64 zero - 788c: 8800 0x8800 - 788e: 0f00 addi s0,sp,912 - 7890: 7304 flw fs1,32(a4) - 7892: 0002 c.slli64 zero - 7894: 0800 addi s0,sp,16 - 7896: 02cc addi a1,sp,324 - 7898: 0000 unimp - 789a: 02cc addi a1,sp,324 - 789c: 0000 unimp - 789e: 2c09 jal 7ab0 <_start-0x7fff8550> - 78a0: 0000 unimp - 78a2: 1f00 addi s0,sp,944 - 78a4: 0f00 addi s0,sp,912 - 78a6: d204 sw s1,32(a2) - 78a8: 0002 c.slli64 zero - 78aa: 1200 addi s0,sp,288 - 78ac: 7b0d lui s6,0xfffe3 - 78ae: 08000007 vlsbu.v v0,(zero),zero,v0.t - 78b2: 7505 lui a0,0xfffe1 - 78b4: fb08 fsw fa0,48(a4) - 78b6: 0002 c.slli64 zero - 78b8: 0b00 addi s0,sp,400 - 78ba: 000001af 0x1af - 78be: 7605 lui a2,0xfffe1 - 78c0: fb11 bnez a4,77d4 <_start-0x7fff882c> - 78c2: 0002 c.slli64 zero - 78c4: 0000 unimp - 78c6: 00060b0b 0x60b0b - 78ca: 0500 addi s0,sp,640 - 78cc: 00250677 0x250677 - 78d0: 0000 unimp - 78d2: 0004 0x4 - 78d4: 0048040f 0x48040f - 78d8: 0000 unimp - 78da: 8c0d sub s0,s0,a1 - 78dc: 0005 c.nop 1 - 78de: 6800 flw fs0,16(s0) - 78e0: b505 j 7700 <_start-0x7fff8900> - 78e2: 4408 lw a0,8(s0) - 78e4: 0004 0x4 - 78e6: 0e00 addi s0,sp,784 - 78e8: 705f 0500 12b6 0x12b60500705f - 78ee: 000002fb 0x2fb - 78f2: 0e00 addi s0,sp,784 - 78f4: 725f 0500 07b7 0x7b70500725f - 78fa: 0025 c.nop 9 - 78fc: 0000 unimp - 78fe: 0e04 addi s1,sp,784 - 7900: 775f 0500 07b8 0x7b80500775f - 7906: 0025 c.nop 9 - 7908: 0000 unimp - 790a: 0b08 addi a0,sp,400 - 790c: 01f0 addi a2,sp,204 - 790e: 0000 unimp - 7910: b905 j 7540 <_start-0x7fff8ac0> - 7912: 4f09 li t5,2 - 7914: 0000 unimp - 7916: 0c00 addi s0,sp,528 - 7918: 0002e40b 0x2e40b - 791c: 0500 addi s0,sp,640 - 791e: 09ba slli s3,s3,0xe - 7920: 0000004f fnmadd.s ft0,ft0,ft0,ft0,rne - 7924: 0e0e slli t3,t3,0x3 - 7926: 625f 0066 bb05 0xbb050066625f - 792c: d311 beqz a4,7830 <_start-0x7fff87d0> - 792e: 0002 c.slli64 zero - 7930: 1000 addi s0,sp,32 - 7932: 0000850b 0x850b - 7936: 0500 addi s0,sp,640 - 7938: 07bc addi a5,sp,968 - 793a: 0025 c.nop 9 - 793c: 0000 unimp - 793e: 0b18 addi a4,sp,400 - 7940: 01e0 addi s0,sp,204 - 7942: 0000 unimp - 7944: c305 beqz a4,7964 <_start-0x7fff869c> - 7946: 1d0a slli s10,s10,0x22 - 7948: 0001 nop - 794a: 1c00 addi s0,sp,560 - 794c: 0004f30b 0x4f30b - 7950: 0500 addi s0,sp,640 - 7952: 1dc5 addi s11,s11,-15 - 7954: 05c8 addi a0,sp,708 - 7956: 0000 unimp - 7958: 0b20 addi s0,sp,408 - 795a: 0424 addi s1,sp,520 - 795c: 0000 unimp - 795e: c705 beqz a4,7986 <_start-0x7fff867a> - 7960: f71d bnez a4,788e <_start-0x7fff8772> - 7962: 0005 c.nop 1 - 7964: 2400 fld fs0,8(s0) - 7966: 0005f40b 0x5f40b - 796a: 0500 addi s0,sp,640 - 796c: 0dca slli s11,s11,0x12 - 796e: 0000061b 0x61b - 7972: 0b28 addi a0,sp,408 - 7974: 00de slli ra,ra,0x17 - 7976: 0000 unimp - 7978: cb05 beqz a4,79a8 <_start-0x7fff8658> - 797a: 3509 jal 777c <_start-0x7fff8884> - 797c: 0006 c.slli zero,0x1 - 797e: 2c00 fld fs0,24(s0) - 7980: 5f0e lw t5,224(sp) - 7982: 6275 lui tp,0x1d - 7984: 0500 addi s0,sp,640 - 7986: 11ce slli gp,gp,0x33 - 7988: 000002d3 fadd.s ft5,ft0,ft0,rne - 798c: 0e30 addi a2,sp,792 - 798e: 755f 0070 cf05 0xcf050070755f - 7994: fb12 fsw ft4,180(sp) - 7996: 0002 c.slli64 zero - 7998: 3800 fld fs0,48(s0) - 799a: 5f0e lw t5,224(sp) - 799c: 7275 lui tp,0xffffd - 799e: 0500 addi s0,sp,640 - 79a0: 07d0 addi a2,sp,964 - 79a2: 0025 c.nop 9 - 79a4: 0000 unimp - 79a6: 0b3c addi a5,sp,408 - 79a8: 01a9 addi gp,gp,10 - 79aa: 0000 unimp - 79ac: d305 beqz a4,78cc <_start-0x7fff8734> - 79ae: 3b11 jal 76c2 <_start-0x7fff893e> - 79b0: 0006 c.slli zero,0x1 - 79b2: 4000 lw s0,0(s0) - 79b4: 0006fd0b 0x6fd0b - 79b8: 0500 addi s0,sp,640 - 79ba: 11d4 addi a3,sp,228 - 79bc: 0000064b fnmsub.s fa2,ft0,ft0,ft0,rne - 79c0: 6c5f0e43 0x6c5f0e43 - 79c4: 0062 c.slli zero,0x18 - 79c6: d705 beqz a4,78ee <_start-0x7fff8712> - 79c8: d311 beqz a4,78cc <_start-0x7fff8734> - 79ca: 0002 c.slli64 zero - 79cc: 4400 lw s0,8(s0) - 79ce: 0006020b 0x6020b - 79d2: 0500 addi s0,sp,640 - 79d4: 07da slli a5,a5,0x16 - 79d6: 0025 c.nop 9 - 79d8: 0000 unimp - 79da: 0b4c addi a1,sp,404 - 79dc: 0466 slli s0,s0,0x19 - 79de: 0000 unimp - 79e0: db05 beqz a4,7910 <_start-0x7fff86f0> - 79e2: 7e0a flw ft8,160(sp) - 79e4: 0000 unimp - 79e6: 5000 lw s0,32(s0) - 79e8: 0000550b 0x550b - 79ec: 0500 addi s0,sp,640 - 79ee: 12de slli t0,t0,0x37 - 79f0: 0462 slli s0,s0,0x18 - 79f2: 0000 unimp - 79f4: 0b54 addi a3,sp,404 - 79f6: 000003eb 0x3eb - 79fa: e205 bnez a2,7a1a <_start-0x7fff85e6> - 79fc: 110c addi a1,sp,160 - 79fe: 0001 nop - 7a00: 5800 lw s0,48(s0) - 7a02: 0002cc0b 0x2cc0b - 7a06: 0500 addi s0,sp,640 - 7a08: 0ee4 addi s1,sp,860 - 7a0a: 0105 addi sp,sp,1 - 7a0c: 0000 unimp - 7a0e: 0b5c addi a5,sp,404 - 7a10: 056a slli a0,a0,0x1a - 7a12: 0000 unimp - 7a14: e505 bnez a0,7a3c <_start-0x7fff85c4> - 7a16: 2509 jal 8018 <_start-0x7fff7fe8> - 7a18: 0000 unimp - 7a1a: 6400 flw fs0,8(s0) - 7a1c: 1300 addi s0,sp,416 - 7a1e: 0096 slli ra,ra,0x5 - 7a20: 0000 unimp - 7a22: 0462 slli s0,s0,0x18 - 7a24: 0000 unimp - 7a26: 6214 flw fa3,0(a2) - 7a28: 0004 0x4 - 7a2a: 1400 addi s0,sp,544 - 7a2c: 011d addi sp,sp,7 - 7a2e: 0000 unimp - 7a30: b614 fsd fa3,40(a2) - 7a32: 0005 c.nop 1 - 7a34: 1400 addi s0,sp,544 - 7a36: 0025 c.nop 9 - 7a38: 0000 unimp - 7a3a: 0f00 addi s0,sp,912 - 7a3c: 6d04 flw fs1,24(a0) - 7a3e: 0004 0x4 - 7a40: 1500 addi s0,sp,672 - 7a42: 0462 slli s0,s0,0x18 - 7a44: 0000 unimp - 7a46: d116 sw t0,160(sp) - 7a48: 0005 c.nop 1 - 7a4a: 2800 fld fs0,16(s0) - 7a4c: 0504 addi s1,sp,640 - 7a4e: 0260 addi s0,sp,268 - 7a50: b608 fsd fa0,40(a2) - 7a52: 0005 c.nop 1 - 7a54: 1700 addi s0,sp,928 - 7a56: 0550 addi a2,sp,644 - 7a58: 0000 unimp - 7a5a: 6205 lui tp,0x1 - 7a5c: 0702 c.slli64 a4 - 7a5e: 0025 c.nop 9 - 7a60: 0000 unimp - 7a62: 1700 addi s0,sp,928 - 7a64: 06ca slli a3,a3,0x12 - 7a66: 0000 unimp - 7a68: 6705 lui a4,0x1 - 7a6a: 0b02 c.slli64 s6 - 7a6c: 000006a7 vsb.v v13,(zero),v0.t - 7a70: 1704 addi s1,sp,928 - 7a72: 06b2 slli a3,a3,0xc - 7a74: 0000 unimp - 7a76: 6705 lui a4,0x1 - 7a78: 1402 slli s0,s0,0x20 - 7a7a: 000006a7 vsb.v v13,(zero),v0.t - 7a7e: 1708 addi a0,sp,928 - 7a80: 027f 0x27f - 7a82: 0000 unimp - 7a84: 6705 lui a4,0x1 - 7a86: 1e02 slli t3,t3,0x20 - 7a88: 000006a7 vsb.v v13,(zero),v0.t - 7a8c: 170c addi a1,sp,928 - 7a8e: 000005ab 0x5ab - 7a92: 6905 lui s2,0x1 - 7a94: 0802 c.slli64 a6 - 7a96: 0025 c.nop 9 - 7a98: 0000 unimp - 7a9a: 1710 addi a2,sp,928 - 7a9c: 0024 addi s1,sp,8 - 7a9e: 0000 unimp - 7aa0: 6a05 lui s4,0x1 - 7aa2: 0802 c.slli64 a6 - 7aa4: 000008a7 vsb.v v17,(zero),v0.t - 7aa8: 1714 addi a3,sp,928 - 7aaa: 029f 0000 6d05 0x6d050000029f - 7ab0: 0702 c.slli64 a4 - 7ab2: 0025 c.nop 9 - 7ab4: 0000 unimp - 7ab6: 1730 addi a2,sp,936 - 7ab8: 0000076b 0x76b - 7abc: 6e05 lui t3,0x1 - 7abe: 1602 slli a2,a2,0x20 - 7ac0: 08bc addi a5,sp,88 - 7ac2: 0000 unimp - 7ac4: 1734 addi a3,sp,936 - 7ac6: 04a6 slli s1,s1,0x9 - 7ac8: 0000 unimp - 7aca: 7005 c.lui zero,0xfffe1 - 7acc: 0702 c.slli64 a4 - 7ace: 0025 c.nop 9 - 7ad0: 0000 unimp - 7ad2: 1738 addi a4,sp,936 - 7ad4: 000005bf 0a027205 0xa027205000005bf - 7adc: 08cd addi a7,a7,19 - 7ade: 0000 unimp - 7ae0: 173c addi a5,sp,936 - 7ae2: 000003c3 fmadd.s ft7,ft0,ft0,ft0,rne - 7ae6: 7505 lui a0,0xfffe1 - 7ae8: 1302 slli t1,t1,0x20 - 7aea: 0185 addi gp,gp,1 - 7aec: 0000 unimp - 7aee: 1740 addi s0,sp,932 - 7af0: 0000020b 0x20b - 7af4: 7605 lui a2,0xfffe1 - 7af6: 0702 c.slli64 a4 - 7af8: 0025 c.nop 9 - 7afa: 0000 unimp - 7afc: 1744 addi s1,sp,932 - 7afe: 0766 slli a4,a4,0x19 - 7b00: 0000 unimp - 7b02: 7705 lui a4,0xfffe1 - 7b04: 1302 slli t1,t1,0x20 - 7b06: 0185 addi gp,gp,1 - 7b08: 0000 unimp - 7b0a: 1748 addi a0,sp,932 - 7b0c: 04c2 slli s1,s1,0x10 - 7b0e: 0000 unimp - 7b10: 7805 lui a6,0xfffe1 - 7b12: 1402 slli s0,s0,0x20 - 7b14: 000008d3 fadd.s fa7,ft0,ft0,rne - 7b18: 174c addi a1,sp,932 - 7b1a: 02dc addi a5,sp,324 - 7b1c: 0000 unimp - 7b1e: 7b05 lui s6,0xfffe1 - 7b20: 0702 c.slli64 a4 - 7b22: 0025 c.nop 9 - 7b24: 0000 unimp - 7b26: 1750 addi a2,sp,932 - 7b28: 0238 addi a4,sp,264 - 7b2a: 0000 unimp - 7b2c: 7c05 lui s8,0xfffe1 - 7b2e: 0902 c.slli64 s2 - 7b30: 05b6 slli a1,a1,0xd - 7b32: 0000 unimp - 7b34: 1754 addi a3,sp,932 - 7b36: 0549 addi a0,a0,18 - 7b38: 0000 unimp - 7b3a: 9f05 0x9f05 - 7b3c: 0702 c.slli64 a4 - 7b3e: 0882 c.slli64 a7 - 7b40: 0000 unimp - 7b42: 1858 addi a4,sp,52 - 7b44: 0494 addi a3,sp,576 - 7b46: 0000 unimp - 7b48: a305 j 8068 <_start-0x7fff7f98> - 7b4a: 1302 slli t1,t1,0x20 - 7b4c: 02b6 slli t0,t0,0xd - 7b4e: 0000 unimp - 7b50: 0148 addi a0,sp,132 - 7b52: a118 fsd fa4,0(a0) - 7b54: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - 7b58: 02a4 addi s1,sp,328 - 7b5a: 7312 flw ft6,36(sp) - 7b5c: 0002 c.slli64 zero - 7b5e: 4c00 lw s0,24(s0) - 7b60: 1801 addi a6,a6,-32 - 7b62: 06e4 addi s1,sp,844 - 7b64: 0000 unimp - 7b66: a805 j 7b96 <_start-0x7fff846a> - 7b68: 0c02 c.slli64 s8 - 7b6a: 08e4 addi s1,sp,92 - 7b6c: 0000 unimp - 7b6e: 02dc addi a5,sp,324 - 7b70: e818 fsw fa4,16(s0) - 7b72: 0001 nop - 7b74: 0500 addi s0,sp,640 - 7b76: 02ad addi t0,t0,11 - 7b78: 6810 flw fa2,16(s0) - 7b7a: 0006 c.slli zero,0x1 - 7b7c: e000 fsw fs0,0(s0) - 7b7e: 1802 slli a6,a6,0x20 - 7b80: 01cd addi gp,gp,19 - 7b82: 0000 unimp - 7b84: af05 j 82b4 <_start-0x7fff7d4c> - 7b86: 0a02 c.slli64 s4 - 7b88: 08f0 addi a2,sp,92 - 7b8a: 0000 unimp - 7b8c: 02ec addi a1,sp,332 - 7b8e: 0f00 addi s0,sp,912 - 7b90: bc04 fsd fs1,56(s0) - 7b92: 0005 c.nop 1 - 7b94: 0300 addi s0,sp,384 - 7b96: 0801 addi a6,a6,0 - 7b98: 0670 addi a2,sp,780 - 7b9a: 0000 unimp - 7b9c: bc15 j 75d0 <_start-0x7fff8a30> - 7b9e: 0005 c.nop 1 - 7ba0: 0f00 addi s0,sp,912 - 7ba2: 4404 lw s1,8(s0) - 7ba4: 0004 0x4 - 7ba6: 1300 addi s0,sp,416 - 7ba8: 0096 slli ra,ra,0x5 - 7baa: 0000 unimp - 7bac: 05ec addi a1,sp,716 - 7bae: 0000 unimp - 7bb0: 6214 flw fa3,0(a2) - 7bb2: 0004 0x4 - 7bb4: 1400 addi s0,sp,544 - 7bb6: 011d addi sp,sp,7 - 7bb8: 0000 unimp - 7bba: ec14 fsw fa3,24(s0) - 7bbc: 0005 c.nop 1 - 7bbe: 1400 addi s0,sp,544 - 7bc0: 0025 c.nop 9 - 7bc2: 0000 unimp - 7bc4: 0f00 addi s0,sp,912 - 7bc6: c304 sw s1,0(a4) - 7bc8: 0005 c.nop 1 - 7bca: 1500 addi s0,sp,672 - 7bcc: 05ec addi a1,sp,716 - 7bce: 0000 unimp - 7bd0: 05ce040f 0x5ce040f - 7bd4: 0000 unimp - 7bd6: 00008a13 mv s4,ra - 7bda: 1b00 addi s0,sp,432 - 7bdc: 0006 c.slli zero,0x1 - 7bde: 1400 addi s0,sp,544 - 7be0: 0462 slli s0,s0,0x18 - 7be2: 0000 unimp - 7be4: 1d14 addi a3,sp,688 - 7be6: 0001 nop - 7be8: 1400 addi s0,sp,544 - 7bea: 008a slli ra,ra,0x2 - 7bec: 0000 unimp - 7bee: 2514 fld fa3,8(a0) - 7bf0: 0000 unimp - 7bf2: 0000 unimp - 7bf4: 05fd040f 0x5fd040f - 7bf8: 0000 unimp - 7bfa: 00002513 slti a0,zero,0 - 7bfe: 3500 fld fs0,40(a0) - 7c00: 0006 c.slli zero,0x1 - 7c02: 1400 addi s0,sp,544 - 7c04: 0462 slli s0,s0,0x18 - 7c06: 0000 unimp - 7c08: 1d14 addi a3,sp,688 - 7c0a: 0001 nop - 7c0c: 0000 unimp - 7c0e: 0621040f 0x621040f - 7c12: 0000 unimp - 7c14: 4808 lw a0,16(s0) - 7c16: 0000 unimp - 7c18: 4b00 lw s0,16(a4) - 7c1a: 0006 c.slli zero,0x1 - 7c1c: 0900 addi s0,sp,144 - 7c1e: 002c addi a1,sp,8 - 7c20: 0000 unimp - 7c22: 0002 c.slli64 zero - 7c24: 4808 lw a0,16(s0) - 7c26: 0000 unimp - 7c28: 5b00 lw s0,48(a4) - 7c2a: 0006 c.slli zero,0x1 - 7c2c: 0900 addi s0,sp,144 - 7c2e: 002c addi a1,sp,8 - 7c30: 0000 unimp - 7c32: 0000 unimp - 7c34: 0405 addi s0,s0,1 - 7c36: 0002 c.slli64 zero - 7c38: 0500 addi s0,sp,640 - 7c3a: 011f 011a 0003 0x3011a011f - 7c40: 1900 addi s0,sp,176 - 7c42: 06c4 addi s1,sp,836 - 7c44: 0000 unimp - 7c46: 050c addi a1,sp,640 - 7c48: a1080123 sb a6,-1534(a6) # fffe0a02 <__BSS_END__+0x7ffc9c8a> - 7c4c: 0006 c.slli zero,0x1 - 7c4e: 1700 addi s0,sp,928 - 7c50: 0791 addi a5,a5,4 - 7c52: 0000 unimp - 7c54: 2505 jal 8274 <_start-0x7fff7d8c> - 7c56: 1101 addi sp,sp,-32 - 7c58: 06a1 addi a3,a3,8 - 7c5a: 0000 unimp - 7c5c: 1700 addi s0,sp,928 - 7c5e: 035d addi t1,t1,23 - 7c60: 0000 unimp - 7c62: 2605 jal 7f82 <_start-0x7fff807e> - 7c64: 0701 addi a4,a4,0 - 7c66: 0025 c.nop 9 - 7c68: 0000 unimp - 7c6a: 1704 addi s1,sp,928 - 7c6c: 0572 slli a0,a0,0x1c - 7c6e: 0000 unimp - 7c70: 2705 jal 8390 <_start-0x7fff7c70> - 7c72: 0b01 addi s6,s6,0 - 7c74: 000006a7 vsb.v v13,(zero),v0.t - 7c78: 0008 0x8 - 7c7a: 0668040f 0x668040f - 7c7e: 0000 unimp - 7c80: 065b040f 0x65b040f - 7c84: 0000 unimp - 7c86: 1c19 addi s8,s8,-26 - 7c88: 0000 unimp - 7c8a: 0e00 addi s0,sp,784 - 7c8c: 3f05 jal 7bbc <_start-0x7fff8444> - 7c8e: 0801 addi a6,a6,0 - 7c90: 06e6 slli a3,a3,0x19 - 7c92: 0000 unimp - 7c94: 00062e17 auipc t3,0x62 - 7c98: 0500 addi s0,sp,640 - 7c9a: 0140 addi s0,sp,132 - 7c9c: e612 fsw ft4,12(sp) - 7c9e: 0006 c.slli zero,0x1 - 7ca0: 0000 unimp - 7ca2: 00040117 auipc sp,0x40 - 7ca6: 0500 addi s0,sp,640 - 7ca8: 0141 addi sp,sp,16 - 7caa: e612 fsw ft4,12(sp) - 7cac: 0006 c.slli zero,0x1 - 7cae: 0600 addi s0,sp,768 - 7cb0: 00067517 auipc a0,0x67 - 7cb4: 0500 addi s0,sp,640 - 7cb6: 0142 slli sp,sp,0x10 - 7cb8: 5612 lw a2,36(sp) - 7cba: 0000 unimp - 7cbc: 0c00 addi s0,sp,528 - 7cbe: 0800 addi s0,sp,16 - 7cc0: 0056 c.slli zero,0x15 - 7cc2: 0000 unimp - 7cc4: 06f6 slli a3,a3,0x1d - 7cc6: 0000 unimp - 7cc8: 2c09 jal 7eda <_start-0x7fff8126> - 7cca: 0000 unimp - 7ccc: 0200 addi s0,sp,256 - 7cce: 1a00 addi s0,sp,304 - 7cd0: 05d0 addi a2,sp,708 - 7cd2: 0280 addi s0,sp,320 - 7cd4: 00080b07 vlbu.v v22,(a6),v0.t - 7cd8: 1700 addi s0,sp,928 - 7cda: 043d addi s0,s0,15 - 7cdc: 0000 unimp - 7cde: 8205 srli a2,a2,0x1 - 7ce0: 1802 slli a6,a6,0x20 - 7ce2: 002c addi a1,sp,8 - 7ce4: 0000 unimp - 7ce6: 1700 addi s0,sp,928 - 7ce8: 064a slli a2,a2,0x12 - 7cea: 0000 unimp - 7cec: 8305 srli a4,a4,0x1 - 7cee: 1202 slli tp,tp,0x20 - 7cf0: 05b6 slli a1,a1,0xd - 7cf2: 0000 unimp - 7cf4: 1704 addi s1,sp,928 - 7cf6: 03b6 slli t2,t2,0xd - 7cf8: 0000 unimp - 7cfa: 8405 srai s0,s0,0x1 - 7cfc: 1002 c.slli zero,0x20 - 7cfe: 0000080b 0x80b - 7d02: 1708 addi a0,sp,928 - 7d04: 0720 addi s0,sp,904 - 7d06: 0000 unimp - 7d08: 8505 srai a0,a0,0x1 - 7d0a: 1702 slli a4,a4,0x20 - 7d0c: 0000019b 0x19b - 7d10: 1724 addi s1,sp,936 - 7d12: 00000287 vlbu.v v5,(zero),v0.t - 7d16: 8605 srai a2,a2,0x1 - 7d18: 0f02 c.slli64 t5 - 7d1a: 0025 c.nop 9 - 7d1c: 0000 unimp - 7d1e: 1748 addi a0,sp,932 - 7d20: 078c addi a1,sp,960 - 7d22: 0000 unimp - 7d24: 8705 srai a4,a4,0x1 - 7d26: 2c02 fld fs8,0(sp) - 7d28: 0000006b 0x6b - 7d2c: 1750 addi a2,sp,932 - 7d2e: 0738 addi a4,sp,904 - 7d30: 0000 unimp - 7d32: 8805 andi s0,s0,1 - 7d34: 1a02 slli s4,s4,0x20 - 7d36: 06ad addi a3,a3,11 - 7d38: 0000 unimp - 7d3a: 1758 addi a4,sp,932 - 7d3c: 059e slli a1,a1,0x7 - 7d3e: 0000 unimp - 7d40: 8905 andi a0,a0,1 - 7d42: 1602 slli a2,a2,0x20 - 7d44: 0105 addi sp,sp,1 - 7d46: 0000 unimp - 7d48: 1768 addi a0,sp,940 - 7d4a: 0758 addi a4,sp,900 - 7d4c: 0000 unimp - 7d4e: 8a05 andi a2,a2,1 - 7d50: 1602 slli a2,a2,0x20 - 7d52: 0105 addi sp,sp,1 - 7d54: 0000 unimp - 7d56: 1770 addi a2,sp,940 - 7d58: 000001bf 16028b05 0x16028b05000001bf - 7d60: 0105 addi sp,sp,1 - 7d62: 0000 unimp - 7d64: 1778 addi a4,sp,940 - 7d66: 06da slli a3,a3,0x16 - 7d68: 0000 unimp - 7d6a: 8c05 sub s0,s0,s1 - 7d6c: 1002 c.slli zero,0x20 - 7d6e: 0000081b 0x81b - 7d72: 1780 addi s0,sp,992 - 7d74: 03aa slli t2,t2,0xa - 7d76: 0000 unimp - 7d78: 8d05 sub a0,a0,s1 - 7d7a: 1002 c.slli zero,0x20 - 7d7c: 0000082b 0x82b - 7d80: 1788 addi a0,sp,992 - 7d82: 0048 addi a0,sp,4 - 7d84: 0000 unimp - 7d86: 8e05 sub a2,a2,s1 - 7d88: 0f02 c.slli64 t5 - 7d8a: 0025 c.nop 9 - 7d8c: 0000 unimp - 7d8e: 17a0 addi s0,sp,1000 - 7d90: 0251 addi tp,tp,20 - 7d92: 0000 unimp - 7d94: 8f05 sub a4,a4,s1 - 7d96: 1602 slli a2,a2,0x20 - 7d98: 0105 addi sp,sp,1 - 7d9a: 0000 unimp - 7d9c: 17a4 addi s1,sp,1000 - 7d9e: 00be slli ra,ra,0xf - 7da0: 0000 unimp - 7da2: 9005 srli s0,s0,0x21 - 7da4: 1602 slli a2,a2,0x20 - 7da6: 0105 addi sp,sp,1 - 7da8: 0000 unimp - 7daa: 17ac addi a1,sp,1000 - 7dac: 0240 addi s0,sp,260 - 7dae: 0000 unimp - 7db0: 9105 srli a0,a0,0x21 - 7db2: 1602 slli a2,a2,0x20 - 7db4: 0105 addi sp,sp,1 - 7db6: 0000 unimp - 7db8: 17b4 addi a3,sp,1000 - 7dba: 0000005b 0x5b - 7dbe: 9205 srli a2,a2,0x21 - 7dc0: 1602 slli a2,a2,0x20 - 7dc2: 0105 addi sp,sp,1 - 7dc4: 0000 unimp - 7dc6: 17bc addi a5,sp,1000 - 7dc8: 006a c.slli zero,0x1a - 7dca: 0000 unimp - 7dcc: 9305 srli a4,a4,0x21 - 7dce: 1602 slli a2,a2,0x20 - 7dd0: 0105 addi sp,sp,1 - 7dd2: 0000 unimp - 7dd4: 17c4 addi s1,sp,996 - 7dd6: 054e slli a0,a0,0x13 - 7dd8: 0000 unimp - 7dda: 9405 srai s0,s0,0x21 - 7ddc: 0802 c.slli64 a6 - 7dde: 0025 c.nop 9 - 7de0: 0000 unimp - 7de2: 00cc addi a1,sp,68 - 7de4: bc08 fsd fa0,56(s0) - 7de6: 0005 c.nop 1 - 7de8: 1b00 addi s0,sp,432 - 7dea: 0008 0x8 - 7dec: 0900 addi s0,sp,144 - 7dee: 002c addi a1,sp,8 - 7df0: 0000 unimp - 7df2: 0019 c.nop 6 - 7df4: bc08 fsd fa0,56(s0) - 7df6: 0005 c.nop 1 - 7df8: 2b00 fld fs0,16(a4) - 7dfa: 0008 0x8 - 7dfc: 0900 addi s0,sp,144 - 7dfe: 002c addi a1,sp,8 - 7e00: 0000 unimp - 7e02: bc080007 vlxseg6b.v v0,(a6),v0,v0.t - 7e06: 0005 c.nop 1 - 7e08: 3b00 fld fs0,48(a4) - 7e0a: 0008 0x8 - 7e0c: 0900 addi s0,sp,144 - 7e0e: 002c addi a1,sp,8 - 7e10: 0000 unimp - 7e12: f01a0017 auipc zero,0xf01a0 - 7e16: 9905 andi a0,a0,-31 - 7e18: 0702 c.slli64 a4 - 7e1a: 0862 slli a6,a6,0x18 - 7e1c: 0000 unimp - 7e1e: 00047617 auipc a2,0x47 - 7e22: 0500 addi s0,sp,640 - 7e24: 029c addi a5,sp,320 - 7e26: 0008621b 0x8621b - 7e2a: 0000 unimp - 7e2c: 00029617 auipc a2,0x29 - 7e30: 0500 addi s0,sp,640 - 7e32: 029d addi t0,t0,7 - 7e34: 7218 flw fa4,32(a2) - 7e36: 0008 0x8 - 7e38: 7800 flw fs0,48(s0) - 7e3a: 0800 addi s0,sp,16 - 7e3c: 000002fb 0x2fb - 7e40: 0872 slli a6,a6,0x1c - 7e42: 0000 unimp - 7e44: 2c09 jal 8056 <_start-0x7fff7faa> - 7e46: 0000 unimp - 7e48: 1d00 addi s0,sp,688 - 7e4a: 0800 addi s0,sp,16 - 7e4c: 002c addi a1,sp,8 - 7e4e: 0000 unimp - 7e50: 0882 c.slli64 a7 - 7e52: 0000 unimp - 7e54: 2c09 jal 8066 <_start-0x7fff7f9a> - 7e56: 0000 unimp - 7e58: 1d00 addi s0,sp,688 - 7e5a: 1b00 addi s0,sp,432 - 7e5c: 05f0 addi a2,sp,716 - 7e5e: 027e slli tp,tp,0x1f - 7e60: 0008a703 lw a4,0(a7) # 0 <_start-0x80000000> - 7e64: 1c00 addi s0,sp,560 - 7e66: 05d1 addi a1,a1,20 - 7e68: 0000 unimp - 7e6a: 9505 srai a0,a0,0x21 - 7e6c: 0b02 c.slli64 s6 - 7e6e: 06f6 slli a3,a3,0x1d - 7e70: 0000 unimp - 7e72: 031c addi a5,sp,384 - 7e74: 05000007 0x5000007 - 7e78: 029e slli t0,t0,0x7 - 7e7a: 00083b0b 0x83b0b - 7e7e: 0000 unimp - 7e80: bc08 fsd fa0,56(s0) - 7e82: 0005 c.nop 1 - 7e84: b700 fsd fs0,40(a4) - 7e86: 0008 0x8 - 7e88: 0900 addi s0,sp,144 - 7e8a: 002c addi a1,sp,8 - 7e8c: 0000 unimp - 7e8e: 0018 0x18 - 7e90: b31d j 7bb6 <_start-0x7fff844a> - 7e92: 0000 unimp - 7e94: 0f00 addi s0,sp,912 - 7e96: b704 fsd fs1,40(a4) - 7e98: 0008 0x8 - 7e9a: 1e00 addi s0,sp,816 - 7e9c: 08cd addi a7,a7,19 - 7e9e: 0000 unimp - 7ea0: 6214 flw fa3,0(a2) - 7ea2: 0004 0x4 - 7ea4: 0000 unimp - 7ea6: 08c2040f 0x8c2040f - 7eaa: 0000 unimp - 7eac: 0185040f 0x185040f - 7eb0: 0000 unimp - 7eb2: e41e fsw ft7,8(sp) - 7eb4: 0008 0x8 - 7eb6: 1400 addi s0,sp,544 - 7eb8: 0025 c.nop 9 - 7eba: 0000 unimp - 7ebc: 0f00 addi s0,sp,912 - 7ebe: ea04 fsw fs1,16(a2) - 7ec0: 0008 0x8 - 7ec2: 0f00 addi s0,sp,912 - 7ec4: d904 sw s1,48(a0) - 7ec6: 0008 0x8 - 7ec8: 0800 addi s0,sp,16 - 7eca: 0000065b 0x65b - 7ece: 0900 addi s0,sp,144 - 7ed0: 0000 unimp - 7ed2: 2c09 jal 80e4 <_start-0x7fff7f1c> - 7ed4: 0000 unimp - 7ed6: 0200 addi s0,sp,256 - 7ed8: 1f00 addi s0,sp,944 - 7eda: 069e slli a3,a3,0x7 - 7edc: 0000 unimp - 7ede: 2e05 jal 820e <_start-0x7fff7df2> - 7ee0: 04621703 lh a4,70(tp) # 1046 <_start-0x7fffefba> - 7ee4: 0000 unimp - 7ee6: 971f 0006 0500 0x5000006971f - 7eec: 681d032f 0x681d032f - 7ef0: 0004 0x4 - 7ef2: 0800 addi s0,sp,16 - 7ef4: 05f2 slli a1,a1,0x1c - 7ef6: 0000 unimp - 7ef8: 0925 addi s2,s2,9 - 7efa: 0000 unimp - 7efc: 0020 addi s0,sp,8 - 7efe: 1a15 addi s4,s4,-27 - 7f00: 0009 c.nop 2 - 7f02: 2100 fld fs0,0(a0) - 7f04: 0000022b 0x22b - 7f08: 1406 slli s0,s0,0x21 - 7f0a: 2524 fld fs1,72(a0) - 7f0c: 0009 c.nop 2 - 7f0e: 2100 fld fs0,0(a0) - 7f10: 0594 addi a3,sp,704 - 7f12: 0000 unimp - 7f14: 1506 slli a0,a0,0x21 - 7f16: 2515 jal 853a <_start-0x7fff7ac6> - 7f18: 0000 unimp - 7f1a: 0f00 addi s0,sp,912 - 7f1c: 4804 lw s1,16(s0) - 7f1e: 0009 c.nop 2 - 7f20: 1300 addi s0,sp,416 - 7f22: 0025 c.nop 9 - 7f24: 0000 unimp - 7f26: 095c addi a5,sp,148 - 7f28: 0000 unimp - 7f2a: 5c14 lw a3,56(s0) - 7f2c: 0009 c.nop 2 - 7f2e: 1400 addi s0,sp,544 - 7f30: 095c addi a5,sp,148 - 7f32: 0000 unimp - 7f34: 0f00 addi s0,sp,912 - 7f36: 6204 flw fs1,0(a2) - 7f38: 0009 c.nop 2 - 7f3a: 2200 fld fs0,0(a2) - 7f3c: 9c21 0x9c21 - 7f3e: 0004 0x4 - 7f40: 0700 addi s0,sp,896 - 7f42: 05b60e67 jalr t3,91(a2) # 30e87 <_start-0x7ffcf179> - 7f46: 0000 unimp - 7f48: dc21 beqz s0,7ea0 <_start-0x7fff8160> - 7f4a: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - 7f4e: 0f10 addi a2,sp,912 - 7f50: 0000097b 0x97b - 7f54: 05b6040f 0x5b6040f - 7f58: 0000 unimp - 7f5a: 9f21 0x9f21 - 7f5c: 0004 0x4 - 7f5e: 0800 addi s0,sp,16 - 7f60: 0efc addi a5,sp,860 - 7f62: 05b6 slli a1,a1,0xd - 7f64: 0000 unimp - 7f66: 8e21 xor a2,a2,s0 - 7f68: 0000 unimp - 7f6a: 0800 addi s0,sp,16 - 7f6c: 0cfd addi s9,s9,31 - 7f6e: 0025 c.nop 9 - 7f70: 0000 unimp - 7f72: 3421 jal 797a <_start-0x7fff8686> - 7f74: 0006 c.slli zero,0x1 - 7f76: 0800 addi s0,sp,16 - 7f78: 14fd addi s1,s1,-1 - 7f7a: 0025 c.nop 9 - 7f7c: 0000 unimp - 7f7e: 4721 li a4,8 - 7f80: 08000007 vlsbu.v v0,(zero),zero,v0.t - 7f84: 1cfd addi s9,s9,-1 - 7f86: 0025 c.nop 9 - 7f88: 0000 unimp - 7f8a: 1b21 addi s6,s6,-24 - 7f8c: 0004 0x4 - 7f8e: 0800 addi s0,sp,16 - 7f90: 0cff 0xcff - 7f92: 0025 c.nop 9 - 7f94: 0000 unimp - 7f96: cc21 beqz s0,7fee <_start-0x7fff8012> - 7f98: 0004 0x4 - 7f9a: 0900 addi s0,sp,144 - 7f9c: 169a slli a3,a3,0x26 - 7f9e: 005d c.nop 23 - 7fa0: 0000 unimp - 7fa2: 2f21 jal 86ba <_start-0x7fff7946> - 7fa4: 0000 unimp - 7fa6: 0900 addi s0,sp,144 - 7fa8: 0025159b 0x25159b - 7fac: 0000 unimp - 7fae: b608 fsd fa0,40(a2) - 7fb0: 0005 c.nop 1 - 7fb2: e500 fsw fs0,8(a0) - 7fb4: 0009 c.nop 2 - 7fb6: 0900 addi s0,sp,144 - 7fb8: 002c addi a1,sp,8 - 7fba: 0000 unimp - 7fbc: 0001 nop - 7fbe: cd21 beqz a0,8016 <_start-0x7fff7fea> - 7fc0: 0000 unimp - 7fc2: 0900 addi s0,sp,144 - 7fc4: 179e slli a5,a5,0x27 - 7fc6: 09d5 addi s3,s3,21 - 7fc8: 0000 unimp - 7fca: ea04 fsw fs1,16(a2) - 7fcc: 0002 c.slli64 zero - 7fce: 0a00 addi s0,sp,272 - 7fd0: 162a slli a2,a2,0x2a - 7fd2: 002c addi a1,sp,8 - 7fd4: 0000 unimp - 7fd6: 8204 0x8204 - 7fd8: 0005 c.nop 1 - 7fda: 0a00 addi s0,sp,272 - 7fdc: 0a09152f 0xa09152f - 7fe0: 0000 unimp - 7fe2: 0a0f040f 0xa0f040f - 7fe6: 0000 unimp - 7fe8: 0009f113 andi sp,s3,0 - 7fec: 1e00 addi s0,sp,816 - 7fee: 000a c.slli zero,0x2 - 7ff0: 1400 addi s0,sp,544 - 7ff2: 095c addi a5,sp,148 - 7ff4: 0000 unimp - 7ff6: 0400 addi s0,sp,512 - 7ff8: 00000797 auipc a5,0x0 - 7ffc: 360a fld fa2,160(sp) - 7ffe: 0009420f 0x9420f - 8002: 2100 fld fs0,0(a0) - 8004: 000a c.slli zero,0x2 - 8006: 0000 unimp - 8008: bb0a fsd ft2,432(sp) - 800a: fd12 fsw ft4,184(sp) - 800c: 0009 c.nop 2 - 800e: 2100 fld fs0,0(a0) - 8010: 0682 c.slli64 a3 - 8012: 0000 unimp - 8014: be0a fsd ft2,312(sp) - 8016: 1e10 addi a2,sp,816 - 8018: 000a c.slli zero,0x2 - 801a: 2300 fld fs0,0(a4) - 801c: 02bd addi t0,t0,15 - 801e: 0000 unimp - 8020: 002c0407 0x2c0407 - 8024: 0000 unimp - 8026: 7f06180b 0x7f06180b - 802a: 000a c.slli zero,0x2 - 802c: 2400 fld fs0,8(s0) - 802e: 0529 addi a0,a0,10 - 8030: 0000 unimp - 8032: 2400 fld fs0,8(s0) - 8034: 03f6 slli t2,t2,0x1d - 8036: 0000 unimp - 8038: 2401 jal 8238 <_start-0x7fff7dc8> - 803a: 03d1 addi t2,t2,20 - 803c: 0000 unimp - 803e: 2402 fld fs0,0(sp) - 8040: 044a slli s0,s0,0x12 - 8042: 0000 unimp - 8044: 05202403 lw s0,82(zero) # 52 <_start-0x7fffffae> - 8048: 0000 unimp - 804a: 2404 fld fs1,8(s0) - 804c: 074e slli a4,a4,0x13 - 804e: 0000 unimp - 8050: 2405 jal 8270 <_start-0x7fff7d90> - 8052: 073d addi a4,a4,15 - 8054: 0000 unimp - 8056: 0006 c.slli zero,0x1 - 8058: a921 j 8470 <_start-0x7fff7b90> - 805a: 0000 unimp - 805c: 0b00 addi s0,sp,400 - 805e: 1c21 addi s8,s8,-24 - 8060: 0a42 slli s4,s4,0x10 - 8062: 0000 unimp - 8064: 00045523 0x45523 - 8068: 0700 addi s0,sp,896 - 806a: 2c04 fld fs1,24(s0) - 806c: 0000 unimp - 806e: 0b00 addi s0,sp,400 - 8070: 0ab00623 sb a1,172(zero) # ac <_start-0x7fffff54> - 8074: 0000 unimp - 8076: 7824 flw fs1,112(s0) - 8078: 0005 c.nop 1 - 807a: 0000 unimp - 807c: 3f24 fld fs1,120(a4) - 807e: 0005 c.nop 1 - 8080: 0100 addi s0,sp,128 - 8082: 5724 lw s1,104(a4) - 8084: 0006 c.slli zero,0x1 - 8086: 0200 addi s0,sp,256 - 8088: 2100 fld fs0,0(a0) - 808a: 025f 0000 280b 0x280b0000025f - 8090: 8b1e mv s6,t2 - 8092: 000a c.slli zero,0x2 - 8094: 2100 fld fs0,0(a0) - 8096: 040c addi a1,sp,512 - 8098: 0000 unimp - 809a: 290c fld fa1,16(a0) - 809c: 251a fld fa0,384(sp) - 809e: 0009 c.nop 2 - 80a0: 2100 fld fs0,0(a0) - 80a2: 061e slli a2,a2,0x7 - 80a4: 0000 unimp - 80a6: 380c fld fa1,48(s0) - 80a8: 251a fld fa0,384(sp) - 80aa: 0009 c.nop 2 - 80ac: 0400 addi s0,sp,512 - 80ae: 00000773 0x773 - 80b2: 7b0d lui s6,0xfffe3 - 80b4: 4816 lw a6,68(sp) - 80b6: 0000 unimp - 80b8: 1500 addi s0,sp,672 - 80ba: 0ad4 addi a3,sp,340 - 80bc: 0000 unimp - 80be: 1604 addi s1,sp,800 - 80c0: 0002 c.slli64 zero - 80c2: 0d00 addi s0,sp,656 - 80c4: 0f80 addi s0,sp,976 - 80c6: 0025 c.nop 9 - 80c8: 0000 unimp - 80ca: 1504 addi s1,sp,672 - 80cc: 0002 c.slli64 zero - 80ce: 0d00 addi s0,sp,656 - 80d0: 1681 addi a3,a3,-32 - 80d2: 002c addi a1,sp,8 - 80d4: 0000 unimp - 80d6: 85040403 lb s0,-1968(s0) # 87a4 <_start-0x7fff785c> - 80da: 0004 0x4 - 80dc: 0300 addi s0,sp,384 - 80de: 0308 addi a0,sp,384 - 80e0: 047d addi s0,s0,31 - 80e2: 0000 unimp - 80e4: a2040803 lb a6,-1504(s0) - 80e8: 0000 unimp - 80ea: 0300 addi s0,sp,384 - 80ec: 0310 addi a2,sp,384 - 80ee: 0039 c.nop 14 - 80f0: 0000 unimp - 80f2: 95032003 lw zero,-1712(t1) - 80f6: 0000 unimp - 80f8: 0800 addi s0,sp,16 - 80fa: 0ae0 addi s0,sp,348 - 80fc: 0000 unimp - 80fe: 0b30 addi a2,sp,408 - 8100: 0000 unimp - 8102: 2c09 jal 8314 <_start-0x7fff7cec> - 8104: 0000 unimp - 8106: ff00 fsw fs0,56(a4) - 8108: 1500 addi s0,sp,672 - 810a: 0b20 addi s0,sp,408 - 810c: 0000 unimp - 810e: ee1f 0006 0d00 0xd000006ee1f - 8114: 01fc addi a5,sp,204 - 8116: 3016 fld ft0,352(sp) - 8118: 1f00000b 0x1f00000b - 811c: 00000397 auipc t2,0x0 - 8120: 020d addi tp,tp,3 - 8122: 1602 slli a2,a2,0x20 - 8124: 0b30 addi a2,sp,408 - 8126: 0000 unimp - 8128: 4625 li a2,9 - 812a: 0012 c.slli zero,0x4 - 812c: 0100 addi s0,sp,128 - 812e: 02c2 slli t0,t0,0x10 - 8130: 2501 jal 8730 <_start-0x7fff78d0> - 8132: 0000 unimp - 8134: fc00 fsw fs0,56(s0) - 8136: 0144 addi s1,sp,132 - 8138: 4c80 lw s0,24(s1) - 813a: 0000 unimp - 813c: 0100 addi s0,sp,128 - 813e: 269c fld fa5,8(a3) - 8140: 0078 addi a4,sp,12 - 8142: c201 beqz a2,8142 <_start-0x7fff7ebe> - 8144: 1202 slli tp,tp,0x20 - 8146: 0af1 addi s5,s5,28 - 8148: 0000 unimp - 814a: fa31 bnez a2,809e <_start-0x7fff7f62> - 814c: 0000 unimp - 814e: 74657227 0x74657227 - 8152: 0100 addi s0,sp,128 - 8154: 02c4 addi s1,sp,324 - 8156: e509 bnez a0,8160 <_start-0x7fff7ea0> - 8158: 000a c.slli zero,0x2 - 815a: 2800 fld fs0,16(s0) - 815c: 1310 addi a2,sp,416 - 815e: 0000 unimp - 8160: 9229 srli a2,a2,0x2a - 8162: 0006 c.slli zero,0x1 - 8164: 0100 addi s0,sp,128 - 8166: 02c6 slli t0,t0,0x11 - 8168: 000af103 0xaf103 - 816c: 5d00 lw s0,56(a0) - 816e: 00fa slli ra,ra,0x1e - 8170: 2a00 fld fs0,16(a2) - 8172: 5f5f 0061 c601 0xc60100615f5f - 8178: 0302 c.slli64 t1 - 817a: 0af1 addi s5,s5,28 - 817c: 0000 unimp - 817e: fa89 bnez a3,8090 <_start-0x7fff7f70> - 8180: 0000 unimp - 8182: 0000 unimp - ... - -Disassembly of section .debug_abbrev: - -00000000 <.debug_abbrev>: - 0: 1101 addi sp,sp,-32 - 2: 2501 jal 602 <_start-0x7ffff9fe> - 4: 130e slli t1,t1,0x23 - 6: 1b0e030b 0x1b0e030b - a: 110e slli sp,sp,0x23 - c: 1201 addi tp,tp,-32 - e: 1006 c.slli zero,0x21 - 10: 02000017 auipc zero,0x2000 - 14: 0024 addi s1,sp,8 - 16: 0b3e0b0b 0xb3e0b0b - 1a: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - 1e: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> - 22: 030b3e0b 0x30b3e0b - 26: 0008 0x8 - 28: 0400 addi s0,sp,512 - 2a: 0016 c.slli zero,0x5 - 2c: 0b3a0e03 lb t3,179(s4) # 10b3 <_start-0x7fffef4d> - 30: 0b390b3b 0xb390b3b - 34: 1349 addi t1,t1,-14 - 36: 0000 unimp - 38: 1605 addi a2,a2,-31 - 3a: 0300 addi s0,sp,384 - 3c: 3a0e fld fs4,224(sp) - 3e: 39053b0b 0x39053b0b - 42: 0013490b 0x13490b - 46: 0600 addi s0,sp,768 - 48: 0b0b0117 auipc sp,0xb0b0 - 4c: 0b3a slli s6,s6,0xe - 4e: 0b390b3b 0xb390b3b - 52: 1301 addi t1,t1,-32 - 54: 0000 unimp - 56: 03000d07 vlbuff.v v26,(zero) - 5a: 3a0e fld fs4,224(sp) - 5c: 390b3b0b 0x390b3b0b - 60: 0013490b 0x13490b - 64: 0800 addi s0,sp,16 - 66: 0101 addi sp,sp,0 - 68: 1349 addi t1,t1,-14 - 6a: 1301 addi t1,t1,-32 - 6c: 0000 unimp - 6e: 2109 jal 470 <_start-0x7ffffb90> - 70: 4900 lw s0,16(a0) - 72: 000b2f13 slti t5,s6,0 - 76: 0a00 addi s0,sp,272 - 78: 0b0b0113 addi sp,s6,176 # fffe30b0 <__BSS_END__+0x7ffcc338> - 7c: 0b3a slli s6,s6,0xe - 7e: 0b390b3b 0xb390b3b - 82: 1301 addi t1,t1,-32 - 84: 0000 unimp - 86: 03000d0b 0x3000d0b - 8a: 3a0e fld fs4,224(sp) - 8c: 390b3b0b 0x390b3b0b - 90: 3813490b 0x3813490b - 94: 0c00000b 0xc00000b - 98: 0b0b000f 0xb0b000f - 9c: 0000 unimp - 9e: 130d addi t1,t1,-29 - a0: 0301 addi t1,t1,0 - a2: 0b0e slli s6,s6,0x3 - a4: 3b0b3a0b 0x3b0b3a0b - a8: 010b390b 0x10b390b - ac: 0e000013 li zero,224 - b0: 000d c.nop 3 - b2: 0b3a0803 lb a6,179(s4) - b6: 0b390b3b 0xb390b3b - ba: 1349 addi t1,t1,-14 - bc: 0b38 addi a4,sp,408 - be: 0000 unimp - c0: 0b000f0f 0xb000f0f - c4: 0013490b 0x13490b - c8: 1000 addi s0,sp,32 - ca: 0e030113 addi sp,t1,224 - ce: 0b3a050b 0xb3a050b - d2: 0b390b3b 0xb390b3b - d6: 1301 addi t1,t1,-32 - d8: 0000 unimp - da: 0d11 addi s10,s10,4 - dc: 0300 addi s0,sp,384 - de: 3a0e fld fs4,224(sp) - e0: 390b3b0b 0x390b3b0b - e4: 3813490b 0x3813490b - e8: 0005 c.nop 1 - ea: 1200 addi s0,sp,288 - ec: 0015 c.nop 5 - ee: 00001927 0x1927 - f2: 27011513 0x27011513 - f6: 4919 li s2,6 - f8: 00130113 addi sp,t1,1 - fc: 1400 addi s0,sp,544 - fe: 0005 c.nop 1 - 100: 1349 addi t1,t1,-14 - 102: 0000 unimp - 104: 2615 jal 428 <_start-0x7ffffbd8> - 106: 4900 lw s0,16(a0) - 108: 16000013 li zero,352 - 10c: 0e030113 addi sp,t1,224 - 110: 0b3a050b 0xb3a050b - 114: 0b39053b 0xb39053b - 118: 1301 addi t1,t1,-32 - 11a: 0000 unimp - 11c: 03000d17 auipc s10,0x3000 - 120: 3a0e fld fs4,224(sp) - 122: 39053b0b 0x39053b0b - 126: 3813490b 0x3813490b - 12a: 1800000b 0x1800000b - 12e: 000d c.nop 3 - 130: 0b3a0e03 lb t3,179(s4) - 134: 0b39053b 0xb39053b - 138: 1349 addi t1,t1,-14 - 13a: 0538 addi a4,sp,648 - 13c: 0000 unimp - 13e: 1319 addi t1,t1,-26 - 140: 0301 addi t1,t1,0 - 142: 0b0e slli s6,s6,0x3 - 144: 3b0b3a0b 0x3b0b3a0b - 148: 3905 jal fffffd78 <__BSS_END__+0x7ffe9000> - 14a: 0013010b 0x13010b - 14e: 1a00 addi s0,sp,304 - 150: 0b0b0113 addi sp,s6,176 - 154: 0b3a slli s6,s6,0xe - 156: 0b39053b 0xb39053b - 15a: 1301 addi t1,t1,-32 - 15c: 0000 unimp - 15e: 0b01171b 0xb01171b - 162: 3b0b3a0b 0x3b0b3a0b - 166: 3905 jal fffffd96 <__BSS_END__+0x7ffe901e> - 168: 0013010b 0x13010b - 16c: 1c00 addi s0,sp,560 - 16e: 000d c.nop 3 - 170: 0b3a0e03 lb t3,179(s4) - 174: 0b39053b 0xb39053b - 178: 1349 addi t1,t1,-14 - 17a: 0000 unimp - 17c: 131d addi t1,t1,-25 - 17e: 0300 addi s0,sp,384 - 180: 3c0e fld fs8,224(sp) - 182: 0019 c.nop 6 - 184: 1e00 addi s0,sp,816 - 186: 0115 addi sp,sp,5 - 188: 13011927 0x13011927 - 18c: 0000 unimp - 18e: 341f 0300 3a0e 0x3a0e0300341f - 194: 39053b0b 0x39053b0b - 198: 3f13490b 0x3f13490b - 19c: 3c19 jal fffffbb2 <__BSS_END__+0x7ffe8e3a> - 19e: 0019 c.nop 6 - 1a0: 2000 fld fs0,0(s0) - 1a2: 0021 c.nop 8 - 1a4: 0000 unimp - 1a6: 3421 jal fffffbae <__BSS_END__+0x7ffe8e36> - 1a8: 0300 addi s0,sp,384 - 1aa: 3a0e fld fs4,224(sp) - 1ac: 390b3b0b 0x390b3b0b - 1b0: 3f13490b 0x3f13490b - 1b4: 3c19 jal fffffbca <__BSS_END__+0x7ffe8e52> - 1b6: 0019 c.nop 6 - 1b8: 2200 fld fs0,0(a2) - 1ba: 0026 c.slli zero,0x9 - 1bc: 0000 unimp - 1be: 03010423 sb a6,40(sp) # b0b0070 <_start-0x74f4ff90> - 1c2: 3e0e fld ft8,224(sp) - 1c4: 490b0b0b 0x490b0b0b - 1c8: 3b0b3a13 sltiu s4,s6,944 - 1cc: 010b390b 0x10b390b - 1d0: 24000013 li zero,576 - 1d4: 0028 addi a0,sp,8 - 1d6: 0b1c0e03 lb t3,177(s8) # fffe10b1 <__BSS_END__+0x7ffca339> - 1da: 0000 unimp - 1dc: 0d25 addi s10,s10,9 - 1de: 0300 addi s0,sp,384 - 1e0: 3a08 fld fa0,48(a2) - 1e2: 39053b0b 0x39053b0b - 1e6: 3813490b 0x3813490b - 1ea: 2600000b 0x2600000b - 1ee: 000d c.nop 3 - 1f0: 0b3a0803 lb a6,179(s4) - 1f4: 0b39053b 0xb39053b - 1f8: 1349 addi t1,t1,-14 - 1fa: 0000 unimp - 1fc: 3f012e27 fsw fa6,1020(sp) - 200: 0319 addi t1,t1,6 - 202: 3a0e fld fs4,224(sp) - 204: 39053b0b 0x39053b0b - 208: 4919270b 0x4919270b - 20c: 12011113 0x12011113 - 210: 4006 0x4006 - 212: 9718 0x9718 - 214: 1942 slli s2,s2,0x30 - 216: 1301 addi t1,t1,-32 - 218: 0000 unimp - 21a: 0528 addi a0,sp,648 - 21c: 0300 addi s0,sp,384 - 21e: 3a08 fld fa0,48(a2) - 220: 39053b0b 0x39053b0b - 224: 0213490b 0x213490b - 228: 29000017 auipc zero,0x29000 - 22c: 011d addi sp,sp,7 - 22e: 1331 addi t1,t1,-20 - 230: 0152 slli sp,sp,0x14 - 232: 1755 addi a4,a4,-11 - 234: 0b58 addi a4,sp,404 - 236: 0559 addi a0,a0,22 - 238: 00000b57 vadd.vv v22,v0,v0,v0.t - 23c: 052a slli a0,a0,0xa - 23e: 3100 fld fs0,32(a0) - 240: 00170213 addi tp,a4,1 # fffe1001 <__BSS_END__+0x7ffca289> - 244: 2b00 fld fs0,16(a4) - 246: 1755010b 0x1755010b - 24a: 0000 unimp - 24c: 342c fld fa1,104(s0) - 24e: 3100 fld fs0,32(a0) - 250: 2d000013 li zero,720 - 254: 0034 addi a3,sp,8 - 256: 1331 addi t1,t1,-20 - 258: 1702 slli a4,a4,0x20 - 25a: 0000 unimp - 25c: 0b2e slli s6,s6,0xb - 25e: 3101 jal fffffe5e <__BSS_END__+0x7ffe90e6> - 260: 01175513 srli a0,a4,0x11 - 264: 2f000013 li zero,752 - 268: 1331010b 0x1331010b - 26c: 0111 addi sp,sp,4 - 26e: 0612 slli a2,a2,0x4 - 270: 1301 addi t1,t1,-32 - 272: 0000 unimp - 274: 0b30 addi a2,sp,408 - 276: 3101 jal fffffe76 <__BSS_END__+0x7ffe90fe> - 278: 00175513 srli a0,a4,0x1 - 27c: 3100 fld fs0,32(a0) - 27e: 012e slli sp,sp,0xb - 280: 0b3a0e03 lb t3,179(s4) - 284: 0b39053b 0xb39053b - 288: 13491927 0x13491927 - 28c: 0b20 addi s0,sp,408 - 28e: 1301 addi t1,t1,-32 - 290: 0000 unimp - 292: 0532 slli a0,a0,0xc - 294: 0300 addi s0,sp,384 - 296: 3a08 fld fa0,48(a2) - 298: 39053b0b 0x39053b0b - 29c: 0013490b 0x13490b - 2a0: 3300 fld fs0,32(a4) - 2a2: 0034 addi a3,sp,8 - 2a4: 0b3a0803 lb a6,179(s4) - 2a8: 0b39053b 0xb39053b - 2ac: 1349 addi t1,t1,-14 - 2ae: 0000 unimp - 2b0: 0b34 addi a3,sp,408 - 2b2: 0101 addi sp,sp,0 - 2b4: 35000013 li zero,848 - 2b8: 0034 addi a3,sp,8 - 2ba: 0b3a0e03 lb t3,179(s4) - 2be: 0b39053b 0xb39053b - 2c2: 1349 addi t1,t1,-14 - 2c4: 0000 unimp - 2c6: 0b36 slli s6,s6,0xd - 2c8: 0001 nop - 2ca: 0000 unimp - 2cc: 1101 addi sp,sp,-32 - 2ce: 2501 jal 8ce <_start-0x7ffff732> - 2d0: 130e slli t1,t1,0x23 - 2d2: 1b0e030b 0x1b0e030b - 2d6: 110e slli sp,sp,0x23 - 2d8: 1201 addi tp,tp,-32 - 2da: 1006 c.slli zero,0x21 - 2dc: 02000017 auipc zero,0x2000 - 2e0: 0024 addi s1,sp,8 - 2e2: 0b3e0b0b 0xb3e0b0b - 2e6: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - 2ea: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> - 2ee: 030b3e0b 0x30b3e0b - 2f2: 0008 0x8 - 2f4: 0400 addi s0,sp,512 - 2f6: 0016 c.slli zero,0x5 - 2f8: 0b3a0e03 lb t3,179(s4) - 2fc: 0b390b3b 0xb390b3b - 300: 1349 addi t1,t1,-14 - 302: 0000 unimp - 304: 1605 addi a2,a2,-31 - 306: 0300 addi s0,sp,384 - 308: 3a0e fld fs4,224(sp) - 30a: 39053b0b 0x39053b0b - 30e: 0013490b 0x13490b - 312: 0600 addi s0,sp,768 - 314: 0b0b0117 auipc sp,0xb0b0 - 318: 0b3a slli s6,s6,0xe - 31a: 0b390b3b 0xb390b3b - 31e: 1301 addi t1,t1,-32 - 320: 0000 unimp - 322: 03000d07 vlbuff.v v26,(zero) - 326: 3a0e fld fs4,224(sp) - 328: 390b3b0b 0x390b3b0b - 32c: 0013490b 0x13490b - 330: 0800 addi s0,sp,16 - 332: 0101 addi sp,sp,0 - 334: 1349 addi t1,t1,-14 - 336: 1301 addi t1,t1,-32 - 338: 0000 unimp - 33a: 2109 jal 73c <_start-0x7ffff8c4> - 33c: 4900 lw s0,16(a0) - 33e: 000b2f13 slti t5,s6,0 - 342: 0a00 addi s0,sp,272 - 344: 0b0b0113 addi sp,s6,176 - 348: 0b3a slli s6,s6,0xe - 34a: 0b390b3b 0xb390b3b - 34e: 1301 addi t1,t1,-32 - 350: 0000 unimp - 352: 03000d0b 0x3000d0b - 356: 3a0e fld fs4,224(sp) - 358: 390b3b0b 0x390b3b0b - 35c: 3813490b 0x3813490b - 360: 0c00000b 0xc00000b - 364: 0b0b000f 0xb0b000f - 368: 0000 unimp - 36a: 130d addi t1,t1,-29 - 36c: 0301 addi t1,t1,0 - 36e: 0b0e slli s6,s6,0x3 - 370: 3b0b3a0b 0x3b0b3a0b - 374: 010b390b 0x10b390b - 378: 0e000013 li zero,224 - 37c: 000d c.nop 3 - 37e: 0b3a0803 lb a6,179(s4) - 382: 0b390b3b 0xb390b3b - 386: 1349 addi t1,t1,-14 - 388: 0b38 addi a4,sp,408 - 38a: 0000 unimp - 38c: 0b000f0f 0xb000f0f - 390: 0013490b 0x13490b - 394: 1000 addi s0,sp,32 - 396: 0e030113 addi sp,t1,224 - 39a: 0b3a050b 0xb3a050b - 39e: 0b390b3b 0xb390b3b - 3a2: 1301 addi t1,t1,-32 - 3a4: 0000 unimp - 3a6: 0d11 addi s10,s10,4 - 3a8: 0300 addi s0,sp,384 - 3aa: 3a0e fld fs4,224(sp) - 3ac: 390b3b0b 0x390b3b0b - 3b0: 3813490b 0x3813490b - 3b4: 0005 c.nop 1 - 3b6: 1200 addi s0,sp,288 - 3b8: 0015 c.nop 5 - 3ba: 00001927 0x1927 - 3be: 27011513 0x27011513 - 3c2: 4919 li s2,6 - 3c4: 00130113 addi sp,t1,1 - 3c8: 1400 addi s0,sp,544 - 3ca: 0005 c.nop 1 - 3cc: 1349 addi t1,t1,-14 - 3ce: 0000 unimp - 3d0: 2615 jal 6f4 <_start-0x7ffff90c> - 3d2: 4900 lw s0,16(a0) - 3d4: 16000013 li zero,352 - 3d8: 0e030113 addi sp,t1,224 - 3dc: 0b3a050b 0xb3a050b - 3e0: 0b39053b 0xb39053b - 3e4: 1301 addi t1,t1,-32 - 3e6: 0000 unimp - 3e8: 03000d17 auipc s10,0x3000 - 3ec: 3a0e fld fs4,224(sp) - 3ee: 39053b0b 0x39053b0b - 3f2: 3813490b 0x3813490b - 3f6: 1800000b 0x1800000b - 3fa: 000d c.nop 3 - 3fc: 0b3a0e03 lb t3,179(s4) - 400: 0b39053b 0xb39053b - 404: 1349 addi t1,t1,-14 - 406: 0538 addi a4,sp,648 - 408: 0000 unimp - 40a: 1319 addi t1,t1,-26 - 40c: 0301 addi t1,t1,0 - 40e: 0b0e slli s6,s6,0x3 - 410: 3b0b3a0b 0x3b0b3a0b - 414: 3905 jal 44 <_start-0x7fffffbc> - 416: 0013010b 0x13010b - 41a: 1a00 addi s0,sp,304 - 41c: 0b0b0113 addi sp,s6,176 - 420: 0b3a slli s6,s6,0xe - 422: 0b39053b 0xb39053b - 426: 1301 addi t1,t1,-32 - 428: 0000 unimp - 42a: 0b01171b 0xb01171b - 42e: 3b0b3a0b 0x3b0b3a0b - 432: 3905 jal 62 <_start-0x7fffff9e> - 434: 0013010b 0x13010b - 438: 1c00 addi s0,sp,560 - 43a: 000d c.nop 3 - 43c: 0b3a0e03 lb t3,179(s4) - 440: 0b39053b 0xb39053b - 444: 1349 addi t1,t1,-14 - 446: 0000 unimp - 448: 131d addi t1,t1,-25 - 44a: 0300 addi s0,sp,384 - 44c: 3c0e fld fs8,224(sp) - 44e: 0019 c.nop 6 - 450: 1e00 addi s0,sp,816 - 452: 0115 addi sp,sp,5 - 454: 13011927 0x13011927 - 458: 0000 unimp - 45a: 341f 0300 3a0e 0x3a0e0300341f - 460: 39053b0b 0x39053b0b - 464: 3f13490b 0x3f13490b - 468: 3c19 jal fffffe7e <__BSS_END__+0x7ffe9106> - 46a: 0019 c.nop 6 - 46c: 2000 fld fs0,0(s0) - 46e: 0021 c.nop 8 - 470: 0000 unimp - 472: 3421 jal fffffe7a <__BSS_END__+0x7ffe9102> - 474: 0300 addi s0,sp,384 - 476: 3a0e fld fs4,224(sp) - 478: 390b3b0b 0x390b3b0b - 47c: 3f13490b 0x3f13490b - 480: 3c19 jal fffffe96 <__BSS_END__+0x7ffe911e> - 482: 0019 c.nop 6 - 484: 2200 fld fs0,0(a2) - 486: 0026 c.slli zero,0x9 - 488: 0000 unimp - 48a: 03010423 sb a6,40(sp) # b0b033c <_start-0x74f4fcc4> - 48e: 3e0e fld ft8,224(sp) - 490: 490b0b0b 0x490b0b0b - 494: 3b0b3a13 sltiu s4,s6,944 - 498: 010b390b 0x10b390b - 49c: 24000013 li zero,576 - 4a0: 0028 addi a0,sp,8 - 4a2: 0b1c0e03 lb t3,177(s8) - 4a6: 0000 unimp - 4a8: 0d25 addi s10,s10,9 - 4aa: 0300 addi s0,sp,384 - 4ac: 3a08 fld fa0,48(a2) - 4ae: 39053b0b 0x39053b0b - 4b2: 3813490b 0x3813490b - 4b6: 2600000b 0x2600000b - 4ba: 000d c.nop 3 - 4bc: 0b3a0803 lb a6,179(s4) - 4c0: 0b39053b 0xb39053b - 4c4: 1349 addi t1,t1,-14 - 4c6: 0000 unimp - 4c8: 3f012e27 fsw fa6,1020(sp) - 4cc: 0319 addi t1,t1,6 - 4ce: 3a0e fld fs4,224(sp) - 4d0: 39053b0b 0x39053b0b - 4d4: 4919270b 0x4919270b - 4d8: 12011113 0x12011113 - 4dc: 4006 0x4006 - 4de: 9718 0x9718 - 4e0: 1942 slli s2,s2,0x30 - 4e2: 1301 addi t1,t1,-32 - 4e4: 0000 unimp - 4e6: 0528 addi a0,sp,648 - 4e8: 0300 addi s0,sp,384 - 4ea: 3a08 fld fa0,48(a2) - 4ec: 39053b0b 0x39053b0b - 4f0: 0213490b 0x213490b - 4f4: 29000017 auipc zero,0x29000 - 4f8: 0034 addi a3,sp,8 - 4fa: 0b3a0803 lb a6,179(s4) - 4fe: 0b39053b 0xb39053b - 502: 1349 addi t1,t1,-14 - 504: 1702 slli a4,a4,0x20 - 506: 0000 unimp - 508: 1d2a slli s10,s10,0x2a - 50a: 3101 jal 10a <_start-0x7ffffef6> - 50c: 55015213 0x55015213 - 510: 590b5817 auipc a6,0x590b5 - 514: 5705 li a4,-31 - 516: 2b00000b 0x2b00000b - 51a: 0005 c.nop 1 - 51c: 1331 addi t1,t1,-20 - 51e: 1702 slli a4,a4,0x20 - 520: 0000 unimp - 522: 0b2c addi a1,sp,408 - 524: 5501 li a0,-32 - 526: 2d000017 auipc zero,0x2d000 - 52a: 0034 addi a3,sp,8 - 52c: 1331 addi t1,t1,-20 - 52e: 0000 unimp - 530: 342e fld fs0,232(sp) - 532: 3100 fld fs0,32(a0) - 534: 00170213 addi tp,a4,1 - 538: 2f00 fld fs0,24(a4) - 53a: 1331010b 0x1331010b - 53e: 1755 addi a4,a4,-11 - 540: 1301 addi t1,t1,-32 - 542: 0000 unimp - 544: 0b30 addi a2,sp,408 - 546: 3101 jal 146 <_start-0x7ffffeba> - 548: 12011113 0x12011113 - 54c: 0106 slli sp,sp,0x1 - 54e: 31000013 li zero,784 - 552: 1331010b 0x1331010b - 556: 0111 addi sp,sp,4 - 558: 0612 slli a2,a2,0x4 - 55a: 0000 unimp - 55c: 3432 fld fs0,296(sp) - 55e: 3100 fld fs0,32(a0) - 560: 00180213 addi tp,a6,1 # 590b5511 <_start-0x26f4aaef> - 564: 3300 fld fs0,32(a4) - 566: 012e slli sp,sp,0xb - 568: 0b3a0e03 lb t3,179(s4) - 56c: 0b39053b 0xb39053b - 570: 13491927 0x13491927 - 574: 0b20 addi s0,sp,408 - 576: 1301 addi t1,t1,-32 - 578: 0000 unimp - 57a: 0534 addi a3,sp,648 - 57c: 0300 addi s0,sp,384 - 57e: 3a08 fld fa0,48(a2) - 580: 39053b0b 0x39053b0b - 584: 0013490b 0x13490b - 588: 3500 fld fs0,40(a0) - 58a: 0034 addi a3,sp,8 - 58c: 0b3a0803 lb a6,179(s4) - 590: 0b39053b 0xb39053b - 594: 1349 addi t1,t1,-14 - 596: 0000 unimp - 598: 0b36 slli s6,s6,0xd - 59a: 0101 addi sp,sp,0 - 59c: 37000013 li zero,880 - 5a0: 0034 addi a3,sp,8 - 5a2: 0b3a0e03 lb t3,179(s4) - 5a6: 0b39053b 0xb39053b - 5aa: 1349 addi t1,t1,-14 - 5ac: 0000 unimp - 5ae: 0b38 addi a4,sp,408 - 5b0: 0001 nop - 5b2: 0000 unimp - 5b4: 1101 addi sp,sp,-32 - 5b6: 2501 jal bb6 <_start-0x7ffff44a> - 5b8: 130e slli t1,t1,0x23 - 5ba: 1b0e030b 0x1b0e030b - 5be: 110e slli sp,sp,0x23 - 5c0: 1201 addi tp,tp,-32 - 5c2: 1006 c.slli zero,0x21 - 5c4: 02000017 auipc zero,0x2000 - 5c8: 0024 addi s1,sp,8 - 5ca: 0b3e0b0b 0xb3e0b0b - 5ce: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - 5d2: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> - 5d6: 030b3e0b 0x30b3e0b - 5da: 0008 0x8 - 5dc: 0400 addi s0,sp,512 - 5de: 0016 c.slli zero,0x5 - 5e0: 0b3a0e03 lb t3,179(s4) - 5e4: 0b39053b 0xb39053b - 5e8: 1349 addi t1,t1,-14 - 5ea: 0000 unimp - 5ec: 2605 jal 90c <_start-0x7ffff6f4> - 5ee: 4900 lw s0,16(a0) - 5f0: 06000013 li zero,96 - 5f4: 0101 addi sp,sp,0 - 5f6: 1349 addi t1,t1,-14 - 5f8: 1301 addi t1,t1,-32 - 5fa: 0000 unimp - 5fc: 49002107 flw ft2,1168(zero) # 490 <_start-0x7ffffb70> - 600: 000b2f13 slti t5,s6,0 - 604: 0800 addi s0,sp,16 - 606: 0034 addi a3,sp,8 - 608: 0b3a0e03 lb t3,179(s4) - 60c: 0b390b3b 0xb390b3b - 610: 1349 addi t1,t1,-14 - 612: 193c193f 16090000 0x16090000193c193f - 61a: 0300 addi s0,sp,384 - 61c: 3a0e fld fs4,224(sp) - 61e: 390b3b0b 0x390b3b0b - 622: 0013490b 0x13490b - 626: 0a00 addi s0,sp,272 - 628: 0b0b0113 addi sp,s6,176 - 62c: 0b3a slli s6,s6,0xe - 62e: 0b390b3b 0xb390b3b - 632: 1301 addi t1,t1,-32 - 634: 0000 unimp - 636: 03000d0b 0x3000d0b - 63a: 3a0e fld fs4,224(sp) - 63c: 390b3b0b 0x390b3b0b - 640: 0b13490b 0xb13490b - 644: 0c0b0d0b 0xc0b0d0b - 648: 000b380b 0xb380b - 64c: 0c00 addi s0,sp,528 - 64e: 000d c.nop 3 - 650: 0b3a0803 lb a6,179(s4) - 654: 0b390b3b 0xb390b3b - 658: 1349 addi t1,t1,-14 - 65a: 0b0d0b0b 0xb0d0b0b - 65e: 0b0c addi a1,sp,400 - 660: 0b38 addi a4,sp,408 - 662: 0000 unimp - 664: 170d addi a4,a4,-29 - 666: 0301 addi t1,t1,0 - 668: 0b0e slli s6,s6,0x3 - 66a: 3b0b3a0b 0x3b0b3a0b - 66e: 010b390b 0x10b390b - 672: 0e000013 li zero,224 - 676: 000d c.nop 3 - 678: 0b3a0803 lb a6,179(s4) - 67c: 0b390b3b 0xb390b3b - 680: 1349 addi t1,t1,-14 - 682: 0000 unimp - 684: 03000d0f 0x3000d0f - 688: 3a0e fld fs4,224(sp) - 68a: 390b3b0b 0x390b3b0b - 68e: 0013490b 0x13490b - 692: 1000 addi s0,sp,32 - 694: 012e slli sp,sp,0xb - 696: 0e03193f 0b3b0b3a 0xb3b0b3a0e03193f - 69e: 0b39 addi s6,s6,14 - 6a0: 13491927 0x13491927 - 6a4: 0111 addi sp,sp,4 - 6a6: 0612 slli a2,a2,0x4 - 6a8: 1840 addi s0,sp,52 - 6aa: 4296 lw t0,68(sp) - 6ac: 0119 addi sp,sp,6 - 6ae: 11000013 li zero,272 - 6b2: 0005 c.nop 1 - 6b4: 0b3a0803 lb a6,179(s4) - 6b8: 0b390b3b 0xb390b3b - 6bc: 1349 addi t1,t1,-14 - 6be: 1702 slli a4,a4,0x20 - 6c0: 0000 unimp - 6c2: 3412 fld fs0,288(sp) - 6c4: 0300 addi s0,sp,384 - 6c6: 3a0e fld fs4,224(sp) - 6c8: 390b3b0b 0x390b3b0b - 6cc: 0213490b 0x213490b - 6d0: 13000017 auipc zero,0x13000 - 6d4: 0034 addi a3,sp,8 - 6d6: 0b3a0e03 lb t3,179(s4) - 6da: 0b390b3b 0xb390b3b - 6de: 1349 addi t1,t1,-14 - 6e0: 0b1c addi a5,sp,400 - 6e2: 0000 unimp - 6e4: 3414 fld fa3,40(s0) - 6e6: 0300 addi s0,sp,384 - 6e8: 3a08 fld fa0,48(a2) - 6ea: 390b3b0b 0x390b3b0b - 6ee: 0213490b 0x213490b - 6f2: 15000017 auipc zero,0x15000 - 6f6: 0034 addi a3,sp,8 - 6f8: 0b3a0803 lb a6,179(s4) - 6fc: 0b390b3b 0xb390b3b - 700: 1349 addi t1,t1,-14 - 702: 0000 unimp - 704: 0b16 slli s6,s6,0x5 - 706: 5501 li a0,-32 - 708: 00130117 auipc sp,0x130 - 70c: 1700 addi s0,sp,928 - 70e: 0034 addi a3,sp,8 - 710: 0b3a0e03 lb t3,179(s4) - 714: 0b390b3b 0xb390b3b - 718: 1349 addi t1,t1,-14 - 71a: 0000 unimp - 71c: 0b18 addi a4,sp,400 - 71e: 1101 addi sp,sp,-32 - 720: 1201 addi tp,tp,-32 - 722: 0106 slli sp,sp,0x1 - 724: 19000013 li zero,400 - 728: 1755010b 0x1755010b - 72c: 0000 unimp - 72e: 0b1a slli s6,s6,0x6 - 730: 0101 addi sp,sp,0 - 732: 1b000013 li zero,432 - 736: 0000010b 0x10b - 73a: 0100 addi s0,sp,128 - 73c: 0111 addi sp,sp,4 - 73e: 0e25 addi t3,t3,9 - 740: 0e030b13 addi s6,t1,224 - 744: 01110e1b 0x1110e1b - 748: 0612 slli a2,a2,0x4 - 74a: 1710 addi a2,sp,928 - 74c: 0000 unimp - 74e: 2402 fld fs0,0(sp) - 750: 0b00 addi s0,sp,400 - 752: 030b3e0b 0x30b3e0b - 756: 000e c.slli zero,0x3 - 758: 0300 addi s0,sp,384 - 75a: 0024 addi s1,sp,8 - 75c: 0b3e0b0b 0xb3e0b0b - 760: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - 764: 1604 addi s1,sp,800 - 766: 0300 addi s0,sp,384 - 768: 3a0e fld fs4,224(sp) - 76a: 39053b0b 0x39053b0b - 76e: 0013490b 0x13490b - 772: 0500 addi s0,sp,640 - 774: 0026 c.slli zero,0x9 - 776: 1349 addi t1,t1,-14 - 778: 0000 unimp - 77a: 0106 slli sp,sp,0x1 - 77c: 4901 li s2,0 - 77e: 00130113 addi sp,t1,1 - 782: 0700 addi s0,sp,896 - 784: 0021 c.nop 8 - 786: 1349 addi t1,t1,-14 - 788: 00000b2f 0xb2f - 78c: 3408 fld fa0,40(s0) - 78e: 0300 addi s0,sp,384 - 790: 3a0e fld fs4,224(sp) - 792: 390b3b0b 0x390b3b0b - 796: 3f13490b 0x3f13490b - 79a: 3c19 jal 1b0 <_start-0x7ffffe50> - 79c: 0019 c.nop 6 - 79e: 0900 addi s0,sp,144 - 7a0: 0016 c.slli zero,0x5 - 7a2: 0b3a0e03 lb t3,179(s4) - 7a6: 0b390b3b 0xb390b3b - 7aa: 1349 addi t1,t1,-14 - 7ac: 0000 unimp - 7ae: 130a slli t1,t1,0x22 - 7b0: 0b01 addi s6,s6,0 - 7b2: 3b0b3a0b 0x3b0b3a0b - 7b6: 010b390b 0x10b390b - 7ba: 0b000013 li zero,176 - 7be: 000d c.nop 3 - 7c0: 0b3a0e03 lb t3,179(s4) - 7c4: 0b390b3b 0xb390b3b - 7c8: 1349 addi t1,t1,-14 - 7ca: 0b0d0b0b 0xb0d0b0b - 7ce: 0b0c addi a1,sp,400 - 7d0: 0b38 addi a4,sp,408 - 7d2: 0000 unimp - 7d4: 0d0c addi a1,sp,656 - 7d6: 0300 addi s0,sp,384 - 7d8: 3a08 fld fa0,48(a2) - 7da: 390b3b0b 0x390b3b0b - 7de: 0b13490b 0xb13490b - 7e2: 0c0b0d0b 0xc0b0d0b - 7e6: 000b380b 0xb380b - 7ea: 0d00 addi s0,sp,656 - 7ec: 0e030117 auipc sp,0xe030 - 7f0: 0b3a0b0b 0xb3a0b0b - 7f4: 0b390b3b 0xb390b3b - 7f8: 1301 addi t1,t1,-32 - 7fa: 0000 unimp - 7fc: 0d0e slli s10,s10,0x3 - 7fe: 0300 addi s0,sp,384 - 800: 3a08 fld fa0,48(a2) - 802: 390b3b0b 0x390b3b0b - 806: 0013490b 0x13490b - 80a: 0f00 addi s0,sp,912 - 80c: 000d c.nop 3 - 80e: 0b3a0e03 lb t3,179(s4) - 812: 0b390b3b 0xb390b3b - 816: 1349 addi t1,t1,-14 - 818: 0000 unimp - 81a: 2e10 fld fa2,24(a2) - 81c: 3f01 jal 72c <_start-0x7ffff8d4> - 81e: 0319 addi t1,t1,6 - 820: 3a0e fld fs4,224(sp) - 822: 390b3b0b 0x390b3b0b - 826: 4919270b 0x4919270b - 82a: 12011113 0x12011113 - 82e: 4006 0x4006 - 830: 9618 0x9618 - 832: 1942 slli s2,s2,0x30 - 834: 1301 addi t1,t1,-32 - 836: 0000 unimp - 838: 0511 addi a0,a0,4 - 83a: 0300 addi s0,sp,384 - 83c: 3a08 fld fa0,48(a2) - 83e: 390b3b0b 0x390b3b0b - 842: 0213490b 0x213490b - 846: 12000017 auipc zero,0x12000 - 84a: 0034 addi a3,sp,8 - 84c: 0b3a0e03 lb t3,179(s4) - 850: 0b390b3b 0xb390b3b - 854: 1349 addi t1,t1,-14 - 856: 1702 slli a4,a4,0x20 - 858: 0000 unimp - 85a: 03003413 sltiu s0,zero,48 - 85e: 3a0e fld fs4,224(sp) - 860: 390b3b0b 0x390b3b0b - 864: 1c13490b 0x1c13490b - 868: 1400000b 0x1400000b - 86c: 0034 addi a3,sp,8 - 86e: 0b3a0803 lb a6,179(s4) - 872: 0b390b3b 0xb390b3b - 876: 1349 addi t1,t1,-14 - 878: 1702 slli a4,a4,0x20 - 87a: 0000 unimp - 87c: 3415 jal 2a0 <_start-0x7ffffd60> - 87e: 0300 addi s0,sp,384 - 880: 3a08 fld fa0,48(a2) - 882: 390b3b0b 0x390b3b0b - 886: 0013490b 0x13490b - 88a: 1600 addi s0,sp,800 - 88c: 1755010b 0x1755010b - 890: 1301 addi t1,t1,-32 - 892: 0000 unimp - 894: 03003417 auipc s0,0x3003 - 898: 3a0e fld fs4,224(sp) - 89a: 390b3b0b 0x390b3b0b - 89e: 0013490b 0x13490b - 8a2: 1800 addi s0,sp,48 - 8a4: 0111010b 0x111010b - 8a8: 0612 slli a2,a2,0x4 - 8aa: 1301 addi t1,t1,-32 - 8ac: 0000 unimp - 8ae: 0b19 addi s6,s6,6 - 8b0: 5501 li a0,-32 - 8b2: 1a000017 auipc zero,0x1a000 - 8b6: 1301010b 0x1301010b - 8ba: 0000 unimp - 8bc: 00010b1b 0x10b1b - 8c0: 1c00 addi s0,sp,560 - 8c2: 0111010b 0x111010b - 8c6: 0612 slli a2,a2,0x4 - 8c8: 0000 unimp - 8ca: 011d addi sp,sp,7 - 8cc: 4901 li s2,0 - 8ce: 00000013 nop - 8d2: 1101 addi sp,sp,-32 - 8d4: 2501 jal ed4 <_start-0x7ffff12c> - 8d6: 130e slli t1,t1,0x23 - 8d8: 1b0e030b 0x1b0e030b - 8dc: 110e slli sp,sp,0x23 - 8de: 1201 addi tp,tp,-32 - 8e0: 1006 c.slli zero,0x21 - 8e2: 02000017 auipc zero,0x2000 - 8e6: 0016 c.slli zero,0x5 - 8e8: 0b3a0e03 lb t3,179(s4) - 8ec: 0b390b3b 0xb390b3b - 8f0: 1349 addi t1,t1,-14 - 8f2: 0000 unimp - 8f4: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> - 8f8: 030b3e0b 0x30b3e0b - 8fc: 0008 0x8 - 8fe: 0400 addi s0,sp,512 - 900: 0024 addi s1,sp,8 - 902: 0b3e0b0b 0xb3e0b0b - 906: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - 90a: 1605 addi a2,a2,-31 - 90c: 0300 addi s0,sp,384 - 90e: 3a0e fld fs4,224(sp) - 910: 39053b0b 0x39053b0b - 914: 0013490b 0x13490b - 918: 0600 addi s0,sp,768 - 91a: 0026 c.slli zero,0x9 - 91c: 1349 addi t1,t1,-14 - 91e: 0000 unimp - 920: 49010107 vlsseg3bu.v v2,(sp),a6,v0.t - 924: 00130113 addi sp,t1,1 - 928: 0800 addi s0,sp,16 - 92a: 0021 c.nop 8 - 92c: 1349 addi t1,t1,-14 - 92e: 00000b2f 0xb2f - 932: 3409 jal 334 <_start-0x7ffffccc> - 934: 0300 addi s0,sp,384 - 936: 3a0e fld fs4,224(sp) - 938: 390b3b0b 0x390b3b0b - 93c: 3f13490b 0x3f13490b - 940: 3c19 jal 356 <_start-0x7ffffcaa> - 942: 0019 c.nop 6 - 944: 0a00 addi s0,sp,272 - 946: 0b0b0113 addi sp,s6,176 - 94a: 0b3a slli s6,s6,0xe - 94c: 0b390b3b 0xb390b3b - 950: 1301 addi t1,t1,-32 - 952: 0000 unimp - 954: 03000d0b 0x3000d0b - 958: 3a0e fld fs4,224(sp) - 95a: 390b3b0b 0x390b3b0b - 95e: 0b13490b 0xb13490b - 962: 0c0b0d0b 0xc0b0d0b - 966: 000b380b 0xb380b - 96a: 0c00 addi s0,sp,528 - 96c: 000d c.nop 3 - 96e: 0b3a0803 lb a6,179(s4) - 972: 0b390b3b 0xb390b3b - 976: 1349 addi t1,t1,-14 - 978: 0b0d0b0b 0xb0d0b0b - 97c: 0b0c addi a1,sp,400 - 97e: 0b38 addi a4,sp,408 - 980: 0000 unimp - 982: 170d addi a4,a4,-29 - 984: 0301 addi t1,t1,0 - 986: 0b0e slli s6,s6,0x3 - 988: 3b0b3a0b 0x3b0b3a0b - 98c: 010b390b 0x10b390b - 990: 0e000013 li zero,224 - 994: 000d c.nop 3 - 996: 0b3a0803 lb a6,179(s4) - 99a: 0b390b3b 0xb390b3b - 99e: 1349 addi t1,t1,-14 - 9a0: 0000 unimp - 9a2: 03000d0f 0x3000d0f - 9a6: 3a0e fld fs4,224(sp) - 9a8: 390b3b0b 0x390b3b0b - 9ac: 0013490b 0x13490b - 9b0: 1000 addi s0,sp,32 - 9b2: 012e slli sp,sp,0xb - 9b4: 0e03193f 0b3b0b3a 0xb3b0b3a0e03193f - 9bc: 0b39 addi s6,s6,14 - 9be: 13491927 0x13491927 - 9c2: 0111 addi sp,sp,4 - 9c4: 0612 slli a2,a2,0x4 - 9c6: 1840 addi s0,sp,52 - 9c8: 01194297 auipc t0,0x1194 - 9cc: 11000013 li zero,272 - 9d0: 0005 c.nop 1 - 9d2: 0b3a0803 lb a6,179(s4) - 9d6: 0b390b3b 0xb390b3b - 9da: 1349 addi t1,t1,-14 - 9dc: 0000 unimp - 9de: 3412 fld fs0,288(sp) - 9e0: 0300 addi s0,sp,384 - 9e2: 3a0e fld fs4,224(sp) - 9e4: 390b3b0b 0x390b3b0b - 9e8: 1c13490b 0x1c13490b - 9ec: 1300000b 0x1300000b - 9f0: 0034 addi a3,sp,8 - 9f2: 0b3a0803 lb a6,179(s4) - 9f6: 0b390b3b 0xb390b3b - 9fa: 1349 addi t1,t1,-14 - 9fc: 0000 unimp - 9fe: 3414 fld fa3,40(s0) - a00: 0300 addi s0,sp,384 - a02: 3a08 fld fa0,48(a2) - a04: 390b3b0b 0x390b3b0b - a08: 0213490b 0x213490b - a0c: 0018 0x18 - a0e: 1500 addi s0,sp,672 - a10: 0034 addi a3,sp,8 - a12: 0b3a0803 lb a6,179(s4) - a16: 0b390b3b 0xb390b3b - a1a: 1349 addi t1,t1,-14 - a1c: 1702 slli a4,a4,0x20 - a1e: 0000 unimp - a20: 0b16 slli s6,s6,0x5 - a22: 5501 li a0,-32 - a24: 00130117 auipc sp,0x130 - a28: 1700 addi s0,sp,928 - a2a: 0034 addi a3,sp,8 - a2c: 0b3a0e03 lb t3,179(s4) - a30: 0b390b3b 0xb390b3b - a34: 1349 addi t1,t1,-14 - a36: 1802 slli a6,a6,0x20 - a38: 0000 unimp - a3a: 0b18 addi a4,sp,400 - a3c: 0101 addi sp,sp,0 - a3e: 19000013 li zero,400 - a42: 0034 addi a3,sp,8 - a44: 0b3a0e03 lb t3,179(s4) - a48: 0b390b3b 0xb390b3b - a4c: 1349 addi t1,t1,-14 - a4e: 0000 unimp - a50: 0b1a slli s6,s6,0x6 - a52: 0001 nop - a54: 1b00 addi s0,sp,432 - a56: 0101 addi sp,sp,0 - a58: 1349 addi t1,t1,-14 - a5a: 0000 unimp - a5c: 0100 addi s0,sp,128 - a5e: 0111 addi sp,sp,4 - a60: 0e25 addi t3,t3,9 - a62: 0e030b13 addi s6,t1,224 - a66: 01110e1b 0x1110e1b - a6a: 0612 slli a2,a2,0x4 - a6c: 1710 addi a2,sp,928 - a6e: 0000 unimp - a70: 1602 slli a2,a2,0x20 - a72: 0300 addi s0,sp,384 - a74: 3a0e fld fs4,224(sp) - a76: 390b3b0b 0x390b3b0b - a7a: 0013490b 0x13490b - a7e: 0300 addi s0,sp,384 - a80: 0024 addi s1,sp,8 - a82: 0b3e0b0b 0xb3e0b0b - a86: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - a8a: 2404 fld fs1,8(s0) - a8c: 0b00 addi s0,sp,400 - a8e: 030b3e0b 0x30b3e0b - a92: 000e c.slli zero,0x3 - a94: 0500 addi s0,sp,640 - a96: 0016 c.slli zero,0x5 - a98: 0b3a0e03 lb t3,179(s4) - a9c: 0b39053b 0xb39053b - aa0: 1349 addi t1,t1,-14 - aa2: 0000 unimp - aa4: 2606 fld fa2,64(sp) - aa6: 4900 lw s0,16(a0) - aa8: 07000013 li zero,112 - aac: 0101 addi sp,sp,0 - aae: 1349 addi t1,t1,-14 - ab0: 1301 addi t1,t1,-32 - ab2: 0000 unimp - ab4: 2108 fld fa0,0(a0) - ab6: 4900 lw s0,16(a0) - ab8: 000b2f13 slti t5,s6,0 - abc: 0900 addi s0,sp,144 - abe: 0034 addi a3,sp,8 - ac0: 0b3a0e03 lb t3,179(s4) - ac4: 0b390b3b 0xb390b3b - ac8: 1349 addi t1,t1,-14 - aca: 193c193f 130a0000 0x130a0000193c193f - ad2: 0b01 addi s6,s6,0 - ad4: 3b0b3a0b 0x3b0b3a0b - ad8: 010b390b 0x10b390b - adc: 0b000013 li zero,176 - ae0: 000d c.nop 3 - ae2: 0b3a0e03 lb t3,179(s4) - ae6: 0b390b3b 0xb390b3b - aea: 1349 addi t1,t1,-14 - aec: 0b0d0b0b 0xb0d0b0b - af0: 0b0c addi a1,sp,400 - af2: 0b38 addi a4,sp,408 - af4: 0000 unimp - af6: 0d0c addi a1,sp,656 - af8: 0300 addi s0,sp,384 - afa: 3a08 fld fa0,48(a2) - afc: 390b3b0b 0x390b3b0b - b00: 0b13490b 0xb13490b - b04: 0c0b0d0b 0xc0b0d0b - b08: 000b380b 0xb380b - b0c: 0d00 addi s0,sp,656 - b0e: 0e030117 auipc sp,0xe030 - b12: 0b3a0b0b 0xb3a0b0b - b16: 0b390b3b 0xb390b3b - b1a: 1301 addi t1,t1,-32 - b1c: 0000 unimp - b1e: 0d0e slli s10,s10,0x3 - b20: 0300 addi s0,sp,384 - b22: 3a08 fld fa0,48(a2) - b24: 390b3b0b 0x390b3b0b - b28: 0013490b 0x13490b - b2c: 0f00 addi s0,sp,912 - b2e: 000d c.nop 3 - b30: 0b3a0e03 lb t3,179(s4) - b34: 0b390b3b 0xb390b3b - b38: 1349 addi t1,t1,-14 - b3a: 0000 unimp - b3c: 2e10 fld fa2,24(a2) - b3e: 3f01 jal a4e <_start-0x7ffff5b2> - b40: 0319 addi t1,t1,6 - b42: 3a0e fld fs4,224(sp) - b44: 390b3b0b 0x390b3b0b - b48: 4919270b 0x4919270b - b4c: 12011113 0x12011113 - b50: 4006 0x4006 - b52: 9718 0x9718 - b54: 1942 slli s2,s2,0x30 - b56: 1301 addi t1,t1,-32 - b58: 0000 unimp - b5a: 0511 addi a0,a0,4 - b5c: 0300 addi s0,sp,384 - b5e: 3a08 fld fa0,48(a2) - b60: 390b3b0b 0x390b3b0b - b64: 0013490b 0x13490b - b68: 1200 addi s0,sp,288 - b6a: 0034 addi a3,sp,8 - b6c: 0b3a0e03 lb t3,179(s4) - b70: 0b390b3b 0xb390b3b - b74: 1349 addi t1,t1,-14 - b76: 0b1c addi a5,sp,400 - b78: 0000 unimp - b7a: 03003413 sltiu s0,zero,48 - b7e: 3a08 fld fa0,48(a2) - b80: 390b3b0b 0x390b3b0b - b84: 0013490b 0x13490b - b88: 1400 addi s0,sp,544 - b8a: 0034 addi a3,sp,8 - b8c: 0b3a0803 lb a6,179(s4) - b90: 0b390b3b 0xb390b3b - b94: 1349 addi t1,t1,-14 - b96: 1702 slli a4,a4,0x20 - b98: 0000 unimp - b9a: 3415 jal 5be <_start-0x7ffffa42> - b9c: 0300 addi s0,sp,384 - b9e: 3a08 fld fa0,48(a2) - ba0: 390b3b0b 0x390b3b0b - ba4: 0213490b 0x213490b - ba8: 0018 0x18 - baa: 1600 addi s0,sp,800 - bac: 1755010b 0x1755010b - bb0: 1301 addi t1,t1,-32 - bb2: 0000 unimp - bb4: 03003417 auipc s0,0x3003 - bb8: 3a0e fld fs4,224(sp) - bba: 390b3b0b 0x390b3b0b - bbe: 0213490b 0x213490b - bc2: 0018 0x18 - bc4: 1800 addi s0,sp,48 - bc6: 1301010b 0x1301010b - bca: 0000 unimp - bcc: 3419 jal 5d2 <_start-0x7ffffa2e> - bce: 0300 addi s0,sp,384 - bd0: 3a0e fld fs4,224(sp) - bd2: 390b3b0b 0x390b3b0b - bd6: 0013490b 0x13490b - bda: 1a00 addi s0,sp,304 - bdc: 1755010b 0x1755010b - be0: 0000 unimp - be2: 0300341b 0x300341b - be6: 3a0e fld fs4,224(sp) - be8: 390b3b0b 0x390b3b0b - bec: 0213490b 0x213490b - bf0: 1c000017 auipc zero,0x1c000 - bf4: 0101 addi sp,sp,0 - bf6: 1349 addi t1,t1,-14 - bf8: 0000 unimp - bfa: 0100 addi s0,sp,128 - bfc: 0111 addi sp,sp,4 - bfe: 0e25 addi t3,t3,9 - c00: 0e030b13 addi s6,t1,224 - c04: 01110e1b 0x1110e1b - c08: 0612 slli a2,a2,0x4 - c0a: 1710 addi a2,sp,928 - c0c: 0000 unimp - c0e: 1602 slli a2,a2,0x20 - c10: 0300 addi s0,sp,384 - c12: 3a0e fld fs4,224(sp) - c14: 390b3b0b 0x390b3b0b - c18: 0013490b 0x13490b - c1c: 0300 addi s0,sp,384 - c1e: 0024 addi s1,sp,8 - c20: 0b3e0b0b 0xb3e0b0b - c24: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - c28: 2404 fld fs1,8(s0) - c2a: 0b00 addi s0,sp,400 - c2c: 030b3e0b 0x30b3e0b - c30: 000e c.slli zero,0x3 - c32: 0500 addi s0,sp,640 - c34: 0016 c.slli zero,0x5 - c36: 0b3a0e03 lb t3,179(s4) - c3a: 0b39053b 0xb39053b - c3e: 1349 addi t1,t1,-14 - c40: 0000 unimp - c42: 2606 fld fa2,64(sp) - c44: 4900 lw s0,16(a0) - c46: 07000013 li zero,112 - c4a: 0101 addi sp,sp,0 - c4c: 1349 addi t1,t1,-14 - c4e: 1301 addi t1,t1,-32 - c50: 0000 unimp - c52: 2108 fld fa0,0(a0) - c54: 4900 lw s0,16(a0) - c56: 000b2f13 slti t5,s6,0 - c5a: 0900 addi s0,sp,144 - c5c: 0034 addi a3,sp,8 - c5e: 0b3a0e03 lb t3,179(s4) - c62: 0b390b3b 0xb390b3b - c66: 1349 addi t1,t1,-14 - c68: 193c193f 130a0000 0x130a0000193c193f - c70: 0b01 addi s6,s6,0 - c72: 3b0b3a0b 0x3b0b3a0b - c76: 010b390b 0x10b390b - c7a: 0b000013 li zero,176 - c7e: 000d c.nop 3 - c80: 0b3a0e03 lb t3,179(s4) - c84: 0b390b3b 0xb390b3b - c88: 1349 addi t1,t1,-14 - c8a: 0b0d0b0b 0xb0d0b0b - c8e: 0b0c addi a1,sp,400 - c90: 0b38 addi a4,sp,408 - c92: 0000 unimp - c94: 0d0c addi a1,sp,656 - c96: 0300 addi s0,sp,384 - c98: 3a08 fld fa0,48(a2) - c9a: 390b3b0b 0x390b3b0b - c9e: 0b13490b 0xb13490b - ca2: 0c0b0d0b 0xc0b0d0b - ca6: 000b380b 0xb380b - caa: 0d00 addi s0,sp,656 - cac: 0e030117 auipc sp,0xe030 - cb0: 0b3a0b0b 0xb3a0b0b - cb4: 0b390b3b 0xb390b3b - cb8: 1301 addi t1,t1,-32 - cba: 0000 unimp - cbc: 0d0e slli s10,s10,0x3 - cbe: 0300 addi s0,sp,384 - cc0: 3a08 fld fa0,48(a2) - cc2: 390b3b0b 0x390b3b0b - cc6: 0013490b 0x13490b - cca: 0f00 addi s0,sp,912 - ccc: 000d c.nop 3 - cce: 0b3a0e03 lb t3,179(s4) - cd2: 0b390b3b 0xb390b3b - cd6: 1349 addi t1,t1,-14 - cd8: 0000 unimp - cda: 2e10 fld fa2,24(a2) - cdc: 3f01 jal bec <_start-0x7ffff414> - cde: 0319 addi t1,t1,6 - ce0: 3a0e fld fs4,224(sp) - ce2: 390b3b0b 0x390b3b0b - ce6: 4919270b 0x4919270b - cea: 12011113 0x12011113 - cee: 4006 0x4006 - cf0: 9718 0x9718 - cf2: 1942 slli s2,s2,0x30 - cf4: 1301 addi t1,t1,-32 - cf6: 0000 unimp - cf8: 0511 addi a0,a0,4 - cfa: 0300 addi s0,sp,384 - cfc: 3a08 fld fa0,48(a2) - cfe: 390b3b0b 0x390b3b0b - d02: 0013490b 0x13490b - d06: 1200 addi s0,sp,288 - d08: 0034 addi a3,sp,8 - d0a: 0b3a0e03 lb t3,179(s4) - d0e: 0b390b3b 0xb390b3b - d12: 1349 addi t1,t1,-14 - d14: 0b1c addi a5,sp,400 - d16: 0000 unimp - d18: 03003413 sltiu s0,zero,48 - d1c: 3a08 fld fa0,48(a2) - d1e: 390b3b0b 0x390b3b0b - d22: 0013490b 0x13490b - d26: 1400 addi s0,sp,544 - d28: 0034 addi a3,sp,8 - d2a: 0b3a0803 lb a6,179(s4) - d2e: 0b390b3b 0xb390b3b - d32: 1349 addi t1,t1,-14 - d34: 1702 slli a4,a4,0x20 - d36: 0000 unimp - d38: 3415 jal 75c <_start-0x7ffff8a4> - d3a: 0300 addi s0,sp,384 - d3c: 3a08 fld fa0,48(a2) - d3e: 390b3b0b 0x390b3b0b - d42: 0213490b 0x213490b - d46: 0018 0x18 - d48: 1600 addi s0,sp,800 - d4a: 1755010b 0x1755010b - d4e: 1301 addi t1,t1,-32 - d50: 0000 unimp - d52: 03003417 auipc s0,0x3003 - d56: 3a0e fld fs4,224(sp) - d58: 390b3b0b 0x390b3b0b - d5c: 0213490b 0x213490b - d60: 0018 0x18 - d62: 1800 addi s0,sp,48 - d64: 1301010b 0x1301010b - d68: 0000 unimp - d6a: 3419 jal 770 <_start-0x7ffff890> - d6c: 0300 addi s0,sp,384 - d6e: 3a0e fld fs4,224(sp) - d70: 390b3b0b 0x390b3b0b - d74: 0013490b 0x13490b - d78: 1a00 addi s0,sp,304 - d7a: 1755010b 0x1755010b - d7e: 0000 unimp - d80: 0300341b 0x300341b - d84: 3a0e fld fs4,224(sp) - d86: 390b3b0b 0x390b3b0b - d8a: 0213490b 0x213490b - d8e: 1c000017 auipc zero,0x1c000 - d92: 0101 addi sp,sp,0 - d94: 1349 addi t1,t1,-14 - d96: 0000 unimp - d98: 0100 addi s0,sp,128 - d9a: 0111 addi sp,sp,4 - d9c: 0e25 addi t3,t3,9 - d9e: 0e030b13 addi s6,t1,224 - da2: 01110e1b 0x1110e1b - da6: 0612 slli a2,a2,0x4 - da8: 1710 addi a2,sp,928 - daa: 0000 unimp - dac: 2402 fld fs0,0(sp) - dae: 0b00 addi s0,sp,400 - db0: 030b3e0b 0x30b3e0b - db4: 0008 0x8 - db6: 0300 addi s0,sp,384 - db8: 0024 addi s1,sp,8 - dba: 0b3e0b0b 0xb3e0b0b - dbe: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - dc2: 1604 addi s1,sp,800 - dc4: 0300 addi s0,sp,384 - dc6: 3a0e fld fs4,224(sp) - dc8: 39053b0b 0x39053b0b - dcc: 0013490b 0x13490b - dd0: 0500 addi s0,sp,640 - dd2: 0026 c.slli zero,0x9 - dd4: 1349 addi t1,t1,-14 - dd6: 0000 unimp - dd8: 0106 slli sp,sp,0x1 - dda: 4901 li s2,0 - ddc: 00130113 addi sp,t1,1 - de0: 0700 addi s0,sp,896 - de2: 0021 c.nop 8 - de4: 1349 addi t1,t1,-14 - de6: 00000b2f 0xb2f - dea: 3408 fld fa0,40(s0) - dec: 0300 addi s0,sp,384 - dee: 3a0e fld fs4,224(sp) - df0: 390b3b0b 0x390b3b0b - df4: 3f13490b 0x3f13490b - df8: 3c19 jal 80e <_start-0x7ffff7f2> - dfa: 0019 c.nop 6 - dfc: 0900 addi s0,sp,144 - dfe: 0016 c.slli zero,0x5 - e00: 0b3a0e03 lb t3,179(s4) - e04: 0b390b3b 0xb390b3b - e08: 1349 addi t1,t1,-14 - e0a: 0000 unimp - e0c: 130a slli t1,t1,0x22 - e0e: 0b01 addi s6,s6,0 - e10: 3b0b3a0b 0x3b0b3a0b - e14: 010b390b 0x10b390b - e18: 0b000013 li zero,176 - e1c: 000d c.nop 3 - e1e: 0b3a0e03 lb t3,179(s4) - e22: 0b390b3b 0xb390b3b - e26: 1349 addi t1,t1,-14 - e28: 0b0d0b0b 0xb0d0b0b - e2c: 0b0c addi a1,sp,400 - e2e: 0b38 addi a4,sp,408 - e30: 0000 unimp - e32: 0d0c addi a1,sp,656 - e34: 0300 addi s0,sp,384 - e36: 3a08 fld fa0,48(a2) - e38: 390b3b0b 0x390b3b0b - e3c: 0b13490b 0xb13490b - e40: 0c0b0d0b 0xc0b0d0b - e44: 000b380b 0xb380b - e48: 0d00 addi s0,sp,656 - e4a: 0e030117 auipc sp,0xe030 - e4e: 0b3a0b0b 0xb3a0b0b - e52: 0b390b3b 0xb390b3b - e56: 1301 addi t1,t1,-32 - e58: 0000 unimp - e5a: 0d0e slli s10,s10,0x3 - e5c: 0300 addi s0,sp,384 - e5e: 3a08 fld fa0,48(a2) - e60: 390b3b0b 0x390b3b0b - e64: 0013490b 0x13490b - e68: 0f00 addi s0,sp,912 - e6a: 000d c.nop 3 - e6c: 0b3a0e03 lb t3,179(s4) - e70: 0b390b3b 0xb390b3b - e74: 1349 addi t1,t1,-14 - e76: 0000 unimp - e78: 2e10 fld fa2,24(a2) - e7a: 3f01 jal d8a <_start-0x7ffff276> - e7c: 0319 addi t1,t1,6 - e7e: 3a0e fld fs4,224(sp) - e80: 390b3b0b 0x390b3b0b - e84: 4919270b 0x4919270b - e88: 12011113 0x12011113 - e8c: 4006 0x4006 - e8e: 9618 0x9618 - e90: 1942 slli s2,s2,0x30 - e92: 1301 addi t1,t1,-32 - e94: 0000 unimp - e96: 0511 addi a0,a0,4 - e98: 0300 addi s0,sp,384 - e9a: 3a08 fld fa0,48(a2) - e9c: 390b3b0b 0x390b3b0b - ea0: 0013490b 0x13490b - ea4: 1200 addi s0,sp,288 - ea6: 0034 addi a3,sp,8 - ea8: 0b3a0e03 lb t3,179(s4) - eac: 0b390b3b 0xb390b3b - eb0: 1349 addi t1,t1,-14 - eb2: 1702 slli a4,a4,0x20 - eb4: 0000 unimp - eb6: 03003413 sltiu s0,zero,48 - eba: 3a0e fld fs4,224(sp) - ebc: 390b3b0b 0x390b3b0b - ec0: 1c13490b 0x1c13490b - ec4: 1400000b 0x1400000b - ec8: 0034 addi a3,sp,8 - eca: 0b3a0803 lb a6,179(s4) - ece: 0b390b3b 0xb390b3b - ed2: 1349 addi t1,t1,-14 - ed4: 1702 slli a4,a4,0x20 - ed6: 0000 unimp - ed8: 3415 jal 8fc <_start-0x7ffff704> - eda: 0300 addi s0,sp,384 - edc: 3a08 fld fa0,48(a2) - ede: 390b3b0b 0x390b3b0b - ee2: 0213490b 0x213490b - ee6: 0018 0x18 - ee8: 1600 addi s0,sp,800 - eea: 1755010b 0x1755010b - eee: 1301 addi t1,t1,-32 - ef0: 0000 unimp - ef2: 03003417 auipc s0,0x3003 - ef6: 3a0e fld fs4,224(sp) - ef8: 390b3b0b 0x390b3b0b - efc: 0213490b 0x213490b - f00: 0018 0x18 - f02: 1800 addi s0,sp,48 - f04: 1755010b 0x1755010b - f08: 0000 unimp - f0a: 3419 jal 910 <_start-0x7ffff6f0> - f0c: 0300 addi s0,sp,384 - f0e: 3a0e fld fs4,224(sp) - f10: 390b3b0b 0x390b3b0b - f14: 0013490b 0x13490b - f18: 1a00 addi s0,sp,304 - f1a: 0111010b 0x111010b - f1e: 0612 slli a2,a2,0x4 - f20: 1301 addi t1,t1,-32 - f22: 0000 unimp - f24: 11010b1b 0x11010b1b - f28: 1201 addi tp,tp,-32 - f2a: 0006 c.slli zero,0x1 - f2c: 1c00 addi s0,sp,560 - f2e: 1301010b 0x1301010b - f32: 0000 unimp - f34: 0b1d addi s6,s6,7 - f36: 0001 nop - f38: 1e00 addi s0,sp,816 - f3a: 0101 addi sp,sp,0 - f3c: 1349 addi t1,t1,-14 - f3e: 0000 unimp - f40: 0100 addi s0,sp,128 - f42: 0111 addi sp,sp,4 - f44: 0e25 addi t3,t3,9 - f46: 0e030b13 addi s6,t1,224 - f4a: 01110e1b 0x1110e1b - f4e: 0612 slli a2,a2,0x4 - f50: 1710 addi a2,sp,928 - f52: 0000 unimp - f54: 2402 fld fs0,0(sp) - f56: 0b00 addi s0,sp,400 - f58: 030b3e0b 0x30b3e0b - f5c: 0008 0x8 - f5e: 0300 addi s0,sp,384 - f60: 0024 addi s1,sp,8 - f62: 0b3e0b0b 0xb3e0b0b - f66: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - f6a: 1604 addi s1,sp,800 - f6c: 0300 addi s0,sp,384 - f6e: 3a0e fld fs4,224(sp) - f70: 39053b0b 0x39053b0b - f74: 0013490b 0x13490b - f78: 0500 addi s0,sp,640 - f7a: 0026 c.slli zero,0x9 - f7c: 1349 addi t1,t1,-14 - f7e: 0000 unimp - f80: 0106 slli sp,sp,0x1 - f82: 4901 li s2,0 - f84: 00130113 addi sp,t1,1 - f88: 0700 addi s0,sp,896 - f8a: 0021 c.nop 8 - f8c: 1349 addi t1,t1,-14 - f8e: 00000b2f 0xb2f - f92: 3408 fld fa0,40(s0) - f94: 0300 addi s0,sp,384 - f96: 3a0e fld fs4,224(sp) - f98: 390b3b0b 0x390b3b0b - f9c: 3f13490b 0x3f13490b - fa0: 3c19 jal 9b6 <_start-0x7ffff64a> - fa2: 0019 c.nop 6 - fa4: 0900 addi s0,sp,144 - fa6: 0016 c.slli zero,0x5 - fa8: 0b3a0e03 lb t3,179(s4) - fac: 0b390b3b 0xb390b3b - fb0: 1349 addi t1,t1,-14 - fb2: 0000 unimp - fb4: 130a slli t1,t1,0x22 - fb6: 0b01 addi s6,s6,0 - fb8: 3b0b3a0b 0x3b0b3a0b - fbc: 010b390b 0x10b390b - fc0: 0b000013 li zero,176 - fc4: 000d c.nop 3 - fc6: 0b3a0e03 lb t3,179(s4) - fca: 0b390b3b 0xb390b3b - fce: 1349 addi t1,t1,-14 - fd0: 0b0d0b0b 0xb0d0b0b - fd4: 0b0c addi a1,sp,400 - fd6: 0b38 addi a4,sp,408 - fd8: 0000 unimp - fda: 0d0c addi a1,sp,656 - fdc: 0300 addi s0,sp,384 - fde: 3a08 fld fa0,48(a2) - fe0: 390b3b0b 0x390b3b0b - fe4: 0b13490b 0xb13490b - fe8: 0c0b0d0b 0xc0b0d0b - fec: 000b380b 0xb380b - ff0: 0d00 addi s0,sp,656 - ff2: 0e030117 auipc sp,0xe030 - ff6: 0b3a0b0b 0xb3a0b0b - ffa: 0b390b3b 0xb390b3b - ffe: 1301 addi t1,t1,-32 - 1000: 0000 unimp - 1002: 0d0e slli s10,s10,0x3 - 1004: 0300 addi s0,sp,384 - 1006: 3a08 fld fa0,48(a2) - 1008: 390b3b0b 0x390b3b0b - 100c: 0013490b 0x13490b - 1010: 0f00 addi s0,sp,912 - 1012: 000d c.nop 3 - 1014: 0b3a0e03 lb t3,179(s4) - 1018: 0b390b3b 0xb390b3b - 101c: 1349 addi t1,t1,-14 - 101e: 0000 unimp - 1020: 2e10 fld fa2,24(a2) - 1022: 3f01 jal f32 <_start-0x7ffff0ce> - 1024: 0319 addi t1,t1,6 - 1026: 3a0e fld fs4,224(sp) - 1028: 390b3b0b 0x390b3b0b - 102c: 4919270b 0x4919270b - 1030: 12011113 0x12011113 - 1034: 4006 0x4006 - 1036: 9618 0x9618 - 1038: 1942 slli s2,s2,0x30 - 103a: 1301 addi t1,t1,-32 - 103c: 0000 unimp - 103e: 0511 addi a0,a0,4 - 1040: 0300 addi s0,sp,384 - 1042: 3a08 fld fa0,48(a2) - 1044: 390b3b0b 0x390b3b0b - 1048: 0013490b 0x13490b - 104c: 1200 addi s0,sp,288 - 104e: 0034 addi a3,sp,8 - 1050: 0b3a0e03 lb t3,179(s4) - 1054: 0b390b3b 0xb390b3b - 1058: 1349 addi t1,t1,-14 - 105a: 1702 slli a4,a4,0x20 - 105c: 0000 unimp - 105e: 03003413 sltiu s0,zero,48 - 1062: 3a0e fld fs4,224(sp) - 1064: 390b3b0b 0x390b3b0b - 1068: 1c13490b 0x1c13490b - 106c: 1400000b 0x1400000b - 1070: 0034 addi a3,sp,8 - 1072: 0b3a0803 lb a6,179(s4) - 1076: 0b390b3b 0xb390b3b - 107a: 1349 addi t1,t1,-14 - 107c: 0000 unimp - 107e: 3415 jal aa2 <_start-0x7ffff55e> - 1080: 0300 addi s0,sp,384 - 1082: 3a08 fld fa0,48(a2) - 1084: 390b3b0b 0x390b3b0b - 1088: 0213490b 0x213490b - 108c: 16000017 auipc zero,0x16000 - 1090: 0034 addi a3,sp,8 - 1092: 0b3a0803 lb a6,179(s4) - 1096: 0b390b3b 0xb390b3b - 109a: 1349 addi t1,t1,-14 - 109c: 1802 slli a6,a6,0x20 - 109e: 0000 unimp - 10a0: 55010b17 auipc s6,0x55010 - 10a4: 00130117 auipc sp,0x130 - 10a8: 1800 addi s0,sp,48 - 10aa: 0034 addi a3,sp,8 - 10ac: 0b3a0e03 lb t3,179(s4) - 10b0: 0b390b3b 0xb390b3b - 10b4: 1349 addi t1,t1,-14 - 10b6: 1802 slli a6,a6,0x20 - 10b8: 0000 unimp - 10ba: 0a19 addi s4,s4,6 - 10bc: 0300 addi s0,sp,384 - 10be: 3a0e fld fs4,224(sp) - 10c0: 390b3b0b 0x390b3b0b - 10c4: 0001110b 0x1110b - 10c8: 1a00 addi s0,sp,304 - 10ca: 0111010b 0x111010b - 10ce: 0612 slli a2,a2,0x4 - 10d0: 1301 addi t1,t1,-32 - 10d2: 0000 unimp - 10d4: 55010b1b 0x55010b1b - 10d8: 1c000017 auipc zero,0x1c000 - 10dc: 1301010b 0x1301010b - 10e0: 0000 unimp - 10e2: 341d jal b08 <_start-0x7ffff4f8> - 10e4: 0300 addi s0,sp,384 - 10e6: 3a0e fld fs4,224(sp) - 10e8: 390b3b0b 0x390b3b0b - 10ec: 0013490b 0x13490b - 10f0: 1e00 addi s0,sp,816 - 10f2: 0000010b 0x10b - 10f6: 011f 4901 0013 0x134901011f - 10fc: 0000 unimp - 10fe: 1101 addi sp,sp,-32 - 1100: 2501 jal 1700 <_start-0x7fffe900> - 1102: 130e slli t1,t1,0x23 - 1104: 1b0e030b 0x1b0e030b - 1108: 110e slli sp,sp,0x23 - 110a: 1201 addi tp,tp,-32 - 110c: 1006 c.slli zero,0x21 - 110e: 02000017 auipc zero,0x2000 - 1112: 0024 addi s1,sp,8 - 1114: 0b3e0b0b 0xb3e0b0b - 1118: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - 111c: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> - 1120: 030b3e0b 0x30b3e0b - 1124: 000e c.slli zero,0x3 - 1126: 0400 addi s0,sp,512 - 1128: 0016 c.slli zero,0x5 - 112a: 0b3a0e03 lb t3,179(s4) - 112e: 0b39053b 0xb39053b - 1132: 1349 addi t1,t1,-14 - 1134: 0000 unimp - 1136: 2605 jal 1456 <_start-0x7fffebaa> - 1138: 4900 lw s0,16(a0) - 113a: 06000013 li zero,96 - 113e: 0101 addi sp,sp,0 - 1140: 1349 addi t1,t1,-14 - 1142: 1301 addi t1,t1,-32 - 1144: 0000 unimp - 1146: 49002107 flw ft2,1168(zero) # 490 <_start-0x7ffffb70> - 114a: 000b2f13 slti t5,s6,0 - 114e: 0800 addi s0,sp,16 - 1150: 0034 addi a3,sp,8 - 1152: 0b3a0e03 lb t3,179(s4) - 1156: 0b390b3b 0xb390b3b - 115a: 1349 addi t1,t1,-14 - 115c: 193c193f 16090000 0x16090000193c193f - 1164: 0300 addi s0,sp,384 - 1166: 3a0e fld fs4,224(sp) - 1168: 390b3b0b 0x390b3b0b - 116c: 0013490b 0x13490b - 1170: 0a00 addi s0,sp,272 - 1172: 0b0b0113 addi sp,s6,176 # 55011150 <_start-0x2afeeeb0> - 1176: 0b3a slli s6,s6,0xe - 1178: 0b390b3b 0xb390b3b - 117c: 1301 addi t1,t1,-32 - 117e: 0000 unimp - 1180: 03000d0b 0x3000d0b - 1184: 3a0e fld fs4,224(sp) - 1186: 390b3b0b 0x390b3b0b - 118a: 0b13490b 0xb13490b - 118e: 0c0b0d0b 0xc0b0d0b - 1192: 000b380b 0xb380b - 1196: 0c00 addi s0,sp,528 - 1198: 000d c.nop 3 - 119a: 0b3a0803 lb a6,179(s4) - 119e: 0b390b3b 0xb390b3b - 11a2: 1349 addi t1,t1,-14 - 11a4: 0b0d0b0b 0xb0d0b0b - 11a8: 0b0c addi a1,sp,400 - 11aa: 0b38 addi a4,sp,408 - 11ac: 0000 unimp - 11ae: 170d addi a4,a4,-29 - 11b0: 0301 addi t1,t1,0 - 11b2: 0b0e slli s6,s6,0x3 - 11b4: 3b0b3a0b 0x3b0b3a0b - 11b8: 010b390b 0x10b390b - 11bc: 0e000013 li zero,224 - 11c0: 000d c.nop 3 - 11c2: 0b3a0803 lb a6,179(s4) - 11c6: 0b390b3b 0xb390b3b - 11ca: 1349 addi t1,t1,-14 - 11cc: 0000 unimp - 11ce: 03000d0f 0x3000d0f - 11d2: 3a0e fld fs4,224(sp) - 11d4: 390b3b0b 0x390b3b0b - 11d8: 0013490b 0x13490b - 11dc: 1000 addi s0,sp,32 - 11de: 012e slli sp,sp,0xb - 11e0: 0e03193f 0b3b0b3a 0xb3b0b3a0e03193f - 11e8: 0b39 addi s6,s6,14 - 11ea: 13491927 0x13491927 - 11ee: 0111 addi sp,sp,4 - 11f0: 0612 slli a2,a2,0x4 - 11f2: 1840 addi s0,sp,52 - 11f4: 01194297 auipc t0,0x1194 - 11f8: 11000013 li zero,272 - 11fc: 0005 c.nop 1 - 11fe: 0b3a0803 lb a6,179(s4) - 1202: 0b390b3b 0xb390b3b - 1206: 1349 addi t1,t1,-14 - 1208: 0000 unimp - 120a: 3412 fld fs0,288(sp) - 120c: 0300 addi s0,sp,384 - 120e: 3a0e fld fs4,224(sp) - 1210: 390b3b0b 0x390b3b0b - 1214: 1c13490b 0x1c13490b - 1218: 1300000b 0x1300000b - 121c: 0034 addi a3,sp,8 - 121e: 0b3a0803 lb a6,179(s4) - 1222: 0b390b3b 0xb390b3b - 1226: 1349 addi t1,t1,-14 - 1228: 0000 unimp - 122a: 3414 fld fa3,40(s0) - 122c: 0300 addi s0,sp,384 - 122e: 3a08 fld fa0,48(a2) - 1230: 390b3b0b 0x390b3b0b - 1234: 0213490b 0x213490b - 1238: 0018 0x18 - 123a: 1500 addi s0,sp,672 - 123c: 0034 addi a3,sp,8 - 123e: 0b3a0803 lb a6,179(s4) - 1242: 0b390b3b 0xb390b3b - 1246: 1349 addi t1,t1,-14 - 1248: 1702 slli a4,a4,0x20 - 124a: 0000 unimp - 124c: 0b16 slli s6,s6,0x5 - 124e: 5501 li a0,-32 - 1250: 00130117 auipc sp,0x130 - 1254: 1700 addi s0,sp,928 - 1256: 0034 addi a3,sp,8 - 1258: 0b3a0e03 lb t3,179(s4) - 125c: 0b390b3b 0xb390b3b - 1260: 1349 addi t1,t1,-14 - 1262: 1802 slli a6,a6,0x20 - 1264: 0000 unimp - 1266: 0b18 addi a4,sp,400 - 1268: 0101 addi sp,sp,0 - 126a: 19000013 li zero,400 - 126e: 0034 addi a3,sp,8 - 1270: 0b3a0e03 lb t3,179(s4) - 1274: 0b390b3b 0xb390b3b - 1278: 1349 addi t1,t1,-14 - 127a: 0000 unimp - 127c: 0b1a slli s6,s6,0x6 - 127e: 0001 nop - 1280: 1b00 addi s0,sp,432 - 1282: 0111010b 0x111010b - 1286: 0612 slli a2,a2,0x4 - 1288: 0000 unimp - 128a: 341c fld fa5,40(s0) - 128c: 0300 addi s0,sp,384 - 128e: 3a0e fld fs4,224(sp) - 1290: 390b3b0b 0x390b3b0b - 1294: 0213490b 0x213490b - 1298: 1d000017 auipc zero,0x1d000 - 129c: 1755010b 0x1755010b - 12a0: 0000 unimp - 12a2: 011e slli sp,sp,0x7 - 12a4: 4901 li s2,0 - 12a6: 00000013 nop - 12aa: 1101 addi sp,sp,-32 - 12ac: 2501 jal 18ac <_start-0x7fffe754> - 12ae: 130e slli t1,t1,0x23 - 12b0: 1b0e030b 0x1b0e030b - 12b4: 110e slli sp,sp,0x23 - 12b6: 1201 addi tp,tp,-32 - 12b8: 1006 c.slli zero,0x21 - 12ba: 02000017 auipc zero,0x2000 - 12be: 0024 addi s1,sp,8 - 12c0: 0b3e0b0b 0xb3e0b0b - 12c4: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - 12c8: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> - 12cc: 030b3e0b 0x30b3e0b - 12d0: 000e c.slli zero,0x3 - 12d2: 0400 addi s0,sp,512 - 12d4: 0016 c.slli zero,0x5 - 12d6: 0b3a0e03 lb t3,179(s4) - 12da: 0b39053b 0xb39053b - 12de: 1349 addi t1,t1,-14 - 12e0: 0000 unimp - 12e2: 2605 jal 1602 <_start-0x7fffe9fe> - 12e4: 4900 lw s0,16(a0) - 12e6: 06000013 li zero,96 - 12ea: 0101 addi sp,sp,0 - 12ec: 1349 addi t1,t1,-14 - 12ee: 1301 addi t1,t1,-32 - 12f0: 0000 unimp - 12f2: 49002107 flw ft2,1168(zero) # 490 <_start-0x7ffffb70> - 12f6: 000b2f13 slti t5,s6,0 - 12fa: 0800 addi s0,sp,16 - 12fc: 0034 addi a3,sp,8 - 12fe: 0b3a0e03 lb t3,179(s4) - 1302: 0b390b3b 0xb390b3b - 1306: 1349 addi t1,t1,-14 - 1308: 193c193f 16090000 0x16090000193c193f - 1310: 0300 addi s0,sp,384 - 1312: 3a0e fld fs4,224(sp) - 1314: 390b3b0b 0x390b3b0b - 1318: 0013490b 0x13490b - 131c: 0a00 addi s0,sp,272 - 131e: 0b0b0113 addi sp,s6,176 - 1322: 0b3a slli s6,s6,0xe - 1324: 0b390b3b 0xb390b3b - 1328: 1301 addi t1,t1,-32 - 132a: 0000 unimp - 132c: 03000d0b 0x3000d0b - 1330: 3a0e fld fs4,224(sp) - 1332: 390b3b0b 0x390b3b0b - 1336: 0b13490b 0xb13490b - 133a: 0c0b0d0b 0xc0b0d0b - 133e: 000b380b 0xb380b - 1342: 0c00 addi s0,sp,528 - 1344: 000d c.nop 3 - 1346: 0b3a0803 lb a6,179(s4) - 134a: 0b390b3b 0xb390b3b - 134e: 1349 addi t1,t1,-14 - 1350: 0b0d0b0b 0xb0d0b0b - 1354: 0b0c addi a1,sp,400 - 1356: 0b38 addi a4,sp,408 - 1358: 0000 unimp - 135a: 170d addi a4,a4,-29 - 135c: 0301 addi t1,t1,0 - 135e: 0b0e slli s6,s6,0x3 - 1360: 3b0b3a0b 0x3b0b3a0b - 1364: 010b390b 0x10b390b - 1368: 0e000013 li zero,224 - 136c: 000d c.nop 3 - 136e: 0b3a0803 lb a6,179(s4) - 1372: 0b390b3b 0xb390b3b - 1376: 1349 addi t1,t1,-14 - 1378: 0000 unimp - 137a: 03000d0f 0x3000d0f - 137e: 3a0e fld fs4,224(sp) - 1380: 390b3b0b 0x390b3b0b - 1384: 0013490b 0x13490b - 1388: 1000 addi s0,sp,32 - 138a: 012e slli sp,sp,0xb - 138c: 0e03193f 0b3b0b3a 0xb3b0b3a0e03193f - 1394: 0b39 addi s6,s6,14 - 1396: 13491927 0x13491927 - 139a: 0111 addi sp,sp,4 - 139c: 0612 slli a2,a2,0x4 - 139e: 1840 addi s0,sp,52 - 13a0: 4296 lw t0,68(sp) - 13a2: 0119 addi sp,sp,6 - 13a4: 11000013 li zero,272 - 13a8: 0005 c.nop 1 - 13aa: 0b3a0803 lb a6,179(s4) - 13ae: 0b390b3b 0xb390b3b - 13b2: 1349 addi t1,t1,-14 - 13b4: 1702 slli a4,a4,0x20 - 13b6: 0000 unimp - 13b8: 3412 fld fs0,288(sp) - 13ba: 0300 addi s0,sp,384 - 13bc: 3a08 fld fa0,48(a2) - 13be: 390b3b0b 0x390b3b0b - 13c2: 0013490b 0x13490b - 13c6: 1300 addi s0,sp,416 - 13c8: 0034 addi a3,sp,8 - 13ca: 0b3a0803 lb a6,179(s4) - 13ce: 0b390b3b 0xb390b3b - 13d2: 1349 addi t1,t1,-14 - 13d4: 1702 slli a4,a4,0x20 - 13d6: 0000 unimp - 13d8: 3414 fld fa3,40(s0) - 13da: 0300 addi s0,sp,384 - 13dc: 3a08 fld fa0,48(a2) - 13de: 390b3b0b 0x390b3b0b - 13e2: 0213490b 0x213490b - 13e6: 0018 0x18 - 13e8: 1500 addi s0,sp,672 - 13ea: 1755010b 0x1755010b - 13ee: 1301 addi t1,t1,-32 - 13f0: 0000 unimp - 13f2: 0a16 slli s4,s4,0x5 - 13f4: 0300 addi s0,sp,384 - 13f6: 3a0e fld fs4,224(sp) - 13f8: 390b3b0b 0x390b3b0b - 13fc: 1700000b 0x1700000b - 1400: 0111010b 0x111010b - 1404: 0612 slli a2,a2,0x4 - 1406: 0000 unimp - 1408: 3418 fld fa4,40(s0) - 140a: 0300 addi s0,sp,384 - 140c: 3a0e fld fs4,224(sp) - 140e: 390b3b0b 0x390b3b0b - 1412: 0213490b 0x213490b - 1416: 19000017 auipc zero,0x19000 - 141a: 0111010b 0x111010b - 141e: 0612 slli a2,a2,0x4 - 1420: 1301 addi t1,t1,-32 - 1422: 0000 unimp - 1424: 0b1a slli s6,s6,0x6 - 1426: 0101 addi sp,sp,0 - 1428: 1b000013 li zero,432 - 142c: 0034 addi a3,sp,8 - 142e: 0b3a0e03 lb t3,179(s4) - 1432: 0b390b3b 0xb390b3b - 1436: 1349 addi t1,t1,-14 - 1438: 0000 unimp - 143a: 0b1c addi a5,sp,400 - 143c: 0001 nop - 143e: 1d00 addi s0,sp,688 - 1440: 1755010b 0x1755010b - 1444: 0000 unimp - 1446: 341e fld fs0,480(sp) - 1448: 0300 addi s0,sp,384 - 144a: 3a0e fld fs4,224(sp) - 144c: 390b3b0b 0x390b3b0b - 1450: 0213490b 0x213490b - 1454: 0018 0x18 - 1456: 1f00 addi s0,sp,944 - 1458: 0101 addi sp,sp,0 - 145a: 1349 addi t1,t1,-14 - 145c: 0000 unimp - 145e: 0100 addi s0,sp,128 - 1460: 0111 addi sp,sp,4 - 1462: 0e25 addi t3,t3,9 - 1464: 0e030b13 addi s6,t1,224 - 1468: 01110e1b 0x1110e1b - 146c: 0612 slli a2,a2,0x4 - 146e: 1710 addi a2,sp,928 - 1470: 0000 unimp - 1472: 2402 fld fs0,0(sp) - 1474: 0b00 addi s0,sp,400 - 1476: 030b3e0b 0x30b3e0b - 147a: 000e c.slli zero,0x3 - 147c: 0300 addi s0,sp,384 - 147e: 0024 addi s1,sp,8 - 1480: 0b3e0b0b 0xb3e0b0b - 1484: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - 1488: 1604 addi s1,sp,800 - 148a: 0300 addi s0,sp,384 - 148c: 3a0e fld fs4,224(sp) - 148e: 39053b0b 0x39053b0b - 1492: 0013490b 0x13490b - 1496: 0500 addi s0,sp,640 - 1498: 0026 c.slli zero,0x9 - 149a: 1349 addi t1,t1,-14 - 149c: 0000 unimp - 149e: 0106 slli sp,sp,0x1 - 14a0: 4901 li s2,0 - 14a2: 00130113 addi sp,t1,1 - 14a6: 0700 addi s0,sp,896 - 14a8: 0021 c.nop 8 - 14aa: 1349 addi t1,t1,-14 - 14ac: 00000b2f 0xb2f - 14b0: 3408 fld fa0,40(s0) - 14b2: 0300 addi s0,sp,384 - 14b4: 3a0e fld fs4,224(sp) - 14b6: 390b3b0b 0x390b3b0b - 14ba: 3f13490b 0x3f13490b - 14be: 3c19 jal ed4 <_start-0x7ffff12c> - 14c0: 0019 c.nop 6 - 14c2: 0900 addi s0,sp,144 - 14c4: 0016 c.slli zero,0x5 - 14c6: 0b3a0e03 lb t3,179(s4) - 14ca: 0b390b3b 0xb390b3b - 14ce: 1349 addi t1,t1,-14 - 14d0: 0000 unimp - 14d2: 130a slli t1,t1,0x22 - 14d4: 0b01 addi s6,s6,0 - 14d6: 3b0b3a0b 0x3b0b3a0b - 14da: 010b390b 0x10b390b - 14de: 0b000013 li zero,176 - 14e2: 000d c.nop 3 - 14e4: 0b3a0e03 lb t3,179(s4) - 14e8: 0b390b3b 0xb390b3b - 14ec: 1349 addi t1,t1,-14 - 14ee: 0b0d0b0b 0xb0d0b0b - 14f2: 0b0c addi a1,sp,400 - 14f4: 0b38 addi a4,sp,408 - 14f6: 0000 unimp - 14f8: 0d0c addi a1,sp,656 - 14fa: 0300 addi s0,sp,384 - 14fc: 3a08 fld fa0,48(a2) - 14fe: 390b3b0b 0x390b3b0b - 1502: 0b13490b 0xb13490b - 1506: 0c0b0d0b 0xc0b0d0b - 150a: 000b380b 0xb380b - 150e: 0d00 addi s0,sp,656 - 1510: 0e030117 auipc sp,0xe030 - 1514: 0b3a0b0b 0xb3a0b0b - 1518: 0b390b3b 0xb390b3b - 151c: 1301 addi t1,t1,-32 - 151e: 0000 unimp - 1520: 0d0e slli s10,s10,0x3 - 1522: 0300 addi s0,sp,384 - 1524: 3a08 fld fa0,48(a2) - 1526: 390b3b0b 0x390b3b0b - 152a: 0013490b 0x13490b - 152e: 0f00 addi s0,sp,912 - 1530: 000d c.nop 3 - 1532: 0b3a0e03 lb t3,179(s4) - 1536: 0b390b3b 0xb390b3b - 153a: 1349 addi t1,t1,-14 - 153c: 0000 unimp - 153e: 2e10 fld fa2,24(a2) - 1540: 3f01 jal 1450 <_start-0x7fffebb0> - 1542: 0319 addi t1,t1,6 - 1544: 3a0e fld fs4,224(sp) - 1546: 390b3b0b 0x390b3b0b - 154a: 4919270b 0x4919270b - 154e: 12011113 0x12011113 - 1552: 4006 0x4006 - 1554: 9618 0x9618 - 1556: 1942 slli s2,s2,0x30 - 1558: 1301 addi t1,t1,-32 - 155a: 0000 unimp - 155c: 0511 addi a0,a0,4 - 155e: 0300 addi s0,sp,384 - 1560: 3a08 fld fa0,48(a2) - 1562: 390b3b0b 0x390b3b0b - 1566: 0213490b 0x213490b - 156a: 12000017 auipc zero,0x12000 - 156e: 0034 addi a3,sp,8 - 1570: 0b3a0e03 lb t3,179(s4) - 1574: 0b390b3b 0xb390b3b - 1578: 1349 addi t1,t1,-14 - 157a: 0b1c addi a5,sp,400 - 157c: 0000 unimp - 157e: 03003413 sltiu s0,zero,48 - 1582: 3a08 fld fa0,48(a2) - 1584: 390b3b0b 0x390b3b0b - 1588: 0013490b 0x13490b - 158c: 1400 addi s0,sp,544 - 158e: 0034 addi a3,sp,8 - 1590: 0b3a0803 lb a6,179(s4) - 1594: 0b390b3b 0xb390b3b - 1598: 1349 addi t1,t1,-14 - 159a: 1702 slli a4,a4,0x20 - 159c: 0000 unimp - 159e: 3415 jal fc2 <_start-0x7ffff03e> - 15a0: 0300 addi s0,sp,384 - 15a2: 3a0e fld fs4,224(sp) - 15a4: 390b3b0b 0x390b3b0b - 15a8: 0213490b 0x213490b - 15ac: 16000017 auipc zero,0x16000 - 15b0: 0034 addi a3,sp,8 - 15b2: 0b3a0803 lb a6,179(s4) - 15b6: 0b390b3b 0xb390b3b - 15ba: 1349 addi t1,t1,-14 - 15bc: 1802 slli a6,a6,0x20 - 15be: 0000 unimp - 15c0: 55010b17 auipc s6,0x55010 - 15c4: 00130117 auipc sp,0x130 - 15c8: 1800 addi s0,sp,48 - 15ca: 0034 addi a3,sp,8 - 15cc: 0b3a0e03 lb t3,179(s4) - 15d0: 0b390b3b 0xb390b3b - 15d4: 1349 addi t1,t1,-14 - 15d6: 0000 unimp - 15d8: 0b19 addi s6,s6,6 - 15da: 0101 addi sp,sp,0 - 15dc: 1a000013 li zero,416 - 15e0: 0111010b 0x111010b - 15e4: 0612 slli a2,a2,0x4 - 15e6: 1301 addi t1,t1,-32 - 15e8: 0000 unimp - 15ea: 55010b1b 0x55010b1b - 15ee: 1c000017 auipc zero,0x1c000 - 15f2: 0034 addi a3,sp,8 - 15f4: 0b3a0e03 lb t3,179(s4) - 15f8: 0b390b3b 0xb390b3b - 15fc: 1349 addi t1,t1,-14 - 15fe: 1802 slli a6,a6,0x20 - 1600: 0000 unimp - 1602: 011d addi sp,sp,7 - 1604: 4901 li s2,0 - 1606: 00000013 nop - 160a: 1101 addi sp,sp,-32 - 160c: 2501 jal 1c0c <_start-0x7fffe3f4> - 160e: 130e slli t1,t1,0x23 - 1610: 1b0e030b 0x1b0e030b - 1614: 110e slli sp,sp,0x23 - 1616: 1201 addi tp,tp,-32 - 1618: 1006 c.slli zero,0x21 - 161a: 02000017 auipc zero,0x2000 - 161e: 0024 addi s1,sp,8 - 1620: 0b3e0b0b 0xb3e0b0b - 1624: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> - 1628: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> - 162c: 030b3e0b 0x30b3e0b - 1630: 000e c.slli zero,0x3 - 1632: 0400 addi s0,sp,512 - 1634: 0016 c.slli zero,0x5 - 1636: 0b3a0e03 lb t3,179(s4) - 163a: 0b39053b 0xb39053b - 163e: 1349 addi t1,t1,-14 - 1640: 0000 unimp - 1642: 2605 jal 1962 <_start-0x7fffe69e> - 1644: 4900 lw s0,16(a0) - 1646: 06000013 li zero,96 - 164a: 0101 addi sp,sp,0 - 164c: 1349 addi t1,t1,-14 - 164e: 1301 addi t1,t1,-32 - 1650: 0000 unimp - 1652: 49002107 flw ft2,1168(zero) # 490 <_start-0x7ffffb70> - 1656: 000b2f13 slti t5,s6,0 - 165a: 0800 addi s0,sp,16 - 165c: 0034 addi a3,sp,8 - 165e: 0b3a0e03 lb t3,179(s4) - 1662: 0b390b3b 0xb390b3b - 1666: 1349 addi t1,t1,-14 - 1668: 193c193f 16090000 0x16090000193c193f - 1670: 0300 addi s0,sp,384 - 1672: 3a0e fld fs4,224(sp) - 1674: 390b3b0b 0x390b3b0b - 1678: 0013490b 0x13490b - 167c: 0a00 addi s0,sp,272 - 167e: 0b0b0113 addi sp,s6,176 # 55011670 <_start-0x2afee990> - 1682: 0b3a slli s6,s6,0xe - 1684: 0b390b3b 0xb390b3b - 1688: 1301 addi t1,t1,-32 - 168a: 0000 unimp - 168c: 03000d0b 0x3000d0b - 1690: 3a0e fld fs4,224(sp) - 1692: 390b3b0b 0x390b3b0b - 1696: 0b13490b 0xb13490b - 169a: 0c0b0d0b 0xc0b0d0b - 169e: 000b380b 0xb380b - 16a2: 0c00 addi s0,sp,528 - 16a4: 000d c.nop 3 - 16a6: 0b3a0803 lb a6,179(s4) - 16aa: 0b390b3b 0xb390b3b - 16ae: 1349 addi t1,t1,-14 - 16b0: 0b0d0b0b 0xb0d0b0b - 16b4: 0b0c addi a1,sp,400 - 16b6: 0b38 addi a4,sp,408 - 16b8: 0000 unimp - 16ba: 170d addi a4,a4,-29 - 16bc: 0301 addi t1,t1,0 - 16be: 0b0e slli s6,s6,0x3 - 16c0: 3b0b3a0b 0x3b0b3a0b - 16c4: 010b390b 0x10b390b - 16c8: 0e000013 li zero,224 - 16cc: 000d c.nop 3 - 16ce: 0b3a0803 lb a6,179(s4) - 16d2: 0b390b3b 0xb390b3b - 16d6: 1349 addi t1,t1,-14 - 16d8: 0000 unimp - 16da: 03000d0f 0x3000d0f - 16de: 3a0e fld fs4,224(sp) - 16e0: 390b3b0b 0x390b3b0b - 16e4: 0013490b 0x13490b - 16e8: 1000 addi s0,sp,32 - 16ea: 012e slli sp,sp,0xb - 16ec: 0e03193f 0b3b0b3a 0xb3b0b3a0e03193f - 16f4: 0b39 addi s6,s6,14 - 16f6: 13491927 0x13491927 - 16fa: 0111 addi sp,sp,4 - 16fc: 0612 slli a2,a2,0x4 - 16fe: 1840 addi s0,sp,52 - 1700: 01194297 auipc t0,0x1194 - 1704: 11000013 li zero,272 - 1708: 0005 c.nop 1 - 170a: 0b3a0803 lb a6,179(s4) - 170e: 0b390b3b 0xb390b3b - 1712: 1349 addi t1,t1,-14 - 1714: 0000 unimp - 1716: 3412 fld fs0,288(sp) - 1718: 0300 addi s0,sp,384 - 171a: 3a0e fld fs4,224(sp) - 171c: 390b3b0b 0x390b3b0b - 1720: 0213490b 0x213490b - 1724: 13000017 auipc zero,0x13000 - 1728: 0034 addi a3,sp,8 - 172a: 0b3a0e03 lb t3,179(s4) - 172e: 0b390b3b 0xb390b3b - 1732: 1349 addi t1,t1,-14 - 1734: 0b1c addi a5,sp,400 - 1736: 0000 unimp - 1738: 3414 fld fa3,40(s0) - 173a: 0300 addi s0,sp,384 - 173c: 3a08 fld fa0,48(a2) - 173e: 390b3b0b 0x390b3b0b - 1742: 0013490b 0x13490b - 1746: 1500 addi s0,sp,672 - 1748: 0034 addi a3,sp,8 - 174a: 0b3a0803 lb a6,179(s4) - 174e: 0b390b3b 0xb390b3b - 1752: 1349 addi t1,t1,-14 - 1754: 1702 slli a4,a4,0x20 - 1756: 0000 unimp - 1758: 3416 fld fs0,352(sp) - 175a: 0300 addi s0,sp,384 - 175c: 3a08 fld fa0,48(a2) - 175e: 390b3b0b 0x390b3b0b - 1762: 0213490b 0x213490b - 1766: 0018 0x18 - 1768: 1700 addi s0,sp,928 - 176a: 1755010b 0x1755010b - 176e: 1301 addi t1,t1,-32 - 1770: 0000 unimp - 1772: 3418 fld fa4,40(s0) - 1774: 0300 addi s0,sp,384 - 1776: 3a0e fld fs4,224(sp) - 1778: 390b3b0b 0x390b3b0b - 177c: 0213490b 0x213490b - 1780: 0018 0x18 - 1782: 1900 addi s0,sp,176 - 1784: 1755010b 0x1755010b - 1788: 0000 unimp - 178a: 0b1a slli s6,s6,0x6 - 178c: 1101 addi sp,sp,-32 - 178e: 1201 addi tp,tp,-32 - 1790: 0106 slli sp,sp,0x1 - 1792: 1b000013 li zero,432 - 1796: 0034 addi a3,sp,8 - 1798: 0b3a0e03 lb t3,179(s4) - 179c: 0b390b3b 0xb390b3b - 17a0: 1349 addi t1,t1,-14 - 17a2: 0000 unimp - 17a4: 0b1c addi a5,sp,400 - 17a6: 0101 addi sp,sp,0 - 17a8: 1d000013 li zero,464 - 17ac: 0000010b 0x10b - 17b0: 0b1e slli s6,s6,0x7 - 17b2: 1101 addi sp,sp,-32 - 17b4: 1201 addi tp,tp,-32 - 17b6: 0006 c.slli zero,0x1 - 17b8: 1f00 addi s0,sp,944 - 17ba: 0101 addi sp,sp,0 - 17bc: 1349 addi t1,t1,-14 - 17be: 0000 unimp - 17c0: 0100 addi s0,sp,128 - 17c2: 0111 addi sp,sp,4 - 17c4: 0e25 addi t3,t3,9 - 17c6: 0e030b13 addi s6,t1,224 - 17ca: 17100e1b 0x17100e1b - 17ce: 0000 unimp - 17d0: 2402 fld fs0,0(sp) - 17d2: 0b00 addi s0,sp,400 - 17d4: 030b3e0b 0x30b3e0b - 17d8: 0008 0x8 - 17da: 0300 addi s0,sp,384 - 17dc: 0024 addi s1,sp,8 - 17de: 0b3e0b0b 0xb3e0b0b - 17e2: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - 17e6: 1604 addi s1,sp,800 - 17e8: 0300 addi s0,sp,384 - 17ea: 3a0e fld fs4,224(sp) - 17ec: 390b3b0b 0x390b3b0b - 17f0: 0013490b 0x13490b - 17f4: 0500 addi s0,sp,640 - 17f6: 0016 c.slli zero,0x5 - 17f8: 0b3a0e03 lb t3,179(s4) - 17fc: 0b39053b 0xb39053b - 1800: 1349 addi t1,t1,-14 - 1802: 0000 unimp - 1804: 1706 slli a4,a4,0x21 - 1806: 0b01 addi s6,s6,0 - 1808: 3b0b3a0b 0x3b0b3a0b - 180c: 010b390b 0x10b390b - 1810: 07000013 li zero,112 - 1814: 000d c.nop 3 - 1816: 0b3a0e03 lb t3,179(s4) - 181a: 0b390b3b 0xb390b3b - 181e: 1349 addi t1,t1,-14 - 1820: 0000 unimp - 1822: 0108 addi a0,sp,128 - 1824: 4901 li s2,0 - 1826: 00130113 addi sp,t1,1 - 182a: 0900 addi s0,sp,144 - 182c: 0021 c.nop 8 - 182e: 1349 addi t1,t1,-14 - 1830: 00000b2f 0xb2f - 1834: 130a slli t1,t1,0x22 - 1836: 0b01 addi s6,s6,0 - 1838: 3b0b3a0b 0x3b0b3a0b - 183c: 010b390b 0x10b390b - 1840: 0b000013 li zero,176 - 1844: 000d c.nop 3 - 1846: 0b3a0e03 lb t3,179(s4) - 184a: 0b390b3b 0xb390b3b - 184e: 1349 addi t1,t1,-14 - 1850: 0b38 addi a4,sp,408 - 1852: 0000 unimp - 1854: 0f0c addi a1,sp,912 - 1856: 0b00 addi s0,sp,400 - 1858: 0d00000b 0xd00000b - 185c: 0e030113 addi sp,t1,224 - 1860: 0b3a0b0b 0xb3a0b0b - 1864: 0b390b3b 0xb390b3b - 1868: 1301 addi t1,t1,-32 - 186a: 0000 unimp - 186c: 0d0e slli s10,s10,0x3 - 186e: 0300 addi s0,sp,384 - 1870: 3a08 fld fa0,48(a2) - 1872: 390b3b0b 0x390b3b0b - 1876: 3813490b 0x3813490b - 187a: 0f00000b 0xf00000b - 187e: 0b0b000f 0xb0b000f - 1882: 1349 addi t1,t1,-14 - 1884: 0000 unimp - 1886: 1310 addi a2,sp,416 - 1888: 0301 addi t1,t1,0 - 188a: 0b0e slli s6,s6,0x3 - 188c: 3a05 jal 11bc <_start-0x7fffee44> - 188e: 390b3b0b 0x390b3b0b - 1892: 0013010b 0x13010b - 1896: 1100 addi s0,sp,160 - 1898: 000d c.nop 3 - 189a: 0b3a0e03 lb t3,179(s4) - 189e: 0b390b3b 0xb390b3b - 18a2: 1349 addi t1,t1,-14 - 18a4: 0538 addi a4,sp,648 - 18a6: 0000 unimp - 18a8: 1512 slli a0,a0,0x24 - 18aa: 2700 fld fs0,8(a4) - 18ac: 0019 c.nop 6 - 18ae: 1300 addi s0,sp,416 - 18b0: 0115 addi sp,sp,5 - 18b2: 13491927 0x13491927 - 18b6: 1301 addi t1,t1,-32 - 18b8: 0000 unimp - 18ba: 0514 addi a3,sp,640 - 18bc: 4900 lw s0,16(a0) - 18be: 15000013 li zero,336 - 18c2: 0026 c.slli zero,0x9 - 18c4: 1349 addi t1,t1,-14 - 18c6: 0000 unimp - 18c8: 1316 slli t1,t1,0x25 - 18ca: 0301 addi t1,t1,0 - 18cc: 0b0e slli s6,s6,0x3 - 18ce: 3a05 jal 11fe <_start-0x7fffee02> - 18d0: 39053b0b 0x39053b0b - 18d4: 0013010b 0x13010b - 18d8: 1700 addi s0,sp,928 - 18da: 000d c.nop 3 - 18dc: 0b3a0e03 lb t3,179(s4) - 18e0: 0b39053b 0xb39053b - 18e4: 1349 addi t1,t1,-14 - 18e6: 0b38 addi a4,sp,408 - 18e8: 0000 unimp - 18ea: 0d18 addi a4,sp,656 - 18ec: 0300 addi s0,sp,384 - 18ee: 3a0e fld fs4,224(sp) - 18f0: 39053b0b 0x39053b0b - 18f4: 3813490b 0x3813490b - 18f8: 0005 c.nop 1 - 18fa: 1900 addi s0,sp,176 - 18fc: 0e030113 addi sp,t1,224 - 1900: 0b3a0b0b 0xb3a0b0b - 1904: 0b39053b 0xb39053b - 1908: 1301 addi t1,t1,-32 - 190a: 0000 unimp - 190c: 131a slli t1,t1,0x26 - 190e: 0b01 addi s6,s6,0 - 1910: 3b0b3a0b 0x3b0b3a0b - 1914: 3905 jal 1544 <_start-0x7fffeabc> - 1916: 0013010b 0x13010b - 191a: 1b00 addi s0,sp,432 - 191c: 0b0b0117 auipc sp,0xb0b0 - 1920: 0b3a slli s6,s6,0xe - 1922: 0b39053b 0xb39053b - 1926: 1301 addi t1,t1,-32 - 1928: 0000 unimp - 192a: 0d1c addi a5,sp,656 - 192c: 0300 addi s0,sp,384 - 192e: 3a0e fld fs4,224(sp) - 1930: 39053b0b 0x39053b0b - 1934: 0013490b 0x13490b - 1938: 1d00 addi s0,sp,688 - 193a: 0e030013 addi zero,t1,224 - 193e: 193c addi a5,sp,184 - 1940: 0000 unimp - 1942: 151e slli a0,a0,0x27 - 1944: 2701 jal 2044 <_start-0x7fffdfbc> - 1946: 0119 addi sp,sp,6 - 1948: 1f000013 li zero,496 - 194c: 0034 addi a3,sp,8 - 194e: 0b3a0e03 lb t3,179(s4) - 1952: 0b39053b 0xb39053b - 1956: 1349 addi t1,t1,-14 - 1958: 193c193f 21200000 0x21200000193c193f - 1960: 0000 unimp - 1962: 2100 fld fs0,0(a0) - 1964: 0034 addi a3,sp,8 - 1966: 0b3a0e03 lb t3,179(s4) - 196a: 0b390b3b 0xb390b3b - 196e: 1349 addi t1,t1,-14 - 1970: 193c193f 26220000 0x26220000193c193f - 1978: 0000 unimp - 197a: 2300 fld fs0,0(a4) - 197c: 0104 addi s1,sp,128 - 197e: 0b3e0e03 lb t3,179(t3) # 69d47 <_start-0x7ff962b9> - 1982: 13490b0b 0x13490b0b - 1986: 0b3a slli s6,s6,0xe - 1988: 0b390b3b 0xb390b3b - 198c: 1301 addi t1,t1,-32 - 198e: 0000 unimp - 1990: 2824 fld fs1,80(s0) - 1992: 0300 addi s0,sp,384 - 1994: 1c0e slli s8,s8,0x23 - 1996: 2500000b 0x2500000b - 199a: 0034 addi a3,sp,8 - 199c: 0b3a1347 fmsub.d ft6,fs4,fs3,ft1,rtz - 19a0: 0b39053b 0xb39053b - 19a4: 1802 slli a6,a6,0x20 - 19a6: 0000 unimp - 19a8: 0100 addi s0,sp,128 - 19aa: 0111 addi sp,sp,4 - 19ac: 0e25 addi t3,t3,9 - 19ae: 0e030b13 addi s6,t1,224 - 19b2: 01110e1b 0x1110e1b - 19b6: 0612 slli a2,a2,0x4 - 19b8: 1710 addi a2,sp,928 - 19ba: 0000 unimp - 19bc: 2402 fld fs0,0(sp) - 19be: 0b00 addi s0,sp,400 - 19c0: 030b3e0b 0x30b3e0b - 19c4: 0008 0x8 - 19c6: 0300 addi s0,sp,384 - 19c8: 0024 addi s1,sp,8 - 19ca: 0b3e0b0b 0xb3e0b0b - 19ce: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> - 19d2: 1604 addi s1,sp,800 - 19d4: 0300 addi s0,sp,384 - 19d6: 3a0e fld fs4,224(sp) - 19d8: 390b3b0b 0x390b3b0b - 19dc: 0013490b 0x13490b - 19e0: 0500 addi s0,sp,640 - 19e2: 0016 c.slli zero,0x5 - 19e4: 0b3a0e03 lb t3,179(s4) - 19e8: 0b39053b 0xb39053b - 19ec: 1349 addi t1,t1,-14 - 19ee: 0000 unimp - 19f0: 1706 slli a4,a4,0x21 - 19f2: 0b01 addi s6,s6,0 - 19f4: 3b0b3a0b 0x3b0b3a0b - 19f8: 010b390b 0x10b390b - 19fc: 07000013 li zero,112 - 1a00: 000d c.nop 3 - 1a02: 0b3a0e03 lb t3,179(s4) - 1a06: 0b390b3b 0xb390b3b - 1a0a: 1349 addi t1,t1,-14 - 1a0c: 0000 unimp - 1a0e: 0108 addi a0,sp,128 - 1a10: 4901 li s2,0 - 1a12: 00130113 addi sp,t1,1 - 1a16: 0900 addi s0,sp,144 - 1a18: 0021 c.nop 8 - 1a1a: 1349 addi t1,t1,-14 - 1a1c: 00000b2f 0xb2f - 1a20: 130a slli t1,t1,0x22 - 1a22: 0b01 addi s6,s6,0 - 1a24: 3b0b3a0b 0x3b0b3a0b - 1a28: 010b390b 0x10b390b - 1a2c: 0b000013 li zero,176 - 1a30: 000d c.nop 3 - 1a32: 0b3a0e03 lb t3,179(s4) - 1a36: 0b390b3b 0xb390b3b - 1a3a: 1349 addi t1,t1,-14 - 1a3c: 0b38 addi a4,sp,408 - 1a3e: 0000 unimp - 1a40: 0f0c addi a1,sp,912 - 1a42: 0b00 addi s0,sp,400 - 1a44: 0d00000b 0xd00000b - 1a48: 0e030113 addi sp,t1,224 - 1a4c: 0b3a0b0b 0xb3a0b0b - 1a50: 0b390b3b 0xb390b3b - 1a54: 1301 addi t1,t1,-32 - 1a56: 0000 unimp - 1a58: 0d0e slli s10,s10,0x3 - 1a5a: 0300 addi s0,sp,384 - 1a5c: 3a08 fld fa0,48(a2) - 1a5e: 390b3b0b 0x390b3b0b - 1a62: 3813490b 0x3813490b - 1a66: 0f00000b 0xf00000b - 1a6a: 0b0b000f 0xb0b000f - 1a6e: 1349 addi t1,t1,-14 - 1a70: 0000 unimp - 1a72: 1310 addi a2,sp,416 - 1a74: 0301 addi t1,t1,0 - 1a76: 0b0e slli s6,s6,0x3 - 1a78: 3a05 jal 13a8 <_start-0x7fffec58> - 1a7a: 390b3b0b 0x390b3b0b - 1a7e: 0013010b 0x13010b - 1a82: 1100 addi s0,sp,160 - 1a84: 000d c.nop 3 - 1a86: 0b3a0e03 lb t3,179(s4) - 1a8a: 0b390b3b 0xb390b3b - 1a8e: 1349 addi t1,t1,-14 - 1a90: 0538 addi a4,sp,648 - 1a92: 0000 unimp - 1a94: 1512 slli a0,a0,0x24 - 1a96: 2700 fld fs0,8(a4) - 1a98: 0019 c.nop 6 - 1a9a: 1300 addi s0,sp,416 - 1a9c: 0115 addi sp,sp,5 - 1a9e: 13491927 0x13491927 - 1aa2: 1301 addi t1,t1,-32 - 1aa4: 0000 unimp - 1aa6: 0514 addi a3,sp,640 - 1aa8: 4900 lw s0,16(a0) - 1aaa: 15000013 li zero,336 - 1aae: 0026 c.slli zero,0x9 - 1ab0: 1349 addi t1,t1,-14 - 1ab2: 0000 unimp - 1ab4: 1316 slli t1,t1,0x25 - 1ab6: 0301 addi t1,t1,0 - 1ab8: 0b0e slli s6,s6,0x3 - 1aba: 3a05 jal 13ea <_start-0x7fffec16> - 1abc: 39053b0b 0x39053b0b - 1ac0: 0013010b 0x13010b - 1ac4: 1700 addi s0,sp,928 - 1ac6: 000d c.nop 3 - 1ac8: 0b3a0e03 lb t3,179(s4) - 1acc: 0b39053b 0xb39053b - 1ad0: 1349 addi t1,t1,-14 - 1ad2: 0b38 addi a4,sp,408 - 1ad4: 0000 unimp - 1ad6: 0d18 addi a4,sp,656 - 1ad8: 0300 addi s0,sp,384 - 1ada: 3a0e fld fs4,224(sp) - 1adc: 39053b0b 0x39053b0b - 1ae0: 3813490b 0x3813490b - 1ae4: 0005 c.nop 1 - 1ae6: 1900 addi s0,sp,176 - 1ae8: 0e030113 addi sp,t1,224 - 1aec: 0b3a0b0b 0xb3a0b0b - 1af0: 0b39053b 0xb39053b - 1af4: 1301 addi t1,t1,-32 - 1af6: 0000 unimp - 1af8: 131a slli t1,t1,0x26 - 1afa: 0b01 addi s6,s6,0 - 1afc: 3b0b3a0b 0x3b0b3a0b - 1b00: 3905 jal 1730 <_start-0x7fffe8d0> - 1b02: 0013010b 0x13010b - 1b06: 1b00 addi s0,sp,432 - 1b08: 0b0b0117 auipc sp,0xb0b0 - 1b0c: 0b3a slli s6,s6,0xe - 1b0e: 0b39053b 0xb39053b - 1b12: 1301 addi t1,t1,-32 - 1b14: 0000 unimp - 1b16: 0d1c addi a5,sp,656 - 1b18: 0300 addi s0,sp,384 - 1b1a: 3a0e fld fs4,224(sp) - 1b1c: 39053b0b 0x39053b0b - 1b20: 0013490b 0x13490b - 1b24: 1d00 addi s0,sp,688 - 1b26: 0e030013 addi zero,t1,224 - 1b2a: 193c addi a5,sp,184 - 1b2c: 0000 unimp - 1b2e: 151e slli a0,a0,0x27 - 1b30: 2701 jal 2230 <_start-0x7fffddd0> - 1b32: 0119 addi sp,sp,6 - 1b34: 1f000013 li zero,496 - 1b38: 0034 addi a3,sp,8 - 1b3a: 0b3a0e03 lb t3,179(s4) - 1b3e: 0b39053b 0xb39053b - 1b42: 1349 addi t1,t1,-14 - 1b44: 193c193f 21200000 0x21200000193c193f - 1b4c: 0000 unimp - 1b4e: 2100 fld fs0,0(a0) - 1b50: 0034 addi a3,sp,8 - 1b52: 0b3a0e03 lb t3,179(s4) - 1b56: 0b390b3b 0xb390b3b - 1b5a: 1349 addi t1,t1,-14 - 1b5c: 193c193f 26220000 0x26220000193c193f - 1b64: 0000 unimp - 1b66: 2300 fld fs0,0(a4) - 1b68: 0104 addi s1,sp,128 - 1b6a: 0b3e0e03 lb t3,179(t3) - 1b6e: 13490b0b 0x13490b0b - 1b72: 0b3a slli s6,s6,0xe - 1b74: 0b390b3b 0xb390b3b - 1b78: 1301 addi t1,t1,-32 - 1b7a: 0000 unimp - 1b7c: 2824 fld fs1,80(s0) - 1b7e: 0300 addi s0,sp,384 - 1b80: 1c0e slli s8,s8,0x23 - 1b82: 2500000b 0x2500000b - 1b86: 012e slli sp,sp,0xb - 1b88: 0e03193f 053b0b3a 0x53b0b3a0e03193f - 1b90: 0b39 addi s6,s6,14 - 1b92: 13491927 0x13491927 - 1b96: 0111 addi sp,sp,4 - 1b98: 0612 slli a2,a2,0x4 - 1b9a: 1840 addi s0,sp,52 - 1b9c: 00194297 auipc t0,0x194 - 1ba0: 2600 fld fs0,8(a2) - 1ba2: 0005 c.nop 1 - 1ba4: 0b3a0803 lb a6,179(s4) - 1ba8: 0b39053b 0xb39053b - 1bac: 1349 addi t1,t1,-14 - 1bae: 1702 slli a4,a4,0x20 - 1bb0: 0000 unimp - 1bb2: 03003427 fsd fa6,40(zero) # 28 <_start-0x7fffffd8> - 1bb6: 3a08 fld fa0,48(a2) - 1bb8: 39053b0b 0x39053b0b - 1bbc: 0013490b 0x13490b - 1bc0: 2800 fld fs0,16(s0) - 1bc2: 1755010b 0x1755010b - 1bc6: 0000 unimp - 1bc8: 3429 jal 15d2 <_start-0x7fffea2e> - 1bca: 0300 addi s0,sp,384 - 1bcc: 3a0e fld fs4,224(sp) - 1bce: 39053b0b 0x39053b0b - 1bd2: 0213490b 0x213490b - 1bd6: 2a000017 auipc zero,0x2a000 - 1bda: 0034 addi a3,sp,8 - 1bdc: 0b3a0803 lb a6,179(s4) - 1be0: 0b39053b 0xb39053b - 1be4: 1349 addi t1,t1,-14 - 1be6: 1702 slli a4,a4,0x20 - 1be8: 0000 unimp - ... - -Disassembly of section .debug_line: - -00000000 <.debug_line>: - 0: 08da slli a7,a7,0x16 - 2: 0000 unimp - 4: 02100003 lb zero,33(zero) # 21 <_start-0x7fffffdf> - 8: 0000 unimp - a: 0101 addi sp,sp,0 - c: 000d0efb 0xd0efb - 10: 0101 addi sp,sp,0 - 12: 0101 addi sp,sp,0 - 14: 0000 unimp - 16: 0100 addi s0,sp,128 - 18: 0000 unimp - 1a: 2e01 jal 32a <_start-0x7ffffcd6> - 1c: 2f2e fld ft10,200(sp) - 1e: 2e2e fld ft8,200(sp) - 20: 2f2e2e2f 0x2f2e2e2f - 24: 2e2e fld ft8,200(sp) - 26: 7369722f 0x7369722f - 2a: 672d7663 bgeu s10,s2,696 <_start-0x7ffff96a> - 2e: 6c2f6363 bltu t5,sp,6f4 <_start-0x7ffff90c> - 32: 6269 lui tp,0x1a - 34: 00636367 0x636367 - 38: 6d6f682f 0x6d6f682f - 3c: 2f65 jal 7f4 <_start-0x7ffff80c> - 3e: 7270 flw fa2,100(a2) - 40: 7969 lui s2,0xffffa - 42: 2f61 jal 7da <_start-0x7ffff826> - 44: 6564 flw fs1,76(a0) - 46: 2f76 fld ft10,344(sp) - 48: 6972 flw fs2,28(sp) - 4a: 5f766373 csrrsi t1,0x5f7,12 - 4e: 6576 flw fa0,92(sp) - 50: 69722f63 0x69722f63 - 54: 2d766373 csrrsi t1,0x2d7,12 - 58: 2f756e67 0x2f756e67 - 5c: 6972 flw fs2,28(sp) - 5e: 33766373 csrrsi t1,mhpmevent23,12 - 62: 2d32 fld fs10,264(sp) - 64: 6e75 lui t3,0x1d - 66: 776f6e6b 0x776f6e6b - 6a: 2d6e fld fs10,216(sp) - 6c: 6c65 lui s8,0x19 - 6e: 2f66 fld ft10,88(sp) - 70: 6e69 lui t3,0x1a - 72: 64756c63 bltu a0,t2,6ca <_start-0x7ffff936> - 76: 2f65 jal 82e <_start-0x7ffff7d2> - 78: 00737973 csrrci s2,0x7,6 - 7c: 6d6f682f 0x6d6f682f - 80: 2f65 jal 838 <_start-0x7ffff7c8> - 82: 7270 flw fa2,100(a2) - 84: 7969 lui s2,0xffffa - 86: 2f61 jal 81e <_start-0x7ffff7e2> - 88: 6544 flw fs1,12(a0) - 8a: 6f746b73 csrrsi s6,0x6f7,8 - 8e: 2f70 fld fa2,216(a4) - 90: 6972 flw fs2,28(sp) - 92: 2d766373 csrrsi t1,0x2d7,12 - 96: 2d756e67 0x2d756e67 - 9a: 6f74 flw fa3,92(a4) - 9c: 68636c6f jal s8,36722 <_start-0x7ffc98de> - a0: 6961 lui s2,0x18 - a2: 2f6e fld ft10,216(sp) - a4: 7562 flw fa0,56(sp) - a6: 6c69 lui s8,0x1a - a8: 2f64 fld fs1,216(a4) - aa: 7562 flw fa0,56(sp) - ac: 6c69 lui s8,0x1a - ae: 2d64 fld fs1,216(a0) - b0: 2d636367 0x2d636367 - b4: 656e flw fa0,216(sp) - b6: 62696c77 0x62696c77 - ba: 732d lui t1,0xfffeb - bc: 6174 flw fa3,68(a0) - be: 2f326567 0x2f326567 - c2: 2f636367 0x2f636367 - c6: 6e69 lui t3,0x1a - c8: 64756c63 bltu a0,t2,720 <_start-0x7ffff8e0> - cc: 0065 c.nop 25 - ce: 6d6f682f 0x6d6f682f - d2: 2f65 jal 88a <_start-0x7ffff776> - d4: 7270 flw fa2,100(a2) - d6: 7969 lui s2,0xffffa - d8: 2f61 jal 870 <_start-0x7ffff790> - da: 6564 flw fs1,76(a0) - dc: 2f76 fld ft10,344(sp) - de: 6972 flw fs2,28(sp) - e0: 5f766373 csrrsi t1,0x5f7,12 - e4: 6576 flw fa0,92(sp) - e6: 69722f63 0x69722f63 - ea: 2d766373 csrrsi t1,0x2d7,12 - ee: 2f756e67 0x2f756e67 - f2: 6972 flw fs2,28(sp) - f4: 33766373 csrrsi t1,mhpmevent23,12 - f8: 2d32 fld fs10,264(sp) - fa: 6e75 lui t3,0x1d - fc: 776f6e6b 0x776f6e6b - 100: 2d6e fld fs10,216(sp) - 102: 6c65 lui s8,0x19 - 104: 2f66 fld ft10,88(sp) - 106: 6e69 lui t3,0x1a - 108: 64756c63 bltu a0,t2,760 <_start-0x7ffff8a0> - 10c: 0065 c.nop 25 - 10e: 2e2e fld ft8,200(sp) - 110: 2f2e2e2f 0x2f2e2e2f - 114: 2e2e fld ft8,200(sp) - 116: 2f2e2e2f 0x2f2e2e2f - 11a: 6972 flw fs2,28(sp) - 11c: 2d766373 csrrsi t1,0x2d7,12 - 120: 2f636367 0x2f636367 - 124: 696c flw fa1,84(a0) - 126: 6762 flw fa4,24(sp) - 128: 2e2f6363 bltu t5,sp,40e <_start-0x7ffffbf2> - 12c: 2f2e fld ft10,200(sp) - 12e: 6e69 lui t3,0x1a - 130: 64756c63 bltu a0,t2,788 <_start-0x7ffff878> - 134: 0065 c.nop 25 - 136: 2e2e fld ft8,200(sp) - 138: 2f2e2e2f 0x2f2e2e2f - 13c: 2e2e fld ft8,200(sp) - 13e: 2f2e2e2f 0x2f2e2e2f - 142: 6972 flw fs2,28(sp) - 144: 2d766373 csrrsi t1,0x2d7,12 - 148: 2f636367 0x2f636367 - 14c: 696c flw fa1,84(a0) - 14e: 6762 flw fa4,24(sp) - 150: 2e2f6363 bltu t5,sp,436 <_start-0x7ffffbca> - 154: 2f2e fld ft10,200(sp) - 156: 2f636367 0x2f636367 - 15a: 666e6f63 bltu t3,t1,7d8 <_start-0x7ffff828> - 15e: 6769 lui a4,0x1a - 160: 7369722f 0x7369722f - 164: 2e007663 bgeu zero,zero,450 <_start-0x7ffffbb0> - 168: 2f2e fld ft10,200(sp) - 16a: 2e2e fld ft8,200(sp) - 16c: 672f2e2f amoand.w.aqrl t3,s2,(t5) - 170: 00006363 bltu zero,zero,176 <_start-0x7ffffe8a> - 174: 696c flw fa1,84(a0) - 176: 6762 flw fa4,24(sp) - 178: 2e326363 bltu tp,gp,45e <_start-0x7ffffba2> - 17c: 00010063 beqz sp,17c <_start-0x7ffffe84> - 180: 6c00 flw fs0,24(s0) - 182: 2e6b636f jal t1,b6468 <_start-0x7ff49b98> - 186: 0068 addi a0,sp,12 - 188: 0002 c.slli64 zero - 18a: 5f00 lw s0,56(a4) - 18c: 7974 flw fa3,116(a0) - 18e: 6570 flw fa2,76(a0) - 190: 00682e73 csrrs t3,0x6,a6 - 194: 0002 c.slli64 zero - 196: 7300 flw fs0,32(a4) - 198: 6474 flw fa3,76(s0) - 19a: 6564 flw fs1,76(a0) - 19c: 2e66 fld ft8,88(sp) - 19e: 0068 addi a0,sp,12 - 1a0: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> - 1a4: 6565 lui a0,0x19 - 1a6: 746e flw fs0,248(sp) - 1a8: 682e flw fa6,200(sp) - 1aa: 0200 addi s0,sp,256 - 1ac: 0000 unimp - 1ae: 7265 lui tp,0xffff9 - 1b0: 6e72 flw ft8,28(sp) - 1b2: 00682e6f jal t3,821b8 <_start-0x7ff7de48> - 1b6: 0002 c.slli64 zero - 1b8: 7300 flw fs0,32(a4) - 1ba: 6474 flw fa3,76(s0) - 1bc: 696c flw fa1,84(a0) - 1be: 2e62 fld ft8,24(sp) - 1c0: 0068 addi a0,sp,12 - 1c2: 0004 0x4 - 1c4: 7500 flw fs0,40(a0) - 1c6: 696e flw fs2,216(sp) - 1c8: 2e647473 csrrci s0,0x2e6,8 - 1cc: 0068 addi a0,sp,12 - 1ce: 0002 c.slli64 zero - 1d0: 7400 flw fs0,40(s0) - 1d2: 6d69 lui s10,0x1a - 1d4: 2e65 jal 58c <_start-0x7ffffa74> - 1d6: 0068 addi a0,sp,12 - 1d8: 0004 0x4 - 1da: 6800 flw fs0,16(s0) - 1dc: 7361 lui t1,0xffff8 - 1de: 7468 flw fa0,108(s0) - 1e0: 6261 lui tp,0x18 - 1e2: 682e flw fa6,200(sp) - 1e4: 0500 addi s0,sp,640 - 1e6: 0000 unimp - 1e8: 6972 flw fs2,28(sp) - 1ea: 2d766373 csrrsi t1,0x2d7,12 - 1ee: 7374706f j 48124 <_start-0x7ffb7edc> - 1f2: 682e flw fa6,200(sp) - 1f4: 0600 addi s0,sp,768 - 1f6: 0000 unimp - 1f8: 6e69 lui t3,0x1a - 1fa: 632d6e73 csrrsi t3,0x632,26 - 1fe: 74736e6f jal t3,37144 <_start-0x7ffc8ebc> - 202: 6e61 lui t3,0x18 - 204: 7374 flw fa3,100(a4) - 206: 682e flw fa6,200(sp) - 208: 0700 addi s0,sp,896 - 20a: 0000 unimp - 20c: 696c flw fa1,84(a0) - 20e: 6762 flw fa4,24(sp) - 210: 2e326363 bltu tp,gp,4f6 <_start-0x7ffffb0a> - 214: 0068 addi a0,sp,12 - 216: 0001 nop - 218: 0000 unimp - 21a: 0105 addi sp,sp,1 - 21c: 0500 addi s0,sp,640 - 21e: a402 fsd ft0,8(sp) - 220: 00ff 0xff - 222: 0380 addi s0,sp,448 - 224: 0aa6 slli s5,s5,0x9 - 226: 0501 addi a0,a0,0 - 228: 09010303 lb t1,144(sp) # b0b1b98 <_start-0x74f4e468> - 22c: 0000 unimp - 22e: 0301 addi t1,t1,0 - 230: 7dd1 lui s11,0xffff4 - 232: 0009 c.nop 2 - 234: 0100 addi s0,sp,128 - 236: 00090103 lb sp,0(s2) # ffffa000 <__BSS_END__+0x7ffe3288> - 23a: 0100 addi s0,sp,128 - 23c: 00090103 lb sp,0(s2) - 240: 0100 addi s0,sp,128 - 242: 00090103 lb sp,0(s2) - 246: 0100 addi s0,sp,128 - 248: 00090103 lb sp,0(s2) - 24c: 0100 addi s0,sp,128 - 24e: 00090103 lb sp,0(s2) - 252: 0100 addi s0,sp,128 - 254: 00090203 lb tp,0(s2) - 258: 0100 addi s0,sp,128 - 25a: 0105 addi sp,sp,1 - 25c: 0306 slli t1,t1,0x1 - 25e: 000902a7 vsb.v v5,(s2),v0.t - 262: 0100 addi s0,sp,128 - 264: 0605 addi a2,a2,1 - 266: 097dd903 lhu s2,151(s11) # ffff4097 <__BSS_END__+0x7ffdd31f> - 26a: 0004 0x4 - 26c: 0501 addi a0,a0,0 - 26e: 01030603 lb a2,16(t1) # ffff8010 <__BSS_END__+0x7ffe1298> - 272: 0409 addi s0,s0,2 - 274: 0100 addi s0,sp,128 - 276: 0605 addi a2,a2,1 - 278: 0306 slli t1,t1,0x1 - 27a: 0900 addi s0,sp,144 - 27c: 0000 unimp - 27e: 0501 addi a0,a0,0 - 280: 01030603 lb a2,16(t1) - 284: 0409 addi s0,s0,2 - 286: 0100 addi s0,sp,128 - 288: 0605 addi a2,a2,1 - 28a: 0306 slli t1,t1,0x1 - 28c: 0900 addi s0,sp,144 - 28e: 0000 unimp - 290: 0501 addi a0,a0,0 - 292: 01030603 lb a2,16(t1) - 296: 0409 addi s0,s0,2 - 298: 0100 addi s0,sp,128 - 29a: 00092503 lw a0,0(s2) - 29e: 0100 addi s0,sp,128 - 2a0: 0605 addi a2,a2,1 - 2a2: 0306 slli t1,t1,0x1 - 2a4: 0900 addi s0,sp,144 - 2a6: 0000 unimp - 2a8: 0501 addi a0,a0,0 - 2aa: 02030607 vlbu.v v12,(t1) - 2ae: 0409 addi s0,s0,2 - 2b0: 0100 addi s0,sp,128 - 2b2: 0a05 addi s4,s4,1 - 2b4: 0306 slli t1,t1,0x1 - 2b6: 0900 addi s0,sp,144 - 2b8: 0008 0x8 - 2ba: 0501 addi a0,a0,0 - 2bc: 0604 addi s1,sp,768 - 2be: 04090403 lb s0,64(s2) - 2c2: 0100 addi s0,sp,128 - 2c4: 00090003 lb zero,0(s2) - 2c8: 0100 addi s0,sp,128 - 2ca: 00090003 lb zero,0(s2) - 2ce: 0100 addi s0,sp,128 - 2d0: 00090003 lb zero,0(s2) - 2d4: 0100 addi s0,sp,128 - 2d6: 00090003 lb zero,0(s2) - 2da: 0100 addi s0,sp,128 - 2dc: 14090003 lb zero,320(s2) - 2e0: 0100 addi s0,sp,128 - 2e2: 18090203 lb tp,384(s2) - 2e6: 0100 addi s0,sp,128 - 2e8: 0705 addi a4,a4,1 - 2ea: 0306 slli t1,t1,0x1 - 2ec: 0900 addi s0,sp,144 - 2ee: 0000 unimp - 2f0: 0501 addi a0,a0,0 - 2f2: 0608 addi a0,sp,768 - 2f4: 04090503 lb a0,64(s2) - 2f8: 0100 addi s0,sp,128 - 2fa: 1105 addi sp,sp,-31 - 2fc: 0306 slli t1,t1,0x1 - 2fe: 0901 addi s2,s2,0 - 300: 0000 unimp - 302: 0501 addi a0,a0,0 - 304: 031e slli t1,t1,0x7 - 306: 0900 addi s0,sp,144 - 308: 0004 0x4 - 30a: 0501 addi a0,a0,0 - 30c: 097f030b 0x97f030b - 310: 0004 0x4 - 312: 0501 addi a0,a0,0 - 314: 0608 addi a0,sp,768 - 316: 04090103 lb sp,64(s2) - 31a: 0100 addi s0,sp,128 - 31c: 0b05 addi s6,s6,1 - 31e: 0306 slli t1,t1,0x1 - 320: 0900 addi s0,sp,144 - 322: 0000 unimp - 324: 0501 addi a0,a0,0 - 326: 0608 addi a0,sp,768 - 328: 04090103 lb sp,64(s2) - 32c: 0100 addi s0,sp,128 - 32e: 0b05 addi s6,s6,1 - 330: 0306 slli t1,t1,0x1 - 332: 0900 addi s0,sp,144 - 334: 0000 unimp - 336: 0501 addi a0,a0,0 - 338: 0604 addi s1,sp,768 - 33a: 04090303 lb t1,64(s2) - 33e: 0100 addi s0,sp,128 - 340: 00090003 lb zero,0(s2) - 344: 0100 addi s0,sp,128 - 346: 00090003 lb zero,0(s2) - 34a: 0100 addi s0,sp,128 - 34c: 00090003 lb zero,0(s2) - 350: 0100 addi s0,sp,128 - 352: 04090003 lb zero,64(s2) - 356: 0100 addi s0,sp,128 - 358: 0c090003 lb zero,192(s2) - 35c: 0100 addi s0,sp,128 - 35e: 00090003 lb zero,0(s2) - 362: 0100 addi s0,sp,128 - 364: 08090003 lb zero,128(s2) - 368: 0100 addi s0,sp,128 - 36a: 0c090003 lb zero,192(s2) - 36e: 0100 addi s0,sp,128 - 370: 00090003 lb zero,0(s2) - 374: 0100 addi s0,sp,128 - 376: 08090003 lb zero,128(s2) - 37a: 0100 addi s0,sp,128 - 37c: 08090003 lb zero,128(s2) - 380: 0100 addi s0,sp,128 - 382: 04090003 lb zero,64(s2) - 386: 0100 addi s0,sp,128 - 388: 04090003 lb zero,64(s2) - 38c: 0100 addi s0,sp,128 - 38e: 08090003 lb zero,128(s2) - 392: 0100 addi s0,sp,128 - 394: 04090003 lb zero,64(s2) - 398: 0100 addi s0,sp,128 - 39a: 04090003 lb zero,64(s2) - 39e: 0100 addi s0,sp,128 - 3a0: 0c090003 lb zero,192(s2) - 3a4: 0100 addi s0,sp,128 - 3a6: 0c090003 lb zero,192(s2) - 3aa: 0100 addi s0,sp,128 - 3ac: 00090003 lb zero,0(s2) - 3b0: 0100 addi s0,sp,128 - 3b2: 08090003 lb zero,128(s2) - 3b6: 0100 addi s0,sp,128 - 3b8: 08090003 lb zero,128(s2) - 3bc: 0100 addi s0,sp,128 - 3be: 04090003 lb zero,64(s2) - 3c2: 0100 addi s0,sp,128 - 3c4: 04090003 lb zero,64(s2) - 3c8: 0100 addi s0,sp,128 - 3ca: 04090003 lb zero,64(s2) - 3ce: 0100 addi s0,sp,128 - 3d0: 00090003 lb zero,0(s2) - 3d4: 0100 addi s0,sp,128 - 3d6: 08090003 lb zero,128(s2) - 3da: 0100 addi s0,sp,128 - 3dc: 00090103 lb sp,0(s2) - 3e0: 0100 addi s0,sp,128 - 3e2: 0b05 addi s6,s6,1 - 3e4: 0306 slli t1,t1,0x1 - 3e6: 00fe slli ra,ra,0x1f - 3e8: 0009 c.nop 2 - 3ea: 0100 addi s0,sp,128 - 3ec: 0405 addi s0,s0,1 - 3ee: 097ef503 0x97ef503 - 3f2: 0008 0x8 - 3f4: 0601 addi a2,a2,0 - 3f6: 14091503 lh a0,320(s2) - 3fa: 0100 addi s0,sp,128 - 3fc: 0705 addi a4,a4,1 - 3fe: 0306 slli t1,t1,0x1 - 400: 0900 addi s0,sp,144 - 402: 0000 unimp - 404: 0501 addi a0,a0,0 - 406: 0606 slli a2,a2,0x1 - 408: 04090103 lb sp,64(s2) - 40c: 0100 addi s0,sp,128 - 40e: 0905 addi s2,s2,1 - 410: 0306 slli t1,t1,0x1 - 412: 0900 addi s0,sp,144 - 414: 0000 unimp - 416: 0501 addi a0,a0,0 - 418: 0604 addi s1,sp,768 - 41a: 08090203 lb tp,128(s2) - 41e: 0100 addi s0,sp,128 - 420: 00090003 lb zero,0(s2) - 424: 0100 addi s0,sp,128 - 426: 00090003 lb zero,0(s2) - 42a: 0100 addi s0,sp,128 - 42c: 00090003 lb zero,0(s2) - 430: 0100 addi s0,sp,128 - 432: 00090003 lb zero,0(s2) - 436: 0100 addi s0,sp,128 - 438: 14090003 lb zero,320(s2) - 43c: 0100 addi s0,sp,128 - 43e: 18090203 lb tp,384(s2) - 442: 0100 addi s0,sp,128 - 444: 0705 addi a4,a4,1 - 446: 0306 slli t1,t1,0x1 - 448: 0900 addi s0,sp,144 - 44a: 0000 unimp - 44c: 0501 addi a0,a0,0 - 44e: 0608 addi a0,sp,768 - 450: 04090903 lb s2,64(s2) - 454: 0100 addi s0,sp,128 - 456: 0b05 addi s6,s6,1 - 458: 0306 slli t1,t1,0x1 - 45a: 0900 addi s0,sp,144 - 45c: 0000 unimp - 45e: 0501 addi a0,a0,0 - 460: 0608 addi a0,sp,768 - 462: 04090103 lb sp,64(s2) - 466: 0100 addi s0,sp,128 - 468: 0b05 addi s6,s6,1 - 46a: 0306 slli t1,t1,0x1 - 46c: 0900 addi s0,sp,144 - 46e: 0000 unimp - 470: 0501 addi a0,a0,0 - 472: 0604 addi s1,sp,768 - 474: 04091203 lh tp,64(s2) - 478: 0100 addi s0,sp,128 - 47a: 00090003 lb zero,0(s2) - 47e: 0100 addi s0,sp,128 - 480: 00090003 lb zero,0(s2) - 484: 0100 addi s0,sp,128 - 486: 00090003 lb zero,0(s2) - 48a: 0100 addi s0,sp,128 - 48c: 04090003 lb zero,64(s2) - 490: 0100 addi s0,sp,128 - 492: 08090003 lb zero,128(s2) - 496: 0100 addi s0,sp,128 - 498: 08090003 lb zero,128(s2) - 49c: 0100 addi s0,sp,128 - 49e: 04090003 lb zero,64(s2) - 4a2: 0100 addi s0,sp,128 - 4a4: 0c090003 lb zero,192(s2) - 4a8: 0100 addi s0,sp,128 - 4aa: 00090003 lb zero,0(s2) - 4ae: 0100 addi s0,sp,128 - 4b0: 08090003 lb zero,128(s2) - 4b4: 0100 addi s0,sp,128 - 4b6: 08090003 lb zero,128(s2) - 4ba: 0100 addi s0,sp,128 - 4bc: 04090003 lb zero,64(s2) - 4c0: 0100 addi s0,sp,128 - 4c2: 04090003 lb zero,64(s2) - 4c6: 0100 addi s0,sp,128 - 4c8: 08090003 lb zero,128(s2) - 4cc: 0100 addi s0,sp,128 - 4ce: 04090003 lb zero,64(s2) - 4d2: 0100 addi s0,sp,128 - 4d4: 04090003 lb zero,64(s2) - 4d8: 0100 addi s0,sp,128 - 4da: 0c090003 lb zero,192(s2) - 4de: 0100 addi s0,sp,128 - 4e0: 0c090003 lb zero,192(s2) - 4e4: 0100 addi s0,sp,128 - 4e6: 00090003 lb zero,0(s2) - 4ea: 0100 addi s0,sp,128 - 4ec: 08090003 lb zero,128(s2) - 4f0: 0100 addi s0,sp,128 - 4f2: 08090003 lb zero,128(s2) - 4f6: 0100 addi s0,sp,128 - 4f8: 04090003 lb zero,64(s2) - 4fc: 0100 addi s0,sp,128 - 4fe: 04090003 lb zero,64(s2) - 502: 0100 addi s0,sp,128 - 504: 04090003 lb zero,64(s2) - 508: 0100 addi s0,sp,128 - 50a: 00090003 lb zero,0(s2) - 50e: 0100 addi s0,sp,128 - 510: 08090003 lb zero,128(s2) - 514: 0100 addi s0,sp,128 - 516: 0305 addi t1,t1,1 - 518: 0900e303 0x900e303 - 51c: 0000 unimp - 51e: 0301 addi t1,t1,0 - 520: 0901 addi s2,s2,0 - 522: 0000 unimp - 524: 0501 addi a0,a0,0 - 526: 0601 addi a2,a2,0 - 528: 0900e103 0x900e103 - 52c: 0000 unimp - 52e: 0501 addi a0,a0,0 - 530: 0304 addi s1,sp,384 - 532: 7e9d lui t4,0xfffe7 - 534: 0809 addi a6,a6,2 - 536: 0100 addi s0,sp,128 - 538: 0805 addi a6,a6,1 - 53a: 0306 slli t1,t1,0x1 - 53c: 0912 slli s2,s2,0x4 - 53e: 0014 0x14 - 540: 0301 addi t1,t1,0 - 542: 0902 c.slli64 s2 - 544: 0000 unimp - 546: 0501 addi a0,a0,0 - 548: 0003060b 0x3060b - 54c: 0009 c.nop 2 - 54e: 0100 addi s0,sp,128 - 550: 0805 addi a6,a6,1 - 552: 0306 slli t1,t1,0x1 - 554: 0901 addi s2,s2,0 - 556: 0004 0x4 - 558: 0501 addi a0,a0,0 - 55a: 0003060b 0x3060b - 55e: 0009 c.nop 2 - 560: 0100 addi s0,sp,128 - 562: 0805 addi a6,a6,1 - 564: 0306 slli t1,t1,0x1 - 566: 0901 addi s2,s2,0 - 568: 0004 0x4 - 56a: 0501 addi a0,a0,0 - 56c: 0103060b 0x103060b - 570: 0009 c.nop 2 - 572: 0100 addi s0,sp,128 - 574: 1e05 addi t3,t3,-31 - 576: 04097f03 0x4097f03 - 57a: 0100 addi s0,sp,128 - 57c: 0805 addi a6,a6,1 - 57e: 04090303 lb t1,64(s2) - 582: 0100 addi s0,sp,128 - 584: 1105 addi sp,sp,-31 - 586: 04097d03 0x4097d03 - 58a: 0100 addi s0,sp,128 - 58c: 0805 addi a6,a6,1 - 58e: 04090303 lb t1,64(s2) - 592: 0100 addi s0,sp,128 - 594: 0b05 addi s6,s6,1 - 596: 04097d03 0x4097d03 - 59a: 0100 addi s0,sp,128 - 59c: 0805 addi a6,a6,1 - 59e: 0306 slli t1,t1,0x1 - 5a0: 0901 addi s2,s2,0 - 5a2: 0004 0x4 - 5a4: 0301 addi t1,t1,0 - 5a6: 0902 c.slli64 s2 - 5a8: 0000 unimp - 5aa: 0301 addi t1,t1,0 - 5ac: 0900 addi s0,sp,144 - 5ae: 0000 unimp - 5b0: 0301 addi t1,t1,0 - 5b2: 0900 addi s0,sp,144 - 5b4: 0000 unimp - 5b6: 0301 addi t1,t1,0 - 5b8: 0900 addi s0,sp,144 - 5ba: 0000 unimp - 5bc: 0301 addi t1,t1,0 - 5be: 0900 addi s0,sp,144 - 5c0: 0000 unimp - 5c2: 0301 addi t1,t1,0 - 5c4: 0900 addi s0,sp,144 - 5c6: 0008 0x8 - 5c8: 0301 addi t1,t1,0 - 5ca: 0900 addi s0,sp,144 - 5cc: 0000 unimp - 5ce: 0301 addi t1,t1,0 - 5d0: 0900 addi s0,sp,144 - 5d2: 0008 0x8 - 5d4: 0301 addi t1,t1,0 - 5d6: 0900 addi s0,sp,144 - 5d8: 000c 0xc - 5da: 0301 addi t1,t1,0 - 5dc: 0900 addi s0,sp,144 - 5de: 0000 unimp - 5e0: 0301 addi t1,t1,0 - 5e2: 0900 addi s0,sp,144 - 5e4: 0008 0x8 - 5e6: 0301 addi t1,t1,0 - 5e8: 0900 addi s0,sp,144 - 5ea: 0008 0x8 - 5ec: 0301 addi t1,t1,0 - 5ee: 0900 addi s0,sp,144 - 5f0: 0004 0x4 - 5f2: 0301 addi t1,t1,0 - 5f4: 0900 addi s0,sp,144 - 5f6: 0004 0x4 - 5f8: 0301 addi t1,t1,0 - 5fa: 0900 addi s0,sp,144 - 5fc: 0008 0x8 - 5fe: 0301 addi t1,t1,0 - 600: 0900 addi s0,sp,144 - 602: 0004 0x4 - 604: 0301 addi t1,t1,0 - 606: 0900 addi s0,sp,144 - 608: 0004 0x4 - 60a: 0301 addi t1,t1,0 - 60c: 0900 addi s0,sp,144 - 60e: 000c 0xc - 610: 0301 addi t1,t1,0 - 612: 0900 addi s0,sp,144 - 614: 0008 0x8 - 616: 0301 addi t1,t1,0 - 618: 0900 addi s0,sp,144 - 61a: 0004 0x4 - 61c: 0301 addi t1,t1,0 - 61e: 0900 addi s0,sp,144 - 620: 0008 0x8 - 622: 0301 addi t1,t1,0 - 624: 0900 addi s0,sp,144 - 626: 0008 0x8 - 628: 0301 addi t1,t1,0 - 62a: 0900 addi s0,sp,144 - 62c: 0004 0x4 - 62e: 0301 addi t1,t1,0 - 630: 0900 addi s0,sp,144 - 632: 0004 0x4 - 634: 0301 addi t1,t1,0 - 636: 0900 addi s0,sp,144 - 638: 0008 0x8 - 63a: 0301 addi t1,t1,0 - 63c: 0900 addi s0,sp,144 - 63e: 0004 0x4 - 640: 0301 addi t1,t1,0 - 642: 0900 addi s0,sp,144 - 644: 0008 0x8 - 646: 0501 addi a0,a0,0 - 648: 09150307 vlsbu.v v6,(a0),a7,v0.t - 64c: 0004 0x4 - 64e: 0501 addi a0,a0,0 - 650: 060a slli a2,a2,0x2 - 652: 00090003 lb zero,0(s2) - 656: 0100 addi s0,sp,128 - 658: 0405 addi s0,s0,1 - 65a: 0306 slli t1,t1,0x1 - 65c: 00040913 mv s2,s0 - 660: 0301 addi t1,t1,0 - 662: 0900 addi s0,sp,144 - 664: 0000 unimp - 666: 0301 addi t1,t1,0 - 668: 0900 addi s0,sp,144 - 66a: 0000 unimp - 66c: 0301 addi t1,t1,0 - 66e: 0900 addi s0,sp,144 - 670: 0000 unimp - 672: 0301 addi t1,t1,0 - 674: 0900 addi s0,sp,144 - 676: 0000 unimp - 678: 0301 addi t1,t1,0 - 67a: 0900 addi s0,sp,144 - 67c: 0014 0x14 - 67e: 0301 addi t1,t1,0 - 680: 0901 addi s2,s2,0 - 682: 0020 addi s0,sp,8 - 684: 0501 addi a0,a0,0 - 686: 00030607 vlbu.v v12,(t1),v0.t - 68a: 0009 c.nop 2 - 68c: 0100 addi s0,sp,128 - 68e: 0805 addi a6,a6,1 - 690: 0306 slli t1,t1,0x1 - 692: 090a slli s2,s2,0x2 - 694: 0004 0x4 - 696: 0601 addi a2,a2,0 - 698: 00090203 lb tp,0(s2) - 69c: 0100 addi s0,sp,128 - 69e: 0b05 addi s6,s6,1 - 6a0: 04097e03 0x4097e03 - 6a4: 0100 addi s0,sp,128 - 6a6: 1405 addi s0,s0,-31 - 6a8: 04090003 lb zero,64(s2) - 6ac: 0100 addi s0,sp,128 - 6ae: 0405 addi s0,s0,1 - 6b0: 0c097503 0xc097503 - 6b4: 0100 addi s0,sp,128 - 6b6: 0805 addi a6,a6,1 - 6b8: 0306 slli t1,t1,0x1 - 6ba: 091e slli s2,s2,0x7 - 6bc: 0014 0x14 - 6be: 0301 addi t1,t1,0 - 6c0: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> - 6c4: 0301 addi t1,t1,0 - 6c6: 0902 c.slli64 s2 - 6c8: 0000 unimp - 6ca: 0501 addi a0,a0,0 - 6cc: 061e slli a2,a2,0x7 - 6ce: 00090003 lb zero,0(s2) - 6d2: 0100 addi s0,sp,128 - 6d4: 1105 addi sp,sp,-31 - 6d6: 04090003 lb zero,64(s2) - 6da: 0100 addi s0,sp,128 - 6dc: 0b05 addi s6,s6,1 - 6de: 04090003 lb zero,64(s2) - 6e2: 0100 addi s0,sp,128 - 6e4: 0805 addi a6,a6,1 - 6e6: 0306 slli t1,t1,0x1 - 6e8: 0901 addi s2,s2,0 - 6ea: 0004 0x4 - 6ec: 0601 addi a2,a2,0 - 6ee: 00090503 lb a0,0(s2) - 6f2: 0100 addi s0,sp,128 - 6f4: 0b05 addi s6,s6,1 - 6f6: 04097c03 0x4097c03 - 6fa: 0100 addi s0,sp,128 - 6fc: 0805 addi a6,a6,1 - 6fe: 04090403 lb s0,64(s2) - 702: 0100 addi s0,sp,128 - 704: 1105 addi sp,sp,-31 - 706: 04097d03 0x4097d03 - 70a: 0100 addi s0,sp,128 - 70c: 1e05 addi t3,t3,-31 - 70e: 04090003 lb zero,64(s2) - 712: 0100 addi s0,sp,128 - 714: 0b05 addi s6,s6,1 - 716: 04090003 lb zero,64(s2) - 71a: 0100 addi s0,sp,128 - 71c: 0805 addi a6,a6,1 - 71e: 04090303 lb t1,64(s2) - 722: 0100 addi s0,sp,128 - 724: 0b05 addi s6,s6,1 - 726: 0c097b03 0xc097b03 - 72a: 0100 addi s0,sp,128 - 72c: 0805 addi a6,a6,1 - 72e: 0306 slli t1,t1,0x1 - 730: 0901 addi s2,s2,0 - 732: 0004 0x4 - 734: 0301 addi t1,t1,0 - 736: 0901 addi s2,s2,0 - 738: 0000 unimp - 73a: 0301 addi t1,t1,0 - 73c: 0901 addi s2,s2,0 - 73e: 0000 unimp - 740: 0301 addi t1,t1,0 - 742: 0902 c.slli64 s2 - 744: 0000 unimp - 746: 0301 addi t1,t1,0 - 748: 0900 addi s0,sp,144 - 74a: 0000 unimp - 74c: 0301 addi t1,t1,0 - 74e: 0900 addi s0,sp,144 - 750: 0000 unimp - 752: 0301 addi t1,t1,0 - 754: 0900 addi s0,sp,144 - 756: 0000 unimp - 758: 0301 addi t1,t1,0 - 75a: 0900 addi s0,sp,144 - 75c: 0000 unimp - 75e: 0301 addi t1,t1,0 - 760: 0900 addi s0,sp,144 - 762: 0000 unimp - 764: 0301 addi t1,t1,0 - 766: 0900 addi s0,sp,144 - 768: 0000 unimp - 76a: 0301 addi t1,t1,0 - 76c: 0900 addi s0,sp,144 - 76e: 0004 0x4 - 770: 0301 addi t1,t1,0 - 772: 0900 addi s0,sp,144 - 774: 000c 0xc - 776: 0301 addi t1,t1,0 - 778: 0900 addi s0,sp,144 - 77a: 0000 unimp - 77c: 0301 addi t1,t1,0 - 77e: 0900 addi s0,sp,144 - 780: 0008 0x8 - 782: 0301 addi t1,t1,0 - 784: 0900 addi s0,sp,144 - 786: 0008 0x8 - 788: 0301 addi t1,t1,0 - 78a: 0900 addi s0,sp,144 - 78c: 0004 0x4 - 78e: 0301 addi t1,t1,0 - 790: 0900 addi s0,sp,144 - 792: 0004 0x4 - 794: 0301 addi t1,t1,0 - 796: 0900 addi s0,sp,144 - 798: 0008 0x8 - 79a: 0301 addi t1,t1,0 - 79c: 0900 addi s0,sp,144 - 79e: 0004 0x4 - 7a0: 0301 addi t1,t1,0 - 7a2: 0900 addi s0,sp,144 - 7a4: 0004 0x4 - 7a6: 0301 addi t1,t1,0 - 7a8: 0900 addi s0,sp,144 - 7aa: 0004 0x4 - 7ac: 0301 addi t1,t1,0 - 7ae: 0900 addi s0,sp,144 - 7b0: 0008 0x8 - 7b2: 0301 addi t1,t1,0 - 7b4: 0900 addi s0,sp,144 - 7b6: 000c 0xc - 7b8: 0301 addi t1,t1,0 - 7ba: 0900 addi s0,sp,144 - 7bc: 0008 0x8 - 7be: 0301 addi t1,t1,0 - 7c0: 0900 addi s0,sp,144 - 7c2: 0008 0x8 - 7c4: 0301 addi t1,t1,0 - 7c6: 0900 addi s0,sp,144 - 7c8: 0004 0x4 - 7ca: 0301 addi t1,t1,0 - 7cc: 0900 addi s0,sp,144 - 7ce: 0004 0x4 - 7d0: 0301 addi t1,t1,0 - 7d2: 0900 addi s0,sp,144 - 7d4: 0008 0x8 - 7d6: 0301 addi t1,t1,0 - 7d8: 0900 addi s0,sp,144 - 7da: 0008 0x8 - 7dc: 0601 addi a2,a2,0 - 7de: 00090103 lb sp,0(s2) - 7e2: 0100 addi s0,sp,128 - 7e4: 04097f03 0x4097f03 - 7e8: 0100 addi s0,sp,128 - 7ea: 0306 slli t1,t1,0x1 - 7ec: 0900 addi s0,sp,144 - 7ee: 0004 0x4 - 7f0: 0301 addi t1,t1,0 - 7f2: 0901 addi s2,s2,0 - 7f4: 0000 unimp - 7f6: 0301 addi t1,t1,0 - 7f8: 0900 addi s0,sp,144 - 7fa: 0000 unimp - 7fc: 0301 addi t1,t1,0 - 7fe: 0900 addi s0,sp,144 - 800: 0000 unimp - 802: 0301 addi t1,t1,0 - 804: 0900 addi s0,sp,144 - 806: 0000 unimp - 808: 0301 addi t1,t1,0 - 80a: 0900 addi s0,sp,144 - 80c: 0008 0x8 - 80e: 0301 addi t1,t1,0 - 810: 0900 addi s0,sp,144 - 812: 0004 0x4 - 814: 0301 addi t1,t1,0 - 816: 0900 addi s0,sp,144 - 818: 0004 0x4 - 81a: 0301 addi t1,t1,0 - 81c: 0900 addi s0,sp,144 - 81e: 0004 0x4 - 820: 0301 addi t1,t1,0 - 822: 0900 addi s0,sp,144 - 824: 0004 0x4 - 826: 0301 addi t1,t1,0 - 828: 0900 addi s0,sp,144 - 82a: 0000 unimp - 82c: 0301 addi t1,t1,0 - 82e: 0900 addi s0,sp,144 - 830: 0004 0x4 - 832: 0301 addi t1,t1,0 - 834: 0900 addi s0,sp,144 - 836: 0014 0x14 - 838: 0301 addi t1,t1,0 - 83a: 0900 addi s0,sp,144 - 83c: 0000 unimp - 83e: 0301 addi t1,t1,0 - 840: 0900 addi s0,sp,144 - 842: 0000 unimp - 844: 0301 addi t1,t1,0 - 846: 0900 addi s0,sp,144 - 848: 0004 0x4 - 84a: 0301 addi t1,t1,0 - 84c: 0900 addi s0,sp,144 - 84e: 0004 0x4 - 850: 0301 addi t1,t1,0 - 852: 0900 addi s0,sp,144 - 854: 0008 0x8 - 856: 0301 addi t1,t1,0 - 858: 0902 c.slli64 s2 - 85a: 0000 unimp - 85c: 0501 addi a0,a0,0 - 85e: 0003060b 0x3060b - 862: 0009 c.nop 2 - 864: 0100 addi s0,sp,128 - 866: 1405 addi s0,s0,-31 - 868: 04090003 lb zero,64(s2) - 86c: 0100 addi s0,sp,128 - 86e: 0805 addi a6,a6,1 - 870: 04097e03 0x4097e03 - 874: 0100 addi s0,sp,128 - 876: 0b05 addi s6,s6,1 - 878: 14097d03 0x14097d03 - 87c: 0100 addi s0,sp,128 - 87e: 0805 addi a6,a6,1 - 880: 04090303 lb t1,64(s2) - 884: 0100 addi s0,sp,128 - 886: 0b05 addi s6,s6,1 - 888: 04090803 lb a6,64(s2) - 88c: 0100 addi s0,sp,128 - 88e: 2105 jal cae <_start-0x7ffff352> - 890: 04097a03 0x4097a03 - 894: 0100 addi s0,sp,128 - 896: 0505 addi a0,a0,1 - 898: 0306 slli t1,t1,0x1 - 89a: 0902 c.slli64 s2 - 89c: 0004 0x4 - 89e: 0501 addi a0,a0,0 - 8a0: 00030607 vlbu.v v12,(t1),v0.t - 8a4: 0009 c.nop 2 - 8a6: 0100 addi s0,sp,128 - 8a8: 0505 addi a0,a0,1 - 8aa: 0306 slli t1,t1,0x1 - 8ac: 0901 addi s2,s2,0 - 8ae: 0004 0x4 - 8b0: 0301 addi t1,t1,0 - 8b2: 0900 addi s0,sp,144 - 8b4: 0000 unimp - 8b6: 0301 addi t1,t1,0 - 8b8: 0900 addi s0,sp,144 - 8ba: 0000 unimp - 8bc: 0301 addi t1,t1,0 - 8be: 0900 addi s0,sp,144 - 8c0: 0000 unimp - 8c2: 0301 addi t1,t1,0 - 8c4: 0900 addi s0,sp,144 - 8c6: 0000 unimp - 8c8: 0501 addi a0,a0,0 - 8ca: 43030607 vlseg3buff.v v12,(t1) - 8ce: 0409 addi s0,s0,2 - 8d0: 0100 addi s0,sp,128 - 8d2: 04097f03 0x4097f03 - 8d6: 0100 addi s0,sp,128 - 8d8: 0809 addi a6,a6,2 - 8da: 0000 unimp - 8dc: 0101 addi sp,sp,0 - 8de: 098a slli s3,s3,0x2 - 8e0: 0000 unimp - 8e2: 02100003 lb zero,33(zero) # 21 <_start-0x7fffffdf> - 8e6: 0000 unimp - 8e8: 0101 addi sp,sp,0 - 8ea: 000d0efb 0xd0efb - 8ee: 0101 addi sp,sp,0 - 8f0: 0101 addi sp,sp,0 - 8f2: 0000 unimp - 8f4: 0100 addi s0,sp,128 - 8f6: 0000 unimp - 8f8: 2e01 jal c08 <_start-0x7ffff3f8> - 8fa: 2f2e fld ft10,200(sp) - 8fc: 2e2e fld ft8,200(sp) - 8fe: 2f2e2e2f 0x2f2e2e2f - 902: 2e2e fld ft8,200(sp) - 904: 7369722f 0x7369722f - 908: 672d7663 bgeu s10,s2,f74 <_start-0x7ffff08c> - 90c: 6c2f6363 bltu t5,sp,fd2 <_start-0x7ffff02e> - 910: 6269 lui tp,0x1a - 912: 00636367 0x636367 - 916: 6d6f682f 0x6d6f682f - 91a: 2f65 jal 10d2 <_start-0x7fffef2e> - 91c: 7270 flw fa2,100(a2) - 91e: 7969 lui s2,0xffffa - 920: 2f61 jal 10b8 <_start-0x7fffef48> - 922: 6564 flw fs1,76(a0) - 924: 2f76 fld ft10,344(sp) - 926: 6972 flw fs2,28(sp) - 928: 5f766373 csrrsi t1,0x5f7,12 - 92c: 6576 flw fa0,92(sp) - 92e: 69722f63 0x69722f63 - 932: 2d766373 csrrsi t1,0x2d7,12 - 936: 2f756e67 0x2f756e67 - 93a: 6972 flw fs2,28(sp) - 93c: 33766373 csrrsi t1,mhpmevent23,12 - 940: 2d32 fld fs10,264(sp) - 942: 6e75 lui t3,0x1d - 944: 776f6e6b 0x776f6e6b - 948: 2d6e fld fs10,216(sp) - 94a: 6c65 lui s8,0x19 - 94c: 2f66 fld ft10,88(sp) - 94e: 6e69 lui t3,0x1a - 950: 64756c63 bltu a0,t2,fa8 <_start-0x7ffff058> - 954: 2f65 jal 110c <_start-0x7fffeef4> - 956: 00737973 csrrci s2,0x7,6 - 95a: 6d6f682f 0x6d6f682f - 95e: 2f65 jal 1116 <_start-0x7fffeeea> - 960: 7270 flw fa2,100(a2) - 962: 7969 lui s2,0xffffa - 964: 2f61 jal 10fc <_start-0x7fffef04> - 966: 6544 flw fs1,12(a0) - 968: 6f746b73 csrrsi s6,0x6f7,8 - 96c: 2f70 fld fa2,216(a4) - 96e: 6972 flw fs2,28(sp) - 970: 2d766373 csrrsi t1,0x2d7,12 - 974: 2d756e67 0x2d756e67 - 978: 6f74 flw fa3,92(a4) - 97a: 68636c6f jal s8,37000 <_start-0x7ffc9000> - 97e: 6961 lui s2,0x18 - 980: 2f6e fld ft10,216(sp) - 982: 7562 flw fa0,56(sp) - 984: 6c69 lui s8,0x1a - 986: 2f64 fld fs1,216(a4) - 988: 7562 flw fa0,56(sp) - 98a: 6c69 lui s8,0x1a - 98c: 2d64 fld fs1,216(a0) - 98e: 2d636367 0x2d636367 - 992: 656e flw fa0,216(sp) - 994: 62696c77 0x62696c77 - 998: 732d lui t1,0xfffeb - 99a: 6174 flw fa3,68(a0) - 99c: 2f326567 0x2f326567 - 9a0: 2f636367 0x2f636367 - 9a4: 6e69 lui t3,0x1a - 9a6: 64756c63 bltu a0,t2,ffe <_start-0x7ffff002> - 9aa: 0065 c.nop 25 - 9ac: 6d6f682f 0x6d6f682f - 9b0: 2f65 jal 1168 <_start-0x7fffee98> - 9b2: 7270 flw fa2,100(a2) - 9b4: 7969 lui s2,0xffffa - 9b6: 2f61 jal 114e <_start-0x7fffeeb2> - 9b8: 6564 flw fs1,76(a0) - 9ba: 2f76 fld ft10,344(sp) - 9bc: 6972 flw fs2,28(sp) - 9be: 5f766373 csrrsi t1,0x5f7,12 - 9c2: 6576 flw fa0,92(sp) - 9c4: 69722f63 0x69722f63 - 9c8: 2d766373 csrrsi t1,0x2d7,12 - 9cc: 2f756e67 0x2f756e67 - 9d0: 6972 flw fs2,28(sp) - 9d2: 33766373 csrrsi t1,mhpmevent23,12 - 9d6: 2d32 fld fs10,264(sp) - 9d8: 6e75 lui t3,0x1d - 9da: 776f6e6b 0x776f6e6b - 9de: 2d6e fld fs10,216(sp) - 9e0: 6c65 lui s8,0x19 - 9e2: 2f66 fld ft10,88(sp) - 9e4: 6e69 lui t3,0x1a - 9e6: 64756c63 bltu a0,t2,103e <_start-0x7fffefc2> - 9ea: 0065 c.nop 25 - 9ec: 2e2e fld ft8,200(sp) - 9ee: 2f2e2e2f 0x2f2e2e2f - 9f2: 2e2e fld ft8,200(sp) - 9f4: 2f2e2e2f 0x2f2e2e2f - 9f8: 6972 flw fs2,28(sp) - 9fa: 2d766373 csrrsi t1,0x2d7,12 - 9fe: 2f636367 0x2f636367 - a02: 696c flw fa1,84(a0) - a04: 6762 flw fa4,24(sp) - a06: 2e2f6363 bltu t5,sp,cec <_start-0x7ffff314> - a0a: 2f2e fld ft10,200(sp) - a0c: 6e69 lui t3,0x1a - a0e: 64756c63 bltu a0,t2,1066 <_start-0x7fffef9a> - a12: 0065 c.nop 25 - a14: 2e2e fld ft8,200(sp) - a16: 2f2e2e2f 0x2f2e2e2f - a1a: 2e2e fld ft8,200(sp) - a1c: 2f2e2e2f 0x2f2e2e2f - a20: 6972 flw fs2,28(sp) - a22: 2d766373 csrrsi t1,0x2d7,12 - a26: 2f636367 0x2f636367 - a2a: 696c flw fa1,84(a0) - a2c: 6762 flw fa4,24(sp) - a2e: 2e2f6363 bltu t5,sp,d14 <_start-0x7ffff2ec> - a32: 2f2e fld ft10,200(sp) - a34: 2f636367 0x2f636367 - a38: 666e6f63 bltu t3,t1,10b6 <_start-0x7fffef4a> - a3c: 6769 lui a4,0x1a - a3e: 7369722f 0x7369722f - a42: 2e007663 bgeu zero,zero,d2e <_start-0x7ffff2d2> - a46: 2f2e fld ft10,200(sp) - a48: 2e2e fld ft8,200(sp) - a4a: 672f2e2f amoand.w.aqrl t3,s2,(t5) - a4e: 00006363 bltu zero,zero,a54 <_start-0x7ffff5ac> - a52: 696c flw fa1,84(a0) - a54: 6762 flw fa4,24(sp) - a56: 2e326363 bltu tp,gp,d3c <_start-0x7ffff2c4> - a5a: 00010063 beqz sp,a5a <_start-0x7ffff5a6> - a5e: 6c00 flw fs0,24(s0) - a60: 2e6b636f jal t1,b6d46 <_start-0x7ff492ba> - a64: 0068 addi a0,sp,12 - a66: 0002 c.slli64 zero - a68: 5f00 lw s0,56(a4) - a6a: 7974 flw fa3,116(a0) - a6c: 6570 flw fa2,76(a0) - a6e: 00682e73 csrrs t3,0x6,a6 - a72: 0002 c.slli64 zero - a74: 7300 flw fs0,32(a4) - a76: 6474 flw fa3,76(s0) - a78: 6564 flw fs1,76(a0) - a7a: 2e66 fld ft8,88(sp) - a7c: 0068 addi a0,sp,12 - a7e: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> - a82: 6565 lui a0,0x19 - a84: 746e flw fs0,248(sp) - a86: 682e flw fa6,200(sp) - a88: 0200 addi s0,sp,256 - a8a: 0000 unimp - a8c: 7265 lui tp,0xffff9 - a8e: 6e72 flw ft8,28(sp) - a90: 00682e6f jal t3,82a96 <_start-0x7ff7d56a> - a94: 0002 c.slli64 zero - a96: 7300 flw fs0,32(a4) - a98: 6474 flw fa3,76(s0) - a9a: 696c flw fa1,84(a0) - a9c: 2e62 fld ft8,24(sp) - a9e: 0068 addi a0,sp,12 - aa0: 0004 0x4 - aa2: 7500 flw fs0,40(a0) - aa4: 696e flw fs2,216(sp) - aa6: 2e647473 csrrci s0,0x2e6,8 - aaa: 0068 addi a0,sp,12 - aac: 0002 c.slli64 zero - aae: 7400 flw fs0,40(s0) - ab0: 6d69 lui s10,0x1a - ab2: 2e65 jal e6a <_start-0x7ffff196> - ab4: 0068 addi a0,sp,12 - ab6: 0004 0x4 - ab8: 6800 flw fs0,16(s0) - aba: 7361 lui t1,0xffff8 - abc: 7468 flw fa0,108(s0) - abe: 6261 lui tp,0x18 - ac0: 682e flw fa6,200(sp) - ac2: 0500 addi s0,sp,640 - ac4: 0000 unimp - ac6: 6972 flw fs2,28(sp) - ac8: 2d766373 csrrsi t1,0x2d7,12 - acc: 7374706f j 48a02 <_start-0x7ffb75fe> - ad0: 682e flw fa6,200(sp) - ad2: 0600 addi s0,sp,768 - ad4: 0000 unimp - ad6: 6e69 lui t3,0x1a - ad8: 632d6e73 csrrsi t3,0x632,26 - adc: 74736e6f jal t3,37a22 <_start-0x7ffc85de> - ae0: 6e61 lui t3,0x18 - ae2: 7374 flw fa3,100(a4) - ae4: 682e flw fa6,200(sp) - ae6: 0700 addi s0,sp,896 - ae8: 0000 unimp - aea: 696c flw fa1,84(a0) - aec: 6762 flw fa4,24(sp) - aee: 2e326363 bltu tp,gp,dd4 <_start-0x7ffff22c> - af2: 0068 addi a0,sp,12 - af4: 0001 nop - af6: 0000 unimp - af8: 0105 addi sp,sp,1 - afa: 0500 addi s0,sp,640 - afc: d802 sw zero,48(sp) - afe: 03800103 lb sp,56(zero) # 38 <_start-0x7fffffc8> - b02: 0a9a slli s5,s5,0x6 - b04: 0501 addi a0,a0,0 - b06: 09010303 lb t1,144(sp) - b0a: 0000 unimp - b0c: 0301 addi t1,t1,0 - b0e: 0902 c.slli64 s2 - b10: 0000 unimp - b12: 0301 addi t1,t1,0 - b14: 00097ddb 0x97ddb - b18: 0100 addi s0,sp,128 - b1a: 00090103 lb sp,0(s2) # ffffa000 <__BSS_END__+0x7ffe3288> - b1e: 0100 addi s0,sp,128 - b20: 00090103 lb sp,0(s2) - b24: 0100 addi s0,sp,128 - b26: 00090103 lb sp,0(s2) - b2a: 0100 addi s0,sp,128 - b2c: 00090103 lb sp,0(s2) - b30: 0100 addi s0,sp,128 - b32: 00090103 lb sp,0(s2) - b36: 0100 addi s0,sp,128 - b38: 00090203 lb tp,0(s2) - b3c: 0100 addi s0,sp,128 - b3e: 0605 addi a2,a2,1 - b40: 0306 slli t1,t1,0x1 - b42: 0900 addi s0,sp,144 - b44: 0000 unimp - b46: 0501 addi a0,a0,0 - b48: 01030603 lb a2,16(t1) # ffff8010 <__BSS_END__+0x7ffe1298> - b4c: 0409 addi s0,s0,2 - b4e: 0100 addi s0,sp,128 - b50: 0605 addi a2,a2,1 - b52: 0306 slli t1,t1,0x1 - b54: 0900 addi s0,sp,144 - b56: 0000 unimp - b58: 0501 addi a0,a0,0 - b5a: 01030603 lb a2,16(t1) - b5e: 0409 addi s0,s0,2 - b60: 0100 addi s0,sp,128 - b62: 0605 addi a2,a2,1 - b64: 0306 slli t1,t1,0x1 - b66: 0900 addi s0,sp,144 - b68: 0000 unimp - b6a: 0501 addi a0,a0,0 - b6c: 01030603 lb a2,16(t1) - b70: 0409 addi s0,s0,2 - b72: 0100 addi s0,sp,128 - b74: 0605 addi a2,a2,1 - b76: 0306 slli t1,t1,0x1 - b78: 0900 addi s0,sp,144 - b7a: 0000 unimp - b7c: 0501 addi a0,a0,0 - b7e: 25030603 lb a2,592(t1) - b82: 0409 addi s0,s0,2 - b84: 0100 addi s0,sp,128 - b86: 0605 addi a2,a2,1 - b88: 0306 slli t1,t1,0x1 - b8a: 0900 addi s0,sp,144 - b8c: 0000 unimp - b8e: 0501 addi a0,a0,0 - b90: 02030607 vlbu.v v12,(t1) - b94: 0409 addi s0,s0,2 - b96: 0100 addi s0,sp,128 - b98: 0a05 addi s4,s4,1 - b9a: 0306 slli t1,t1,0x1 - b9c: 0900 addi s0,sp,144 - b9e: 0008 0x8 - ba0: 0501 addi a0,a0,0 - ba2: 0604 addi s1,sp,768 - ba4: 04090403 lb s0,64(s2) - ba8: 0100 addi s0,sp,128 - baa: 00090003 lb zero,0(s2) - bae: 0100 addi s0,sp,128 - bb0: 00090003 lb zero,0(s2) - bb4: 0100 addi s0,sp,128 - bb6: 00090003 lb zero,0(s2) - bba: 0100 addi s0,sp,128 - bbc: 00090003 lb zero,0(s2) - bc0: 0100 addi s0,sp,128 - bc2: 14090003 lb zero,320(s2) - bc6: 0100 addi s0,sp,128 - bc8: 18090203 lb tp,384(s2) - bcc: 0100 addi s0,sp,128 - bce: 0705 addi a4,a4,1 - bd0: 0306 slli t1,t1,0x1 - bd2: 0900 addi s0,sp,144 - bd4: 0000 unimp - bd6: 0501 addi a0,a0,0 - bd8: 0608 addi a0,sp,768 - bda: 04090503 lb a0,64(s2) - bde: 0100 addi s0,sp,128 - be0: 1105 addi sp,sp,-31 - be2: 0306 slli t1,t1,0x1 - be4: 0901 addi s2,s2,0 - be6: 0000 unimp - be8: 0501 addi a0,a0,0 - bea: 031e slli t1,t1,0x7 - bec: 0900 addi s0,sp,144 - bee: 0004 0x4 - bf0: 0501 addi a0,a0,0 - bf2: 097f030b 0x97f030b - bf6: 0004 0x4 - bf8: 0501 addi a0,a0,0 - bfa: 0608 addi a0,sp,768 - bfc: 04090103 lb sp,64(s2) - c00: 0100 addi s0,sp,128 - c02: 0b05 addi s6,s6,1 - c04: 0306 slli t1,t1,0x1 - c06: 0900 addi s0,sp,144 - c08: 0000 unimp - c0a: 0501 addi a0,a0,0 - c0c: 0608 addi a0,sp,768 - c0e: 04090103 lb sp,64(s2) - c12: 0100 addi s0,sp,128 - c14: 0b05 addi s6,s6,1 - c16: 0306 slli t1,t1,0x1 - c18: 0900 addi s0,sp,144 - c1a: 0000 unimp - c1c: 0501 addi a0,a0,0 - c1e: 0604 addi s1,sp,768 - c20: 04090303 lb t1,64(s2) - c24: 0100 addi s0,sp,128 - c26: 00090003 lb zero,0(s2) - c2a: 0100 addi s0,sp,128 - c2c: 00090003 lb zero,0(s2) - c30: 0100 addi s0,sp,128 - c32: 00090003 lb zero,0(s2) - c36: 0100 addi s0,sp,128 - c38: 04090003 lb zero,64(s2) - c3c: 0100 addi s0,sp,128 - c3e: 0c090003 lb zero,192(s2) - c42: 0100 addi s0,sp,128 - c44: 00090003 lb zero,0(s2) - c48: 0100 addi s0,sp,128 - c4a: 08090003 lb zero,128(s2) - c4e: 0100 addi s0,sp,128 - c50: 0c090003 lb zero,192(s2) - c54: 0100 addi s0,sp,128 - c56: 00090003 lb zero,0(s2) - c5a: 0100 addi s0,sp,128 - c5c: 04090003 lb zero,64(s2) - c60: 0100 addi s0,sp,128 - c62: 04090003 lb zero,64(s2) - c66: 0100 addi s0,sp,128 - c68: 04090003 lb zero,64(s2) - c6c: 0100 addi s0,sp,128 - c6e: 04090003 lb zero,64(s2) - c72: 0100 addi s0,sp,128 - c74: 04090003 lb zero,64(s2) - c78: 0100 addi s0,sp,128 - c7a: 04090003 lb zero,64(s2) - c7e: 0100 addi s0,sp,128 - c80: 04090003 lb zero,64(s2) - c84: 0100 addi s0,sp,128 - c86: 0c090003 lb zero,192(s2) - c8a: 0100 addi s0,sp,128 - c8c: 04090003 lb zero,64(s2) - c90: 0100 addi s0,sp,128 - c92: 08090003 lb zero,128(s2) - c96: 0100 addi s0,sp,128 - c98: 04090003 lb zero,64(s2) - c9c: 0100 addi s0,sp,128 - c9e: 04090003 lb zero,64(s2) - ca2: 0100 addi s0,sp,128 - ca4: 04090003 lb zero,64(s2) - ca8: 0100 addi s0,sp,128 - caa: 04090003 lb zero,64(s2) - cae: 0100 addi s0,sp,128 - cb0: 04090003 lb zero,64(s2) - cb4: 0100 addi s0,sp,128 - cb6: 04090003 lb zero,64(s2) - cba: 0100 addi s0,sp,128 - cbc: 00090003 lb zero,0(s2) - cc0: 0100 addi s0,sp,128 - cc2: 00090103 lb sp,0(s2) - cc6: 0100 addi s0,sp,128 - cc8: 0705 addi a4,a4,1 - cca: 00092e03 lw t3,0(s2) - cce: 0100 addi s0,sp,128 - cd0: 0405 addi s0,s0,1 - cd2: 00090203 lb tp,0(s2) - cd6: 0100 addi s0,sp,128 - cd8: 1205 addi tp,tp,-31 - cda: 0306 slli t1,t1,0x1 - cdc: 0900 addi s0,sp,144 - cde: 0000 unimp - ce0: 0501 addi a0,a0,0 - ce2: 0604 addi s1,sp,768 - ce4: 04090103 lb sp,64(s2) - ce8: 0100 addi s0,sp,128 - cea: 00090103 lb sp,0(s2) - cee: 0100 addi s0,sp,128 - cf0: 0c05 addi s8,s8,1 - cf2: 0306 slli t1,t1,0x1 - cf4: 0900 addi s0,sp,144 - cf6: 0000 unimp - cf8: 0501 addi a0,a0,0 - cfa: 0301 addi t1,t1,0 - cfc: 01b4 addi a3,sp,200 - cfe: 0409 addi s0,s0,2 - d00: 0100 addi s0,sp,128 - d02: 0405 addi s0,s0,1 - d04: 097e8d03 lb s10,151(t4) # fffe7097 <__BSS_END__+0x7ffd031f> - d08: 0004 0x4 - d0a: 0601 addi a2,a2,0 - d0c: 14091503 lh a0,320(s2) - d10: 0100 addi s0,sp,128 - d12: 0705 addi a4,a4,1 - d14: 0306 slli t1,t1,0x1 - d16: 0900 addi s0,sp,144 - d18: 0000 unimp - d1a: 0501 addi a0,a0,0 - d1c: 0606 slli a2,a2,0x1 - d1e: 04090103 lb sp,64(s2) - d22: 0100 addi s0,sp,128 - d24: 0905 addi s2,s2,1 - d26: 0306 slli t1,t1,0x1 - d28: 0900 addi s0,sp,144 - d2a: 0000 unimp - d2c: 0501 addi a0,a0,0 - d2e: 0604 addi s1,sp,768 - d30: 08090203 lb tp,128(s2) - d34: 0100 addi s0,sp,128 - d36: 00090003 lb zero,0(s2) - d3a: 0100 addi s0,sp,128 - d3c: 00090003 lb zero,0(s2) - d40: 0100 addi s0,sp,128 - d42: 00090003 lb zero,0(s2) - d46: 0100 addi s0,sp,128 - d48: 00090003 lb zero,0(s2) - d4c: 0100 addi s0,sp,128 - d4e: 14090003 lb zero,320(s2) - d52: 0100 addi s0,sp,128 - d54: 18090203 lb tp,384(s2) - d58: 0100 addi s0,sp,128 - d5a: 0705 addi a4,a4,1 - d5c: 0306 slli t1,t1,0x1 - d5e: 0900 addi s0,sp,144 - d60: 0000 unimp - d62: 0501 addi a0,a0,0 - d64: 0608 addi a0,sp,768 - d66: 04090903 lb s2,64(s2) - d6a: 0100 addi s0,sp,128 - d6c: 0b05 addi s6,s6,1 - d6e: 0306 slli t1,t1,0x1 - d70: 0900 addi s0,sp,144 - d72: 0000 unimp - d74: 0501 addi a0,a0,0 - d76: 0608 addi a0,sp,768 - d78: 04090103 lb sp,64(s2) - d7c: 0100 addi s0,sp,128 - d7e: 0405 addi s0,s0,1 - d80: 00091203 lh tp,0(s2) - d84: 0100 addi s0,sp,128 - d86: 00090003 lb zero,0(s2) - d8a: 0100 addi s0,sp,128 - d8c: 00090003 lb zero,0(s2) - d90: 0100 addi s0,sp,128 - d92: 00090003 lb zero,0(s2) - d96: 0100 addi s0,sp,128 - d98: 04090003 lb zero,64(s2) - d9c: 0100 addi s0,sp,128 - d9e: 08090003 lb zero,128(s2) - da2: 0100 addi s0,sp,128 - da4: 08090003 lb zero,128(s2) - da8: 0100 addi s0,sp,128 - daa: 04090003 lb zero,64(s2) - dae: 0100 addi s0,sp,128 - db0: 0c090003 lb zero,192(s2) - db4: 0100 addi s0,sp,128 - db6: 00090003 lb zero,0(s2) - dba: 0100 addi s0,sp,128 - dbc: 04090003 lb zero,64(s2) - dc0: 0100 addi s0,sp,128 - dc2: 04090003 lb zero,64(s2) - dc6: 0100 addi s0,sp,128 - dc8: 04090003 lb zero,64(s2) - dcc: 0100 addi s0,sp,128 - dce: 04090003 lb zero,64(s2) - dd2: 0100 addi s0,sp,128 - dd4: 04090003 lb zero,64(s2) - dd8: 0100 addi s0,sp,128 - dda: 04090003 lb zero,64(s2) - dde: 0100 addi s0,sp,128 - de0: 04090003 lb zero,64(s2) - de4: 0100 addi s0,sp,128 - de6: 0c090003 lb zero,192(s2) - dea: 0100 addi s0,sp,128 - dec: 04090003 lb zero,64(s2) - df0: 0100 addi s0,sp,128 - df2: 08090003 lb zero,128(s2) - df6: 0100 addi s0,sp,128 - df8: 04090003 lb zero,64(s2) - dfc: 0100 addi s0,sp,128 - dfe: 04090003 lb zero,64(s2) - e02: 0100 addi s0,sp,128 - e04: 04090003 lb zero,64(s2) - e08: 0100 addi s0,sp,128 - e0a: 04090003 lb zero,64(s2) - e0e: 0100 addi s0,sp,128 - e10: 04090003 lb zero,64(s2) - e14: 0100 addi s0,sp,128 - e16: 04090003 lb zero,64(s2) - e1a: 0100 addi s0,sp,128 - e1c: 00090003 lb zero,0(s2) - e20: 0100 addi s0,sp,128 - e22: 0306 slli t1,t1,0x1 - e24: 0962 slli s2,s2,0x18 - e26: 0004 0x4 - e28: 0501 addi a0,a0,0 - e2a: 0608 addi a0,sp,768 - e2c: 14091203 lh tp,320(s2) - e30: 0100 addi s0,sp,128 - e32: 00090203 lb tp,0(s2) - e36: 0100 addi s0,sp,128 - e38: 0b05 addi s6,s6,1 - e3a: 0306 slli t1,t1,0x1 - e3c: 0900 addi s0,sp,144 - e3e: 0000 unimp - e40: 0501 addi a0,a0,0 - e42: 0608 addi a0,sp,768 - e44: 04090103 lb sp,64(s2) - e48: 0100 addi s0,sp,128 - e4a: 0b05 addi s6,s6,1 - e4c: 0306 slli t1,t1,0x1 - e4e: 0900 addi s0,sp,144 - e50: 0000 unimp - e52: 0501 addi a0,a0,0 - e54: 0608 addi a0,sp,768 - e56: 04090103 lb sp,64(s2) - e5a: 0100 addi s0,sp,128 - e5c: 0b05 addi s6,s6,1 - e5e: 0306 slli t1,t1,0x1 - e60: 0901 addi s2,s2,0 - e62: 0000 unimp - e64: 0501 addi a0,a0,0 - e66: 031e slli t1,t1,0x7 - e68: 097f 0x97f - e6a: 0004 0x4 - e6c: 0501 addi a0,a0,0 - e6e: 0308 addi a0,sp,384 - e70: 00040903 lb s2,0(s0) # 3003ef2 <_start-0x7cffc10e> - e74: 0501 addi a0,a0,0 - e76: 0311 addi t1,t1,4 - e78: 097d addi s2,s2,31 - e7a: 0008 0x8 - e7c: 0501 addi a0,a0,0 - e7e: 0900030b 0x900030b - e82: 0004 0x4 - e84: 0501 addi a0,a0,0 - e86: 0608 addi a0,sp,768 - e88: 04090103 lb sp,64(s2) - e8c: 0100 addi s0,sp,128 - e8e: 00090203 lb tp,0(s2) - e92: 0100 addi s0,sp,128 - e94: 00090003 lb zero,0(s2) - e98: 0100 addi s0,sp,128 - e9a: 00090003 lb zero,0(s2) - e9e: 0100 addi s0,sp,128 - ea0: 00090003 lb zero,0(s2) - ea4: 0100 addi s0,sp,128 - ea6: 00090003 lb zero,0(s2) - eaa: 0100 addi s0,sp,128 - eac: 08090003 lb zero,128(s2) - eb0: 0100 addi s0,sp,128 - eb2: 00090003 lb zero,0(s2) - eb6: 0100 addi s0,sp,128 - eb8: 08090003 lb zero,128(s2) - ebc: 0100 addi s0,sp,128 - ebe: 0c090003 lb zero,192(s2) - ec2: 0100 addi s0,sp,128 - ec4: 00090003 lb zero,0(s2) - ec8: 0100 addi s0,sp,128 - eca: 04090003 lb zero,64(s2) - ece: 0100 addi s0,sp,128 - ed0: 04090003 lb zero,64(s2) - ed4: 0100 addi s0,sp,128 - ed6: 04090003 lb zero,64(s2) - eda: 0100 addi s0,sp,128 - edc: 04090003 lb zero,64(s2) - ee0: 0100 addi s0,sp,128 - ee2: 04090003 lb zero,64(s2) - ee6: 0100 addi s0,sp,128 - ee8: 04090003 lb zero,64(s2) - eec: 0100 addi s0,sp,128 - eee: 04090003 lb zero,64(s2) - ef2: 0100 addi s0,sp,128 - ef4: 0c090003 lb zero,192(s2) - ef8: 0100 addi s0,sp,128 - efa: 08090003 lb zero,128(s2) - efe: 0100 addi s0,sp,128 - f00: 04090003 lb zero,64(s2) - f04: 0100 addi s0,sp,128 - f06: 04090003 lb zero,64(s2) - f0a: 0100 addi s0,sp,128 - f0c: 04090003 lb zero,64(s2) - f10: 0100 addi s0,sp,128 - f12: 04090003 lb zero,64(s2) - f16: 0100 addi s0,sp,128 - f18: 04090003 lb zero,64(s2) - f1c: 0100 addi s0,sp,128 - f1e: 04090003 lb zero,64(s2) - f22: 0100 addi s0,sp,128 - f24: 04090003 lb zero,64(s2) - f28: 0100 addi s0,sp,128 - f2a: 00090003 lb zero,0(s2) - f2e: 0100 addi s0,sp,128 - f30: 0705 addi a4,a4,1 - f32: 04091503 lh a0,64(s2) - f36: 0100 addi s0,sp,128 - f38: 0a05 addi s4,s4,1 - f3a: 0306 slli t1,t1,0x1 - f3c: 0900 addi s0,sp,144 - f3e: 0000 unimp - f40: 0501 addi a0,a0,0 - f42: 0604 addi s1,sp,768 - f44: 04091303 lh t1,64(s2) - f48: 0100 addi s0,sp,128 - f4a: 00090003 lb zero,0(s2) - f4e: 0100 addi s0,sp,128 - f50: 00090003 lb zero,0(s2) - f54: 0100 addi s0,sp,128 - f56: 00090003 lb zero,0(s2) - f5a: 0100 addi s0,sp,128 - f5c: 00090003 lb zero,0(s2) - f60: 0100 addi s0,sp,128 - f62: 14090003 lb zero,320(s2) - f66: 0100 addi s0,sp,128 - f68: 20090103 lb sp,512(s2) - f6c: 0100 addi s0,sp,128 - f6e: 0705 addi a4,a4,1 - f70: 0306 slli t1,t1,0x1 - f72: 0900 addi s0,sp,144 - f74: 0000 unimp - f76: 0501 addi a0,a0,0 - f78: 0608 addi a0,sp,768 - f7a: 04090a03 lb s4,64(s2) - f7e: 0100 addi s0,sp,128 - f80: 0b05 addi s6,s6,1 - f82: 0306 slli t1,t1,0x1 - f84: 0900 addi s0,sp,144 - f86: 0000 unimp - f88: 0501 addi a0,a0,0 - f8a: 0314 addi a3,sp,384 - f8c: 0900 addi s0,sp,144 - f8e: 0004 0x4 - f90: 0501 addi a0,a0,0 - f92: 0605 addi a2,a2,1 - f94: 04090203 lb tp,64(s2) - f98: 0100 addi s0,sp,128 - f9a: 00090103 lb sp,0(s2) - f9e: 0100 addi s0,sp,128 - fa0: 00090003 lb zero,0(s2) - fa4: 0100 addi s0,sp,128 - fa6: 00090003 lb zero,0(s2) - faa: 0100 addi s0,sp,128 - fac: 04090003 lb zero,64(s2) - fb0: 0100 addi s0,sp,128 - fb2: 0c090003 lb zero,192(s2) - fb6: 0100 addi s0,sp,128 - fb8: 0805 addi a6,a6,1 - fba: 00090503 lb a0,0(s2) - fbe: 0100 addi s0,sp,128 - fc0: 00090203 lb tp,0(s2) - fc4: 0100 addi s0,sp,128 - fc6: 0505 addi a0,a0,1 - fc8: 00090203 lb tp,0(s2) - fcc: 0100 addi s0,sp,128 - fce: 00090103 lb sp,0(s2) - fd2: 0100 addi s0,sp,128 - fd4: 00090103 lb sp,0(s2) - fd8: 0100 addi s0,sp,128 - fda: 0d05 addi s10,s10,1 - fdc: 0306 slli t1,t1,0x1 - fde: 0900 addi s0,sp,144 - fe0: 0000 unimp - fe2: 0501 addi a0,a0,0 - fe4: 0304 addi s1,sp,384 - fe6: 000c0967 jalr s2,s8 # 19000 <_start-0x7ffe7000> - fea: 0501 addi a0,a0,0 - fec: 0608 addi a0,sp,768 - fee: 14091e03 lh t3,320(s2) - ff2: 0100 addi s0,sp,128 - ff4: 00090303 lb t1,0(s2) - ff8: 0100 addi s0,sp,128 - ffa: 00090203 lb tp,0(s2) - ffe: 0100 addi s0,sp,128 - 1000: 1e05 addi t3,t3,-31 - 1002: 0306 slli t1,t1,0x1 - 1004: 0900 addi s0,sp,144 - 1006: 0000 unimp - 1008: 0501 addi a0,a0,0 - 100a: 0311 addi t1,t1,4 - 100c: 0900 addi s0,sp,144 - 100e: 0004 0x4 - 1010: 0501 addi a0,a0,0 - 1012: 0900030b 0x900030b - 1016: 0004 0x4 - 1018: 0501 addi a0,a0,0 - 101a: 0608 addi a0,sp,768 - 101c: 04090103 lb sp,64(s2) - 1020: 0100 addi s0,sp,128 - 1022: 0306 slli t1,t1,0x1 - 1024: 0905 addi s2,s2,1 - 1026: 0000 unimp - 1028: 0501 addi a0,a0,0 - 102a: 097c030b 0x97c030b - 102e: 0004 0x4 - 1030: 0501 addi a0,a0,0 - 1032: 0308 addi a0,sp,384 - 1034: 0904 addi s1,sp,144 - 1036: 0004 0x4 - 1038: 0501 addi a0,a0,0 - 103a: 0311 addi t1,t1,4 - 103c: 097d addi s2,s2,31 - 103e: 0004 0x4 - 1040: 0501 addi a0,a0,0 - 1042: 031e slli t1,t1,0x7 - 1044: 0900 addi s0,sp,144 - 1046: 0004 0x4 - 1048: 0501 addi a0,a0,0 - 104a: 0900030b 0x900030b - 104e: 0004 0x4 - 1050: 0501 addi a0,a0,0 - 1052: 0308 addi a0,sp,384 - 1054: 00040903 lb s2,0(s0) - 1058: 0501 addi a0,a0,0 - 105a: 097b030b 0x97b030b - 105e: 000c 0xc - 1060: 0501 addi a0,a0,0 - 1062: 0608 addi a0,sp,768 - 1064: 04090103 lb sp,64(s2) - 1068: 0100 addi s0,sp,128 - 106a: 00090103 lb sp,0(s2) - 106e: 0100 addi s0,sp,128 - 1070: 00090103 lb sp,0(s2) - 1074: 0100 addi s0,sp,128 - 1076: 0b05 addi s6,s6,1 - 1078: 0306 slli t1,t1,0x1 - 107a: 0900 addi s0,sp,144 - 107c: 0000 unimp - 107e: 0501 addi a0,a0,0 - 1080: 0608 addi a0,sp,768 - 1082: 04090203 lb tp,64(s2) - 1086: 0100 addi s0,sp,128 - 1088: 00090003 lb zero,0(s2) - 108c: 0100 addi s0,sp,128 - 108e: 00090003 lb zero,0(s2) - 1092: 0100 addi s0,sp,128 - 1094: 00090003 lb zero,0(s2) - 1098: 0100 addi s0,sp,128 - 109a: 00090003 lb zero,0(s2) - 109e: 0100 addi s0,sp,128 - 10a0: 00090003 lb zero,0(s2) - 10a4: 0100 addi s0,sp,128 - 10a6: 00090003 lb zero,0(s2) - 10aa: 0100 addi s0,sp,128 - 10ac: 04090003 lb zero,64(s2) - 10b0: 0100 addi s0,sp,128 - 10b2: 0c090003 lb zero,192(s2) - 10b6: 0100 addi s0,sp,128 - 10b8: 00090003 lb zero,0(s2) - 10bc: 0100 addi s0,sp,128 - 10be: 08090003 lb zero,128(s2) - 10c2: 0100 addi s0,sp,128 - 10c4: 08090003 lb zero,128(s2) - 10c8: 0100 addi s0,sp,128 - 10ca: 04090003 lb zero,64(s2) - 10ce: 0100 addi s0,sp,128 - 10d0: 04090003 lb zero,64(s2) - 10d4: 0100 addi s0,sp,128 - 10d6: 08090003 lb zero,128(s2) - 10da: 0100 addi s0,sp,128 - 10dc: 04090003 lb zero,64(s2) - 10e0: 0100 addi s0,sp,128 - 10e2: 04090003 lb zero,64(s2) - 10e6: 0100 addi s0,sp,128 - 10e8: 04090003 lb zero,64(s2) - 10ec: 0100 addi s0,sp,128 - 10ee: 08090003 lb zero,128(s2) - 10f2: 0100 addi s0,sp,128 - 10f4: 0c090003 lb zero,192(s2) - 10f8: 0100 addi s0,sp,128 - 10fa: 08090003 lb zero,128(s2) - 10fe: 0100 addi s0,sp,128 - 1100: 08090003 lb zero,128(s2) - 1104: 0100 addi s0,sp,128 - 1106: 04090003 lb zero,64(s2) - 110a: 0100 addi s0,sp,128 - 110c: 04090003 lb zero,64(s2) - 1110: 0100 addi s0,sp,128 - 1112: 08090003 lb zero,128(s2) - 1116: 0100 addi s0,sp,128 - 1118: 0306 slli t1,t1,0x1 - 111a: 0901 addi s2,s2,0 - 111c: 0004 0x4 - 111e: 0301 addi t1,t1,0 - 1120: 097f 0x97f - 1122: 0004 0x4 - 1124: 0301 addi t1,t1,0 - 1126: 0901 addi s2,s2,0 - 1128: 0004 0x4 - 112a: 0301 addi t1,t1,0 - 112c: 097f 0x97f - 112e: 0008 0x8 - 1130: 0601 addi a2,a2,0 - 1132: 04090003 lb zero,64(s2) - 1136: 0100 addi s0,sp,128 - 1138: 00090003 lb zero,0(s2) - 113c: 0100 addi s0,sp,128 - 113e: 00090103 lb sp,0(s2) - 1142: 0100 addi s0,sp,128 - 1144: 00090003 lb zero,0(s2) - 1148: 0100 addi s0,sp,128 - 114a: 00090003 lb zero,0(s2) - 114e: 0100 addi s0,sp,128 - 1150: 00090003 lb zero,0(s2) - 1154: 0100 addi s0,sp,128 - 1156: 00090003 lb zero,0(s2) - 115a: 0100 addi s0,sp,128 - 115c: 04090003 lb zero,64(s2) - 1160: 0100 addi s0,sp,128 - 1162: 08090003 lb zero,128(s2) - 1166: 0100 addi s0,sp,128 - 1168: 00090003 lb zero,0(s2) - 116c: 0100 addi s0,sp,128 - 116e: 04090003 lb zero,64(s2) - 1172: 0100 addi s0,sp,128 - 1174: 00090003 lb zero,0(s2) - 1178: 0100 addi s0,sp,128 - 117a: 04090003 lb zero,64(s2) - 117e: 0100 addi s0,sp,128 - 1180: 08090003 lb zero,128(s2) - 1184: 0100 addi s0,sp,128 - 1186: 04090003 lb zero,64(s2) - 118a: 0100 addi s0,sp,128 - 118c: 08090003 lb zero,128(s2) - 1190: 0100 addi s0,sp,128 - 1192: 04090003 lb zero,64(s2) - 1196: 0100 addi s0,sp,128 - 1198: 04090003 lb zero,64(s2) - 119c: 0100 addi s0,sp,128 - 119e: 08090003 lb zero,128(s2) - 11a2: 0100 addi s0,sp,128 - 11a4: 18090203 lb tp,384(s2) - 11a8: 0100 addi s0,sp,128 - 11aa: 0b05 addi s6,s6,1 - 11ac: 0306 slli t1,t1,0x1 - 11ae: 0900 addi s0,sp,144 - 11b0: 0000 unimp - 11b2: 0501 addi a0,a0,0 - 11b4: 0314 addi a3,sp,384 - 11b6: 0900 addi s0,sp,144 - 11b8: 0004 0x4 - 11ba: 0501 addi a0,a0,0 - 11bc: 0321 addi t1,t1,8 - 11be: 0900 addi s0,sp,144 - 11c0: 0004 0x4 - 11c2: 0501 addi a0,a0,0 - 11c4: 0605 addi a2,a2,1 - 11c6: 04090203 lb tp,64(s2) - 11ca: 0100 addi s0,sp,128 - 11cc: 00090103 lb sp,0(s2) - 11d0: 0100 addi s0,sp,128 - 11d2: 00090003 lb zero,0(s2) - 11d6: 0100 addi s0,sp,128 - 11d8: 00090003 lb zero,0(s2) - 11dc: 0100 addi s0,sp,128 - 11de: 04090003 lb zero,64(s2) - 11e2: 0100 addi s0,sp,128 - 11e4: 0c090003 lb zero,192(s2) - 11e8: 0100 addi s0,sp,128 - 11ea: 0805 addi a6,a6,1 - 11ec: 04090303 lb t1,64(s2) - 11f0: 0100 addi s0,sp,128 - 11f2: 00090303 lb t1,0(s2) - 11f6: 0100 addi s0,sp,128 - 11f8: 0505 addi a0,a0,1 - 11fa: 00090203 lb tp,0(s2) - 11fe: 0100 addi s0,sp,128 - 1200: 00090003 lb zero,0(s2) - 1204: 0100 addi s0,sp,128 - 1206: 00090003 lb zero,0(s2) - 120a: 0100 addi s0,sp,128 - 120c: 04090003 lb zero,64(s2) - 1210: 0100 addi s0,sp,128 - 1212: 0c090003 lb zero,192(s2) - 1216: 0100 addi s0,sp,128 - 1218: 00090103 lb sp,0(s2) - 121c: 0100 addi s0,sp,128 - 121e: 1405 addi s0,s0,-31 - 1220: 0306 slli t1,t1,0x1 - 1222: 0900 addi s0,sp,144 - 1224: 0000 unimp - 1226: 0501 addi a0,a0,0 - 1228: 0320 addi s0,sp,392 - 122a: 0900 addi s0,sp,144 - 122c: 0004 0x4 - 122e: 0501 addi a0,a0,0 - 1230: 0605 addi a2,a2,1 - 1232: 04090103 lb sp,64(s2) - 1236: 0100 addi s0,sp,128 - 1238: 00090103 lb sp,0(s2) - 123c: 0100 addi s0,sp,128 - 123e: 0d05 addi s10,s10,1 - 1240: 0306 slli t1,t1,0x1 - 1242: 0900 addi s0,sp,144 - 1244: 0000 unimp - 1246: 0501 addi a0,a0,0 - 1248: 06030603 lb a2,96(t1) - 124c: 0809 addi a6,a6,2 - 124e: 0100 addi s0,sp,128 - 1250: 00090103 lb sp,0(s2) - 1254: 0100 addi s0,sp,128 - 1256: 0900d803 lhu a6,144(ra) - 125a: 0000 unimp - 125c: 0501 addi a0,a0,0 - 125e: 060a slli a2,a2,0x2 - 1260: 00090003 lb zero,0(s2) - 1264: 0100 addi s0,sp,128 - 1266: 0409 addi s0,s0,2 - 1268: 0000 unimp - 126a: 0101 addi sp,sp,0 - 126c: 00000e2b 0xe2b - 1270: 00930003 lb zero,9(t1) - 1274: 0000 unimp - 1276: 0101 addi sp,sp,0 - 1278: 000d0efb 0xd0efb - 127c: 0101 addi sp,sp,0 - 127e: 0101 addi sp,sp,0 - 1280: 0000 unimp - 1282: 0100 addi s0,sp,128 - 1284: 0000 unimp - 1286: 2e01 jal 1596 <_start-0x7fffea6a> - 1288: 2f2e fld ft10,200(sp) - 128a: 2e2e fld ft8,200(sp) - 128c: 2f2e2e2f 0x2f2e2e2f - 1290: 2e2e fld ft8,200(sp) - 1292: 7369722f 0x7369722f - 1296: 672d7663 bgeu s10,s2,1902 <_start-0x7fffe6fe> - 129a: 6c2f6363 bltu t5,sp,1960 <_start-0x7fffe6a0> - 129e: 6269 lui tp,0x1a - 12a0: 2f636367 0x2f636367 - 12a4: 74666f73 csrrsi t5,0x746,12 - 12a8: 662d lui a2,0xb - 12aa: 0070 addi a2,sp,12 - 12ac: 2e2e fld ft8,200(sp) - 12ae: 2f2e2e2f 0x2f2e2e2f - 12b2: 2e2e fld ft8,200(sp) - 12b4: 2f2e2e2f 0x2f2e2e2f - 12b8: 6972 flw fs2,28(sp) - 12ba: 2d766373 csrrsi t1,0x2d7,12 - 12be: 2f636367 0x2f636367 - 12c2: 696c flw fa1,84(a0) - 12c4: 6762 flw fa4,24(sp) - 12c6: 2e2f6363 bltu t5,sp,15ac <_start-0x7fffea54> - 12ca: 2f2e fld ft10,200(sp) - 12cc: 6e69 lui t3,0x1a - 12ce: 64756c63 bltu a0,t2,1926 <_start-0x7fffe6da> - 12d2: 0065 c.nop 25 - 12d4: 6400 flw fs0,8(s0) - 12d6: 7669 lui a2,0xffffa - 12d8: 6664 flw fs1,76(a2) - 12da: 00632e33 slt t3,t1,t1 - 12de: 0001 nop - 12e0: 7300 flw fs0,32(a4) - 12e2: 2d74666f jal a2,47db8 <_start-0x7ffb8248> - 12e6: 7066 flw ft0,120(sp) - 12e8: 682e flw fa6,200(sp) - 12ea: 0100 addi s0,sp,128 - 12ec: 0000 unimp - 12ee: 6f64 flw fs1,92(a4) - 12f0: 6275 lui tp,0x1d - 12f2: 656c flw fa1,76(a0) - 12f4: 682e flw fa6,200(sp) - 12f6: 0100 addi s0,sp,128 - 12f8: 0000 unimp - 12fa: 6f6c flw fa1,92(a4) - 12fc: 676e flw fa4,216(sp) - 12fe: 6f6c flw fa1,92(a4) - 1300: 676e flw fa4,216(sp) - 1302: 682e flw fa6,200(sp) - 1304: 0200 addi s0,sp,256 - 1306: 0000 unimp - 1308: 0500 addi s0,sp,640 - 130a: 0001 nop - 130c: 0205 addi tp,tp,1 - 130e: 07e8 addi a0,sp,972 - 1310: 8001 c.srli64 s0 - 1312: 05012303 lw t1,80(sp) - 1316: 09010303 lb t1,144(sp) - 131a: 0000 unimp - 131c: 0301 addi t1,t1,0 - 131e: 0900 addi s0,sp,144 - 1320: 0000 unimp - 1322: 0501 addi a0,a0,0 - 1324: 030d addi t1,t1,3 - 1326: 0900 addi s0,sp,144 - 1328: 0000 unimp - 132a: 0501 addi a0,a0,0 - 132c: 09010303 lb t1,144(sp) - 1330: 0000 unimp - 1332: 0301 addi t1,t1,0 - 1334: 0900 addi s0,sp,144 - 1336: 0000 unimp - 1338: 0301 addi t1,t1,0 - 133a: 0900 addi s0,sp,144 - 133c: 0000 unimp - 133e: 0301 addi t1,t1,0 - 1340: 0900 addi s0,sp,144 - 1342: 0000 unimp - 1344: 0301 addi t1,t1,0 - 1346: 0901 addi s2,s2,0 - 1348: 0000 unimp - 134a: 0301 addi t1,t1,0 - 134c: 0900 addi s0,sp,144 - 134e: 0000 unimp - 1350: 0301 addi t1,t1,0 - 1352: 0900 addi s0,sp,144 - 1354: 0000 unimp - 1356: 0301 addi t1,t1,0 - 1358: 0900 addi s0,sp,144 - 135a: 0000 unimp - 135c: 0301 addi t1,t1,0 - 135e: 0901 addi s2,s2,0 - 1360: 0000 unimp - 1362: 0301 addi t1,t1,0 - 1364: 0900 addi s0,sp,144 - 1366: 0000 unimp - 1368: 0301 addi t1,t1,0 - 136a: 0900 addi s0,sp,144 - 136c: 0000 unimp - 136e: 0301 addi t1,t1,0 - 1370: 0900 addi s0,sp,144 - 1372: 0000 unimp - 1374: 0301 addi t1,t1,0 - 1376: 0901 addi s2,s2,0 - 1378: 0000 unimp - 137a: 0301 addi t1,t1,0 - 137c: 0902 c.slli64 s2 - 137e: 0000 unimp - 1380: 0301 addi t1,t1,0 - 1382: 0901 addi s2,s2,0 - 1384: 0000 unimp - 1386: 0301 addi t1,t1,0 - 1388: 0900 addi s0,sp,144 - 138a: 0000 unimp - 138c: 0301 addi t1,t1,0 - 138e: 0900 addi s0,sp,144 - 1390: 0000 unimp - 1392: 0301 addi t1,t1,0 - 1394: 0900 addi s0,sp,144 - 1396: 0000 unimp - 1398: 0301 addi t1,t1,0 - 139a: 0900 addi s0,sp,144 - 139c: 0000 unimp - 139e: 0301 addi t1,t1,0 - 13a0: 0900 addi s0,sp,144 - 13a2: 0000 unimp - 13a4: 0501 addi a0,a0,0 - 13a6: 0601 addi a2,a2,0 - 13a8: 00097803 0x97803 - 13ac: 0100 addi s0,sp,128 - 13ae: 0305 addi t1,t1,1 - 13b0: 04090803 lb a6,64(s2) - 13b4: 0100 addi s0,sp,128 - 13b6: 0105 addi sp,sp,1 - 13b8: 04097803 0x4097803 - 13bc: 0100 addi s0,sp,128 - 13be: 0305 addi t1,t1,1 - 13c0: 14090803 lb a6,320(s2) - 13c4: 0100 addi s0,sp,128 - 13c6: 0105 addi sp,sp,1 - 13c8: 04097803 0x4097803 - 13cc: 0100 addi s0,sp,128 - 13ce: 0305 addi t1,t1,1 - 13d0: 10090803 lb a6,256(s2) - 13d4: 0100 addi s0,sp,128 - 13d6: 0105 addi sp,sp,1 - 13d8: 04097803 0x4097803 - 13dc: 0100 addi s0,sp,128 - 13de: 0305 addi t1,t1,1 - 13e0: 0c090803 lb a6,192(s2) - 13e4: 0100 addi s0,sp,128 - 13e6: 0306 slli t1,t1,0x1 - 13e8: 0900 addi s0,sp,144 - 13ea: 0004 0x4 - 13ec: 0301 addi t1,t1,0 - 13ee: 0900 addi s0,sp,144 - 13f0: 0000 unimp - 13f2: 0301 addi t1,t1,0 - 13f4: 0900 addi s0,sp,144 - 13f6: 0004 0x4 - 13f8: 0301 addi t1,t1,0 - 13fa: 0900 addi s0,sp,144 - 13fc: 0000 unimp - 13fe: 0001 nop - 1400: 0402 c.slli64 s0 - 1402: 0301 addi t1,t1,0 - 1404: 0900 addi s0,sp,144 - 1406: 000c 0xc - 1408: 0001 nop - 140a: 0402 c.slli64 s0 - 140c: 0301 addi t1,t1,0 - 140e: 0900 addi s0,sp,144 - 1410: 0000 unimp - 1412: 0001 nop - 1414: 0402 c.slli64 s0 - 1416: 0301 addi t1,t1,0 - 1418: 0900 addi s0,sp,144 - 141a: 0000 unimp - 141c: 0001 nop - 141e: 0402 c.slli64 s0 - 1420: 0301 addi t1,t1,0 - 1422: 0900 addi s0,sp,144 - 1424: 0000 unimp - 1426: 0001 nop - 1428: 0402 c.slli64 s0 - 142a: 0301 addi t1,t1,0 - 142c: 0900 addi s0,sp,144 - 142e: 0014 0x14 - 1430: 0001 nop - 1432: 0402 c.slli64 s0 - 1434: 0301 addi t1,t1,0 - 1436: 0900 addi s0,sp,144 - 1438: 0004 0x4 - 143a: 0001 nop - 143c: 0402 c.slli64 s0 - 143e: 0301 addi t1,t1,0 - 1440: 0900 addi s0,sp,144 - 1442: 0000 unimp - 1444: 0001 nop - 1446: 0402 c.slli64 s0 - 1448: 0301 addi t1,t1,0 - 144a: 0900 addi s0,sp,144 - 144c: 0004 0x4 - 144e: 0001 nop - 1450: 0402 c.slli64 s0 - 1452: 0301 addi t1,t1,0 - 1454: 0900 addi s0,sp,144 - 1456: 0000 unimp - 1458: 0001 nop - 145a: 0402 c.slli64 s0 - 145c: 0325 addi t1,t1,9 - 145e: 0900 addi s0,sp,144 - 1460: 0000 unimp - 1462: 0001 nop - 1464: 0402 c.slli64 s0 - 1466: 0325 addi t1,t1,9 - 1468: 0900 addi s0,sp,144 - 146a: 0000 unimp - 146c: 0301 addi t1,t1,0 - 146e: 0901 addi s2,s2,0 - 1470: 0004 0x4 - 1472: 0301 addi t1,t1,0 - 1474: 0900 addi s0,sp,144 - 1476: 0000 unimp - 1478: 0301 addi t1,t1,0 - 147a: 0900 addi s0,sp,144 - 147c: 0000 unimp - 147e: 0301 addi t1,t1,0 - 1480: 0900 addi s0,sp,144 - 1482: 0000 unimp - 1484: 0301 addi t1,t1,0 - 1486: 0900 addi s0,sp,144 - 1488: 0000 unimp - 148a: 0301 addi t1,t1,0 - 148c: 0900 addi s0,sp,144 - 148e: 0000 unimp - 1490: 0301 addi t1,t1,0 - 1492: 0900 addi s0,sp,144 - 1494: 0010 0x10 - 1496: 0301 addi t1,t1,0 - 1498: 0900 addi s0,sp,144 - 149a: 0000 unimp - 149c: 0301 addi t1,t1,0 - 149e: 0900 addi s0,sp,144 - 14a0: 0004 0x4 - 14a2: 0301 addi t1,t1,0 - 14a4: 0900 addi s0,sp,144 - 14a6: 0000 unimp - 14a8: 0001 nop - 14aa: 0402 c.slli64 s0 - 14ac: 0301 addi t1,t1,0 - 14ae: 0900 addi s0,sp,144 - 14b0: 000c 0xc - 14b2: 0001 nop - 14b4: 0402 c.slli64 s0 - 14b6: 0301 addi t1,t1,0 - 14b8: 0900 addi s0,sp,144 - 14ba: 0000 unimp - 14bc: 0001 nop - 14be: 0402 c.slli64 s0 - 14c0: 0301 addi t1,t1,0 - 14c2: 0900 addi s0,sp,144 - 14c4: 0000 unimp - 14c6: 0001 nop - 14c8: 0402 c.slli64 s0 - 14ca: 0301 addi t1,t1,0 - 14cc: 0900 addi s0,sp,144 - 14ce: 0000 unimp - 14d0: 0001 nop - 14d2: 0402 c.slli64 s0 - 14d4: 0301 addi t1,t1,0 - 14d6: 0900 addi s0,sp,144 - 14d8: 0014 0x14 - 14da: 0001 nop - 14dc: 0402 c.slli64 s0 - 14de: 0301 addi t1,t1,0 - 14e0: 0900 addi s0,sp,144 - 14e2: 0004 0x4 - 14e4: 0001 nop - 14e6: 0402 c.slli64 s0 - 14e8: 0301 addi t1,t1,0 - 14ea: 0900 addi s0,sp,144 - 14ec: 0000 unimp - 14ee: 0001 nop - 14f0: 0402 c.slli64 s0 - 14f2: 0301 addi t1,t1,0 - 14f4: 0900 addi s0,sp,144 - 14f6: 0004 0x4 - 14f8: 0001 nop - 14fa: 0402 c.slli64 s0 - 14fc: 0301 addi t1,t1,0 - 14fe: 0900 addi s0,sp,144 - 1500: 0000 unimp - 1502: 0001 nop - 1504: 0402 c.slli64 s0 - 1506: 0325 addi t1,t1,9 - 1508: 0900 addi s0,sp,144 - 150a: 0000 unimp - 150c: 0001 nop - 150e: 0402 c.slli64 s0 - 1510: 0325 addi t1,t1,9 - 1512: 0900 addi s0,sp,144 - 1514: 0000 unimp - 1516: 0301 addi t1,t1,0 - 1518: 0901 addi s2,s2,0 - 151a: 0004 0x4 - 151c: 0301 addi t1,t1,0 - 151e: 0900 addi s0,sp,144 - 1520: 0000 unimp - 1522: 0301 addi t1,t1,0 - 1524: 0900 addi s0,sp,144 - 1526: 0014 0x14 - 1528: 0301 addi t1,t1,0 - 152a: 0900 addi s0,sp,144 - 152c: 0004 0x4 - 152e: 0001 nop - 1530: 0402 c.slli64 s0 - 1532: 0302 c.slli64 t1 - 1534: 097e slli s2,s2,0x1f - 1536: 001c 0x1c - 1538: 0001 nop - 153a: 0402 c.slli64 s0 - 153c: 030c addi a1,sp,384 - 153e: 0900 addi s0,sp,144 - 1540: 0008 0x8 - 1542: 0001 nop - 1544: 0402 c.slli64 s0 - 1546: 030c addi a1,sp,384 - 1548: 0900 addi s0,sp,144 - 154a: 0000 unimp - 154c: 0001 nop - 154e: 0402 c.slli64 s0 - 1550: 030c addi a1,sp,384 - 1552: 0900 addi s0,sp,144 - 1554: 0000 unimp - 1556: 0001 nop - 1558: 0402 c.slli64 s0 - 155a: 030c addi a1,sp,384 - 155c: 0900 addi s0,sp,144 - 155e: 0000 unimp - 1560: 0001 nop - 1562: 0402 c.slli64 s0 - 1564: 0310 addi a2,sp,384 - 1566: 0900 addi s0,sp,144 - 1568: 0004 0x4 - 156a: 0001 nop - 156c: 0402 c.slli64 s0 - 156e: 0310 addi a2,sp,384 - 1570: 0900 addi s0,sp,144 - 1572: 0000 unimp - 1574: 0001 nop - 1576: 0402 c.slli64 s0 - 1578: 0310 addi a2,sp,384 - 157a: 0900 addi s0,sp,144 - 157c: 0000 unimp - 157e: 0001 nop - 1580: 0402 c.slli64 s0 - 1582: 0310 addi a2,sp,384 - 1584: 0900 addi s0,sp,144 - 1586: 0000 unimp - 1588: 0001 nop - 158a: 0402 c.slli64 s0 - 158c: 0900031b 0x900031b - 1590: 0008 0x8 - 1592: 0001 nop - 1594: 0402 c.slli64 s0 - 1596: 0900031b 0x900031b - 159a: 0004 0x4 - 159c: 0001 nop - 159e: 0402 c.slli64 s0 - 15a0: 031c addi a5,sp,384 - 15a2: 0900 addi s0,sp,144 - 15a4: 0008 0x8 - 15a6: 0001 nop - 15a8: 0402 c.slli64 s0 - 15aa: 031c addi a5,sp,384 - 15ac: 0900 addi s0,sp,144 - 15ae: 0008 0x8 - 15b0: 0001 nop - 15b2: 0402 c.slli64 s0 - 15b4: 031c addi a5,sp,384 - 15b6: 0900 addi s0,sp,144 - 15b8: 0010 0x10 - 15ba: 0001 nop - 15bc: 0402 c.slli64 s0 - 15be: 031c addi a5,sp,384 - 15c0: 0900 addi s0,sp,144 - 15c2: 0004 0x4 - 15c4: 0001 nop - 15c6: 0402 c.slli64 s0 - 15c8: 0325 addi t1,t1,9 - 15ca: 0900 addi s0,sp,144 - 15cc: 0000 unimp - 15ce: 0001 nop - 15d0: 0402 c.slli64 s0 - 15d2: 0314 addi a3,sp,384 - 15d4: 0900 addi s0,sp,144 - 15d6: 000c 0xc - 15d8: 0001 nop - 15da: 0402 c.slli64 s0 - 15dc: 0314 addi a3,sp,384 - 15de: 0900 addi s0,sp,144 - 15e0: 0000 unimp - 15e2: 0001 nop - 15e4: 0402 c.slli64 s0 - 15e6: 0314 addi a3,sp,384 - 15e8: 0900 addi s0,sp,144 - 15ea: 0000 unimp - 15ec: 0001 nop - 15ee: 0402 c.slli64 s0 - 15f0: 0314 addi a3,sp,384 - 15f2: 0900 addi s0,sp,144 - 15f4: 0000 unimp - 15f6: 0001 nop - 15f8: 0402 c.slli64 s0 - 15fa: 0314 addi a3,sp,384 - 15fc: 0900 addi s0,sp,144 - 15fe: 0004 0x4 - 1600: 0001 nop - 1602: 0402 c.slli64 s0 - 1604: 031d addi t1,t1,7 - 1606: 0900 addi s0,sp,144 - 1608: 0008 0x8 - 160a: 0001 nop - 160c: 0402 c.slli64 s0 - 160e: 031d addi t1,t1,7 - 1610: 0900 addi s0,sp,144 - 1612: 0008 0x8 - 1614: 0001 nop - 1616: 0402 c.slli64 s0 - 1618: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 161c: 0008 0x8 - 161e: 0601 addi a2,a2,0 - 1620: 0c090003 lb zero,192(s2) - 1624: 0100 addi s0,sp,128 - 1626: 0200 addi s0,sp,256 - 1628: 0204 addi s1,sp,256 - 162a: 0306 slli t1,t1,0x1 - 162c: 0901 addi s2,s2,0 - 162e: 0030 addi a2,sp,8 - 1630: 0001 nop - 1632: 0402 c.slli64 s0 - 1634: 030c addi a1,sp,384 - 1636: 0900 addi s0,sp,144 - 1638: 0008 0x8 - 163a: 0001 nop - 163c: 0402 c.slli64 s0 - 163e: 030c addi a1,sp,384 - 1640: 0900 addi s0,sp,144 - 1642: 0000 unimp - 1644: 0001 nop - 1646: 0402 c.slli64 s0 - 1648: 030c addi a1,sp,384 - 164a: 0900 addi s0,sp,144 - 164c: 0000 unimp - 164e: 0001 nop - 1650: 0402 c.slli64 s0 - 1652: 030c addi a1,sp,384 - 1654: 0900 addi s0,sp,144 - 1656: 0000 unimp - 1658: 0001 nop - 165a: 0402 c.slli64 s0 - 165c: 0310 addi a2,sp,384 - 165e: 0900 addi s0,sp,144 - 1660: 0004 0x4 - 1662: 0001 nop - 1664: 0402 c.slli64 s0 - 1666: 0310 addi a2,sp,384 - 1668: 0900 addi s0,sp,144 - 166a: 0000 unimp - 166c: 0001 nop - 166e: 0402 c.slli64 s0 - 1670: 0310 addi a2,sp,384 - 1672: 0900 addi s0,sp,144 - 1674: 0000 unimp - 1676: 0001 nop - 1678: 0402 c.slli64 s0 - 167a: 0310 addi a2,sp,384 - 167c: 0900 addi s0,sp,144 - 167e: 0000 unimp - 1680: 0001 nop - 1682: 0402 c.slli64 s0 - 1684: 0900031b 0x900031b - 1688: 0008 0x8 - 168a: 0001 nop - 168c: 0402 c.slli64 s0 - 168e: 0900031b 0x900031b - 1692: 0004 0x4 - 1694: 0001 nop - 1696: 0402 c.slli64 s0 - 1698: 031c addi a5,sp,384 - 169a: 0900 addi s0,sp,144 - 169c: 0008 0x8 - 169e: 0001 nop - 16a0: 0402 c.slli64 s0 - 16a2: 031c addi a5,sp,384 - 16a4: 0900 addi s0,sp,144 - 16a6: 0008 0x8 - 16a8: 0001 nop - 16aa: 0402 c.slli64 s0 - 16ac: 031c addi a5,sp,384 - 16ae: 0900 addi s0,sp,144 - 16b0: 0010 0x10 - 16b2: 0001 nop - 16b4: 0402 c.slli64 s0 - 16b6: 031c addi a5,sp,384 - 16b8: 0900 addi s0,sp,144 - 16ba: 0004 0x4 - 16bc: 0001 nop - 16be: 0402 c.slli64 s0 - 16c0: 0325 addi t1,t1,9 - 16c2: 0900 addi s0,sp,144 - 16c4: 0000 unimp - 16c6: 0001 nop - 16c8: 0402 c.slli64 s0 - 16ca: 0314 addi a3,sp,384 - 16cc: 0900 addi s0,sp,144 - 16ce: 000c 0xc - 16d0: 0001 nop - 16d2: 0402 c.slli64 s0 - 16d4: 0314 addi a3,sp,384 - 16d6: 0900 addi s0,sp,144 - 16d8: 0000 unimp - 16da: 0001 nop - 16dc: 0402 c.slli64 s0 - 16de: 0314 addi a3,sp,384 - 16e0: 0900 addi s0,sp,144 - 16e2: 0000 unimp - 16e4: 0001 nop - 16e6: 0402 c.slli64 s0 - 16e8: 0314 addi a3,sp,384 - 16ea: 0900 addi s0,sp,144 - 16ec: 0000 unimp - 16ee: 0001 nop - 16f0: 0402 c.slli64 s0 - 16f2: 0314 addi a3,sp,384 - 16f4: 0900 addi s0,sp,144 - 16f6: 0008 0x8 - 16f8: 0001 nop - 16fa: 0402 c.slli64 s0 - 16fc: 031d addi t1,t1,7 - 16fe: 0900 addi s0,sp,144 - 1700: 0008 0x8 - 1702: 0001 nop - 1704: 0402 c.slli64 s0 - 1706: 031d addi t1,t1,7 - 1708: 0900 addi s0,sp,144 - 170a: 0008 0x8 - 170c: 0001 nop - 170e: 0402 c.slli64 s0 - 1710: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 1714: 0008 0x8 - 1716: 0601 addi a2,a2,0 - 1718: 08090003 lb zero,128(s2) - 171c: 0100 addi s0,sp,128 - 171e: 0200 addi s0,sp,256 - 1720: 0204 addi s1,sp,256 - 1722: 0306 slli t1,t1,0x1 - 1724: 0901 addi s2,s2,0 - 1726: 0030 addi a2,sp,8 - 1728: 0001 nop - 172a: 0402 c.slli64 s0 - 172c: 0302 c.slli64 t1 - 172e: 0900 addi s0,sp,144 - 1730: 0000 unimp - 1732: 0001 nop - 1734: 0402 c.slli64 s0 - 1736: 0302 c.slli64 t1 - 1738: 0900 addi s0,sp,144 - 173a: 0000 unimp - 173c: 0001 nop - 173e: 0402 c.slli64 s0 - 1740: 0302 c.slli64 t1 - 1742: 0900 addi s0,sp,144 - 1744: 0000 unimp - 1746: 0001 nop - 1748: 0402 c.slli64 s0 - 174a: 0302 c.slli64 t1 - 174c: 0900 addi s0,sp,144 - 174e: 0000 unimp - 1750: 0001 nop - 1752: 0402 c.slli64 s0 - 1754: 0302 c.slli64 t1 - 1756: 0900 addi s0,sp,144 - 1758: 0000 unimp - 175a: 0001 nop - 175c: 0402 c.slli64 s0 - 175e: 0302 c.slli64 t1 - 1760: 0900 addi s0,sp,144 - 1762: 0000 unimp - 1764: 0001 nop - 1766: 0402 c.slli64 s0 - 1768: 0302 c.slli64 t1 - 176a: 0900 addi s0,sp,144 - 176c: 0000 unimp - 176e: 0001 nop - 1770: 0402 c.slli64 s0 - 1772: 0302 c.slli64 t1 - 1774: 0900 addi s0,sp,144 - 1776: 0000 unimp - 1778: 0001 nop - 177a: 0402 c.slli64 s0 - 177c: 0302 c.slli64 t1 - 177e: 0900 addi s0,sp,144 - 1780: 0000 unimp - 1782: 0001 nop - 1784: 0402 c.slli64 s0 - 1786: 0003060b 0x3060b - 178a: 0409 addi s0,s0,2 - 178c: 0100 addi s0,sp,128 - 178e: 0200 addi s0,sp,256 - 1790: 0c04 addi s1,sp,528 - 1792: 04090003 lb zero,64(s2) - 1796: 0100 addi s0,sp,128 - 1798: 0200 addi s0,sp,256 - 179a: 0e04 addi s1,sp,784 - 179c: 0306 slli t1,t1,0x1 - 179e: 0900 addi s0,sp,144 - 17a0: 0004 0x4 - 17a2: 0001 nop - 17a4: 0402 c.slli64 s0 - 17a6: 030e slli t1,t1,0x3 - 17a8: 0900 addi s0,sp,144 - 17aa: 0000 unimp - 17ac: 0001 nop - 17ae: 0402 c.slli64 s0 - 17b0: 030e slli t1,t1,0x3 - 17b2: 0900 addi s0,sp,144 - 17b4: 0008 0x8 - 17b6: 0001 nop - 17b8: 0402 c.slli64 s0 - 17ba: 09000313 li t1,144 - 17be: 000c 0xc - 17c0: 0001 nop - 17c2: 0402 c.slli64 s0 - 17c4: 09000313 li t1,144 - 17c8: 0000 unimp - 17ca: 0001 nop - 17cc: 0402 c.slli64 s0 - 17ce: 09000313 li t1,144 - 17d2: 0000 unimp - 17d4: 0001 nop - 17d6: 0402 c.slli64 s0 - 17d8: 09000313 li t1,144 - 17dc: 000c 0xc - 17de: 0001 nop - 17e0: 0402 c.slli64 s0 - 17e2: 09000313 li t1,144 - 17e6: 0018 0x18 - 17e8: 0001 nop - 17ea: 0402 c.slli64 s0 - 17ec: 09000313 li t1,144 - 17f0: 0000 unimp - 17f2: 0001 nop - 17f4: 0402 c.slli64 s0 - 17f6: 09000313 li t1,144 - 17fa: 0000 unimp - 17fc: 0001 nop - 17fe: 0402 c.slli64 s0 - 1800: 09000313 li t1,144 - 1804: 0000 unimp - 1806: 0001 nop - 1808: 0402 c.slli64 s0 - 180a: 09000313 li t1,144 - 180e: 0000 unimp - 1810: 0001 nop - 1812: 0402 c.slli64 s0 - 1814: 09000313 li t1,144 - 1818: 0000 unimp - 181a: 0001 nop - 181c: 0402 c.slli64 s0 - 181e: 09000313 li t1,144 - 1822: 0000 unimp - 1824: 0001 nop - 1826: 0402 c.slli64 s0 - 1828: 09000313 li t1,144 - 182c: 0000 unimp - 182e: 0001 nop - 1830: 0402 c.slli64 s0 - 1832: 09000313 li t1,144 - 1836: 0000 unimp - 1838: 0001 nop - 183a: 0402 c.slli64 s0 - 183c: 09000313 li t1,144 - 1840: 000c 0xc - 1842: 0001 nop - 1844: 0402 c.slli64 s0 - 1846: 09000313 li t1,144 - 184a: 0008 0x8 - 184c: 0001 nop - 184e: 0402 c.slli64 s0 - 1850: 0316 slli t1,t1,0x5 - 1852: 0900 addi s0,sp,144 - 1854: 0004 0x4 - 1856: 0001 nop - 1858: 0402 c.slli64 s0 - 185a: 0316 slli t1,t1,0x5 - 185c: 0900 addi s0,sp,144 - 185e: 0008 0x8 - 1860: 0001 nop - 1862: 0402 c.slli64 s0 - 1864: 0318 addi a4,sp,384 - 1866: 0900 addi s0,sp,144 - 1868: 0004 0x4 - 186a: 0001 nop - 186c: 0402 c.slli64 s0 - 186e: 031a slli t1,t1,0x6 - 1870: 0900 addi s0,sp,144 - 1872: 0004 0x4 - 1874: 0001 nop - 1876: 0402 c.slli64 s0 - 1878: 031c addi a5,sp,384 - 187a: 0900 addi s0,sp,144 - 187c: 0008 0x8 - 187e: 0001 nop - 1880: 0402 c.slli64 s0 - 1882: 031c addi a5,sp,384 - 1884: 0900 addi s0,sp,144 - 1886: 0004 0x4 - 1888: 0001 nop - 188a: 0402 c.slli64 s0 - 188c: 031c addi a5,sp,384 - 188e: 0900 addi s0,sp,144 - 1890: 0000 unimp - 1892: 0001 nop - 1894: 0402 c.slli64 s0 - 1896: 031c addi a5,sp,384 - 1898: 0900 addi s0,sp,144 - 189a: 0004 0x4 - 189c: 0001 nop - 189e: 0402 c.slli64 s0 - 18a0: 031c addi a5,sp,384 - 18a2: 0900 addi s0,sp,144 - 18a4: 0014 0x14 - 18a6: 0001 nop - 18a8: 0402 c.slli64 s0 - 18aa: 031c addi a5,sp,384 - 18ac: 0900 addi s0,sp,144 - 18ae: 0008 0x8 - 18b0: 0001 nop - 18b2: 0402 c.slli64 s0 - 18b4: 031d addi t1,t1,7 - 18b6: 0900 addi s0,sp,144 - 18b8: 0004 0x4 - 18ba: 0001 nop - 18bc: 0402 c.slli64 s0 - 18be: 031d addi t1,t1,7 - 18c0: 0900 addi s0,sp,144 - 18c2: 0008 0x8 - 18c4: 0001 nop - 18c6: 0402 c.slli64 s0 - 18c8: 031f 0900 0004 0x40900031f - 18ce: 0001 nop - 18d0: 0402 c.slli64 s0 - 18d2: 0321 addi t1,t1,8 - 18d4: 0900 addi s0,sp,144 - 18d6: 0004 0x4 - 18d8: 0001 nop - 18da: 0402 c.slli64 s0 - 18dc: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 18e0: 0008 0x8 - 18e2: 0001 nop - 18e4: 0402 c.slli64 s0 - 18e6: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 18ea: 0010 0x10 - 18ec: 0001 nop - 18ee: 0402 c.slli64 s0 - 18f0: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 18f4: 0000 unimp - 18f6: 0001 nop - 18f8: 0402 c.slli64 s0 - 18fa: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 18fe: 0000 unimp - 1900: 0001 nop - 1902: 0402 c.slli64 s0 - 1904: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1908: 0000 unimp - 190a: 0001 nop - 190c: 0402 c.slli64 s0 - 190e: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1912: 0000 unimp - 1914: 0001 nop - 1916: 0402 c.slli64 s0 - 1918: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 191c: 0000 unimp - 191e: 0001 nop - 1920: 0402 c.slli64 s0 - 1922: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1926: 0000 unimp - 1928: 0001 nop - 192a: 0402 c.slli64 s0 - 192c: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1930: 0008 0x8 - 1932: 0001 nop - 1934: 0402 c.slli64 s0 - 1936: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 193a: 0000 unimp - 193c: 0001 nop - 193e: 0402 c.slli64 s0 - 1940: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1944: 0008 0x8 - 1946: 0001 nop - 1948: 0402 c.slli64 s0 - 194a: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 194e: 0008 0x8 - 1950: 0001 nop - 1952: 0402 c.slli64 s0 - 1954: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1958: 0000 unimp - 195a: 0001 nop - 195c: 0402 c.slli64 s0 - 195e: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1962: 0004 0x4 - 1964: 0001 nop - 1966: 0402 c.slli64 s0 - 1968: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 196c: 0008 0x8 - 196e: 0001 nop - 1970: 0402 c.slli64 s0 - 1972: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1976: 0004 0x4 - 1978: 0001 nop - 197a: 0402 c.slli64 s0 - 197c: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1980: 0008 0x8 - 1982: 0001 nop - 1984: 0402 c.slli64 s0 - 1986: 0324 addi s1,sp,392 - 1988: 0900 addi s0,sp,144 - 198a: 0004 0x4 - 198c: 0001 nop - 198e: 0402 c.slli64 s0 - 1990: 0326 slli t1,t1,0x9 - 1992: 0900 addi s0,sp,144 - 1994: 0004 0x4 - 1996: 0001 nop - 1998: 0402 c.slli64 s0 - 199a: 0326 slli t1,t1,0x9 - 199c: 0900 addi s0,sp,144 - 199e: 0008 0x8 - 19a0: 0001 nop - 19a2: 0402 c.slli64 s0 - 19a4: 0326 slli t1,t1,0x9 - 19a6: 0900 addi s0,sp,144 - 19a8: 0018 0x18 - 19aa: 0001 nop - 19ac: 0402 c.slli64 s0 - 19ae: 0326 slli t1,t1,0x9 - 19b0: 0900 addi s0,sp,144 - 19b2: 0000 unimp - 19b4: 0001 nop - 19b6: 0402 c.slli64 s0 - 19b8: 0628 addi a0,sp,776 - 19ba: 04090003 lb zero,64(s2) - 19be: 0100 addi s0,sp,128 - 19c0: 0200 addi s0,sp,256 - 19c2: 2904 fld fs1,16(a0) - 19c4: 08090003 lb zero,128(s2) - 19c8: 0100 addi s0,sp,128 - 19ca: 0200 addi s0,sp,256 - 19cc: 2b04 fld fs1,16(a4) - 19ce: 0306 slli t1,t1,0x1 - 19d0: 0900 addi s0,sp,144 - 19d2: 0004 0x4 - 19d4: 0001 nop - 19d6: 0402 c.slli64 s0 - 19d8: 0900032b 0x900032b - 19dc: 0014 0x14 - 19de: 0001 nop - 19e0: 0402 c.slli64 s0 - 19e2: 0900032b 0x900032b - 19e6: 0000 unimp - 19e8: 0001 nop - 19ea: 0402 c.slli64 s0 - 19ec: 0900032b 0x900032b - 19f0: 0000 unimp - 19f2: 0001 nop - 19f4: 0402 c.slli64 s0 - 19f6: 0900032b 0x900032b - 19fa: 0000 unimp - 19fc: 0001 nop - 19fe: 0402 c.slli64 s0 - 1a00: 0900032b 0x900032b - 1a04: 0000 unimp - 1a06: 0001 nop - 1a08: 0402 c.slli64 s0 - 1a0a: 0900032b 0x900032b - 1a0e: 0000 unimp - 1a10: 0001 nop - 1a12: 0402 c.slli64 s0 - 1a14: 062e slli a2,a2,0xb - 1a16: 04090003 lb zero,64(s2) - 1a1a: 0100 addi s0,sp,128 - 1a1c: 0200 addi s0,sp,256 - 1a1e: 2f04 fld fs1,24(a4) - 1a20: 04090003 lb zero,64(s2) - 1a24: 0100 addi s0,sp,128 - 1a26: 0200 addi s0,sp,256 - 1a28: 3104 fld fs1,32(a0) - 1a2a: 04090003 lb zero,64(s2) - 1a2e: 0100 addi s0,sp,128 - 1a30: 0200 addi s0,sp,256 - 1a32: 3404 fld fs1,40(s0) - 1a34: 04090003 lb zero,64(s2) - 1a38: 0100 addi s0,sp,128 - 1a3a: 0200 addi s0,sp,256 - 1a3c: 3504 fld fs1,40(a0) - 1a3e: 04090003 lb zero,64(s2) - 1a42: 0100 addi s0,sp,128 - 1a44: 0200 addi s0,sp,256 - 1a46: 3704 fld fs1,40(a4) - 1a48: 0306 slli t1,t1,0x1 - 1a4a: 0900 addi s0,sp,144 - 1a4c: 0004 0x4 - 1a4e: 0001 nop - 1a50: 0402 c.slli64 s0 - 1a52: 09000337 lui t1,0x9000 - 1a56: 0010 0x10 - 1a58: 0001 nop - 1a5a: 0402 c.slli64 s0 - 1a5c: 09000337 lui t1,0x9000 - 1a60: 0000 unimp - 1a62: 0001 nop - 1a64: 0402 c.slli64 s0 - 1a66: 09000337 lui t1,0x9000 - 1a6a: 0000 unimp - 1a6c: 0001 nop - 1a6e: 0402 c.slli64 s0 - 1a70: 09000337 lui t1,0x9000 - 1a74: 0000 unimp - 1a76: 0001 nop - 1a78: 0402 c.slli64 s0 - 1a7a: 09000337 lui t1,0x9000 - 1a7e: 0004 0x4 - 1a80: 0001 nop - 1a82: 0402 c.slli64 s0 - 1a84: 0339 addi t1,t1,14 - 1a86: 0900 addi s0,sp,144 - 1a88: 0000 unimp - 1a8a: 0001 nop - 1a8c: 0402 c.slli64 s0 - 1a8e: 0339 addi t1,t1,14 - 1a90: 0900 addi s0,sp,144 - 1a92: 0000 unimp - 1a94: 0001 nop - 1a96: 0402 c.slli64 s0 - 1a98: 0339 addi t1,t1,14 - 1a9a: 0900 addi s0,sp,144 - 1a9c: 0000 unimp - 1a9e: 0001 nop - 1aa0: 0402 c.slli64 s0 - 1aa2: 0339 addi t1,t1,14 - 1aa4: 0900 addi s0,sp,144 - 1aa6: 0004 0x4 - 1aa8: 0001 nop - 1aaa: 0402 c.slli64 s0 - 1aac: 0339 addi t1,t1,14 - 1aae: 0900 addi s0,sp,144 - 1ab0: 000c 0xc - 1ab2: 0001 nop - 1ab4: 0402 c.slli64 s0 - 1ab6: 0339 addi t1,t1,14 - 1ab8: 0900 addi s0,sp,144 - 1aba: 0000 unimp - 1abc: 0001 nop - 1abe: 0402 c.slli64 s0 - 1ac0: 0900033b 0x900033b - 1ac4: 0008 0x8 - 1ac6: 0001 nop - 1ac8: 0402 c.slli64 s0 - 1aca: 0900033b 0x900033b - 1ace: 0000 unimp - 1ad0: 0001 nop - 1ad2: 0402 c.slli64 s0 - 1ad4: 0900033b 0x900033b - 1ad8: 0000 unimp - 1ada: 0001 nop - 1adc: 0402 c.slli64 s0 - 1ade: 0900033b 0x900033b - 1ae2: 0000 unimp - 1ae4: 0001 nop - 1ae6: 0402 c.slli64 s0 - 1ae8: 0900033b 0x900033b - 1aec: 0000 unimp - 1aee: 0001 nop - 1af0: 0402 c.slli64 s0 - 1af2: 0900033b 0x900033b - 1af6: 0000 unimp - 1af8: 0001 nop - 1afa: 0402 c.slli64 s0 - 1afc: 0900033b 0x900033b - 1b00: 0000 unimp - 1b02: 0001 nop - 1b04: 0402 c.slli64 s0 - 1b06: 0900033b 0x900033b - 1b0a: 0004 0x4 - 1b0c: 0001 nop - 1b0e: 0402 c.slli64 s0 - 1b10: 0900033b 0x900033b - 1b14: 000c 0xc - 1b16: 0001 nop - 1b18: 0402 c.slli64 s0 - 1b1a: 0900033b 0x900033b - 1b1e: 0008 0x8 - 1b20: 0001 nop - 1b22: 0402 c.slli64 s0 - 1b24: 033d addi t1,t1,15 - 1b26: 0900 addi s0,sp,144 - 1b28: 0008 0x8 - 1b2a: 0001 nop - 1b2c: 0402 c.slli64 s0 - 1b2e: 033d addi t1,t1,15 - 1b30: 0900 addi s0,sp,144 - 1b32: 0008 0x8 - 1b34: 0001 nop - 1b36: 0402 c.slli64 s0 - 1b38: 0900033f 00010004 0x100040900033f - 1b40: 0402 c.slli64 s0 - 1b42: 0341 addi t1,t1,16 - 1b44: 0900 addi s0,sp,144 - 1b46: 0004 0x4 - 1b48: 0001 nop - 1b4a: 0402 c.slli64 s0 - 1b4c: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1b50: 0008 0x8 - 1b52: 0001 nop - 1b54: 0402 c.slli64 s0 - 1b56: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1b5a: 0004 0x4 - 1b5c: 0001 nop - 1b5e: 0402 c.slli64 s0 - 1b60: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1b64: 0000 unimp - 1b66: 0001 nop - 1b68: 0402 c.slli64 s0 - 1b6a: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1b6e: 0004 0x4 - 1b70: 0001 nop - 1b72: 0402 c.slli64 s0 - 1b74: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1b78: 0014 0x14 - 1b7a: 0001 nop - 1b7c: 0402 c.slli64 s0 - 1b7e: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1b82: 0008 0x8 - 1b84: 0001 nop - 1b86: 0402 c.slli64 s0 - 1b88: 0344 addi s1,sp,388 - 1b8a: 0900 addi s0,sp,144 - 1b8c: 0004 0x4 - 1b8e: 0001 nop - 1b90: 0402 c.slli64 s0 - 1b92: 0344 addi s1,sp,388 - 1b94: 0900 addi s0,sp,144 - 1b96: 0008 0x8 - 1b98: 0001 nop - 1b9a: 0402 c.slli64 s0 - 1b9c: 0346 slli t1,t1,0x11 - 1b9e: 0900 addi s0,sp,144 - 1ba0: 0004 0x4 - 1ba2: 0001 nop - 1ba4: 0402 c.slli64 s0 - 1ba6: 0348 addi a0,sp,388 - 1ba8: 0900 addi s0,sp,144 - 1baa: 0004 0x4 - 1bac: 0001 nop - 1bae: 0402 c.slli64 s0 - 1bb0: 034a slli t1,t1,0x12 - 1bb2: 0900 addi s0,sp,144 - 1bb4: 0008 0x8 - 1bb6: 0001 nop - 1bb8: 0402 c.slli64 s0 - 1bba: 034a slli t1,t1,0x12 - 1bbc: 0900 addi s0,sp,144 - 1bbe: 0014 0x14 - 1bc0: 0001 nop - 1bc2: 0402 c.slli64 s0 - 1bc4: 034a slli t1,t1,0x12 - 1bc6: 0900 addi s0,sp,144 - 1bc8: 0000 unimp - 1bca: 0001 nop - 1bcc: 0402 c.slli64 s0 - 1bce: 034a slli t1,t1,0x12 - 1bd0: 0900 addi s0,sp,144 - 1bd2: 0000 unimp - 1bd4: 0001 nop - 1bd6: 0402 c.slli64 s0 - 1bd8: 034a slli t1,t1,0x12 - 1bda: 0900 addi s0,sp,144 - 1bdc: 0000 unimp - 1bde: 0001 nop - 1be0: 0402 c.slli64 s0 - 1be2: 034a slli t1,t1,0x12 - 1be4: 0900 addi s0,sp,144 - 1be6: 0000 unimp - 1be8: 0001 nop - 1bea: 0402 c.slli64 s0 - 1bec: 034a slli t1,t1,0x12 - 1bee: 0900 addi s0,sp,144 - 1bf0: 0000 unimp - 1bf2: 0001 nop - 1bf4: 0402 c.slli64 s0 - 1bf6: 034a slli t1,t1,0x12 - 1bf8: 0900 addi s0,sp,144 - 1bfa: 0000 unimp - 1bfc: 0001 nop - 1bfe: 0402 c.slli64 s0 - 1c00: 034a slli t1,t1,0x12 - 1c02: 0900 addi s0,sp,144 - 1c04: 0004 0x4 - 1c06: 0001 nop - 1c08: 0402 c.slli64 s0 - 1c0a: 034a slli t1,t1,0x12 - 1c0c: 0900 addi s0,sp,144 - 1c0e: 0000 unimp - 1c10: 0001 nop - 1c12: 0402 c.slli64 s0 - 1c14: 034a slli t1,t1,0x12 - 1c16: 0900 addi s0,sp,144 - 1c18: 0000 unimp - 1c1a: 0001 nop - 1c1c: 0402 c.slli64 s0 - 1c1e: 034a slli t1,t1,0x12 - 1c20: 0900 addi s0,sp,144 - 1c22: 0004 0x4 - 1c24: 0001 nop - 1c26: 0402 c.slli64 s0 - 1c28: 034a slli t1,t1,0x12 - 1c2a: 0900 addi s0,sp,144 - 1c2c: 0000 unimp - 1c2e: 0001 nop - 1c30: 0402 c.slli64 s0 - 1c32: 034a slli t1,t1,0x12 - 1c34: 0900 addi s0,sp,144 - 1c36: 0004 0x4 - 1c38: 0001 nop - 1c3a: 0402 c.slli64 s0 - 1c3c: 034a slli t1,t1,0x12 - 1c3e: 0900 addi s0,sp,144 - 1c40: 0004 0x4 - 1c42: 0001 nop - 1c44: 0402 c.slli64 s0 - 1c46: 034a slli t1,t1,0x12 - 1c48: 0900 addi s0,sp,144 - 1c4a: 000c 0xc - 1c4c: 0001 nop - 1c4e: 0402 c.slli64 s0 - 1c50: 034a slli t1,t1,0x12 - 1c52: 0900 addi s0,sp,144 - 1c54: 0004 0x4 - 1c56: 0001 nop - 1c58: 0402 c.slli64 s0 - 1c5a: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne - 1c5e: 0004 0x4 - 1c60: 0001 nop - 1c62: 0402 c.slli64 s0 - 1c64: 034d addi t1,t1,19 - 1c66: 0900 addi s0,sp,144 - 1c68: 0008 0x8 - 1c6a: 0001 nop - 1c6c: 0402 c.slli64 s0 - 1c6e: 034d addi t1,t1,19 - 1c70: 0900 addi s0,sp,144 - 1c72: 0008 0x8 - 1c74: 0001 nop - 1c76: 0402 c.slli64 s0 - 1c78: 034d addi t1,t1,19 - 1c7a: 0900 addi s0,sp,144 - 1c7c: 0018 0x18 - 1c7e: 0001 nop - 1c80: 0402 c.slli64 s0 - 1c82: 034d addi t1,t1,19 - 1c84: 0900 addi s0,sp,144 - 1c86: 0000 unimp - 1c88: 0001 nop - 1c8a: 0402 c.slli64 s0 - 1c8c: 0003064f fnmadd.s fa2,ft6,ft0,ft0,rne - 1c90: 0409 addi s0,s0,2 - 1c92: 0100 addi s0,sp,128 - 1c94: 0200 addi s0,sp,256 - 1c96: 5004 lw s1,32(s0) - 1c98: 04090003 lb zero,64(s2) - 1c9c: 0100 addi s0,sp,128 - 1c9e: 0200 addi s0,sp,256 - 1ca0: 5204 lw s1,32(a2) - 1ca2: 0306 slli t1,t1,0x1 - 1ca4: 0900 addi s0,sp,144 - 1ca6: 0008 0x8 - 1ca8: 0001 nop - 1caa: 0402 c.slli64 s0 - 1cac: 0352 slli t1,t1,0x14 - 1cae: 0900 addi s0,sp,144 - 1cb0: 0008 0x8 - 1cb2: 0001 nop - 1cb4: 0402 c.slli64 s0 - 1cb6: 0352 slli t1,t1,0x14 - 1cb8: 0900 addi s0,sp,144 - 1cba: 0000 unimp - 1cbc: 0001 nop - 1cbe: 0402 c.slli64 s0 - 1cc0: 0352 slli t1,t1,0x14 - 1cc2: 0900 addi s0,sp,144 - 1cc4: 0000 unimp - 1cc6: 0001 nop - 1cc8: 0402 c.slli64 s0 - 1cca: 0352 slli t1,t1,0x14 - 1ccc: 0900 addi s0,sp,144 - 1cce: 0000 unimp - 1cd0: 0001 nop - 1cd2: 0402 c.slli64 s0 - 1cd4: 0352 slli t1,t1,0x14 - 1cd6: 0900 addi s0,sp,144 - 1cd8: 0000 unimp - 1cda: 0001 nop - 1cdc: 0402 c.slli64 s0 - 1cde: 0352 slli t1,t1,0x14 - 1ce0: 0900 addi s0,sp,144 - 1ce2: 0000 unimp - 1ce4: 0001 nop - 1ce6: 0402 c.slli64 s0 - 1ce8: 0658 addi a4,sp,772 - 1cea: 04090003 lb zero,64(s2) - 1cee: 0100 addi s0,sp,128 - 1cf0: 0200 addi s0,sp,256 - 1cf2: 5b04 lw s1,48(a4) - 1cf4: 04090003 lb zero,64(s2) - 1cf8: 0100 addi s0,sp,128 - 1cfa: 0200 addi s0,sp,256 - 1cfc: 5c04 lw s1,56(s0) - 1cfe: 04090003 lb zero,64(s2) - 1d02: 0100 addi s0,sp,128 - 1d04: 0200 addi s0,sp,256 - 1d06: 5e04 lw s1,56(a2) - 1d08: 0306 slli t1,t1,0x1 - 1d0a: 0900 addi s0,sp,144 - 1d0c: 0004 0x4 - 1d0e: 0001 nop - 1d10: 0402 c.slli64 s0 - 1d12: 035e slli t1,t1,0x17 - 1d14: 0900 addi s0,sp,144 - 1d16: 0010 0x10 - 1d18: 0001 nop - 1d1a: 0402 c.slli64 s0 - 1d1c: 035e slli t1,t1,0x17 - 1d1e: 0900 addi s0,sp,144 - 1d20: 0000 unimp - 1d22: 0001 nop - 1d24: 0402 c.slli64 s0 - 1d26: 035e slli t1,t1,0x17 - 1d28: 0900 addi s0,sp,144 - 1d2a: 0000 unimp - 1d2c: 0001 nop - 1d2e: 0402 c.slli64 s0 - 1d30: 035e slli t1,t1,0x17 - 1d32: 0900 addi s0,sp,144 - 1d34: 0000 unimp - 1d36: 0001 nop - 1d38: 0402 c.slli64 s0 - 1d3a: 035e slli t1,t1,0x17 - 1d3c: 0900 addi s0,sp,144 - 1d3e: 0004 0x4 - 1d40: 0001 nop - 1d42: 0402 c.slli64 s0 - 1d44: 0360 addi s0,sp,396 - 1d46: 0900 addi s0,sp,144 - 1d48: 0004 0x4 - 1d4a: 0001 nop - 1d4c: 0402 c.slli64 s0 - 1d4e: 0662 slli a2,a2,0x18 - 1d50: 04090003 lb zero,64(s2) - 1d54: 0100 addi s0,sp,128 - 1d56: 0200 addi s0,sp,256 - 1d58: 6304 flw fs1,0(a4) - 1d5a: 0306 slli t1,t1,0x1 - 1d5c: 0900 addi s0,sp,144 - 1d5e: 0004 0x4 - 1d60: 0001 nop - 1d62: 0402 c.slli64 s0 - 1d64: 0302 c.slli64 t1 - 1d66: 0901 addi s2,s2,0 - 1d68: 0004 0x4 - 1d6a: 0001 nop - 1d6c: 0402 c.slli64 s0 - 1d6e: 0302 c.slli64 t1 - 1d70: 0900 addi s0,sp,144 - 1d72: 0004 0x4 - 1d74: 0001 nop - 1d76: 0402 c.slli64 s0 - 1d78: 0306 slli t1,t1,0x1 - 1d7a: 0900 addi s0,sp,144 - 1d7c: 0004 0x4 - 1d7e: 0001 nop - 1d80: 0402 c.slli64 s0 - 1d82: 0306 slli t1,t1,0x1 - 1d84: 0900 addi s0,sp,144 - 1d86: 0000 unimp - 1d88: 0001 nop - 1d8a: 0402 c.slli64 s0 - 1d8c: 0308 addi a0,sp,384 - 1d8e: 0900 addi s0,sp,144 - 1d90: 0008 0x8 - 1d92: 0001 nop - 1d94: 0402 c.slli64 s0 - 1d96: 0308 addi a0,sp,384 - 1d98: 0900 addi s0,sp,144 - 1d9a: 0000 unimp - 1d9c: 0001 nop - 1d9e: 0402 c.slli64 s0 - 1da0: 0308 addi a0,sp,384 - 1da2: 0900 addi s0,sp,144 - 1da4: 0000 unimp - 1da6: 0001 nop - 1da8: 0402 c.slli64 s0 - 1daa: 0308 addi a0,sp,384 - 1dac: 0900 addi s0,sp,144 - 1dae: 0000 unimp - 1db0: 0001 nop - 1db2: 0402 c.slli64 s0 - 1db4: 030a slli t1,t1,0x2 - 1db6: 0900 addi s0,sp,144 - 1db8: 000c 0xc - 1dba: 0001 nop - 1dbc: 0402 c.slli64 s0 - 1dbe: 030a slli t1,t1,0x2 - 1dc0: 0900 addi s0,sp,144 - 1dc2: 0000 unimp - 1dc4: 0001 nop - 1dc6: 0402 c.slli64 s0 - 1dc8: 030a slli t1,t1,0x2 - 1dca: 0900 addi s0,sp,144 - 1dcc: 0000 unimp - 1dce: 0001 nop - 1dd0: 0402 c.slli64 s0 - 1dd2: 030a slli t1,t1,0x2 - 1dd4: 0900 addi s0,sp,144 - 1dd6: 0004 0x4 - 1dd8: 0001 nop - 1dda: 0402 c.slli64 s0 - 1ddc: 030a slli t1,t1,0x2 - 1dde: 0900 addi s0,sp,144 - 1de0: 0008 0x8 - 1de2: 0001 nop - 1de4: 0402 c.slli64 s0 - 1de6: 0309 addi t1,t1,2 - 1de8: 0900 addi s0,sp,144 - 1dea: 0004 0x4 - 1dec: 0001 nop - 1dee: 0402 c.slli64 s0 - 1df0: 0318 addi a4,sp,384 - 1df2: 0900 addi s0,sp,144 - 1df4: 0008 0x8 - 1df6: 0001 nop - 1df8: 0402 c.slli64 s0 - 1dfa: 0318 addi a4,sp,384 - 1dfc: 0900 addi s0,sp,144 - 1dfe: 000c 0xc - 1e00: 0001 nop - 1e02: 0402 c.slli64 s0 - 1e04: 031a slli t1,t1,0x6 - 1e06: 0900 addi s0,sp,144 - 1e08: 0004 0x4 - 1e0a: 0001 nop - 1e0c: 0402 c.slli64 s0 - 1e0e: 031a slli t1,t1,0x6 - 1e10: 0900 addi s0,sp,144 - 1e12: 0000 unimp - 1e14: 0001 nop - 1e16: 0402 c.slli64 s0 - 1e18: 031a slli t1,t1,0x6 - 1e1a: 0900 addi s0,sp,144 - 1e1c: 0000 unimp - 1e1e: 0001 nop - 1e20: 0402 c.slli64 s0 - 1e22: 031a slli t1,t1,0x6 - 1e24: 0900 addi s0,sp,144 - 1e26: 0000 unimp - 1e28: 0601 addi a2,a2,0 - 1e2a: 08090003 lb zero,128(s2) - 1e2e: 0100 addi s0,sp,128 - 1e30: 0200 addi s0,sp,256 - 1e32: 7804 flw fs1,48(s0) - 1e34: 0306 slli t1,t1,0x1 - 1e36: 0900 addi s0,sp,144 - 1e38: 0010 0x10 - 1e3a: 0001 nop - 1e3c: 0402 c.slli64 s0 - 1e3e: 0378 addi a4,sp,396 - 1e40: 0900 addi s0,sp,144 - 1e42: 0000 unimp - 1e44: 0001 nop - 1e46: 0402 c.slli64 s0 - 1e48: 0378 addi a4,sp,396 - 1e4a: 0900 addi s0,sp,144 - 1e4c: 0000 unimp - 1e4e: 0001 nop - 1e50: 0402 c.slli64 s0 - 1e52: 0378 addi a4,sp,396 - 1e54: 0900 addi s0,sp,144 - 1e56: 0000 unimp - 1e58: 0001 nop - 1e5a: 0402 c.slli64 s0 - 1e5c: 0378 addi a4,sp,396 - 1e5e: 0900 addi s0,sp,144 - 1e60: 0000 unimp - 1e62: 0001 nop - 1e64: 0402 c.slli64 s0 - 1e66: 0378 addi a4,sp,396 - 1e68: 0900 addi s0,sp,144 - 1e6a: 0000 unimp - 1e6c: 0001 nop - 1e6e: 0402 c.slli64 s0 - 1e70: 0378 addi a4,sp,396 - 1e72: 0900 addi s0,sp,144 - 1e74: 0000 unimp - 1e76: 0501 addi a0,a0,0 - 1e78: 0001 nop - 1e7a: 0402 c.slli64 s0 - 1e7c: 0678 addi a4,sp,780 - 1e7e: 0c090403 lb s0,192(s2) - 1e82: 0100 addi s0,sp,128 - 1e84: 0305 addi t1,t1,1 - 1e86: 0200 addi s0,sp,256 - 1e88: 7804 flw fs1,48(s0) - 1e8a: 08097c03 0x8097c03 - 1e8e: 0100 addi s0,sp,128 - 1e90: 0200 addi s0,sp,256 - 1e92: 7804 flw fs1,48(s0) - 1e94: 0306 slli t1,t1,0x1 - 1e96: 0901 addi s2,s2,0 - 1e98: 0010 0x10 - 1e9a: 0001 nop - 1e9c: 0402 c.slli64 s0 - 1e9e: 0378 addi a4,sp,396 - 1ea0: 0900 addi s0,sp,144 - 1ea2: 0000 unimp - 1ea4: 0001 nop - 1ea6: 0402 c.slli64 s0 - 1ea8: 0378 addi a4,sp,396 - 1eaa: 0902 c.slli64 s2 - 1eac: 0000 unimp - 1eae: 0501 addi a0,a0,0 - 1eb0: 0001 nop - 1eb2: 0402 c.slli64 s0 - 1eb4: 0678 addi a4,sp,780 - 1eb6: 00090103 lb sp,0(s2) - 1eba: 0100 addi s0,sp,128 - 1ebc: 0305 addi t1,t1,1 - 1ebe: 0200 addi s0,sp,256 - 1ec0: 0f04 addi s1,sp,912 - 1ec2: 0306 slli t1,t1,0x1 - 1ec4: 002c097b 0x2c097b - 1ec8: 0001 nop - 1eca: 0402 c.slli64 s0 - 1ecc: 0900030f 0x900030f - 1ed0: 0004 0x4 - 1ed2: 0001 nop - 1ed4: 0402 c.slli64 s0 - 1ed6: 0900030f 0x900030f - 1eda: 0000 unimp - 1edc: 0001 nop - 1ede: 0402 c.slli64 s0 - 1ee0: 0900030f 0x900030f - 1ee4: 0000 unimp - 1ee6: 0001 nop - 1ee8: 0402 c.slli64 s0 - 1eea: 0608 addi a0,sp,768 - 1eec: 08097e03 0x8097e03 - 1ef0: 0100 addi s0,sp,128 - 1ef2: 0200 addi s0,sp,256 - 1ef4: 0804 addi s1,sp,16 - 1ef6: 0306 slli t1,t1,0x1 - 1ef8: 0902 c.slli64 s2 - 1efa: 0004 0x4 - 1efc: 0001 nop - 1efe: 0402 c.slli64 s0 - 1f00: 0308 addi a0,sp,384 - 1f02: 0900 addi s0,sp,144 - 1f04: 0000 unimp - 1f06: 0001 nop - 1f08: 0402 c.slli64 s0 - 1f0a: 0308 addi a0,sp,384 - 1f0c: 0900 addi s0,sp,144 - 1f0e: 0000 unimp - 1f10: 0001 nop - 1f12: 0402 c.slli64 s0 - 1f14: 0308 addi a0,sp,384 - 1f16: 0900 addi s0,sp,144 - 1f18: 0000 unimp - 1f1a: 0301 addi t1,t1,0 - 1f1c: 0901 addi s2,s2,0 - 1f1e: 000c 0xc - 1f20: 0301 addi t1,t1,0 - 1f22: 0900 addi s0,sp,144 - 1f24: 0000 unimp - 1f26: 0301 addi t1,t1,0 - 1f28: 0900 addi s0,sp,144 - 1f2a: 0000 unimp - 1f2c: 0001 nop - 1f2e: 0402 c.slli64 s0 - 1f30: 0605 addi a2,a2,1 - 1f32: 24097e03 0x24097e03 - 1f36: 0100 addi s0,sp,128 - 1f38: 0200 addi s0,sp,256 - 1f3a: 0504 addi s1,sp,640 - 1f3c: 0306 slli t1,t1,0x1 - 1f3e: 0901 addi s2,s2,0 - 1f40: 0004 0x4 - 1f42: 0001 nop - 1f44: 0402 c.slli64 s0 - 1f46: 0305 addi t1,t1,1 - 1f48: 0900 addi s0,sp,144 - 1f4a: 0000 unimp - 1f4c: 0001 nop - 1f4e: 0402 c.slli64 s0 - 1f50: 0305 addi t1,t1,1 - 1f52: 0900 addi s0,sp,144 - 1f54: 0000 unimp - 1f56: 0001 nop - 1f58: 0402 c.slli64 s0 - 1f5a: 0305 addi t1,t1,1 - 1f5c: 0900 addi s0,sp,144 - 1f5e: 0000 unimp - 1f60: 0601 addi a2,a2,0 - 1f62: 04090003 lb zero,64(s2) - 1f66: 0100 addi s0,sp,128 - 1f68: 0200 addi s0,sp,256 - 1f6a: 3b04 fld fs1,48(a4) - 1f6c: 0306 slli t1,t1,0x1 - 1f6e: 0901 addi s2,s2,0 - 1f70: 0014 0x14 - 1f72: 0001 nop - 1f74: 0402 c.slli64 s0 - 1f76: 0900033b 0x900033b - 1f7a: 0000 unimp - 1f7c: 0001 nop - 1f7e: 0402 c.slli64 s0 - 1f80: 0900033b 0x900033b - 1f84: 0000 unimp - 1f86: 0001 nop - 1f88: 0402 c.slli64 s0 - 1f8a: 0900033b 0x900033b - 1f8e: 0008 0x8 - 1f90: 0001 nop - 1f92: 0402 c.slli64 s0 - 1f94: 033c addi a5,sp,392 - 1f96: 0900 addi s0,sp,144 - 1f98: 0008 0x8 - 1f9a: 0001 nop - 1f9c: 0402 c.slli64 s0 - 1f9e: 033e slli t1,t1,0xf - 1fa0: 0900 addi s0,sp,144 - 1fa2: 0008 0x8 - 1fa4: 0001 nop - 1fa6: 0402 c.slli64 s0 - 1fa8: 033e slli t1,t1,0xf - 1faa: 0900 addi s0,sp,144 - 1fac: 001c 0x1c - 1fae: 0001 nop - 1fb0: 0402 c.slli64 s0 - 1fb2: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne - 1fb6: 0004 0x4 - 1fb8: 0001 nop - 1fba: 0402 c.slli64 s0 - 1fbc: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne - 1fc0: 0000 unimp - 1fc2: 0001 nop - 1fc4: 0402 c.slli64 s0 - 1fc6: 034c addi a1,sp,388 - 1fc8: 0900 addi s0,sp,144 - 1fca: 0008 0x8 - 1fcc: 0001 nop - 1fce: 0402 c.slli64 s0 - 1fd0: 034c addi a1,sp,388 - 1fd2: 0900 addi s0,sp,144 - 1fd4: 0000 unimp - 1fd6: 0001 nop - 1fd8: 0402 c.slli64 s0 - 1fda: 034c addi a1,sp,388 - 1fdc: 0900 addi s0,sp,144 - 1fde: 0000 unimp - 1fe0: 0001 nop - 1fe2: 0402 c.slli64 s0 - 1fe4: 034c addi a1,sp,388 - 1fe6: 0900 addi s0,sp,144 - 1fe8: 0000 unimp - 1fea: 0001 nop - 1fec: 0402 c.slli64 s0 - 1fee: 034e slli t1,t1,0x13 - 1ff0: 0900 addi s0,sp,144 - 1ff2: 000c 0xc - 1ff4: 0001 nop - 1ff6: 0402 c.slli64 s0 - 1ff8: 034e slli t1,t1,0x13 - 1ffa: 0900 addi s0,sp,144 - 1ffc: 0000 unimp - 1ffe: 0001 nop - 2000: 0402 c.slli64 s0 - 2002: 034e slli t1,t1,0x13 - 2004: 0900 addi s0,sp,144 - 2006: 0000 unimp - 2008: 0001 nop - 200a: 0402 c.slli64 s0 - 200c: 034e slli t1,t1,0x13 - 200e: 0900 addi s0,sp,144 - 2010: 0004 0x4 - 2012: 0001 nop - 2014: 0402 c.slli64 s0 - 2016: 034e slli t1,t1,0x13 - 2018: 0900 addi s0,sp,144 - 201a: 0008 0x8 - 201c: 0001 nop - 201e: 0402 c.slli64 s0 - 2020: 034d addi t1,t1,19 - 2022: 0900 addi s0,sp,144 - 2024: 0004 0x4 - 2026: 0001 nop - 2028: 0402 c.slli64 s0 - 202a: 035d addi t1,t1,23 - 202c: 0900 addi s0,sp,144 - 202e: 0008 0x8 - 2030: 0001 nop - 2032: 0402 c.slli64 s0 - 2034: 035d addi t1,t1,23 - 2036: 0900 addi s0,sp,144 - 2038: 0000 unimp - 203a: 0001 nop - 203c: 0402 c.slli64 s0 - 203e: 035d addi t1,t1,23 - 2040: 0900 addi s0,sp,144 - 2042: 0000 unimp - 2044: 0001 nop - 2046: 0402 c.slli64 s0 - 2048: 035d addi t1,t1,23 - 204a: 0900 addi s0,sp,144 - 204c: 000c 0xc - 204e: 0601 addi a2,a2,0 - 2050: 04090003 lb zero,64(s2) - 2054: 0100 addi s0,sp,128 - 2056: 0200 addi s0,sp,256 - 2058: 3f04 fld fs1,56(a4) - 205a: 0306 slli t1,t1,0x1 - 205c: 0900 addi s0,sp,144 - 205e: 0008 0x8 - 2060: 0001 nop - 2062: 0402 c.slli64 s0 - 2064: 00030647 fmsub.s fa2,ft6,ft0,ft0,rne - 2068: 1809 addi a6,a6,-30 - 206a: 0100 addi s0,sp,128 - 206c: 0200 addi s0,sp,256 - 206e: 4a04 lw s1,16(a2) - 2070: 08090003 lb zero,128(s2) - 2074: 0100 addi s0,sp,128 - 2076: 0200 addi s0,sp,256 - 2078: 4a04 lw s1,16(a2) - 207a: 0306 slli t1,t1,0x1 - 207c: 0900 addi s0,sp,144 - 207e: 000c 0xc - 2080: 0601 addi a2,a2,0 - 2082: 08090003 lb zero,128(s2) - 2086: 0100 addi s0,sp,128 - 2088: 34097f03 0x34097f03 - 208c: 0100 addi s0,sp,128 - 208e: 0306 slli t1,t1,0x1 - 2090: 0900 addi s0,sp,144 - 2092: 0004 0x4 - 2094: 0901 addi s2,s2,0 - 2096: 0008 0x8 - 2098: 0100 addi s0,sp,128 - 209a: ee01 bnez a2,20b2 <_start-0x7fffdf4e> - 209c: 0300000b 0x300000b - 20a0: 9300 0x9300 - 20a2: 0000 unimp - 20a4: 0100 addi s0,sp,128 - 20a6: fb01 bnez a4,1fb6 <_start-0x7fffe04a> - 20a8: 0d0e slli s10,s10,0x3 - 20aa: 0100 addi s0,sp,128 - 20ac: 0101 addi sp,sp,0 - 20ae: 0001 nop - 20b0: 0000 unimp - 20b2: 0001 nop - 20b4: 0100 addi s0,sp,128 - 20b6: 2e2e fld ft8,200(sp) - 20b8: 2f2e2e2f 0x2f2e2e2f - 20bc: 2e2e fld ft8,200(sp) - 20be: 2f2e2e2f 0x2f2e2e2f - 20c2: 6972 flw fs2,28(sp) - 20c4: 2d766373 csrrsi t1,0x2d7,12 - 20c8: 2f636367 0x2f636367 - 20cc: 696c flw fa1,84(a0) - 20ce: 6762 flw fa4,24(sp) - 20d0: 732f6363 bltu t5,s2,27f6 <_start-0x7fffd80a> - 20d4: 2d74666f jal a2,48baa <_start-0x7ffb7456> - 20d8: 7066 flw ft0,120(sp) - 20da: 2e00 fld fs0,24(a2) - 20dc: 2f2e fld ft10,200(sp) - 20de: 2e2e fld ft8,200(sp) - 20e0: 2f2e2e2f 0x2f2e2e2f - 20e4: 2e2e fld ft8,200(sp) - 20e6: 7369722f 0x7369722f - 20ea: 672d7663 bgeu s10,s2,2756 <_start-0x7fffd8aa> - 20ee: 6c2f6363 bltu t5,sp,27b4 <_start-0x7fffd84c> - 20f2: 6269 lui tp,0x1a - 20f4: 2f636367 0x2f636367 - 20f8: 2e2e fld ft8,200(sp) - 20fa: 636e692f vamoandw.v zero,v22,(t3),v18 - 20fe: 756c flw fa1,108(a0) - 2100: 6564 flw fs1,76(a0) - 2102: 0000 unimp - 2104: 756d lui a0,0xffffb - 2106: 646c flw fa1,76(s0) - 2108: 3366 fld ft6,120(sp) - 210a: 632e flw ft6,200(sp) - 210c: 0100 addi s0,sp,128 - 210e: 0000 unimp - 2110: 74666f73 csrrsi t5,0x746,12 - 2114: 662d lui a2,0xb - 2116: 2e70 fld fa2,216(a2) - 2118: 0068 addi a0,sp,12 - 211a: 0001 nop - 211c: 6400 flw fs0,8(s0) - 211e: 6c62756f jal a0,297e4 <_start-0x7ffd681c> - 2122: 2e65 jal 24da <_start-0x7fffdb26> - 2124: 0068 addi a0,sp,12 - 2126: 0001 nop - 2128: 6c00 flw fs0,24(s0) - 212a: 6c676e6f jal t3,787f0 <_start-0x7ff87810> - 212e: 2e676e6f jal t3,78414 <_start-0x7ff87bec> - 2132: 0068 addi a0,sp,12 - 2134: 0002 c.slli64 zero - 2136: 0000 unimp - 2138: 0105 addi sp,sp,1 - 213a: 0500 addi s0,sp,640 - 213c: b002 fsd ft0,32(sp) - 213e: 010e slli sp,sp,0x3 - 2140: 0380 addi s0,sp,448 - 2142: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe42aa> - 2146: 00090103 lb sp,0(s2) - 214a: 0100 addi s0,sp,128 - 214c: 00090003 lb zero,0(s2) - 2150: 0100 addi s0,sp,128 - 2152: 0d05 addi s10,s10,1 - 2154: 00090003 lb zero,0(s2) - 2158: 0100 addi s0,sp,128 - 215a: 0305 addi t1,t1,1 - 215c: 00090103 lb sp,0(s2) - 2160: 0100 addi s0,sp,128 - 2162: 00090003 lb zero,0(s2) - 2166: 0100 addi s0,sp,128 - 2168: 00090003 lb zero,0(s2) - 216c: 0100 addi s0,sp,128 - 216e: 00090003 lb zero,0(s2) - 2172: 0100 addi s0,sp,128 - 2174: 00090103 lb sp,0(s2) - 2178: 0100 addi s0,sp,128 - 217a: 00090003 lb zero,0(s2) - 217e: 0100 addi s0,sp,128 - 2180: 00090003 lb zero,0(s2) - 2184: 0100 addi s0,sp,128 - 2186: 00090003 lb zero,0(s2) - 218a: 0100 addi s0,sp,128 - 218c: 00090103 lb sp,0(s2) - 2190: 0100 addi s0,sp,128 - 2192: 00090003 lb zero,0(s2) - 2196: 0100 addi s0,sp,128 - 2198: 00090003 lb zero,0(s2) - 219c: 0100 addi s0,sp,128 - 219e: 00090003 lb zero,0(s2) - 21a2: 0100 addi s0,sp,128 - 21a4: 00090103 lb sp,0(s2) - 21a8: 0100 addi s0,sp,128 - 21aa: 00090203 lb tp,0(s2) - 21ae: 0100 addi s0,sp,128 - 21b0: 00090103 lb sp,0(s2) - 21b4: 0100 addi s0,sp,128 - 21b6: 00090003 lb zero,0(s2) - 21ba: 0100 addi s0,sp,128 - 21bc: 00090003 lb zero,0(s2) - 21c0: 0100 addi s0,sp,128 - 21c2: 00090003 lb zero,0(s2) - 21c6: 0100 addi s0,sp,128 - 21c8: 00090003 lb zero,0(s2) - 21cc: 0100 addi s0,sp,128 - 21ce: 00090003 lb zero,0(s2) - 21d2: 0100 addi s0,sp,128 - 21d4: 0105 addi sp,sp,1 - 21d6: 0306 slli t1,t1,0x1 - 21d8: 0978 addi a4,sp,156 - 21da: 0000 unimp - 21dc: 0501 addi a0,a0,0 - 21de: 09080303 lb t1,144(a6) - 21e2: 0008 0x8 - 21e4: 0501 addi a0,a0,0 - 21e6: 0301 addi t1,t1,0 - 21e8: 0978 addi a4,sp,156 - 21ea: 0004 0x4 - 21ec: 0501 addi a0,a0,0 - 21ee: 09080303 lb t1,144(a6) - 21f2: 0014 0x14 - 21f4: 0501 addi a0,a0,0 - 21f6: 0301 addi t1,t1,0 - 21f8: 0978 addi a4,sp,156 - 21fa: 0004 0x4 - 21fc: 0501 addi a0,a0,0 - 21fe: 09080303 lb t1,144(a6) - 2202: 000c 0xc - 2204: 0501 addi a0,a0,0 - 2206: 0301 addi t1,t1,0 - 2208: 0978 addi a4,sp,156 - 220a: 0004 0x4 - 220c: 0501 addi a0,a0,0 - 220e: 09080303 lb t1,144(a6) - 2212: 000c 0xc - 2214: 0601 addi a2,a2,0 - 2216: 04090003 lb zero,64(s2) - 221a: 0100 addi s0,sp,128 - 221c: 00090003 lb zero,0(s2) - 2220: 0100 addi s0,sp,128 - 2222: 04090003 lb zero,64(s2) - 2226: 0100 addi s0,sp,128 - 2228: 00090003 lb zero,0(s2) - 222c: 0100 addi s0,sp,128 - 222e: 0200 addi s0,sp,256 - 2230: 0104 addi s1,sp,128 - 2232: 0c090003 lb zero,192(s2) - 2236: 0100 addi s0,sp,128 - 2238: 0200 addi s0,sp,256 - 223a: 0104 addi s1,sp,128 - 223c: 00090003 lb zero,0(s2) - 2240: 0100 addi s0,sp,128 - 2242: 0200 addi s0,sp,256 - 2244: 0104 addi s1,sp,128 - 2246: 00090003 lb zero,0(s2) - 224a: 0100 addi s0,sp,128 - 224c: 0200 addi s0,sp,256 - 224e: 0104 addi s1,sp,128 - 2250: 00090003 lb zero,0(s2) - 2254: 0100 addi s0,sp,128 - 2256: 0200 addi s0,sp,256 - 2258: 0104 addi s1,sp,128 - 225a: 14090003 lb zero,320(s2) - 225e: 0100 addi s0,sp,128 - 2260: 0200 addi s0,sp,256 - 2262: 0104 addi s1,sp,128 - 2264: 04090003 lb zero,64(s2) - 2268: 0100 addi s0,sp,128 - 226a: 0200 addi s0,sp,256 - 226c: 0104 addi s1,sp,128 - 226e: 00090003 lb zero,0(s2) - 2272: 0100 addi s0,sp,128 - 2274: 0200 addi s0,sp,256 - 2276: 0104 addi s1,sp,128 - 2278: 04090003 lb zero,64(s2) - 227c: 0100 addi s0,sp,128 - 227e: 0200 addi s0,sp,256 - 2280: 0104 addi s1,sp,128 - 2282: 00090003 lb zero,0(s2) - 2286: 0100 addi s0,sp,128 - 2288: 0200 addi s0,sp,256 - 228a: 2504 fld fs1,8(a0) - 228c: 00090003 lb zero,0(s2) - 2290: 0100 addi s0,sp,128 - 2292: 0200 addi s0,sp,256 - 2294: 2504 fld fs1,8(a0) - 2296: 00090003 lb zero,0(s2) - 229a: 0100 addi s0,sp,128 - 229c: 04090103 lb sp,64(s2) - 22a0: 0100 addi s0,sp,128 - 22a2: 00090003 lb zero,0(s2) - 22a6: 0100 addi s0,sp,128 - 22a8: 00090003 lb zero,0(s2) - 22ac: 0100 addi s0,sp,128 - 22ae: 00090003 lb zero,0(s2) - 22b2: 0100 addi s0,sp,128 - 22b4: 00090003 lb zero,0(s2) - 22b8: 0100 addi s0,sp,128 - 22ba: 00090003 lb zero,0(s2) - 22be: 0100 addi s0,sp,128 - 22c0: 10090003 lb zero,256(s2) - 22c4: 0100 addi s0,sp,128 - 22c6: 00090003 lb zero,0(s2) - 22ca: 0100 addi s0,sp,128 - 22cc: 04090003 lb zero,64(s2) - 22d0: 0100 addi s0,sp,128 - 22d2: 00090003 lb zero,0(s2) - 22d6: 0100 addi s0,sp,128 - 22d8: 0200 addi s0,sp,256 - 22da: 0104 addi s1,sp,128 - 22dc: 0c090003 lb zero,192(s2) - 22e0: 0100 addi s0,sp,128 - 22e2: 0200 addi s0,sp,256 - 22e4: 0104 addi s1,sp,128 - 22e6: 00090003 lb zero,0(s2) - 22ea: 0100 addi s0,sp,128 - 22ec: 0200 addi s0,sp,256 - 22ee: 0104 addi s1,sp,128 - 22f0: 00090003 lb zero,0(s2) - 22f4: 0100 addi s0,sp,128 - 22f6: 0200 addi s0,sp,256 - 22f8: 0104 addi s1,sp,128 - 22fa: 00090003 lb zero,0(s2) - 22fe: 0100 addi s0,sp,128 - 2300: 0200 addi s0,sp,256 - 2302: 0104 addi s1,sp,128 - 2304: 14090003 lb zero,320(s2) - 2308: 0100 addi s0,sp,128 - 230a: 0200 addi s0,sp,256 - 230c: 0104 addi s1,sp,128 - 230e: 08090003 lb zero,128(s2) - 2312: 0100 addi s0,sp,128 - 2314: 0200 addi s0,sp,256 - 2316: 0104 addi s1,sp,128 - 2318: 00090003 lb zero,0(s2) - 231c: 0100 addi s0,sp,128 - 231e: 0200 addi s0,sp,256 - 2320: 0104 addi s1,sp,128 - 2322: 00090003 lb zero,0(s2) - 2326: 0100 addi s0,sp,128 - 2328: 0200 addi s0,sp,256 - 232a: 0104 addi s1,sp,128 - 232c: 00090003 lb zero,0(s2) - 2330: 0100 addi s0,sp,128 - 2332: 0200 addi s0,sp,256 - 2334: 2504 fld fs1,8(a0) - 2336: 00090003 lb zero,0(s2) - 233a: 0100 addi s0,sp,128 - 233c: 0200 addi s0,sp,256 - 233e: 2504 fld fs1,8(a0) - 2340: 00090003 lb zero,0(s2) - 2344: 0100 addi s0,sp,128 - 2346: 04090103 lb sp,64(s2) - 234a: 0100 addi s0,sp,128 - 234c: 00090003 lb zero,0(s2) - 2350: 0100 addi s0,sp,128 - 2352: 18090003 lb zero,384(s2) - 2356: 0100 addi s0,sp,128 - 2358: 04090003 lb zero,64(s2) - 235c: 0100 addi s0,sp,128 - 235e: 0200 addi s0,sp,256 - 2360: 0204 addi s1,sp,256 - 2362: 1c097e03 0x1c097e03 - 2366: 0100 addi s0,sp,128 - 2368: 0200 addi s0,sp,256 - 236a: 0c04 addi s1,sp,528 - 236c: 08090003 lb zero,128(s2) - 2370: 0100 addi s0,sp,128 - 2372: 0200 addi s0,sp,256 - 2374: 0c04 addi s1,sp,528 - 2376: 00090003 lb zero,0(s2) - 237a: 0100 addi s0,sp,128 - 237c: 0200 addi s0,sp,256 - 237e: 0c04 addi s1,sp,528 - 2380: 00090003 lb zero,0(s2) - 2384: 0100 addi s0,sp,128 - 2386: 0200 addi s0,sp,256 - 2388: 0c04 addi s1,sp,528 - 238a: 00090003 lb zero,0(s2) - 238e: 0100 addi s0,sp,128 - 2390: 0200 addi s0,sp,256 - 2392: 1004 addi s1,sp,32 - 2394: 04090003 lb zero,64(s2) - 2398: 0100 addi s0,sp,128 - 239a: 0200 addi s0,sp,256 - 239c: 1004 addi s1,sp,32 - 239e: 00090003 lb zero,0(s2) - 23a2: 0100 addi s0,sp,128 - 23a4: 0200 addi s0,sp,256 - 23a6: 1004 addi s1,sp,32 - 23a8: 00090003 lb zero,0(s2) - 23ac: 0100 addi s0,sp,128 - 23ae: 0200 addi s0,sp,256 - 23b0: 1004 addi s1,sp,32 - 23b2: 00090003 lb zero,0(s2) - 23b6: 0100 addi s0,sp,128 - 23b8: 0200 addi s0,sp,256 - 23ba: 1b04 addi s1,sp,432 - 23bc: 08090003 lb zero,128(s2) - 23c0: 0100 addi s0,sp,128 - 23c2: 0200 addi s0,sp,256 - 23c4: 1b04 addi s1,sp,432 - 23c6: 04090003 lb zero,64(s2) - 23ca: 0100 addi s0,sp,128 - 23cc: 0200 addi s0,sp,256 - 23ce: 1c04 addi s1,sp,560 - 23d0: 08090003 lb zero,128(s2) - 23d4: 0100 addi s0,sp,128 - 23d6: 0200 addi s0,sp,256 - 23d8: 1c04 addi s1,sp,560 - 23da: 08090003 lb zero,128(s2) - 23de: 0100 addi s0,sp,128 - 23e0: 0200 addi s0,sp,256 - 23e2: 1c04 addi s1,sp,560 - 23e4: 10090003 lb zero,256(s2) - 23e8: 0100 addi s0,sp,128 - 23ea: 0200 addi s0,sp,256 - 23ec: 1c04 addi s1,sp,560 - 23ee: 04090003 lb zero,64(s2) - 23f2: 0100 addi s0,sp,128 - 23f4: 0200 addi s0,sp,256 - 23f6: 2504 fld fs1,8(a0) - 23f8: 00090003 lb zero,0(s2) - 23fc: 0100 addi s0,sp,128 - 23fe: 0200 addi s0,sp,256 - 2400: 1404 addi s1,sp,544 - 2402: 0c090003 lb zero,192(s2) - 2406: 0100 addi s0,sp,128 - 2408: 0200 addi s0,sp,256 - 240a: 1404 addi s1,sp,544 - 240c: 00090003 lb zero,0(s2) - 2410: 0100 addi s0,sp,128 - 2412: 0200 addi s0,sp,256 - 2414: 1404 addi s1,sp,544 - 2416: 00090003 lb zero,0(s2) - 241a: 0100 addi s0,sp,128 - 241c: 0200 addi s0,sp,256 - 241e: 1404 addi s1,sp,544 - 2420: 00090003 lb zero,0(s2) - 2424: 0100 addi s0,sp,128 - 2426: 0200 addi s0,sp,256 - 2428: 1404 addi s1,sp,544 - 242a: 04090003 lb zero,64(s2) - 242e: 0100 addi s0,sp,128 - 2430: 0200 addi s0,sp,256 - 2432: 1d04 addi s1,sp,688 - 2434: 08090003 lb zero,128(s2) - 2438: 0100 addi s0,sp,128 - 243a: 0200 addi s0,sp,256 - 243c: 1d04 addi s1,sp,688 - 243e: 08090003 lb zero,128(s2) - 2442: 0100 addi s0,sp,128 - 2444: 0200 addi s0,sp,256 - 2446: 0304 addi s1,sp,384 - 2448: 08090003 lb zero,128(s2) - 244c: 0100 addi s0,sp,128 - 244e: 0306 slli t1,t1,0x1 - 2450: 0900 addi s0,sp,144 - 2452: 0008 0x8 - 2454: 0001 nop - 2456: 0402 c.slli64 s0 - 2458: 0602 c.slli64 a2 - 245a: 30090103 lb sp,768(s2) - 245e: 0100 addi s0,sp,128 - 2460: 0200 addi s0,sp,256 - 2462: 0c04 addi s1,sp,528 - 2464: 08090003 lb zero,128(s2) - 2468: 0100 addi s0,sp,128 - 246a: 0200 addi s0,sp,256 - 246c: 0c04 addi s1,sp,528 - 246e: 00090003 lb zero,0(s2) - 2472: 0100 addi s0,sp,128 - 2474: 0200 addi s0,sp,256 - 2476: 0c04 addi s1,sp,528 - 2478: 00090003 lb zero,0(s2) - 247c: 0100 addi s0,sp,128 - 247e: 0200 addi s0,sp,256 - 2480: 0c04 addi s1,sp,528 - 2482: 00090003 lb zero,0(s2) - 2486: 0100 addi s0,sp,128 - 2488: 0200 addi s0,sp,256 - 248a: 1004 addi s1,sp,32 - 248c: 04090003 lb zero,64(s2) - 2490: 0100 addi s0,sp,128 - 2492: 0200 addi s0,sp,256 - 2494: 1004 addi s1,sp,32 - 2496: 00090003 lb zero,0(s2) - 249a: 0100 addi s0,sp,128 - 249c: 0200 addi s0,sp,256 - 249e: 1004 addi s1,sp,32 - 24a0: 00090003 lb zero,0(s2) - 24a4: 0100 addi s0,sp,128 - 24a6: 0200 addi s0,sp,256 - 24a8: 1004 addi s1,sp,32 - 24aa: 00090003 lb zero,0(s2) - 24ae: 0100 addi s0,sp,128 - 24b0: 0200 addi s0,sp,256 - 24b2: 1b04 addi s1,sp,432 - 24b4: 08090003 lb zero,128(s2) - 24b8: 0100 addi s0,sp,128 - 24ba: 0200 addi s0,sp,256 - 24bc: 1b04 addi s1,sp,432 - 24be: 04090003 lb zero,64(s2) - 24c2: 0100 addi s0,sp,128 - 24c4: 0200 addi s0,sp,256 - 24c6: 1c04 addi s1,sp,560 - 24c8: 08090003 lb zero,128(s2) - 24cc: 0100 addi s0,sp,128 - 24ce: 0200 addi s0,sp,256 - 24d0: 1c04 addi s1,sp,560 - 24d2: 08090003 lb zero,128(s2) - 24d6: 0100 addi s0,sp,128 - 24d8: 0200 addi s0,sp,256 - 24da: 1c04 addi s1,sp,560 - 24dc: 10090003 lb zero,256(s2) - 24e0: 0100 addi s0,sp,128 - 24e2: 0200 addi s0,sp,256 - 24e4: 1c04 addi s1,sp,560 - 24e6: 04090003 lb zero,64(s2) - 24ea: 0100 addi s0,sp,128 - 24ec: 0200 addi s0,sp,256 - 24ee: 2504 fld fs1,8(a0) - 24f0: 00090003 lb zero,0(s2) - 24f4: 0100 addi s0,sp,128 - 24f6: 0200 addi s0,sp,256 - 24f8: 1404 addi s1,sp,544 - 24fa: 0c090003 lb zero,192(s2) - 24fe: 0100 addi s0,sp,128 - 2500: 0200 addi s0,sp,256 - 2502: 1404 addi s1,sp,544 - 2504: 00090003 lb zero,0(s2) - 2508: 0100 addi s0,sp,128 - 250a: 0200 addi s0,sp,256 - 250c: 1404 addi s1,sp,544 - 250e: 00090003 lb zero,0(s2) - 2512: 0100 addi s0,sp,128 - 2514: 0200 addi s0,sp,256 - 2516: 1404 addi s1,sp,544 - 2518: 00090003 lb zero,0(s2) - 251c: 0100 addi s0,sp,128 - 251e: 0200 addi s0,sp,256 - 2520: 1404 addi s1,sp,544 - 2522: 08090003 lb zero,128(s2) - 2526: 0100 addi s0,sp,128 - 2528: 0200 addi s0,sp,256 - 252a: 1d04 addi s1,sp,688 - 252c: 08090003 lb zero,128(s2) - 2530: 0100 addi s0,sp,128 - 2532: 0200 addi s0,sp,256 - 2534: 1d04 addi s1,sp,688 - 2536: 08090003 lb zero,128(s2) - 253a: 0100 addi s0,sp,128 - 253c: 0200 addi s0,sp,256 - 253e: 0304 addi s1,sp,384 - 2540: 08090003 lb zero,128(s2) - 2544: 0100 addi s0,sp,128 - 2546: 0306 slli t1,t1,0x1 - 2548: 0900 addi s0,sp,144 - 254a: 0008 0x8 - 254c: 0001 nop - 254e: 0402 c.slli64 s0 - 2550: 0602 c.slli64 a2 - 2552: 30090103 lb sp,768(s2) - 2556: 0100 addi s0,sp,128 - 2558: 0200 addi s0,sp,256 - 255a: 0204 addi s1,sp,256 - 255c: 00090003 lb zero,0(s2) - 2560: 0100 addi s0,sp,128 - 2562: 0200 addi s0,sp,256 - 2564: 0204 addi s1,sp,256 - 2566: 00090003 lb zero,0(s2) - 256a: 0100 addi s0,sp,128 - 256c: 0200 addi s0,sp,256 - 256e: 0204 addi s1,sp,256 - 2570: 00090003 lb zero,0(s2) - 2574: 0100 addi s0,sp,128 - 2576: 0200 addi s0,sp,256 - 2578: 0204 addi s1,sp,256 - 257a: 00090003 lb zero,0(s2) - 257e: 0100 addi s0,sp,128 - 2580: 0200 addi s0,sp,256 - 2582: 0204 addi s1,sp,256 - 2584: 00090003 lb zero,0(s2) - 2588: 0100 addi s0,sp,128 - 258a: 0200 addi s0,sp,256 - 258c: 0204 addi s1,sp,256 - 258e: 00090003 lb zero,0(s2) - 2592: 0100 addi s0,sp,128 - 2594: 0200 addi s0,sp,256 - 2596: 0204 addi s1,sp,256 - 2598: 00090003 lb zero,0(s2) - 259c: 0100 addi s0,sp,128 - 259e: 0200 addi s0,sp,256 - 25a0: 0204 addi s1,sp,256 - 25a2: 00090003 lb zero,0(s2) - 25a6: 0100 addi s0,sp,128 - 25a8: 0200 addi s0,sp,256 - 25aa: 0204 addi s1,sp,256 - 25ac: 00090003 lb zero,0(s2) - 25b0: 0100 addi s0,sp,128 - 25b2: 0200 addi s0,sp,256 - 25b4: 0204 addi s1,sp,256 - 25b6: 00090003 lb zero,0(s2) - 25ba: 0100 addi s0,sp,128 - 25bc: 0200 addi s0,sp,256 - 25be: 0204 addi s1,sp,256 - 25c0: 0c090003 lb zero,192(s2) - 25c4: 0100 addi s0,sp,128 - 25c6: 0200 addi s0,sp,256 - 25c8: 0204 addi s1,sp,256 - 25ca: 00090003 lb zero,0(s2) - 25ce: 0100 addi s0,sp,128 - 25d0: 0200 addi s0,sp,256 - 25d2: 0204 addi s1,sp,256 - 25d4: 04090003 lb zero,64(s2) - 25d8: 0100 addi s0,sp,128 - 25da: 0200 addi s0,sp,256 - 25dc: 0204 addi s1,sp,256 - 25de: 10090003 lb zero,256(s2) - 25e2: 0100 addi s0,sp,128 - 25e4: 0200 addi s0,sp,256 - 25e6: 0204 addi s1,sp,256 - 25e8: 00090003 lb zero,0(s2) - 25ec: 0100 addi s0,sp,128 - 25ee: 0200 addi s0,sp,256 - 25f0: 0204 addi s1,sp,256 - 25f2: 04090003 lb zero,64(s2) - 25f6: 0100 addi s0,sp,128 - 25f8: 0200 addi s0,sp,256 - 25fa: 0204 addi s1,sp,256 - 25fc: 10090003 lb zero,256(s2) - 2600: 0100 addi s0,sp,128 - 2602: 0200 addi s0,sp,256 - 2604: 0204 addi s1,sp,256 - 2606: 00090003 lb zero,0(s2) - 260a: 0100 addi s0,sp,128 - 260c: 0200 addi s0,sp,256 - 260e: 0204 addi s1,sp,256 - 2610: 00090003 lb zero,0(s2) - 2614: 0100 addi s0,sp,128 - 2616: 0200 addi s0,sp,256 - 2618: 0904 addi s1,sp,144 - 261a: 04090003 lb zero,64(s2) - 261e: 0100 addi s0,sp,128 - 2620: 0200 addi s0,sp,256 - 2622: 0b04 addi s1,sp,400 - 2624: 04090003 lb zero,64(s2) - 2628: 0100 addi s0,sp,128 - 262a: 0200 addi s0,sp,256 - 262c: 0b04 addi s1,sp,400 - 262e: 04090003 lb zero,64(s2) - 2632: 0100 addi s0,sp,128 - 2634: 0200 addi s0,sp,256 - 2636: 0b04 addi s1,sp,400 - 2638: 18090003 lb zero,384(s2) - 263c: 0100 addi s0,sp,128 - 263e: 0200 addi s0,sp,256 - 2640: 0b04 addi s1,sp,400 - 2642: 00090003 lb zero,0(s2) - 2646: 0100 addi s0,sp,128 - 2648: 0200 addi s0,sp,256 - 264a: 0b04 addi s1,sp,400 - 264c: 00090003 lb zero,0(s2) - 2650: 0100 addi s0,sp,128 - 2652: 0200 addi s0,sp,256 - 2654: 0b04 addi s1,sp,400 - 2656: 00090003 lb zero,0(s2) - 265a: 0100 addi s0,sp,128 - 265c: 0200 addi s0,sp,256 - 265e: 0b04 addi s1,sp,400 - 2660: 00090003 lb zero,0(s2) - 2664: 0100 addi s0,sp,128 - 2666: 0200 addi s0,sp,256 - 2668: 0b04 addi s1,sp,400 - 266a: 00090003 lb zero,0(s2) - 266e: 0100 addi s0,sp,128 - 2670: 0200 addi s0,sp,256 - 2672: 0b04 addi s1,sp,400 - 2674: 00090003 lb zero,0(s2) - 2678: 0100 addi s0,sp,128 - 267a: 0200 addi s0,sp,256 - 267c: 0b04 addi s1,sp,400 - 267e: 00090003 lb zero,0(s2) - 2682: 0100 addi s0,sp,128 - 2684: 0200 addi s0,sp,256 - 2686: 0b04 addi s1,sp,400 - 2688: 08090003 lb zero,128(s2) - 268c: 0100 addi s0,sp,128 - 268e: 0200 addi s0,sp,256 - 2690: 0b04 addi s1,sp,400 - 2692: 00090003 lb zero,0(s2) - 2696: 0100 addi s0,sp,128 - 2698: 0200 addi s0,sp,256 - 269a: 0b04 addi s1,sp,400 - 269c: 00090003 lb zero,0(s2) - 26a0: 0100 addi s0,sp,128 - 26a2: 0200 addi s0,sp,256 - 26a4: 0b04 addi s1,sp,400 - 26a6: 14090003 lb zero,320(s2) - 26aa: 0100 addi s0,sp,128 - 26ac: 0200 addi s0,sp,256 - 26ae: 0b04 addi s1,sp,400 - 26b0: 00090003 lb zero,0(s2) - 26b4: 0100 addi s0,sp,128 - 26b6: 0200 addi s0,sp,256 - 26b8: 0b04 addi s1,sp,400 - 26ba: 00090003 lb zero,0(s2) - 26be: 0100 addi s0,sp,128 - 26c0: 0200 addi s0,sp,256 - 26c2: 0c04 addi s1,sp,528 - 26c4: 04090003 lb zero,64(s2) - 26c8: 0100 addi s0,sp,128 - 26ca: 0200 addi s0,sp,256 - 26cc: 0e04 addi s1,sp,784 - 26ce: 08090003 lb zero,128(s2) - 26d2: 0100 addi s0,sp,128 - 26d4: 0200 addi s0,sp,256 - 26d6: 0e04 addi s1,sp,784 - 26d8: 0c090003 lb zero,192(s2) - 26dc: 0100 addi s0,sp,128 - 26de: 0200 addi s0,sp,256 - 26e0: 0e04 addi s1,sp,784 - 26e2: 24090003 lb zero,576(s2) - 26e6: 0100 addi s0,sp,128 - 26e8: 0200 addi s0,sp,256 - 26ea: 0e04 addi s1,sp,784 - 26ec: 00090003 lb zero,0(s2) - 26f0: 0100 addi s0,sp,128 - 26f2: 0200 addi s0,sp,256 - 26f4: 0e04 addi s1,sp,784 - 26f6: 00090003 lb zero,0(s2) - 26fa: 0100 addi s0,sp,128 - 26fc: 0200 addi s0,sp,256 - 26fe: 0e04 addi s1,sp,784 - 2700: 00090003 lb zero,0(s2) - 2704: 0100 addi s0,sp,128 - 2706: 0200 addi s0,sp,256 - 2708: 0e04 addi s1,sp,784 - 270a: 00090003 lb zero,0(s2) - 270e: 0100 addi s0,sp,128 - 2710: 0200 addi s0,sp,256 - 2712: 0e04 addi s1,sp,784 - 2714: 00090003 lb zero,0(s2) - 2718: 0100 addi s0,sp,128 - 271a: 0200 addi s0,sp,256 - 271c: 0e04 addi s1,sp,784 - 271e: 00090003 lb zero,0(s2) - 2722: 0100 addi s0,sp,128 - 2724: 0200 addi s0,sp,256 - 2726: 0e04 addi s1,sp,784 - 2728: 00090003 lb zero,0(s2) - 272c: 0100 addi s0,sp,128 - 272e: 0200 addi s0,sp,256 - 2730: 0e04 addi s1,sp,784 - 2732: 00090003 lb zero,0(s2) - 2736: 0100 addi s0,sp,128 - 2738: 0200 addi s0,sp,256 - 273a: 0e04 addi s1,sp,784 - 273c: 00090003 lb zero,0(s2) - 2740: 0100 addi s0,sp,128 - 2742: 0200 addi s0,sp,256 - 2744: 0e04 addi s1,sp,784 - 2746: 04090003 lb zero,64(s2) - 274a: 0100 addi s0,sp,128 - 274c: 0200 addi s0,sp,256 - 274e: 0e04 addi s1,sp,784 - 2750: 08090003 lb zero,128(s2) - 2754: 0100 addi s0,sp,128 - 2756: 0200 addi s0,sp,256 - 2758: 0e04 addi s1,sp,784 - 275a: 04090003 lb zero,64(s2) - 275e: 0100 addi s0,sp,128 - 2760: 0200 addi s0,sp,256 - 2762: 0e04 addi s1,sp,784 - 2764: 08090003 lb zero,128(s2) - 2768: 0100 addi s0,sp,128 - 276a: 0200 addi s0,sp,256 - 276c: 0f04 addi s1,sp,912 - 276e: 04090003 lb zero,64(s2) - 2772: 0100 addi s0,sp,128 - 2774: 0200 addi s0,sp,256 - 2776: 1104 addi s1,sp,160 - 2778: 04090003 lb zero,64(s2) - 277c: 0100 addi s0,sp,128 - 277e: 0200 addi s0,sp,256 - 2780: 1104 addi s1,sp,160 - 2782: 0c090003 lb zero,192(s2) - 2786: 0100 addi s0,sp,128 - 2788: 0200 addi s0,sp,256 - 278a: 1104 addi s1,sp,160 - 278c: 18090003 lb zero,384(s2) - 2790: 0100 addi s0,sp,128 - 2792: 0200 addi s0,sp,256 - 2794: 1104 addi s1,sp,160 - 2796: 00090003 lb zero,0(s2) - 279a: 0100 addi s0,sp,128 - 279c: 0200 addi s0,sp,256 - 279e: 1104 addi s1,sp,160 - 27a0: 00090003 lb zero,0(s2) - 27a4: 0100 addi s0,sp,128 - 27a6: 0200 addi s0,sp,256 - 27a8: 1104 addi s1,sp,160 - 27aa: 00090003 lb zero,0(s2) - 27ae: 0100 addi s0,sp,128 - 27b0: 0200 addi s0,sp,256 - 27b2: 1104 addi s1,sp,160 - 27b4: 00090003 lb zero,0(s2) - 27b8: 0100 addi s0,sp,128 - 27ba: 0200 addi s0,sp,256 - 27bc: 1104 addi s1,sp,160 - 27be: 00090003 lb zero,0(s2) - 27c2: 0100 addi s0,sp,128 - 27c4: 0200 addi s0,sp,256 - 27c6: 1104 addi s1,sp,160 - 27c8: 00090003 lb zero,0(s2) - 27cc: 0100 addi s0,sp,128 - 27ce: 0200 addi s0,sp,256 - 27d0: 1104 addi s1,sp,160 - 27d2: 00090003 lb zero,0(s2) - 27d6: 0100 addi s0,sp,128 - 27d8: 0200 addi s0,sp,256 - 27da: 1104 addi s1,sp,160 - 27dc: 00090003 lb zero,0(s2) - 27e0: 0100 addi s0,sp,128 - 27e2: 0200 addi s0,sp,256 - 27e4: 1104 addi s1,sp,160 - 27e6: 00090003 lb zero,0(s2) - 27ea: 0100 addi s0,sp,128 - 27ec: 0200 addi s0,sp,256 - 27ee: 1104 addi s1,sp,160 - 27f0: 04090003 lb zero,64(s2) - 27f4: 0100 addi s0,sp,128 - 27f6: 0200 addi s0,sp,256 - 27f8: 1104 addi s1,sp,160 - 27fa: 08090003 lb zero,128(s2) - 27fe: 0100 addi s0,sp,128 - 2800: 0200 addi s0,sp,256 - 2802: 1104 addi s1,sp,160 - 2804: 04090003 lb zero,64(s2) - 2808: 0100 addi s0,sp,128 - 280a: 0200 addi s0,sp,256 - 280c: 1104 addi s1,sp,160 - 280e: 08090003 lb zero,128(s2) - 2812: 0100 addi s0,sp,128 - 2814: 0200 addi s0,sp,256 - 2816: 1204 addi s1,sp,288 - 2818: 04090003 lb zero,64(s2) - 281c: 0100 addi s0,sp,128 - 281e: 0200 addi s0,sp,256 - 2820: 1404 addi s1,sp,544 - 2822: 04090003 lb zero,64(s2) - 2826: 0100 addi s0,sp,128 - 2828: 0200 addi s0,sp,256 - 282a: 1404 addi s1,sp,544 - 282c: 00090003 lb zero,0(s2) - 2830: 0100 addi s0,sp,128 - 2832: 0200 addi s0,sp,256 - 2834: 1404 addi s1,sp,544 - 2836: 00090003 lb zero,0(s2) - 283a: 0100 addi s0,sp,128 - 283c: 0200 addi s0,sp,256 - 283e: 1404 addi s1,sp,544 - 2840: 00090003 lb zero,0(s2) - 2844: 0100 addi s0,sp,128 - 2846: 0200 addi s0,sp,256 - 2848: 1404 addi s1,sp,544 - 284a: 00090003 lb zero,0(s2) - 284e: 0100 addi s0,sp,128 - 2850: 0200 addi s0,sp,256 - 2852: 1404 addi s1,sp,544 - 2854: 18090003 lb zero,384(s2) - 2858: 0100 addi s0,sp,128 - 285a: 0200 addi s0,sp,256 - 285c: 1404 addi s1,sp,544 - 285e: 08090003 lb zero,128(s2) - 2862: 0100 addi s0,sp,128 - 2864: 0200 addi s0,sp,256 - 2866: 1404 addi s1,sp,544 - 2868: 04090003 lb zero,64(s2) - 286c: 0100 addi s0,sp,128 - 286e: 0200 addi s0,sp,256 - 2870: 1404 addi s1,sp,544 - 2872: 00090003 lb zero,0(s2) - 2876: 0100 addi s0,sp,128 - 2878: 0200 addi s0,sp,256 - 287a: 1404 addi s1,sp,544 - 287c: 04090003 lb zero,64(s2) - 2880: 0100 addi s0,sp,128 - 2882: 0200 addi s0,sp,256 - 2884: 1404 addi s1,sp,544 - 2886: 00090003 lb zero,0(s2) - 288a: 0100 addi s0,sp,128 - 288c: 0200 addi s0,sp,256 - 288e: 1404 addi s1,sp,544 - 2890: 00090003 lb zero,0(s2) - 2894: 0100 addi s0,sp,128 - 2896: 0200 addi s0,sp,256 - 2898: 1404 addi s1,sp,544 - 289a: 00090003 lb zero,0(s2) - 289e: 0100 addi s0,sp,128 - 28a0: 0200 addi s0,sp,256 - 28a2: 1404 addi s1,sp,544 - 28a4: 00090003 lb zero,0(s2) - 28a8: 0100 addi s0,sp,128 - 28aa: 0200 addi s0,sp,256 - 28ac: 1404 addi s1,sp,544 - 28ae: 04090003 lb zero,64(s2) - 28b2: 0100 addi s0,sp,128 - 28b4: 0200 addi s0,sp,256 - 28b6: 1404 addi s1,sp,544 - 28b8: 04090003 lb zero,64(s2) - 28bc: 0100 addi s0,sp,128 - 28be: 0200 addi s0,sp,256 - 28c0: 1404 addi s1,sp,544 - 28c2: 04090003 lb zero,64(s2) - 28c6: 0100 addi s0,sp,128 - 28c8: 0200 addi s0,sp,256 - 28ca: 1404 addi s1,sp,544 - 28cc: 00090003 lb zero,0(s2) - 28d0: 0100 addi s0,sp,128 - 28d2: 0200 addi s0,sp,256 - 28d4: 1404 addi s1,sp,544 - 28d6: 04090003 lb zero,64(s2) - 28da: 0100 addi s0,sp,128 - 28dc: 0200 addi s0,sp,256 - 28de: 1404 addi s1,sp,544 - 28e0: 00090003 lb zero,0(s2) - 28e4: 0100 addi s0,sp,128 - 28e6: 0200 addi s0,sp,256 - 28e8: 1404 addi s1,sp,544 - 28ea: 00090003 lb zero,0(s2) - 28ee: 0100 addi s0,sp,128 - 28f0: 0200 addi s0,sp,256 - 28f2: 1404 addi s1,sp,544 - 28f4: 00090003 lb zero,0(s2) - 28f8: 0100 addi s0,sp,128 - 28fa: 0200 addi s0,sp,256 - 28fc: 1404 addi s1,sp,544 - 28fe: 00090003 lb zero,0(s2) - 2902: 0100 addi s0,sp,128 - 2904: 0200 addi s0,sp,256 - 2906: 1404 addi s1,sp,544 - 2908: 00090003 lb zero,0(s2) - 290c: 0100 addi s0,sp,128 - 290e: 0200 addi s0,sp,256 - 2910: 1404 addi s1,sp,544 - 2912: 00090003 lb zero,0(s2) - 2916: 0100 addi s0,sp,128 - 2918: 0200 addi s0,sp,256 - 291a: 1404 addi s1,sp,544 - 291c: 00090003 lb zero,0(s2) - 2920: 0100 addi s0,sp,128 - 2922: 0200 addi s0,sp,256 - 2924: 1404 addi s1,sp,544 - 2926: 00090003 lb zero,0(s2) - 292a: 0100 addi s0,sp,128 - 292c: 0200 addi s0,sp,256 - 292e: 1404 addi s1,sp,544 - 2930: 00090003 lb zero,0(s2) - 2934: 0100 addi s0,sp,128 - 2936: 0200 addi s0,sp,256 - 2938: 1404 addi s1,sp,544 - 293a: 00090003 lb zero,0(s2) - 293e: 0100 addi s0,sp,128 - 2940: 0200 addi s0,sp,256 - 2942: 1404 addi s1,sp,544 - 2944: 00090003 lb zero,0(s2) - 2948: 0100 addi s0,sp,128 - 294a: 0200 addi s0,sp,256 - 294c: 1404 addi s1,sp,544 - 294e: 00090003 lb zero,0(s2) - 2952: 0100 addi s0,sp,128 - 2954: 0200 addi s0,sp,256 - 2956: 1404 addi s1,sp,544 - 2958: 00090003 lb zero,0(s2) - 295c: 0100 addi s0,sp,128 - 295e: 0200 addi s0,sp,256 - 2960: 1404 addi s1,sp,544 - 2962: 00090003 lb zero,0(s2) - 2966: 0100 addi s0,sp,128 - 2968: 0200 addi s0,sp,256 - 296a: 1404 addi s1,sp,544 - 296c: 00090003 lb zero,0(s2) - 2970: 0100 addi s0,sp,128 - 2972: 0200 addi s0,sp,256 - 2974: 1404 addi s1,sp,544 - 2976: 00090003 lb zero,0(s2) - 297a: 0100 addi s0,sp,128 - 297c: 0200 addi s0,sp,256 - 297e: 1404 addi s1,sp,544 - 2980: 00090003 lb zero,0(s2) - 2984: 0100 addi s0,sp,128 - 2986: 0200 addi s0,sp,256 - 2988: 1404 addi s1,sp,544 - 298a: 34090003 lb zero,832(s2) - 298e: 0100 addi s0,sp,128 - 2990: 0200 addi s0,sp,256 - 2992: 1404 addi s1,sp,544 - 2994: 00090003 lb zero,0(s2) - 2998: 0100 addi s0,sp,128 - 299a: 0200 addi s0,sp,256 - 299c: 1404 addi s1,sp,544 - 299e: 00090003 lb zero,0(s2) - 29a2: 0100 addi s0,sp,128 - 29a4: 0200 addi s0,sp,256 - 29a6: 1404 addi s1,sp,544 - 29a8: 1c090003 lb zero,448(s2) - 29ac: 0100 addi s0,sp,128 - 29ae: 0200 addi s0,sp,256 - 29b0: 1404 addi s1,sp,544 - 29b2: 00090003 lb zero,0(s2) - 29b6: 0100 addi s0,sp,128 - 29b8: 0200 addi s0,sp,256 - 29ba: 1404 addi s1,sp,544 - 29bc: 00090003 lb zero,0(s2) - 29c0: 0100 addi s0,sp,128 - 29c2: 0200 addi s0,sp,256 - 29c4: 2604 fld fs1,8(a2) - 29c6: 08090003 lb zero,128(s2) - 29ca: 0100 addi s0,sp,128 - 29cc: 0200 addi s0,sp,256 - 29ce: 2604 fld fs1,8(a2) - 29d0: 00090003 lb zero,0(s2) - 29d4: 0100 addi s0,sp,128 - 29d6: 0200 addi s0,sp,256 - 29d8: 2604 fld fs1,8(a2) - 29da: 14090003 lb zero,320(s2) - 29de: 0100 addi s0,sp,128 - 29e0: 0200 addi s0,sp,256 - 29e2: 0204 addi s1,sp,256 - 29e4: 04090103 lb sp,64(s2) - 29e8: 0100 addi s0,sp,128 - 29ea: 0200 addi s0,sp,256 - 29ec: 0204 addi s1,sp,256 - 29ee: 04090003 lb zero,64(s2) - 29f2: 0100 addi s0,sp,128 - 29f4: 0200 addi s0,sp,256 - 29f6: 0604 addi s1,sp,768 - 29f8: 04090003 lb zero,64(s2) - 29fc: 0100 addi s0,sp,128 - 29fe: 0200 addi s0,sp,256 - 2a00: 0604 addi s1,sp,768 - 2a02: 00090003 lb zero,0(s2) - 2a06: 0100 addi s0,sp,128 - 2a08: 0200 addi s0,sp,256 - 2a0a: 0804 addi s1,sp,16 - 2a0c: 08090003 lb zero,128(s2) - 2a10: 0100 addi s0,sp,128 - 2a12: 0200 addi s0,sp,256 - 2a14: 0804 addi s1,sp,16 - 2a16: 00090003 lb zero,0(s2) - 2a1a: 0100 addi s0,sp,128 - 2a1c: 0200 addi s0,sp,256 - 2a1e: 0804 addi s1,sp,16 - 2a20: 00090003 lb zero,0(s2) - 2a24: 0100 addi s0,sp,128 - 2a26: 0200 addi s0,sp,256 - 2a28: 0804 addi s1,sp,16 - 2a2a: 00090003 lb zero,0(s2) - 2a2e: 0100 addi s0,sp,128 - 2a30: 0200 addi s0,sp,256 - 2a32: 0a04 addi s1,sp,272 - 2a34: 0c090003 lb zero,192(s2) - 2a38: 0100 addi s0,sp,128 - 2a3a: 0200 addi s0,sp,256 - 2a3c: 0a04 addi s1,sp,272 - 2a3e: 00090003 lb zero,0(s2) - 2a42: 0100 addi s0,sp,128 - 2a44: 0200 addi s0,sp,256 - 2a46: 0a04 addi s1,sp,272 - 2a48: 00090003 lb zero,0(s2) - 2a4c: 0100 addi s0,sp,128 - 2a4e: 0200 addi s0,sp,256 - 2a50: 0a04 addi s1,sp,272 - 2a52: 04090003 lb zero,64(s2) - 2a56: 0100 addi s0,sp,128 - 2a58: 0200 addi s0,sp,256 - 2a5a: 0a04 addi s1,sp,272 - 2a5c: 08090003 lb zero,128(s2) - 2a60: 0100 addi s0,sp,128 - 2a62: 0200 addi s0,sp,256 - 2a64: 0904 addi s1,sp,144 - 2a66: 04090003 lb zero,64(s2) - 2a6a: 0100 addi s0,sp,128 - 2a6c: 0200 addi s0,sp,256 - 2a6e: 1804 addi s1,sp,48 - 2a70: 08090003 lb zero,128(s2) - 2a74: 0100 addi s0,sp,128 - 2a76: 0200 addi s0,sp,256 - 2a78: 1804 addi s1,sp,48 - 2a7a: 0c090003 lb zero,192(s2) - 2a7e: 0100 addi s0,sp,128 - 2a80: 0200 addi s0,sp,256 - 2a82: 1a04 addi s1,sp,304 - 2a84: 04090003 lb zero,64(s2) - 2a88: 0100 addi s0,sp,128 - 2a8a: 0200 addi s0,sp,256 - 2a8c: 1a04 addi s1,sp,304 - 2a8e: 00090003 lb zero,0(s2) - 2a92: 0100 addi s0,sp,128 - 2a94: 0200 addi s0,sp,256 - 2a96: 1a04 addi s1,sp,304 - 2a98: 00090003 lb zero,0(s2) - 2a9c: 0100 addi s0,sp,128 - 2a9e: 0200 addi s0,sp,256 - 2aa0: 1a04 addi s1,sp,304 - 2aa2: 00090003 lb zero,0(s2) - 2aa6: 0100 addi s0,sp,128 - 2aa8: 0306 slli t1,t1,0x1 - 2aaa: 0900 addi s0,sp,144 - 2aac: 0008 0x8 - 2aae: 0001 nop - 2ab0: 0402 c.slli64 s0 - 2ab2: 0678 addi a4,sp,780 - 2ab4: 10090003 lb zero,256(s2) - 2ab8: 0100 addi s0,sp,128 - 2aba: 0200 addi s0,sp,256 - 2abc: 7804 flw fs1,48(s0) - 2abe: 00090003 lb zero,0(s2) - 2ac2: 0100 addi s0,sp,128 - 2ac4: 0200 addi s0,sp,256 - 2ac6: 7804 flw fs1,48(s0) - 2ac8: 00090003 lb zero,0(s2) - 2acc: 0100 addi s0,sp,128 - 2ace: 0200 addi s0,sp,256 - 2ad0: 7804 flw fs1,48(s0) - 2ad2: 00090003 lb zero,0(s2) - 2ad6: 0100 addi s0,sp,128 - 2ad8: 0200 addi s0,sp,256 - 2ada: 7804 flw fs1,48(s0) - 2adc: 00090003 lb zero,0(s2) - 2ae0: 0100 addi s0,sp,128 - 2ae2: 0200 addi s0,sp,256 - 2ae4: 7804 flw fs1,48(s0) - 2ae6: 00090003 lb zero,0(s2) - 2aea: 0100 addi s0,sp,128 - 2aec: 0200 addi s0,sp,256 - 2aee: 7804 flw fs1,48(s0) - 2af0: 00090003 lb zero,0(s2) - 2af4: 0100 addi s0,sp,128 - 2af6: 0200 addi s0,sp,256 - 2af8: 7804 flw fs1,48(s0) - 2afa: 1c090103 lb sp,448(s2) - 2afe: 0100 addi s0,sp,128 - 2b00: 0200 addi s0,sp,256 - 2b02: 7804 flw fs1,48(s0) - 2b04: 00090003 lb zero,0(s2) - 2b08: 0100 addi s0,sp,128 - 2b0a: 0200 addi s0,sp,256 - 2b0c: 7804 flw fs1,48(s0) - 2b0e: 00090203 lb tp,0(s2) - 2b12: 0100 addi s0,sp,128 - 2b14: 0105 addi sp,sp,1 - 2b16: 0200 addi s0,sp,256 - 2b18: 7804 flw fs1,48(s0) - 2b1a: 0306 slli t1,t1,0x1 - 2b1c: 0901 addi s2,s2,0 - 2b1e: 0000 unimp - 2b20: 0501 addi a0,a0,0 - 2b22: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> - 2b26: 09790307 vlsbu.v v6,(s2),s7,v0.t - 2b2a: 0034 addi a3,sp,8 - 2b2c: 0001 nop - 2b2e: 0402 c.slli64 s0 - 2b30: 02030607 vlbu.v v12,(t1) - 2b34: 0409 addi s0,s0,2 - 2b36: 0100 addi s0,sp,128 - 2b38: 0c090103 lb sp,192(s2) - 2b3c: 0100 addi s0,sp,128 - 2b3e: 00090003 lb zero,0(s2) - 2b42: 0100 addi s0,sp,128 - 2b44: 00090003 lb zero,0(s2) - 2b48: 0100 addi s0,sp,128 - 2b4a: 0200 addi s0,sp,256 - 2b4c: 0404 addi s1,sp,512 - 2b4e: 0306 slli t1,t1,0x1 - 2b50: 097e slli s2,s2,0x1f - 2b52: 0024 addi s1,sp,8 - 2b54: 0001 nop - 2b56: 0402 c.slli64 s0 - 2b58: 0604 addi s1,sp,768 - 2b5a: 04090103 lb sp,64(s2) - 2b5e: 0100 addi s0,sp,128 - 2b60: 0306 slli t1,t1,0x1 - 2b62: 0900 addi s0,sp,144 - 2b64: 0004 0x4 - 2b66: 0001 nop - 2b68: 0402 c.slli64 s0 - 2b6a: 0103063b 0x103063b - 2b6e: 0809 addi a6,a6,2 - 2b70: 0100 addi s0,sp,128 - 2b72: 0200 addi s0,sp,256 - 2b74: 3b04 fld fs1,48(a4) - 2b76: 00090003 lb zero,0(s2) - 2b7a: 0100 addi s0,sp,128 - 2b7c: 0200 addi s0,sp,256 - 2b7e: 3b04 fld fs1,48(a4) - 2b80: 00090003 lb zero,0(s2) - 2b84: 0100 addi s0,sp,128 - 2b86: 0200 addi s0,sp,256 - 2b88: 3b04 fld fs1,48(a4) - 2b8a: 08090003 lb zero,128(s2) - 2b8e: 0100 addi s0,sp,128 - 2b90: 0200 addi s0,sp,256 - 2b92: 3c04 fld fs1,56(s0) - 2b94: 08090003 lb zero,128(s2) - 2b98: 0100 addi s0,sp,128 - 2b9a: 0200 addi s0,sp,256 - 2b9c: 3e04 fld fs1,56(a2) - 2b9e: 08090003 lb zero,128(s2) - 2ba2: 0100 addi s0,sp,128 - 2ba4: 0200 addi s0,sp,256 - 2ba6: 3e04 fld fs1,56(a2) - 2ba8: 1c090003 lb zero,448(s2) - 2bac: 0100 addi s0,sp,128 - 2bae: 0200 addi s0,sp,256 - 2bb0: 4b04 lw s1,16(a4) - 2bb2: 04090003 lb zero,64(s2) - 2bb6: 0100 addi s0,sp,128 - 2bb8: 0200 addi s0,sp,256 - 2bba: 4b04 lw s1,16(a4) - 2bbc: 00090003 lb zero,0(s2) - 2bc0: 0100 addi s0,sp,128 - 2bc2: 0200 addi s0,sp,256 - 2bc4: 4c04 lw s1,24(s0) - 2bc6: 08090003 lb zero,128(s2) - 2bca: 0100 addi s0,sp,128 - 2bcc: 0200 addi s0,sp,256 - 2bce: 4c04 lw s1,24(s0) - 2bd0: 00090003 lb zero,0(s2) - 2bd4: 0100 addi s0,sp,128 - 2bd6: 0200 addi s0,sp,256 - 2bd8: 4c04 lw s1,24(s0) - 2bda: 00090003 lb zero,0(s2) - 2bde: 0100 addi s0,sp,128 - 2be0: 0200 addi s0,sp,256 - 2be2: 4c04 lw s1,24(s0) - 2be4: 00090003 lb zero,0(s2) - 2be8: 0100 addi s0,sp,128 - 2bea: 0200 addi s0,sp,256 - 2bec: 4e04 lw s1,24(a2) - 2bee: 0c090003 lb zero,192(s2) - 2bf2: 0100 addi s0,sp,128 - 2bf4: 0200 addi s0,sp,256 - 2bf6: 4e04 lw s1,24(a2) - 2bf8: 00090003 lb zero,0(s2) - 2bfc: 0100 addi s0,sp,128 - 2bfe: 0200 addi s0,sp,256 - 2c00: 4e04 lw s1,24(a2) - 2c02: 00090003 lb zero,0(s2) - 2c06: 0100 addi s0,sp,128 - 2c08: 0200 addi s0,sp,256 - 2c0a: 4e04 lw s1,24(a2) - 2c0c: 04090003 lb zero,64(s2) - 2c10: 0100 addi s0,sp,128 - 2c12: 0200 addi s0,sp,256 - 2c14: 4e04 lw s1,24(a2) - 2c16: 08090003 lb zero,128(s2) - 2c1a: 0100 addi s0,sp,128 - 2c1c: 0200 addi s0,sp,256 - 2c1e: 4d04 lw s1,24(a0) - 2c20: 04090003 lb zero,64(s2) - 2c24: 0100 addi s0,sp,128 - 2c26: 0200 addi s0,sp,256 - 2c28: 5d04 lw s1,56(a0) - 2c2a: 08090003 lb zero,128(s2) - 2c2e: 0100 addi s0,sp,128 - 2c30: 0200 addi s0,sp,256 - 2c32: 5d04 lw s1,56(a0) - 2c34: 00090003 lb zero,0(s2) - 2c38: 0100 addi s0,sp,128 - 2c3a: 0200 addi s0,sp,256 - 2c3c: 5d04 lw s1,56(a0) - 2c3e: 00090003 lb zero,0(s2) - 2c42: 0100 addi s0,sp,128 - 2c44: 0200 addi s0,sp,256 - 2c46: 5d04 lw s1,56(a0) - 2c48: 0c090003 lb zero,192(s2) - 2c4c: 0100 addi s0,sp,128 - 2c4e: 0306 slli t1,t1,0x1 - 2c50: 0900 addi s0,sp,144 - 2c52: 0004 0x4 - 2c54: 0001 nop - 2c56: 0402 c.slli64 s0 - 2c58: 0003063f 01000809 0x10008090003063f - 2c60: 0200 addi s0,sp,256 - 2c62: 4704 lw s1,8(a4) - 2c64: 0306 slli t1,t1,0x1 - 2c66: 0900 addi s0,sp,144 - 2c68: 0018 0x18 - 2c6a: 0001 nop - 2c6c: 0402 c.slli64 s0 - 2c6e: 034a slli t1,t1,0x12 - 2c70: 0900 addi s0,sp,144 - 2c72: 0008 0x8 - 2c74: 0001 nop - 2c76: 0402 c.slli64 s0 - 2c78: 064a slli a2,a2,0x12 - 2c7a: 0c090003 lb zero,192(s2) - 2c7e: 0100 addi s0,sp,128 - 2c80: 0306 slli t1,t1,0x1 - 2c82: 0900 addi s0,sp,144 - 2c84: 0008 0x8 - 2c86: 0901 addi s2,s2,0 - 2c88: 0034 addi a3,sp,8 - 2c8a: 0100 addi s0,sp,128 - 2c8c: a201 j 2d8c <_start-0x7fffd274> - 2c8e: 0002 c.slli64 zero - 2c90: 0300 addi s0,sp,384 - 2c92: a300 fsd fs0,0(a4) - 2c94: 0000 unimp - 2c96: 0100 addi s0,sp,128 - 2c98: fb01 bnez a4,2ba8 <_start-0x7fffd458> - 2c9a: 0d0e slli s10,s10,0x3 - 2c9c: 0100 addi s0,sp,128 - 2c9e: 0101 addi sp,sp,0 - 2ca0: 0001 nop - 2ca2: 0000 unimp - 2ca4: 0001 nop - 2ca6: 0100 addi s0,sp,128 - 2ca8: 2e2e fld ft8,200(sp) - 2caa: 2f2e2e2f 0x2f2e2e2f - 2cae: 2e2e fld ft8,200(sp) - 2cb0: 2f2e2e2f 0x2f2e2e2f - 2cb4: 6972 flw fs2,28(sp) - 2cb6: 2d766373 csrrsi t1,0x2d7,12 - 2cba: 2f636367 0x2f636367 - 2cbe: 696c flw fa1,84(a0) - 2cc0: 6762 flw fa4,24(sp) - 2cc2: 732f6363 bltu t5,s2,33e8 <_start-0x7fffcc18> - 2cc6: 2d74666f jal a2,4979c <_start-0x7ffb6864> - 2cca: 7066 flw ft0,120(sp) - 2ccc: 2e00 fld fs0,24(a2) - 2cce: 2e00 fld fs0,24(a2) - 2cd0: 2f2e fld ft10,200(sp) - 2cd2: 2e2e fld ft8,200(sp) - 2cd4: 2f2e2e2f 0x2f2e2e2f - 2cd8: 2e2e fld ft8,200(sp) - 2cda: 7369722f 0x7369722f - 2cde: 672d7663 bgeu s10,s2,334a <_start-0x7fffccb6> - 2ce2: 6c2f6363 bltu t5,sp,33a8 <_start-0x7fffcc58> - 2ce6: 6269 lui tp,0x1a - 2ce8: 2f636367 0x2f636367 - 2cec: 2e2e fld ft8,200(sp) - 2cee: 636e692f vamoandw.v zero,v22,(t3),v18 - 2cf2: 756c flw fa1,108(a0) - 2cf4: 6564 flw fs1,76(a0) - 2cf6: 0000 unimp - 2cf8: 7165 addi sp,sp,-400 - 2cfa: 6674 flw fa3,76(a2) - 2cfc: 2e32 fld ft8,264(sp) - 2cfe: 00010063 beqz sp,2cfe <_start-0x7fffd302> - 2d02: 7300 flw fs0,32(a4) - 2d04: 7066 flw ft0,120(sp) - 2d06: 6d2d lui s10,0xb - 2d08: 6361 lui t1,0x18 - 2d0a: 6968 flw fa0,84(a0) - 2d0c: 656e flw fa0,216(sp) - 2d0e: 682e flw fa6,200(sp) - 2d10: 0200 addi s0,sp,256 - 2d12: 0000 unimp - 2d14: 74666f73 csrrsi t5,0x746,12 - 2d18: 662d lui a2,0xb - 2d1a: 2e70 fld fa2,216(a2) - 2d1c: 0068 addi a0,sp,12 - 2d1e: 0001 nop - 2d20: 7100 flw fs0,32(a0) - 2d22: 6175 addi sp,sp,368 - 2d24: 2e64 fld fs1,216(a2) - 2d26: 0068 addi a0,sp,12 - 2d28: 0001 nop - 2d2a: 6c00 flw fs0,24(s0) - 2d2c: 6c676e6f jal t3,793f2 <_start-0x7ff86c0e> - 2d30: 2e676e6f jal t3,79016 <_start-0x7ff86fea> - 2d34: 0068 addi a0,sp,12 - 2d36: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> - 2d3a: 0105 addi sp,sp,1 - 2d3c: 0500 addi s0,sp,640 - 2d3e: 6802 flw fa6,0(sp) - 2d40: 0114 addi a3,sp,128 - 2d42: 0380 addi s0,sp,448 - 2d44: 03050123 sb a6,34(a0) - 2d48: 00090103 lb sp,0(s2) - 2d4c: 0100 addi s0,sp,128 - 2d4e: 00090003 lb zero,0(s2) - 2d52: 0100 addi s0,sp,128 - 2d54: 0d05 addi s10,s10,1 - 2d56: 00090003 lb zero,0(s2) - 2d5a: 0100 addi s0,sp,128 - 2d5c: 0305 addi t1,t1,1 - 2d5e: 00090103 lb sp,0(s2) - 2d62: 0100 addi s0,sp,128 - 2d64: 00090003 lb zero,0(s2) - 2d68: 0100 addi s0,sp,128 - 2d6a: 00090003 lb zero,0(s2) - 2d6e: 0100 addi s0,sp,128 - 2d70: 00090003 lb zero,0(s2) - 2d74: 0100 addi s0,sp,128 - 2d76: 00090103 lb sp,0(s2) - 2d7a: 0100 addi s0,sp,128 - 2d7c: 00090003 lb zero,0(s2) - 2d80: 0100 addi s0,sp,128 - 2d82: 00090003 lb zero,0(s2) - 2d86: 0100 addi s0,sp,128 - 2d88: 00090003 lb zero,0(s2) - 2d8c: 0100 addi s0,sp,128 - 2d8e: 00090103 lb sp,0(s2) - 2d92: 0100 addi s0,sp,128 - 2d94: 00090203 lb tp,0(s2) - 2d98: 0100 addi s0,sp,128 - 2d9a: 00090103 lb sp,0(s2) - 2d9e: 0100 addi s0,sp,128 - 2da0: 00090003 lb zero,0(s2) - 2da4: 0100 addi s0,sp,128 - 2da6: 00090003 lb zero,0(s2) - 2daa: 0100 addi s0,sp,128 - 2dac: 00090003 lb zero,0(s2) - 2db0: 0100 addi s0,sp,128 - 2db2: 0105 addi sp,sp,1 - 2db4: 0306 slli t1,t1,0x1 - 2db6: 0979 addi s2,s2,30 - 2db8: 0000 unimp - 2dba: 0501 addi a0,a0,0 - 2dbc: 09070303 lb t1,144(a4) # 1a090 <_start-0x7ffe5f70> - 2dc0: 0014 0x14 - 2dc2: 0301 addi t1,t1,0 - 2dc4: 0901 addi s2,s2,0 - 2dc6: 0010 0x10 - 2dc8: 0301 addi t1,t1,0 - 2dca: 097f 0x97f - 2dcc: 0004 0x4 - 2dce: 0301 addi t1,t1,0 - 2dd0: 0901 addi s2,s2,0 - 2dd2: 0008 0x8 - 2dd4: 0501 addi a0,a0,0 - 2dd6: 0301 addi t1,t1,0 - 2dd8: 0978 addi a4,sp,156 - 2dda: 0004 0x4 - 2ddc: 0301 addi t1,t1,0 - 2dde: 0900 addi s0,sp,144 - 2de0: 0004 0x4 - 2de2: 0501 addi a0,a0,0 - 2de4: 07030603 lb a2,112(t1) # 18070 <_start-0x7ffe7f90> - 2de8: 0409 addi s0,s0,2 - 2dea: 0100 addi s0,sp,128 - 2dec: 0105 addi sp,sp,1 - 2dee: 0306 slli t1,t1,0x1 - 2df0: 0979 addi s2,s2,30 - 2df2: 0000 unimp - 2df4: 0501 addi a0,a0,0 - 2df6: 07030603 lb a2,112(t1) - 2dfa: 0409 addi s0,s0,2 - 2dfc: 0100 addi s0,sp,128 - 2dfe: 0105 addi sp,sp,1 - 2e00: 0306 slli t1,t1,0x1 - 2e02: 0979 addi s2,s2,30 - 2e04: 0000 unimp - 2e06: 0501 addi a0,a0,0 - 2e08: 07030603 lb a2,112(t1) - 2e0c: 0409 addi s0,s0,2 - 2e0e: 0100 addi s0,sp,128 - 2e10: 04090003 lb zero,64(s2) - 2e14: 0100 addi s0,sp,128 - 2e16: 00090003 lb zero,0(s2) - 2e1a: 0100 addi s0,sp,128 - 2e1c: 00090103 lb sp,0(s2) - 2e20: 0100 addi s0,sp,128 - 2e22: 00090003 lb zero,0(s2) - 2e26: 0100 addi s0,sp,128 - 2e28: 00090003 lb zero,0(s2) - 2e2c: 0100 addi s0,sp,128 - 2e2e: 00090003 lb zero,0(s2) - 2e32: 0100 addi s0,sp,128 - 2e34: 00090003 lb zero,0(s2) - 2e38: 0100 addi s0,sp,128 - 2e3a: 00090003 lb zero,0(s2) - 2e3e: 0100 addi s0,sp,128 - 2e40: 00090003 lb zero,0(s2) - 2e44: 0100 addi s0,sp,128 - 2e46: 04090003 lb zero,64(s2) - 2e4a: 0100 addi s0,sp,128 - 2e4c: 04090003 lb zero,64(s2) - 2e50: 0100 addi s0,sp,128 - 2e52: 04090103 lb sp,64(s2) - 2e56: 0100 addi s0,sp,128 - 2e58: 00090003 lb zero,0(s2) - 2e5c: 0100 addi s0,sp,128 - 2e5e: 00090003 lb zero,0(s2) - 2e62: 0100 addi s0,sp,128 - 2e64: 00090003 lb zero,0(s2) - 2e68: 0100 addi s0,sp,128 - 2e6a: 0200 addi s0,sp,256 - 2e6c: 1204 addi s1,sp,288 - 2e6e: 0306 slli t1,t1,0x1 - 2e70: 0900 addi s0,sp,144 - 2e72: 0004 0x4 - 2e74: 0301 addi t1,t1,0 - 2e76: 0900 addi s0,sp,144 - 2e78: 0014 0x14 - 2e7a: 0001 nop - 2e7c: 0402 c.slli64 s0 - 2e7e: 0315 addi t1,t1,5 - 2e80: 0900 addi s0,sp,144 - 2e82: 0008 0x8 - 2e84: 0001 nop - 2e86: 0402 c.slli64 s0 - 2e88: 0316 slli t1,t1,0x5 - 2e8a: 0900 addi s0,sp,144 - 2e8c: 0004 0x4 - 2e8e: 0001 nop - 2e90: 0402 c.slli64 s0 - 2e92: 0649 addi a2,a2,18 - 2e94: 14090003 lb zero,320(s2) - 2e98: 0100 addi s0,sp,128 - 2e9a: 0200 addi s0,sp,256 - 2e9c: 4904 lw s1,16(a0) - 2e9e: 00090003 lb zero,0(s2) - 2ea2: 0100 addi s0,sp,128 - 2ea4: 0200 addi s0,sp,256 - 2ea6: 4904 lw s1,16(a0) - 2ea8: 00090003 lb zero,0(s2) - 2eac: 0100 addi s0,sp,128 - 2eae: 0200 addi s0,sp,256 - 2eb0: 4904 lw s1,16(a0) - 2eb2: 00090003 lb zero,0(s2) - 2eb6: 0100 addi s0,sp,128 - 2eb8: 0200 addi s0,sp,256 - 2eba: 4904 lw s1,16(a0) - 2ebc: 00090003 lb zero,0(s2) - 2ec0: 0100 addi s0,sp,128 - 2ec2: 0200 addi s0,sp,256 - 2ec4: 4904 lw s1,16(a0) - 2ec6: 00090003 lb zero,0(s2) - 2eca: 0100 addi s0,sp,128 - 2ecc: 0200 addi s0,sp,256 - 2ece: 4904 lw s1,16(a0) - 2ed0: 00090003 lb zero,0(s2) - 2ed4: 0100 addi s0,sp,128 - 2ed6: 0200 addi s0,sp,256 - 2ed8: 4b04 lw s1,16(a4) - 2eda: 0306 slli t1,t1,0x1 - 2edc: 0900 addi s0,sp,144 - 2ede: 0008 0x8 - 2ee0: 0001 nop - 2ee2: 0402 c.slli64 s0 - 2ee4: 034d addi t1,t1,19 - 2ee6: 0900 addi s0,sp,144 - 2ee8: 0004 0x4 - 2eea: 0001 nop - 2eec: 0402 c.slli64 s0 - 2eee: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 2ef2: 0004 0x4 - 2ef4: 0001 nop - 2ef6: 0402 c.slli64 s0 - 2ef8: 0351 addi t1,t1,20 - 2efa: 0900 addi s0,sp,144 - 2efc: 0004 0x4 - 2efe: 0001 nop - 2f00: 0402 c.slli64 s0 - 2f02: 09000353 fsub.s ft6,ft0,fa6,rne - 2f06: 0004 0x4 - 2f08: 0001 nop - 2f0a: 0402 c.slli64 s0 - 2f0c: 0354 addi a3,sp,388 - 2f0e: 0900 addi s0,sp,144 - 2f10: 0004 0x4 - 2f12: 0001 nop - 2f14: 0402 c.slli64 s0 - 2f16: 09000357 vsub.vv v6,v16,v0,v0.t - 2f1a: 0004 0x4 - 2f1c: 0501 addi a0,a0,0 - 2f1e: 0301 addi t1,t1,0 - 2f20: 0904 addi s1,sp,144 - 2f22: 0010 0x10 - 2f24: 0501 addi a0,a0,0 - 2f26: 097c0303 lb t1,151(s8) - 2f2a: 0008 0x8 - 2f2c: 0901 addi s2,s2,0 - 2f2e: 0008 0x8 - 2f30: 0100 addi s0,sp,128 - 2f32: 8901 andi a0,a0,0 - 2f34: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 2f38: a300 fsd fs0,0(a4) - 2f3a: 0000 unimp - 2f3c: 0100 addi s0,sp,128 - 2f3e: fb01 bnez a4,2e4e <_start-0x7fffd1b2> - 2f40: 0d0e slli s10,s10,0x3 - 2f42: 0100 addi s0,sp,128 - 2f44: 0101 addi sp,sp,0 - 2f46: 0001 nop - 2f48: 0000 unimp - 2f4a: 0001 nop - 2f4c: 0100 addi s0,sp,128 - 2f4e: 2e2e fld ft8,200(sp) - 2f50: 2f2e2e2f 0x2f2e2e2f - 2f54: 2e2e fld ft8,200(sp) - 2f56: 2f2e2e2f 0x2f2e2e2f - 2f5a: 6972 flw fs2,28(sp) - 2f5c: 2d766373 csrrsi t1,0x2d7,12 - 2f60: 2f636367 0x2f636367 - 2f64: 696c flw fa1,84(a0) - 2f66: 6762 flw fa4,24(sp) - 2f68: 732f6363 bltu t5,s2,368e <_start-0x7fffc972> - 2f6c: 2d74666f jal a2,49a42 <_start-0x7ffb65be> - 2f70: 7066 flw ft0,120(sp) - 2f72: 2e00 fld fs0,24(a2) - 2f74: 2e00 fld fs0,24(a2) - 2f76: 2f2e fld ft10,200(sp) - 2f78: 2e2e fld ft8,200(sp) - 2f7a: 2f2e2e2f 0x2f2e2e2f - 2f7e: 2e2e fld ft8,200(sp) - 2f80: 7369722f 0x7369722f - 2f84: 672d7663 bgeu s10,s2,35f0 <_start-0x7fffca10> - 2f88: 6c2f6363 bltu t5,sp,364e <_start-0x7fffc9b2> - 2f8c: 6269 lui tp,0x1a - 2f8e: 2f636367 0x2f636367 - 2f92: 2e2e fld ft8,200(sp) - 2f94: 636e692f vamoandw.v zero,v22,(t3),v18 - 2f98: 756c flw fa1,108(a0) - 2f9a: 6564 flw fs1,76(a0) - 2f9c: 0000 unimp - 2f9e: 66746567 0x66746567 - 2fa2: 2e32 fld ft8,264(sp) - 2fa4: 00010063 beqz sp,2fa4 <_start-0x7fffd05c> - 2fa8: 7300 flw fs0,32(a4) - 2faa: 7066 flw ft0,120(sp) - 2fac: 6d2d lui s10,0xb - 2fae: 6361 lui t1,0x18 - 2fb0: 6968 flw fa0,84(a0) - 2fb2: 656e flw fa0,216(sp) - 2fb4: 682e flw fa6,200(sp) - 2fb6: 0200 addi s0,sp,256 - 2fb8: 0000 unimp - 2fba: 74666f73 csrrsi t5,0x746,12 - 2fbe: 662d lui a2,0xb - 2fc0: 2e70 fld fa2,216(a2) - 2fc2: 0068 addi a0,sp,12 - 2fc4: 0001 nop - 2fc6: 7100 flw fs0,32(a0) - 2fc8: 6175 addi sp,sp,368 - 2fca: 2e64 fld fs1,216(a2) - 2fcc: 0068 addi a0,sp,12 - 2fce: 0001 nop - 2fd0: 6c00 flw fs0,24(s0) - 2fd2: 6c676e6f jal t3,79698 <_start-0x7ff86968> - 2fd6: 2e676e6f jal t3,792bc <_start-0x7ff86d44> - 2fda: 0068 addi a0,sp,12 - 2fdc: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> - 2fe0: 0105 addi sp,sp,1 - 2fe2: 0500 addi s0,sp,640 - 2fe4: 3402 fld fs0,32(sp) - 2fe6: 0115 addi sp,sp,5 - 2fe8: 0380 addi s0,sp,448 - 2fea: 03050123 sb a6,34(a0) - 2fee: 00090103 lb sp,0(s2) - 2ff2: 0100 addi s0,sp,128 - 2ff4: 00090003 lb zero,0(s2) - 2ff8: 0100 addi s0,sp,128 - 2ffa: 0d05 addi s10,s10,1 - 2ffc: 00090003 lb zero,0(s2) - 3000: 0100 addi s0,sp,128 - 3002: 0305 addi t1,t1,1 - 3004: 00090103 lb sp,0(s2) - 3008: 0100 addi s0,sp,128 - 300a: 00090003 lb zero,0(s2) - 300e: 0100 addi s0,sp,128 - 3010: 00090003 lb zero,0(s2) - 3014: 0100 addi s0,sp,128 - 3016: 00090003 lb zero,0(s2) - 301a: 0100 addi s0,sp,128 - 301c: 00090103 lb sp,0(s2) - 3020: 0100 addi s0,sp,128 - 3022: 00090003 lb zero,0(s2) - 3026: 0100 addi s0,sp,128 - 3028: 00090003 lb zero,0(s2) - 302c: 0100 addi s0,sp,128 - 302e: 00090003 lb zero,0(s2) - 3032: 0100 addi s0,sp,128 - 3034: 00090103 lb sp,0(s2) - 3038: 0100 addi s0,sp,128 - 303a: 00090203 lb tp,0(s2) - 303e: 0100 addi s0,sp,128 - 3040: 00090103 lb sp,0(s2) - 3044: 0100 addi s0,sp,128 - 3046: 00090003 lb zero,0(s2) - 304a: 0100 addi s0,sp,128 - 304c: 00090003 lb zero,0(s2) - 3050: 0100 addi s0,sp,128 - 3052: 00090003 lb zero,0(s2) - 3056: 0100 addi s0,sp,128 - 3058: 0105 addi sp,sp,1 - 305a: 0306 slli t1,t1,0x1 - 305c: 0979 addi s2,s2,30 - 305e: 0000 unimp - 3060: 0501 addi a0,a0,0 - 3062: 07030603 lb a2,112(t1) # 18070 <_start-0x7ffe7f90> - 3066: 0409 addi s0,s0,2 - 3068: 0100 addi s0,sp,128 - 306a: 0105 addi sp,sp,1 - 306c: 0306 slli t1,t1,0x1 - 306e: 0979 addi s2,s2,30 - 3070: 0000 unimp - 3072: 0501 addi a0,a0,0 - 3074: 07030603 lb a2,112(t1) - 3078: 0409 addi s0,s0,2 - 307a: 0100 addi s0,sp,128 - 307c: 0105 addi sp,sp,1 - 307e: 0306 slli t1,t1,0x1 - 3080: 0979 addi s2,s2,30 - 3082: 0000 unimp - 3084: 0501 addi a0,a0,0 - 3086: 07030603 lb a2,112(t1) - 308a: 0409 addi s0,s0,2 - 308c: 0100 addi s0,sp,128 - 308e: 0105 addi sp,sp,1 - 3090: 0306 slli t1,t1,0x1 - 3092: 0979 addi s2,s2,30 - 3094: 0000 unimp - 3096: 0501 addi a0,a0,0 - 3098: 09070303 lb t1,144(a4) - 309c: 0008 0x8 - 309e: 0301 addi t1,t1,0 - 30a0: 0901 addi s2,s2,0 - 30a2: 000c 0xc - 30a4: 0501 addi a0,a0,0 - 30a6: 0301 addi t1,t1,0 - 30a8: 0978 addi a4,sp,156 - 30aa: 0008 0x8 - 30ac: 0501 addi a0,a0,0 - 30ae: 09070303 lb t1,144(a4) - 30b2: 000c 0xc - 30b4: 0501 addi a0,a0,0 - 30b6: 0301 addi t1,t1,0 - 30b8: 0979 addi s2,s2,30 - 30ba: 0008 0x8 - 30bc: 0501 addi a0,a0,0 - 30be: 09070303 lb t1,144(a4) - 30c2: 0004 0x4 - 30c4: 0601 addi a2,a2,0 - 30c6: 04090003 lb zero,64(s2) - 30ca: 0100 addi s0,sp,128 - 30cc: 00090003 lb zero,0(s2) - 30d0: 0100 addi s0,sp,128 - 30d2: 04090103 lb sp,64(s2) - 30d6: 0100 addi s0,sp,128 - 30d8: 00090003 lb zero,0(s2) - 30dc: 0100 addi s0,sp,128 - 30de: 00090003 lb zero,0(s2) - 30e2: 0100 addi s0,sp,128 - 30e4: 00090003 lb zero,0(s2) - 30e8: 0100 addi s0,sp,128 - 30ea: 00090003 lb zero,0(s2) - 30ee: 0100 addi s0,sp,128 - 30f0: 00090003 lb zero,0(s2) - 30f4: 0100 addi s0,sp,128 - 30f6: 00090003 lb zero,0(s2) - 30fa: 0100 addi s0,sp,128 - 30fc: 04090003 lb zero,64(s2) - 3100: 0100 addi s0,sp,128 - 3102: 04090003 lb zero,64(s2) - 3106: 0100 addi s0,sp,128 - 3108: 04090103 lb sp,64(s2) - 310c: 0100 addi s0,sp,128 - 310e: 00090003 lb zero,0(s2) - 3112: 0100 addi s0,sp,128 - 3114: 00090003 lb zero,0(s2) - 3118: 0100 addi s0,sp,128 - 311a: 00090003 lb zero,0(s2) - 311e: 0100 addi s0,sp,128 - 3120: 0200 addi s0,sp,256 - 3122: 1204 addi s1,sp,288 - 3124: 0306 slli t1,t1,0x1 - 3126: 0900 addi s0,sp,144 - 3128: 0004 0x4 - 312a: 0301 addi t1,t1,0 - 312c: 0900 addi s0,sp,144 - 312e: 0010 0x10 - 3130: 0001 nop - 3132: 0402 c.slli64 s0 - 3134: 0315 addi t1,t1,5 - 3136: 0900 addi s0,sp,144 - 3138: 0008 0x8 - 313a: 0001 nop - 313c: 0402 c.slli64 s0 - 313e: 0316 slli t1,t1,0x5 - 3140: 0900 addi s0,sp,144 - 3142: 0004 0x4 - 3144: 0001 nop - 3146: 0402 c.slli64 s0 - 3148: 0639 addi a2,a2,14 - 314a: 10090003 lb zero,256(s2) - 314e: 0100 addi s0,sp,128 - 3150: 0200 addi s0,sp,256 - 3152: 3904 fld fs1,48(a0) - 3154: 00090003 lb zero,0(s2) - 3158: 0100 addi s0,sp,128 - 315a: 0200 addi s0,sp,256 - 315c: 3904 fld fs1,48(a0) - 315e: 00090003 lb zero,0(s2) - 3162: 0100 addi s0,sp,128 - 3164: 0200 addi s0,sp,256 - 3166: 3904 fld fs1,48(a0) - 3168: 00090003 lb zero,0(s2) - 316c: 0100 addi s0,sp,128 - 316e: 0200 addi s0,sp,256 - 3170: 3904 fld fs1,48(a0) - 3172: 00090003 lb zero,0(s2) - 3176: 0100 addi s0,sp,128 - 3178: 0200 addi s0,sp,256 - 317a: 3904 fld fs1,48(a0) - 317c: 00090003 lb zero,0(s2) - 3180: 0100 addi s0,sp,128 - 3182: 0200 addi s0,sp,256 - 3184: 3904 fld fs1,48(a0) - 3186: 00090003 lb zero,0(s2) - 318a: 0100 addi s0,sp,128 - 318c: 0200 addi s0,sp,256 - 318e: 3904 fld fs1,48(a0) - 3190: 00090003 lb zero,0(s2) - 3194: 0100 addi s0,sp,128 - 3196: 0200 addi s0,sp,256 - 3198: 3904 fld fs1,48(a0) - 319a: 00090003 lb zero,0(s2) - 319e: 0100 addi s0,sp,128 - 31a0: 0200 addi s0,sp,256 - 31a2: 3a04 fld fs1,48(a2) - 31a4: 0306 slli t1,t1,0x1 - 31a6: 0900 addi s0,sp,144 - 31a8: 0004 0x4 - 31aa: 0001 nop - 31ac: 0402 c.slli64 s0 - 31ae: 063a slli a2,a2,0xe - 31b0: 10090003 lb zero,256(s2) - 31b4: 0100 addi s0,sp,128 - 31b6: 0200 addi s0,sp,256 - 31b8: 4004 lw s1,0(s0) - 31ba: 0306 slli t1,t1,0x1 - 31bc: 0900 addi s0,sp,144 - 31be: 0004 0x4 - 31c0: 0601 addi a2,a2,0 - 31c2: 10090003 lb zero,256(s2) - 31c6: 0100 addi s0,sp,128 - 31c8: 04090003 lb zero,64(s2) - 31cc: 0100 addi s0,sp,128 - 31ce: 00090003 lb zero,0(s2) - 31d2: 0100 addi s0,sp,128 - 31d4: 00090003 lb zero,0(s2) - 31d8: 0100 addi s0,sp,128 - 31da: 0200 addi s0,sp,256 - 31dc: 7404 flw fs1,40(s0) - 31de: 04090003 lb zero,64(s2) - 31e2: 0100 addi s0,sp,128 - 31e4: 0306 slli t1,t1,0x1 - 31e6: 0900 addi s0,sp,144 - 31e8: 0004 0x4 - 31ea: 0001 nop - 31ec: 0402 c.slli64 s0 - 31ee: 064a slli a2,a2,0x12 - 31f0: 08090003 lb zero,128(s2) - 31f4: 0100 addi s0,sp,128 - 31f6: 0200 addi s0,sp,256 - 31f8: 4a04 lw s1,16(a2) - 31fa: 00090003 lb zero,0(s2) - 31fe: 0100 addi s0,sp,128 - 3200: 0306 slli t1,t1,0x1 - 3202: 0900 addi s0,sp,144 - 3204: 0008 0x8 - 3206: 0501 addi a0,a0,0 - 3208: 0301 addi t1,t1,0 - 320a: 0904 addi s1,sp,144 - 320c: 0004 0x4 - 320e: 0501 addi a0,a0,0 - 3210: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> - 3214: 7c030657 0x7c030657 - 3218: 0809 addi a6,a6,2 - 321a: 0100 addi s0,sp,128 - 321c: 0200 addi s0,sp,256 - 321e: 5d04 lw s1,56(a0) - 3220: 04090003 lb zero,64(s2) - 3224: 0100 addi s0,sp,128 - 3226: 0300 addi s0,sp,384 - 3228: 8604 0x8604 - 322a: 0301 addi t1,t1,0 - 322c: 0900 addi s0,sp,144 - 322e: 0004 0x4 - 3230: 0001 nop - 3232: 0402 c.slli64 s0 - 3234: 09000363 beq zero,a6,32ba <_start-0x7fffcd46> - 3238: 0008 0x8 - 323a: 0001 nop - 323c: 0402 c.slli64 s0 - 323e: 0669 addi a2,a2,26 - 3240: 04090003 lb zero,64(s2) - 3244: 0100 addi s0,sp,128 - 3246: 0200 addi s0,sp,256 - 3248: 6a04 flw fs1,16(a2) - 324a: 04090003 lb zero,64(s2) - 324e: 0100 addi s0,sp,128 - 3250: 0200 addi s0,sp,256 - 3252: 6d04 flw fs1,24(a0) - 3254: 04090003 lb zero,64(s2) - 3258: 0100 addi s0,sp,128 - 325a: 0200 addi s0,sp,256 - 325c: 6e04 flw fs1,24(a2) - 325e: 04090003 lb zero,64(s2) - 3262: 0100 addi s0,sp,128 - 3264: 0200 addi s0,sp,256 - 3266: 7104 flw fs1,32(a0) - 3268: 04090003 lb zero,64(s2) - 326c: 0100 addi s0,sp,128 - 326e: 0200 addi s0,sp,256 - 3270: 7204 flw fs1,32(a2) - 3272: 04090003 lb zero,64(s2) - 3276: 0100 addi s0,sp,128 - 3278: 0300 addi s0,sp,384 - 327a: 8004 0x8004 - 327c: 0601 addi a2,a2,0 - 327e: 04090003 lb zero,64(s2) - 3282: 0100 addi s0,sp,128 - 3284: 0300 addi s0,sp,384 - 3286: 8304 0x8304 - 3288: 0601 addi a2,a2,0 - 328a: 04090003 lb zero,64(s2) - 328e: 0100 addi s0,sp,128 - 3290: 0300 addi s0,sp,384 - 3292: 8404 0x8404 - 3294: 0301 addi t1,t1,0 - 3296: 0900 addi s0,sp,144 - 3298: 0004 0x4 - 329a: 0301 addi t1,t1,0 - 329c: 0900 addi s0,sp,144 - 329e: 0004 0x4 - 32a0: 0601 addi a2,a2,0 - 32a2: 10090003 lb zero,256(s2) - 32a6: 0100 addi s0,sp,128 - 32a8: 08090003 lb zero,128(s2) - 32ac: 0100 addi s0,sp,128 - 32ae: 08090003 lb zero,128(s2) - 32b2: 0100 addi s0,sp,128 - 32b4: 0c090003 lb zero,192(s2) - 32b8: 0100 addi s0,sp,128 - 32ba: 0c09 addi s8,s8,2 - 32bc: 0000 unimp - 32be: 0101 addi sp,sp,0 - 32c0: 0389 addi t2,t2,2 - 32c2: 0000 unimp - 32c4: 00a30003 lb zero,10(t1) - 32c8: 0000 unimp - 32ca: 0101 addi sp,sp,0 - 32cc: 000d0efb 0xd0efb - 32d0: 0101 addi sp,sp,0 - 32d2: 0101 addi sp,sp,0 - 32d4: 0000 unimp - 32d6: 0100 addi s0,sp,128 - 32d8: 0000 unimp - 32da: 2e01 jal 35ea <_start-0x7fffca16> - 32dc: 2f2e fld ft10,200(sp) - 32de: 2e2e fld ft8,200(sp) - 32e0: 2f2e2e2f 0x2f2e2e2f - 32e4: 2e2e fld ft8,200(sp) - 32e6: 7369722f 0x7369722f - 32ea: 672d7663 bgeu s10,s2,3956 <_start-0x7fffc6aa> - 32ee: 6c2f6363 bltu t5,sp,39b4 <_start-0x7fffc64c> - 32f2: 6269 lui tp,0x1a - 32f4: 2f636367 0x2f636367 - 32f8: 74666f73 csrrsi t5,0x746,12 - 32fc: 662d lui a2,0xb - 32fe: 0070 addi a2,sp,12 - 3300: 002e c.slli zero,0xb - 3302: 2e2e fld ft8,200(sp) - 3304: 2f2e2e2f 0x2f2e2e2f - 3308: 2e2e fld ft8,200(sp) - 330a: 2f2e2e2f 0x2f2e2e2f - 330e: 6972 flw fs2,28(sp) - 3310: 2d766373 csrrsi t1,0x2d7,12 - 3314: 2f636367 0x2f636367 - 3318: 696c flw fa1,84(a0) - 331a: 6762 flw fa4,24(sp) - 331c: 2e2f6363 bltu t5,sp,3602 <_start-0x7fffc9fe> - 3320: 2f2e fld ft10,200(sp) - 3322: 6e69 lui t3,0x1a - 3324: 64756c63 bltu a0,t2,397c <_start-0x7fffc684> - 3328: 0065 c.nop 25 - 332a: 6c00 flw fs0,24(s0) - 332c: 7465 lui s0,0xffff9 - 332e: 3266 fld ft4,120(sp) - 3330: 632e flw ft6,200(sp) - 3332: 0100 addi s0,sp,128 - 3334: 0000 unimp - 3336: 2d706673 csrrsi a2,0x2d7,0 - 333a: 616d addi sp,sp,240 - 333c: 6e696863 bltu s2,t1,3a2c <_start-0x7fffc5d4> - 3340: 2e65 jal 36f8 <_start-0x7fffc908> - 3342: 0068 addi a0,sp,12 - 3344: 0002 c.slli64 zero - 3346: 7300 flw fs0,32(a4) - 3348: 2d74666f jal a2,49e1e <_start-0x7ffb61e2> - 334c: 7066 flw ft0,120(sp) - 334e: 682e flw fa6,200(sp) - 3350: 0100 addi s0,sp,128 - 3352: 0000 unimp - 3354: 7571 lui a0,0xffffc - 3356: 6461 lui s0,0x18 - 3358: 682e flw fa6,200(sp) - 335a: 0100 addi s0,sp,128 - 335c: 0000 unimp - 335e: 6f6c flw fa1,92(a4) - 3360: 676e flw fa4,216(sp) - 3362: 6f6c flw fa1,92(a4) - 3364: 676e flw fa4,216(sp) - 3366: 682e flw fa6,200(sp) - 3368: 0300 addi s0,sp,384 - 336a: 0000 unimp - 336c: 0500 addi s0,sp,640 - 336e: 0001 nop - 3370: 0205 addi tp,tp,1 - 3372: 1678 addi a4,sp,812 - 3374: 8001 c.srli64 s0 - 3376: 05012303 lw t1,80(sp) - 337a: 09010303 lb t1,144(sp) - 337e: 0000 unimp - 3380: 0301 addi t1,t1,0 - 3382: 0900 addi s0,sp,144 - 3384: 0000 unimp - 3386: 0501 addi a0,a0,0 - 3388: 030d addi t1,t1,3 - 338a: 0900 addi s0,sp,144 - 338c: 0000 unimp - 338e: 0501 addi a0,a0,0 - 3390: 09010303 lb t1,144(sp) - 3394: 0000 unimp - 3396: 0301 addi t1,t1,0 - 3398: 0900 addi s0,sp,144 - 339a: 0000 unimp - 339c: 0301 addi t1,t1,0 - 339e: 0900 addi s0,sp,144 - 33a0: 0000 unimp - 33a2: 0301 addi t1,t1,0 - 33a4: 0900 addi s0,sp,144 - 33a6: 0000 unimp - 33a8: 0301 addi t1,t1,0 - 33aa: 0901 addi s2,s2,0 - 33ac: 0000 unimp - 33ae: 0301 addi t1,t1,0 - 33b0: 0900 addi s0,sp,144 - 33b2: 0000 unimp - 33b4: 0301 addi t1,t1,0 - 33b6: 0900 addi s0,sp,144 - 33b8: 0000 unimp - 33ba: 0301 addi t1,t1,0 - 33bc: 0900 addi s0,sp,144 - 33be: 0000 unimp - 33c0: 0301 addi t1,t1,0 - 33c2: 0901 addi s2,s2,0 - 33c4: 0000 unimp - 33c6: 0301 addi t1,t1,0 - 33c8: 0902 c.slli64 s2 - 33ca: 0000 unimp - 33cc: 0301 addi t1,t1,0 - 33ce: 0901 addi s2,s2,0 - 33d0: 0000 unimp - 33d2: 0301 addi t1,t1,0 - 33d4: 0900 addi s0,sp,144 - 33d6: 0000 unimp - 33d8: 0301 addi t1,t1,0 - 33da: 0900 addi s0,sp,144 - 33dc: 0000 unimp - 33de: 0301 addi t1,t1,0 - 33e0: 0900 addi s0,sp,144 - 33e2: 0000 unimp - 33e4: 0501 addi a0,a0,0 - 33e6: 0601 addi a2,a2,0 - 33e8: 00097903 0x97903 - 33ec: 0100 addi s0,sp,128 - 33ee: 0305 addi t1,t1,1 - 33f0: 0306 slli t1,t1,0x1 - 33f2: 00040907 vlbu.v v18,(s0),v0.t - 33f6: 0501 addi a0,a0,0 - 33f8: 0601 addi a2,a2,0 - 33fa: 00097903 0x97903 - 33fe: 0100 addi s0,sp,128 - 3400: 0305 addi t1,t1,1 - 3402: 0306 slli t1,t1,0x1 - 3404: 00040907 vlbu.v v18,(s0),v0.t - 3408: 0501 addi a0,a0,0 - 340a: 0601 addi a2,a2,0 - 340c: 00097903 0x97903 - 3410: 0100 addi s0,sp,128 - 3412: 0305 addi t1,t1,1 - 3414: 0306 slli t1,t1,0x1 - 3416: 00040907 vlbu.v v18,(s0),v0.t - 341a: 0501 addi a0,a0,0 - 341c: 0601 addi a2,a2,0 - 341e: 00097903 0x97903 - 3422: 0100 addi s0,sp,128 - 3424: 0305 addi t1,t1,1 - 3426: 08090703 lb a4,128(s2) - 342a: 0100 addi s0,sp,128 - 342c: 0c090103 lb sp,192(s2) - 3430: 0100 addi s0,sp,128 - 3432: 0105 addi sp,sp,1 - 3434: 08097803 0x8097803 - 3438: 0100 addi s0,sp,128 - 343a: 0305 addi t1,t1,1 - 343c: 0c090703 lb a4,192(s2) - 3440: 0100 addi s0,sp,128 - 3442: 0105 addi sp,sp,1 - 3444: 08097903 0x8097903 - 3448: 0100 addi s0,sp,128 - 344a: 0305 addi t1,t1,1 - 344c: 04090703 lb a4,64(s2) - 3450: 0100 addi s0,sp,128 - 3452: 0306 slli t1,t1,0x1 - 3454: 0900 addi s0,sp,144 - 3456: 0004 0x4 - 3458: 0301 addi t1,t1,0 - 345a: 0900 addi s0,sp,144 - 345c: 0000 unimp - 345e: 0301 addi t1,t1,0 - 3460: 0901 addi s2,s2,0 - 3462: 0004 0x4 - 3464: 0301 addi t1,t1,0 - 3466: 0900 addi s0,sp,144 - 3468: 0000 unimp - 346a: 0301 addi t1,t1,0 - 346c: 0900 addi s0,sp,144 - 346e: 0000 unimp - 3470: 0301 addi t1,t1,0 - 3472: 0900 addi s0,sp,144 - 3474: 0000 unimp - 3476: 0301 addi t1,t1,0 - 3478: 0900 addi s0,sp,144 - 347a: 0000 unimp - 347c: 0301 addi t1,t1,0 - 347e: 0900 addi s0,sp,144 - 3480: 0000 unimp - 3482: 0301 addi t1,t1,0 - 3484: 0900 addi s0,sp,144 - 3486: 0000 unimp - 3488: 0301 addi t1,t1,0 - 348a: 0900 addi s0,sp,144 - 348c: 0004 0x4 - 348e: 0301 addi t1,t1,0 - 3490: 0900 addi s0,sp,144 - 3492: 0004 0x4 - 3494: 0301 addi t1,t1,0 - 3496: 0901 addi s2,s2,0 - 3498: 0004 0x4 - 349a: 0301 addi t1,t1,0 - 349c: 0900 addi s0,sp,144 - 349e: 0000 unimp - 34a0: 0301 addi t1,t1,0 - 34a2: 0900 addi s0,sp,144 - 34a4: 0000 unimp - 34a6: 0301 addi t1,t1,0 - 34a8: 0900 addi s0,sp,144 - 34aa: 0000 unimp - 34ac: 0001 nop - 34ae: 0402 c.slli64 s0 - 34b0: 0612 slli a2,a2,0x4 - 34b2: 04090003 lb zero,64(s2) - 34b6: 0100 addi s0,sp,128 - 34b8: 10090003 lb zero,256(s2) - 34bc: 0100 addi s0,sp,128 - 34be: 0200 addi s0,sp,256 - 34c0: 1504 addi s1,sp,672 - 34c2: 08090003 lb zero,128(s2) - 34c6: 0100 addi s0,sp,128 - 34c8: 0200 addi s0,sp,256 - 34ca: 1604 addi s1,sp,800 - 34cc: 04090003 lb zero,64(s2) - 34d0: 0100 addi s0,sp,128 - 34d2: 0200 addi s0,sp,256 - 34d4: 3904 fld fs1,48(a0) - 34d6: 0306 slli t1,t1,0x1 - 34d8: 0900 addi s0,sp,144 - 34da: 0010 0x10 - 34dc: 0001 nop - 34de: 0402 c.slli64 s0 - 34e0: 0339 addi t1,t1,14 - 34e2: 0900 addi s0,sp,144 - 34e4: 0000 unimp - 34e6: 0001 nop - 34e8: 0402 c.slli64 s0 - 34ea: 0339 addi t1,t1,14 - 34ec: 0900 addi s0,sp,144 - 34ee: 0000 unimp - 34f0: 0001 nop - 34f2: 0402 c.slli64 s0 - 34f4: 0339 addi t1,t1,14 - 34f6: 0900 addi s0,sp,144 - 34f8: 0000 unimp - 34fa: 0001 nop - 34fc: 0402 c.slli64 s0 - 34fe: 0339 addi t1,t1,14 - 3500: 0900 addi s0,sp,144 - 3502: 0000 unimp - 3504: 0001 nop - 3506: 0402 c.slli64 s0 - 3508: 0339 addi t1,t1,14 - 350a: 0900 addi s0,sp,144 - 350c: 0000 unimp - 350e: 0001 nop - 3510: 0402 c.slli64 s0 - 3512: 0339 addi t1,t1,14 - 3514: 0900 addi s0,sp,144 - 3516: 0000 unimp - 3518: 0001 nop - 351a: 0402 c.slli64 s0 - 351c: 0339 addi t1,t1,14 - 351e: 0900 addi s0,sp,144 - 3520: 0000 unimp - 3522: 0001 nop - 3524: 0402 c.slli64 s0 - 3526: 0339 addi t1,t1,14 - 3528: 0900 addi s0,sp,144 - 352a: 0000 unimp - 352c: 0001 nop - 352e: 0402 c.slli64 s0 - 3530: 063a slli a2,a2,0xe - 3532: 04090003 lb zero,64(s2) - 3536: 0100 addi s0,sp,128 - 3538: 0200 addi s0,sp,256 - 353a: 3a04 fld fs1,48(a2) - 353c: 0306 slli t1,t1,0x1 - 353e: 0900 addi s0,sp,144 - 3540: 0010 0x10 - 3542: 0001 nop - 3544: 0402 c.slli64 s0 - 3546: 0640 addi s0,sp,772 - 3548: 04090003 lb zero,64(s2) - 354c: 0100 addi s0,sp,128 - 354e: 0306 slli t1,t1,0x1 - 3550: 0900 addi s0,sp,144 - 3552: 0010 0x10 - 3554: 0301 addi t1,t1,0 - 3556: 0900 addi s0,sp,144 - 3558: 0004 0x4 - 355a: 0301 addi t1,t1,0 - 355c: 0900 addi s0,sp,144 - 355e: 0000 unimp - 3560: 0301 addi t1,t1,0 - 3562: 0900 addi s0,sp,144 - 3564: 0000 unimp - 3566: 0001 nop - 3568: 0402 c.slli64 s0 - 356a: 0374 addi a3,sp,396 - 356c: 0900 addi s0,sp,144 - 356e: 0004 0x4 - 3570: 0601 addi a2,a2,0 - 3572: 04090003 lb zero,64(s2) - 3576: 0100 addi s0,sp,128 - 3578: 0200 addi s0,sp,256 - 357a: 4a04 lw s1,16(a2) - 357c: 0306 slli t1,t1,0x1 - 357e: 0900 addi s0,sp,144 - 3580: 0008 0x8 - 3582: 0001 nop - 3584: 0402 c.slli64 s0 - 3586: 034a slli t1,t1,0x12 - 3588: 0900 addi s0,sp,144 - 358a: 0000 unimp - 358c: 0601 addi a2,a2,0 - 358e: 08090003 lb zero,128(s2) - 3592: 0100 addi s0,sp,128 - 3594: 0105 addi sp,sp,1 - 3596: 04090403 lb s0,64(s2) - 359a: 0100 addi s0,sp,128 - 359c: 0305 addi t1,t1,1 - 359e: 0200 addi s0,sp,256 - 35a0: 5704 lw s1,40(a4) - 35a2: 0306 slli t1,t1,0x1 - 35a4: 097c addi a5,sp,156 - 35a6: 0008 0x8 - 35a8: 0001 nop - 35aa: 0402 c.slli64 s0 - 35ac: 035d addi t1,t1,23 - 35ae: 0900 addi s0,sp,144 - 35b0: 0004 0x4 - 35b2: 0001 nop - 35b4: 01860403 lb s0,24(a2) # b018 <_start-0x7fff4fe8> - 35b8: 04090003 lb zero,64(s2) - 35bc: 0100 addi s0,sp,128 - 35be: 0200 addi s0,sp,256 - 35c0: 6304 flw fs1,0(a4) - 35c2: 08090003 lb zero,128(s2) - 35c6: 0100 addi s0,sp,128 - 35c8: 0200 addi s0,sp,256 - 35ca: 6904 flw fs1,16(a0) - 35cc: 0306 slli t1,t1,0x1 - 35ce: 0900 addi s0,sp,144 - 35d0: 0004 0x4 - 35d2: 0001 nop - 35d4: 0402 c.slli64 s0 - 35d6: 036a slli t1,t1,0x1a - 35d8: 0900 addi s0,sp,144 - 35da: 0004 0x4 - 35dc: 0001 nop - 35de: 0402 c.slli64 s0 - 35e0: 036d addi t1,t1,27 - 35e2: 0900 addi s0,sp,144 - 35e4: 0004 0x4 - 35e6: 0001 nop - 35e8: 0402 c.slli64 s0 - 35ea: 036e slli t1,t1,0x1b - 35ec: 0900 addi s0,sp,144 - 35ee: 0004 0x4 - 35f0: 0001 nop - 35f2: 0402 c.slli64 s0 - 35f4: 0371 addi t1,t1,28 - 35f6: 0900 addi s0,sp,144 - 35f8: 0004 0x4 - 35fa: 0001 nop - 35fc: 0402 c.slli64 s0 - 35fe: 0372 slli t1,t1,0x1c - 3600: 0900 addi s0,sp,144 - 3602: 0004 0x4 - 3604: 0001 nop - 3606: 01800403 lb s0,24(zero) # 18 <_start-0x7fffffe8> - 360a: 0306 slli t1,t1,0x1 - 360c: 0900 addi s0,sp,144 - 360e: 0004 0x4 - 3610: 0001 nop - 3612: 01830403 lb s0,24(t1) - 3616: 0306 slli t1,t1,0x1 - 3618: 0900 addi s0,sp,144 - 361a: 0004 0x4 - 361c: 0001 nop - 361e: 01840403 lb s0,24(s0) # 18018 <_start-0x7ffe7fe8> - 3622: 04090003 lb zero,64(s2) - 3626: 0100 addi s0,sp,128 - 3628: 04090003 lb zero,64(s2) - 362c: 0100 addi s0,sp,128 - 362e: 0306 slli t1,t1,0x1 - 3630: 0900 addi s0,sp,144 - 3632: 0010 0x10 - 3634: 0301 addi t1,t1,0 - 3636: 0900 addi s0,sp,144 - 3638: 0008 0x8 - 363a: 0301 addi t1,t1,0 - 363c: 0900 addi s0,sp,144 - 363e: 0008 0x8 - 3640: 0301 addi t1,t1,0 - 3642: 0900 addi s0,sp,144 - 3644: 000c 0xc - 3646: 0901 addi s2,s2,0 - 3648: 000c 0xc - 364a: 0100 addi s0,sp,128 - 364c: 4d01 li s10,0 - 364e: 001e c.slli zero,0x7 - 3650: 0300 addi s0,sp,384 - 3652: 9100 0x9100 - 3654: 0000 unimp - 3656: 0100 addi s0,sp,128 - 3658: fb01 bnez a4,3568 <_start-0x7fffca98> - 365a: 0d0e slli s10,s10,0x3 - 365c: 0100 addi s0,sp,128 - 365e: 0101 addi sp,sp,0 - 3660: 0001 nop - 3662: 0000 unimp - 3664: 0001 nop - 3666: 0100 addi s0,sp,128 - 3668: 2e2e fld ft8,200(sp) - 366a: 2f2e2e2f 0x2f2e2e2f - 366e: 2e2e fld ft8,200(sp) - 3670: 2f2e2e2f 0x2f2e2e2f - 3674: 6972 flw fs2,28(sp) - 3676: 2d766373 csrrsi t1,0x2d7,12 - 367a: 2f636367 0x2f636367 - 367e: 696c flw fa1,84(a0) - 3680: 6762 flw fa4,24(sp) - 3682: 732f6363 bltu t5,s2,3da8 <_start-0x7fffc258> - 3686: 2d74666f jal a2,4a15c <_start-0x7ffb5ea4> - 368a: 7066 flw ft0,120(sp) - 368c: 2e00 fld fs0,24(a2) - 368e: 2f2e fld ft10,200(sp) - 3690: 2e2e fld ft8,200(sp) - 3692: 2f2e2e2f 0x2f2e2e2f - 3696: 2e2e fld ft8,200(sp) - 3698: 7369722f 0x7369722f - 369c: 672d7663 bgeu s10,s2,3d08 <_start-0x7fffc2f8> - 36a0: 6c2f6363 bltu t5,sp,3d66 <_start-0x7fffc29a> - 36a4: 6269 lui tp,0x1a - 36a6: 2f636367 0x2f636367 - 36aa: 2e2e fld ft8,200(sp) - 36ac: 636e692f vamoandw.v zero,v22,(t3),v18 - 36b0: 756c flw fa1,108(a0) - 36b2: 6564 flw fs1,76(a0) - 36b4: 0000 unimp - 36b6: 756d lui a0,0xffffb - 36b8: 746c flw fa1,108(s0) - 36ba: 3366 fld ft6,120(sp) - 36bc: 632e flw ft6,200(sp) - 36be: 0100 addi s0,sp,128 - 36c0: 0000 unimp - 36c2: 74666f73 csrrsi t5,0x746,12 - 36c6: 662d lui a2,0xb - 36c8: 2e70 fld fa2,216(a2) - 36ca: 0068 addi a0,sp,12 - 36cc: 0001 nop - 36ce: 7100 flw fs0,32(a0) - 36d0: 6175 addi sp,sp,368 - 36d2: 2e64 fld fs1,216(a2) - 36d4: 0068 addi a0,sp,12 - 36d6: 0001 nop - 36d8: 6c00 flw fs0,24(s0) - 36da: 6c676e6f jal t3,79da0 <_start-0x7ff86260> - 36de: 2e676e6f jal t3,799c4 <_start-0x7ff8663c> - 36e2: 0068 addi a0,sp,12 - 36e4: 0002 c.slli64 zero - 36e6: 0000 unimp - 36e8: 0105 addi sp,sp,1 - 36ea: 0500 addi s0,sp,640 - 36ec: bc02 fsd ft0,56(sp) - 36ee: 03800117 auipc sp,0x3800 - 36f2: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe42aa> - 36f6: 00090103 lb sp,0(s2) - 36fa: 0100 addi s0,sp,128 - 36fc: 00090003 lb zero,0(s2) - 3700: 0100 addi s0,sp,128 - 3702: 0d05 addi s10,s10,1 - 3704: 00090003 lb zero,0(s2) - 3708: 0100 addi s0,sp,128 - 370a: 0305 addi t1,t1,1 - 370c: 00090103 lb sp,0(s2) - 3710: 0100 addi s0,sp,128 - 3712: 00090003 lb zero,0(s2) - 3716: 0100 addi s0,sp,128 - 3718: 00090003 lb zero,0(s2) - 371c: 0100 addi s0,sp,128 - 371e: 00090003 lb zero,0(s2) - 3722: 0100 addi s0,sp,128 - 3724: 00090103 lb sp,0(s2) - 3728: 0100 addi s0,sp,128 - 372a: 00090003 lb zero,0(s2) - 372e: 0100 addi s0,sp,128 - 3730: 00090003 lb zero,0(s2) - 3734: 0100 addi s0,sp,128 - 3736: 00090003 lb zero,0(s2) - 373a: 0100 addi s0,sp,128 - 373c: 00090103 lb sp,0(s2) - 3740: 0100 addi s0,sp,128 - 3742: 00090003 lb zero,0(s2) - 3746: 0100 addi s0,sp,128 - 3748: 00090003 lb zero,0(s2) - 374c: 0100 addi s0,sp,128 - 374e: 00090003 lb zero,0(s2) - 3752: 0100 addi s0,sp,128 - 3754: 00090103 lb sp,0(s2) - 3758: 0100 addi s0,sp,128 - 375a: 00090203 lb tp,0(s2) - 375e: 0100 addi s0,sp,128 - 3760: 00090103 lb sp,0(s2) - 3764: 0100 addi s0,sp,128 - 3766: 00090003 lb zero,0(s2) - 376a: 0100 addi s0,sp,128 - 376c: 00090003 lb zero,0(s2) - 3770: 0100 addi s0,sp,128 - 3772: 00090003 lb zero,0(s2) - 3776: 0100 addi s0,sp,128 - 3778: 0105 addi sp,sp,1 - 377a: 0306 slli t1,t1,0x1 - 377c: 0978 addi a4,sp,156 - 377e: 0000 unimp - 3780: 0501 addi a0,a0,0 - 3782: 09080303 lb t1,144(a6) - 3786: 0040 addi s0,sp,4 - 3788: 0501 addi a0,a0,0 - 378a: 0301 addi t1,t1,0 - 378c: 0978 addi a4,sp,156 - 378e: 0004 0x4 - 3790: 0501 addi a0,a0,0 - 3792: 09080303 lb t1,144(a6) - 3796: 0008 0x8 - 3798: 0601 addi a2,a2,0 - 379a: 0c090003 lb zero,192(s2) - 379e: 0100 addi s0,sp,128 - 37a0: 0105 addi sp,sp,1 - 37a2: 0306 slli t1,t1,0x1 - 37a4: 0978 addi a4,sp,156 - 37a6: 0000 unimp - 37a8: 0501 addi a0,a0,0 - 37aa: 09080303 lb t1,144(a6) - 37ae: 001c 0x1c - 37b0: 0601 addi a2,a2,0 - 37b2: 10090003 lb zero,256(s2) - 37b6: 0100 addi s0,sp,128 - 37b8: 04090003 lb zero,64(s2) - 37bc: 0100 addi s0,sp,128 - 37be: 04090003 lb zero,64(s2) - 37c2: 0100 addi s0,sp,128 - 37c4: 04090003 lb zero,64(s2) - 37c8: 0100 addi s0,sp,128 - 37ca: 04090003 lb zero,64(s2) - 37ce: 0100 addi s0,sp,128 - 37d0: 04090003 lb zero,64(s2) - 37d4: 0100 addi s0,sp,128 - 37d6: 00090003 lb zero,0(s2) - 37da: 0100 addi s0,sp,128 - 37dc: 0200 addi s0,sp,256 - 37de: 0104 addi s1,sp,128 - 37e0: 08090003 lb zero,128(s2) - 37e4: 0100 addi s0,sp,128 - 37e6: 0200 addi s0,sp,256 - 37e8: 0104 addi s1,sp,128 - 37ea: 0c090003 lb zero,192(s2) - 37ee: 0100 addi s0,sp,128 - 37f0: 0200 addi s0,sp,256 - 37f2: 0104 addi s1,sp,128 - 37f4: 00090003 lb zero,0(s2) - 37f8: 0100 addi s0,sp,128 - 37fa: 0200 addi s0,sp,256 - 37fc: 0104 addi s1,sp,128 - 37fe: 00090003 lb zero,0(s2) - 3802: 0100 addi s0,sp,128 - 3804: 0200 addi s0,sp,256 - 3806: 0104 addi s1,sp,128 - 3808: 00090003 lb zero,0(s2) - 380c: 0100 addi s0,sp,128 - 380e: 0200 addi s0,sp,256 - 3810: 0104 addi s1,sp,128 - 3812: 00090003 lb zero,0(s2) - 3816: 0100 addi s0,sp,128 - 3818: 0200 addi s0,sp,256 - 381a: 0104 addi s1,sp,128 - 381c: 00090003 lb zero,0(s2) - 3820: 0100 addi s0,sp,128 - 3822: 0200 addi s0,sp,256 - 3824: 0104 addi s1,sp,128 - 3826: 00090003 lb zero,0(s2) - 382a: 0100 addi s0,sp,128 - 382c: 0200 addi s0,sp,256 - 382e: 0104 addi s1,sp,128 - 3830: 00090003 lb zero,0(s2) - 3834: 0100 addi s0,sp,128 - 3836: 0200 addi s0,sp,256 - 3838: 0b04 addi s1,sp,400 - 383a: 08090003 lb zero,128(s2) - 383e: 0100 addi s0,sp,128 - 3840: 0200 addi s0,sp,256 - 3842: 0c04 addi s1,sp,528 - 3844: 20090003 lb zero,512(s2) - 3848: 0100 addi s0,sp,128 - 384a: 0200 addi s0,sp,256 - 384c: 0c04 addi s1,sp,528 - 384e: 14090003 lb zero,320(s2) - 3852: 0100 addi s0,sp,128 - 3854: 0200 addi s0,sp,256 - 3856: 0c04 addi s1,sp,528 - 3858: 04090003 lb zero,64(s2) - 385c: 0100 addi s0,sp,128 - 385e: 0200 addi s0,sp,256 - 3860: 0c04 addi s1,sp,528 - 3862: 00090003 lb zero,0(s2) - 3866: 0100 addi s0,sp,128 - 3868: 0200 addi s0,sp,256 - 386a: 4504 lw s1,8(a0) - 386c: 00090003 lb zero,0(s2) - 3870: 0100 addi s0,sp,128 - 3872: 0200 addi s0,sp,256 - 3874: 4504 lw s1,8(a0) - 3876: 00090003 lb zero,0(s2) - 387a: 0100 addi s0,sp,128 - 387c: 04090103 lb sp,64(s2) - 3880: 0100 addi s0,sp,128 - 3882: 00090003 lb zero,0(s2) - 3886: 0100 addi s0,sp,128 - 3888: 00090003 lb zero,0(s2) - 388c: 0100 addi s0,sp,128 - 388e: 00090003 lb zero,0(s2) - 3892: 0100 addi s0,sp,128 - 3894: 18090003 lb zero,384(s2) - 3898: 0100 addi s0,sp,128 - 389a: 10090003 lb zero,256(s2) - 389e: 0100 addi s0,sp,128 - 38a0: 04090003 lb zero,64(s2) - 38a4: 0100 addi s0,sp,128 - 38a6: 04090003 lb zero,64(s2) - 38aa: 0100 addi s0,sp,128 - 38ac: 04090003 lb zero,64(s2) - 38b0: 0100 addi s0,sp,128 - 38b2: 04090003 lb zero,64(s2) - 38b6: 0100 addi s0,sp,128 - 38b8: 04090003 lb zero,64(s2) - 38bc: 0100 addi s0,sp,128 - 38be: 00090003 lb zero,0(s2) - 38c2: 0100 addi s0,sp,128 - 38c4: 0200 addi s0,sp,256 - 38c6: 0104 addi s1,sp,128 - 38c8: 08090003 lb zero,128(s2) - 38cc: 0100 addi s0,sp,128 - 38ce: 0200 addi s0,sp,256 - 38d0: 0104 addi s1,sp,128 - 38d2: 0c090003 lb zero,192(s2) - 38d6: 0100 addi s0,sp,128 - 38d8: 0200 addi s0,sp,256 - 38da: 0104 addi s1,sp,128 - 38dc: 00090003 lb zero,0(s2) - 38e0: 0100 addi s0,sp,128 - 38e2: 0200 addi s0,sp,256 - 38e4: 0104 addi s1,sp,128 - 38e6: 00090003 lb zero,0(s2) - 38ea: 0100 addi s0,sp,128 - 38ec: 0200 addi s0,sp,256 - 38ee: 0104 addi s1,sp,128 - 38f0: 00090003 lb zero,0(s2) - 38f4: 0100 addi s0,sp,128 - 38f6: 0200 addi s0,sp,256 - 38f8: 0104 addi s1,sp,128 - 38fa: 00090003 lb zero,0(s2) - 38fe: 0100 addi s0,sp,128 - 3900: 0200 addi s0,sp,256 - 3902: 0104 addi s1,sp,128 - 3904: 00090003 lb zero,0(s2) - 3908: 0100 addi s0,sp,128 - 390a: 0200 addi s0,sp,256 - 390c: 0104 addi s1,sp,128 - 390e: 00090003 lb zero,0(s2) - 3912: 0100 addi s0,sp,128 - 3914: 0200 addi s0,sp,256 - 3916: 0104 addi s1,sp,128 - 3918: 00090003 lb zero,0(s2) - 391c: 0100 addi s0,sp,128 - 391e: 0200 addi s0,sp,256 - 3920: 0b04 addi s1,sp,400 - 3922: 08090003 lb zero,128(s2) - 3926: 0100 addi s0,sp,128 - 3928: 0200 addi s0,sp,256 - 392a: 0c04 addi s1,sp,528 - 392c: 20090003 lb zero,512(s2) - 3930: 0100 addi s0,sp,128 - 3932: 0200 addi s0,sp,256 - 3934: 0c04 addi s1,sp,528 - 3936: 14090003 lb zero,320(s2) - 393a: 0100 addi s0,sp,128 - 393c: 0200 addi s0,sp,256 - 393e: 0c04 addi s1,sp,528 - 3940: 04090003 lb zero,64(s2) - 3944: 0100 addi s0,sp,128 - 3946: 0200 addi s0,sp,256 - 3948: 0c04 addi s1,sp,528 - 394a: 00090003 lb zero,0(s2) - 394e: 0100 addi s0,sp,128 - 3950: 0200 addi s0,sp,256 - 3952: 4504 lw s1,8(a0) - 3954: 00090003 lb zero,0(s2) - 3958: 0100 addi s0,sp,128 - 395a: 0200 addi s0,sp,256 - 395c: 4504 lw s1,8(a0) - 395e: 00090003 lb zero,0(s2) - 3962: 0100 addi s0,sp,128 - 3964: 04090103 lb sp,64(s2) - 3968: 0100 addi s0,sp,128 - 396a: 00090003 lb zero,0(s2) - 396e: 0100 addi s0,sp,128 - 3970: 20090003 lb zero,512(s2) - 3974: 0100 addi s0,sp,128 - 3976: 00090003 lb zero,0(s2) - 397a: 0100 addi s0,sp,128 - 397c: 0200 addi s0,sp,256 - 397e: 0204 addi s1,sp,256 - 3980: 24097e03 0x24097e03 - 3984: 0100 addi s0,sp,128 - 3986: 0200 addi s0,sp,256 - 3988: 1504 addi s1,sp,672 - 398a: 10090003 lb zero,256(s2) - 398e: 0100 addi s0,sp,128 - 3990: 0200 addi s0,sp,256 - 3992: 1504 addi s1,sp,672 - 3994: 00090003 lb zero,0(s2) - 3998: 0100 addi s0,sp,128 - 399a: 0200 addi s0,sp,256 - 399c: 1504 addi s1,sp,672 - 399e: 00090003 lb zero,0(s2) - 39a2: 0100 addi s0,sp,128 - 39a4: 0200 addi s0,sp,256 - 39a6: 1504 addi s1,sp,672 - 39a8: 00090003 lb zero,0(s2) - 39ac: 0100 addi s0,sp,128 - 39ae: 0200 addi s0,sp,256 - 39b0: 1904 addi s1,sp,176 - 39b2: 04090003 lb zero,64(s2) - 39b6: 0100 addi s0,sp,128 - 39b8: 0200 addi s0,sp,256 - 39ba: 1904 addi s1,sp,176 - 39bc: 00090003 lb zero,0(s2) - 39c0: 0100 addi s0,sp,128 - 39c2: 0200 addi s0,sp,256 - 39c4: 1904 addi s1,sp,176 - 39c6: 00090003 lb zero,0(s2) - 39ca: 0100 addi s0,sp,128 - 39cc: 0200 addi s0,sp,256 - 39ce: 1904 addi s1,sp,176 - 39d0: 00090003 lb zero,0(s2) - 39d4: 0100 addi s0,sp,128 - 39d6: 0200 addi s0,sp,256 - 39d8: 3804 fld fs1,48(s0) - 39da: 08090003 lb zero,128(s2) - 39de: 0100 addi s0,sp,128 - 39e0: 0200 addi s0,sp,256 - 39e2: 3804 fld fs1,48(s0) - 39e4: 00090003 lb zero,0(s2) - 39e8: 0100 addi s0,sp,128 - 39ea: 0200 addi s0,sp,256 - 39ec: 3804 fld fs1,48(s0) - 39ee: 00090003 lb zero,0(s2) - 39f2: 0100 addi s0,sp,128 - 39f4: 0200 addi s0,sp,256 - 39f6: 3804 fld fs1,48(s0) - 39f8: 00090003 lb zero,0(s2) - 39fc: 0100 addi s0,sp,128 - 39fe: 0200 addi s0,sp,256 - 3a00: 3804 fld fs1,48(s0) - 3a02: 00090003 lb zero,0(s2) - 3a06: 0100 addi s0,sp,128 - 3a08: 0200 addi s0,sp,256 - 3a0a: 3804 fld fs1,48(s0) - 3a0c: 08090003 lb zero,128(s2) - 3a10: 0100 addi s0,sp,128 - 3a12: 0200 addi s0,sp,256 - 3a14: 3804 fld fs1,48(s0) - 3a16: 04090003 lb zero,64(s2) - 3a1a: 0100 addi s0,sp,128 - 3a1c: 0200 addi s0,sp,256 - 3a1e: 3804 fld fs1,48(s0) - 3a20: 00090003 lb zero,0(s2) - 3a24: 0100 addi s0,sp,128 - 3a26: 0306 slli t1,t1,0x1 - 3a28: 0900 addi s0,sp,144 - 3a2a: 0010 0x10 - 3a2c: 0001 nop - 3a2e: 0402 c.slli64 s0 - 3a30: 033e slli t1,t1,0xf - 3a32: 0900 addi s0,sp,144 - 3a34: 0014 0x14 - 3a36: 0001 nop - 3a38: 0402 c.slli64 s0 - 3a3a: 0341 addi t1,t1,16 - 3a3c: 0900 addi s0,sp,144 - 3a3e: 0004 0x4 - 3a40: 0001 nop - 3a42: 0402 c.slli64 s0 - 3a44: 0641 addi a2,a2,16 - 3a46: 10090003 lb zero,256(s2) - 3a4a: 0100 addi s0,sp,128 - 3a4c: 0200 addi s0,sp,256 - 3a4e: 4304 lw s1,0(a4) - 3a50: 0306 slli t1,t1,0x1 - 3a52: 0900 addi s0,sp,144 - 3a54: 0008 0x8 - 3a56: 0001 nop - 3a58: 0402 c.slli64 s0 - 3a5a: 0618 addi a4,sp,768 - 3a5c: 08090003 lb zero,128(s2) - 3a60: 0100 addi s0,sp,128 - 3a62: 0200 addi s0,sp,256 - 3a64: 1f04 addi s1,sp,944 - 3a66: 04090003 lb zero,64(s2) - 3a6a: 0100 addi s0,sp,128 - 3a6c: 0200 addi s0,sp,256 - 3a6e: 1f04 addi s1,sp,944 - 3a70: 00090003 lb zero,0(s2) - 3a74: 0100 addi s0,sp,128 - 3a76: 0200 addi s0,sp,256 - 3a78: 1f04 addi s1,sp,944 - 3a7a: 00090003 lb zero,0(s2) - 3a7e: 0100 addi s0,sp,128 - 3a80: 0200 addi s0,sp,256 - 3a82: 1f04 addi s1,sp,944 - 3a84: 00090003 lb zero,0(s2) - 3a88: 0100 addi s0,sp,128 - 3a8a: 0200 addi s0,sp,256 - 3a8c: 1f04 addi s1,sp,944 - 3a8e: 04090003 lb zero,64(s2) - 3a92: 0100 addi s0,sp,128 - 3a94: 0200 addi s0,sp,256 - 3a96: 1e04 addi s1,sp,816 - 3a98: 08090003 lb zero,128(s2) - 3a9c: 0100 addi s0,sp,128 - 3a9e: 0200 addi s0,sp,256 - 3aa0: 2904 fld fs1,16(a0) - 3aa2: 04090003 lb zero,64(s2) - 3aa6: 0100 addi s0,sp,128 - 3aa8: 0200 addi s0,sp,256 - 3aaa: 2904 fld fs1,16(a0) - 3aac: 00090003 lb zero,0(s2) - 3ab0: 0100 addi s0,sp,128 - 3ab2: 0200 addi s0,sp,256 - 3ab4: 2904 fld fs1,16(a0) - 3ab6: 00090003 lb zero,0(s2) - 3aba: 0100 addi s0,sp,128 - 3abc: 0200 addi s0,sp,256 - 3abe: 2904 fld fs1,16(a0) - 3ac0: 00090003 lb zero,0(s2) - 3ac4: 0100 addi s0,sp,128 - 3ac6: 0200 addi s0,sp,256 - 3ac8: 2904 fld fs1,16(a0) - 3aca: 08090003 lb zero,128(s2) - 3ace: 0100 addi s0,sp,128 - 3ad0: 0200 addi s0,sp,256 - 3ad2: 3104 fld fs1,32(a0) - 3ad4: 08090003 lb zero,128(s2) - 3ad8: 0100 addi s0,sp,128 - 3ada: 0200 addi s0,sp,256 - 3adc: 3104 fld fs1,32(a0) - 3ade: 00090003 lb zero,0(s2) - 3ae2: 0100 addi s0,sp,128 - 3ae4: 0200 addi s0,sp,256 - 3ae6: 3104 fld fs1,32(a0) - 3ae8: 00090003 lb zero,0(s2) - 3aec: 0100 addi s0,sp,128 - 3aee: 0200 addi s0,sp,256 - 3af0: 3104 fld fs1,32(a0) - 3af2: 00090003 lb zero,0(s2) - 3af6: 0100 addi s0,sp,128 - 3af8: 0200 addi s0,sp,256 - 3afa: 3104 fld fs1,32(a0) - 3afc: 08090003 lb zero,128(s2) - 3b00: 0100 addi s0,sp,128 - 3b02: 0306 slli t1,t1,0x1 - 3b04: 0900 addi s0,sp,144 - 3b06: 0014 0x14 - 3b08: 0001 nop - 3b0a: 0402 c.slli64 s0 - 3b0c: 063d addi a2,a2,15 - 3b0e: 04090003 lb zero,64(s2) - 3b12: 0100 addi s0,sp,128 - 3b14: 0200 addi s0,sp,256 - 3b16: 4004 lw s1,0(s0) - 3b18: 20090003 lb zero,512(s2) - 3b1c: 0100 addi s0,sp,128 - 3b1e: 0200 addi s0,sp,256 - 3b20: 4404 lw s1,8(s0) - 3b22: 24090003 lb zero,576(s2) - 3b26: 0100 addi s0,sp,128 - 3b28: 0200 addi s0,sp,256 - 3b2a: 4304 lw s1,0(a4) - 3b2c: 0306 slli t1,t1,0x1 - 3b2e: 0900 addi s0,sp,144 - 3b30: 0014 0x14 - 3b32: 0001 nop - 3b34: 0402 c.slli64 s0 - 3b36: 0645 addi a2,a2,17 - 3b38: 04090003 lb zero,64(s2) - 3b3c: 0100 addi s0,sp,128 - 3b3e: 0200 addi s0,sp,256 - 3b40: 0304 addi s1,sp,384 - 3b42: 10090003 lb zero,256(s2) - 3b46: 0100 addi s0,sp,128 - 3b48: 0306 slli t1,t1,0x1 - 3b4a: 0900 addi s0,sp,144 - 3b4c: 0014 0x14 - 3b4e: 0001 nop - 3b50: 0402 c.slli64 s0 - 3b52: 0602 c.slli64 a2 - 3b54: 14090103 lb sp,320(s2) - 3b58: 0100 addi s0,sp,128 - 3b5a: 0200 addi s0,sp,256 - 3b5c: 1504 addi s1,sp,672 - 3b5e: 10090003 lb zero,256(s2) - 3b62: 0100 addi s0,sp,128 - 3b64: 0200 addi s0,sp,256 - 3b66: 1504 addi s1,sp,672 - 3b68: 00090003 lb zero,0(s2) - 3b6c: 0100 addi s0,sp,128 - 3b6e: 0200 addi s0,sp,256 - 3b70: 1504 addi s1,sp,672 - 3b72: 00090003 lb zero,0(s2) - 3b76: 0100 addi s0,sp,128 - 3b78: 0200 addi s0,sp,256 - 3b7a: 1504 addi s1,sp,672 - 3b7c: 00090003 lb zero,0(s2) - 3b80: 0100 addi s0,sp,128 - 3b82: 0200 addi s0,sp,256 - 3b84: 1904 addi s1,sp,176 - 3b86: 04090003 lb zero,64(s2) - 3b8a: 0100 addi s0,sp,128 - 3b8c: 0200 addi s0,sp,256 - 3b8e: 1904 addi s1,sp,176 - 3b90: 00090003 lb zero,0(s2) - 3b94: 0100 addi s0,sp,128 - 3b96: 0200 addi s0,sp,256 - 3b98: 1904 addi s1,sp,176 - 3b9a: 00090003 lb zero,0(s2) - 3b9e: 0100 addi s0,sp,128 - 3ba0: 0200 addi s0,sp,256 - 3ba2: 1904 addi s1,sp,176 - 3ba4: 00090003 lb zero,0(s2) - 3ba8: 0100 addi s0,sp,128 - 3baa: 0200 addi s0,sp,256 - 3bac: 3804 fld fs1,48(s0) - 3bae: 04090003 lb zero,64(s2) - 3bb2: 0100 addi s0,sp,128 - 3bb4: 0200 addi s0,sp,256 - 3bb6: 3804 fld fs1,48(s0) - 3bb8: 00090003 lb zero,0(s2) - 3bbc: 0100 addi s0,sp,128 - 3bbe: 0200 addi s0,sp,256 - 3bc0: 3804 fld fs1,48(s0) - 3bc2: 00090003 lb zero,0(s2) - 3bc6: 0100 addi s0,sp,128 - 3bc8: 0200 addi s0,sp,256 - 3bca: 3804 fld fs1,48(s0) - 3bcc: 00090003 lb zero,0(s2) - 3bd0: 0100 addi s0,sp,128 - 3bd2: 0200 addi s0,sp,256 - 3bd4: 3804 fld fs1,48(s0) - 3bd6: 00090003 lb zero,0(s2) - 3bda: 0100 addi s0,sp,128 - 3bdc: 0200 addi s0,sp,256 - 3bde: 3804 fld fs1,48(s0) - 3be0: 08090003 lb zero,128(s2) - 3be4: 0100 addi s0,sp,128 - 3be6: 0200 addi s0,sp,256 - 3be8: 3804 fld fs1,48(s0) - 3bea: 04090003 lb zero,64(s2) - 3bee: 0100 addi s0,sp,128 - 3bf0: 0200 addi s0,sp,256 - 3bf2: 3804 fld fs1,48(s0) - 3bf4: 00090003 lb zero,0(s2) - 3bf8: 0100 addi s0,sp,128 - 3bfa: 0306 slli t1,t1,0x1 - 3bfc: 0900 addi s0,sp,144 - 3bfe: 0010 0x10 - 3c00: 0001 nop - 3c02: 0402 c.slli64 s0 - 3c04: 033e slli t1,t1,0xf - 3c06: 0900 addi s0,sp,144 - 3c08: 0014 0x14 - 3c0a: 0001 nop - 3c0c: 0402 c.slli64 s0 - 3c0e: 0341 addi t1,t1,16 - 3c10: 0900 addi s0,sp,144 - 3c12: 0004 0x4 - 3c14: 0001 nop - 3c16: 0402 c.slli64 s0 - 3c18: 0641 addi a2,a2,16 - 3c1a: 10090003 lb zero,256(s2) - 3c1e: 0100 addi s0,sp,128 - 3c20: 0200 addi s0,sp,256 - 3c22: 4304 lw s1,0(a4) - 3c24: 0306 slli t1,t1,0x1 - 3c26: 0900 addi s0,sp,144 - 3c28: 0008 0x8 - 3c2a: 0001 nop - 3c2c: 0402 c.slli64 s0 - 3c2e: 0618 addi a4,sp,768 - 3c30: 08090003 lb zero,128(s2) - 3c34: 0100 addi s0,sp,128 - 3c36: 0200 addi s0,sp,256 - 3c38: 1f04 addi s1,sp,944 - 3c3a: 04090003 lb zero,64(s2) - 3c3e: 0100 addi s0,sp,128 - 3c40: 0200 addi s0,sp,256 - 3c42: 1f04 addi s1,sp,944 - 3c44: 00090003 lb zero,0(s2) - 3c48: 0100 addi s0,sp,128 - 3c4a: 0200 addi s0,sp,256 - 3c4c: 1f04 addi s1,sp,944 - 3c4e: 00090003 lb zero,0(s2) - 3c52: 0100 addi s0,sp,128 - 3c54: 0200 addi s0,sp,256 - 3c56: 1f04 addi s1,sp,944 - 3c58: 00090003 lb zero,0(s2) - 3c5c: 0100 addi s0,sp,128 - 3c5e: 0200 addi s0,sp,256 - 3c60: 1f04 addi s1,sp,944 - 3c62: 08090003 lb zero,128(s2) - 3c66: 0100 addi s0,sp,128 - 3c68: 0200 addi s0,sp,256 - 3c6a: 1e04 addi s1,sp,816 - 3c6c: 08090003 lb zero,128(s2) - 3c70: 0100 addi s0,sp,128 - 3c72: 0200 addi s0,sp,256 - 3c74: 2904 fld fs1,16(a0) - 3c76: 04090003 lb zero,64(s2) - 3c7a: 0100 addi s0,sp,128 - 3c7c: 0200 addi s0,sp,256 - 3c7e: 2904 fld fs1,16(a0) - 3c80: 00090003 lb zero,0(s2) - 3c84: 0100 addi s0,sp,128 - 3c86: 0200 addi s0,sp,256 - 3c88: 2904 fld fs1,16(a0) - 3c8a: 00090003 lb zero,0(s2) - 3c8e: 0100 addi s0,sp,128 - 3c90: 0200 addi s0,sp,256 - 3c92: 2904 fld fs1,16(a0) - 3c94: 00090003 lb zero,0(s2) - 3c98: 0100 addi s0,sp,128 - 3c9a: 0200 addi s0,sp,256 - 3c9c: 2904 fld fs1,16(a0) - 3c9e: 08090003 lb zero,128(s2) - 3ca2: 0100 addi s0,sp,128 - 3ca4: 0200 addi s0,sp,256 - 3ca6: 3104 fld fs1,32(a0) - 3ca8: 08090003 lb zero,128(s2) - 3cac: 0100 addi s0,sp,128 - 3cae: 0200 addi s0,sp,256 - 3cb0: 3104 fld fs1,32(a0) - 3cb2: 00090003 lb zero,0(s2) - 3cb6: 0100 addi s0,sp,128 - 3cb8: 0200 addi s0,sp,256 - 3cba: 3104 fld fs1,32(a0) - 3cbc: 00090003 lb zero,0(s2) - 3cc0: 0100 addi s0,sp,128 - 3cc2: 0200 addi s0,sp,256 - 3cc4: 3104 fld fs1,32(a0) - 3cc6: 00090003 lb zero,0(s2) - 3cca: 0100 addi s0,sp,128 - 3ccc: 0200 addi s0,sp,256 - 3cce: 3104 fld fs1,32(a0) - 3cd0: 08090003 lb zero,128(s2) - 3cd4: 0100 addi s0,sp,128 - 3cd6: 0306 slli t1,t1,0x1 - 3cd8: 0900 addi s0,sp,144 - 3cda: 0014 0x14 - 3cdc: 0001 nop - 3cde: 0402 c.slli64 s0 - 3ce0: 063d addi a2,a2,15 - 3ce2: 04090003 lb zero,64(s2) - 3ce6: 0100 addi s0,sp,128 - 3ce8: 0200 addi s0,sp,256 - 3cea: 4004 lw s1,0(s0) - 3cec: 20090003 lb zero,512(s2) - 3cf0: 0100 addi s0,sp,128 - 3cf2: 0200 addi s0,sp,256 - 3cf4: 4404 lw s1,8(s0) - 3cf6: 24090003 lb zero,576(s2) - 3cfa: 0100 addi s0,sp,128 - 3cfc: 0200 addi s0,sp,256 - 3cfe: 4304 lw s1,0(a4) - 3d00: 0306 slli t1,t1,0x1 - 3d02: 0900 addi s0,sp,144 - 3d04: 0014 0x14 - 3d06: 0001 nop - 3d08: 0402 c.slli64 s0 - 3d0a: 0645 addi a2,a2,17 - 3d0c: 04090003 lb zero,64(s2) - 3d10: 0100 addi s0,sp,128 - 3d12: 0200 addi s0,sp,256 - 3d14: 0304 addi s1,sp,384 - 3d16: 10090003 lb zero,256(s2) - 3d1a: 0100 addi s0,sp,128 - 3d1c: 0306 slli t1,t1,0x1 - 3d1e: 0900 addi s0,sp,144 - 3d20: 0014 0x14 - 3d22: 0001 nop - 3d24: 0402 c.slli64 s0 - 3d26: 0602 c.slli64 a2 - 3d28: 14090103 lb sp,320(s2) - 3d2c: 0100 addi s0,sp,128 - 3d2e: 0200 addi s0,sp,256 - 3d30: 0204 addi s1,sp,256 - 3d32: 00090003 lb zero,0(s2) - 3d36: 0100 addi s0,sp,128 - 3d38: 0200 addi s0,sp,256 - 3d3a: 0204 addi s1,sp,256 - 3d3c: 00090003 lb zero,0(s2) - 3d40: 0100 addi s0,sp,128 - 3d42: 0200 addi s0,sp,256 - 3d44: 0204 addi s1,sp,256 - 3d46: 00090003 lb zero,0(s2) - 3d4a: 0100 addi s0,sp,128 - 3d4c: 0200 addi s0,sp,256 - 3d4e: 0204 addi s1,sp,256 - 3d50: 00090003 lb zero,0(s2) - 3d54: 0100 addi s0,sp,128 - 3d56: 0200 addi s0,sp,256 - 3d58: 0204 addi s1,sp,256 - 3d5a: 00090003 lb zero,0(s2) - 3d5e: 0100 addi s0,sp,128 - 3d60: 0200 addi s0,sp,256 - 3d62: 0204 addi s1,sp,256 - 3d64: 00090003 lb zero,0(s2) - 3d68: 0100 addi s0,sp,128 - 3d6a: 0200 addi s0,sp,256 - 3d6c: 0204 addi s1,sp,256 - 3d6e: 00090003 lb zero,0(s2) - 3d72: 0100 addi s0,sp,128 - 3d74: 0200 addi s0,sp,256 - 3d76: 0204 addi s1,sp,256 - 3d78: 00090003 lb zero,0(s2) - 3d7c: 0100 addi s0,sp,128 - 3d7e: 0200 addi s0,sp,256 - 3d80: 0204 addi s1,sp,256 - 3d82: 00090003 lb zero,0(s2) - 3d86: 0100 addi s0,sp,128 - 3d88: 0200 addi s0,sp,256 - 3d8a: 0204 addi s1,sp,256 - 3d8c: 00090003 lb zero,0(s2) - 3d90: 0100 addi s0,sp,128 - 3d92: 0200 addi s0,sp,256 - 3d94: 0204 addi s1,sp,256 - 3d96: 00090003 lb zero,0(s2) - 3d9a: 0100 addi s0,sp,128 - 3d9c: 0200 addi s0,sp,256 - 3d9e: 0204 addi s1,sp,256 - 3da0: 00090003 lb zero,0(s2) - 3da4: 0100 addi s0,sp,128 - 3da6: 0200 addi s0,sp,256 - 3da8: 0204 addi s1,sp,256 - 3daa: 04090003 lb zero,64(s2) - 3dae: 0100 addi s0,sp,128 - 3db0: 0200 addi s0,sp,256 - 3db2: 0204 addi s1,sp,256 - 3db4: 10090003 lb zero,256(s2) - 3db8: 0100 addi s0,sp,128 - 3dba: 0200 addi s0,sp,256 - 3dbc: 0204 addi s1,sp,256 - 3dbe: 00090003 lb zero,0(s2) - 3dc2: 0100 addi s0,sp,128 - 3dc4: 0200 addi s0,sp,256 - 3dc6: 0204 addi s1,sp,256 - 3dc8: 04090003 lb zero,64(s2) - 3dcc: 0100 addi s0,sp,128 - 3dce: 0200 addi s0,sp,256 - 3dd0: 0204 addi s1,sp,256 - 3dd2: 10090003 lb zero,256(s2) - 3dd6: 0100 addi s0,sp,128 - 3dd8: 0200 addi s0,sp,256 - 3dda: 0204 addi s1,sp,256 - 3ddc: 00090003 lb zero,0(s2) - 3de0: 0100 addi s0,sp,128 - 3de2: 0200 addi s0,sp,256 - 3de4: 0204 addi s1,sp,256 - 3de6: 04090003 lb zero,64(s2) - 3dea: 0100 addi s0,sp,128 - 3dec: 0200 addi s0,sp,256 - 3dee: 0204 addi s1,sp,256 - 3df0: 10090003 lb zero,256(s2) - 3df4: 0100 addi s0,sp,128 - 3df6: 0200 addi s0,sp,256 - 3df8: 0204 addi s1,sp,256 - 3dfa: 00090003 lb zero,0(s2) - 3dfe: 0100 addi s0,sp,128 - 3e00: 0200 addi s0,sp,256 - 3e02: 0204 addi s1,sp,256 - 3e04: 00090003 lb zero,0(s2) - 3e08: 0100 addi s0,sp,128 - 3e0a: 0200 addi s0,sp,256 - 3e0c: 0904 addi s1,sp,144 - 3e0e: 04090003 lb zero,64(s2) - 3e12: 0100 addi s0,sp,128 - 3e14: 0200 addi s0,sp,256 - 3e16: 0b04 addi s1,sp,400 - 3e18: 04090003 lb zero,64(s2) - 3e1c: 0100 addi s0,sp,128 - 3e1e: 0200 addi s0,sp,256 - 3e20: 0b04 addi s1,sp,400 - 3e22: 08090003 lb zero,128(s2) - 3e26: 0100 addi s0,sp,128 - 3e28: 0200 addi s0,sp,256 - 3e2a: 0b04 addi s1,sp,400 - 3e2c: 20090003 lb zero,512(s2) - 3e30: 0100 addi s0,sp,128 - 3e32: 0200 addi s0,sp,256 - 3e34: 0b04 addi s1,sp,400 - 3e36: 00090003 lb zero,0(s2) - 3e3a: 0100 addi s0,sp,128 - 3e3c: 0200 addi s0,sp,256 - 3e3e: 0b04 addi s1,sp,400 - 3e40: 00090003 lb zero,0(s2) - 3e44: 0100 addi s0,sp,128 - 3e46: 0200 addi s0,sp,256 - 3e48: 0b04 addi s1,sp,400 - 3e4a: 00090003 lb zero,0(s2) - 3e4e: 0100 addi s0,sp,128 - 3e50: 0200 addi s0,sp,256 - 3e52: 0b04 addi s1,sp,400 - 3e54: 00090003 lb zero,0(s2) - 3e58: 0100 addi s0,sp,128 - 3e5a: 0200 addi s0,sp,256 - 3e5c: 0b04 addi s1,sp,400 - 3e5e: 00090003 lb zero,0(s2) - 3e62: 0100 addi s0,sp,128 - 3e64: 0200 addi s0,sp,256 - 3e66: 0b04 addi s1,sp,400 - 3e68: 00090003 lb zero,0(s2) - 3e6c: 0100 addi s0,sp,128 - 3e6e: 0200 addi s0,sp,256 - 3e70: 0b04 addi s1,sp,400 - 3e72: 00090003 lb zero,0(s2) - 3e76: 0100 addi s0,sp,128 - 3e78: 0200 addi s0,sp,256 - 3e7a: 0b04 addi s1,sp,400 - 3e7c: 04090003 lb zero,64(s2) - 3e80: 0100 addi s0,sp,128 - 3e82: 0200 addi s0,sp,256 - 3e84: 0b04 addi s1,sp,400 - 3e86: 00090003 lb zero,0(s2) - 3e8a: 0100 addi s0,sp,128 - 3e8c: 0200 addi s0,sp,256 - 3e8e: 0b04 addi s1,sp,400 - 3e90: 08090003 lb zero,128(s2) - 3e94: 0100 addi s0,sp,128 - 3e96: 0200 addi s0,sp,256 - 3e98: 0b04 addi s1,sp,400 - 3e9a: 10090003 lb zero,256(s2) - 3e9e: 0100 addi s0,sp,128 - 3ea0: 0200 addi s0,sp,256 - 3ea2: 0b04 addi s1,sp,400 - 3ea4: 00090003 lb zero,0(s2) - 3ea8: 0100 addi s0,sp,128 - 3eaa: 0200 addi s0,sp,256 - 3eac: 0b04 addi s1,sp,400 - 3eae: 00090003 lb zero,0(s2) - 3eb2: 0100 addi s0,sp,128 - 3eb4: 0200 addi s0,sp,256 - 3eb6: 0c04 addi s1,sp,528 - 3eb8: 04090003 lb zero,64(s2) - 3ebc: 0100 addi s0,sp,128 - 3ebe: 0200 addi s0,sp,256 - 3ec0: 0e04 addi s1,sp,784 - 3ec2: 08090003 lb zero,128(s2) - 3ec6: 0100 addi s0,sp,128 - 3ec8: 0200 addi s0,sp,256 - 3eca: 0e04 addi s1,sp,784 - 3ecc: 10090003 lb zero,256(s2) - 3ed0: 0100 addi s0,sp,128 - 3ed2: 0200 addi s0,sp,256 - 3ed4: 0e04 addi s1,sp,784 - 3ed6: 20090003 lb zero,512(s2) - 3eda: 0100 addi s0,sp,128 - 3edc: 0200 addi s0,sp,256 - 3ede: 0e04 addi s1,sp,784 - 3ee0: 00090003 lb zero,0(s2) - 3ee4: 0100 addi s0,sp,128 - 3ee6: 0200 addi s0,sp,256 - 3ee8: 0e04 addi s1,sp,784 - 3eea: 00090003 lb zero,0(s2) - 3eee: 0100 addi s0,sp,128 - 3ef0: 0200 addi s0,sp,256 - 3ef2: 0e04 addi s1,sp,784 - 3ef4: 00090003 lb zero,0(s2) - 3ef8: 0100 addi s0,sp,128 - 3efa: 0200 addi s0,sp,256 - 3efc: 0e04 addi s1,sp,784 - 3efe: 00090003 lb zero,0(s2) - 3f02: 0100 addi s0,sp,128 - 3f04: 0200 addi s0,sp,256 - 3f06: 0e04 addi s1,sp,784 - 3f08: 00090003 lb zero,0(s2) - 3f0c: 0100 addi s0,sp,128 - 3f0e: 0200 addi s0,sp,256 - 3f10: 0e04 addi s1,sp,784 - 3f12: 00090003 lb zero,0(s2) - 3f16: 0100 addi s0,sp,128 - 3f18: 0200 addi s0,sp,256 - 3f1a: 0e04 addi s1,sp,784 - 3f1c: 00090003 lb zero,0(s2) - 3f20: 0100 addi s0,sp,128 - 3f22: 0200 addi s0,sp,256 - 3f24: 0e04 addi s1,sp,784 - 3f26: 04090003 lb zero,64(s2) - 3f2a: 0100 addi s0,sp,128 - 3f2c: 0200 addi s0,sp,256 - 3f2e: 0e04 addi s1,sp,784 - 3f30: 00090003 lb zero,0(s2) - 3f34: 0100 addi s0,sp,128 - 3f36: 0200 addi s0,sp,256 - 3f38: 0e04 addi s1,sp,784 - 3f3a: 04090003 lb zero,64(s2) - 3f3e: 0100 addi s0,sp,128 - 3f40: 0200 addi s0,sp,256 - 3f42: 0e04 addi s1,sp,784 - 3f44: 10090003 lb zero,256(s2) - 3f48: 0100 addi s0,sp,128 - 3f4a: 0200 addi s0,sp,256 - 3f4c: 0e04 addi s1,sp,784 - 3f4e: 00090003 lb zero,0(s2) - 3f52: 0100 addi s0,sp,128 - 3f54: 0200 addi s0,sp,256 - 3f56: 0e04 addi s1,sp,784 - 3f58: 00090003 lb zero,0(s2) - 3f5c: 0100 addi s0,sp,128 - 3f5e: 0200 addi s0,sp,256 - 3f60: 0f04 addi s1,sp,912 - 3f62: 04090003 lb zero,64(s2) - 3f66: 0100 addi s0,sp,128 - 3f68: 0200 addi s0,sp,256 - 3f6a: 1104 addi s1,sp,160 - 3f6c: 04090003 lb zero,64(s2) - 3f70: 0100 addi s0,sp,128 - 3f72: 0200 addi s0,sp,256 - 3f74: 1104 addi s1,sp,160 - 3f76: 08090003 lb zero,128(s2) - 3f7a: 0100 addi s0,sp,128 - 3f7c: 0200 addi s0,sp,256 - 3f7e: 1104 addi s1,sp,160 - 3f80: 18090003 lb zero,384(s2) - 3f84: 0100 addi s0,sp,128 - 3f86: 0200 addi s0,sp,256 - 3f88: 1104 addi s1,sp,160 - 3f8a: 00090003 lb zero,0(s2) - 3f8e: 0100 addi s0,sp,128 - 3f90: 0200 addi s0,sp,256 - 3f92: 1104 addi s1,sp,160 - 3f94: 00090003 lb zero,0(s2) - 3f98: 0100 addi s0,sp,128 - 3f9a: 0200 addi s0,sp,256 - 3f9c: 1104 addi s1,sp,160 - 3f9e: 00090003 lb zero,0(s2) - 3fa2: 0100 addi s0,sp,128 - 3fa4: 0200 addi s0,sp,256 - 3fa6: 1104 addi s1,sp,160 - 3fa8: 00090003 lb zero,0(s2) - 3fac: 0100 addi s0,sp,128 - 3fae: 0200 addi s0,sp,256 - 3fb0: 1104 addi s1,sp,160 - 3fb2: 00090003 lb zero,0(s2) - 3fb6: 0100 addi s0,sp,128 - 3fb8: 0200 addi s0,sp,256 - 3fba: 1104 addi s1,sp,160 - 3fbc: 00090003 lb zero,0(s2) - 3fc0: 0100 addi s0,sp,128 - 3fc2: 0200 addi s0,sp,256 - 3fc4: 1104 addi s1,sp,160 - 3fc6: 00090003 lb zero,0(s2) - 3fca: 0100 addi s0,sp,128 - 3fcc: 0200 addi s0,sp,256 - 3fce: 1104 addi s1,sp,160 - 3fd0: 04090003 lb zero,64(s2) - 3fd4: 0100 addi s0,sp,128 - 3fd6: 0200 addi s0,sp,256 - 3fd8: 1104 addi s1,sp,160 - 3fda: 00090003 lb zero,0(s2) - 3fde: 0100 addi s0,sp,128 - 3fe0: 0200 addi s0,sp,256 - 3fe2: 1104 addi s1,sp,160 - 3fe4: 04090003 lb zero,64(s2) - 3fe8: 0100 addi s0,sp,128 - 3fea: 0200 addi s0,sp,256 - 3fec: 1104 addi s1,sp,160 - 3fee: 14090003 lb zero,320(s2) - 3ff2: 0100 addi s0,sp,128 - 3ff4: 0200 addi s0,sp,256 - 3ff6: 1104 addi s1,sp,160 - 3ff8: 00090003 lb zero,0(s2) - 3ffc: 0100 addi s0,sp,128 - 3ffe: 0200 addi s0,sp,256 - 4000: 1104 addi s1,sp,160 - 4002: 00090003 lb zero,0(s2) - 4006: 0100 addi s0,sp,128 - 4008: 0200 addi s0,sp,256 - 400a: 1204 addi s1,sp,288 - 400c: 04090003 lb zero,64(s2) - 4010: 0100 addi s0,sp,128 - 4012: 0200 addi s0,sp,256 - 4014: 1404 addi s1,sp,544 - 4016: 04090003 lb zero,64(s2) - 401a: 0100 addi s0,sp,128 - 401c: 0200 addi s0,sp,256 - 401e: 1404 addi s1,sp,544 - 4020: 14090003 lb zero,320(s2) - 4024: 0100 addi s0,sp,128 - 4026: 0200 addi s0,sp,256 - 4028: 1404 addi s1,sp,544 - 402a: 20090003 lb zero,512(s2) - 402e: 0100 addi s0,sp,128 - 4030: 0200 addi s0,sp,256 - 4032: 1404 addi s1,sp,544 - 4034: 00090003 lb zero,0(s2) - 4038: 0100 addi s0,sp,128 - 403a: 0200 addi s0,sp,256 - 403c: 1404 addi s1,sp,544 - 403e: 00090003 lb zero,0(s2) - 4042: 0100 addi s0,sp,128 - 4044: 0200 addi s0,sp,256 - 4046: 1404 addi s1,sp,544 - 4048: 00090003 lb zero,0(s2) - 404c: 0100 addi s0,sp,128 - 404e: 0200 addi s0,sp,256 - 4050: 1404 addi s1,sp,544 - 4052: 00090003 lb zero,0(s2) - 4056: 0100 addi s0,sp,128 - 4058: 0200 addi s0,sp,256 - 405a: 1404 addi s1,sp,544 - 405c: 00090003 lb zero,0(s2) - 4060: 0100 addi s0,sp,128 - 4062: 0200 addi s0,sp,256 - 4064: 1404 addi s1,sp,544 - 4066: 00090003 lb zero,0(s2) - 406a: 0100 addi s0,sp,128 - 406c: 0200 addi s0,sp,256 - 406e: 1404 addi s1,sp,544 - 4070: 00090003 lb zero,0(s2) - 4074: 0100 addi s0,sp,128 - 4076: 0200 addi s0,sp,256 - 4078: 1404 addi s1,sp,544 - 407a: 04090003 lb zero,64(s2) - 407e: 0100 addi s0,sp,128 - 4080: 0200 addi s0,sp,256 - 4082: 1404 addi s1,sp,544 - 4084: 00090003 lb zero,0(s2) - 4088: 0100 addi s0,sp,128 - 408a: 0200 addi s0,sp,256 - 408c: 1404 addi s1,sp,544 - 408e: 04090003 lb zero,64(s2) - 4092: 0100 addi s0,sp,128 - 4094: 0200 addi s0,sp,256 - 4096: 1404 addi s1,sp,544 - 4098: 10090003 lb zero,256(s2) - 409c: 0100 addi s0,sp,128 - 409e: 0200 addi s0,sp,256 - 40a0: 1404 addi s1,sp,544 - 40a2: 00090003 lb zero,0(s2) - 40a6: 0100 addi s0,sp,128 - 40a8: 0200 addi s0,sp,256 - 40aa: 1404 addi s1,sp,544 - 40ac: 00090003 lb zero,0(s2) - 40b0: 0100 addi s0,sp,128 - 40b2: 0200 addi s0,sp,256 - 40b4: 1504 addi s1,sp,672 - 40b6: 04090003 lb zero,64(s2) - 40ba: 0100 addi s0,sp,128 - 40bc: 0200 addi s0,sp,256 - 40be: 1704 addi s1,sp,928 - 40c0: 04090003 lb zero,64(s2) - 40c4: 0100 addi s0,sp,128 - 40c6: 0200 addi s0,sp,256 - 40c8: 1704 addi s1,sp,928 - 40ca: 14090003 lb zero,320(s2) - 40ce: 0100 addi s0,sp,128 - 40d0: 0200 addi s0,sp,256 - 40d2: 1704 addi s1,sp,928 - 40d4: 1c090003 lb zero,448(s2) - 40d8: 0100 addi s0,sp,128 - 40da: 0200 addi s0,sp,256 - 40dc: 1704 addi s1,sp,928 - 40de: 00090003 lb zero,0(s2) - 40e2: 0100 addi s0,sp,128 - 40e4: 0200 addi s0,sp,256 - 40e6: 1704 addi s1,sp,928 - 40e8: 00090003 lb zero,0(s2) - 40ec: 0100 addi s0,sp,128 - 40ee: 0200 addi s0,sp,256 - 40f0: 1704 addi s1,sp,928 - 40f2: 00090003 lb zero,0(s2) - 40f6: 0100 addi s0,sp,128 - 40f8: 0200 addi s0,sp,256 - 40fa: 1704 addi s1,sp,928 - 40fc: 00090003 lb zero,0(s2) - 4100: 0100 addi s0,sp,128 - 4102: 0200 addi s0,sp,256 - 4104: 1704 addi s1,sp,928 - 4106: 00090003 lb zero,0(s2) - 410a: 0100 addi s0,sp,128 - 410c: 0200 addi s0,sp,256 - 410e: 1704 addi s1,sp,928 - 4110: 00090003 lb zero,0(s2) - 4114: 0100 addi s0,sp,128 - 4116: 0200 addi s0,sp,256 - 4118: 1704 addi s1,sp,928 - 411a: 00090003 lb zero,0(s2) - 411e: 0100 addi s0,sp,128 - 4120: 0200 addi s0,sp,256 - 4122: 1704 addi s1,sp,928 - 4124: 04090003 lb zero,64(s2) - 4128: 0100 addi s0,sp,128 - 412a: 0200 addi s0,sp,256 - 412c: 1704 addi s1,sp,928 - 412e: 00090003 lb zero,0(s2) - 4132: 0100 addi s0,sp,128 - 4134: 0200 addi s0,sp,256 - 4136: 1704 addi s1,sp,928 - 4138: 04090003 lb zero,64(s2) - 413c: 0100 addi s0,sp,128 - 413e: 0200 addi s0,sp,256 - 4140: 1704 addi s1,sp,928 - 4142: 14090003 lb zero,320(s2) - 4146: 0100 addi s0,sp,128 - 4148: 0200 addi s0,sp,256 - 414a: 1704 addi s1,sp,928 - 414c: 00090003 lb zero,0(s2) - 4150: 0100 addi s0,sp,128 - 4152: 0200 addi s0,sp,256 - 4154: 1704 addi s1,sp,928 - 4156: 00090003 lb zero,0(s2) - 415a: 0100 addi s0,sp,128 - 415c: 0200 addi s0,sp,256 - 415e: 1804 addi s1,sp,48 - 4160: 04090003 lb zero,64(s2) - 4164: 0100 addi s0,sp,128 - 4166: 0200 addi s0,sp,256 - 4168: 1a04 addi s1,sp,304 - 416a: 04090003 lb zero,64(s2) - 416e: 0100 addi s0,sp,128 - 4170: 0200 addi s0,sp,256 - 4172: 1a04 addi s1,sp,304 - 4174: 08090003 lb zero,128(s2) - 4178: 0100 addi s0,sp,128 - 417a: 0200 addi s0,sp,256 - 417c: 1a04 addi s1,sp,304 - 417e: 28090003 lb zero,640(s2) - 4182: 0100 addi s0,sp,128 - 4184: 0200 addi s0,sp,256 - 4186: 1a04 addi s1,sp,304 - 4188: 00090003 lb zero,0(s2) - 418c: 0100 addi s0,sp,128 - 418e: 0200 addi s0,sp,256 - 4190: 1a04 addi s1,sp,304 - 4192: 00090003 lb zero,0(s2) - 4196: 0100 addi s0,sp,128 - 4198: 0200 addi s0,sp,256 - 419a: 1a04 addi s1,sp,304 - 419c: 00090003 lb zero,0(s2) - 41a0: 0100 addi s0,sp,128 - 41a2: 0200 addi s0,sp,256 - 41a4: 1a04 addi s1,sp,304 - 41a6: 00090003 lb zero,0(s2) - 41aa: 0100 addi s0,sp,128 - 41ac: 0200 addi s0,sp,256 - 41ae: 1a04 addi s1,sp,304 - 41b0: 00090003 lb zero,0(s2) - 41b4: 0100 addi s0,sp,128 - 41b6: 0200 addi s0,sp,256 - 41b8: 1a04 addi s1,sp,304 - 41ba: 00090003 lb zero,0(s2) - 41be: 0100 addi s0,sp,128 - 41c0: 0200 addi s0,sp,256 - 41c2: 1a04 addi s1,sp,304 - 41c4: 00090003 lb zero,0(s2) - 41c8: 0100 addi s0,sp,128 - 41ca: 0200 addi s0,sp,256 - 41cc: 1a04 addi s1,sp,304 - 41ce: 00090003 lb zero,0(s2) - 41d2: 0100 addi s0,sp,128 - 41d4: 0200 addi s0,sp,256 - 41d6: 1a04 addi s1,sp,304 - 41d8: 00090003 lb zero,0(s2) - 41dc: 0100 addi s0,sp,128 - 41de: 0200 addi s0,sp,256 - 41e0: 1a04 addi s1,sp,304 - 41e2: 00090003 lb zero,0(s2) - 41e6: 0100 addi s0,sp,128 - 41e8: 0200 addi s0,sp,256 - 41ea: 1a04 addi s1,sp,304 - 41ec: 00090003 lb zero,0(s2) - 41f0: 0100 addi s0,sp,128 - 41f2: 0200 addi s0,sp,256 - 41f4: 1a04 addi s1,sp,304 - 41f6: 10090003 lb zero,256(s2) - 41fa: 0100 addi s0,sp,128 - 41fc: 0200 addi s0,sp,256 - 41fe: 1a04 addi s1,sp,304 - 4200: 00090003 lb zero,0(s2) - 4204: 0100 addi s0,sp,128 - 4206: 0200 addi s0,sp,256 - 4208: 1a04 addi s1,sp,304 - 420a: 04090003 lb zero,64(s2) - 420e: 0100 addi s0,sp,128 - 4210: 0200 addi s0,sp,256 - 4212: 1a04 addi s1,sp,304 - 4214: 00090003 lb zero,0(s2) - 4218: 0100 addi s0,sp,128 - 421a: 0200 addi s0,sp,256 - 421c: 1a04 addi s1,sp,304 - 421e: 04090003 lb zero,64(s2) - 4222: 0100 addi s0,sp,128 - 4224: 0200 addi s0,sp,256 - 4226: 1a04 addi s1,sp,304 - 4228: 00090003 lb zero,0(s2) - 422c: 0100 addi s0,sp,128 - 422e: 0200 addi s0,sp,256 - 4230: 1a04 addi s1,sp,304 - 4232: 00090003 lb zero,0(s2) - 4236: 0100 addi s0,sp,128 - 4238: 0200 addi s0,sp,256 - 423a: 1a04 addi s1,sp,304 - 423c: 00090003 lb zero,0(s2) - 4240: 0100 addi s0,sp,128 - 4242: 0200 addi s0,sp,256 - 4244: 1a04 addi s1,sp,304 - 4246: 00090003 lb zero,0(s2) - 424a: 0100 addi s0,sp,128 - 424c: 0200 addi s0,sp,256 - 424e: 1a04 addi s1,sp,304 - 4250: 1c090003 lb zero,448(s2) - 4254: 0100 addi s0,sp,128 - 4256: 0200 addi s0,sp,256 - 4258: 1a04 addi s1,sp,304 - 425a: 08090003 lb zero,128(s2) - 425e: 0100 addi s0,sp,128 - 4260: 0200 addi s0,sp,256 - 4262: 1a04 addi s1,sp,304 - 4264: 04090003 lb zero,64(s2) - 4268: 0100 addi s0,sp,128 - 426a: 0200 addi s0,sp,256 - 426c: 1a04 addi s1,sp,304 - 426e: 00090003 lb zero,0(s2) - 4272: 0100 addi s0,sp,128 - 4274: 0200 addi s0,sp,256 - 4276: 1a04 addi s1,sp,304 - 4278: 08090003 lb zero,128(s2) - 427c: 0100 addi s0,sp,128 - 427e: 0200 addi s0,sp,256 - 4280: 1a04 addi s1,sp,304 - 4282: 00090003 lb zero,0(s2) - 4286: 0100 addi s0,sp,128 - 4288: 0200 addi s0,sp,256 - 428a: 1a04 addi s1,sp,304 - 428c: 00090003 lb zero,0(s2) - 4290: 0100 addi s0,sp,128 - 4292: 0200 addi s0,sp,256 - 4294: 1a04 addi s1,sp,304 - 4296: 00090003 lb zero,0(s2) - 429a: 0100 addi s0,sp,128 - 429c: 0200 addi s0,sp,256 - 429e: 1a04 addi s1,sp,304 - 42a0: 00090003 lb zero,0(s2) - 42a4: 0100 addi s0,sp,128 - 42a6: 0200 addi s0,sp,256 - 42a8: 1a04 addi s1,sp,304 - 42aa: 04090003 lb zero,64(s2) - 42ae: 0100 addi s0,sp,128 - 42b0: 0200 addi s0,sp,256 - 42b2: 1a04 addi s1,sp,304 - 42b4: 0c090003 lb zero,192(s2) - 42b8: 0100 addi s0,sp,128 - 42ba: 0200 addi s0,sp,256 - 42bc: 1a04 addi s1,sp,304 - 42be: 04090003 lb zero,64(s2) - 42c2: 0100 addi s0,sp,128 - 42c4: 0200 addi s0,sp,256 - 42c6: 1a04 addi s1,sp,304 - 42c8: 00090003 lb zero,0(s2) - 42cc: 0100 addi s0,sp,128 - 42ce: 0200 addi s0,sp,256 - 42d0: 1a04 addi s1,sp,304 - 42d2: 0c090003 lb zero,192(s2) - 42d6: 0100 addi s0,sp,128 - 42d8: 0200 addi s0,sp,256 - 42da: 1a04 addi s1,sp,304 - 42dc: 00090003 lb zero,0(s2) - 42e0: 0100 addi s0,sp,128 - 42e2: 0200 addi s0,sp,256 - 42e4: 1a04 addi s1,sp,304 - 42e6: 00090003 lb zero,0(s2) - 42ea: 0100 addi s0,sp,128 - 42ec: 0200 addi s0,sp,256 - 42ee: 1a04 addi s1,sp,304 - 42f0: 00090003 lb zero,0(s2) - 42f4: 0100 addi s0,sp,128 - 42f6: 0200 addi s0,sp,256 - 42f8: 1a04 addi s1,sp,304 - 42fa: 00090003 lb zero,0(s2) - 42fe: 0100 addi s0,sp,128 - 4300: 0200 addi s0,sp,256 - 4302: 1a04 addi s1,sp,304 - 4304: 14090003 lb zero,320(s2) - 4308: 0100 addi s0,sp,128 - 430a: 0200 addi s0,sp,256 - 430c: 1a04 addi s1,sp,304 - 430e: 00090003 lb zero,0(s2) - 4312: 0100 addi s0,sp,128 - 4314: 0200 addi s0,sp,256 - 4316: 1a04 addi s1,sp,304 - 4318: 04090003 lb zero,64(s2) - 431c: 0100 addi s0,sp,128 - 431e: 0200 addi s0,sp,256 - 4320: 1a04 addi s1,sp,304 - 4322: 00090003 lb zero,0(s2) - 4326: 0100 addi s0,sp,128 - 4328: 0200 addi s0,sp,256 - 432a: 1a04 addi s1,sp,304 - 432c: 08090003 lb zero,128(s2) - 4330: 0100 addi s0,sp,128 - 4332: 0200 addi s0,sp,256 - 4334: 1a04 addi s1,sp,304 - 4336: 00090003 lb zero,0(s2) - 433a: 0100 addi s0,sp,128 - 433c: 0200 addi s0,sp,256 - 433e: 1a04 addi s1,sp,304 - 4340: 28090003 lb zero,640(s2) - 4344: 0100 addi s0,sp,128 - 4346: 0200 addi s0,sp,256 - 4348: 1a04 addi s1,sp,304 - 434a: 00090003 lb zero,0(s2) - 434e: 0100 addi s0,sp,128 - 4350: 0200 addi s0,sp,256 - 4352: 1a04 addi s1,sp,304 - 4354: 00090003 lb zero,0(s2) - 4358: 0100 addi s0,sp,128 - 435a: 0200 addi s0,sp,256 - 435c: 1a04 addi s1,sp,304 - 435e: 00090003 lb zero,0(s2) - 4362: 0100 addi s0,sp,128 - 4364: 0200 addi s0,sp,256 - 4366: 1a04 addi s1,sp,304 - 4368: 00090003 lb zero,0(s2) - 436c: 0100 addi s0,sp,128 - 436e: 0200 addi s0,sp,256 - 4370: 1a04 addi s1,sp,304 - 4372: 00090003 lb zero,0(s2) - 4376: 0100 addi s0,sp,128 - 4378: 0200 addi s0,sp,256 - 437a: 1a04 addi s1,sp,304 - 437c: 00090003 lb zero,0(s2) - 4380: 0100 addi s0,sp,128 - 4382: 0200 addi s0,sp,256 - 4384: 1a04 addi s1,sp,304 - 4386: 00090003 lb zero,0(s2) - 438a: 0100 addi s0,sp,128 - 438c: 0200 addi s0,sp,256 - 438e: 1a04 addi s1,sp,304 - 4390: 00090003 lb zero,0(s2) - 4394: 0100 addi s0,sp,128 - 4396: 0200 addi s0,sp,256 - 4398: 1a04 addi s1,sp,304 - 439a: 00090003 lb zero,0(s2) - 439e: 0100 addi s0,sp,128 - 43a0: 0200 addi s0,sp,256 - 43a2: 1a04 addi s1,sp,304 - 43a4: 0c090003 lb zero,192(s2) - 43a8: 0100 addi s0,sp,128 - 43aa: 0200 addi s0,sp,256 - 43ac: 1a04 addi s1,sp,304 - 43ae: 0c090003 lb zero,192(s2) - 43b2: 0100 addi s0,sp,128 - 43b4: 0200 addi s0,sp,256 - 43b6: 1a04 addi s1,sp,304 - 43b8: 00090003 lb zero,0(s2) - 43bc: 0100 addi s0,sp,128 - 43be: 0200 addi s0,sp,256 - 43c0: 1a04 addi s1,sp,304 - 43c2: 00090003 lb zero,0(s2) - 43c6: 0100 addi s0,sp,128 - 43c8: 0200 addi s0,sp,256 - 43ca: 1b04 addi s1,sp,432 - 43cc: 04090003 lb zero,64(s2) - 43d0: 0100 addi s0,sp,128 - 43d2: 0200 addi s0,sp,256 - 43d4: 1d04 addi s1,sp,688 - 43d6: 04090003 lb zero,64(s2) - 43da: 0100 addi s0,sp,128 - 43dc: 0200 addi s0,sp,256 - 43de: 1d04 addi s1,sp,688 - 43e0: 34090003 lb zero,832(s2) - 43e4: 0100 addi s0,sp,128 - 43e6: 0200 addi s0,sp,256 - 43e8: 1d04 addi s1,sp,688 - 43ea: 00090003 lb zero,0(s2) - 43ee: 0100 addi s0,sp,128 - 43f0: 0200 addi s0,sp,256 - 43f2: 1d04 addi s1,sp,688 - 43f4: 00090003 lb zero,0(s2) - 43f8: 0100 addi s0,sp,128 - 43fa: 0200 addi s0,sp,256 - 43fc: 1d04 addi s1,sp,688 - 43fe: 00090003 lb zero,0(s2) - 4402: 0100 addi s0,sp,128 - 4404: 0200 addi s0,sp,256 - 4406: 1d04 addi s1,sp,688 - 4408: 00090003 lb zero,0(s2) - 440c: 0100 addi s0,sp,128 - 440e: 0200 addi s0,sp,256 - 4410: 1d04 addi s1,sp,688 - 4412: 00090003 lb zero,0(s2) - 4416: 0100 addi s0,sp,128 - 4418: 0200 addi s0,sp,256 - 441a: 1d04 addi s1,sp,688 - 441c: 00090003 lb zero,0(s2) - 4420: 0100 addi s0,sp,128 - 4422: 0200 addi s0,sp,256 - 4424: 1d04 addi s1,sp,688 - 4426: 00090003 lb zero,0(s2) - 442a: 0100 addi s0,sp,128 - 442c: 0200 addi s0,sp,256 - 442e: 1d04 addi s1,sp,688 - 4430: 00090003 lb zero,0(s2) - 4434: 0100 addi s0,sp,128 - 4436: 0200 addi s0,sp,256 - 4438: 1d04 addi s1,sp,688 - 443a: 04090003 lb zero,64(s2) - 443e: 0100 addi s0,sp,128 - 4440: 0200 addi s0,sp,256 - 4442: 1d04 addi s1,sp,688 - 4444: 00090003 lb zero,0(s2) - 4448: 0100 addi s0,sp,128 - 444a: 0200 addi s0,sp,256 - 444c: 1d04 addi s1,sp,688 - 444e: 0c090003 lb zero,192(s2) - 4452: 0100 addi s0,sp,128 - 4454: 0200 addi s0,sp,256 - 4456: 1d04 addi s1,sp,688 - 4458: 00090003 lb zero,0(s2) - 445c: 0100 addi s0,sp,128 - 445e: 0200 addi s0,sp,256 - 4460: 1d04 addi s1,sp,688 - 4462: 04090003 lb zero,64(s2) - 4466: 0100 addi s0,sp,128 - 4468: 0200 addi s0,sp,256 - 446a: 1d04 addi s1,sp,688 - 446c: 04090003 lb zero,64(s2) - 4470: 0100 addi s0,sp,128 - 4472: 0200 addi s0,sp,256 - 4474: 1e04 addi s1,sp,816 - 4476: 04090003 lb zero,64(s2) - 447a: 0100 addi s0,sp,128 - 447c: 0200 addi s0,sp,256 - 447e: 2004 fld fs1,0(s0) - 4480: 04090003 lb zero,64(s2) - 4484: 0100 addi s0,sp,128 - 4486: 0200 addi s0,sp,256 - 4488: 2004 fld fs1,0(s0) - 448a: 10090003 lb zero,256(s2) - 448e: 0100 addi s0,sp,128 - 4490: 0200 addi s0,sp,256 - 4492: 2004 fld fs1,0(s0) - 4494: 14090003 lb zero,320(s2) - 4498: 0100 addi s0,sp,128 - 449a: 0200 addi s0,sp,256 - 449c: 2004 fld fs1,0(s0) - 449e: 00090003 lb zero,0(s2) - 44a2: 0100 addi s0,sp,128 - 44a4: 0200 addi s0,sp,256 - 44a6: 2004 fld fs1,0(s0) - 44a8: 00090003 lb zero,0(s2) - 44ac: 0100 addi s0,sp,128 - 44ae: 0200 addi s0,sp,256 - 44b0: 2004 fld fs1,0(s0) - 44b2: 00090003 lb zero,0(s2) - 44b6: 0100 addi s0,sp,128 - 44b8: 0200 addi s0,sp,256 - 44ba: 2004 fld fs1,0(s0) - 44bc: 00090003 lb zero,0(s2) - 44c0: 0100 addi s0,sp,128 - 44c2: 0200 addi s0,sp,256 - 44c4: 2004 fld fs1,0(s0) - 44c6: 00090003 lb zero,0(s2) - 44ca: 0100 addi s0,sp,128 - 44cc: 0200 addi s0,sp,256 - 44ce: 2004 fld fs1,0(s0) - 44d0: 00090003 lb zero,0(s2) - 44d4: 0100 addi s0,sp,128 - 44d6: 0200 addi s0,sp,256 - 44d8: 2004 fld fs1,0(s0) - 44da: 00090003 lb zero,0(s2) - 44de: 0100 addi s0,sp,128 - 44e0: 0200 addi s0,sp,256 - 44e2: 2004 fld fs1,0(s0) - 44e4: 04090003 lb zero,64(s2) - 44e8: 0100 addi s0,sp,128 - 44ea: 0200 addi s0,sp,256 - 44ec: 2004 fld fs1,0(s0) - 44ee: 00090003 lb zero,0(s2) - 44f2: 0100 addi s0,sp,128 - 44f4: 0200 addi s0,sp,256 - 44f6: 2004 fld fs1,0(s0) - 44f8: 04090003 lb zero,64(s2) - 44fc: 0100 addi s0,sp,128 - 44fe: 0200 addi s0,sp,256 - 4500: 2004 fld fs1,0(s0) - 4502: 14090003 lb zero,320(s2) - 4506: 0100 addi s0,sp,128 - 4508: 0200 addi s0,sp,256 - 450a: 2004 fld fs1,0(s0) - 450c: 00090003 lb zero,0(s2) - 4510: 0100 addi s0,sp,128 - 4512: 0200 addi s0,sp,256 - 4514: 2004 fld fs1,0(s0) - 4516: 00090003 lb zero,0(s2) - 451a: 0100 addi s0,sp,128 - 451c: 0200 addi s0,sp,256 - 451e: 2104 fld fs1,0(a0) - 4520: 04090003 lb zero,64(s2) - 4524: 0100 addi s0,sp,128 - 4526: 0200 addi s0,sp,256 - 4528: 2304 fld fs1,0(a4) - 452a: 04090003 lb zero,64(s2) - 452e: 0100 addi s0,sp,128 - 4530: 0200 addi s0,sp,256 - 4532: 2304 fld fs1,0(a4) - 4534: 10090003 lb zero,256(s2) - 4538: 0100 addi s0,sp,128 - 453a: 0200 addi s0,sp,256 - 453c: 2304 fld fs1,0(a4) - 453e: 18090003 lb zero,384(s2) - 4542: 0100 addi s0,sp,128 - 4544: 0200 addi s0,sp,256 - 4546: 2304 fld fs1,0(a4) - 4548: 00090003 lb zero,0(s2) - 454c: 0100 addi s0,sp,128 - 454e: 0200 addi s0,sp,256 - 4550: 2304 fld fs1,0(a4) - 4552: 00090003 lb zero,0(s2) - 4556: 0100 addi s0,sp,128 - 4558: 0200 addi s0,sp,256 - 455a: 2304 fld fs1,0(a4) - 455c: 00090003 lb zero,0(s2) - 4560: 0100 addi s0,sp,128 - 4562: 0200 addi s0,sp,256 - 4564: 2304 fld fs1,0(a4) - 4566: 00090003 lb zero,0(s2) - 456a: 0100 addi s0,sp,128 - 456c: 0200 addi s0,sp,256 - 456e: 2304 fld fs1,0(a4) - 4570: 00090003 lb zero,0(s2) - 4574: 0100 addi s0,sp,128 - 4576: 0200 addi s0,sp,256 - 4578: 2304 fld fs1,0(a4) - 457a: 00090003 lb zero,0(s2) - 457e: 0100 addi s0,sp,128 - 4580: 0200 addi s0,sp,256 - 4582: 2304 fld fs1,0(a4) - 4584: 00090003 lb zero,0(s2) - 4588: 0100 addi s0,sp,128 - 458a: 0200 addi s0,sp,256 - 458c: 2304 fld fs1,0(a4) - 458e: 04090003 lb zero,64(s2) - 4592: 0100 addi s0,sp,128 - 4594: 0200 addi s0,sp,256 - 4596: 2304 fld fs1,0(a4) - 4598: 00090003 lb zero,0(s2) - 459c: 0100 addi s0,sp,128 - 459e: 0200 addi s0,sp,256 - 45a0: 2304 fld fs1,0(a4) - 45a2: 00090003 lb zero,0(s2) - 45a6: 0100 addi s0,sp,128 - 45a8: 0200 addi s0,sp,256 - 45aa: 2304 fld fs1,0(a4) - 45ac: 14090003 lb zero,320(s2) - 45b0: 0100 addi s0,sp,128 - 45b2: 0200 addi s0,sp,256 - 45b4: 2304 fld fs1,0(a4) - 45b6: 00090003 lb zero,0(s2) - 45ba: 0100 addi s0,sp,128 - 45bc: 0200 addi s0,sp,256 - 45be: 2304 fld fs1,0(a4) - 45c0: 00090003 lb zero,0(s2) - 45c4: 0100 addi s0,sp,128 - 45c6: 0200 addi s0,sp,256 - 45c8: 2404 fld fs1,8(s0) - 45ca: 04090003 lb zero,64(s2) - 45ce: 0100 addi s0,sp,128 - 45d0: 0200 addi s0,sp,256 - 45d2: 2604 fld fs1,8(a2) - 45d4: 04090003 lb zero,64(s2) - 45d8: 0100 addi s0,sp,128 - 45da: 0200 addi s0,sp,256 - 45dc: 2604 fld fs1,8(a2) - 45de: 78090003 lb zero,1920(s2) - 45e2: 0100 addi s0,sp,128 - 45e4: 0200 addi s0,sp,256 - 45e6: 2604 fld fs1,8(a2) - 45e8: 00090003 lb zero,0(s2) - 45ec: 0100 addi s0,sp,128 - 45ee: 0200 addi s0,sp,256 - 45f0: 2604 fld fs1,8(a2) - 45f2: 00090003 lb zero,0(s2) - 45f6: 0100 addi s0,sp,128 - 45f8: 0200 addi s0,sp,256 - 45fa: 2604 fld fs1,8(a2) - 45fc: 00090003 lb zero,0(s2) - 4600: 0100 addi s0,sp,128 - 4602: 0200 addi s0,sp,256 - 4604: 2604 fld fs1,8(a2) - 4606: 00090003 lb zero,0(s2) - 460a: 0100 addi s0,sp,128 - 460c: 0200 addi s0,sp,256 - 460e: 2604 fld fs1,8(a2) - 4610: 00090003 lb zero,0(s2) - 4614: 0100 addi s0,sp,128 - 4616: 0200 addi s0,sp,256 - 4618: 2604 fld fs1,8(a2) - 461a: 00090003 lb zero,0(s2) - 461e: 0100 addi s0,sp,128 - 4620: 0200 addi s0,sp,256 - 4622: 2604 fld fs1,8(a2) - 4624: 00090003 lb zero,0(s2) - 4628: 0100 addi s0,sp,128 - 462a: 0200 addi s0,sp,256 - 462c: 2604 fld fs1,8(a2) - 462e: 00090003 lb zero,0(s2) - 4632: 0100 addi s0,sp,128 - 4634: 0200 addi s0,sp,256 - 4636: 2604 fld fs1,8(a2) - 4638: 00090003 lb zero,0(s2) - 463c: 0100 addi s0,sp,128 - 463e: 0200 addi s0,sp,256 - 4640: 2604 fld fs1,8(a2) - 4642: 00090003 lb zero,0(s2) - 4646: 0100 addi s0,sp,128 - 4648: 0200 addi s0,sp,256 - 464a: 2604 fld fs1,8(a2) - 464c: 00090003 lb zero,0(s2) - 4650: 0100 addi s0,sp,128 - 4652: 0200 addi s0,sp,256 - 4654: 2604 fld fs1,8(a2) - 4656: 00090003 lb zero,0(s2) - 465a: 0100 addi s0,sp,128 - 465c: 0200 addi s0,sp,256 - 465e: 2604 fld fs1,8(a2) - 4660: 00090003 lb zero,0(s2) - 4664: 0100 addi s0,sp,128 - 4666: 0200 addi s0,sp,256 - 4668: 2604 fld fs1,8(a2) - 466a: 00090003 lb zero,0(s2) - 466e: 0100 addi s0,sp,128 - 4670: 0200 addi s0,sp,256 - 4672: 2604 fld fs1,8(a2) - 4674: 00090003 lb zero,0(s2) - 4678: 0100 addi s0,sp,128 - 467a: 0200 addi s0,sp,256 - 467c: 2604 fld fs1,8(a2) - 467e: 00090003 lb zero,0(s2) - 4682: 0100 addi s0,sp,128 - 4684: 0200 addi s0,sp,256 - 4686: 2604 fld fs1,8(a2) - 4688: 00090003 lb zero,0(s2) - 468c: 0100 addi s0,sp,128 - 468e: 0200 addi s0,sp,256 - 4690: 2604 fld fs1,8(a2) - 4692: 00090003 lb zero,0(s2) - 4696: 0100 addi s0,sp,128 - 4698: 0200 addi s0,sp,256 - 469a: 2604 fld fs1,8(a2) - 469c: 00090003 lb zero,0(s2) - 46a0: 0100 addi s0,sp,128 - 46a2: 0200 addi s0,sp,256 - 46a4: 2604 fld fs1,8(a2) - 46a6: 00090003 lb zero,0(s2) - 46aa: 0100 addi s0,sp,128 - 46ac: 0200 addi s0,sp,256 - 46ae: 2604 fld fs1,8(a2) - 46b0: 00090003 lb zero,0(s2) - 46b4: 0100 addi s0,sp,128 - 46b6: 0200 addi s0,sp,256 - 46b8: 2604 fld fs1,8(a2) - 46ba: 00090003 lb zero,0(s2) - 46be: 0100 addi s0,sp,128 - 46c0: 0200 addi s0,sp,256 - 46c2: 2604 fld fs1,8(a2) - 46c4: 00090003 lb zero,0(s2) - 46c8: 0100 addi s0,sp,128 - 46ca: 0200 addi s0,sp,256 - 46cc: 2604 fld fs1,8(a2) - 46ce: 00090003 lb zero,0(s2) - 46d2: 0100 addi s0,sp,128 - 46d4: 0200 addi s0,sp,256 - 46d6: 2604 fld fs1,8(a2) - 46d8: 00090003 lb zero,0(s2) - 46dc: 0100 addi s0,sp,128 - 46de: 0200 addi s0,sp,256 - 46e0: 2604 fld fs1,8(a2) - 46e2: 00090003 lb zero,0(s2) - 46e6: 0100 addi s0,sp,128 - 46e8: 0200 addi s0,sp,256 - 46ea: 2604 fld fs1,8(a2) - 46ec: 00090003 lb zero,0(s2) - 46f0: 0100 addi s0,sp,128 - 46f2: 0200 addi s0,sp,256 - 46f4: 2604 fld fs1,8(a2) - 46f6: 00090003 lb zero,0(s2) - 46fa: 0100 addi s0,sp,128 - 46fc: 0200 addi s0,sp,256 - 46fe: 2604 fld fs1,8(a2) - 4700: 00090003 lb zero,0(s2) - 4704: 0100 addi s0,sp,128 - 4706: 0200 addi s0,sp,256 - 4708: 2604 fld fs1,8(a2) - 470a: 00090003 lb zero,0(s2) - 470e: 0100 addi s0,sp,128 - 4710: 0200 addi s0,sp,256 - 4712: 2604 fld fs1,8(a2) - 4714: 3c090003 lb zero,960(s2) - 4718: 0100 addi s0,sp,128 - 471a: 0200 addi s0,sp,256 - 471c: 2604 fld fs1,8(a2) - 471e: 00090003 lb zero,0(s2) - 4722: 0100 addi s0,sp,128 - 4724: 0200 addi s0,sp,256 - 4726: 2604 fld fs1,8(a2) - 4728: 00090003 lb zero,0(s2) - 472c: 0100 addi s0,sp,128 - 472e: 0200 addi s0,sp,256 - 4730: 2604 fld fs1,8(a2) - 4732: 00090003 lb zero,0(s2) - 4736: 0100 addi s0,sp,128 - 4738: 0200 addi s0,sp,256 - 473a: 2604 fld fs1,8(a2) - 473c: 00090003 lb zero,0(s2) - 4740: 0100 addi s0,sp,128 - 4742: 0200 addi s0,sp,256 - 4744: 2604 fld fs1,8(a2) - 4746: 00090003 lb zero,0(s2) - 474a: 0100 addi s0,sp,128 - 474c: 0200 addi s0,sp,256 - 474e: 2604 fld fs1,8(a2) - 4750: 00090003 lb zero,0(s2) - 4754: 0100 addi s0,sp,128 - 4756: 0200 addi s0,sp,256 - 4758: 2604 fld fs1,8(a2) - 475a: 00090003 lb zero,0(s2) - 475e: 0100 addi s0,sp,128 - 4760: 0200 addi s0,sp,256 - 4762: 2604 fld fs1,8(a2) - 4764: 00090003 lb zero,0(s2) - 4768: 0100 addi s0,sp,128 - 476a: 0200 addi s0,sp,256 - 476c: 2604 fld fs1,8(a2) - 476e: 00090003 lb zero,0(s2) - 4772: 0100 addi s0,sp,128 - 4774: 0200 addi s0,sp,256 - 4776: 2604 fld fs1,8(a2) - 4778: 00090003 lb zero,0(s2) - 477c: 0100 addi s0,sp,128 - 477e: 0200 addi s0,sp,256 - 4780: 2604 fld fs1,8(a2) - 4782: 00090003 lb zero,0(s2) - 4786: 0100 addi s0,sp,128 - 4788: 0200 addi s0,sp,256 - 478a: 2604 fld fs1,8(a2) - 478c: 00090003 lb zero,0(s2) - 4790: 0100 addi s0,sp,128 - 4792: 0200 addi s0,sp,256 - 4794: 2604 fld fs1,8(a2) - 4796: 00090003 lb zero,0(s2) - 479a: 0100 addi s0,sp,128 - 479c: 0200 addi s0,sp,256 - 479e: 2604 fld fs1,8(a2) - 47a0: 00090003 lb zero,0(s2) - 47a4: 0100 addi s0,sp,128 - 47a6: 0200 addi s0,sp,256 - 47a8: 2604 fld fs1,8(a2) - 47aa: 00090003 lb zero,0(s2) - 47ae: 0100 addi s0,sp,128 - 47b0: 0200 addi s0,sp,256 - 47b2: 2604 fld fs1,8(a2) - 47b4: 04090003 lb zero,64(s2) - 47b8: 0100 addi s0,sp,128 - 47ba: 0200 addi s0,sp,256 - 47bc: 2604 fld fs1,8(a2) - 47be: 14090003 lb zero,320(s2) - 47c2: 0100 addi s0,sp,128 - 47c4: 0200 addi s0,sp,256 - 47c6: 2604 fld fs1,8(a2) - 47c8: 00090003 lb zero,0(s2) - 47cc: 0100 addi s0,sp,128 - 47ce: 0200 addi s0,sp,256 - 47d0: 2604 fld fs1,8(a2) - 47d2: 00090003 lb zero,0(s2) - 47d6: 0100 addi s0,sp,128 - 47d8: 0200 addi s0,sp,256 - 47da: 2704 fld fs1,8(a4) - 47dc: 04090003 lb zero,64(s2) - 47e0: 0100 addi s0,sp,128 - 47e2: 0200 addi s0,sp,256 - 47e4: 2904 fld fs1,16(a0) - 47e6: 08090003 lb zero,128(s2) - 47ea: 0100 addi s0,sp,128 - 47ec: 0200 addi s0,sp,256 - 47ee: 2904 fld fs1,16(a0) - 47f0: 10090003 lb zero,256(s2) - 47f4: 0100 addi s0,sp,128 - 47f6: 0200 addi s0,sp,256 - 47f8: 2904 fld fs1,16(a0) - 47fa: 14090003 lb zero,320(s2) - 47fe: 0100 addi s0,sp,128 - 4800: 0200 addi s0,sp,256 - 4802: 2904 fld fs1,16(a0) - 4804: 00090003 lb zero,0(s2) - 4808: 0100 addi s0,sp,128 - 480a: 0200 addi s0,sp,256 - 480c: 2904 fld fs1,16(a0) - 480e: 00090003 lb zero,0(s2) - 4812: 0100 addi s0,sp,128 - 4814: 0200 addi s0,sp,256 - 4816: 2904 fld fs1,16(a0) - 4818: 00090003 lb zero,0(s2) - 481c: 0100 addi s0,sp,128 - 481e: 0200 addi s0,sp,256 - 4820: 2904 fld fs1,16(a0) - 4822: 00090003 lb zero,0(s2) - 4826: 0100 addi s0,sp,128 - 4828: 0200 addi s0,sp,256 - 482a: 2904 fld fs1,16(a0) - 482c: 00090003 lb zero,0(s2) - 4830: 0100 addi s0,sp,128 - 4832: 0200 addi s0,sp,256 - 4834: 2904 fld fs1,16(a0) - 4836: 00090003 lb zero,0(s2) - 483a: 0100 addi s0,sp,128 - 483c: 0200 addi s0,sp,256 - 483e: 2904 fld fs1,16(a0) - 4840: 00090003 lb zero,0(s2) - 4844: 0100 addi s0,sp,128 - 4846: 0200 addi s0,sp,256 - 4848: 2904 fld fs1,16(a0) - 484a: 04090003 lb zero,64(s2) - 484e: 0100 addi s0,sp,128 - 4850: 0200 addi s0,sp,256 - 4852: 2904 fld fs1,16(a0) - 4854: 00090003 lb zero,0(s2) - 4858: 0100 addi s0,sp,128 - 485a: 0200 addi s0,sp,256 - 485c: 2904 fld fs1,16(a0) - 485e: 00090003 lb zero,0(s2) - 4862: 0100 addi s0,sp,128 - 4864: 0200 addi s0,sp,256 - 4866: 2904 fld fs1,16(a0) - 4868: 14090003 lb zero,320(s2) - 486c: 0100 addi s0,sp,128 - 486e: 0200 addi s0,sp,256 - 4870: 2904 fld fs1,16(a0) - 4872: 00090003 lb zero,0(s2) - 4876: 0100 addi s0,sp,128 - 4878: 0200 addi s0,sp,256 - 487a: 2904 fld fs1,16(a0) - 487c: 00090003 lb zero,0(s2) - 4880: 0100 addi s0,sp,128 - 4882: 0200 addi s0,sp,256 - 4884: 2a04 fld fs1,16(a2) - 4886: 04090003 lb zero,64(s2) - 488a: 0100 addi s0,sp,128 - 488c: 0200 addi s0,sp,256 - 488e: 2c04 fld fs1,24(s0) - 4890: 04090003 lb zero,64(s2) - 4894: 0100 addi s0,sp,128 - 4896: 0200 addi s0,sp,256 - 4898: 2c04 fld fs1,24(s0) - 489a: 14090003 lb zero,320(s2) - 489e: 0100 addi s0,sp,128 - 48a0: 0200 addi s0,sp,256 - 48a2: 2c04 fld fs1,24(s0) - 48a4: 10090003 lb zero,256(s2) - 48a8: 0100 addi s0,sp,128 - 48aa: 0200 addi s0,sp,256 - 48ac: 2c04 fld fs1,24(s0) - 48ae: 00090003 lb zero,0(s2) - 48b2: 0100 addi s0,sp,128 - 48b4: 0200 addi s0,sp,256 - 48b6: 2c04 fld fs1,24(s0) - 48b8: 00090003 lb zero,0(s2) - 48bc: 0100 addi s0,sp,128 - 48be: 0200 addi s0,sp,256 - 48c0: 2c04 fld fs1,24(s0) - 48c2: 00090003 lb zero,0(s2) - 48c6: 0100 addi s0,sp,128 - 48c8: 0200 addi s0,sp,256 - 48ca: 2c04 fld fs1,24(s0) - 48cc: 00090003 lb zero,0(s2) - 48d0: 0100 addi s0,sp,128 - 48d2: 0200 addi s0,sp,256 - 48d4: 2c04 fld fs1,24(s0) - 48d6: 00090003 lb zero,0(s2) - 48da: 0100 addi s0,sp,128 - 48dc: 0200 addi s0,sp,256 - 48de: 2c04 fld fs1,24(s0) - 48e0: 00090003 lb zero,0(s2) - 48e4: 0100 addi s0,sp,128 - 48e6: 0200 addi s0,sp,256 - 48e8: 2c04 fld fs1,24(s0) - 48ea: 00090003 lb zero,0(s2) - 48ee: 0100 addi s0,sp,128 - 48f0: 0200 addi s0,sp,256 - 48f2: 2c04 fld fs1,24(s0) - 48f4: 00090003 lb zero,0(s2) - 48f8: 0100 addi s0,sp,128 - 48fa: 0200 addi s0,sp,256 - 48fc: 2c04 fld fs1,24(s0) - 48fe: 00090003 lb zero,0(s2) - 4902: 0100 addi s0,sp,128 - 4904: 0200 addi s0,sp,256 - 4906: 2c04 fld fs1,24(s0) - 4908: 04090003 lb zero,64(s2) - 490c: 0100 addi s0,sp,128 - 490e: 0200 addi s0,sp,256 - 4910: 2c04 fld fs1,24(s0) - 4912: 08090003 lb zero,128(s2) - 4916: 0100 addi s0,sp,128 - 4918: 0200 addi s0,sp,256 - 491a: 2c04 fld fs1,24(s0) - 491c: 08090003 lb zero,128(s2) - 4920: 0100 addi s0,sp,128 - 4922: 0200 addi s0,sp,256 - 4924: 2c04 fld fs1,24(s0) - 4926: 04090003 lb zero,64(s2) - 492a: 0100 addi s0,sp,128 - 492c: 0200 addi s0,sp,256 - 492e: 2d04 fld fs1,24(a0) - 4930: 04090003 lb zero,64(s2) - 4934: 0100 addi s0,sp,128 - 4936: 0200 addi s0,sp,256 - 4938: 2f04 fld fs1,24(a4) - 493a: 04090003 lb zero,64(s2) - 493e: 0100 addi s0,sp,128 - 4940: 0200 addi s0,sp,256 - 4942: 2f04 fld fs1,24(a4) - 4944: 08090003 lb zero,128(s2) - 4948: 0100 addi s0,sp,128 - 494a: 0200 addi s0,sp,256 - 494c: 2f04 fld fs1,24(a4) - 494e: 1c090003 lb zero,448(s2) - 4952: 0100 addi s0,sp,128 - 4954: 0200 addi s0,sp,256 - 4956: 2f04 fld fs1,24(a4) - 4958: 00090003 lb zero,0(s2) - 495c: 0100 addi s0,sp,128 - 495e: 0200 addi s0,sp,256 - 4960: 2f04 fld fs1,24(a4) - 4962: 00090003 lb zero,0(s2) - 4966: 0100 addi s0,sp,128 - 4968: 0200 addi s0,sp,256 - 496a: 2f04 fld fs1,24(a4) - 496c: 00090003 lb zero,0(s2) - 4970: 0100 addi s0,sp,128 - 4972: 0200 addi s0,sp,256 - 4974: 2f04 fld fs1,24(a4) - 4976: 00090003 lb zero,0(s2) - 497a: 0100 addi s0,sp,128 - 497c: 0200 addi s0,sp,256 - 497e: 2f04 fld fs1,24(a4) - 4980: 00090003 lb zero,0(s2) - 4984: 0100 addi s0,sp,128 - 4986: 0200 addi s0,sp,256 - 4988: 2f04 fld fs1,24(a4) - 498a: 00090003 lb zero,0(s2) - 498e: 0100 addi s0,sp,128 - 4990: 0200 addi s0,sp,256 - 4992: 2f04 fld fs1,24(a4) - 4994: 00090003 lb zero,0(s2) - 4998: 0100 addi s0,sp,128 - 499a: 0200 addi s0,sp,256 - 499c: 2f04 fld fs1,24(a4) - 499e: 04090003 lb zero,64(s2) - 49a2: 0100 addi s0,sp,128 - 49a4: 0200 addi s0,sp,256 - 49a6: 2f04 fld fs1,24(a4) - 49a8: 00090003 lb zero,0(s2) - 49ac: 0100 addi s0,sp,128 - 49ae: 0200 addi s0,sp,256 - 49b0: 2f04 fld fs1,24(a4) - 49b2: 00090003 lb zero,0(s2) - 49b6: 0100 addi s0,sp,128 - 49b8: 0200 addi s0,sp,256 - 49ba: 2f04 fld fs1,24(a4) - 49bc: 14090003 lb zero,320(s2) - 49c0: 0100 addi s0,sp,128 - 49c2: 0200 addi s0,sp,256 - 49c4: 2f04 fld fs1,24(a4) - 49c6: 00090003 lb zero,0(s2) - 49ca: 0100 addi s0,sp,128 - 49cc: 0200 addi s0,sp,256 - 49ce: 2f04 fld fs1,24(a4) - 49d0: 00090003 lb zero,0(s2) - 49d4: 0100 addi s0,sp,128 - 49d6: 0200 addi s0,sp,256 - 49d8: 3004 fld fs1,32(s0) - 49da: 04090003 lb zero,64(s2) - 49de: 0100 addi s0,sp,128 - 49e0: 0200 addi s0,sp,256 - 49e2: 3204 fld fs1,32(a2) - 49e4: 04090003 lb zero,64(s2) - 49e8: 0100 addi s0,sp,128 - 49ea: 0200 addi s0,sp,256 - 49ec: 3204 fld fs1,32(a2) - 49ee: 10090003 lb zero,256(s2) - 49f2: 0100 addi s0,sp,128 - 49f4: 0200 addi s0,sp,256 - 49f6: 3204 fld fs1,32(a2) - 49f8: 10090003 lb zero,256(s2) - 49fc: 0100 addi s0,sp,128 - 49fe: 0200 addi s0,sp,256 - 4a00: 3204 fld fs1,32(a2) - 4a02: 00090003 lb zero,0(s2) - 4a06: 0100 addi s0,sp,128 - 4a08: 0200 addi s0,sp,256 - 4a0a: 3204 fld fs1,32(a2) - 4a0c: 00090003 lb zero,0(s2) - 4a10: 0100 addi s0,sp,128 - 4a12: 0200 addi s0,sp,256 - 4a14: 3204 fld fs1,32(a2) - 4a16: 00090003 lb zero,0(s2) - 4a1a: 0100 addi s0,sp,128 - 4a1c: 0200 addi s0,sp,256 - 4a1e: 3204 fld fs1,32(a2) - 4a20: 00090003 lb zero,0(s2) - 4a24: 0100 addi s0,sp,128 - 4a26: 0200 addi s0,sp,256 - 4a28: 3204 fld fs1,32(a2) - 4a2a: 00090003 lb zero,0(s2) - 4a2e: 0100 addi s0,sp,128 - 4a30: 0200 addi s0,sp,256 - 4a32: 3204 fld fs1,32(a2) - 4a34: 00090003 lb zero,0(s2) - 4a38: 0100 addi s0,sp,128 - 4a3a: 0200 addi s0,sp,256 - 4a3c: 3204 fld fs1,32(a2) - 4a3e: 00090003 lb zero,0(s2) - 4a42: 0100 addi s0,sp,128 - 4a44: 0200 addi s0,sp,256 - 4a46: 3204 fld fs1,32(a2) - 4a48: 08090003 lb zero,128(s2) - 4a4c: 0100 addi s0,sp,128 - 4a4e: 0200 addi s0,sp,256 - 4a50: 3204 fld fs1,32(a2) - 4a52: 00090003 lb zero,0(s2) - 4a56: 0100 addi s0,sp,128 - 4a58: 0200 addi s0,sp,256 - 4a5a: 3204 fld fs1,32(a2) - 4a5c: 04090003 lb zero,64(s2) - 4a60: 0100 addi s0,sp,128 - 4a62: 0200 addi s0,sp,256 - 4a64: 3204 fld fs1,32(a2) - 4a66: 10090003 lb zero,256(s2) - 4a6a: 0100 addi s0,sp,128 - 4a6c: 0200 addi s0,sp,256 - 4a6e: 3204 fld fs1,32(a2) - 4a70: 00090003 lb zero,0(s2) - 4a74: 0100 addi s0,sp,128 - 4a76: 0200 addi s0,sp,256 - 4a78: 3204 fld fs1,32(a2) - 4a7a: 00090003 lb zero,0(s2) - 4a7e: 0100 addi s0,sp,128 - 4a80: 0200 addi s0,sp,256 - 4a82: 3304 fld fs1,32(a4) - 4a84: 04090003 lb zero,64(s2) - 4a88: 0100 addi s0,sp,128 - 4a8a: 0200 addi s0,sp,256 - 4a8c: 3504 fld fs1,40(a0) - 4a8e: 04090003 lb zero,64(s2) - 4a92: 0100 addi s0,sp,128 - 4a94: 0200 addi s0,sp,256 - 4a96: 3504 fld fs1,40(a0) - 4a98: 0c090003 lb zero,192(s2) - 4a9c: 0100 addi s0,sp,128 - 4a9e: 0200 addi s0,sp,256 - 4aa0: 3504 fld fs1,40(a0) - 4aa2: 28090003 lb zero,640(s2) - 4aa6: 0100 addi s0,sp,128 - 4aa8: 0200 addi s0,sp,256 - 4aaa: 3504 fld fs1,40(a0) - 4aac: 00090003 lb zero,0(s2) - 4ab0: 0100 addi s0,sp,128 - 4ab2: 0200 addi s0,sp,256 - 4ab4: 3504 fld fs1,40(a0) - 4ab6: 00090003 lb zero,0(s2) - 4aba: 0100 addi s0,sp,128 - 4abc: 0200 addi s0,sp,256 - 4abe: 3504 fld fs1,40(a0) - 4ac0: 00090003 lb zero,0(s2) - 4ac4: 0100 addi s0,sp,128 - 4ac6: 0200 addi s0,sp,256 - 4ac8: 3504 fld fs1,40(a0) - 4aca: 00090003 lb zero,0(s2) - 4ace: 0100 addi s0,sp,128 - 4ad0: 0200 addi s0,sp,256 - 4ad2: 3504 fld fs1,40(a0) - 4ad4: 00090003 lb zero,0(s2) - 4ad8: 0100 addi s0,sp,128 - 4ada: 0200 addi s0,sp,256 - 4adc: 3504 fld fs1,40(a0) - 4ade: 00090003 lb zero,0(s2) - 4ae2: 0100 addi s0,sp,128 - 4ae4: 0200 addi s0,sp,256 - 4ae6: 3504 fld fs1,40(a0) - 4ae8: 00090003 lb zero,0(s2) - 4aec: 0100 addi s0,sp,128 - 4aee: 0200 addi s0,sp,256 - 4af0: 3504 fld fs1,40(a0) - 4af2: 00090003 lb zero,0(s2) - 4af6: 0100 addi s0,sp,128 - 4af8: 0200 addi s0,sp,256 - 4afa: 3504 fld fs1,40(a0) - 4afc: 00090003 lb zero,0(s2) - 4b00: 0100 addi s0,sp,128 - 4b02: 0200 addi s0,sp,256 - 4b04: 3504 fld fs1,40(a0) - 4b06: 00090003 lb zero,0(s2) - 4b0a: 0100 addi s0,sp,128 - 4b0c: 0200 addi s0,sp,256 - 4b0e: 3504 fld fs1,40(a0) - 4b10: 00090003 lb zero,0(s2) - 4b14: 0100 addi s0,sp,128 - 4b16: 0200 addi s0,sp,256 - 4b18: 3504 fld fs1,40(a0) - 4b1a: 00090003 lb zero,0(s2) - 4b1e: 0100 addi s0,sp,128 - 4b20: 0200 addi s0,sp,256 - 4b22: 3504 fld fs1,40(a0) - 4b24: 04090003 lb zero,64(s2) - 4b28: 0100 addi s0,sp,128 - 4b2a: 0200 addi s0,sp,256 - 4b2c: 3504 fld fs1,40(a0) - 4b2e: 04090003 lb zero,64(s2) - 4b32: 0100 addi s0,sp,128 - 4b34: 0200 addi s0,sp,256 - 4b36: 3504 fld fs1,40(a0) - 4b38: 00090003 lb zero,0(s2) - 4b3c: 0100 addi s0,sp,128 - 4b3e: 0200 addi s0,sp,256 - 4b40: 3504 fld fs1,40(a0) - 4b42: 08090003 lb zero,128(s2) - 4b46: 0100 addi s0,sp,128 - 4b48: 0200 addi s0,sp,256 - 4b4a: 3504 fld fs1,40(a0) - 4b4c: 00090003 lb zero,0(s2) - 4b50: 0100 addi s0,sp,128 - 4b52: 0200 addi s0,sp,256 - 4b54: 3504 fld fs1,40(a0) - 4b56: 00090003 lb zero,0(s2) - 4b5a: 0100 addi s0,sp,128 - 4b5c: 0200 addi s0,sp,256 - 4b5e: 3504 fld fs1,40(a0) - 4b60: 00090003 lb zero,0(s2) - 4b64: 0100 addi s0,sp,128 - 4b66: 0200 addi s0,sp,256 - 4b68: 3504 fld fs1,40(a0) - 4b6a: 00090003 lb zero,0(s2) - 4b6e: 0100 addi s0,sp,128 - 4b70: 0200 addi s0,sp,256 - 4b72: 3504 fld fs1,40(a0) - 4b74: 08090003 lb zero,128(s2) - 4b78: 0100 addi s0,sp,128 - 4b7a: 0200 addi s0,sp,256 - 4b7c: 3504 fld fs1,40(a0) - 4b7e: 04090003 lb zero,64(s2) - 4b82: 0100 addi s0,sp,128 - 4b84: 0200 addi s0,sp,256 - 4b86: 3504 fld fs1,40(a0) - 4b88: 00090003 lb zero,0(s2) - 4b8c: 0100 addi s0,sp,128 - 4b8e: 0200 addi s0,sp,256 - 4b90: 3504 fld fs1,40(a0) - 4b92: 00090003 lb zero,0(s2) - 4b96: 0100 addi s0,sp,128 - 4b98: 0200 addi s0,sp,256 - 4b9a: 3504 fld fs1,40(a0) - 4b9c: 04090003 lb zero,64(s2) - 4ba0: 0100 addi s0,sp,128 - 4ba2: 0200 addi s0,sp,256 - 4ba4: 3504 fld fs1,40(a0) - 4ba6: 00090003 lb zero,0(s2) - 4baa: 0100 addi s0,sp,128 - 4bac: 0200 addi s0,sp,256 - 4bae: 3504 fld fs1,40(a0) - 4bb0: 00090003 lb zero,0(s2) - 4bb4: 0100 addi s0,sp,128 - 4bb6: 0200 addi s0,sp,256 - 4bb8: 3504 fld fs1,40(a0) - 4bba: 00090003 lb zero,0(s2) - 4bbe: 0100 addi s0,sp,128 - 4bc0: 0200 addi s0,sp,256 - 4bc2: 3504 fld fs1,40(a0) - 4bc4: 00090003 lb zero,0(s2) - 4bc8: 0100 addi s0,sp,128 - 4bca: 0200 addi s0,sp,256 - 4bcc: 3504 fld fs1,40(a0) - 4bce: 2c090003 lb zero,704(s2) - 4bd2: 0100 addi s0,sp,128 - 4bd4: 0200 addi s0,sp,256 - 4bd6: 3504 fld fs1,40(a0) - 4bd8: 08090003 lb zero,128(s2) - 4bdc: 0100 addi s0,sp,128 - 4bde: 0200 addi s0,sp,256 - 4be0: 3504 fld fs1,40(a0) - 4be2: 04090003 lb zero,64(s2) - 4be6: 0100 addi s0,sp,128 - 4be8: 0200 addi s0,sp,256 - 4bea: 3504 fld fs1,40(a0) - 4bec: 00090003 lb zero,0(s2) - 4bf0: 0100 addi s0,sp,128 - 4bf2: 0200 addi s0,sp,256 - 4bf4: 3504 fld fs1,40(a0) - 4bf6: 04090003 lb zero,64(s2) - 4bfa: 0100 addi s0,sp,128 - 4bfc: 0200 addi s0,sp,256 - 4bfe: 3504 fld fs1,40(a0) - 4c00: 2c090003 lb zero,704(s2) - 4c04: 0100 addi s0,sp,128 - 4c06: 0200 addi s0,sp,256 - 4c08: 3504 fld fs1,40(a0) - 4c0a: 00090003 lb zero,0(s2) - 4c0e: 0100 addi s0,sp,128 - 4c10: 0200 addi s0,sp,256 - 4c12: 3504 fld fs1,40(a0) - 4c14: 00090003 lb zero,0(s2) - 4c18: 0100 addi s0,sp,128 - 4c1a: 0200 addi s0,sp,256 - 4c1c: 3504 fld fs1,40(a0) - 4c1e: 00090003 lb zero,0(s2) - 4c22: 0100 addi s0,sp,128 - 4c24: 0200 addi s0,sp,256 - 4c26: 3504 fld fs1,40(a0) - 4c28: 00090003 lb zero,0(s2) - 4c2c: 0100 addi s0,sp,128 - 4c2e: 0200 addi s0,sp,256 - 4c30: 3504 fld fs1,40(a0) - 4c32: 00090003 lb zero,0(s2) - 4c36: 0100 addi s0,sp,128 - 4c38: 0200 addi s0,sp,256 - 4c3a: 3504 fld fs1,40(a0) - 4c3c: 00090003 lb zero,0(s2) - 4c40: 0100 addi s0,sp,128 - 4c42: 0200 addi s0,sp,256 - 4c44: 3504 fld fs1,40(a0) - 4c46: 00090003 lb zero,0(s2) - 4c4a: 0100 addi s0,sp,128 - 4c4c: 0200 addi s0,sp,256 - 4c4e: 3504 fld fs1,40(a0) - 4c50: 00090003 lb zero,0(s2) - 4c54: 0100 addi s0,sp,128 - 4c56: 0200 addi s0,sp,256 - 4c58: 3504 fld fs1,40(a0) - 4c5a: 0c090003 lb zero,192(s2) - 4c5e: 0100 addi s0,sp,128 - 4c60: 0200 addi s0,sp,256 - 4c62: 3504 fld fs1,40(a0) - 4c64: 00090003 lb zero,0(s2) - 4c68: 0100 addi s0,sp,128 - 4c6a: 0200 addi s0,sp,256 - 4c6c: 3504 fld fs1,40(a0) - 4c6e: 00090003 lb zero,0(s2) - 4c72: 0100 addi s0,sp,128 - 4c74: 0200 addi s0,sp,256 - 4c76: 3504 fld fs1,40(a0) - 4c78: 00090003 lb zero,0(s2) - 4c7c: 0100 addi s0,sp,128 - 4c7e: 0200 addi s0,sp,256 - 4c80: 3504 fld fs1,40(a0) - 4c82: 00090003 lb zero,0(s2) - 4c86: 0100 addi s0,sp,128 - 4c88: 0200 addi s0,sp,256 - 4c8a: 3504 fld fs1,40(a0) - 4c8c: 00090003 lb zero,0(s2) - 4c90: 0100 addi s0,sp,128 - 4c92: 0200 addi s0,sp,256 - 4c94: 3504 fld fs1,40(a0) - 4c96: 00090003 lb zero,0(s2) - 4c9a: 0100 addi s0,sp,128 - 4c9c: 0200 addi s0,sp,256 - 4c9e: 3504 fld fs1,40(a0) - 4ca0: 00090003 lb zero,0(s2) - 4ca4: 0100 addi s0,sp,128 - 4ca6: 0200 addi s0,sp,256 - 4ca8: 3504 fld fs1,40(a0) - 4caa: 00090003 lb zero,0(s2) - 4cae: 0100 addi s0,sp,128 - 4cb0: 0200 addi s0,sp,256 - 4cb2: 3504 fld fs1,40(a0) - 4cb4: 00090003 lb zero,0(s2) - 4cb8: 0100 addi s0,sp,128 - 4cba: 0200 addi s0,sp,256 - 4cbc: 3504 fld fs1,40(a0) - 4cbe: 00090003 lb zero,0(s2) - 4cc2: 0100 addi s0,sp,128 - 4cc4: 0200 addi s0,sp,256 - 4cc6: 3504 fld fs1,40(a0) - 4cc8: 00090003 lb zero,0(s2) - 4ccc: 0100 addi s0,sp,128 - 4cce: 0200 addi s0,sp,256 - 4cd0: 3504 fld fs1,40(a0) - 4cd2: 0c090003 lb zero,192(s2) - 4cd6: 0100 addi s0,sp,128 - 4cd8: 0200 addi s0,sp,256 - 4cda: 3504 fld fs1,40(a0) - 4cdc: 00090003 lb zero,0(s2) - 4ce0: 0100 addi s0,sp,128 - 4ce2: 0200 addi s0,sp,256 - 4ce4: 3504 fld fs1,40(a0) - 4ce6: 04090003 lb zero,64(s2) - 4cea: 0100 addi s0,sp,128 - 4cec: 0200 addi s0,sp,256 - 4cee: 3604 fld fs1,40(a2) - 4cf0: 04090003 lb zero,64(s2) - 4cf4: 0100 addi s0,sp,128 - 4cf6: 0200 addi s0,sp,256 - 4cf8: 3804 fld fs1,48(s0) - 4cfa: 04090003 lb zero,64(s2) - 4cfe: 0100 addi s0,sp,128 - 4d00: 0200 addi s0,sp,256 - 4d02: 3804 fld fs1,48(s0) - 4d04: 00090003 lb zero,0(s2) - 4d08: 0100 addi s0,sp,128 - 4d0a: 0200 addi s0,sp,256 - 4d0c: 3804 fld fs1,48(s0) - 4d0e: 10090003 lb zero,256(s2) - 4d12: 0100 addi s0,sp,128 - 4d14: 0200 addi s0,sp,256 - 4d16: 3804 fld fs1,48(s0) - 4d18: 00090003 lb zero,0(s2) - 4d1c: 0100 addi s0,sp,128 - 4d1e: 0200 addi s0,sp,256 - 4d20: 3804 fld fs1,48(s0) - 4d22: 00090003 lb zero,0(s2) - 4d26: 0100 addi s0,sp,128 - 4d28: 0200 addi s0,sp,256 - 4d2a: 3804 fld fs1,48(s0) - 4d2c: 08090003 lb zero,128(s2) - 4d30: 0100 addi s0,sp,128 - 4d32: 0200 addi s0,sp,256 - 4d34: 3804 fld fs1,48(s0) - 4d36: 34090003 lb zero,832(s2) - 4d3a: 0100 addi s0,sp,128 - 4d3c: 0200 addi s0,sp,256 - 4d3e: 3804 fld fs1,48(s0) - 4d40: 00090003 lb zero,0(s2) - 4d44: 0100 addi s0,sp,128 - 4d46: 0200 addi s0,sp,256 - 4d48: 3804 fld fs1,48(s0) - 4d4a: 00090003 lb zero,0(s2) - 4d4e: 0100 addi s0,sp,128 - 4d50: 0200 addi s0,sp,256 - 4d52: 3804 fld fs1,48(s0) - 4d54: 00090003 lb zero,0(s2) - 4d58: 0100 addi s0,sp,128 - 4d5a: 0200 addi s0,sp,256 - 4d5c: 3804 fld fs1,48(s0) - 4d5e: 00090003 lb zero,0(s2) - 4d62: 0100 addi s0,sp,128 - 4d64: 0200 addi s0,sp,256 - 4d66: 3804 fld fs1,48(s0) - 4d68: 00090003 lb zero,0(s2) - 4d6c: 0100 addi s0,sp,128 - 4d6e: 0200 addi s0,sp,256 - 4d70: 3804 fld fs1,48(s0) - 4d72: 00090003 lb zero,0(s2) - 4d76: 0100 addi s0,sp,128 - 4d78: 0200 addi s0,sp,256 - 4d7a: 3804 fld fs1,48(s0) - 4d7c: 00090003 lb zero,0(s2) - 4d80: 0100 addi s0,sp,128 - 4d82: 0200 addi s0,sp,256 - 4d84: 3804 fld fs1,48(s0) - 4d86: 00090003 lb zero,0(s2) - 4d8a: 0100 addi s0,sp,128 - 4d8c: 0200 addi s0,sp,256 - 4d8e: 3804 fld fs1,48(s0) - 4d90: 00090003 lb zero,0(s2) - 4d94: 0100 addi s0,sp,128 - 4d96: 0200 addi s0,sp,256 - 4d98: 3804 fld fs1,48(s0) - 4d9a: 00090003 lb zero,0(s2) - 4d9e: 0100 addi s0,sp,128 - 4da0: 0200 addi s0,sp,256 - 4da2: 3804 fld fs1,48(s0) - 4da4: 00090003 lb zero,0(s2) - 4da8: 0100 addi s0,sp,128 - 4daa: 0200 addi s0,sp,256 - 4dac: 3804 fld fs1,48(s0) - 4dae: 00090003 lb zero,0(s2) - 4db2: 0100 addi s0,sp,128 - 4db4: 0200 addi s0,sp,256 - 4db6: 3804 fld fs1,48(s0) - 4db8: 00090003 lb zero,0(s2) - 4dbc: 0100 addi s0,sp,128 - 4dbe: 0200 addi s0,sp,256 - 4dc0: 3804 fld fs1,48(s0) - 4dc2: 04090003 lb zero,64(s2) - 4dc6: 0100 addi s0,sp,128 - 4dc8: 0200 addi s0,sp,256 - 4dca: 4404 lw s1,8(s0) - 4dcc: 08090003 lb zero,128(s2) - 4dd0: 0100 addi s0,sp,128 - 4dd2: 20090003 lb zero,512(s2) - 4dd6: 0100 addi s0,sp,128 - 4dd8: 00090003 lb zero,0(s2) - 4ddc: 0100 addi s0,sp,128 - 4dde: 00090003 lb zero,0(s2) - 4de2: 0100 addi s0,sp,128 - 4de4: 00090003 lb zero,0(s2) - 4de8: 0100 addi s0,sp,128 - 4dea: 10090003 lb zero,256(s2) - 4dee: 0100 addi s0,sp,128 - 4df0: 10090003 lb zero,256(s2) - 4df4: 0100 addi s0,sp,128 - 4df6: 0200 addi s0,sp,256 - 4df8: 5104 lw s1,32(a0) - 4dfa: 10090003 lb zero,256(s2) - 4dfe: 0100 addi s0,sp,128 - 4e00: 0200 addi s0,sp,256 - 4e02: 5104 lw s1,32(a0) - 4e04: 00090003 lb zero,0(s2) - 4e08: 0100 addi s0,sp,128 - 4e0a: 0200 addi s0,sp,256 - 4e0c: 5104 lw s1,32(a0) - 4e0e: 00090003 lb zero,0(s2) - 4e12: 0100 addi s0,sp,128 - 4e14: 0200 addi s0,sp,256 - 4e16: 5104 lw s1,32(a0) - 4e18: 00090003 lb zero,0(s2) - 4e1c: 0100 addi s0,sp,128 - 4e1e: 0200 addi s0,sp,256 - 4e20: 5104 lw s1,32(a0) - 4e22: 00090003 lb zero,0(s2) - 4e26: 0100 addi s0,sp,128 - 4e28: 0200 addi s0,sp,256 - 4e2a: 5104 lw s1,32(a0) - 4e2c: 00090003 lb zero,0(s2) - 4e30: 0100 addi s0,sp,128 - 4e32: 0200 addi s0,sp,256 - 4e34: 5104 lw s1,32(a0) - 4e36: 00090003 lb zero,0(s2) - 4e3a: 0100 addi s0,sp,128 - 4e3c: 0200 addi s0,sp,256 - 4e3e: 5104 lw s1,32(a0) - 4e40: 00090003 lb zero,0(s2) - 4e44: 0100 addi s0,sp,128 - 4e46: 0200 addi s0,sp,256 - 4e48: 5104 lw s1,32(a0) - 4e4a: 00090003 lb zero,0(s2) - 4e4e: 0100 addi s0,sp,128 - 4e50: 0200 addi s0,sp,256 - 4e52: 5104 lw s1,32(a0) - 4e54: 00090003 lb zero,0(s2) - 4e58: 0100 addi s0,sp,128 - 4e5a: 0200 addi s0,sp,256 - 4e5c: 5104 lw s1,32(a0) - 4e5e: 00090003 lb zero,0(s2) - 4e62: 0100 addi s0,sp,128 - 4e64: 0200 addi s0,sp,256 - 4e66: 5104 lw s1,32(a0) - 4e68: 00090003 lb zero,0(s2) - 4e6c: 0100 addi s0,sp,128 - 4e6e: 0200 addi s0,sp,256 - 4e70: 5104 lw s1,32(a0) - 4e72: 04090003 lb zero,64(s2) - 4e76: 0100 addi s0,sp,128 - 4e78: 0200 addi s0,sp,256 - 4e7a: 5704 lw s1,40(a4) - 4e7c: 08090003 lb zero,128(s2) - 4e80: 0100 addi s0,sp,128 - 4e82: 0200 addi s0,sp,256 - 4e84: 5804 lw s1,48(s0) - 4e86: 20090003 lb zero,512(s2) - 4e8a: 0100 addi s0,sp,128 - 4e8c: 0200 addi s0,sp,256 - 4e8e: 5804 lw s1,48(s0) - 4e90: 10090003 lb zero,256(s2) - 4e94: 0100 addi s0,sp,128 - 4e96: 0200 addi s0,sp,256 - 4e98: 5804 lw s1,48(s0) - 4e9a: 00090003 lb zero,0(s2) - 4e9e: 0100 addi s0,sp,128 - 4ea0: 0200 addi s0,sp,256 - 4ea2: 0204 addi s1,sp,256 - 4ea4: 0c090103 lb sp,192(s2) - 4ea8: 0100 addi s0,sp,128 - 4eaa: 0200 addi s0,sp,256 - 4eac: 0204 addi s1,sp,256 - 4eae: 10090003 lb zero,256(s2) - 4eb2: 0100 addi s0,sp,128 - 4eb4: 0200 addi s0,sp,256 - 4eb6: 0604 addi s1,sp,768 - 4eb8: 04090003 lb zero,64(s2) - 4ebc: 0100 addi s0,sp,128 - 4ebe: 0200 addi s0,sp,256 - 4ec0: 0604 addi s1,sp,768 - 4ec2: 00090003 lb zero,0(s2) - 4ec6: 0100 addi s0,sp,128 - 4ec8: 0200 addi s0,sp,256 - 4eca: 0804 addi s1,sp,16 - 4ecc: 0c090003 lb zero,192(s2) - 4ed0: 0100 addi s0,sp,128 - 4ed2: 0200 addi s0,sp,256 - 4ed4: 0804 addi s1,sp,16 - 4ed6: 00090003 lb zero,0(s2) - 4eda: 0100 addi s0,sp,128 - 4edc: 0200 addi s0,sp,256 - 4ede: 0804 addi s1,sp,16 - 4ee0: 00090003 lb zero,0(s2) - 4ee4: 0100 addi s0,sp,128 - 4ee6: 0200 addi s0,sp,256 - 4ee8: 0804 addi s1,sp,16 - 4eea: 00090003 lb zero,0(s2) - 4eee: 0100 addi s0,sp,128 - 4ef0: 0200 addi s0,sp,256 - 4ef2: 0a04 addi s1,sp,272 - 4ef4: 0c090003 lb zero,192(s2) - 4ef8: 0100 addi s0,sp,128 - 4efa: 0200 addi s0,sp,256 - 4efc: 0a04 addi s1,sp,272 - 4efe: 00090003 lb zero,0(s2) - 4f02: 0100 addi s0,sp,128 - 4f04: 0200 addi s0,sp,256 - 4f06: 0a04 addi s1,sp,272 - 4f08: 00090003 lb zero,0(s2) - 4f0c: 0100 addi s0,sp,128 - 4f0e: 0200 addi s0,sp,256 - 4f10: 0a04 addi s1,sp,272 - 4f12: 10090003 lb zero,256(s2) - 4f16: 0100 addi s0,sp,128 - 4f18: 0200 addi s0,sp,256 - 4f1a: 0a04 addi s1,sp,272 - 4f1c: 0c090003 lb zero,192(s2) - 4f20: 0100 addi s0,sp,128 - 4f22: 0200 addi s0,sp,256 - 4f24: 0a04 addi s1,sp,272 - 4f26: 00090003 lb zero,0(s2) - 4f2a: 0100 addi s0,sp,128 - 4f2c: 0200 addi s0,sp,256 - 4f2e: 0a04 addi s1,sp,272 - 4f30: 0c090003 lb zero,192(s2) - 4f34: 0100 addi s0,sp,128 - 4f36: 0200 addi s0,sp,256 - 4f38: 0a04 addi s1,sp,272 - 4f3a: 04090003 lb zero,64(s2) - 4f3e: 0100 addi s0,sp,128 - 4f40: 0200 addi s0,sp,256 - 4f42: 0904 addi s1,sp,144 - 4f44: 0c090003 lb zero,192(s2) - 4f48: 0100 addi s0,sp,128 - 4f4a: 0200 addi s0,sp,256 - 4f4c: 1804 addi s1,sp,48 - 4f4e: 0c090003 lb zero,192(s2) - 4f52: 0100 addi s0,sp,128 - 4f54: 0200 addi s0,sp,256 - 4f56: 1804 addi s1,sp,48 - 4f58: 10090003 lb zero,256(s2) - 4f5c: 0100 addi s0,sp,128 - 4f5e: 0200 addi s0,sp,256 - 4f60: 1a04 addi s1,sp,304 - 4f62: 0c090003 lb zero,192(s2) - 4f66: 0100 addi s0,sp,128 - 4f68: 0200 addi s0,sp,256 - 4f6a: 1a04 addi s1,sp,304 - 4f6c: 00090003 lb zero,0(s2) - 4f70: 0100 addi s0,sp,128 - 4f72: 0200 addi s0,sp,256 - 4f74: 1a04 addi s1,sp,304 - 4f76: 00090003 lb zero,0(s2) - 4f7a: 0100 addi s0,sp,128 - 4f7c: 0200 addi s0,sp,256 - 4f7e: 1a04 addi s1,sp,304 - 4f80: 00090003 lb zero,0(s2) - 4f84: 0100 addi s0,sp,128 - 4f86: 0200 addi s0,sp,256 - 4f88: 1a04 addi s1,sp,304 - 4f8a: 00090003 lb zero,0(s2) - 4f8e: 0100 addi s0,sp,128 - 4f90: 0200 addi s0,sp,256 - 4f92: 1a04 addi s1,sp,304 - 4f94: 00090003 lb zero,0(s2) - 4f98: 0100 addi s0,sp,128 - 4f9a: 0200 addi s0,sp,256 - 4f9c: 1a04 addi s1,sp,304 - 4f9e: 00090003 lb zero,0(s2) - 4fa2: 0100 addi s0,sp,128 - 4fa4: 0200 addi s0,sp,256 - 4fa6: 1a04 addi s1,sp,304 - 4fa8: 00090003 lb zero,0(s2) - 4fac: 0100 addi s0,sp,128 - 4fae: 0200 addi s0,sp,256 - 4fb0: 2204 fld fs1,0(a2) - 4fb2: 08090003 lb zero,128(s2) - 4fb6: 0100 addi s0,sp,128 - 4fb8: 0200 addi s0,sp,256 - 4fba: 2304 fld fs1,0(a4) - 4fbc: 20090003 lb zero,512(s2) - 4fc0: 0100 addi s0,sp,128 - 4fc2: 0200 addi s0,sp,256 - 4fc4: 2304 fld fs1,0(a4) - 4fc6: 00090003 lb zero,0(s2) - 4fca: 0100 addi s0,sp,128 - 4fcc: 0306 slli t1,t1,0x1 - 4fce: 0900 addi s0,sp,144 - 4fd0: 000c 0xc - 4fd2: 0001 nop - 4fd4: 01920403 lb s0,25(tp) # 1a019 <_start-0x7ffe5fe7> - 4fd8: 0306 slli t1,t1,0x1 - 4fda: 0900 addi s0,sp,144 - 4fdc: 000c 0xc - 4fde: 0001 nop - 4fe0: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 4fe4: 00090003 lb zero,0(s2) - 4fe8: 0100 addi s0,sp,128 - 4fea: 0300 addi s0,sp,384 - 4fec: 9204 0x9204 - 4fee: 0301 addi t1,t1,0 - 4ff0: 0900 addi s0,sp,144 - 4ff2: 0000 unimp - 4ff4: 0001 nop - 4ff6: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 4ffa: 00090003 lb zero,0(s2) - 4ffe: 0100 addi s0,sp,128 - 5000: 0300 addi s0,sp,384 - 5002: 9204 0x9204 - 5004: 0301 addi t1,t1,0 - 5006: 0900 addi s0,sp,144 - 5008: 0000 unimp - 500a: 0001 nop - 500c: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 5010: 00090003 lb zero,0(s2) - 5014: 0100 addi s0,sp,128 - 5016: 0300 addi s0,sp,384 - 5018: 9204 0x9204 - 501a: 0301 addi t1,t1,0 - 501c: 0900 addi s0,sp,144 - 501e: 0010 0x10 - 5020: 0001 nop - 5022: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 5026: 18090003 lb zero,384(s2) - 502a: 0100 addi s0,sp,128 - 502c: 0a05 addi s4,s4,1 - 502e: 0300 addi s0,sp,384 - 5030: 9204 0x9204 - 5032: 0601 addi a2,a2,0 - 5034: 10090303 lb t1,256(s2) - 5038: 0100 addi s0,sp,128 - 503a: 0305 addi t1,t1,1 - 503c: 0300 addi s0,sp,384 - 503e: 9204 0x9204 - 5040: 0301 addi t1,t1,0 - 5042: 097d addi s2,s2,31 - 5044: 0004 0x4 - 5046: 0001 nop - 5048: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 504c: 0306 slli t1,t1,0x1 - 504e: 0900 addi s0,sp,144 - 5050: 0004 0x4 - 5052: 0001 nop - 5054: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 5058: 00090103 lb sp,0(s2) - 505c: 0100 addi s0,sp,128 - 505e: 0300 addi s0,sp,384 - 5060: 9204 0x9204 - 5062: 0301 addi t1,t1,0 - 5064: 0900 addi s0,sp,144 - 5066: 0000 unimp - 5068: 0001 nop - 506a: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 506e: 00090203 lb tp,0(s2) - 5072: 0100 addi s0,sp,128 - 5074: 0a05 addi s4,s4,1 - 5076: 0300 addi s0,sp,384 - 5078: 9204 0x9204 - 507a: 0601 addi a2,a2,0 - 507c: 00090003 lb zero,0(s2) - 5080: 0100 addi s0,sp,128 - 5082: 0105 addi sp,sp,1 - 5084: 0300 addi s0,sp,384 - 5086: 9204 0x9204 - 5088: 0301 addi t1,t1,0 - 508a: 0901 addi s2,s2,0 - 508c: 0004 0x4 - 508e: 0501 addi a0,a0,0 - 5090: 000a c.slli zero,0x2 - 5092: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 5096: 08097f03 0x8097f03 - 509a: 0100 addi s0,sp,128 - 509c: 0105 addi sp,sp,1 - 509e: 0300 addi s0,sp,384 - 50a0: 9204 0x9204 - 50a2: 0301 addi t1,t1,0 - 50a4: 0901 addi s2,s2,0 - 50a6: 000c 0xc - 50a8: 0501 addi a0,a0,0 - 50aa: 000a c.slli zero,0x2 - 50ac: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 50b0: 04097f03 0x4097f03 - 50b4: 0100 addi s0,sp,128 - 50b6: 0105 addi sp,sp,1 - 50b8: 0300 addi s0,sp,384 - 50ba: 9204 0x9204 - 50bc: 0301 addi t1,t1,0 - 50be: 0901 addi s2,s2,0 - 50c0: 0008 0x8 - 50c2: 0501 addi a0,a0,0 - 50c4: 000a c.slli zero,0x2 - 50c6: 01920403 lb s0,25(tp) # 19 <_start-0x7fffffe7> - 50ca: 08097f03 0x8097f03 - 50ce: 0100 addi s0,sp,128 - 50d0: 0105 addi sp,sp,1 - 50d2: 0300 addi s0,sp,384 - 50d4: 9204 0x9204 - 50d6: 0301 addi t1,t1,0 - 50d8: 0901 addi s2,s2,0 - 50da: 0004 0x4 - 50dc: 0501 addi a0,a0,0 - 50de: 09790303 lb t1,151(s2) - 50e2: 002c addi a1,sp,8 - 50e4: 0001 nop - 50e6: 0402 c.slli64 s0 - 50e8: 065f 0203 0409 0x4090203065f - 50ee: 0100 addi s0,sp,128 - 50f0: 0200 addi s0,sp,256 - 50f2: 5f04 lw s1,56(a4) - 50f4: 20090003 lb zero,512(s2) - 50f8: 0100 addi s0,sp,128 - 50fa: 0200 addi s0,sp,256 - 50fc: 5f04 lw s1,56(a4) - 50fe: 00090003 lb zero,0(s2) - 5102: 0100 addi s0,sp,128 - 5104: 00090103 lb sp,0(s2) - 5108: 0100 addi s0,sp,128 - 510a: 00090003 lb zero,0(s2) - 510e: 0100 addi s0,sp,128 - 5110: 00090003 lb zero,0(s2) - 5114: 0100 addi s0,sp,128 - 5116: 0200 addi s0,sp,256 - 5118: 0304 addi s1,sp,384 - 511a: 18090003 lb zero,384(s2) - 511e: 0100 addi s0,sp,128 - 5120: 0200 addi s0,sp,256 - 5122: 0304 addi s1,sp,384 - 5124: 00090003 lb zero,0(s2) - 5128: 0100 addi s0,sp,128 - 512a: 0306 slli t1,t1,0x1 - 512c: 097e slli s2,s2,0x1f - 512e: 0014 0x14 - 5130: 0001 nop - 5132: 0402 c.slli64 s0 - 5134: 0660 addi s0,sp,780 - 5136: 04090103 lb sp,64(s2) - 513a: 0100 addi s0,sp,128 - 513c: 0200 addi s0,sp,256 - 513e: 6004 flw fs1,0(s0) - 5140: 24090003 lb zero,576(s2) - 5144: 0100 addi s0,sp,128 - 5146: 0200 addi s0,sp,256 - 5148: 6004 flw fs1,0(s0) - 514a: 00090003 lb zero,0(s2) - 514e: 0100 addi s0,sp,128 - 5150: 0306 slli t1,t1,0x1 - 5152: 0900 addi s0,sp,144 - 5154: 0004 0x4 - 5156: 0001 nop - 5158: 0402 c.slli64 s0 - 515a: 0630 addi a2,sp,776 - 515c: 0c090103 lb sp,192(s2) - 5160: 0100 addi s0,sp,128 - 5162: 0200 addi s0,sp,256 - 5164: 3004 fld fs1,32(s0) - 5166: 00090003 lb zero,0(s2) - 516a: 0100 addi s0,sp,128 - 516c: 0200 addi s0,sp,256 - 516e: 3004 fld fs1,32(s0) - 5170: 00090003 lb zero,0(s2) - 5174: 0100 addi s0,sp,128 - 5176: 0200 addi s0,sp,256 - 5178: 3004 fld fs1,32(s0) - 517a: 00090003 lb zero,0(s2) - 517e: 0100 addi s0,sp,128 - 5180: 0200 addi s0,sp,256 - 5182: 3004 fld fs1,32(s0) - 5184: 00090003 lb zero,0(s2) - 5188: 0100 addi s0,sp,128 - 518a: 0200 addi s0,sp,256 - 518c: 3004 fld fs1,32(s0) - 518e: 00090003 lb zero,0(s2) - 5192: 0100 addi s0,sp,128 - 5194: 0200 addi s0,sp,256 - 5196: 3004 fld fs1,32(s0) - 5198: 10090003 lb zero,256(s2) - 519c: 0100 addi s0,sp,128 - 519e: 0200 addi s0,sp,256 - 51a0: 3004 fld fs1,32(s0) - 51a2: 00090003 lb zero,0(s2) - 51a6: 0100 addi s0,sp,128 - 51a8: 0200 addi s0,sp,256 - 51aa: 3504 fld fs1,40(a0) - 51ac: 08090003 lb zero,128(s2) - 51b0: 0100 addi s0,sp,128 - 51b2: 0200 addi s0,sp,256 - 51b4: 3504 fld fs1,40(a0) - 51b6: 00090003 lb zero,0(s2) - 51ba: 0100 addi s0,sp,128 - 51bc: 0200 addi s0,sp,256 - 51be: 3504 fld fs1,40(a0) - 51c0: 00090003 lb zero,0(s2) - 51c4: 0100 addi s0,sp,128 - 51c6: 0200 addi s0,sp,256 - 51c8: 3504 fld fs1,40(a0) - 51ca: 08090003 lb zero,128(s2) - 51ce: 0100 addi s0,sp,128 - 51d0: 0200 addi s0,sp,256 - 51d2: 4704 lw s1,8(a4) - 51d4: 08090003 lb zero,128(s2) - 51d8: 0100 addi s0,sp,128 - 51da: 0200 addi s0,sp,256 - 51dc: 4704 lw s1,8(a4) - 51de: 00090003 lb zero,0(s2) - 51e2: 0100 addi s0,sp,128 - 51e4: 0200 addi s0,sp,256 - 51e6: 4704 lw s1,8(a4) - 51e8: 00090003 lb zero,0(s2) - 51ec: 0100 addi s0,sp,128 - 51ee: 0200 addi s0,sp,256 - 51f0: 4704 lw s1,8(a4) - 51f2: 00090003 lb zero,0(s2) - 51f6: 0100 addi s0,sp,128 - 51f8: 0200 addi s0,sp,256 - 51fa: 4704 lw s1,8(a4) - 51fc: 00090003 lb zero,0(s2) - 5200: 0100 addi s0,sp,128 - 5202: 0200 addi s0,sp,256 - 5204: 4704 lw s1,8(a4) - 5206: 00090003 lb zero,0(s2) - 520a: 0100 addi s0,sp,128 - 520c: 0200 addi s0,sp,256 - 520e: 4704 lw s1,8(a4) - 5210: 00090003 lb zero,0(s2) - 5214: 0100 addi s0,sp,128 - 5216: 0200 addi s0,sp,256 - 5218: 4704 lw s1,8(a4) - 521a: 04090003 lb zero,64(s2) - 521e: 0100 addi s0,sp,128 - 5220: 0200 addi s0,sp,256 - 5222: 4704 lw s1,8(a4) - 5224: 08090003 lb zero,128(s2) - 5228: 0100 addi s0,sp,128 - 522a: 0200 addi s0,sp,256 - 522c: 4704 lw s1,8(a4) - 522e: 00090003 lb zero,0(s2) - 5232: 0100 addi s0,sp,128 - 5234: 0200 addi s0,sp,256 - 5236: 4904 lw s1,16(a0) - 5238: 0306 slli t1,t1,0x1 - 523a: 0900 addi s0,sp,144 - 523c: 0004 0x4 - 523e: 0001 nop - 5240: 0402 c.slli64 s0 - 5242: 064c addi a1,sp,772 - 5244: 08090003 lb zero,128(s2) - 5248: 0100 addi s0,sp,128 - 524a: 0306 slli t1,t1,0x1 - 524c: 0900 addi s0,sp,144 - 524e: 0004 0x4 - 5250: 0001 nop - 5252: 0402 c.slli64 s0 - 5254: 0651 addi a2,a2,20 - 5256: 0c090003 lb zero,192(s2) - 525a: 0100 addi s0,sp,128 - 525c: 0200 addi s0,sp,256 - 525e: 5704 lw s1,40(a4) - 5260: 0306 slli t1,t1,0x1 - 5262: 0900 addi s0,sp,144 - 5264: 0018 0x18 - 5266: 0001 nop - 5268: 0402 c.slli64 s0 - 526a: 0003064b fnmsub.s fa2,ft6,ft0,ft0,rne - 526e: 0809 addi a6,a6,2 - 5270: 0100 addi s0,sp,128 - 5272: 0200 addi s0,sp,256 - 5274: 4e04 lw s1,24(a2) - 5276: 0306 slli t1,t1,0x1 - 5278: 0900 addi s0,sp,144 - 527a: 0018 0x18 - 527c: 0001 nop - 527e: 0402 c.slli64 s0 - 5280: 064e slli a2,a2,0x13 - 5282: 14090003 lb zero,320(s2) - 5286: 0100 addi s0,sp,128 - 5288: 0200 addi s0,sp,256 - 528a: 4e04 lw s1,24(a2) - 528c: 08090003 lb zero,128(s2) - 5290: 0100 addi s0,sp,128 - 5292: 0200 addi s0,sp,256 - 5294: 5204 lw s1,32(a2) - 5296: 0306 slli t1,t1,0x1 - 5298: 0900 addi s0,sp,144 - 529a: 0018 0x18 - 529c: 0001 nop - 529e: 0402 c.slli64 s0 - 52a0: 0655 addi a2,a2,21 - 52a2: 04090003 lb zero,64(s2) - 52a6: 0100 addi s0,sp,128 - 52a8: 0200 addi s0,sp,256 - 52aa: 5404 lw s1,40(s0) - 52ac: 24090003 lb zero,576(s2) - 52b0: 0100 addi s0,sp,128 - 52b2: 0200 addi s0,sp,256 - 52b4: 5804 lw s1,48(s0) - 52b6: 2c090003 lb zero,704(s2) - 52ba: 0100 addi s0,sp,128 - 52bc: 0200 addi s0,sp,256 - 52be: 5704 lw s1,40(a4) - 52c0: 0306 slli t1,t1,0x1 - 52c2: 0900 addi s0,sp,144 - 52c4: 0014 0x14 - 52c6: 0001 nop - 52c8: 0402 c.slli64 s0 - 52ca: 0659 addi a2,a2,22 - 52cc: 04090003 lb zero,64(s2) - 52d0: 0100 addi s0,sp,128 - 52d2: 0200 addi s0,sp,256 - 52d4: 5904 lw s1,48(a0) - 52d6: 00090003 lb zero,0(s2) - 52da: 0100 addi s0,sp,128 - 52dc: 0200 addi s0,sp,256 - 52de: 5904 lw s1,48(a0) - 52e0: 10090003 lb zero,256(s2) - 52e4: 0100 addi s0,sp,128 - 52e6: 0200 addi s0,sp,256 - 52e8: 5904 lw s1,48(a0) - 52ea: 00090003 lb zero,0(s2) - 52ee: 0100 addi s0,sp,128 - 52f0: 0200 addi s0,sp,256 - 52f2: 5a04 lw s1,48(a2) - 52f4: 08090003 lb zero,128(s2) - 52f8: 0100 addi s0,sp,128 - 52fa: 0200 addi s0,sp,256 - 52fc: 5a04 lw s1,48(a2) - 52fe: 00090003 lb zero,0(s2) - 5302: 0100 addi s0,sp,128 - 5304: 0200 addi s0,sp,256 - 5306: 5a04 lw s1,48(a2) - 5308: 00090003 lb zero,0(s2) - 530c: 0100 addi s0,sp,128 - 530e: 0200 addi s0,sp,256 - 5310: 5a04 lw s1,48(a2) - 5312: 00090003 lb zero,0(s2) - 5316: 0100 addi s0,sp,128 - 5318: 0200 addi s0,sp,256 - 531a: 5c04 lw s1,56(s0) - 531c: 08090003 lb zero,128(s2) - 5320: 0100 addi s0,sp,128 - 5322: 0200 addi s0,sp,256 - 5324: 5c04 lw s1,56(s0) - 5326: 00090003 lb zero,0(s2) - 532a: 0100 addi s0,sp,128 - 532c: 0200 addi s0,sp,256 - 532e: 5c04 lw s1,56(s0) - 5330: 00090003 lb zero,0(s2) - 5334: 0100 addi s0,sp,128 - 5336: 0200 addi s0,sp,256 - 5338: 5c04 lw s1,56(s0) - 533a: 10090003 lb zero,256(s2) - 533e: 0100 addi s0,sp,128 - 5340: 0200 addi s0,sp,256 - 5342: 5c04 lw s1,56(s0) - 5344: 0c090003 lb zero,192(s2) - 5348: 0100 addi s0,sp,128 - 534a: 0200 addi s0,sp,256 - 534c: 5c04 lw s1,56(s0) - 534e: 00090003 lb zero,0(s2) - 5352: 0100 addi s0,sp,128 - 5354: 0200 addi s0,sp,256 - 5356: 5c04 lw s1,56(s0) - 5358: 0c090003 lb zero,192(s2) - 535c: 0100 addi s0,sp,128 - 535e: 0200 addi s0,sp,256 - 5360: 5c04 lw s1,56(s0) - 5362: 04090003 lb zero,64(s2) - 5366: 0100 addi s0,sp,128 - 5368: 0200 addi s0,sp,256 - 536a: 5b04 lw s1,48(a4) - 536c: 0c090003 lb zero,192(s2) - 5370: 0100 addi s0,sp,128 - 5372: 0200 addi s0,sp,256 - 5374: 6a04 flw fs1,16(a2) - 5376: 0c090003 lb zero,192(s2) - 537a: 0100 addi s0,sp,128 - 537c: 0200 addi s0,sp,256 - 537e: 6a04 flw fs1,16(a2) - 5380: 00090003 lb zero,0(s2) - 5384: 0100 addi s0,sp,128 - 5386: 0200 addi s0,sp,256 - 5388: 6a04 flw fs1,16(a2) - 538a: 10090003 lb zero,256(s2) - 538e: 0100 addi s0,sp,128 - 5390: 0200 addi s0,sp,256 - 5392: 7404 flw fs1,40(s0) - 5394: 10090003 lb zero,256(s2) - 5398: 0100 addi s0,sp,128 - 539a: 0200 addi s0,sp,256 - 539c: 7504 flw fs1,40(a0) - 539e: 20090003 lb zero,512(s2) - 53a2: 0100 addi s0,sp,128 - 53a4: 0200 addi s0,sp,256 - 53a6: 0304 addi s1,sp,384 - 53a8: 0c090003 lb zero,192(s2) - 53ac: 0100 addi s0,sp,128 - 53ae: 0200 addi s0,sp,256 - 53b0: 4804 lw s1,16(s0) - 53b2: 08090003 lb zero,128(s2) - 53b6: 0100 addi s0,sp,128 - 53b8: 0200 addi s0,sp,256 - 53ba: 4804 lw s1,16(s0) - 53bc: 00090003 lb zero,0(s2) - 53c0: 0100 addi s0,sp,128 - 53c2: 0200 addi s0,sp,256 - 53c4: 7c04 flw fs1,56(s0) - 53c6: 24090003 lb zero,576(s2) - 53ca: 0100 addi s0,sp,128 - 53cc: 0200 addi s0,sp,256 - 53ce: 7c04 flw fs1,56(s0) - 53d0: 0c090003 lb zero,192(s2) - 53d4: 0100 addi s0,sp,128 - 53d6: 0200 addi s0,sp,256 - 53d8: 7c04 flw fs1,56(s0) - 53da: 00090003 lb zero,0(s2) - 53de: 0100 addi s0,sp,128 - 53e0: 0200 addi s0,sp,256 - 53e2: 7c04 flw fs1,56(s0) - 53e4: 00090003 lb zero,0(s2) - 53e8: 0100 addi s0,sp,128 - 53ea: 0200 addi s0,sp,256 - 53ec: 7c04 flw fs1,56(s0) - 53ee: 00090003 lb zero,0(s2) - 53f2: 0100 addi s0,sp,128 - 53f4: 0200 addi s0,sp,256 - 53f6: 7c04 flw fs1,56(s0) - 53f8: 00090003 lb zero,0(s2) - 53fc: 0100 addi s0,sp,128 - 53fe: 0200 addi s0,sp,256 - 5400: 7c04 flw fs1,56(s0) - 5402: 00090003 lb zero,0(s2) - 5406: 0100 addi s0,sp,128 - 5408: 0200 addi s0,sp,256 - 540a: 7c04 flw fs1,56(s0) - 540c: 00090003 lb zero,0(s2) - 5410: 0100 addi s0,sp,128 - 5412: 0200 addi s0,sp,256 - 5414: 7c04 flw fs1,56(s0) - 5416: 00090003 lb zero,0(s2) - 541a: 0100 addi s0,sp,128 - 541c: 0200 addi s0,sp,256 - 541e: 7c04 flw fs1,56(s0) - 5420: 00090003 lb zero,0(s2) - 5424: 0100 addi s0,sp,128 - 5426: 0200 addi s0,sp,256 - 5428: 7c04 flw fs1,56(s0) - 542a: 00090003 lb zero,0(s2) - 542e: 0100 addi s0,sp,128 - 5430: 0200 addi s0,sp,256 - 5432: 7c04 flw fs1,56(s0) - 5434: 00090003 lb zero,0(s2) - 5438: 0100 addi s0,sp,128 - 543a: 0200 addi s0,sp,256 - 543c: 7c04 flw fs1,56(s0) - 543e: 00090003 lb zero,0(s2) - 5442: 0100 addi s0,sp,128 - 5444: 0200 addi s0,sp,256 - 5446: 7c04 flw fs1,56(s0) - 5448: 00090003 lb zero,0(s2) - 544c: 0100 addi s0,sp,128 - 544e: 0200 addi s0,sp,256 - 5450: 7c04 flw fs1,56(s0) - 5452: 00090003 lb zero,0(s2) - 5456: 0100 addi s0,sp,128 - 5458: 0200 addi s0,sp,256 - 545a: 7c04 flw fs1,56(s0) - 545c: 00090003 lb zero,0(s2) - 5460: 0100 addi s0,sp,128 - 5462: 0200 addi s0,sp,256 - 5464: 0404 addi s1,sp,512 - 5466: 08090003 lb zero,128(s2) - 546a: 0100 addi s0,sp,128 - 546c: 0200 addi s0,sp,256 - 546e: 0404 addi s1,sp,512 - 5470: 00090003 lb zero,0(s2) - 5474: 0100 addi s0,sp,128 - 5476: 0200 addi s0,sp,256 - 5478: 0404 addi s1,sp,512 - 547a: 14090003 lb zero,320(s2) - 547e: 0100 addi s0,sp,128 - 5480: 08090003 lb zero,128(s2) - 5484: 0100 addi s0,sp,128 - 5486: 00090003 lb zero,0(s2) - 548a: 0100 addi s0,sp,128 - 548c: 00090003 lb zero,0(s2) - 5490: 0100 addi s0,sp,128 - 5492: 14090003 lb zero,320(s2) - 5496: 0100 addi s0,sp,128 - 5498: 0c09 addi s8,s8,2 - 549a: 0000 unimp - 549c: 0101 addi sp,sp,0 - 549e: 00002177 0x2177 - 54a2: 00910003 lb zero,9(sp) # 38036f7 <_start-0x7c7fc909> - 54a6: 0000 unimp - 54a8: 0101 addi sp,sp,0 - 54aa: 000d0efb 0xd0efb - 54ae: 0101 addi sp,sp,0 - 54b0: 0101 addi sp,sp,0 - 54b2: 0000 unimp - 54b4: 0100 addi s0,sp,128 - 54b6: 0000 unimp - 54b8: 2e01 jal 57c8 <_start-0x7fffa838> - 54ba: 2f2e fld ft10,200(sp) - 54bc: 2e2e fld ft8,200(sp) - 54be: 2f2e2e2f 0x2f2e2e2f - 54c2: 2e2e fld ft8,200(sp) - 54c4: 7369722f 0x7369722f - 54c8: 672d7663 bgeu s10,s2,5b34 <_start-0x7fffa4cc> - 54cc: 6c2f6363 bltu t5,sp,5b92 <_start-0x7fffa46e> - 54d0: 6269 lui tp,0x1a - 54d2: 2f636367 0x2f636367 - 54d6: 74666f73 csrrsi t5,0x746,12 - 54da: 662d lui a2,0xb - 54dc: 0070 addi a2,sp,12 - 54de: 2e2e fld ft8,200(sp) - 54e0: 2f2e2e2f 0x2f2e2e2f - 54e4: 2e2e fld ft8,200(sp) - 54e6: 2f2e2e2f 0x2f2e2e2f - 54ea: 6972 flw fs2,28(sp) - 54ec: 2d766373 csrrsi t1,0x2d7,12 - 54f0: 2f636367 0x2f636367 - 54f4: 696c flw fa1,84(a0) - 54f6: 6762 flw fa4,24(sp) - 54f8: 2e2f6363 bltu t5,sp,57de <_start-0x7fffa822> - 54fc: 2f2e fld ft10,200(sp) - 54fe: 6e69 lui t3,0x1a - 5500: 64756c63 bltu a0,t2,5b58 <_start-0x7fffa4a8> - 5504: 0065 c.nop 25 - 5506: 7300 flw fs0,32(a4) - 5508: 6275 lui tp,0x1d - 550a: 6674 flw fa3,76(a2) - 550c: 00632e33 slt t3,t1,t1 - 5510: 0001 nop - 5512: 7300 flw fs0,32(a4) - 5514: 2d74666f jal a2,4bfea <_start-0x7ffb4016> - 5518: 7066 flw ft0,120(sp) - 551a: 682e flw fa6,200(sp) - 551c: 0100 addi s0,sp,128 - 551e: 0000 unimp - 5520: 7571 lui a0,0xffffc - 5522: 6461 lui s0,0x18 - 5524: 682e flw fa6,200(sp) - 5526: 0100 addi s0,sp,128 - 5528: 0000 unimp - 552a: 6f6c flw fa1,92(a4) - 552c: 676e flw fa4,216(sp) - 552e: 6f6c flw fa1,92(a4) - 5530: 676e flw fa4,216(sp) - 5532: 682e flw fa6,200(sp) - 5534: 0200 addi s0,sp,256 - 5536: 0000 unimp - 5538: 0500 addi s0,sp,640 - 553a: 0001 nop - 553c: 0205 addi tp,tp,1 - 553e: 27c4 fld fs1,136(a5) - 5540: 8001 c.srli64 s0 - 5542: 05012303 lw t1,80(sp) - 5546: 09010303 lb t1,144(sp) - 554a: 0000 unimp - 554c: 0301 addi t1,t1,0 - 554e: 0900 addi s0,sp,144 - 5550: 0000 unimp - 5552: 0501 addi a0,a0,0 - 5554: 030d addi t1,t1,3 - 5556: 0900 addi s0,sp,144 - 5558: 0000 unimp - 555a: 0501 addi a0,a0,0 - 555c: 09010303 lb t1,144(sp) - 5560: 0000 unimp - 5562: 0301 addi t1,t1,0 - 5564: 0900 addi s0,sp,144 - 5566: 0000 unimp - 5568: 0301 addi t1,t1,0 - 556a: 0900 addi s0,sp,144 - 556c: 0000 unimp - 556e: 0301 addi t1,t1,0 - 5570: 0900 addi s0,sp,144 - 5572: 0000 unimp - 5574: 0301 addi t1,t1,0 - 5576: 0901 addi s2,s2,0 - 5578: 0000 unimp - 557a: 0301 addi t1,t1,0 - 557c: 0900 addi s0,sp,144 - 557e: 0000 unimp - 5580: 0301 addi t1,t1,0 - 5582: 0900 addi s0,sp,144 - 5584: 0000 unimp - 5586: 0301 addi t1,t1,0 - 5588: 0900 addi s0,sp,144 - 558a: 0000 unimp - 558c: 0301 addi t1,t1,0 - 558e: 0901 addi s2,s2,0 - 5590: 0000 unimp - 5592: 0301 addi t1,t1,0 - 5594: 0900 addi s0,sp,144 - 5596: 0000 unimp - 5598: 0301 addi t1,t1,0 - 559a: 0900 addi s0,sp,144 - 559c: 0000 unimp - 559e: 0301 addi t1,t1,0 - 55a0: 0900 addi s0,sp,144 - 55a2: 0000 unimp - 55a4: 0301 addi t1,t1,0 - 55a6: 0901 addi s2,s2,0 - 55a8: 0000 unimp - 55aa: 0301 addi t1,t1,0 - 55ac: 0902 c.slli64 s2 - 55ae: 0000 unimp - 55b0: 0301 addi t1,t1,0 - 55b2: 0901 addi s2,s2,0 - 55b4: 0000 unimp - 55b6: 0301 addi t1,t1,0 - 55b8: 0900 addi s0,sp,144 - 55ba: 0000 unimp - 55bc: 0301 addi t1,t1,0 - 55be: 0900 addi s0,sp,144 - 55c0: 0000 unimp - 55c2: 0301 addi t1,t1,0 - 55c4: 0900 addi s0,sp,144 - 55c6: 0000 unimp - 55c8: 0501 addi a0,a0,0 - 55ca: 0601 addi a2,a2,0 - 55cc: 00097803 0x97803 - 55d0: 0100 addi s0,sp,128 - 55d2: 0305 addi t1,t1,1 - 55d4: 20090803 lb a6,512(s2) - 55d8: 0100 addi s0,sp,128 - 55da: 0105 addi sp,sp,1 - 55dc: 08097803 0x8097803 - 55e0: 0100 addi s0,sp,128 - 55e2: 0305 addi t1,t1,1 - 55e4: 04090803 lb a6,64(s2) - 55e8: 0100 addi s0,sp,128 - 55ea: 0105 addi sp,sp,1 - 55ec: 04097803 0x4097803 - 55f0: 0100 addi s0,sp,128 - 55f2: 0305 addi t1,t1,1 - 55f4: 10090803 lb a6,256(s2) - 55f8: 0100 addi s0,sp,128 - 55fa: 0306 slli t1,t1,0x1 - 55fc: 0900 addi s0,sp,144 - 55fe: 000c 0xc - 5600: 0501 addi a0,a0,0 - 5602: 0601 addi a2,a2,0 - 5604: 00097803 0x97803 - 5608: 0100 addi s0,sp,128 - 560a: 0305 addi t1,t1,1 - 560c: 10090803 lb a6,256(s2) - 5610: 0100 addi s0,sp,128 - 5612: 0306 slli t1,t1,0x1 - 5614: 0900 addi s0,sp,144 - 5616: 000c 0xc - 5618: 0301 addi t1,t1,0 - 561a: 0900 addi s0,sp,144 - 561c: 0004 0x4 - 561e: 0301 addi t1,t1,0 - 5620: 0900 addi s0,sp,144 - 5622: 0000 unimp - 5624: 0301 addi t1,t1,0 - 5626: 0900 addi s0,sp,144 - 5628: 0004 0x4 - 562a: 0301 addi t1,t1,0 - 562c: 0900 addi s0,sp,144 - 562e: 0004 0x4 - 5630: 0301 addi t1,t1,0 - 5632: 0900 addi s0,sp,144 - 5634: 0004 0x4 - 5636: 0301 addi t1,t1,0 - 5638: 0900 addi s0,sp,144 - 563a: 0000 unimp - 563c: 0301 addi t1,t1,0 - 563e: 0900 addi s0,sp,144 - 5640: 0000 unimp - 5642: 0301 addi t1,t1,0 - 5644: 0900 addi s0,sp,144 - 5646: 0000 unimp - 5648: 0301 addi t1,t1,0 - 564a: 0900 addi s0,sp,144 - 564c: 0000 unimp - 564e: 0301 addi t1,t1,0 - 5650: 0900 addi s0,sp,144 - 5652: 0000 unimp - 5654: 0301 addi t1,t1,0 - 5656: 0900 addi s0,sp,144 - 5658: 0000 unimp - 565a: 0301 addi t1,t1,0 - 565c: 0900 addi s0,sp,144 - 565e: 0000 unimp - 5660: 0001 nop - 5662: 0402 c.slli64 s0 - 5664: 0308 addi a0,sp,384 - 5666: 0900 addi s0,sp,144 - 5668: 0008 0x8 - 566a: 0001 nop - 566c: 0402 c.slli64 s0 - 566e: 0309 addi t1,t1,2 - 5670: 0900 addi s0,sp,144 - 5672: 0020 addi s0,sp,8 - 5674: 0001 nop - 5676: 0402 c.slli64 s0 - 5678: 0609 addi a2,a2,2 - 567a: 04090103 lb sp,64(s2) - 567e: 0100 addi s0,sp,128 - 5680: 0200 addi s0,sp,256 - 5682: 0904 addi s1,sp,144 - 5684: 08097f03 0x8097f03 - 5688: 0100 addi s0,sp,128 - 568a: 0200 addi s0,sp,256 - 568c: 0904 addi s1,sp,144 - 568e: 04090103 lb sp,64(s2) - 5692: 0100 addi s0,sp,128 - 5694: 0200 addi s0,sp,256 - 5696: 0904 addi s1,sp,144 - 5698: 18097f03 0x18097f03 - 569c: 0100 addi s0,sp,128 - 569e: 0200 addi s0,sp,256 - 56a0: 0904 addi s1,sp,144 - 56a2: 0306 slli t1,t1,0x1 - 56a4: 0901 addi s2,s2,0 - 56a6: 0004 0x4 - 56a8: 0001 nop - 56aa: 0402 c.slli64 s0 - 56ac: 0309 addi t1,t1,2 - 56ae: 0900 addi s0,sp,144 - 56b0: 0000 unimp - 56b2: 0001 nop - 56b4: 0402 c.slli64 s0 - 56b6: 0309 addi t1,t1,2 - 56b8: 0900 addi s0,sp,144 - 56ba: 0000 unimp - 56bc: 0001 nop - 56be: 0402 c.slli64 s0 - 56c0: 0309 addi t1,t1,2 - 56c2: 0900 addi s0,sp,144 - 56c4: 0000 unimp - 56c6: 0001 nop - 56c8: 0402 c.slli64 s0 - 56ca: 0309 addi t1,t1,2 - 56cc: 0900 addi s0,sp,144 - 56ce: 0000 unimp - 56d0: 0001 nop - 56d2: 0402 c.slli64 s0 - 56d4: 0309 addi t1,t1,2 - 56d6: 0900 addi s0,sp,144 - 56d8: 0000 unimp - 56da: 0001 nop - 56dc: 0402 c.slli64 s0 - 56de: 0309 addi t1,t1,2 - 56e0: 0900 addi s0,sp,144 - 56e2: 0000 unimp - 56e4: 0001 nop - 56e6: 0402 c.slli64 s0 - 56e8: 0309 addi t1,t1,2 - 56ea: 0900 addi s0,sp,144 - 56ec: 0008 0x8 - 56ee: 0001 nop - 56f0: 0402 c.slli64 s0 - 56f2: 0309 addi t1,t1,2 - 56f4: 0900 addi s0,sp,144 - 56f6: 0004 0x4 - 56f8: 0001 nop - 56fa: 0402 c.slli64 s0 - 56fc: 0309 addi t1,t1,2 - 56fe: 0900 addi s0,sp,144 - 5700: 0004 0x4 - 5702: 0001 nop - 5704: 0402 c.slli64 s0 - 5706: 0309 addi t1,t1,2 - 5708: 0900 addi s0,sp,144 - 570a: 0004 0x4 - 570c: 0001 nop - 570e: 0402 c.slli64 s0 - 5710: 0309 addi t1,t1,2 - 5712: 0900 addi s0,sp,144 - 5714: 0000 unimp - 5716: 0001 nop - 5718: 0402 c.slli64 s0 - 571a: 0309 addi t1,t1,2 - 571c: 0900 addi s0,sp,144 - 571e: 0000 unimp - 5720: 0001 nop - 5722: 0402 c.slli64 s0 - 5724: 0309 addi t1,t1,2 - 5726: 0900 addi s0,sp,144 - 5728: 0000 unimp - 572a: 0001 nop - 572c: 0402 c.slli64 s0 - 572e: 0309 addi t1,t1,2 - 5730: 0900 addi s0,sp,144 - 5732: 0000 unimp - 5734: 0001 nop - 5736: 0402 c.slli64 s0 - 5738: 0309 addi t1,t1,2 - 573a: 0900 addi s0,sp,144 - 573c: 0000 unimp - 573e: 0001 nop - 5740: 0402 c.slli64 s0 - 5742: 0309 addi t1,t1,2 - 5744: 0900 addi s0,sp,144 - 5746: 0000 unimp - 5748: 0001 nop - 574a: 0402 c.slli64 s0 - 574c: 0309 addi t1,t1,2 - 574e: 0900 addi s0,sp,144 - 5750: 0000 unimp - 5752: 0001 nop - 5754: 0402 c.slli64 s0 - 5756: 0308 addi a0,sp,384 - 5758: 0900 addi s0,sp,144 - 575a: 0008 0x8 - 575c: 0001 nop - 575e: 0402 c.slli64 s0 - 5760: 0309 addi t1,t1,2 - 5762: 0900 addi s0,sp,144 - 5764: 0020 addi s0,sp,8 - 5766: 0001 nop - 5768: 0402 c.slli64 s0 - 576a: 0609 addi a2,a2,2 - 576c: 04090103 lb sp,64(s2) - 5770: 0100 addi s0,sp,128 - 5772: 0200 addi s0,sp,256 - 5774: 0904 addi s1,sp,144 - 5776: 08097f03 0x8097f03 - 577a: 0100 addi s0,sp,128 - 577c: 0200 addi s0,sp,256 - 577e: 0904 addi s1,sp,144 - 5780: 0306 slli t1,t1,0x1 - 5782: 0901 addi s2,s2,0 - 5784: 0008 0x8 - 5786: 0001 nop - 5788: 0402 c.slli64 s0 - 578a: 0309 addi t1,t1,2 - 578c: 0900 addi s0,sp,144 - 578e: 0000 unimp - 5790: 0001 nop - 5792: 0402 c.slli64 s0 - 5794: 0602 c.slli64 a2 - 5796: 04090003 lb zero,64(s2) - 579a: 0100 addi s0,sp,128 - 579c: 0200 addi s0,sp,256 - 579e: 0304 addi s1,sp,384 - 57a0: 0306 slli t1,t1,0x1 - 57a2: 0900 addi s0,sp,144 - 57a4: 001c 0x1c - 57a6: 0001 nop - 57a8: 0402 c.slli64 s0 - 57aa: 0900030b 0x900030b - 57ae: 0004 0x4 - 57b0: 0001 nop - 57b2: 0402 c.slli64 s0 - 57b4: 0900030b 0x900030b - 57b8: 0000 unimp - 57ba: 0001 nop - 57bc: 0402 c.slli64 s0 - 57be: 0900030b 0x900030b - 57c2: 0000 unimp - 57c4: 0001 nop - 57c6: 0402 c.slli64 s0 - 57c8: 0900030b 0x900030b - 57cc: 0000 unimp - 57ce: 0001 nop - 57d0: 0402 c.slli64 s0 - 57d2: 0900030b 0x900030b - 57d6: 0000 unimp - 57d8: 0001 nop - 57da: 0402 c.slli64 s0 - 57dc: 0900030b 0x900030b - 57e0: 0000 unimp - 57e2: 0001 nop - 57e4: 0402 c.slli64 s0 - 57e6: 030c addi a1,sp,384 - 57e8: 0900 addi s0,sp,144 - 57ea: 0008 0x8 - 57ec: 0001 nop - 57ee: 0402 c.slli64 s0 - 57f0: 030c addi a1,sp,384 - 57f2: 0900 addi s0,sp,144 - 57f4: 0000 unimp - 57f6: 0001 nop - 57f8: 0402 c.slli64 s0 - 57fa: 030c addi a1,sp,384 - 57fc: 0900 addi s0,sp,144 - 57fe: 0000 unimp - 5800: 0001 nop - 5802: 0402 c.slli64 s0 - 5804: 030e slli t1,t1,0x3 - 5806: 0900 addi s0,sp,144 - 5808: 0004 0x4 - 580a: 0001 nop - 580c: 0402 c.slli64 s0 - 580e: 030e slli t1,t1,0x3 - 5810: 0900 addi s0,sp,144 - 5812: 0000 unimp - 5814: 0001 nop - 5816: 0402 c.slli64 s0 - 5818: 0310 addi a2,sp,384 - 581a: 0900 addi s0,sp,144 - 581c: 0004 0x4 - 581e: 0001 nop - 5820: 02c20403 lb s0,44(tp) # 1d02c <_start-0x7ffe2fd4> - 5824: 1c090003 lb zero,448(s2) - 5828: 0100 addi s0,sp,128 - 582a: 0300 addi s0,sp,384 - 582c: c204 sw s1,0(a2) - 582e: 0302 c.slli64 t1 - 5830: 0900 addi s0,sp,144 - 5832: 0000 unimp - 5834: 0001 nop - 5836: 02c20403 lb s0,44(tp) # 2c <_start-0x7fffffd4> - 583a: 00090003 lb zero,0(s2) - 583e: 0100 addi s0,sp,128 - 5840: 0200 addi s0,sp,256 - 5842: 1304 addi s1,sp,416 - 5844: 1c090003 lb zero,448(s2) - 5848: 0100 addi s0,sp,128 - 584a: 0200 addi s0,sp,256 - 584c: 1304 addi s1,sp,416 - 584e: 00090003 lb zero,0(s2) - 5852: 0100 addi s0,sp,128 - 5854: 0200 addi s0,sp,256 - 5856: 1304 addi s1,sp,416 - 5858: 04090003 lb zero,64(s2) - 585c: 0100 addi s0,sp,128 - 585e: 0200 addi s0,sp,256 - 5860: 1c04 addi s1,sp,560 - 5862: 04090003 lb zero,64(s2) - 5866: 0100 addi s0,sp,128 - 5868: 0200 addi s0,sp,256 - 586a: 1c04 addi s1,sp,560 - 586c: 00090003 lb zero,0(s2) - 5870: 0100 addi s0,sp,128 - 5872: 0200 addi s0,sp,256 - 5874: 1c04 addi s1,sp,560 - 5876: 00090003 lb zero,0(s2) - 587a: 0100 addi s0,sp,128 - 587c: 0200 addi s0,sp,256 - 587e: 1c04 addi s1,sp,560 - 5880: 00090003 lb zero,0(s2) - 5884: 0100 addi s0,sp,128 - 5886: 0200 addi s0,sp,256 - 5888: 1c04 addi s1,sp,560 - 588a: 14090003 lb zero,320(s2) - 588e: 0100 addi s0,sp,128 - 5890: 0200 addi s0,sp,256 - 5892: 1c04 addi s1,sp,560 - 5894: 00090003 lb zero,0(s2) - 5898: 0100 addi s0,sp,128 - 589a: 0200 addi s0,sp,256 - 589c: 1c04 addi s1,sp,560 - 589e: 00090003 lb zero,0(s2) - 58a2: 0100 addi s0,sp,128 - 58a4: 0200 addi s0,sp,256 - 58a6: 1c04 addi s1,sp,560 - 58a8: 00090003 lb zero,0(s2) - 58ac: 0100 addi s0,sp,128 - 58ae: 0200 addi s0,sp,256 - 58b0: 1c04 addi s1,sp,560 - 58b2: 0c090003 lb zero,192(s2) - 58b6: 0100 addi s0,sp,128 - 58b8: 0200 addi s0,sp,256 - 58ba: 1c04 addi s1,sp,560 - 58bc: 0c090003 lb zero,192(s2) - 58c0: 0100 addi s0,sp,128 - 58c2: 0200 addi s0,sp,256 - 58c4: 1c04 addi s1,sp,560 - 58c6: 04090003 lb zero,64(s2) - 58ca: 0100 addi s0,sp,128 - 58cc: 0200 addi s0,sp,256 - 58ce: 1c04 addi s1,sp,560 - 58d0: 00090003 lb zero,0(s2) - 58d4: 0100 addi s0,sp,128 - 58d6: 0200 addi s0,sp,256 - 58d8: 1c04 addi s1,sp,560 - 58da: 18090003 lb zero,384(s2) - 58de: 0100 addi s0,sp,128 - 58e0: 0200 addi s0,sp,256 - 58e2: 1c04 addi s1,sp,560 - 58e4: 00090003 lb zero,0(s2) - 58e8: 0100 addi s0,sp,128 - 58ea: 0200 addi s0,sp,256 - 58ec: 1c04 addi s1,sp,560 - 58ee: 0c090003 lb zero,192(s2) - 58f2: 0100 addi s0,sp,128 - 58f4: 0200 addi s0,sp,256 - 58f6: 5b04 lw s1,48(a4) - 58f8: 00090003 lb zero,0(s2) - 58fc: 0100 addi s0,sp,128 - 58fe: 0200 addi s0,sp,256 - 5900: 5b04 lw s1,48(a4) - 5902: 0306 slli t1,t1,0x1 - 5904: 097f 0x97f - 5906: 0000 unimp - 5908: 0001 nop - 590a: 0402 c.slli64 s0 - 590c: 0901035b 0x901035b - 5910: 0004 0x4 - 5912: 0001 nop - 5914: 0402 c.slli64 s0 - 5916: 061d addi a2,a2,7 - 5918: 04090003 lb zero,64(s2) - 591c: 0100 addi s0,sp,128 - 591e: 0c090003 lb zero,192(s2) - 5922: 0100 addi s0,sp,128 - 5924: 08090003 lb zero,128(s2) - 5928: 0100 addi s0,sp,128 - 592a: 0200 addi s0,sp,256 - 592c: 1104 addi s1,sp,160 - 592e: 18090003 lb zero,384(s2) - 5932: 0100 addi s0,sp,128 - 5934: 0300 addi s0,sp,384 - 5936: cd04 sw s1,24(a0) - 5938: 0302 c.slli64 t1 - 593a: 0900 addi s0,sp,144 - 593c: 000c 0xc - 593e: 0001 nop - 5940: 02cd0403 lb s0,44(s10) # b02c <_start-0x7fff4fd4> - 5944: 00090003 lb zero,0(s2) - 5948: 0100 addi s0,sp,128 - 594a: 0300 addi s0,sp,384 - 594c: cd04 sw s1,24(a0) - 594e: 0302 c.slli64 t1 - 5950: 0900 addi s0,sp,144 - 5952: 0000 unimp - 5954: 0001 nop - 5956: 05940403 lb s0,89(s0) # 18059 <_start-0x7ffe7fa7> - 595a: 0306 slli t1,t1,0x1 - 595c: 0900 addi s0,sp,144 - 595e: 0018 0x18 - 5960: 0001 nop - 5962: 0402 c.slli64 s0 - 5964: 0003062b 0x3062b - 5968: 0809 addi a6,a6,2 - 596a: 0100 addi s0,sp,128 - 596c: 0200 addi s0,sp,256 - 596e: 2b04 fld fs1,16(a4) - 5970: 10090003 lb zero,256(s2) - 5974: 0100 addi s0,sp,128 - 5976: 0200 addi s0,sp,256 - 5978: 3504 fld fs1,40(a0) - 597a: 0c090003 lb zero,192(s2) - 597e: 0100 addi s0,sp,128 - 5980: 0200 addi s0,sp,256 - 5982: 3504 fld fs1,40(a0) - 5984: 00090003 lb zero,0(s2) - 5988: 0100 addi s0,sp,128 - 598a: 0200 addi s0,sp,256 - 598c: 3504 fld fs1,40(a0) - 598e: 00090003 lb zero,0(s2) - 5992: 0100 addi s0,sp,128 - 5994: 0200 addi s0,sp,256 - 5996: 3504 fld fs1,40(a0) - 5998: 00090003 lb zero,0(s2) - 599c: 0100 addi s0,sp,128 - 599e: 0200 addi s0,sp,256 - 59a0: 3504 fld fs1,40(a0) - 59a2: 00090003 lb zero,0(s2) - 59a6: 0100 addi s0,sp,128 - 59a8: 0200 addi s0,sp,256 - 59aa: 3504 fld fs1,40(a0) - 59ac: 00090003 lb zero,0(s2) - 59b0: 0100 addi s0,sp,128 - 59b2: 0200 addi s0,sp,256 - 59b4: 3504 fld fs1,40(a0) - 59b6: 00090003 lb zero,0(s2) - 59ba: 0100 addi s0,sp,128 - 59bc: 0200 addi s0,sp,256 - 59be: 3504 fld fs1,40(a0) - 59c0: 04090003 lb zero,64(s2) - 59c4: 0100 addi s0,sp,128 - 59c6: 0200 addi s0,sp,256 - 59c8: 3504 fld fs1,40(a0) - 59ca: 04090003 lb zero,64(s2) - 59ce: 0100 addi s0,sp,128 - 59d0: 0200 addi s0,sp,256 - 59d2: 3504 fld fs1,40(a0) - 59d4: 00090003 lb zero,0(s2) - 59d8: 0100 addi s0,sp,128 - 59da: 0200 addi s0,sp,256 - 59dc: 3704 fld fs1,40(a4) - 59de: 0306 slli t1,t1,0x1 - 59e0: 0900 addi s0,sp,144 - 59e2: 0008 0x8 - 59e4: 0001 nop - 59e6: 0402 c.slli64 s0 - 59e8: 063a slli a2,a2,0xe - 59ea: 08090003 lb zero,128(s2) - 59ee: 0100 addi s0,sp,128 - 59f0: 0306 slli t1,t1,0x1 - 59f2: 0900 addi s0,sp,144 - 59f4: 0004 0x4 - 59f6: 0001 nop - 59f8: 0402 c.slli64 s0 - 59fa: 0003063f 01000809 0x10008090003063f - 5a02: 0200 addi s0,sp,256 - 5a04: 4504 lw s1,8(a0) - 5a06: 0306 slli t1,t1,0x1 - 5a08: 0900 addi s0,sp,144 - 5a0a: 0018 0x18 - 5a0c: 0001 nop - 5a0e: 0402 c.slli64 s0 - 5a10: 0639 addi a2,a2,14 - 5a12: 08090003 lb zero,128(s2) - 5a16: 0100 addi s0,sp,128 - 5a18: 0200 addi s0,sp,256 - 5a1a: 3c04 fld fs1,56(s0) - 5a1c: 0306 slli t1,t1,0x1 - 5a1e: 0900 addi s0,sp,144 - 5a20: 0014 0x14 - 5a22: 0001 nop - 5a24: 0402 c.slli64 s0 - 5a26: 063c addi a5,sp,776 - 5a28: 14090003 lb zero,320(s2) - 5a2c: 0100 addi s0,sp,128 - 5a2e: 0200 addi s0,sp,256 - 5a30: 3c04 fld fs1,56(s0) - 5a32: 08090003 lb zero,128(s2) - 5a36: 0100 addi s0,sp,128 - 5a38: 0200 addi s0,sp,256 - 5a3a: 4004 lw s1,0(s0) - 5a3c: 0306 slli t1,t1,0x1 - 5a3e: 0900 addi s0,sp,144 - 5a40: 0014 0x14 - 5a42: 0001 nop - 5a44: 0402 c.slli64 s0 - 5a46: 00030643 fmadd.s fa2,ft6,ft0,ft0,rne - 5a4a: 0409 addi s0,s0,2 - 5a4c: 0100 addi s0,sp,128 - 5a4e: 0200 addi s0,sp,256 - 5a50: 4204 lw s1,0(a2) - 5a52: 24090003 lb zero,576(s2) - 5a56: 0100 addi s0,sp,128 - 5a58: 0200 addi s0,sp,256 - 5a5a: 4604 lw s1,8(a2) - 5a5c: 28090003 lb zero,640(s2) - 5a60: 0100 addi s0,sp,128 - 5a62: 0200 addi s0,sp,256 - 5a64: 4504 lw s1,8(a0) - 5a66: 0306 slli t1,t1,0x1 - 5a68: 0900 addi s0,sp,144 - 5a6a: 0010 0x10 - 5a6c: 0001 nop - 5a6e: 0402 c.slli64 s0 - 5a70: 00030647 fmsub.s fa2,ft6,ft0,ft0,rne - 5a74: 0409 addi s0,s0,2 - 5a76: 0100 addi s0,sp,128 - 5a78: 0200 addi s0,sp,256 - 5a7a: 4704 lw s1,8(a4) - 5a7c: 00090003 lb zero,0(s2) - 5a80: 0100 addi s0,sp,128 - 5a82: 0200 addi s0,sp,256 - 5a84: 4b04 lw s1,16(a4) - 5a86: 10090003 lb zero,256(s2) - 5a8a: 0100 addi s0,sp,128 - 5a8c: 0200 addi s0,sp,256 - 5a8e: 4b04 lw s1,16(a4) - 5a90: 00090003 lb zero,0(s2) - 5a94: 0100 addi s0,sp,128 - 5a96: 0200 addi s0,sp,256 - 5a98: 4b04 lw s1,16(a4) - 5a9a: 00090003 lb zero,0(s2) - 5a9e: 0100 addi s0,sp,128 - 5aa0: 0200 addi s0,sp,256 - 5aa2: 4b04 lw s1,16(a4) - 5aa4: 00090003 lb zero,0(s2) - 5aa8: 0100 addi s0,sp,128 - 5aaa: 0200 addi s0,sp,256 - 5aac: 4b04 lw s1,16(a4) - 5aae: 1c090003 lb zero,448(s2) - 5ab2: 0100 addi s0,sp,128 - 5ab4: 0200 addi s0,sp,256 - 5ab6: 4b04 lw s1,16(a4) - 5ab8: 00090003 lb zero,0(s2) - 5abc: 0100 addi s0,sp,128 - 5abe: 0200 addi s0,sp,256 - 5ac0: 4b04 lw s1,16(a4) - 5ac2: 0c090003 lb zero,192(s2) - 5ac6: 0100 addi s0,sp,128 - 5ac8: 0200 addi s0,sp,256 - 5aca: 4b04 lw s1,16(a4) - 5acc: 00090003 lb zero,0(s2) - 5ad0: 0100 addi s0,sp,128 - 5ad2: 0200 addi s0,sp,256 - 5ad4: 4b04 lw s1,16(a4) - 5ad6: 1c090003 lb zero,448(s2) - 5ada: 0100 addi s0,sp,128 - 5adc: 0200 addi s0,sp,256 - 5ade: 4b04 lw s1,16(a4) - 5ae0: 00090003 lb zero,0(s2) - 5ae4: 0100 addi s0,sp,128 - 5ae6: 0200 addi s0,sp,256 - 5ae8: 4b04 lw s1,16(a4) - 5aea: 04090003 lb zero,64(s2) - 5aee: 0100 addi s0,sp,128 - 5af0: 0200 addi s0,sp,256 - 5af2: 4b04 lw s1,16(a4) - 5af4: 00090003 lb zero,0(s2) - 5af8: 0100 addi s0,sp,128 - 5afa: 0200 addi s0,sp,256 - 5afc: 4b04 lw s1,16(a4) - 5afe: 1c090003 lb zero,448(s2) - 5b02: 0100 addi s0,sp,128 - 5b04: 0200 addi s0,sp,256 - 5b06: 4b04 lw s1,16(a4) - 5b08: 00090003 lb zero,0(s2) - 5b0c: 0100 addi s0,sp,128 - 5b0e: 0300 addi s0,sp,384 - 5b10: 8b04 0x8b04 - 5b12: 0301 addi t1,t1,0 - 5b14: 0900 addi s0,sp,144 - 5b16: 0004 0x4 - 5b18: 0001 nop - 5b1a: 01fa0403 lb s0,31(s4) - 5b1e: 0c090003 lb zero,192(s2) - 5b22: 0100 addi s0,sp,128 - 5b24: 0300 addi s0,sp,384 - 5b26: fa04 fsw fs1,48(a2) - 5b28: 0301 addi t1,t1,0 - 5b2a: 0900 addi s0,sp,144 - 5b2c: 0010 0x10 - 5b2e: 0001 nop - 5b30: 01fa0403 lb s0,31(s4) - 5b34: 08090003 lb zero,128(s2) - 5b38: 0100 addi s0,sp,128 - 5b3a: 0300 addi s0,sp,384 - 5b3c: fa04 fsw fs1,48(a2) - 5b3e: 0301 addi t1,t1,0 - 5b40: 0900 addi s0,sp,144 - 5b42: 0000 unimp - 5b44: 0001 nop - 5b46: 01fa0403 lb s0,31(s4) - 5b4a: 00090003 lb zero,0(s2) - 5b4e: 0100 addi s0,sp,128 - 5b50: 0300 addi s0,sp,384 - 5b52: fa04 fsw fs1,48(a2) - 5b54: 0301 addi t1,t1,0 - 5b56: 0900 addi s0,sp,144 - 5b58: 0000 unimp - 5b5a: 0001 nop - 5b5c: 01fa0403 lb s0,31(s4) - 5b60: 00090003 lb zero,0(s2) - 5b64: 0100 addi s0,sp,128 - 5b66: 0300 addi s0,sp,384 - 5b68: fa04 fsw fs1,48(a2) - 5b6a: 0301 addi t1,t1,0 - 5b6c: 0900 addi s0,sp,144 - 5b6e: 0000 unimp - 5b70: 0001 nop - 5b72: 01fa0403 lb s0,31(s4) - 5b76: 00090003 lb zero,0(s2) - 5b7a: 0100 addi s0,sp,128 - 5b7c: 0300 addi s0,sp,384 - 5b7e: fa04 fsw fs1,48(a2) - 5b80: 0301 addi t1,t1,0 - 5b82: 0900 addi s0,sp,144 - 5b84: 0000 unimp - 5b86: 0001 nop - 5b88: 01fa0403 lb s0,31(s4) - 5b8c: 00090003 lb zero,0(s2) - 5b90: 0100 addi s0,sp,128 - 5b92: 0300 addi s0,sp,384 - 5b94: fa04 fsw fs1,48(a2) - 5b96: 0301 addi t1,t1,0 - 5b98: 0900 addi s0,sp,144 - 5b9a: 0000 unimp - 5b9c: 0001 nop - 5b9e: 01fa0403 lb s0,31(s4) - 5ba2: 00090003 lb zero,0(s2) - 5ba6: 0100 addi s0,sp,128 - 5ba8: 0300 addi s0,sp,384 - 5baa: fa04 fsw fs1,48(a2) - 5bac: 0301 addi t1,t1,0 - 5bae: 0900 addi s0,sp,144 - 5bb0: 0000 unimp - 5bb2: 0001 nop - 5bb4: 01fa0403 lb s0,31(s4) - 5bb8: 08090003 lb zero,128(s2) - 5bbc: 0100 addi s0,sp,128 - 5bbe: 0300 addi s0,sp,384 - 5bc0: 8704 0x8704 - 5bc2: 0302 c.slli64 t1 - 5bc4: 0900 addi s0,sp,144 - 5bc6: 0004 0x4 - 5bc8: 0001 nop - 5bca: 02880403 lb s0,40(a6) - 5bce: 20090003 lb zero,512(s2) - 5bd2: 0100 addi s0,sp,128 - 5bd4: 0300 addi s0,sp,384 - 5bd6: 8804 0x8804 - 5bd8: 0302 c.slli64 t1 - 5bda: 0900 addi s0,sp,144 - 5bdc: 000c 0xc - 5bde: 0001 nop - 5be0: 02880403 lb s0,40(a6) - 5be4: 00090003 lb zero,0(s2) - 5be8: 0100 addi s0,sp,128 - 5bea: 0300 addi s0,sp,384 - 5bec: 8804 0x8804 - 5bee: 0302 c.slli64 t1 - 5bf0: 0900 addi s0,sp,144 - 5bf2: 0010 0x10 - 5bf4: 0001 nop - 5bf6: 02970403 lb s0,41(a4) - 5bfa: 0c090003 lb zero,192(s2) - 5bfe: 0100 addi s0,sp,128 - 5c00: 0300 addi s0,sp,384 - 5c02: 9704 0x9704 - 5c04: 0302 c.slli64 t1 - 5c06: 0900 addi s0,sp,144 - 5c08: 0000 unimp - 5c0a: 0001 nop - 5c0c: 02970403 lb s0,41(a4) - 5c10: 00090003 lb zero,0(s2) - 5c14: 0100 addi s0,sp,128 - 5c16: 0300 addi s0,sp,384 - 5c18: 9704 0x9704 - 5c1a: 0302 c.slli64 t1 - 5c1c: 0900 addi s0,sp,144 - 5c1e: 0000 unimp - 5c20: 0001 nop - 5c22: 02970403 lb s0,41(a4) - 5c26: 10090003 lb zero,256(s2) - 5c2a: 0100 addi s0,sp,128 - 5c2c: 0300 addi s0,sp,384 - 5c2e: 9704 0x9704 - 5c30: 0302 c.slli64 t1 - 5c32: 0900 addi s0,sp,144 - 5c34: 0000 unimp - 5c36: 0001 nop - 5c38: 0402 c.slli64 s0 - 5c3a: 0900030f 0x900030f - 5c3e: 0004 0x4 - 5c40: 0001 nop - 5c42: 0402 c.slli64 s0 - 5c44: 034d addi t1,t1,19 - 5c46: 0900 addi s0,sp,144 - 5c48: 0004 0x4 - 5c4a: 0001 nop - 5c4c: 0402 c.slli64 s0 - 5c4e: 034d addi t1,t1,19 - 5c50: 0900 addi s0,sp,144 - 5c52: 0004 0x4 - 5c54: 0001 nop - 5c56: 0402 c.slli64 s0 - 5c58: 034d addi t1,t1,19 - 5c5a: 0900 addi s0,sp,144 - 5c5c: 0000 unimp - 5c5e: 0001 nop - 5c60: 0402 c.slli64 s0 - 5c62: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 5c66: 0004 0x4 - 5c68: 0001 nop - 5c6a: 0402 c.slli64 s0 - 5c6c: 0359 addi t1,t1,22 - 5c6e: 0900 addi s0,sp,144 - 5c70: 001c 0x1c - 5c72: 0001 nop - 5c74: 0402 c.slli64 s0 - 5c76: 0359 addi t1,t1,22 - 5c78: 0900 addi s0,sp,144 - 5c7a: 0000 unimp - 5c7c: 0001 nop - 5c7e: 0402 c.slli64 s0 - 5c80: 0359 addi t1,t1,22 - 5c82: 0900 addi s0,sp,144 - 5c84: 0000 unimp - 5c86: 0001 nop - 5c88: 0402 c.slli64 s0 - 5c8a: 0359 addi t1,t1,22 - 5c8c: 0900 addi s0,sp,144 - 5c8e: 001c 0x1c - 5c90: 0001 nop - 5c92: 05a70403 lb s0,90(a4) - 5c96: 04090003 lb zero,64(s2) - 5c9a: 0100 addi s0,sp,128 - 5c9c: 0300 addi s0,sp,384 - 5c9e: a704 fsd fs1,8(a4) - 5ca0: 0305 addi t1,t1,1 - 5ca2: 0901 addi s2,s2,0 - 5ca4: 0000 unimp - 5ca6: 0001 nop - 5ca8: 05a70403 lb s0,90(a4) - 5cac: 00090003 lb zero,0(s2) - 5cb0: 0100 addi s0,sp,128 - 5cb2: 0300 addi s0,sp,384 - 5cb4: a704 fsd fs1,8(a4) - 5cb6: 0305 addi t1,t1,1 - 5cb8: 0900 addi s0,sp,144 - 5cba: 0000 unimp - 5cbc: 0001 nop - 5cbe: 05a70403 lb s0,90(a4) - 5cc2: 00090003 lb zero,0(s2) - 5cc6: 0100 addi s0,sp,128 - 5cc8: 0300 addi s0,sp,384 - 5cca: a704 fsd fs1,8(a4) - 5ccc: 0305 addi t1,t1,1 - 5cce: 0900 addi s0,sp,144 - 5cd0: 0000 unimp - 5cd2: 0001 nop - 5cd4: 0402 c.slli64 s0 - 5cd6: 032c addi a1,sp,392 - 5cd8: 0900 addi s0,sp,144 - 5cda: 000c 0xc - 5cdc: 0001 nop - 5cde: 0402 c.slli64 s0 - 5ce0: 032c addi a1,sp,392 - 5ce2: 0900 addi s0,sp,144 - 5ce4: 0000 unimp - 5ce6: 0001 nop - 5ce8: 0402 c.slli64 s0 - 5cea: 032c addi a1,sp,392 - 5cec: 0900 addi s0,sp,144 - 5cee: 0000 unimp - 5cf0: 0001 nop - 5cf2: 0402 c.slli64 s0 - 5cf4: 032c addi a1,sp,392 - 5cf6: 0900 addi s0,sp,144 - 5cf8: 0000 unimp - 5cfa: 0001 nop - 5cfc: 0402 c.slli64 s0 - 5cfe: 09000333 0x9000333 - 5d02: 000c 0xc - 5d04: 0001 nop - 5d06: 0402 c.slli64 s0 - 5d08: 09000333 0x9000333 - 5d0c: 0000 unimp - 5d0e: 0001 nop - 5d10: 0402 c.slli64 s0 - 5d12: 09000333 0x9000333 - 5d16: 0000 unimp - 5d18: 0001 nop - 5d1a: 0402 c.slli64 s0 - 5d1c: 09000333 0x9000333 - 5d20: 0010 0x10 - 5d22: 0001 nop - 5d24: 0402 c.slli64 s0 - 5d26: 09000333 0x9000333 - 5d2a: 000c 0xc - 5d2c: 0001 nop - 5d2e: 0402 c.slli64 s0 - 5d30: 09000333 0x9000333 - 5d34: 0000 unimp - 5d36: 0001 nop - 5d38: 0402 c.slli64 s0 - 5d3a: 09000333 0x9000333 - 5d3e: 000c 0xc - 5d40: 0001 nop - 5d42: 0402 c.slli64 s0 - 5d44: 09000333 0x9000333 - 5d48: 0004 0x4 - 5d4a: 0001 nop - 5d4c: 0402 c.slli64 s0 - 5d4e: 0336 slli t1,t1,0xd - 5d50: 0900 addi s0,sp,144 - 5d52: 000c 0xc - 5d54: 0001 nop - 5d56: 0402 c.slli64 s0 - 5d58: 0336 slli t1,t1,0xd - 5d5a: 0900 addi s0,sp,144 - 5d5c: 0000 unimp - 5d5e: 0001 nop - 5d60: 0402 c.slli64 s0 - 5d62: 0346 slli t1,t1,0x11 - 5d64: 0900 addi s0,sp,144 - 5d66: 000c 0xc - 5d68: 0001 nop - 5d6a: 0402 c.slli64 s0 - 5d6c: 0346 slli t1,t1,0x11 - 5d6e: 0900 addi s0,sp,144 - 5d70: 0000 unimp - 5d72: 0001 nop - 5d74: 0402 c.slli64 s0 - 5d76: 0346 slli t1,t1,0x11 - 5d78: 0900 addi s0,sp,144 - 5d7a: 0008 0x8 - 5d7c: 0601 addi a2,a2,0 - 5d7e: 0c090003 lb zero,192(s2) - 5d82: 0100 addi s0,sp,128 - 5d84: 0200 addi s0,sp,256 - 5d86: 5604 lw s1,40(a2) - 5d88: 0306 slli t1,t1,0x1 - 5d8a: 0900 addi s0,sp,144 - 5d8c: 0010 0x10 - 5d8e: 0001 nop - 5d90: 0402 c.slli64 s0 - 5d92: 0356 slli t1,t1,0x15 - 5d94: 0900 addi s0,sp,144 - 5d96: 0000 unimp - 5d98: 0001 nop - 5d9a: 0402 c.slli64 s0 - 5d9c: 0356 slli t1,t1,0x15 - 5d9e: 0900 addi s0,sp,144 - 5da0: 0000 unimp - 5da2: 0001 nop - 5da4: 0402 c.slli64 s0 - 5da6: 0356 slli t1,t1,0x15 - 5da8: 0900 addi s0,sp,144 - 5daa: 0000 unimp - 5dac: 0001 nop - 5dae: 0402 c.slli64 s0 - 5db0: 0356 slli t1,t1,0x15 - 5db2: 0900 addi s0,sp,144 - 5db4: 0000 unimp - 5db6: 0001 nop - 5db8: 0402 c.slli64 s0 - 5dba: 0356 slli t1,t1,0x15 - 5dbc: 0900 addi s0,sp,144 - 5dbe: 0000 unimp - 5dc0: 0001 nop - 5dc2: 0402 c.slli64 s0 - 5dc4: 0356 slli t1,t1,0x15 - 5dc6: 0900 addi s0,sp,144 - 5dc8: 0000 unimp - 5dca: 0001 nop - 5dcc: 0402 c.slli64 s0 - 5dce: 0356 slli t1,t1,0x15 - 5dd0: 0900 addi s0,sp,144 - 5dd2: 0000 unimp - 5dd4: 0001 nop - 5dd6: 0402 c.slli64 s0 - 5dd8: 035e slli t1,t1,0x17 - 5dda: 0900 addi s0,sp,144 - 5ddc: 0008 0x8 - 5dde: 0001 nop - 5de0: 0402 c.slli64 s0 - 5de2: 035f 0900 0020 0x200900035f - 5de8: 0001 nop - 5dea: 0402 c.slli64 s0 - 5dec: 035f 0900 0010 0x100900035f - 5df2: 0001 nop - 5df4: 0402 c.slli64 s0 - 5df6: 0664 addi s1,sp,780 - 5df8: 08090003 lb zero,128(s2) - 5dfc: 0100 addi s0,sp,128 - 5dfe: 0200 addi s0,sp,256 - 5e00: 6804 flw fs1,16(s0) - 5e02: 0306 slli t1,t1,0x1 - 5e04: 0900 addi s0,sp,144 - 5e06: 001c 0x1c - 5e08: 0001 nop - 5e0a: 0402 c.slli64 s0 - 5e0c: 0368 addi a0,sp,396 - 5e0e: 0900 addi s0,sp,144 - 5e10: 0000 unimp - 5e12: 0001 nop - 5e14: 0402 c.slli64 s0 - 5e16: 0368 addi a0,sp,396 - 5e18: 0900 addi s0,sp,144 - 5e1a: 0010 0x10 - 5e1c: 0001 nop - 5e1e: 0402 c.slli64 s0 - 5e20: 036e slli t1,t1,0x1b - 5e22: 0900 addi s0,sp,144 - 5e24: 0004 0x4 - 5e26: 0001 nop - 5e28: 0402 c.slli64 s0 - 5e2a: 036e slli t1,t1,0x1b - 5e2c: 0900 addi s0,sp,144 - 5e2e: 0000 unimp - 5e30: 0001 nop - 5e32: 0402 c.slli64 s0 - 5e34: 036e slli t1,t1,0x1b - 5e36: 0900 addi s0,sp,144 - 5e38: 0000 unimp - 5e3a: 0001 nop - 5e3c: 0402 c.slli64 s0 - 5e3e: 036e slli t1,t1,0x1b - 5e40: 0900 addi s0,sp,144 - 5e42: 0000 unimp - 5e44: 0001 nop - 5e46: 0402 c.slli64 s0 - 5e48: 036e slli t1,t1,0x1b - 5e4a: 0900 addi s0,sp,144 - 5e4c: 0000 unimp - 5e4e: 0001 nop - 5e50: 0402 c.slli64 s0 - 5e52: 036e slli t1,t1,0x1b - 5e54: 0900 addi s0,sp,144 - 5e56: 0000 unimp - 5e58: 0001 nop - 5e5a: 0402 c.slli64 s0 - 5e5c: 036e slli t1,t1,0x1b - 5e5e: 0900 addi s0,sp,144 - 5e60: 0010 0x10 - 5e62: 0001 nop - 5e64: 0402 c.slli64 s0 - 5e66: 036e slli t1,t1,0x1b - 5e68: 0900 addi s0,sp,144 - 5e6a: 0018 0x18 - 5e6c: 0501 addi a0,a0,0 - 5e6e: 000a c.slli zero,0x2 - 5e70: 0402 c.slli64 s0 - 5e72: 066e slli a2,a2,0x1b - 5e74: 00090303 lb t1,0(s2) - 5e78: 0100 addi s0,sp,128 - 5e7a: 0305 addi t1,t1,1 - 5e7c: 0200 addi s0,sp,256 - 5e7e: 6e04 flw fs1,24(a2) - 5e80: 04097d03 0x4097d03 - 5e84: 0100 addi s0,sp,128 - 5e86: 0a05 addi s4,s4,1 - 5e88: 0200 addi s0,sp,256 - 5e8a: 6e04 flw fs1,24(a2) - 5e8c: 08090303 lb t1,128(s2) - 5e90: 0100 addi s0,sp,128 - 5e92: 0305 addi t1,t1,1 - 5e94: 0200 addi s0,sp,256 - 5e96: 6e04 flw fs1,24(a2) - 5e98: 08097d03 0x8097d03 - 5e9c: 0100 addi s0,sp,128 - 5e9e: 0200 addi s0,sp,256 - 5ea0: 6e04 flw fs1,24(a2) - 5ea2: 0306 slli t1,t1,0x1 - 5ea4: 0900 addi s0,sp,144 - 5ea6: 0008 0x8 - 5ea8: 0001 nop - 5eaa: 0402 c.slli64 s0 - 5eac: 036e slli t1,t1,0x1b - 5eae: 0901 addi s2,s2,0 - 5eb0: 0000 unimp - 5eb2: 0001 nop - 5eb4: 0402 c.slli64 s0 - 5eb6: 036e slli t1,t1,0x1b - 5eb8: 0900 addi s0,sp,144 - 5eba: 0000 unimp - 5ebc: 0001 nop - 5ebe: 0402 c.slli64 s0 - 5ec0: 036e slli t1,t1,0x1b - 5ec2: 0902 c.slli64 s2 - 5ec4: 0000 unimp - 5ec6: 0501 addi a0,a0,0 - 5ec8: 000a c.slli zero,0x2 - 5eca: 0402 c.slli64 s0 - 5ecc: 066e slli a2,a2,0x1b - 5ece: 00090003 lb zero,0(s2) - 5ed2: 0100 addi s0,sp,128 - 5ed4: 0105 addi sp,sp,1 - 5ed6: 0200 addi s0,sp,256 - 5ed8: 6e04 flw fs1,24(a2) - 5eda: 0c090103 lb sp,192(s2) - 5ede: 0100 addi s0,sp,128 - 5ee0: 0a05 addi s4,s4,1 - 5ee2: 0200 addi s0,sp,256 - 5ee4: 6e04 flw fs1,24(a2) - 5ee6: 08097f03 0x8097f03 - 5eea: 0100 addi s0,sp,128 - 5eec: 0105 addi sp,sp,1 - 5eee: 0200 addi s0,sp,256 - 5ef0: 6e04 flw fs1,24(a2) - 5ef2: 04090103 lb sp,64(s2) - 5ef6: 0100 addi s0,sp,128 - 5ef8: 0305 addi t1,t1,1 - 5efa: 0200 addi s0,sp,256 - 5efc: 5204 lw s1,32(a2) - 5efe: 0306 slli t1,t1,0x1 - 5f00: 0020097b 0x20097b - 5f04: 0001 nop - 5f06: 0402 c.slli64 s0 - 5f08: 0352 slli t1,t1,0x14 - 5f0a: 0900 addi s0,sp,144 - 5f0c: 0000 unimp - 5f0e: 0001 nop - 5f10: 0402 c.slli64 s0 - 5f12: 0352 slli t1,t1,0x14 - 5f14: 0900 addi s0,sp,144 - 5f16: 0004 0x4 - 5f18: 0001 nop - 5f1a: 0402 c.slli64 s0 - 5f1c: 0900035b 0x900035b - 5f20: 0004 0x4 - 5f22: 0001 nop - 5f24: 0402 c.slli64 s0 - 5f26: 0900035b 0x900035b - 5f2a: 0000 unimp - 5f2c: 0001 nop - 5f2e: 0402 c.slli64 s0 - 5f30: 0900035b 0x900035b - 5f34: 0000 unimp - 5f36: 0001 nop - 5f38: 0402 c.slli64 s0 - 5f3a: 0900035b 0x900035b - 5f3e: 0000 unimp - 5f40: 0001 nop - 5f42: 0402 c.slli64 s0 - 5f44: 0900035b 0x900035b - 5f48: 0014 0x14 - 5f4a: 0001 nop - 5f4c: 0402 c.slli64 s0 - 5f4e: 0900035b 0x900035b - 5f52: 0000 unimp - 5f54: 0001 nop - 5f56: 0402 c.slli64 s0 - 5f58: 0900035b 0x900035b - 5f5c: 0000 unimp - 5f5e: 0001 nop - 5f60: 0402 c.slli64 s0 - 5f62: 0900035b 0x900035b - 5f66: 0000 unimp - 5f68: 0001 nop - 5f6a: 0402 c.slli64 s0 - 5f6c: 0900035b 0x900035b - 5f70: 000c 0xc - 5f72: 0001 nop - 5f74: 0402 c.slli64 s0 - 5f76: 0900035b 0x900035b - 5f7a: 000c 0xc - 5f7c: 0001 nop - 5f7e: 0402 c.slli64 s0 - 5f80: 0900035b 0x900035b - 5f84: 0004 0x4 - 5f86: 0001 nop - 5f88: 0402 c.slli64 s0 - 5f8a: 0900035b 0x900035b - 5f8e: 0000 unimp - 5f90: 0001 nop - 5f92: 0402 c.slli64 s0 - 5f94: 0900035b 0x900035b - 5f98: 0018 0x18 - 5f9a: 0001 nop - 5f9c: 0402 c.slli64 s0 - 5f9e: 0900035b 0x900035b - 5fa2: 0000 unimp - 5fa4: 0001 nop - 5fa6: 0402 c.slli64 s0 - 5fa8: 035c addi a5,sp,388 - 5faa: 0900 addi s0,sp,144 - 5fac: 0010 0x10 - 5fae: 0301 addi t1,t1,0 - 5fb0: 0900 addi s0,sp,144 - 5fb2: 000c 0xc - 5fb4: 0301 addi t1,t1,0 - 5fb6: 0900 addi s0,sp,144 - 5fb8: 0008 0x8 - 5fba: 0001 nop - 5fbc: 0402 c.slli64 s0 - 5fbe: 0350 addi a2,sp,388 - 5fc0: 0900 addi s0,sp,144 - 5fc2: 0018 0x18 - 5fc4: 0001 nop - 5fc6: 0402 c.slli64 s0 - 5fc8: 0371 addi t1,t1,28 - 5fca: 0900 addi s0,sp,144 - 5fcc: 000c 0xc - 5fce: 0001 nop - 5fd0: 0402 c.slli64 s0 - 5fd2: 0371 addi t1,t1,28 - 5fd4: 0900 addi s0,sp,144 - 5fd6: 0000 unimp - 5fd8: 0001 nop - 5fda: 0402 c.slli64 s0 - 5fdc: 0371 addi t1,t1,28 - 5fde: 0900 addi s0,sp,144 - 5fe0: 0000 unimp - 5fe2: 0001 nop - 5fe4: 0402 c.slli64 s0 - 5fe6: 0371 addi t1,t1,28 - 5fe8: 0900 addi s0,sp,144 - 5fea: 0020 addi s0,sp,8 - 5fec: 0001 nop - 5fee: 0402 c.slli64 s0 - 5ff0: 036a slli t1,t1,0x1a - 5ff2: 0900 addi s0,sp,144 - 5ff4: 0004 0x4 - 5ff6: 0001 nop - 5ff8: 0402 c.slli64 s0 - 5ffa: 036a slli t1,t1,0x1a - 5ffc: 0900 addi s0,sp,144 - 5ffe: 0010 0x10 - 6000: 0001 nop - 6002: 0402 c.slli64 s0 - 6004: 0374 addi a3,sp,396 - 6006: 0900 addi s0,sp,144 - 6008: 000c 0xc - 600a: 0001 nop - 600c: 0402 c.slli64 s0 - 600e: 0374 addi a3,sp,396 - 6010: 0900 addi s0,sp,144 - 6012: 0000 unimp - 6014: 0001 nop - 6016: 0402 c.slli64 s0 - 6018: 0374 addi a3,sp,396 - 601a: 0900 addi s0,sp,144 - 601c: 0000 unimp - 601e: 0001 nop - 6020: 0402 c.slli64 s0 - 6022: 0374 addi a3,sp,396 - 6024: 0900 addi s0,sp,144 - 6026: 0000 unimp - 6028: 0001 nop - 602a: 0402 c.slli64 s0 - 602c: 0374 addi a3,sp,396 - 602e: 0900 addi s0,sp,144 - 6030: 0000 unimp - 6032: 0001 nop - 6034: 0402 c.slli64 s0 - 6036: 0374 addi a3,sp,396 - 6038: 0900 addi s0,sp,144 - 603a: 0000 unimp - 603c: 0001 nop - 603e: 0402 c.slli64 s0 - 6040: 0374 addi a3,sp,396 - 6042: 0900 addi s0,sp,144 - 6044: 0000 unimp - 6046: 0001 nop - 6048: 0402 c.slli64 s0 - 604a: 0374 addi a3,sp,396 - 604c: 0900 addi s0,sp,144 - 604e: 0008 0x8 - 6050: 0001 nop - 6052: 0402 c.slli64 s0 - 6054: 0374 addi a3,sp,396 - 6056: 0900 addi s0,sp,144 - 6058: 0008 0x8 - 605a: 0001 nop - 605c: 0402 c.slli64 s0 - 605e: 0374 addi a3,sp,396 - 6060: 0900 addi s0,sp,144 - 6062: 0000 unimp - 6064: 0001 nop - 6066: 0402 c.slli64 s0 - 6068: 0676 slli a2,a2,0x1d - 606a: 04090003 lb zero,64(s2) - 606e: 0100 addi s0,sp,128 - 6070: 0200 addi s0,sp,256 - 6072: 7904 flw fs1,48(a0) - 6074: 0306 slli t1,t1,0x1 - 6076: 0900 addi s0,sp,144 - 6078: 0010 0x10 - 607a: 0601 addi a2,a2,0 - 607c: 08090003 lb zero,128(s2) - 6080: 0100 addi s0,sp,128 - 6082: 0200 addi s0,sp,256 - 6084: 7e04 flw fs1,56(a2) - 6086: 0306 slli t1,t1,0x1 - 6088: 0900 addi s0,sp,144 - 608a: 0008 0x8 - 608c: 0001 nop - 608e: 01840403 lb s0,24(s0) - 6092: 0306 slli t1,t1,0x1 - 6094: 0900 addi s0,sp,144 - 6096: 0018 0x18 - 6098: 0001 nop - 609a: 0402 c.slli64 s0 - 609c: 0678 addi a4,sp,780 - 609e: 08090003 lb zero,128(s2) - 60a2: 0100 addi s0,sp,128 - 60a4: 0200 addi s0,sp,256 - 60a6: 7b04 flw fs1,48(a4) - 60a8: 0306 slli t1,t1,0x1 - 60aa: 0900 addi s0,sp,144 - 60ac: 0018 0x18 - 60ae: 0001 nop - 60b0: 0402 c.slli64 s0 - 60b2: 0003067b 0x3067b - 60b6: 1809 addi a6,a6,-30 - 60b8: 0100 addi s0,sp,128 - 60ba: 0200 addi s0,sp,256 - 60bc: 7b04 flw fs1,48(a4) - 60be: 08090003 lb zero,128(s2) - 60c2: 0100 addi s0,sp,128 - 60c4: 0200 addi s0,sp,256 - 60c6: 7f04 flw fs1,56(a4) - 60c8: 0306 slli t1,t1,0x1 - 60ca: 0900 addi s0,sp,144 - 60cc: 0014 0x14 - 60ce: 0001 nop - 60d0: 01820403 lb s0,24(tp) # 18 <_start-0x7fffffe8> - 60d4: 0306 slli t1,t1,0x1 - 60d6: 0900 addi s0,sp,144 - 60d8: 0004 0x4 - 60da: 0001 nop - 60dc: 01810403 lb s0,24(sp) - 60e0: 24090003 lb zero,576(s2) - 60e4: 0100 addi s0,sp,128 - 60e6: 0300 addi s0,sp,384 - 60e8: 8504 0x8504 - 60ea: 0301 addi t1,t1,0 - 60ec: 0900 addi s0,sp,144 - 60ee: 0028 addi a0,sp,8 - 60f0: 0001 nop - 60f2: 01840403 lb s0,24(s0) - 60f6: 0306 slli t1,t1,0x1 - 60f8: 0900 addi s0,sp,144 - 60fa: 0010 0x10 - 60fc: 0001 nop - 60fe: 01860403 lb s0,24(a2) # b018 <_start-0x7fff4fe8> - 6102: 0306 slli t1,t1,0x1 - 6104: 0900 addi s0,sp,144 - 6106: 0004 0x4 - 6108: 0001 nop - 610a: 01860403 lb s0,24(a2) - 610e: 00090003 lb zero,0(s2) - 6112: 0100 addi s0,sp,128 - 6114: 0300 addi s0,sp,384 - 6116: 8a04 0x8a04 - 6118: 0301 addi t1,t1,0 - 611a: 0900 addi s0,sp,144 - 611c: 0010 0x10 - 611e: 0001 nop - 6120: 018a0403 lb s0,24(s4) - 6124: 00090003 lb zero,0(s2) - 6128: 0100 addi s0,sp,128 - 612a: 0300 addi s0,sp,384 - 612c: 8a04 0x8a04 - 612e: 0301 addi t1,t1,0 - 6130: 0900 addi s0,sp,144 - 6132: 0000 unimp - 6134: 0001 nop - 6136: 018a0403 lb s0,24(s4) - 613a: 00090003 lb zero,0(s2) - 613e: 0100 addi s0,sp,128 - 6140: 0300 addi s0,sp,384 - 6142: 8a04 0x8a04 - 6144: 0301 addi t1,t1,0 - 6146: 0900 addi s0,sp,144 - 6148: 001c 0x1c - 614a: 0001 nop - 614c: 018a0403 lb s0,24(s4) - 6150: 00090003 lb zero,0(s2) - 6154: 0100 addi s0,sp,128 - 6156: 0300 addi s0,sp,384 - 6158: 8a04 0x8a04 - 615a: 0601 addi a2,a2,0 - 615c: 08097f03 0x8097f03 - 6160: 0100 addi s0,sp,128 - 6162: 0300 addi s0,sp,384 - 6164: 8a04 0x8a04 - 6166: 0301 addi t1,t1,0 - 6168: 0901 addi s2,s2,0 - 616a: 0004 0x4 - 616c: 0001 nop - 616e: 018a0403 lb s0,24(s4) - 6172: 0306 slli t1,t1,0x1 - 6174: 0900 addi s0,sp,144 - 6176: 0004 0x4 - 6178: 0001 nop - 617a: 018a0403 lb s0,24(s4) - 617e: 00090003 lb zero,0(s2) - 6182: 0100 addi s0,sp,128 - 6184: 0300 addi s0,sp,384 - 6186: 8a04 0x8a04 - 6188: 0301 addi t1,t1,0 - 618a: 0900 addi s0,sp,144 - 618c: 001c 0x1c - 618e: 0001 nop - 6190: 018a0403 lb s0,24(s4) - 6194: 00090003 lb zero,0(s2) - 6198: 0100 addi s0,sp,128 - 619a: 0300 addi s0,sp,384 - 619c: 8a04 0x8a04 - 619e: 0301 addi t1,t1,0 - 61a0: 0900 addi s0,sp,144 - 61a2: 0004 0x4 - 61a4: 0001 nop - 61a6: 018a0403 lb s0,24(s4) - 61aa: 00090003 lb zero,0(s2) - 61ae: 0100 addi s0,sp,128 - 61b0: 0300 addi s0,sp,384 - 61b2: 8a04 0x8a04 - 61b4: 0301 addi t1,t1,0 - 61b6: 0900 addi s0,sp,144 - 61b8: 001c 0x1c - 61ba: 0001 nop - 61bc: 018a0403 lb s0,24(s4) - 61c0: 00090003 lb zero,0(s2) - 61c4: 0100 addi s0,sp,128 - 61c6: 0200 addi s0,sp,256 - 61c8: 4e04 lw s1,24(a2) - 61ca: 08090003 lb zero,128(s2) - 61ce: 0100 addi s0,sp,128 - 61d0: 0300 addi s0,sp,384 - 61d2: 8c04 0x8c04 - 61d4: 0301 addi t1,t1,0 - 61d6: 0900 addi s0,sp,144 - 61d8: 0034 addi a3,sp,8 - 61da: 0001 nop - 61dc: 018e0403 lb s0,24(t3) # 1a018 <_start-0x7ffe5fe8> - 61e0: 10090003 lb zero,256(s2) - 61e4: 0100 addi s0,sp,128 - 61e6: 0300 addi s0,sp,384 - 61e8: 8e04 0x8e04 - 61ea: 0301 addi t1,t1,0 - 61ec: 0900 addi s0,sp,144 - 61ee: 0000 unimp - 61f0: 0001 nop - 61f2: 01900403 lb s0,25(zero) # 19 <_start-0x7fffffe7> - 61f6: 04090003 lb zero,64(s2) - 61fa: 0100 addi s0,sp,128 - 61fc: 0300 addi s0,sp,384 - 61fe: 9004 0x9004 - 6200: 0301 addi t1,t1,0 - 6202: 0900 addi s0,sp,144 - 6204: 0000 unimp - 6206: 0001 nop - 6208: 01900403 lb s0,25(zero) # 19 <_start-0x7fffffe7> - 620c: 10090003 lb zero,256(s2) - 6210: 0100 addi s0,sp,128 - 6212: 0300 addi s0,sp,384 - 6214: 9104 0x9104 - 6216: 0301 addi t1,t1,0 - 6218: 0900 addi s0,sp,144 - 621a: 0004 0x4 - 621c: 0001 nop - 621e: 01960403 lb s0,25(a2) - 6222: 10090003 lb zero,256(s2) - 6226: 0100 addi s0,sp,128 - 6228: 0300 addi s0,sp,384 - 622a: 9604 0x9604 - 622c: 0301 addi t1,t1,0 - 622e: 0900 addi s0,sp,144 - 6230: 0000 unimp - 6232: 0001 nop - 6234: 01960403 lb s0,25(a2) - 6238: 10090003 lb zero,256(s2) - 623c: 0100 addi s0,sp,128 - 623e: 0300 addi s0,sp,384 - 6240: 9704 0x9704 - 6242: 0301 addi t1,t1,0 - 6244: 0900 addi s0,sp,144 - 6246: 0004 0x4 - 6248: 0001 nop - 624a: 01970403 lb s0,25(a4) - 624e: 00090003 lb zero,0(s2) - 6252: 0100 addi s0,sp,128 - 6254: 0300 addi s0,sp,384 - 6256: 9704 0x9704 - 6258: 0301 addi t1,t1,0 - 625a: 0900 addi s0,sp,144 - 625c: 0000 unimp - 625e: 0001 nop - 6260: 01970403 lb s0,25(a4) - 6264: 00090003 lb zero,0(s2) - 6268: 0100 addi s0,sp,128 - 626a: 0300 addi s0,sp,384 - 626c: 9704 0x9704 - 626e: 0301 addi t1,t1,0 - 6270: 0900 addi s0,sp,144 - 6272: 0000 unimp - 6274: 0001 nop - 6276: 01970403 lb s0,25(a4) - 627a: 10090003 lb zero,256(s2) - 627e: 0100 addi s0,sp,128 - 6280: 0300 addi s0,sp,384 - 6282: 9704 0x9704 - 6284: 0301 addi t1,t1,0 - 6286: 0900 addi s0,sp,144 - 6288: 0000 unimp - 628a: 0001 nop - 628c: 01970403 lb s0,25(a4) - 6290: 00090003 lb zero,0(s2) - 6294: 0100 addi s0,sp,128 - 6296: 0300 addi s0,sp,384 - 6298: 9704 0x9704 - 629a: 0301 addi t1,t1,0 - 629c: 0900 addi s0,sp,144 - 629e: 0000 unimp - 62a0: 0001 nop - 62a2: 01970403 lb s0,25(a4) - 62a6: 18090003 lb zero,384(s2) - 62aa: 0100 addi s0,sp,128 - 62ac: 0300 addi s0,sp,384 - 62ae: 9704 0x9704 - 62b0: 0301 addi t1,t1,0 - 62b2: 0900 addi s0,sp,144 - 62b4: 0000 unimp - 62b6: 0001 nop - 62b8: 01970403 lb s0,25(a4) - 62bc: 00090003 lb zero,0(s2) - 62c0: 0100 addi s0,sp,128 - 62c2: 0300 addi s0,sp,384 - 62c4: 9704 0x9704 - 62c6: 0301 addi t1,t1,0 - 62c8: 0900 addi s0,sp,144 - 62ca: 0000 unimp - 62cc: 0001 nop - 62ce: 01970403 lb s0,25(a4) - 62d2: 1c090003 lb zero,448(s2) - 62d6: 0100 addi s0,sp,128 - 62d8: 0300 addi s0,sp,384 - 62da: 9704 0x9704 - 62dc: 0301 addi t1,t1,0 - 62de: 0900 addi s0,sp,144 - 62e0: 0000 unimp - 62e2: 0001 nop - 62e4: 01970403 lb s0,25(a4) - 62e8: 00090003 lb zero,0(s2) - 62ec: 0100 addi s0,sp,128 - 62ee: 0306 slli t1,t1,0x1 - 62f0: 0900 addi s0,sp,144 - 62f2: 0008 0x8 - 62f4: 0001 nop - 62f6: 01990403 lb s0,25(s2) - 62fa: 0306 slli t1,t1,0x1 - 62fc: 0900 addi s0,sp,144 - 62fe: 0008 0x8 - 6300: 0001 nop - 6302: 01990403 lb s0,25(s2) - 6306: 10090003 lb zero,256(s2) - 630a: 0100 addi s0,sp,128 - 630c: 0300 addi s0,sp,384 - 630e: aa04 fsd fs1,16(a2) - 6310: 0301 addi t1,t1,0 - 6312: 0900 addi s0,sp,144 - 6314: 0008 0x8 - 6316: 0001 nop - 6318: 01aa0403 lb s0,26(s4) - 631c: 00090003 lb zero,0(s2) - 6320: 0100 addi s0,sp,128 - 6322: 0300 addi s0,sp,384 - 6324: aa04 fsd fs1,16(a2) - 6326: 0301 addi t1,t1,0 - 6328: 0900 addi s0,sp,144 - 632a: 0000 unimp - 632c: 0001 nop - 632e: 01aa0403 lb s0,26(s4) - 6332: 00090003 lb zero,0(s2) - 6336: 0100 addi s0,sp,128 - 6338: 0300 addi s0,sp,384 - 633a: aa04 fsd fs1,16(a2) - 633c: 0301 addi t1,t1,0 - 633e: 0900 addi s0,sp,144 - 6340: 0000 unimp - 6342: 0001 nop - 6344: 01aa0403 lb s0,26(s4) - 6348: 00090003 lb zero,0(s2) - 634c: 0100 addi s0,sp,128 - 634e: 0300 addi s0,sp,384 - 6350: ab04 fsd fs1,16(a4) - 6352: 0301 addi t1,t1,0 - 6354: 0900 addi s0,sp,144 - 6356: 0004 0x4 - 6358: 0001 nop - 635a: 01ae0403 lb s0,26(t3) - 635e: 0306 slli t1,t1,0x1 - 6360: 0900 addi s0,sp,144 - 6362: 0010 0x10 - 6364: 0001 nop - 6366: 01ac0403 lb s0,26(s8) - 636a: 0306 slli t1,t1,0x1 - 636c: 0900 addi s0,sp,144 - 636e: 0008 0x8 - 6370: 0001 nop - 6372: 01ae0403 lb s0,26(t3) - 6376: 10090003 lb zero,256(s2) - 637a: 0100 addi s0,sp,128 - 637c: 0300 addi s0,sp,384 - 637e: c604 sw s1,8(a2) - 6380: 0301 addi t1,t1,0 - 6382: 0900 addi s0,sp,144 - 6384: 0014 0x14 - 6386: 0001 nop - 6388: 01c60403 lb s0,28(a2) - 638c: 00090003 lb zero,0(s2) - 6390: 0100 addi s0,sp,128 - 6392: 0300 addi s0,sp,384 - 6394: c604 sw s1,8(a2) - 6396: 0301 addi t1,t1,0 - 6398: 0900 addi s0,sp,144 - 639a: 0000 unimp - 639c: 0001 nop - 639e: 01c60403 lb s0,28(a2) - 63a2: 00090003 lb zero,0(s2) - 63a6: 0100 addi s0,sp,128 - 63a8: 0300 addi s0,sp,384 - 63aa: c604 sw s1,8(a2) - 63ac: 0301 addi t1,t1,0 - 63ae: 0900 addi s0,sp,144 - 63b0: 0000 unimp - 63b2: 0001 nop - 63b4: 01c60403 lb s0,28(a2) - 63b8: 10090003 lb zero,256(s2) - 63bc: 0100 addi s0,sp,128 - 63be: 0300 addi s0,sp,384 - 63c0: c604 sw s1,8(a2) - 63c2: 0301 addi t1,t1,0 - 63c4: 0900 addi s0,sp,144 - 63c6: 0000 unimp - 63c8: 0001 nop - 63ca: 01c60403 lb s0,28(a2) - 63ce: 00090003 lb zero,0(s2) - 63d2: 0100 addi s0,sp,128 - 63d4: 0300 addi s0,sp,384 - 63d6: c604 sw s1,8(a2) - 63d8: 0301 addi t1,t1,0 - 63da: 0900 addi s0,sp,144 - 63dc: 0000 unimp - 63de: 0001 nop - 63e0: 01c60403 lb s0,28(a2) - 63e4: 00090003 lb zero,0(s2) - 63e8: 0100 addi s0,sp,128 - 63ea: 0300 addi s0,sp,384 - 63ec: c604 sw s1,8(a2) - 63ee: 0301 addi t1,t1,0 - 63f0: 0900 addi s0,sp,144 - 63f2: 0000 unimp - 63f4: 0001 nop - 63f6: 01c60403 lb s0,28(a2) - 63fa: 00090003 lb zero,0(s2) - 63fe: 0100 addi s0,sp,128 - 6400: 0300 addi s0,sp,384 - 6402: c604 sw s1,8(a2) - 6404: 0301 addi t1,t1,0 - 6406: 0900 addi s0,sp,144 - 6408: 0000 unimp - 640a: 0001 nop - 640c: 01c60403 lb s0,28(a2) - 6410: 00090003 lb zero,0(s2) - 6414: 0100 addi s0,sp,128 - 6416: 0300 addi s0,sp,384 - 6418: d204 sw s1,32(a2) - 641a: 0301 addi t1,t1,0 - 641c: 0900 addi s0,sp,144 - 641e: 0004 0x4 - 6420: 0001 nop - 6422: 04bc0403 lb s0,75(s8) - 6426: 20090003 lb zero,512(s2) - 642a: 0100 addi s0,sp,128 - 642c: 0300 addi s0,sp,384 - 642e: 8d04 0x8d04 - 6430: 0301 addi t1,t1,0 - 6432: 0900 addi s0,sp,144 - 6434: 001c 0x1c - 6436: 0001 nop - 6438: 018d0403 lb s0,24(s10) - 643c: 00090003 lb zero,0(s2) - 6440: 0100 addi s0,sp,128 - 6442: 0300 addi s0,sp,384 - 6444: 8d04 0x8d04 - 6446: 0301 addi t1,t1,0 - 6448: 0900 addi s0,sp,144 - 644a: 0000 unimp - 644c: 0001 nop - 644e: 018d0403 lb s0,24(s10) - 6452: 00090003 lb zero,0(s2) - 6456: 0100 addi s0,sp,128 - 6458: 0300 addi s0,sp,384 - 645a: 8d04 0x8d04 - 645c: 0301 addi t1,t1,0 - 645e: 0900 addi s0,sp,144 - 6460: 0010 0x10 - 6462: 0001 nop - 6464: 018d0403 lb s0,24(s10) - 6468: 00090003 lb zero,0(s2) - 646c: 0100 addi s0,sp,128 - 646e: 0300 addi s0,sp,384 - 6470: 8d04 0x8d04 - 6472: 0301 addi t1,t1,0 - 6474: 0900 addi s0,sp,144 - 6476: 0000 unimp - 6478: 0001 nop - 647a: 018d0403 lb s0,24(s10) - 647e: 00090003 lb zero,0(s2) - 6482: 0100 addi s0,sp,128 - 6484: 0300 addi s0,sp,384 - 6486: 8d04 0x8d04 - 6488: 0301 addi t1,t1,0 - 648a: 0900 addi s0,sp,144 - 648c: 0030 addi a2,sp,8 - 648e: 0001 nop - 6490: 018d0403 lb s0,24(s10) - 6494: 00090003 lb zero,0(s2) - 6498: 0100 addi s0,sp,128 - 649a: 0300 addi s0,sp,384 - 649c: 8d04 0x8d04 - 649e: 0301 addi t1,t1,0 - 64a0: 0900 addi s0,sp,144 - 64a2: 0000 unimp - 64a4: 0001 nop - 64a6: 018d0403 lb s0,24(s10) - 64aa: 00090003 lb zero,0(s2) - 64ae: 0100 addi s0,sp,128 - 64b0: 0300 addi s0,sp,384 - 64b2: 8d04 0x8d04 - 64b4: 0301 addi t1,t1,0 - 64b6: 0900 addi s0,sp,144 - 64b8: 0004 0x4 - 64ba: 0001 nop - 64bc: 018d0403 lb s0,24(s10) - 64c0: 00090003 lb zero,0(s2) - 64c4: 0100 addi s0,sp,128 - 64c6: 0300 addi s0,sp,384 - 64c8: 8d04 0x8d04 - 64ca: 0301 addi t1,t1,0 - 64cc: 0900 addi s0,sp,144 - 64ce: 0004 0x4 - 64d0: 0001 nop - 64d2: 018d0403 lb s0,24(s10) - 64d6: 00090003 lb zero,0(s2) - 64da: 0100 addi s0,sp,128 - 64dc: 0300 addi s0,sp,384 - 64de: 8d04 0x8d04 - 64e0: 0301 addi t1,t1,0 - 64e2: 0900 addi s0,sp,144 - 64e4: 0000 unimp - 64e6: 0001 nop - 64e8: 018d0403 lb s0,24(s10) - 64ec: 00090003 lb zero,0(s2) - 64f0: 0100 addi s0,sp,128 - 64f2: 0300 addi s0,sp,384 - 64f4: 8d04 0x8d04 - 64f6: 0301 addi t1,t1,0 - 64f8: 0900 addi s0,sp,144 - 64fa: 0000 unimp - 64fc: 0001 nop - 64fe: 018d0403 lb s0,24(s10) - 6502: 00090003 lb zero,0(s2) - 6506: 0100 addi s0,sp,128 - 6508: 0300 addi s0,sp,384 - 650a: 8d04 0x8d04 - 650c: 0301 addi t1,t1,0 - 650e: 0900 addi s0,sp,144 - 6510: 0000 unimp - 6512: 0001 nop - 6514: 018d0403 lb s0,24(s10) - 6518: 00090003 lb zero,0(s2) - 651c: 0100 addi s0,sp,128 - 651e: 0300 addi s0,sp,384 - 6520: 8d04 0x8d04 - 6522: 0301 addi t1,t1,0 - 6524: 0900 addi s0,sp,144 - 6526: 0000 unimp - 6528: 0001 nop - 652a: 018d0403 lb s0,24(s10) - 652e: 00090003 lb zero,0(s2) - 6532: 0100 addi s0,sp,128 - 6534: 0300 addi s0,sp,384 - 6536: 8d04 0x8d04 - 6538: 0301 addi t1,t1,0 - 653a: 0900 addi s0,sp,144 - 653c: 0000 unimp - 653e: 0001 nop - 6540: 018d0403 lb s0,24(s10) - 6544: 00090003 lb zero,0(s2) - 6548: 0100 addi s0,sp,128 - 654a: 0300 addi s0,sp,384 - 654c: 8d04 0x8d04 - 654e: 0301 addi t1,t1,0 - 6550: 0900 addi s0,sp,144 - 6552: 0000 unimp - 6554: 0001 nop - 6556: 018d0403 lb s0,24(s10) - 655a: 00090003 lb zero,0(s2) - 655e: 0100 addi s0,sp,128 - 6560: 0300 addi s0,sp,384 - 6562: e404 fsw fs1,8(s0) - 6564: 0301 addi t1,t1,0 - 6566: 0900 addi s0,sp,144 - 6568: 0004 0x4 - 656a: 0001 nop - 656c: 01e50403 lb s0,30(a0) # ffffc01e <__BSS_END__+0x7ffe52a6> - 6570: 20090003 lb zero,512(s2) - 6574: 0100 addi s0,sp,128 - 6576: 0300 addi s0,sp,384 - 6578: e504 fsw fs1,8(a0) - 657a: 0301 addi t1,t1,0 - 657c: 0900 addi s0,sp,144 - 657e: 0000 unimp - 6580: 0001 nop - 6582: 01e50403 lb s0,30(a0) - 6586: 00090003 lb zero,0(s2) - 658a: 0100 addi s0,sp,128 - 658c: 0300 addi s0,sp,384 - 658e: e504 fsw fs1,8(a0) - 6590: 0301 addi t1,t1,0 - 6592: 0900 addi s0,sp,144 - 6594: 0000 unimp - 6596: 0601 addi a2,a2,0 - 6598: 0c090003 lb zero,192(s2) - 659c: 0100 addi s0,sp,128 - 659e: 0300 addi s0,sp,384 - 65a0: f404 fsw fs1,40(s0) - 65a2: 0601 addi a2,a2,0 - 65a4: 0c090003 lb zero,192(s2) - 65a8: 0100 addi s0,sp,128 - 65aa: 0300 addi s0,sp,384 - 65ac: f404 fsw fs1,40(s0) - 65ae: 0301 addi t1,t1,0 - 65b0: 0900 addi s0,sp,144 - 65b2: 0000 unimp - 65b4: 0001 nop - 65b6: 01f40403 lb s0,31(s0) - 65ba: 08090003 lb zero,128(s2) - 65be: 0100 addi s0,sp,128 - 65c0: 0300 addi s0,sp,384 - 65c2: f404 fsw fs1,40(s0) - 65c4: 0301 addi t1,t1,0 - 65c6: 0900 addi s0,sp,144 - 65c8: 0000 unimp - 65ca: 0001 nop - 65cc: 01f40403 lb s0,31(s0) - 65d0: 00090003 lb zero,0(s2) - 65d4: 0100 addi s0,sp,128 - 65d6: 0300 addi s0,sp,384 - 65d8: f404 fsw fs1,40(s0) - 65da: 0301 addi t1,t1,0 - 65dc: 0900 addi s0,sp,144 - 65de: 0000 unimp - 65e0: 0001 nop - 65e2: 0402 c.slli64 s0 - 65e4: 030d addi t1,t1,3 - 65e6: 0900 addi s0,sp,144 - 65e8: 0014 0x14 - 65ea: 0001 nop - 65ec: 0402 c.slli64 s0 - 65ee: 030d addi t1,t1,3 - 65f0: 0900 addi s0,sp,144 - 65f2: 0000 unimp - 65f4: 0001 nop - 65f6: 029d0403 lb s0,41(s10) - 65fa: 04090003 lb zero,64(s2) - 65fe: 0100 addi s0,sp,128 - 6600: 0300 addi s0,sp,384 - 6602: 9d04 0x9d04 - 6604: 0302 c.slli64 t1 - 6606: 0900 addi s0,sp,144 - 6608: 0000 unimp - 660a: 0001 nop - 660c: 029d0403 lb s0,41(s10) - 6610: 00090003 lb zero,0(s2) - 6614: 0100 addi s0,sp,128 - 6616: 0300 addi s0,sp,384 - 6618: 9f04 0x9f04 - 661a: 0302 c.slli64 t1 - 661c: 0900 addi s0,sp,144 - 661e: 0004 0x4 - 6620: 0001 nop - 6622: 02a20403 lb s0,42(tp) # 2a <_start-0x7fffffd6> - 6626: 1c090003 lb zero,448(s2) - 662a: 0100 addi s0,sp,128 - 662c: 0300 addi s0,sp,384 - 662e: a204 fsd fs1,0(a2) - 6630: 0302 c.slli64 t1 - 6632: 0900 addi s0,sp,144 - 6634: 0000 unimp - 6636: 0001 nop - 6638: 02a20403 lb s0,42(tp) # 2a <_start-0x7fffffd6> - 663c: 04090003 lb zero,64(s2) - 6640: 0100 addi s0,sp,128 - 6642: 0300 addi s0,sp,384 - 6644: ab04 fsd fs1,16(a4) - 6646: 0302 c.slli64 t1 - 6648: 0900 addi s0,sp,144 - 664a: 0004 0x4 - 664c: 0001 nop - 664e: 02ab0403 lb s0,42(s6) - 6652: 00090003 lb zero,0(s2) - 6656: 0100 addi s0,sp,128 - 6658: 0300 addi s0,sp,384 - 665a: ab04 fsd fs1,16(a4) - 665c: 0302 c.slli64 t1 - 665e: 0900 addi s0,sp,144 - 6660: 0000 unimp - 6662: 0001 nop - 6664: 02ab0403 lb s0,42(s6) - 6668: 00090003 lb zero,0(s2) - 666c: 0100 addi s0,sp,128 - 666e: 0300 addi s0,sp,384 - 6670: ab04 fsd fs1,16(a4) - 6672: 0302 c.slli64 t1 - 6674: 0900 addi s0,sp,144 - 6676: 001c 0x1c - 6678: 0001 nop - 667a: 02ab0403 lb s0,42(s6) - 667e: 00090003 lb zero,0(s2) - 6682: 0100 addi s0,sp,128 - 6684: 0300 addi s0,sp,384 - 6686: ab04 fsd fs1,16(a4) - 6688: 0302 c.slli64 t1 - 668a: 0900 addi s0,sp,144 - 668c: 0000 unimp - 668e: 0001 nop - 6690: 02ab0403 lb s0,42(s6) - 6694: 00090003 lb zero,0(s2) - 6698: 0100 addi s0,sp,128 - 669a: 0300 addi s0,sp,384 - 669c: ab04 fsd fs1,16(a4) - 669e: 0302 c.slli64 t1 - 66a0: 0900 addi s0,sp,144 - 66a2: 0004 0x4 - 66a4: 0001 nop - 66a6: 02ad0403 lb s0,42(s10) - 66aa: 0306 slli t1,t1,0x1 - 66ac: 0900 addi s0,sp,144 - 66ae: 0008 0x8 - 66b0: 0001 nop - 66b2: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> - 66b6: 08090003 lb zero,128(s2) - 66ba: 0100 addi s0,sp,128 - 66bc: 0300 addi s0,sp,384 - 66be: b204 fsd fs1,32(a2) - 66c0: 0602 c.slli64 a2 - 66c2: 08090003 lb zero,128(s2) - 66c6: 0100 addi s0,sp,128 - 66c8: 0300 addi s0,sp,384 - 66ca: b204 fsd fs1,32(a2) - 66cc: 0302 c.slli64 t1 - 66ce: 0900 addi s0,sp,144 - 66d0: 0004 0x4 - 66d2: 0001 nop - 66d4: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> - 66d8: 04090003 lb zero,64(s2) - 66dc: 0100 addi s0,sp,128 - 66de: 0300 addi s0,sp,384 - 66e0: b204 fsd fs1,32(a2) - 66e2: 0302 c.slli64 t1 - 66e4: 0900 addi s0,sp,144 - 66e6: 0008 0x8 - 66e8: 0001 nop - 66ea: 02b30403 lb s0,43(t1) - 66ee: 0306 slli t1,t1,0x1 - 66f0: 0900 addi s0,sp,144 - 66f2: 0004 0x4 - 66f4: 0001 nop - 66f6: 02b80403 lb s0,43(a6) - 66fa: 0306 slli t1,t1,0x1 - 66fc: 0900 addi s0,sp,144 - 66fe: 0008 0x8 - 6700: 0001 nop - 6702: 02b80403 lb s0,43(a6) - 6706: 14090003 lb zero,320(s2) - 670a: 0100 addi s0,sp,128 - 670c: 0300 addi s0,sp,384 - 670e: 8f04 0x8f04 - 6710: 7f030603 lb a2,2032(t1) - 6714: 0009 c.nop 2 - 6716: 0100 addi s0,sp,128 - 6718: 0300 addi s0,sp,384 - 671a: 8f04 0x8f04 - 671c: 09010303 lb t1,144(sp) - 6720: 0004 0x4 - 6722: 0001 nop - 6724: 02ac0403 lb s0,42(s8) - 6728: 0306 slli t1,t1,0x1 - 672a: 0900 addi s0,sp,144 - 672c: 0004 0x4 - 672e: 0301 addi t1,t1,0 - 6730: 0900 addi s0,sp,144 - 6732: 000c 0xc - 6734: 0301 addi t1,t1,0 - 6736: 0900 addi s0,sp,144 - 6738: 0008 0x8 - 673a: 0001 nop - 673c: 02a00403 lb s0,42(zero) # 2a <_start-0x7fffffd6> - 6740: 18090003 lb zero,384(s2) - 6744: 0100 addi s0,sp,128 - 6746: 0300 addi s0,sp,384 - 6748: c604 sw s1,8(a2) - 674a: 0302 c.slli64 t1 - 674c: 0900 addi s0,sp,144 - 674e: 000c 0xc - 6750: 0001 nop - 6752: 02c60403 lb s0,44(a2) - 6756: 10090003 lb zero,256(s2) - 675a: 0100 addi s0,sp,128 - 675c: 0300 addi s0,sp,384 - 675e: d004 sw s1,32(s0) - 6760: 0302 c.slli64 t1 - 6762: 0900 addi s0,sp,144 - 6764: 000c 0xc - 6766: 0001 nop - 6768: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 676c: 00090003 lb zero,0(s2) - 6770: 0100 addi s0,sp,128 - 6772: 0300 addi s0,sp,384 - 6774: d004 sw s1,32(s0) - 6776: 0302 c.slli64 t1 - 6778: 0900 addi s0,sp,144 - 677a: 0000 unimp - 677c: 0001 nop - 677e: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 6782: 00090003 lb zero,0(s2) - 6786: 0100 addi s0,sp,128 - 6788: 0300 addi s0,sp,384 - 678a: d004 sw s1,32(s0) - 678c: 0302 c.slli64 t1 - 678e: 0900 addi s0,sp,144 - 6790: 0000 unimp - 6792: 0001 nop - 6794: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 6798: 00090003 lb zero,0(s2) - 679c: 0100 addi s0,sp,128 - 679e: 0300 addi s0,sp,384 - 67a0: d004 sw s1,32(s0) - 67a2: 0302 c.slli64 t1 - 67a4: 0900 addi s0,sp,144 - 67a6: 0000 unimp - 67a8: 0001 nop - 67aa: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 67ae: 04090003 lb zero,64(s2) - 67b2: 0100 addi s0,sp,128 - 67b4: 0300 addi s0,sp,384 - 67b6: d004 sw s1,32(s0) - 67b8: 0302 c.slli64 t1 - 67ba: 0900 addi s0,sp,144 - 67bc: 0004 0x4 - 67be: 0001 nop - 67c0: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 67c4: 00090003 lb zero,0(s2) - 67c8: 0100 addi s0,sp,128 - 67ca: 0300 addi s0,sp,384 - 67cc: d204 sw s1,32(a2) - 67ce: 0602 c.slli64 a2 - 67d0: 08090003 lb zero,128(s2) - 67d4: 0100 addi s0,sp,128 - 67d6: 0300 addi s0,sp,384 - 67d8: d504 sw s1,40(a0) - 67da: 0602 c.slli64 a2 - 67dc: 08090003 lb zero,128(s2) - 67e0: 0100 addi s0,sp,128 - 67e2: 0306 slli t1,t1,0x1 - 67e4: 0900 addi s0,sp,144 - 67e6: 0004 0x4 - 67e8: 0001 nop - 67ea: 02da0403 lb s0,45(s4) - 67ee: 0306 slli t1,t1,0x1 - 67f0: 0900 addi s0,sp,144 - 67f2: 0008 0x8 - 67f4: 0001 nop - 67f6: 02e00403 lb s0,46(zero) # 2e <_start-0x7fffffd2> - 67fa: 0306 slli t1,t1,0x1 - 67fc: 0900 addi s0,sp,144 - 67fe: 0018 0x18 - 6800: 0001 nop - 6802: 02d40403 lb s0,45(s0) - 6806: 0306 slli t1,t1,0x1 - 6808: 0900 addi s0,sp,144 - 680a: 0008 0x8 - 680c: 0001 nop - 680e: 02d70403 lb s0,45(a4) - 6812: 0306 slli t1,t1,0x1 - 6814: 0900 addi s0,sp,144 - 6816: 0014 0x14 - 6818: 0001 nop - 681a: 02d70403 lb s0,45(a4) - 681e: 0306 slli t1,t1,0x1 - 6820: 0900 addi s0,sp,144 - 6822: 0014 0x14 - 6824: 0001 nop - 6826: 02d70403 lb s0,45(a4) - 682a: 08090003 lb zero,128(s2) - 682e: 0100 addi s0,sp,128 - 6830: 0300 addi s0,sp,384 - 6832: db04 sw s1,48(a4) - 6834: 0602 c.slli64 a2 - 6836: 14090003 lb zero,320(s2) - 683a: 0100 addi s0,sp,128 - 683c: 0300 addi s0,sp,384 - 683e: de04 sw s1,56(a2) - 6840: 0602 c.slli64 a2 - 6842: 04090003 lb zero,64(s2) - 6846: 0100 addi s0,sp,128 - 6848: 0300 addi s0,sp,384 - 684a: dd04 sw s1,56(a0) - 684c: 0302 c.slli64 t1 - 684e: 0900 addi s0,sp,144 - 6850: 0024 addi s1,sp,8 - 6852: 0001 nop - 6854: 02e10403 lb s0,46(sp) - 6858: 28090003 lb zero,640(s2) - 685c: 0100 addi s0,sp,128 - 685e: 0300 addi s0,sp,384 - 6860: e004 fsw fs1,0(s0) - 6862: 0602 c.slli64 a2 - 6864: 10090003 lb zero,256(s2) - 6868: 0100 addi s0,sp,128 - 686a: 0300 addi s0,sp,384 - 686c: e204 fsw fs1,0(a2) - 686e: 0602 c.slli64 a2 - 6870: 04090003 lb zero,64(s2) - 6874: 0100 addi s0,sp,128 - 6876: 0300 addi s0,sp,384 - 6878: e204 fsw fs1,0(a2) - 687a: 0302 c.slli64 t1 - 687c: 0900 addi s0,sp,144 - 687e: 0000 unimp - 6880: 0001 nop - 6882: 02e60403 lb s0,46(a2) - 6886: 10090003 lb zero,256(s2) - 688a: 0100 addi s0,sp,128 - 688c: 0300 addi s0,sp,384 - 688e: e604 fsw fs1,8(a2) - 6890: 0302 c.slli64 t1 - 6892: 0900 addi s0,sp,144 - 6894: 0000 unimp - 6896: 0001 nop - 6898: 02e60403 lb s0,46(a2) - 689c: 00090003 lb zero,0(s2) - 68a0: 0100 addi s0,sp,128 - 68a2: 0300 addi s0,sp,384 - 68a4: e604 fsw fs1,8(a2) - 68a6: 0302 c.slli64 t1 - 68a8: 0900 addi s0,sp,144 - 68aa: 0000 unimp - 68ac: 0001 nop - 68ae: 02e60403 lb s0,46(a2) - 68b2: 2c090003 lb zero,704(s2) - 68b6: 0100 addi s0,sp,128 - 68b8: 0300 addi s0,sp,384 - 68ba: e604 fsw fs1,8(a2) - 68bc: 0302 c.slli64 t1 - 68be: 0900 addi s0,sp,144 - 68c0: 0000 unimp - 68c2: 0001 nop - 68c4: 02e60403 lb s0,46(a2) - 68c8: 00090003 lb zero,0(s2) - 68cc: 0100 addi s0,sp,128 - 68ce: 0300 addi s0,sp,384 - 68d0: e604 fsw fs1,8(a2) - 68d2: 0302 c.slli64 t1 - 68d4: 0900 addi s0,sp,144 - 68d6: 0000 unimp - 68d8: 0001 nop - 68da: 02e60403 lb s0,46(a2) - 68de: 00090003 lb zero,0(s2) - 68e2: 0100 addi s0,sp,128 - 68e4: 0300 addi s0,sp,384 - 68e6: e704 fsw fs1,8(a4) - 68e8: 0602 c.slli64 a2 - 68ea: 08090003 lb zero,128(s2) - 68ee: 0100 addi s0,sp,128 - 68f0: 0300 addi s0,sp,384 - 68f2: ec04 fsw fs1,24(s0) - 68f4: 0302 c.slli64 t1 - 68f6: 0900 addi s0,sp,144 - 68f8: 0004 0x4 - 68fa: 0001 nop - 68fc: 02ec0403 lb s0,46(s8) - 6900: 0306 slli t1,t1,0x1 - 6902: 0900 addi s0,sp,144 - 6904: 0004 0x4 - 6906: 0001 nop - 6908: 02ec0403 lb s0,46(s8) - 690c: 0c090003 lb zero,192(s2) - 6910: 0100 addi s0,sp,128 - 6912: 0300 addi s0,sp,384 - 6914: ec04 fsw fs1,24(s0) - 6916: 0302 c.slli64 t1 - 6918: 0900 addi s0,sp,144 - 691a: 000c 0xc - 691c: 0001 nop - 691e: 02ec0403 lb s0,46(s8) - 6922: 00090003 lb zero,0(s2) - 6926: 0100 addi s0,sp,128 - 6928: 0300 addi s0,sp,384 - 692a: ed04 fsw fs1,24(a0) - 692c: 0602 c.slli64 a2 - 692e: 08090003 lb zero,128(s2) - 6932: 0100 addi s0,sp,128 - 6934: 0300 addi s0,sp,384 - 6936: f204 fsw fs1,32(a2) - 6938: 0602 c.slli64 a2 - 693a: 04090003 lb zero,64(s2) - 693e: 0100 addi s0,sp,128 - 6940: 0300 addi s0,sp,384 - 6942: ca04 sw s1,16(a2) - 6944: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6948: 0018 0x18 - 694a: 0001 nop - 694c: 04e10403 lb s0,78(sp) - 6950: 0c090003 lb zero,192(s2) - 6954: 0100 addi s0,sp,128 - 6956: 0300 addi s0,sp,384 - 6958: e104 fsw fs1,0(a0) - 695a: 0304 addi s1,sp,384 - 695c: 0900 addi s0,sp,144 - 695e: 0000 unimp - 6960: 0001 nop - 6962: 029e0403 lb s0,41(t3) - 6966: 14090003 lb zero,320(s2) - 696a: 0100 addi s0,sp,128 - 696c: 0300 addi s0,sp,384 - 696e: f404 fsw fs1,40(s0) - 6970: 0302 c.slli64 t1 - 6972: 0900 addi s0,sp,144 - 6974: 0004 0x4 - 6976: 0001 nop - 6978: 02f40403 lb s0,47(s0) - 697c: 04090003 lb zero,64(s2) - 6980: 0100 addi s0,sp,128 - 6982: 0300 addi s0,sp,384 - 6984: f404 fsw fs1,40(s0) - 6986: 0302 c.slli64 t1 - 6988: 0900 addi s0,sp,144 - 698a: 0000 unimp - 698c: 0001 nop - 698e: 02f40403 lb s0,47(s0) - 6992: 00090003 lb zero,0(s2) - 6996: 0100 addi s0,sp,128 - 6998: 0300 addi s0,sp,384 - 699a: f604 fsw fs1,40(a2) - 699c: 0302 c.slli64 t1 - 699e: 0900 addi s0,sp,144 - 69a0: 0004 0x4 - 69a2: 0001 nop - 69a4: 03990403 lb s0,57(s2) - 69a8: 1c090003 lb zero,448(s2) - 69ac: 0100 addi s0,sp,128 - 69ae: 0300 addi s0,sp,384 - 69b0: 9904 0x9904 - 69b2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 69b6: 0000 unimp - 69b8: 0001 nop - 69ba: 03990403 lb s0,57(s2) - 69be: 00090003 lb zero,0(s2) - 69c2: 0100 addi s0,sp,128 - 69c4: 0300 addi s0,sp,384 - 69c6: 9904 0x9904 - 69c8: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 69cc: 0020 addi s0,sp,8 - 69ce: 0001 nop - 69d0: 03f20403 lb s0,63(tp) # 3f <_start-0x7fffffc1> - 69d4: 00090003 lb zero,0(s2) - 69d8: 0100 addi s0,sp,128 - 69da: 0300 addi s0,sp,384 - 69dc: f904 fsw fs1,48(a0) - 69de: 0302 c.slli64 t1 - 69e0: 0900 addi s0,sp,144 - 69e2: 0008 0x8 - 69e4: 0001 nop - 69e6: 02f90403 lb s0,47(s2) - 69ea: 00090003 lb zero,0(s2) - 69ee: 0100 addi s0,sp,128 - 69f0: 0300 addi s0,sp,384 - 69f2: f904 fsw fs1,48(a0) - 69f4: 0302 c.slli64 t1 - 69f6: 0900 addi s0,sp,144 - 69f8: 0004 0x4 - 69fa: 0001 nop - 69fc: 03820403 lb s0,56(tp) # 38 <_start-0x7fffffc8> - 6a00: 04090003 lb zero,64(s2) - 6a04: 0100 addi s0,sp,128 - 6a06: 0300 addi s0,sp,384 - 6a08: 8204 0x8204 - 6a0a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6a0e: 0000 unimp - 6a10: 0001 nop - 6a12: 03820403 lb s0,56(tp) # 38 <_start-0x7fffffc8> - 6a16: 00090003 lb zero,0(s2) - 6a1a: 0100 addi s0,sp,128 - 6a1c: 0300 addi s0,sp,384 - 6a1e: 8204 0x8204 - 6a20: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6a24: 0000 unimp - 6a26: 0001 nop - 6a28: 03820403 lb s0,56(tp) # 38 <_start-0x7fffffc8> - 6a2c: 1c090003 lb zero,448(s2) - 6a30: 0100 addi s0,sp,128 - 6a32: 0300 addi s0,sp,384 - 6a34: 8204 0x8204 - 6a36: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6a3a: 0000 unimp - 6a3c: 0001 nop - 6a3e: 03820403 lb s0,56(tp) # 38 <_start-0x7fffffc8> - 6a42: 00090003 lb zero,0(s2) - 6a46: 0100 addi s0,sp,128 - 6a48: 0300 addi s0,sp,384 - 6a4a: 8204 0x8204 - 6a4c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6a50: 0000 unimp - 6a52: 0001 nop - 6a54: 03820403 lb s0,56(tp) # 38 <_start-0x7fffffc8> - 6a58: 04090003 lb zero,64(s2) - 6a5c: 0100 addi s0,sp,128 - 6a5e: 0300 addi s0,sp,384 - 6a60: 8404 0x8404 - 6a62: 00030603 lb a2,0(t1) - 6a66: 0809 addi a6,a6,2 - 6a68: 0100 addi s0,sp,128 - 6a6a: 0300 addi s0,sp,384 - 6a6c: 8904 0x8904 - 6a6e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6a72: 0008 0x8 - 6a74: 0001 nop - 6a76: 03890403 lb s0,56(s2) - 6a7a: 0306 slli t1,t1,0x1 - 6a7c: 0900 addi s0,sp,144 - 6a7e: 0008 0x8 - 6a80: 0001 nop - 6a82: 03890403 lb s0,56(s2) - 6a86: 04090003 lb zero,64(s2) - 6a8a: 0100 addi s0,sp,128 - 6a8c: 0300 addi s0,sp,384 - 6a8e: 8904 0x8904 - 6a90: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6a94: 0004 0x4 - 6a96: 0001 nop - 6a98: 03890403 lb s0,56(s2) - 6a9c: 08090003 lb zero,128(s2) - 6aa0: 0100 addi s0,sp,128 - 6aa2: 0300 addi s0,sp,384 - 6aa4: 8a04 0x8a04 - 6aa6: 00030603 lb a2,0(t1) - 6aaa: 0409 addi s0,s0,2 - 6aac: 0100 addi s0,sp,128 - 6aae: 0300 addi s0,sp,384 - 6ab0: 8f04 0x8f04 - 6ab2: 00030603 lb a2,0(t1) - 6ab6: 0809 addi a6,a6,2 - 6ab8: 0100 addi s0,sp,128 - 6aba: 0300 addi s0,sp,384 - 6abc: 8f04 0x8f04 - 6abe: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6ac2: 0018 0x18 - 6ac4: 0001 nop - 6ac6: 03830403 lb s0,56(t1) - 6aca: 04090003 lb zero,64(s2) - 6ace: 0100 addi s0,sp,128 - 6ad0: 0c090003 lb zero,192(s2) - 6ad4: 0100 addi s0,sp,128 - 6ad6: 08090003 lb zero,128(s2) - 6ada: 0100 addi s0,sp,128 - 6adc: 0300 addi s0,sp,384 - 6ade: f704 fsw fs1,40(a4) - 6ae0: 0302 c.slli64 t1 - 6ae2: 0900 addi s0,sp,144 - 6ae4: 0018 0x18 - 6ae6: 0001 nop - 6ae8: 03a40403 lb s0,58(s0) - 6aec: 0c090003 lb zero,192(s2) - 6af0: 0100 addi s0,sp,128 - 6af2: 0300 addi s0,sp,384 - 6af4: a404 fsd fs1,8(s0) - 6af6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6afa: 0000 unimp - 6afc: 0001 nop - 6afe: 03a40403 lb s0,58(s0) - 6b02: 00090003 lb zero,0(s2) - 6b06: 0100 addi s0,sp,128 - 6b08: 0300 addi s0,sp,384 - 6b0a: a404 fsd fs1,8(s0) - 6b0c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6b10: 0020 addi s0,sp,8 - 6b12: 0001 nop - 6b14: 039d0403 lb s0,57(s10) - 6b18: 04090003 lb zero,64(s2) - 6b1c: 0100 addi s0,sp,128 - 6b1e: 0300 addi s0,sp,384 - 6b20: 9d04 0x9d04 - 6b22: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6b26: 0010 0x10 - 6b28: 0001 nop - 6b2a: 03a70403 lb s0,58(a4) - 6b2e: 08090003 lb zero,128(s2) - 6b32: 0100 addi s0,sp,128 - 6b34: 0300 addi s0,sp,384 - 6b36: a704 fsd fs1,8(a4) - 6b38: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6b3c: 0000 unimp - 6b3e: 0001 nop - 6b40: 03a70403 lb s0,58(a4) - 6b44: 00090003 lb zero,0(s2) - 6b48: 0100 addi s0,sp,128 - 6b4a: 0300 addi s0,sp,384 - 6b4c: a704 fsd fs1,8(a4) - 6b4e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6b52: 0000 unimp - 6b54: 0001 nop - 6b56: 03a70403 lb s0,58(a4) - 6b5a: 00090003 lb zero,0(s2) - 6b5e: 0100 addi s0,sp,128 - 6b60: 0300 addi s0,sp,384 - 6b62: a704 fsd fs1,8(a4) - 6b64: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6b68: 0000 unimp - 6b6a: 0001 nop - 6b6c: 03a70403 lb s0,58(a4) - 6b70: 00090003 lb zero,0(s2) - 6b74: 0100 addi s0,sp,128 - 6b76: 0300 addi s0,sp,384 - 6b78: a704 fsd fs1,8(a4) - 6b7a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6b7e: 0008 0x8 - 6b80: 0001 nop - 6b82: 03a70403 lb s0,58(a4) - 6b86: 08090003 lb zero,128(s2) - 6b8a: 0100 addi s0,sp,128 - 6b8c: 0300 addi s0,sp,384 - 6b8e: a704 fsd fs1,8(a4) - 6b90: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6b94: 0000 unimp - 6b96: 0001 nop - 6b98: 03a90403 lb s0,58(s2) - 6b9c: 0306 slli t1,t1,0x1 - 6b9e: 0900 addi s0,sp,144 - 6ba0: 0004 0x4 - 6ba2: 0001 nop - 6ba4: 03ac0403 lb s0,58(s8) - 6ba8: 0306 slli t1,t1,0x1 - 6baa: 0900 addi s0,sp,144 - 6bac: 0010 0x10 - 6bae: 0601 addi a2,a2,0 - 6bb0: 08090003 lb zero,128(s2) - 6bb4: 0100 addi s0,sp,128 - 6bb6: 0300 addi s0,sp,384 - 6bb8: b104 fsd fs1,32(a0) - 6bba: 00030603 lb a2,0(t1) - 6bbe: 0809 addi a6,a6,2 - 6bc0: 0100 addi s0,sp,128 - 6bc2: 0300 addi s0,sp,384 - 6bc4: b704 fsd fs1,40(a4) - 6bc6: 00030603 lb a2,0(t1) - 6bca: 1809 addi a6,a6,-30 - 6bcc: 0100 addi s0,sp,128 - 6bce: 08090003 lb zero,128(s2) - 6bd2: 0100 addi s0,sp,128 - 6bd4: 0300 addi s0,sp,384 - 6bd6: ab04 fsd fs1,16(a4) - 6bd8: 00030603 lb a2,0(t1) - 6bdc: 0809 addi a6,a6,2 - 6bde: 0100 addi s0,sp,128 - 6be0: 0300 addi s0,sp,384 - 6be2: ae04 fsd fs1,24(a2) - 6be4: 00030603 lb a2,0(t1) - 6be8: 1809 addi a6,a6,-30 - 6bea: 0100 addi s0,sp,128 - 6bec: 0300 addi s0,sp,384 - 6bee: ae04 fsd fs1,24(a2) - 6bf0: 00030603 lb a2,0(t1) - 6bf4: 1809 addi a6,a6,-30 - 6bf6: 0100 addi s0,sp,128 - 6bf8: 0300 addi s0,sp,384 - 6bfa: ae04 fsd fs1,24(a2) - 6bfc: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6c00: 0008 0x8 - 6c02: 0001 nop - 6c04: 03b20403 lb s0,59(tp) # 3b <_start-0x7fffffc5> - 6c08: 0306 slli t1,t1,0x1 - 6c0a: 0900 addi s0,sp,144 - 6c0c: 0014 0x14 - 6c0e: 0001 nop - 6c10: 03b50403 lb s0,59(a0) - 6c14: 0306 slli t1,t1,0x1 - 6c16: 0900 addi s0,sp,144 - 6c18: 0004 0x4 - 6c1a: 0001 nop - 6c1c: 03b40403 lb s0,59(s0) - 6c20: 24090003 lb zero,576(s2) - 6c24: 0100 addi s0,sp,128 - 6c26: 0300 addi s0,sp,384 - 6c28: b804 fsd fs1,48(s0) - 6c2a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6c2e: 0028 addi a0,sp,8 - 6c30: 0001 nop - 6c32: 03b70403 lb s0,59(a4) - 6c36: 0306 slli t1,t1,0x1 - 6c38: 0900 addi s0,sp,144 - 6c3a: 0010 0x10 - 6c3c: 0001 nop - 6c3e: 03b90403 lb s0,59(s2) - 6c42: 0306 slli t1,t1,0x1 - 6c44: 0900 addi s0,sp,144 - 6c46: 0004 0x4 - 6c48: 0001 nop - 6c4a: 03b90403 lb s0,59(s2) - 6c4e: 00090003 lb zero,0(s2) - 6c52: 0100 addi s0,sp,128 - 6c54: 0300 addi s0,sp,384 - 6c56: bd04 fsd fs1,56(a0) - 6c58: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6c5c: 0010 0x10 - 6c5e: 0001 nop - 6c60: 03bd0403 lb s0,59(s10) - 6c64: 00090003 lb zero,0(s2) - 6c68: 0100 addi s0,sp,128 - 6c6a: 0300 addi s0,sp,384 - 6c6c: bd04 fsd fs1,56(a0) - 6c6e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6c72: 0000 unimp - 6c74: 0001 nop - 6c76: 03bd0403 lb s0,59(s10) - 6c7a: 00090003 lb zero,0(s2) - 6c7e: 0100 addi s0,sp,128 - 6c80: 0300 addi s0,sp,384 - 6c82: bd04 fsd fs1,56(a0) - 6c84: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6c88: 002c addi a1,sp,8 - 6c8a: 0001 nop - 6c8c: 03bd0403 lb s0,59(s10) - 6c90: 00090003 lb zero,0(s2) - 6c94: 0100 addi s0,sp,128 - 6c96: 0300 addi s0,sp,384 - 6c98: bd04 fsd fs1,56(a0) - 6c9a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6c9e: 0000 unimp - 6ca0: 0001 nop - 6ca2: 03bd0403 lb s0,59(s10) - 6ca6: 00090003 lb zero,0(s2) - 6caa: 0100 addi s0,sp,128 - 6cac: 0300 addi s0,sp,384 - 6cae: bd04 fsd fs1,56(a0) - 6cb0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6cb4: 0000 unimp - 6cb6: 0001 nop - 6cb8: 03be0403 lb s0,59(t3) - 6cbc: 0306 slli t1,t1,0x1 - 6cbe: 0900 addi s0,sp,144 - 6cc0: 0008 0x8 - 6cc2: 0001 nop - 6cc4: 03c30403 lb s0,60(t1) - 6cc8: 04090003 lb zero,64(s2) - 6ccc: 0100 addi s0,sp,128 - 6cce: 0300 addi s0,sp,384 - 6cd0: c304 sw s1,0(a4) - 6cd2: 00030603 lb a2,0(t1) - 6cd6: 0409 addi s0,s0,2 - 6cd8: 0100 addi s0,sp,128 - 6cda: 0300 addi s0,sp,384 - 6cdc: c304 sw s1,0(a4) - 6cde: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6ce2: 000c 0xc - 6ce4: 0001 nop - 6ce6: 03c30403 lb s0,60(t1) - 6cea: 0c090003 lb zero,192(s2) - 6cee: 0100 addi s0,sp,128 - 6cf0: 0300 addi s0,sp,384 - 6cf2: c304 sw s1,0(a4) - 6cf4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6cf8: 0000 unimp - 6cfa: 0001 nop - 6cfc: 03c40403 lb s0,60(s0) - 6d00: 0306 slli t1,t1,0x1 - 6d02: 0900 addi s0,sp,144 - 6d04: 0008 0x8 - 6d06: 0001 nop - 6d08: 03c90403 lb s0,60(s2) - 6d0c: 0306 slli t1,t1,0x1 - 6d0e: 0900 addi s0,sp,144 - 6d10: 0004 0x4 - 6d12: 0001 nop - 6d14: 03c90403 lb s0,60(s2) - 6d18: 0306 slli t1,t1,0x1 - 6d1a: 097f 0x97f - 6d1c: 000c 0xc - 6d1e: 0001 nop - 6d20: 03c90403 lb s0,60(s2) - 6d24: 04090103 lb sp,64(s2) - 6d28: 0100 addi s0,sp,128 - 6d2a: 0300 addi s0,sp,384 - 6d2c: f504 fsw fs1,40(a0) - 6d2e: 0602 c.slli64 a2 - 6d30: 14090003 lb zero,320(s2) - 6d34: 0100 addi s0,sp,128 - 6d36: 0300 addi s0,sp,384 - 6d38: cb04 sw s1,16(a4) - 6d3a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6d3e: 002c addi a1,sp,8 - 6d40: 0001 nop - 6d42: 03cd0403 lb s0,60(s10) - 6d46: 1c090003 lb zero,448(s2) - 6d4a: 0100 addi s0,sp,128 - 6d4c: 0300 addi s0,sp,384 - 6d4e: cd04 sw s1,24(a0) - 6d50: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6d54: 0000 unimp - 6d56: 0001 nop - 6d58: 03cf0403 lb s0,60(t5) # 2224c <_start-0x7ffdddb4> - 6d5c: 04090003 lb zero,64(s2) - 6d60: 0100 addi s0,sp,128 - 6d62: 0300 addi s0,sp,384 - 6d64: cf04 sw s1,24(a4) - 6d66: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6d6a: 0010 0x10 - 6d6c: 0601 addi a2,a2,0 - 6d6e: 08090003 lb zero,128(s2) - 6d72: 0100 addi s0,sp,128 - 6d74: 0300 addi s0,sp,384 - 6d76: d004 sw s1,32(s0) - 6d78: 00030603 lb a2,0(t1) - 6d7c: 0c09 addi s8,s8,2 - 6d7e: 0100 addi s0,sp,128 - 6d80: 0300 addi s0,sp,384 - 6d82: d604 sw s1,40(a2) - 6d84: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6d88: 0004 0x4 - 6d8a: 0001 nop - 6d8c: 03d60403 lb s0,61(a2) - 6d90: 00090003 lb zero,0(s2) - 6d94: 0100 addi s0,sp,128 - 6d96: 0300 addi s0,sp,384 - 6d98: d604 sw s1,40(a2) - 6d9a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6d9e: 0010 0x10 - 6da0: 0001 nop - 6da2: 03d60403 lb s0,61(a2) - 6da6: 00090003 lb zero,0(s2) - 6daa: 0100 addi s0,sp,128 - 6dac: 0300 addi s0,sp,384 - 6dae: d704 sw s1,40(a4) - 6db0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6db4: 0004 0x4 - 6db6: 0001 nop - 6db8: 03d70403 lb s0,61(a4) - 6dbc: 00090003 lb zero,0(s2) - 6dc0: 0100 addi s0,sp,128 - 6dc2: 0300 addi s0,sp,384 - 6dc4: d704 sw s1,40(a4) - 6dc6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6dca: 0000 unimp - 6dcc: 0001 nop - 6dce: 03d70403 lb s0,61(a4) - 6dd2: 00090003 lb zero,0(s2) - 6dd6: 0100 addi s0,sp,128 - 6dd8: 0300 addi s0,sp,384 - 6dda: d704 sw s1,40(a4) - 6ddc: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6de0: 0000 unimp - 6de2: 0001 nop - 6de4: 03d70403 lb s0,61(a4) - 6de8: 18090003 lb zero,384(s2) - 6dec: 0100 addi s0,sp,128 - 6dee: 0300 addi s0,sp,384 - 6df0: d704 sw s1,40(a4) - 6df2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6df6: 0000 unimp - 6df8: 0001 nop - 6dfa: 03d70403 lb s0,61(a4) - 6dfe: 00090003 lb zero,0(s2) - 6e02: 0100 addi s0,sp,128 - 6e04: 0300 addi s0,sp,384 - 6e06: d704 sw s1,40(a4) - 6e08: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6e0c: 0000 unimp - 6e0e: 0001 nop - 6e10: 03d70403 lb s0,61(a4) - 6e14: 04090003 lb zero,64(s2) - 6e18: 0100 addi s0,sp,128 - 6e1a: 0300 addi s0,sp,384 - 6e1c: d904 sw s1,48(a0) - 6e1e: 00030603 lb a2,0(t1) - 6e22: 0809 addi a6,a6,2 - 6e24: 0100 addi s0,sp,128 - 6e26: 0300 addi s0,sp,384 - 6e28: de04 sw s1,56(a2) - 6e2a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6e2e: 0008 0x8 - 6e30: 0001 nop - 6e32: 03de0403 lb s0,61(t3) - 6e36: 0306 slli t1,t1,0x1 - 6e38: 0900 addi s0,sp,144 - 6e3a: 0008 0x8 - 6e3c: 0001 nop - 6e3e: 03de0403 lb s0,61(t3) - 6e42: 00090003 lb zero,0(s2) - 6e46: 0100 addi s0,sp,128 - 6e48: 0300 addi s0,sp,384 - 6e4a: de04 sw s1,56(a2) - 6e4c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6e50: 000c 0xc - 6e52: 0001 nop - 6e54: 03de0403 lb s0,61(t3) - 6e58: 00090003 lb zero,0(s2) - 6e5c: 0100 addi s0,sp,128 - 6e5e: 0300 addi s0,sp,384 - 6e60: df04 sw s1,56(a4) - 6e62: 00030603 lb a2,0(t1) - 6e66: 0809 addi a6,a6,2 - 6e68: 0100 addi s0,sp,128 - 6e6a: 0300 addi s0,sp,384 - 6e6c: e404 fsw fs1,8(s0) - 6e6e: 00030603 lb a2,0(t1) - 6e72: 0409 addi s0,s0,2 - 6e74: 0100 addi s0,sp,128 - 6e76: 0300 addi s0,sp,384 - 6e78: e404 fsw fs1,8(s0) - 6e7a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6e7e: 0010 0x10 - 6e80: 0001 nop - 6e82: 03e40403 lb s0,62(s0) - 6e86: 00090003 lb zero,0(s2) - 6e8a: 0100 addi s0,sp,128 - 6e8c: 0300 addi s0,sp,384 - 6e8e: e504 fsw fs1,8(a0) - 6e90: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6e94: 0008 0x8 - 6e96: 0001 nop - 6e98: 03e50403 lb s0,62(a0) - 6e9c: 00090003 lb zero,0(s2) - 6ea0: 0100 addi s0,sp,128 - 6ea2: 0300 addi s0,sp,384 - 6ea4: e504 fsw fs1,8(a0) - 6ea6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6eaa: 0000 unimp - 6eac: 0001 nop - 6eae: 03e50403 lb s0,62(a0) - 6eb2: 00090003 lb zero,0(s2) - 6eb6: 0100 addi s0,sp,128 - 6eb8: 0300 addi s0,sp,384 - 6eba: e504 fsw fs1,8(a0) - 6ebc: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6ec0: 0018 0x18 - 6ec2: 0001 nop - 6ec4: 03e50403 lb s0,62(a0) - 6ec8: 00090003 lb zero,0(s2) - 6ecc: 0100 addi s0,sp,128 - 6ece: 0300 addi s0,sp,384 - 6ed0: e504 fsw fs1,8(a0) - 6ed2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6ed6: 0000 unimp - 6ed8: 0001 nop - 6eda: 03e50403 lb s0,62(a0) - 6ede: 04090003 lb zero,64(s2) - 6ee2: 0100 addi s0,sp,128 - 6ee4: 0300 addi s0,sp,384 - 6ee6: e504 fsw fs1,8(a0) - 6ee8: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6eec: 0000 unimp - 6eee: 0001 nop - 6ef0: 03e70403 lb s0,62(a4) - 6ef4: 0306 slli t1,t1,0x1 - 6ef6: 0900 addi s0,sp,144 - 6ef8: 0008 0x8 - 6efa: 0001 nop - 6efc: 03ec0403 lb s0,62(s8) - 6f00: 04090003 lb zero,64(s2) - 6f04: 0100 addi s0,sp,128 - 6f06: 0300 addi s0,sp,384 - 6f08: ec04 fsw fs1,24(s0) - 6f0a: 00030603 lb a2,0(t1) - 6f0e: 0409 addi s0,s0,2 - 6f10: 0100 addi s0,sp,128 - 6f12: 0300 addi s0,sp,384 - 6f14: ec04 fsw fs1,24(s0) - 6f16: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6f1a: 0004 0x4 - 6f1c: 0001 nop - 6f1e: 03ec0403 lb s0,62(s8) - 6f22: 04090003 lb zero,64(s2) - 6f26: 0100 addi s0,sp,128 - 6f28: 0300 addi s0,sp,384 - 6f2a: ec04 fsw fs1,24(s0) - 6f2c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6f30: 0008 0x8 - 6f32: 0001 nop - 6f34: 03ed0403 lb s0,62(s10) - 6f38: 0306 slli t1,t1,0x1 - 6f3a: 0900 addi s0,sp,144 - 6f3c: 0008 0x8 - 6f3e: 0001 nop - 6f40: 03f20403 lb s0,63(tp) # 3f <_start-0x7fffffc1> - 6f44: 0306 slli t1,t1,0x1 - 6f46: 0900 addi s0,sp,144 - 6f48: 0004 0x4 - 6f4a: 0001 nop - 6f4c: 03e60403 lb s0,62(a2) - 6f50: 14090003 lb zero,320(s2) - 6f54: 0100 addi s0,sp,128 - 6f56: 0300 addi s0,sp,384 - 6f58: 8504 0x8504 - 6f5a: 0304 addi s1,sp,384 - 6f5c: 0900 addi s0,sp,144 - 6f5e: 0010 0x10 - 6f60: 0001 nop - 6f62: 04850403 lb s0,72(a0) - 6f66: 00090003 lb zero,0(s2) - 6f6a: 0100 addi s0,sp,128 - 6f6c: 0300 addi s0,sp,384 - 6f6e: 8504 0x8504 - 6f70: 0304 addi s1,sp,384 - 6f72: 0900 addi s0,sp,144 - 6f74: 0000 unimp - 6f76: 0001 nop - 6f78: 04850403 lb s0,72(a0) - 6f7c: 00090003 lb zero,0(s2) - 6f80: 0100 addi s0,sp,128 - 6f82: 0300 addi s0,sp,384 - 6f84: 8504 0x8504 - 6f86: 0304 addi s1,sp,384 - 6f88: 0900 addi s0,sp,144 - 6f8a: 0000 unimp - 6f8c: 0001 nop - 6f8e: 04850403 lb s0,72(a0) - 6f92: 00090003 lb zero,0(s2) - 6f96: 0100 addi s0,sp,128 - 6f98: 0300 addi s0,sp,384 - 6f9a: 8604 0x8604 - 6f9c: 0304 addi s1,sp,384 - 6f9e: 0900 addi s0,sp,144 - 6fa0: 0008 0x8 - 6fa2: 0001 nop - 6fa4: 04880403 lb s0,72(a6) - 6fa8: 04090003 lb zero,64(s2) - 6fac: 0100 addi s0,sp,128 - 6fae: 0300 addi s0,sp,384 - 6fb0: 8804 0x8804 - 6fb2: 0304 addi s1,sp,384 - 6fb4: 0900 addi s0,sp,144 - 6fb6: 0000 unimp - 6fb8: 0001 nop - 6fba: 04880403 lb s0,72(a6) - 6fbe: 10090003 lb zero,256(s2) - 6fc2: 0100 addi s0,sp,128 - 6fc4: 0300 addi s0,sp,384 - 6fc6: 8804 0x8804 - 6fc8: 0304 addi s1,sp,384 - 6fca: 0900 addi s0,sp,144 - 6fcc: 0000 unimp - 6fce: 0001 nop - 6fd0: 04880403 lb s0,72(a6) - 6fd4: 00090003 lb zero,0(s2) - 6fd8: 0100 addi s0,sp,128 - 6fda: 0300 addi s0,sp,384 - 6fdc: 8804 0x8804 - 6fde: 0304 addi s1,sp,384 - 6fe0: 0900 addi s0,sp,144 - 6fe2: 0000 unimp - 6fe4: 0001 nop - 6fe6: 04880403 lb s0,72(a6) - 6fea: 00090003 lb zero,0(s2) - 6fee: 0100 addi s0,sp,128 - 6ff0: 0300 addi s0,sp,384 - 6ff2: 8804 0x8804 - 6ff4: 0304 addi s1,sp,384 - 6ff6: 0900 addi s0,sp,144 - 6ff8: 0000 unimp - 6ffa: 0001 nop - 6ffc: 04880403 lb s0,72(a6) - 7000: 00090003 lb zero,0(s2) - 7004: 0100 addi s0,sp,128 - 7006: 0300 addi s0,sp,384 - 7008: 8804 0x8804 - 700a: 0304 addi s1,sp,384 - 700c: 0900 addi s0,sp,144 - 700e: 0000 unimp - 7010: 0001 nop - 7012: 04910403 lb s0,73(sp) - 7016: 04090003 lb zero,64(s2) - 701a: 0100 addi s0,sp,128 - 701c: 0300 addi s0,sp,384 - 701e: 8904 0x8904 - 7020: 0304 addi s1,sp,384 - 7022: 0900 addi s0,sp,144 - 7024: 0024 addi s1,sp,8 - 7026: 0001 nop - 7028: 04890403 lb s0,72(s2) - 702c: 00090003 lb zero,0(s2) - 7030: 0100 addi s0,sp,128 - 7032: 0300 addi s0,sp,384 - 7034: 9704 0x9704 - 7036: 0604 addi s1,sp,768 - 7038: 14090003 lb zero,320(s2) - 703c: 0100 addi s0,sp,128 - 703e: 0300 addi s0,sp,384 - 7040: 8704 0x8704 - 7042: 0604 addi s1,sp,768 - 7044: 08090003 lb zero,128(s2) - 7048: 0100 addi s0,sp,128 - 704a: 0300 addi s0,sp,384 - 704c: 9704 0x9704 - 704e: 0304 addi s1,sp,384 - 7050: 0900 addi s0,sp,144 - 7052: 0004 0x4 - 7054: 0001 nop - 7056: 04970403 lb s0,73(a4) - 705a: 00090003 lb zero,0(s2) - 705e: 0100 addi s0,sp,128 - 7060: 0300 addi s0,sp,384 - 7062: af04 fsd fs1,24(a4) - 7064: 0304 addi s1,sp,384 - 7066: 0900 addi s0,sp,144 - 7068: 0014 0x14 - 706a: 0001 nop - 706c: 04af0403 lb s0,74(t5) - 7070: 00090003 lb zero,0(s2) - 7074: 0100 addi s0,sp,128 - 7076: 0300 addi s0,sp,384 - 7078: af04 fsd fs1,24(a4) - 707a: 0304 addi s1,sp,384 - 707c: 0900 addi s0,sp,144 - 707e: 0000 unimp - 7080: 0001 nop - 7082: 04af0403 lb s0,74(t5) - 7086: 00090003 lb zero,0(s2) - 708a: 0100 addi s0,sp,128 - 708c: 0300 addi s0,sp,384 - 708e: af04 fsd fs1,24(a4) - 7090: 0304 addi s1,sp,384 - 7092: 0900 addi s0,sp,144 - 7094: 0000 unimp - 7096: 0001 nop - 7098: 04af0403 lb s0,74(t5) - 709c: 10090003 lb zero,256(s2) - 70a0: 0100 addi s0,sp,128 - 70a2: 0300 addi s0,sp,384 - 70a4: af04 fsd fs1,24(a4) - 70a6: 0304 addi s1,sp,384 - 70a8: 0900 addi s0,sp,144 - 70aa: 0000 unimp - 70ac: 0001 nop - 70ae: 04af0403 lb s0,74(t5) - 70b2: 00090003 lb zero,0(s2) - 70b6: 0100 addi s0,sp,128 - 70b8: 0300 addi s0,sp,384 - 70ba: af04 fsd fs1,24(a4) - 70bc: 0304 addi s1,sp,384 - 70be: 0900 addi s0,sp,144 - 70c0: 0000 unimp - 70c2: 0001 nop - 70c4: 04af0403 lb s0,74(t5) - 70c8: 00090003 lb zero,0(s2) - 70cc: 0100 addi s0,sp,128 - 70ce: 0300 addi s0,sp,384 - 70d0: af04 fsd fs1,24(a4) - 70d2: 0304 addi s1,sp,384 - 70d4: 0900 addi s0,sp,144 - 70d6: 0000 unimp - 70d8: 0001 nop - 70da: 04af0403 lb s0,74(t5) - 70de: 00090003 lb zero,0(s2) - 70e2: 0100 addi s0,sp,128 - 70e4: 0300 addi s0,sp,384 - 70e6: af04 fsd fs1,24(a4) - 70e8: 0304 addi s1,sp,384 - 70ea: 0900 addi s0,sp,144 - 70ec: 0000 unimp - 70ee: 0001 nop - 70f0: 04af0403 lb s0,74(t5) - 70f4: 00090003 lb zero,0(s2) - 70f8: 0100 addi s0,sp,128 - 70fa: 0300 addi s0,sp,384 - 70fc: bb04 fsd fs1,48(a4) - 70fe: 0304 addi s1,sp,384 - 7100: 0900 addi s0,sp,144 - 7102: 0004 0x4 - 7104: 0001 nop - 7106: 03cc0403 lb s0,60(s8) - 710a: 24090003 lb zero,576(s2) - 710e: 0100 addi s0,sp,128 - 7110: 0300 addi s0,sp,384 - 7112: cc04 sw s1,24(s0) - 7114: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7118: 0000 unimp - 711a: 0001 nop - 711c: 03cc0403 lb s0,60(s8) - 7120: 00090003 lb zero,0(s2) - 7124: 0100 addi s0,sp,128 - 7126: 0300 addi s0,sp,384 - 7128: cc04 sw s1,24(s0) - 712a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 712e: 0000 unimp - 7130: 0001 nop - 7132: 03cc0403 lb s0,60(s8) - 7136: 00090003 lb zero,0(s2) - 713a: 0100 addi s0,sp,128 - 713c: 0300 addi s0,sp,384 - 713e: cc04 sw s1,24(s0) - 7140: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7144: 0018 0x18 - 7146: 0001 nop - 7148: 03cc0403 lb s0,60(s8) - 714c: 00090003 lb zero,0(s2) - 7150: 0100 addi s0,sp,128 - 7152: 0300 addi s0,sp,384 - 7154: cc04 sw s1,24(s0) - 7156: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 715a: 0000 unimp - 715c: 0001 nop - 715e: 03cc0403 lb s0,60(s8) - 7162: 00090003 lb zero,0(s2) - 7166: 0100 addi s0,sp,128 - 7168: 0300 addi s0,sp,384 - 716a: cc04 sw s1,24(s0) - 716c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7170: 0004 0x4 - 7172: 0001 nop - 7174: 04c20403 lb s0,76(tp) # 4c <_start-0x7fffffb4> - 7178: 0306 slli t1,t1,0x1 - 717a: 0900 addi s0,sp,144 - 717c: 0008 0x8 - 717e: 0001 nop - 7180: 04c70403 lb s0,76(a4) - 7184: 08090003 lb zero,128(s2) - 7188: 0100 addi s0,sp,128 - 718a: 0300 addi s0,sp,384 - 718c: c704 sw s1,8(a4) - 718e: 0604 addi s1,sp,768 - 7190: 08090003 lb zero,128(s2) - 7194: 0100 addi s0,sp,128 - 7196: 0300 addi s0,sp,384 - 7198: c704 sw s1,8(a4) - 719a: 0304 addi s1,sp,384 - 719c: 0900 addi s0,sp,144 - 719e: 0000 unimp - 71a0: 0001 nop - 71a2: 04c70403 lb s0,76(a4) - 71a6: 0c090003 lb zero,192(s2) - 71aa: 0100 addi s0,sp,128 - 71ac: 0300 addi s0,sp,384 - 71ae: c704 sw s1,8(a4) - 71b0: 0304 addi s1,sp,384 - 71b2: 0900 addi s0,sp,144 - 71b4: 0000 unimp - 71b6: 0001 nop - 71b8: 04c80403 lb s0,76(a6) - 71bc: 0306 slli t1,t1,0x1 - 71be: 0900 addi s0,sp,144 - 71c0: 0008 0x8 - 71c2: 0001 nop - 71c4: 04cd0403 lb s0,76(s10) - 71c8: 0306 slli t1,t1,0x1 - 71ca: 0900 addi s0,sp,144 - 71cc: 0004 0x4 - 71ce: 0001 nop - 71d0: 04cd0403 lb s0,76(s10) - 71d4: 10090003 lb zero,256(s2) - 71d8: 0100 addi s0,sp,128 - 71da: 0300 addi s0,sp,384 - 71dc: cd04 sw s1,24(a0) - 71de: 0304 addi s1,sp,384 - 71e0: 0900 addi s0,sp,144 - 71e2: 0000 unimp - 71e4: 0001 nop - 71e6: 04ce0403 lb s0,76(t3) - 71ea: 08090003 lb zero,128(s2) - 71ee: 0100 addi s0,sp,128 - 71f0: 0300 addi s0,sp,384 - 71f2: ce04 sw s1,24(a2) - 71f4: 0304 addi s1,sp,384 - 71f6: 0900 addi s0,sp,144 - 71f8: 0000 unimp - 71fa: 0001 nop - 71fc: 04ce0403 lb s0,76(t3) - 7200: 00090003 lb zero,0(s2) - 7204: 0100 addi s0,sp,128 - 7206: 0300 addi s0,sp,384 - 7208: ce04 sw s1,24(a2) - 720a: 0304 addi s1,sp,384 - 720c: 0900 addi s0,sp,144 - 720e: 0000 unimp - 7210: 0001 nop - 7212: 04ce0403 lb s0,76(t3) - 7216: 18090003 lb zero,384(s2) - 721a: 0100 addi s0,sp,128 - 721c: 0300 addi s0,sp,384 - 721e: ce04 sw s1,24(a2) - 7220: 0304 addi s1,sp,384 - 7222: 0900 addi s0,sp,144 - 7224: 0000 unimp - 7226: 0001 nop - 7228: 04ce0403 lb s0,76(t3) - 722c: 00090003 lb zero,0(s2) - 7230: 0100 addi s0,sp,128 - 7232: 0300 addi s0,sp,384 - 7234: ce04 sw s1,24(a2) - 7236: 0304 addi s1,sp,384 - 7238: 0900 addi s0,sp,144 - 723a: 0004 0x4 - 723c: 0001 nop - 723e: 04ce0403 lb s0,76(t3) - 7242: 00090003 lb zero,0(s2) - 7246: 0100 addi s0,sp,128 - 7248: 0300 addi s0,sp,384 - 724a: d004 sw s1,32(s0) - 724c: 0604 addi s1,sp,768 - 724e: 08090003 lb zero,128(s2) - 7252: 0100 addi s0,sp,128 - 7254: 0300 addi s0,sp,384 - 7256: d504 sw s1,40(a0) - 7258: 0304 addi s1,sp,384 - 725a: 0900 addi s0,sp,144 - 725c: 0004 0x4 - 725e: 0001 nop - 7260: 04d50403 lb s0,77(a0) - 7264: 0306 slli t1,t1,0x1 - 7266: 0900 addi s0,sp,144 - 7268: 0008 0x8 - 726a: 0001 nop - 726c: 04d50403 lb s0,77(a0) - 7270: 00090003 lb zero,0(s2) - 7274: 0100 addi s0,sp,128 - 7276: 0300 addi s0,sp,384 - 7278: d504 sw s1,40(a0) - 727a: 0304 addi s1,sp,384 - 727c: 0900 addi s0,sp,144 - 727e: 0004 0x4 - 7280: 0001 nop - 7282: 04d50403 lb s0,77(a0) - 7286: 08090003 lb zero,128(s2) - 728a: 0100 addi s0,sp,128 - 728c: 0300 addi s0,sp,384 - 728e: d604 sw s1,40(a2) - 7290: 0604 addi s1,sp,768 - 7292: 04090003 lb zero,64(s2) - 7296: 0100 addi s0,sp,128 - 7298: 0300 addi s0,sp,384 - 729a: db04 sw s1,48(a4) - 729c: 0604 addi s1,sp,768 - 729e: 04090003 lb zero,64(s2) - 72a2: 0100 addi s0,sp,128 - 72a4: 0300 addi s0,sp,384 - 72a6: db04 sw s1,48(a4) - 72a8: 0304 addi s1,sp,384 - 72aa: 0900 addi s0,sp,144 - 72ac: 0010 0x10 - 72ae: 0001 nop - 72b0: 04e30403 lb s0,78(t1) - 72b4: 04090003 lb zero,64(s2) - 72b8: 0100 addi s0,sp,128 - 72ba: 0300 addi s0,sp,384 - 72bc: e304 fsw fs1,0(a4) - 72be: 0304 addi s1,sp,384 - 72c0: 0900 addi s0,sp,144 - 72c2: 0000 unimp - 72c4: 0001 nop - 72c6: 04e60403 lb s0,78(a2) - 72ca: 08090003 lb zero,128(s2) - 72ce: 0100 addi s0,sp,128 - 72d0: 0300 addi s0,sp,384 - 72d2: e604 fsw fs1,8(a2) - 72d4: 0304 addi s1,sp,384 - 72d6: 0900 addi s0,sp,144 - 72d8: 0000 unimp - 72da: 0001 nop - 72dc: 04e60403 lb s0,78(a2) - 72e0: 00090003 lb zero,0(s2) - 72e4: 0100 addi s0,sp,128 - 72e6: 0300 addi s0,sp,384 - 72e8: e604 fsw fs1,8(a2) - 72ea: 0304 addi s1,sp,384 - 72ec: 0900 addi s0,sp,144 - 72ee: 0000 unimp - 72f0: 0001 nop - 72f2: 05850403 lb s0,88(a0) - 72f6: 04090003 lb zero,64(s2) - 72fa: 0100 addi s0,sp,128 - 72fc: 0300 addi s0,sp,384 - 72fe: 8504 0x8504 - 7300: 0305 addi t1,t1,1 - 7302: 0900 addi s0,sp,144 - 7304: 0004 0x4 - 7306: 0001 nop - 7308: 05850403 lb s0,88(a0) - 730c: 00090003 lb zero,0(s2) - 7310: 0100 addi s0,sp,128 - 7312: 0300 addi s0,sp,384 - 7314: 8504 0x8504 - 7316: 0305 addi t1,t1,1 - 7318: 0900 addi s0,sp,144 - 731a: 0000 unimp - 731c: 0001 nop - 731e: 05850403 lb s0,88(a0) - 7322: 00090003 lb zero,0(s2) - 7326: 0100 addi s0,sp,128 - 7328: 0300 addi s0,sp,384 - 732a: 8504 0x8504 - 732c: 0305 addi t1,t1,1 - 732e: 0900 addi s0,sp,144 - 7330: 000c 0xc - 7332: 0001 nop - 7334: 05850403 lb s0,88(a0) - 7338: 00090003 lb zero,0(s2) - 733c: 0100 addi s0,sp,128 - 733e: 0300 addi s0,sp,384 - 7340: 8504 0x8504 - 7342: 0305 addi t1,t1,1 - 7344: 0900 addi s0,sp,144 - 7346: 0000 unimp - 7348: 0601 addi a2,a2,0 - 734a: 10090003 lb zero,256(s2) - 734e: 0100 addi s0,sp,128 - 7350: 0300 addi s0,sp,384 - 7352: 8b04 0x8b04 - 7354: 0305 addi t1,t1,1 - 7356: 0900 addi s0,sp,144 - 7358: 0010 0x10 - 735a: 0001 nop - 735c: 058e0403 lb s0,88(t3) - 7360: 04090003 lb zero,64(s2) - 7364: 0100 addi s0,sp,128 - 7366: 0300 addi s0,sp,384 - 7368: 8e04 0x8e04 - 736a: 0605 addi a2,a2,1 - 736c: 10090003 lb zero,256(s2) - 7370: 0100 addi s0,sp,128 - 7372: 0300 addi s0,sp,384 - 7374: 9004 0x9004 - 7376: 0605 addi a2,a2,1 - 7378: 08090003 lb zero,128(s2) - 737c: 0100 addi s0,sp,128 - 737e: 0300 addi s0,sp,384 - 7380: cf04 sw s1,24(a4) - 7382: 0604 addi s1,sp,768 - 7384: 08090003 lb zero,128(s2) - 7388: 0100 addi s0,sp,128 - 738a: 0300 addi s0,sp,384 - 738c: e504 fsw fs1,8(a0) - 738e: 0304 addi s1,sp,384 - 7390: 0900 addi s0,sp,144 - 7392: 0014 0x14 - 7394: 0001 nop - 7396: 04ec0403 lb s0,78(s8) - 739a: 08090003 lb zero,128(s2) - 739e: 0100 addi s0,sp,128 - 73a0: 0300 addi s0,sp,384 - 73a2: ec04 fsw fs1,24(s0) - 73a4: 0304 addi s1,sp,384 - 73a6: 0900 addi s0,sp,144 - 73a8: 0000 unimp - 73aa: 0001 nop - 73ac: 04ec0403 lb s0,78(s8) - 73b0: 00090003 lb zero,0(s2) - 73b4: 0100 addi s0,sp,128 - 73b6: 0300 addi s0,sp,384 - 73b8: ec04 fsw fs1,24(s0) - 73ba: 0304 addi s1,sp,384 - 73bc: 0900 addi s0,sp,144 - 73be: 0000 unimp - 73c0: 0001 nop - 73c2: 04ec0403 lb s0,78(s8) - 73c6: 04090003 lb zero,64(s2) - 73ca: 0100 addi s0,sp,128 - 73cc: 0300 addi s0,sp,384 - 73ce: eb04 fsw fs1,16(a4) - 73d0: 0304 addi s1,sp,384 - 73d2: 0900 addi s0,sp,144 - 73d4: 0008 0x8 - 73d6: 0001 nop - 73d8: 04f60403 lb s0,79(a2) - 73dc: 08090003 lb zero,128(s2) - 73e0: 0100 addi s0,sp,128 - 73e2: 0300 addi s0,sp,384 - 73e4: f604 fsw fs1,40(a2) - 73e6: 0304 addi s1,sp,384 - 73e8: 0900 addi s0,sp,144 - 73ea: 0000 unimp - 73ec: 0001 nop - 73ee: 04f60403 lb s0,79(a2) - 73f2: 00090003 lb zero,0(s2) - 73f6: 0100 addi s0,sp,128 - 73f8: 0300 addi s0,sp,384 - 73fa: f604 fsw fs1,40(a2) - 73fc: 0304 addi s1,sp,384 - 73fe: 0900 addi s0,sp,144 - 7400: 0000 unimp - 7402: 0001 nop - 7404: 04f60403 lb s0,79(a2) - 7408: 04090003 lb zero,64(s2) - 740c: 0100 addi s0,sp,128 - 740e: 0300 addi s0,sp,384 - 7410: fe04 fsw fs1,56(a2) - 7412: 0304 addi s1,sp,384 - 7414: 0900 addi s0,sp,144 - 7416: 0008 0x8 - 7418: 0001 nop - 741a: 04fe0403 lb s0,79(t3) - 741e: 00090003 lb zero,0(s2) - 7422: 0100 addi s0,sp,128 - 7424: 0300 addi s0,sp,384 - 7426: fe04 fsw fs1,56(a2) - 7428: 0304 addi s1,sp,384 - 742a: 0900 addi s0,sp,144 - 742c: 0000 unimp - 742e: 0001 nop - 7430: 04fe0403 lb s0,79(t3) - 7434: 00090003 lb zero,0(s2) - 7438: 0100 addi s0,sp,128 - 743a: 0300 addi s0,sp,384 - 743c: fe04 fsw fs1,56(a2) - 743e: 0304 addi s1,sp,384 - 7440: 0900 addi s0,sp,144 - 7442: 0008 0x8 - 7444: 0601 addi a2,a2,0 - 7446: 14090003 lb zero,320(s2) - 744a: 0100 addi s0,sp,128 - 744c: 0300 addi s0,sp,384 - 744e: 8a04 0x8a04 - 7450: 0605 addi a2,a2,1 - 7452: 04090003 lb zero,64(s2) - 7456: 0100 addi s0,sp,128 - 7458: 0300 addi s0,sp,384 - 745a: 8d04 0x8d04 - 745c: 0305 addi t1,t1,1 - 745e: 0900 addi s0,sp,144 - 7460: 0020 addi s0,sp,8 - 7462: 0001 nop - 7464: 05910403 lb s0,89(sp) - 7468: 24090003 lb zero,576(s2) - 746c: 0100 addi s0,sp,128 - 746e: 0300 addi s0,sp,384 - 7470: 9004 0x9004 - 7472: 0605 addi a2,a2,1 - 7474: 14090003 lb zero,320(s2) - 7478: 0100 addi s0,sp,128 - 747a: 0300 addi s0,sp,384 - 747c: 9204 0x9204 - 747e: 0605 addi a2,a2,1 - 7480: 04090003 lb zero,64(s2) - 7484: 0100 addi s0,sp,128 - 7486: 0300 addi s0,sp,384 - 7488: 9304 0x9304 - 748a: 0305 addi t1,t1,1 - 748c: 0900 addi s0,sp,144 - 748e: 0004 0x4 - 7490: 0001 nop - 7492: 05930403 lb s0,89(t1) - 7496: 08090003 lb zero,128(s2) - 749a: 0100 addi s0,sp,128 - 749c: 0300 addi s0,sp,384 - 749e: 9304 0x9304 - 74a0: 0305 addi t1,t1,1 - 74a2: 0900 addi s0,sp,144 - 74a4: 0000 unimp - 74a6: 0001 nop - 74a8: 05930403 lb s0,89(t1) - 74ac: 00090003 lb zero,0(s2) - 74b0: 0100 addi s0,sp,128 - 74b2: 0300 addi s0,sp,384 - 74b4: 9304 0x9304 - 74b6: 0305 addi t1,t1,1 - 74b8: 0900 addi s0,sp,144 - 74ba: 0000 unimp - 74bc: 0001 nop - 74be: 05930403 lb s0,89(t1) - 74c2: 00090003 lb zero,0(s2) - 74c6: 0100 addi s0,sp,128 - 74c8: 0300 addi s0,sp,384 - 74ca: 9304 0x9304 - 74cc: 0305 addi t1,t1,1 - 74ce: 0900 addi s0,sp,144 - 74d0: 0000 unimp - 74d2: 0001 nop - 74d4: 05930403 lb s0,89(t1) - 74d8: 00090003 lb zero,0(s2) - 74dc: 0100 addi s0,sp,128 - 74de: 0300 addi s0,sp,384 - 74e0: 9304 0x9304 - 74e2: 0305 addi t1,t1,1 - 74e4: 0900 addi s0,sp,144 - 74e6: 0008 0x8 - 74e8: 0001 nop - 74ea: 05930403 lb s0,89(t1) - 74ee: 0c090003 lb zero,192(s2) - 74f2: 0100 addi s0,sp,128 - 74f4: 0300 addi s0,sp,384 - 74f6: 9304 0x9304 - 74f8: 0305 addi t1,t1,1 - 74fa: 0900 addi s0,sp,144 - 74fc: 0000 unimp - 74fe: 0001 nop - 7500: 05950403 lb s0,89(a0) - 7504: 0306 slli t1,t1,0x1 - 7506: 0900 addi s0,sp,144 - 7508: 0000 unimp - 750a: 0001 nop - 750c: 05980403 lb s0,89(a6) - 7510: 0306 slli t1,t1,0x1 - 7512: 0900 addi s0,sp,144 - 7514: 0010 0x10 - 7516: 0601 addi a2,a2,0 - 7518: 08090003 lb zero,128(s2) - 751c: 0100 addi s0,sp,128 - 751e: 0300 addi s0,sp,384 - 7520: 9d04 0x9d04 - 7522: 0605 addi a2,a2,1 - 7524: 0c090003 lb zero,192(s2) - 7528: 0100 addi s0,sp,128 - 752a: 0300 addi s0,sp,384 - 752c: a304 fsd fs1,0(a4) - 752e: 0605 addi a2,a2,1 - 7530: 18090003 lb zero,384(s2) - 7534: 0100 addi s0,sp,128 - 7536: 0300 addi s0,sp,384 - 7538: 9704 0x9704 - 753a: 0605 addi a2,a2,1 - 753c: 08090003 lb zero,128(s2) - 7540: 0100 addi s0,sp,128 - 7542: 0300 addi s0,sp,384 - 7544: 9a04 0x9a04 - 7546: 0605 addi a2,a2,1 - 7548: 1c090003 lb zero,448(s2) - 754c: 0100 addi s0,sp,128 - 754e: 0300 addi s0,sp,384 - 7550: 9a04 0x9a04 - 7552: 0605 addi a2,a2,1 - 7554: 18090003 lb zero,384(s2) - 7558: 0100 addi s0,sp,128 - 755a: 0300 addi s0,sp,384 - 755c: 9a04 0x9a04 - 755e: 0305 addi t1,t1,1 - 7560: 0900 addi s0,sp,144 - 7562: 0008 0x8 - 7564: 0001 nop - 7566: 059e0403 lb s0,89(t3) - 756a: 0306 slli t1,t1,0x1 - 756c: 0900 addi s0,sp,144 - 756e: 0018 0x18 - 7570: 0001 nop - 7572: 05a10403 lb s0,90(sp) - 7576: 0306 slli t1,t1,0x1 - 7578: 0900 addi s0,sp,144 - 757a: 0004 0x4 - 757c: 0001 nop - 757e: 05a00403 lb s0,90(zero) # 5a <_start-0x7fffffa6> - 7582: 24090003 lb zero,576(s2) - 7586: 0100 addi s0,sp,128 - 7588: 0300 addi s0,sp,384 - 758a: a404 fsd fs1,8(s0) - 758c: 0305 addi t1,t1,1 - 758e: 0900 addi s0,sp,144 - 7590: 002c addi a1,sp,8 - 7592: 0001 nop - 7594: 05a30403 lb s0,90(t1) - 7598: 0306 slli t1,t1,0x1 - 759a: 0900 addi s0,sp,144 - 759c: 0014 0x14 - 759e: 0001 nop - 75a0: 05a50403 lb s0,90(a0) - 75a4: 0306 slli t1,t1,0x1 - 75a6: 0900 addi s0,sp,144 - 75a8: 0004 0x4 - 75aa: 0001 nop - 75ac: 05a50403 lb s0,90(a0) - 75b0: 00090003 lb zero,0(s2) - 75b4: 0100 addi s0,sp,128 - 75b6: 0300 addi s0,sp,384 - 75b8: a504 fsd fs1,8(a0) - 75ba: 0305 addi t1,t1,1 - 75bc: 0900 addi s0,sp,144 - 75be: 0014 0x14 - 75c0: 0001 nop - 75c2: 05940403 lb s0,89(s0) - 75c6: 04090003 lb zero,64(s2) - 75ca: 0100 addi s0,sp,128 - 75cc: 0300 addi s0,sp,384 - 75ce: 9404 0x9404 - 75d0: 0305 addi t1,t1,1 - 75d2: 0900 addi s0,sp,144 - 75d4: 0010 0x10 - 75d6: 0001 nop - 75d8: 0402 c.slli64 s0 - 75da: 0352 slli t1,t1,0x14 - 75dc: 0901 addi s2,s2,0 - 75de: 0008 0x8 - 75e0: 0001 nop - 75e2: 0402 c.slli64 s0 - 75e4: 0352 slli t1,t1,0x14 - 75e6: 0900 addi s0,sp,144 - 75e8: 0000 unimp - 75ea: 0001 nop - 75ec: 0402 c.slli64 s0 - 75ee: 0352 slli t1,t1,0x14 - 75f0: 0900 addi s0,sp,144 - 75f2: 0000 unimp - 75f4: 0001 nop - 75f6: 0402 c.slli64 s0 - 75f8: 0352 slli t1,t1,0x14 - 75fa: 0900 addi s0,sp,144 - 75fc: 0000 unimp - 75fe: 0001 nop - 7600: 0402 c.slli64 s0 - 7602: 0352 slli t1,t1,0x14 - 7604: 0900 addi s0,sp,144 - 7606: 0010 0x10 - 7608: 0001 nop - 760a: 0402 c.slli64 s0 - 760c: 0352 slli t1,t1,0x14 - 760e: 0900 addi s0,sp,144 - 7610: 0000 unimp - 7612: 0901 addi s2,s2,0 - 7614: 0004 0x4 - 7616: 0100 addi s0,sp,128 - 7618: ad01 j 7c28 <_start-0x7fff83d8> - 761a: 0002 c.slli64 zero - 761c: 0300 addi s0,sp,384 - 761e: 9200 0x9200 - 7620: 0000 unimp - 7622: 0100 addi s0,sp,128 - 7624: fb01 bnez a4,7534 <_start-0x7fff8acc> - 7626: 0d0e slli s10,s10,0x3 - 7628: 0100 addi s0,sp,128 - 762a: 0101 addi sp,sp,0 - 762c: 0001 nop - 762e: 0000 unimp - 7630: 0001 nop - 7632: 0100 addi s0,sp,128 - 7634: 2e2e fld ft8,200(sp) - 7636: 2f2e2e2f 0x2f2e2e2f - 763a: 2e2e fld ft8,200(sp) - 763c: 2f2e2e2f 0x2f2e2e2f - 7640: 6972 flw fs2,28(sp) - 7642: 2d766373 csrrsi t1,0x2d7,12 - 7646: 2f636367 0x2f636367 - 764a: 696c flw fa1,84(a0) - 764c: 6762 flw fa4,24(sp) - 764e: 732f6363 bltu t5,s2,7d74 <_start-0x7fff828c> - 7652: 2d74666f jal a2,4e128 <_start-0x7ffb1ed8> - 7656: 7066 flw ft0,120(sp) - 7658: 2e00 fld fs0,24(a2) - 765a: 2f2e fld ft10,200(sp) - 765c: 2e2e fld ft8,200(sp) - 765e: 2f2e2e2f 0x2f2e2e2f - 7662: 2e2e fld ft8,200(sp) - 7664: 7369722f 0x7369722f - 7668: 672d7663 bgeu s10,s2,7cd4 <_start-0x7fff832c> - 766c: 6c2f6363 bltu t5,sp,7d32 <_start-0x7fff82ce> - 7670: 6269 lui tp,0x1a - 7672: 2f636367 0x2f636367 - 7676: 2e2e fld ft8,200(sp) - 7678: 636e692f vamoandw.v zero,v22,(t3),v18 - 767c: 756c flw fa1,108(a0) - 767e: 6564 flw fs1,76(a0) - 7680: 0000 unimp - 7682: 6966 flw fs2,88(sp) - 7684: 7478 flw fa4,108(s0) - 7686: 7366 flw ft6,120(sp) - 7688: 2e69 jal 7a22 <_start-0x7fff85de> - 768a: 00010063 beqz sp,768a <_start-0x7fff8976> - 768e: 7300 flw fs0,32(a4) - 7690: 2d74666f jal a2,4e166 <_start-0x7ffb1e9a> - 7694: 7066 flw ft0,120(sp) - 7696: 682e flw fa6,200(sp) - 7698: 0100 addi s0,sp,128 - 769a: 0000 unimp - 769c: 7571 lui a0,0xffffc - 769e: 6461 lui s0,0x18 - 76a0: 682e flw fa6,200(sp) - 76a2: 0100 addi s0,sp,128 - 76a4: 0000 unimp - 76a6: 6f6c flw fa1,92(a4) - 76a8: 676e flw fa4,216(sp) - 76aa: 6f6c flw fa1,92(a4) - 76ac: 676e flw fa4,216(sp) - 76ae: 682e flw fa6,200(sp) - 76b0: 0200 addi s0,sp,256 - 76b2: 0000 unimp - 76b4: 0500 addi s0,sp,640 - 76b6: 0001 nop - 76b8: 0205 addi tp,tp,1 - 76ba: 3ce4 fld fs1,248(s1) - 76bc: 8001 c.srli64 s0 - 76be: 05012303 lw t1,80(sp) - 76c2: 09010303 lb t1,144(sp) - 76c6: 0000 unimp - 76c8: 0301 addi t1,t1,0 - 76ca: 0900 addi s0,sp,144 - 76cc: 0000 unimp - 76ce: 0501 addi a0,a0,0 - 76d0: 030d addi t1,t1,3 - 76d2: 0900 addi s0,sp,144 - 76d4: 0000 unimp - 76d6: 0501 addi a0,a0,0 - 76d8: 09010303 lb t1,144(sp) - 76dc: 0000 unimp - 76de: 0301 addi t1,t1,0 - 76e0: 0900 addi s0,sp,144 - 76e2: 0000 unimp - 76e4: 0301 addi t1,t1,0 - 76e6: 0900 addi s0,sp,144 - 76e8: 0000 unimp - 76ea: 0301 addi t1,t1,0 - 76ec: 0900 addi s0,sp,144 - 76ee: 0000 unimp - 76f0: 0301 addi t1,t1,0 - 76f2: 0901 addi s2,s2,0 - 76f4: 0000 unimp - 76f6: 0301 addi t1,t1,0 - 76f8: 0902 c.slli64 s2 - 76fa: 0000 unimp - 76fc: 0301 addi t1,t1,0 - 76fe: 0901 addi s2,s2,0 - 7700: 0000 unimp - 7702: 0301 addi t1,t1,0 - 7704: 0900 addi s0,sp,144 - 7706: 0000 unimp - 7708: 0301 addi t1,t1,0 - 770a: 0900 addi s0,sp,144 - 770c: 0000 unimp - 770e: 0501 addi a0,a0,0 - 7710: 0601 addi a2,a2,0 - 7712: 00097a03 0x97a03 - 7716: 0100 addi s0,sp,128 - 7718: 0305 addi t1,t1,1 - 771a: 14090603 lb a2,320(s2) - 771e: 0100 addi s0,sp,128 - 7720: 0306 slli t1,t1,0x1 - 7722: 0900 addi s0,sp,144 - 7724: 0008 0x8 - 7726: 0601 addi a2,a2,0 - 7728: 10090103 lb sp,256(s2) - 772c: 0100 addi s0,sp,128 - 772e: 04097f03 0x4097f03 - 7732: 0100 addi s0,sp,128 - 7734: 0306 slli t1,t1,0x1 - 7736: 0900 addi s0,sp,144 - 7738: 0014 0x14 - 773a: 0301 addi t1,t1,0 - 773c: 0900 addi s0,sp,144 - 773e: 0000 unimp - 7740: 0301 addi t1,t1,0 - 7742: 0900 addi s0,sp,144 - 7744: 0000 unimp - 7746: 0301 addi t1,t1,0 - 7748: 0900 addi s0,sp,144 - 774a: 0000 unimp - 774c: 0301 addi t1,t1,0 - 774e: 0900 addi s0,sp,144 - 7750: 0000 unimp - 7752: 0301 addi t1,t1,0 - 7754: 0901 addi s2,s2,0 - 7756: 0000 unimp - 7758: 0301 addi t1,t1,0 - 775a: 0900 addi s0,sp,144 - 775c: 0000 unimp - 775e: 0001 nop - 7760: 0402 c.slli64 s0 - 7762: 030a slli t1,t1,0x2 - 7764: 0900 addi s0,sp,144 - 7766: 000c 0xc - 7768: 0001 nop - 776a: 0402 c.slli64 s0 - 776c: 030a slli t1,t1,0x2 - 776e: 0900 addi s0,sp,144 - 7770: 0000 unimp - 7772: 0001 nop - 7774: 0402 c.slli64 s0 - 7776: 030d addi t1,t1,3 - 7778: 0900 addi s0,sp,144 - 777a: 0008 0x8 - 777c: 0001 nop - 777e: 0402 c.slli64 s0 - 7780: 030d addi t1,t1,3 - 7782: 0900 addi s0,sp,144 - 7784: 0000 unimp - 7786: 0001 nop - 7788: 0402 c.slli64 s0 - 778a: 030d addi t1,t1,3 - 778c: 0900 addi s0,sp,144 - 778e: 0000 unimp - 7790: 0001 nop - 7792: 0402 c.slli64 s0 - 7794: 030d addi t1,t1,3 - 7796: 0900 addi s0,sp,144 - 7798: 0000 unimp - 779a: 0001 nop - 779c: 0402 c.slli64 s0 - 779e: 030d addi t1,t1,3 - 77a0: 0900 addi s0,sp,144 - 77a2: 000c 0xc - 77a4: 0301 addi t1,t1,0 - 77a6: 0901 addi s2,s2,0 - 77a8: 0000 unimp - 77aa: 0301 addi t1,t1,0 - 77ac: 0900 addi s0,sp,144 - 77ae: 0000 unimp - 77b0: 0301 addi t1,t1,0 - 77b2: 0902 c.slli64 s2 - 77b4: 0000 unimp - 77b6: 0501 addi a0,a0,0 - 77b8: 0601 addi a2,a2,0 - 77ba: 00090103 lb sp,0(s2) - 77be: 0100 addi s0,sp,128 - 77c0: 0305 addi t1,t1,1 - 77c2: 0200 addi s0,sp,256 - 77c4: 0c04 addi s1,sp,528 - 77c6: 08097c03 0x8097c03 - 77ca: 0100 addi s0,sp,128 - 77cc: 0200 addi s0,sp,256 - 77ce: 0c04 addi s1,sp,528 - 77d0: 0306 slli t1,t1,0x1 - 77d2: 0900 addi s0,sp,144 - 77d4: 0008 0x8 - 77d6: 0001 nop - 77d8: 0402 c.slli64 s0 - 77da: 030c addi a1,sp,384 - 77dc: 0900 addi s0,sp,144 - 77de: 0000 unimp - 77e0: 0001 nop - 77e2: 0402 c.slli64 s0 - 77e4: 030c addi a1,sp,384 - 77e6: 0900 addi s0,sp,144 - 77e8: 0014 0x14 - 77ea: 0001 nop - 77ec: 0402 c.slli64 s0 - 77ee: 030c addi a1,sp,384 - 77f0: 0900 addi s0,sp,144 - 77f2: 0000 unimp - 77f4: 0001 nop - 77f6: 0402 c.slli64 s0 - 77f8: 030c addi a1,sp,384 - 77fa: 0900 addi s0,sp,144 - 77fc: 0000 unimp - 77fe: 0001 nop - 7800: 0402 c.slli64 s0 - 7802: 030c addi a1,sp,384 - 7804: 0900 addi s0,sp,144 - 7806: 0000 unimp - 7808: 0001 nop - 780a: 0402 c.slli64 s0 - 780c: 030c addi a1,sp,384 - 780e: 0900 addi s0,sp,144 - 7810: 0000 unimp - 7812: 0001 nop - 7814: 0402 c.slli64 s0 - 7816: 030c addi a1,sp,384 - 7818: 0900 addi s0,sp,144 - 781a: 0000 unimp - 781c: 0001 nop - 781e: 0402 c.slli64 s0 - 7820: 030c addi a1,sp,384 - 7822: 0900 addi s0,sp,144 - 7824: 0000 unimp - 7826: 0001 nop - 7828: 0402 c.slli64 s0 - 782a: 030c addi a1,sp,384 - 782c: 0900 addi s0,sp,144 - 782e: 0004 0x4 - 7830: 0001 nop - 7832: 0402 c.slli64 s0 - 7834: 030c addi a1,sp,384 - 7836: 0900 addi s0,sp,144 - 7838: 0000 unimp - 783a: 0001 nop - 783c: 0402 c.slli64 s0 - 783e: 030c addi a1,sp,384 - 7840: 0900 addi s0,sp,144 - 7842: 0000 unimp - 7844: 0301 addi t1,t1,0 - 7846: 0900 addi s0,sp,144 - 7848: 0004 0x4 - 784a: 0001 nop - 784c: 0402 c.slli64 s0 - 784e: 0644 addi s1,sp,772 - 7850: 24090003 lb zero,576(s2) - 7854: 0100 addi s0,sp,128 - 7856: 0200 addi s0,sp,256 - 7858: 4404 lw s1,8(s0) - 785a: 0306 slli t1,t1,0x1 - 785c: 0900 addi s0,sp,144 - 785e: 0004 0x4 - 7860: 0001 nop - 7862: 0402 c.slli64 s0 - 7864: 0345 addi t1,t1,17 - 7866: 0900 addi s0,sp,144 - 7868: 0018 0x18 - 786a: 0001 nop - 786c: 0402 c.slli64 s0 - 786e: 0345 addi t1,t1,17 - 7870: 0900 addi s0,sp,144 - 7872: 0000 unimp - 7874: 0001 nop - 7876: 0402 c.slli64 s0 - 7878: 0345 addi t1,t1,17 - 787a: 0900 addi s0,sp,144 - 787c: 0000 unimp - 787e: 0001 nop - 7880: 0402 c.slli64 s0 - 7882: 0345 addi t1,t1,17 - 7884: 0900 addi s0,sp,144 - 7886: 0000 unimp - 7888: 0001 nop - 788a: 0402 c.slli64 s0 - 788c: 0345 addi t1,t1,17 - 788e: 0900 addi s0,sp,144 - 7890: 0004 0x4 - 7892: 0001 nop - 7894: 0402 c.slli64 s0 - 7896: 034d addi t1,t1,19 - 7898: 0900 addi s0,sp,144 - 789a: 0004 0x4 - 789c: 0001 nop - 789e: 0402 c.slli64 s0 - 78a0: 0340 addi s0,sp,388 - 78a2: 0900 addi s0,sp,144 - 78a4: 0008 0x8 - 78a6: 0001 nop - 78a8: 0402 c.slli64 s0 - 78aa: 063e slli a2,a2,0xf - 78ac: 1c090003 lb zero,448(s2) - 78b0: 0100 addi s0,sp,128 - 78b2: 0200 addi s0,sp,256 - 78b4: 4104 lw s1,0(a0) - 78b6: 0306 slli t1,t1,0x1 - 78b8: 0900 addi s0,sp,144 - 78ba: 0004 0x4 - 78bc: 0601 addi a2,a2,0 - 78be: 1c090003 lb zero,448(s2) - 78c2: 0100 addi s0,sp,128 - 78c4: 3409 jal 72c6 <_start-0x7fff8d3a> - 78c6: 0000 unimp - 78c8: 0101 addi sp,sp,0 - 78ca: 02cc addi a1,sp,324 - 78cc: 0000 unimp - 78ce: 00940003 lb zero,9(s0) # 18009 <_start-0x7ffe7ff7> - 78d2: 0000 unimp - 78d4: 0101 addi sp,sp,0 - 78d6: 000d0efb 0xd0efb - 78da: 0101 addi sp,sp,0 - 78dc: 0101 addi sp,sp,0 - 78de: 0000 unimp - 78e0: 0100 addi s0,sp,128 - 78e2: 0000 unimp - 78e4: 2e01 jal 7bf4 <_start-0x7fff840c> - 78e6: 2f2e fld ft10,200(sp) - 78e8: 2e2e fld ft8,200(sp) - 78ea: 2f2e2e2f 0x2f2e2e2f - 78ee: 2e2e fld ft8,200(sp) - 78f0: 7369722f 0x7369722f - 78f4: 672d7663 bgeu s10,s2,7f60 <_start-0x7fff80a0> - 78f8: 6c2f6363 bltu t5,sp,7fbe <_start-0x7fff8042> - 78fc: 6269 lui tp,0x1a - 78fe: 2f636367 0x2f636367 - 7902: 74666f73 csrrsi t5,0x746,12 - 7906: 662d lui a2,0xb - 7908: 0070 addi a2,sp,12 - 790a: 2e2e fld ft8,200(sp) - 790c: 2f2e2e2f 0x2f2e2e2f - 7910: 2e2e fld ft8,200(sp) - 7912: 2f2e2e2f 0x2f2e2e2f - 7916: 6972 flw fs2,28(sp) - 7918: 2d766373 csrrsi t1,0x2d7,12 - 791c: 2f636367 0x2f636367 - 7920: 696c flw fa1,84(a0) - 7922: 6762 flw fa4,24(sp) - 7924: 2e2f6363 bltu t5,sp,7c0a <_start-0x7fff83f6> - 7928: 2f2e fld ft10,200(sp) - 792a: 6e69 lui t3,0x1a - 792c: 64756c63 bltu a0,t2,7f84 <_start-0x7fff807c> - 7930: 0065 c.nop 25 - 7932: 6600 flw fs0,8(a2) - 7934: 6f6c flw fa1,92(a4) - 7936: 7461 lui s0,0xffff8 - 7938: 66746973 csrrsi s2,0x667,8 - 793c: 632e flw ft6,200(sp) - 793e: 0100 addi s0,sp,128 - 7940: 0000 unimp - 7942: 74666f73 csrrsi t5,0x746,12 - 7946: 662d lui a2,0xb - 7948: 2e70 fld fa2,216(a2) - 794a: 0068 addi a0,sp,12 - 794c: 0001 nop - 794e: 7100 flw fs0,32(a0) - 7950: 6175 addi sp,sp,368 - 7952: 2e64 fld fs1,216(a2) - 7954: 0068 addi a0,sp,12 - 7956: 0001 nop - 7958: 6c00 flw fs0,24(s0) - 795a: 6c676e6f jal t3,7e020 <_start-0x7ff81fe0> - 795e: 2e676e6f jal t3,7dc44 <_start-0x7ff823bc> - 7962: 0068 addi a0,sp,12 - 7964: 0002 c.slli64 zero - 7966: 0000 unimp - 7968: 0105 addi sp,sp,1 - 796a: 0500 addi s0,sp,640 - 796c: 3402 fld fs0,32(sp) - 796e: 013e slli sp,sp,0xf - 7970: 0380 addi s0,sp,448 - 7972: 0124 addi s1,sp,136 - 7974: 0305 addi t1,t1,1 - 7976: 00090103 lb sp,0(s2) - 797a: 0100 addi s0,sp,128 - 797c: 00090003 lb zero,0(s2) - 7980: 0100 addi s0,sp,128 - 7982: 00090003 lb zero,0(s2) - 7986: 0100 addi s0,sp,128 - 7988: 00090003 lb zero,0(s2) - 798c: 0100 addi s0,sp,128 - 798e: 00090103 lb sp,0(s2) - 7992: 0100 addi s0,sp,128 - 7994: 00090203 lb tp,0(s2) - 7998: 0100 addi s0,sp,128 - 799a: 00090003 lb zero,0(s2) - 799e: 0100 addi s0,sp,128 - 79a0: 0105 addi sp,sp,1 - 79a2: 0306 slli t1,t1,0x1 - 79a4: 097c addi a5,sp,156 - 79a6: 0000 unimp - 79a8: 0301 addi t1,t1,0 - 79aa: 0900 addi s0,sp,144 - 79ac: 0014 0x14 - 79ae: 0501 addi a0,a0,0 - 79b0: 09040303 lb t1,144(s0) # ffff8090 <__BSS_END__+0x7ffe1318> - 79b4: 0004 0x4 - 79b6: 0001 nop - 79b8: 0402 c.slli64 s0 - 79ba: 0601 addi a2,a2,0 - 79bc: 04090003 lb zero,64(s2) - 79c0: 0100 addi s0,sp,128 - 79c2: 0200 addi s0,sp,256 - 79c4: 0104 addi s1,sp,128 - 79c6: 00090003 lb zero,0(s2) - 79ca: 0100 addi s0,sp,128 - 79cc: 0200 addi s0,sp,256 - 79ce: 0104 addi s1,sp,128 - 79d0: 14090003 lb zero,320(s2) - 79d4: 0100 addi s0,sp,128 - 79d6: 0200 addi s0,sp,256 - 79d8: 0104 addi s1,sp,128 - 79da: 00090003 lb zero,0(s2) - 79de: 0100 addi s0,sp,128 - 79e0: 0200 addi s0,sp,256 - 79e2: 0104 addi s1,sp,128 - 79e4: 00090003 lb zero,0(s2) - 79e8: 0100 addi s0,sp,128 - 79ea: 0200 addi s0,sp,256 - 79ec: 0104 addi s1,sp,128 - 79ee: 00090003 lb zero,0(s2) - 79f2: 0100 addi s0,sp,128 - 79f4: 0200 addi s0,sp,256 - 79f6: 0104 addi s1,sp,128 - 79f8: 00090003 lb zero,0(s2) - 79fc: 0100 addi s0,sp,128 - 79fe: 0200 addi s0,sp,256 - 7a00: 0104 addi s1,sp,128 - 7a02: 00090003 lb zero,0(s2) - 7a06: 0100 addi s0,sp,128 - 7a08: 0200 addi s0,sp,256 - 7a0a: 0104 addi s1,sp,128 - 7a0c: 00090003 lb zero,0(s2) - 7a10: 0100 addi s0,sp,128 - 7a12: 0200 addi s0,sp,256 - 7a14: 0104 addi s1,sp,128 - 7a16: 04090003 lb zero,64(s2) - 7a1a: 0100 addi s0,sp,128 - 7a1c: 0200 addi s0,sp,256 - 7a1e: 0104 addi s1,sp,128 - 7a20: 0c090003 lb zero,192(s2) - 7a24: 0100 addi s0,sp,128 - 7a26: 0200 addi s0,sp,256 - 7a28: 0104 addi s1,sp,128 - 7a2a: 00090003 lb zero,0(s2) - 7a2e: 0100 addi s0,sp,128 - 7a30: 0200 addi s0,sp,256 - 7a32: 0104 addi s1,sp,128 - 7a34: 00090003 lb zero,0(s2) - 7a38: 0100 addi s0,sp,128 - 7a3a: 0200 addi s0,sp,256 - 7a3c: 0104 addi s1,sp,128 - 7a3e: 00090003 lb zero,0(s2) - 7a42: 0100 addi s0,sp,128 - 7a44: 0200 addi s0,sp,256 - 7a46: 0104 addi s1,sp,128 - 7a48: 08090003 lb zero,128(s2) - 7a4c: 0100 addi s0,sp,128 - 7a4e: 0200 addi s0,sp,256 - 7a50: 0104 addi s1,sp,128 - 7a52: 04090003 lb zero,64(s2) - 7a56: 0100 addi s0,sp,128 - 7a58: 0200 addi s0,sp,256 - 7a5a: 0104 addi s1,sp,128 - 7a5c: 04090003 lb zero,64(s2) - 7a60: 0100 addi s0,sp,128 - 7a62: 0200 addi s0,sp,256 - 7a64: 0104 addi s1,sp,128 - 7a66: 04090003 lb zero,64(s2) - 7a6a: 0100 addi s0,sp,128 - 7a6c: 0200 addi s0,sp,256 - 7a6e: 0104 addi s1,sp,128 - 7a70: 00090003 lb zero,0(s2) - 7a74: 0100 addi s0,sp,128 - 7a76: 0200 addi s0,sp,256 - 7a78: 0104 addi s1,sp,128 - 7a7a: 00090003 lb zero,0(s2) - 7a7e: 0100 addi s0,sp,128 - 7a80: 0200 addi s0,sp,256 - 7a82: 0104 addi s1,sp,128 - 7a84: 00090003 lb zero,0(s2) - 7a88: 0100 addi s0,sp,128 - 7a8a: 0200 addi s0,sp,256 - 7a8c: 0104 addi s1,sp,128 - 7a8e: 00090003 lb zero,0(s2) - 7a92: 0100 addi s0,sp,128 - 7a94: 0200 addi s0,sp,256 - 7a96: 0104 addi s1,sp,128 - 7a98: 00090003 lb zero,0(s2) - 7a9c: 0100 addi s0,sp,128 - 7a9e: 0200 addi s0,sp,256 - 7aa0: 0104 addi s1,sp,128 - 7aa2: 04090003 lb zero,64(s2) - 7aa6: 0100 addi s0,sp,128 - 7aa8: 0200 addi s0,sp,256 - 7aaa: 0104 addi s1,sp,128 - 7aac: 00090003 lb zero,0(s2) - 7ab0: 0100 addi s0,sp,128 - 7ab2: 0306 slli t1,t1,0x1 - 7ab4: 0900 addi s0,sp,144 - 7ab6: 0004 0x4 - 7ab8: 0601 addi a2,a2,0 - 7aba: 0c090003 lb zero,192(s2) - 7abe: 0100 addi s0,sp,128 - 7ac0: 0200 addi s0,sp,256 - 7ac2: 1f04 addi s1,sp,944 - 7ac4: 14090003 lb zero,320(s2) - 7ac8: 0100 addi s0,sp,128 - 7aca: 0306 slli t1,t1,0x1 - 7acc: 0900 addi s0,sp,144 - 7ace: 001c 0x1c - 7ad0: 0601 addi a2,a2,0 - 7ad2: 04090003 lb zero,64(s2) - 7ad6: 0100 addi s0,sp,128 - 7ad8: 28090003 lb zero,640(s2) - 7adc: 0100 addi s0,sp,128 - 7ade: 0200 addi s0,sp,256 - 7ae0: 2204 fld fs1,0(a2) - 7ae2: 0306 slli t1,t1,0x1 - 7ae4: 0900 addi s0,sp,144 - 7ae6: 0020 addi s0,sp,8 - 7ae8: 0001 nop - 7aea: 0402 c.slli64 s0 - 7aec: 0622 slli a2,a2,0x8 - 7aee: 04090003 lb zero,64(s2) - 7af2: 0100 addi s0,sp,128 - 7af4: 18090103 lb sp,384(s2) - 7af8: 0100 addi s0,sp,128 - 7afa: 00090003 lb zero,0(s2) - 7afe: 0100 addi s0,sp,128 - 7b00: 00090003 lb zero,0(s2) - 7b04: 0100 addi s0,sp,128 - 7b06: 00090003 lb zero,0(s2) - 7b0a: 0100 addi s0,sp,128 - 7b0c: 00090003 lb zero,0(s2) - 7b10: 0100 addi s0,sp,128 - 7b12: 00090003 lb zero,0(s2) - 7b16: 0100 addi s0,sp,128 - 7b18: 10090003 lb zero,256(s2) - 7b1c: 0100 addi s0,sp,128 - 7b1e: 18090003 lb zero,384(s2) - 7b22: 0100 addi s0,sp,128 - 7b24: 0a05 addi s4,s4,1 - 7b26: 0306 slli t1,t1,0x1 - 7b28: 0902 c.slli64 s2 - 7b2a: 0000 unimp - 7b2c: 0501 addi a0,a0,0 - 7b2e: 097e0303 lb t1,151(t3) # 1a097 <_start-0x7ffe5f69> - 7b32: 0004 0x4 - 7b34: 0501 addi a0,a0,0 - 7b36: 030a slli t1,t1,0x2 - 7b38: 0902 c.slli64 s2 - 7b3a: 0008 0x8 - 7b3c: 0501 addi a0,a0,0 - 7b3e: 0301 addi t1,t1,0 - 7b40: 0901 addi s2,s2,0 - 7b42: 0008 0x8 - 7b44: 0501 addi a0,a0,0 - 7b46: 030a slli t1,t1,0x2 - 7b48: 097f 0x97f - 7b4a: 0008 0x8 - 7b4c: 0501 addi a0,a0,0 - 7b4e: 097e0303 lb t1,151(t3) - 7b52: 0008 0x8 - 7b54: 0601 addi a2,a2,0 - 7b56: 08090003 lb zero,128(s2) - 7b5a: 0100 addi s0,sp,128 - 7b5c: 00090203 lb tp,0(s2) - 7b60: 0100 addi s0,sp,128 - 7b62: 0a05 addi s4,s4,1 - 7b64: 0306 slli t1,t1,0x1 - 7b66: 0900 addi s0,sp,144 - 7b68: 0000 unimp - 7b6a: 0501 addi a0,a0,0 - 7b6c: 0301 addi t1,t1,0 - 7b6e: 0901 addi s2,s2,0 - 7b70: 0008 0x8 - 7b72: 0501 addi a0,a0,0 - 7b74: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> - 7b78: 0602 c.slli64 a2 - 7b7a: 14097c03 0x14097c03 - 7b7e: 0100 addi s0,sp,128 - 7b80: 0200 addi s0,sp,256 - 7b82: 0204 addi s1,sp,256 - 7b84: 00090003 lb zero,0(s2) - 7b88: 0100 addi s0,sp,128 - 7b8a: 0200 addi s0,sp,256 - 7b8c: 0204 addi s1,sp,256 - 7b8e: 00090003 lb zero,0(s2) - 7b92: 0100 addi s0,sp,128 - 7b94: 1809 addi a6,a6,-30 - 7b96: 0000 unimp - 7b98: 0101 addi sp,sp,0 - 7b9a: 045e slli s0,s0,0x17 - 7b9c: 0000 unimp - 7b9e: 00a20003 lb zero,10(tp) # a <_start-0x7ffffff6> - 7ba2: 0000 unimp - 7ba4: 0101 addi sp,sp,0 - 7ba6: 000d0efb 0xd0efb - 7baa: 0101 addi sp,sp,0 - 7bac: 0101 addi sp,sp,0 - 7bae: 0000 unimp - 7bb0: 0100 addi s0,sp,128 - 7bb2: 0000 unimp - 7bb4: 2e01 jal 7ec4 <_start-0x7fff813c> - 7bb6: 2f2e fld ft10,200(sp) - 7bb8: 2e2e fld ft8,200(sp) - 7bba: 2f2e2e2f 0x2f2e2e2f - 7bbe: 2e2e fld ft8,200(sp) - 7bc0: 7369722f 0x7369722f - 7bc4: 672d7663 bgeu s10,s2,8230 <_start-0x7fff7dd0> - 7bc8: 6c2f6363 bltu t5,sp,828e <_start-0x7fff7d72> - 7bcc: 6269 lui tp,0x1a - 7bce: 2f636367 0x2f636367 - 7bd2: 74666f73 csrrsi t5,0x746,12 - 7bd6: 662d lui a2,0xb - 7bd8: 0070 addi a2,sp,12 - 7bda: 2e2e fld ft8,200(sp) - 7bdc: 2f2e2e2f 0x2f2e2e2f - 7be0: 2e2e fld ft8,200(sp) - 7be2: 2f2e2e2f 0x2f2e2e2f - 7be6: 6972 flw fs2,28(sp) - 7be8: 2d766373 csrrsi t1,0x2d7,12 - 7bec: 2f636367 0x2f636367 - 7bf0: 696c flw fa1,84(a0) - 7bf2: 6762 flw fa4,24(sp) - 7bf4: 2e2f6363 bltu t5,sp,7eda <_start-0x7fff8126> - 7bf8: 2f2e fld ft10,200(sp) - 7bfa: 6e69 lui t3,0x1a - 7bfc: 64756c63 bltu a0,t2,8254 <_start-0x7fff7dac> - 7c00: 0065 c.nop 25 - 7c02: 6500 flw fs0,8(a0) - 7c04: 7478 flw fa4,108(s0) - 7c06: 6e65 lui t3,0x19 - 7c08: 6464 flw fs1,76(s0) - 7c0a: 7466 flw fs0,120(sp) - 7c0c: 3266 fld ft4,120(sp) - 7c0e: 632e flw ft6,200(sp) - 7c10: 0100 addi s0,sp,128 - 7c12: 0000 unimp - 7c14: 74666f73 csrrsi t5,0x746,12 - 7c18: 662d lui a2,0xb - 7c1a: 2e70 fld fa2,216(a2) - 7c1c: 0068 addi a0,sp,12 - 7c1e: 0001 nop - 7c20: 6400 flw fs0,8(s0) - 7c22: 6c62756f jal a0,2f2e8 <_start-0x7ffd0d18> - 7c26: 2e65 jal 7fde <_start-0x7fff8022> - 7c28: 0068 addi a0,sp,12 - 7c2a: 0001 nop - 7c2c: 7100 flw fs0,32(a0) - 7c2e: 6175 addi sp,sp,368 - 7c30: 2e64 fld fs1,216(a2) - 7c32: 0068 addi a0,sp,12 - 7c34: 0001 nop - 7c36: 6c00 flw fs0,24(s0) - 7c38: 6c676e6f jal t3,7e2fe <_start-0x7ff81d02> - 7c3c: 2e676e6f jal t3,7df22 <_start-0x7ff820de> - 7c40: 0068 addi a0,sp,12 - 7c42: 0002 c.slli64 zero - 7c44: 0000 unimp - 7c46: 0105 addi sp,sp,1 - 7c48: 0500 addi s0,sp,640 - 7c4a: bc02 fsd ft0,56(sp) - 7c4c: 0380013f 03050125 0x30501250380013f - 7c54: 00090103 lb sp,0(s2) - 7c58: 0100 addi s0,sp,128 - 7c5a: 00090003 lb zero,0(s2) - 7c5e: 0100 addi s0,sp,128 - 7c60: 0d05 addi s10,s10,1 - 7c62: 00090003 lb zero,0(s2) - 7c66: 0100 addi s0,sp,128 - 7c68: 0305 addi t1,t1,1 - 7c6a: 00090103 lb sp,0(s2) - 7c6e: 0100 addi s0,sp,128 - 7c70: 00090003 lb zero,0(s2) - 7c74: 0100 addi s0,sp,128 - 7c76: 00090003 lb zero,0(s2) - 7c7a: 0100 addi s0,sp,128 - 7c7c: 00090003 lb zero,0(s2) - 7c80: 0100 addi s0,sp,128 - 7c82: 00090103 lb sp,0(s2) - 7c86: 0100 addi s0,sp,128 - 7c88: 00090003 lb zero,0(s2) - 7c8c: 0100 addi s0,sp,128 - 7c8e: 00090003 lb zero,0(s2) - 7c92: 0100 addi s0,sp,128 - 7c94: 00090003 lb zero,0(s2) - 7c98: 0100 addi s0,sp,128 - 7c9a: 00090103 lb sp,0(s2) - 7c9e: 0100 addi s0,sp,128 - 7ca0: 00090203 lb tp,0(s2) - 7ca4: 0100 addi s0,sp,128 - 7ca6: 00090103 lb sp,0(s2) - 7caa: 0100 addi s0,sp,128 - 7cac: 00090003 lb zero,0(s2) - 7cb0: 0100 addi s0,sp,128 - 7cb2: 00090003 lb zero,0(s2) - 7cb6: 0100 addi s0,sp,128 - 7cb8: 00090003 lb zero,0(s2) - 7cbc: 0100 addi s0,sp,128 - 7cbe: 00090003 lb zero,0(s2) - 7cc2: 0100 addi s0,sp,128 - 7cc4: 0105 addi sp,sp,1 - 7cc6: 0306 slli t1,t1,0x1 - 7cc8: 0979 addi s2,s2,30 - 7cca: 000c 0xc - 7ccc: 0501 addi a0,a0,0 - 7cce: 09070303 lb t1,144(a4) - 7cd2: 0004 0x4 - 7cd4: 0601 addi a2,a2,0 - 7cd6: 04090003 lb zero,64(s2) - 7cda: 0100 addi s0,sp,128 - 7cdc: 00090003 lb zero,0(s2) - 7ce0: 0100 addi s0,sp,128 - 7ce2: 0306 slli t1,t1,0x1 - 7ce4: 0902 c.slli64 s2 - 7ce6: 0000 unimp - 7ce8: 0501 addi a0,a0,0 - 7cea: 0301 addi t1,t1,0 - 7cec: 00040977 0x40977 - 7cf0: 0501 addi a0,a0,0 - 7cf2: 09090303 lb t1,144(s2) - 7cf6: 000c 0xc - 7cf8: 0501 addi a0,a0,0 - 7cfa: 0301 addi t1,t1,0 - 7cfc: 00140977 0x140977 - 7d00: 0501 addi a0,a0,0 - 7d02: 09070303 lb t1,144(a4) - 7d06: 0004 0x4 - 7d08: 0601 addi a2,a2,0 - 7d0a: 04090203 lb tp,64(s2) - 7d0e: 0100 addi s0,sp,128 - 7d10: 00090003 lb zero,0(s2) - 7d14: 0100 addi s0,sp,128 - 7d16: 00090003 lb zero,0(s2) - 7d1a: 0100 addi s0,sp,128 - 7d1c: 00090003 lb zero,0(s2) - 7d20: 0100 addi s0,sp,128 - 7d22: 00090003 lb zero,0(s2) - 7d26: 0100 addi s0,sp,128 - 7d28: 00090003 lb zero,0(s2) - 7d2c: 0100 addi s0,sp,128 - 7d2e: 00090003 lb zero,0(s2) - 7d32: 0100 addi s0,sp,128 - 7d34: 00090003 lb zero,0(s2) - 7d38: 0100 addi s0,sp,128 - 7d3a: 00090003 lb zero,0(s2) - 7d3e: 0100 addi s0,sp,128 - 7d40: 00090003 lb zero,0(s2) - 7d44: 0100 addi s0,sp,128 - 7d46: 0200 addi s0,sp,256 - 7d48: 0104 addi s1,sp,128 - 7d4a: 04090003 lb zero,64(s2) - 7d4e: 0100 addi s0,sp,128 - 7d50: 0200 addi s0,sp,256 - 7d52: 0104 addi s1,sp,128 - 7d54: 10090003 lb zero,256(s2) - 7d58: 0100 addi s0,sp,128 - 7d5a: 0200 addi s0,sp,256 - 7d5c: 0104 addi s1,sp,128 - 7d5e: 00090003 lb zero,0(s2) - 7d62: 0100 addi s0,sp,128 - 7d64: 0200 addi s0,sp,256 - 7d66: 0104 addi s1,sp,128 - 7d68: 00090003 lb zero,0(s2) - 7d6c: 0100 addi s0,sp,128 - 7d6e: 0200 addi s0,sp,256 - 7d70: 0104 addi s1,sp,128 - 7d72: 00090003 lb zero,0(s2) - 7d76: 0100 addi s0,sp,128 - 7d78: 0200 addi s0,sp,256 - 7d7a: 0104 addi s1,sp,128 - 7d7c: 00090003 lb zero,0(s2) - 7d80: 0100 addi s0,sp,128 - 7d82: 0200 addi s0,sp,256 - 7d84: 0104 addi s1,sp,128 - 7d86: 00090003 lb zero,0(s2) - 7d8a: 0100 addi s0,sp,128 - 7d8c: 0200 addi s0,sp,256 - 7d8e: 0104 addi s1,sp,128 - 7d90: 00090003 lb zero,0(s2) - 7d94: 0100 addi s0,sp,128 - 7d96: 0200 addi s0,sp,256 - 7d98: 0104 addi s1,sp,128 - 7d9a: 00090003 lb zero,0(s2) - 7d9e: 0100 addi s0,sp,128 - 7da0: 0200 addi s0,sp,256 - 7da2: 0104 addi s1,sp,128 - 7da4: 00090003 lb zero,0(s2) - 7da8: 0100 addi s0,sp,128 - 7daa: 0200 addi s0,sp,256 - 7dac: 0104 addi s1,sp,128 - 7dae: 14090003 lb zero,320(s2) - 7db2: 0100 addi s0,sp,128 - 7db4: 0200 addi s0,sp,256 - 7db6: 0104 addi s1,sp,128 - 7db8: 04090003 lb zero,64(s2) - 7dbc: 0100 addi s0,sp,128 - 7dbe: 0200 addi s0,sp,256 - 7dc0: 0104 addi s1,sp,128 - 7dc2: 04090003 lb zero,64(s2) - 7dc6: 0100 addi s0,sp,128 - 7dc8: 04090403 lb s0,64(s2) - 7dcc: 0100 addi s0,sp,128 - 7dce: 00090003 lb zero,0(s2) - 7dd2: 0100 addi s0,sp,128 - 7dd4: 00090003 lb zero,0(s2) - 7dd8: 0100 addi s0,sp,128 - 7dda: 00090003 lb zero,0(s2) - 7dde: 0100 addi s0,sp,128 - 7de0: 00090003 lb zero,0(s2) - 7de4: 0100 addi s0,sp,128 - 7de6: 00090003 lb zero,0(s2) - 7dea: 0100 addi s0,sp,128 - 7dec: 10090003 lb zero,256(s2) - 7df0: 0100 addi s0,sp,128 - 7df2: 18090003 lb zero,384(s2) - 7df6: 0100 addi s0,sp,128 - 7df8: 0a05 addi s4,s4,1 - 7dfa: 0306 slli t1,t1,0x1 - 7dfc: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> - 7e00: 0501 addi a0,a0,0 - 7e02: 097d0303 lb t1,151(s10) - 7e06: 0004 0x4 - 7e08: 0501 addi a0,a0,0 - 7e0a: 030a slli t1,t1,0x2 - 7e0c: 00080903 lb s2,0(a6) - 7e10: 0501 addi a0,a0,0 - 7e12: 097d0303 lb t1,151(s10) - 7e16: 0008 0x8 - 7e18: 0601 addi a2,a2,0 - 7e1a: 08090003 lb zero,128(s2) - 7e1e: 0100 addi s0,sp,128 - 7e20: 00090103 lb sp,0(s2) - 7e24: 0100 addi s0,sp,128 - 7e26: 00090003 lb zero,0(s2) - 7e2a: 0100 addi s0,sp,128 - 7e2c: 00090203 lb tp,0(s2) - 7e30: 0100 addi s0,sp,128 - 7e32: 0a05 addi s4,s4,1 - 7e34: 0306 slli t1,t1,0x1 - 7e36: 0900 addi s0,sp,144 - 7e38: 0000 unimp - 7e3a: 0501 addi a0,a0,0 - 7e3c: 0301 addi t1,t1,0 - 7e3e: 0901 addi s2,s2,0 - 7e40: 0008 0x8 - 7e42: 0501 addi a0,a0,0 - 7e44: 030a slli t1,t1,0x2 - 7e46: 097f 0x97f - 7e48: 0008 0x8 - 7e4a: 0501 addi a0,a0,0 - 7e4c: 0301 addi t1,t1,0 - 7e4e: 0901 addi s2,s2,0 - 7e50: 0008 0x8 - 7e52: 0501 addi a0,a0,0 - 7e54: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> - 7e58: 0602 c.slli64 a2 - 7e5a: 10097803 0x10097803 - 7e5e: 0100 addi s0,sp,128 - 7e60: 0200 addi s0,sp,256 - 7e62: 1304 addi s1,sp,416 - 7e64: 08090003 lb zero,128(s2) - 7e68: 0100 addi s0,sp,128 - 7e6a: 0200 addi s0,sp,256 - 7e6c: 1304 addi s1,sp,416 - 7e6e: 00090003 lb zero,0(s2) - 7e72: 0100 addi s0,sp,128 - 7e74: 0200 addi s0,sp,256 - 7e76: 1304 addi s1,sp,416 - 7e78: 00090003 lb zero,0(s2) - 7e7c: 0100 addi s0,sp,128 - 7e7e: 0200 addi s0,sp,256 - 7e80: 1704 addi s1,sp,928 - 7e82: 04090003 lb zero,64(s2) - 7e86: 0100 addi s0,sp,128 - 7e88: 0200 addi s0,sp,256 - 7e8a: 1704 addi s1,sp,928 - 7e8c: 00090003 lb zero,0(s2) - 7e90: 0100 addi s0,sp,128 - 7e92: 0200 addi s0,sp,256 - 7e94: 1704 addi s1,sp,928 - 7e96: 00090003 lb zero,0(s2) - 7e9a: 0100 addi s0,sp,128 - 7e9c: 0200 addi s0,sp,256 - 7e9e: 1704 addi s1,sp,928 - 7ea0: 00090003 lb zero,0(s2) - 7ea4: 0100 addi s0,sp,128 - 7ea6: 0200 addi s0,sp,256 - 7ea8: 1704 addi s1,sp,928 - 7eaa: 00090003 lb zero,0(s2) - 7eae: 0100 addi s0,sp,128 - 7eb0: 0200 addi s0,sp,256 - 7eb2: 2804 fld fs1,16(s0) - 7eb4: 04090003 lb zero,64(s2) - 7eb8: 0100 addi s0,sp,128 - 7eba: 0200 addi s0,sp,256 - 7ebc: 2804 fld fs1,16(s0) - 7ebe: 00090003 lb zero,0(s2) - 7ec2: 0100 addi s0,sp,128 - 7ec4: 0200 addi s0,sp,256 - 7ec6: 2804 fld fs1,16(s0) - 7ec8: 00090003 lb zero,0(s2) - 7ecc: 0100 addi s0,sp,128 - 7ece: 0200 addi s0,sp,256 - 7ed0: 2804 fld fs1,16(s0) - 7ed2: 00090003 lb zero,0(s2) - 7ed6: 0100 addi s0,sp,128 - 7ed8: 0200 addi s0,sp,256 - 7eda: 3304 fld fs1,32(a4) - 7edc: 08090003 lb zero,128(s2) - 7ee0: 0100 addi s0,sp,128 - 7ee2: 0200 addi s0,sp,256 - 7ee4: 3304 fld fs1,32(a4) - 7ee6: 00090003 lb zero,0(s2) - 7eea: 0100 addi s0,sp,128 - 7eec: 0200 addi s0,sp,256 - 7eee: 3304 fld fs1,32(a4) - 7ef0: 00090003 lb zero,0(s2) - 7ef4: 0100 addi s0,sp,128 - 7ef6: 0200 addi s0,sp,256 - 7ef8: 3304 fld fs1,32(a4) - 7efa: 00090003 lb zero,0(s2) - 7efe: 0100 addi s0,sp,128 - 7f00: 0200 addi s0,sp,256 - 7f02: 3304 fld fs1,32(a4) - 7f04: 08090003 lb zero,128(s2) - 7f08: 0100 addi s0,sp,128 - 7f0a: 0200 addi s0,sp,256 - 7f0c: 3304 fld fs1,32(a4) - 7f0e: 04090003 lb zero,64(s2) - 7f12: 0100 addi s0,sp,128 - 7f14: 0200 addi s0,sp,256 - 7f16: 3304 fld fs1,32(a4) - 7f18: 00090003 lb zero,0(s2) - 7f1c: 0100 addi s0,sp,128 - 7f1e: 0306 slli t1,t1,0x1 - 7f20: 0900 addi s0,sp,144 - 7f22: 0010 0x10 - 7f24: 0001 nop - 7f26: 0402 c.slli64 s0 - 7f28: 0339 addi t1,t1,14 - 7f2a: 0900 addi s0,sp,144 - 7f2c: 0014 0x14 - 7f2e: 0001 nop - 7f30: 0402 c.slli64 s0 - 7f32: 033c addi a5,sp,392 - 7f34: 0900 addi s0,sp,144 - 7f36: 0004 0x4 - 7f38: 0001 nop - 7f3a: 0402 c.slli64 s0 - 7f3c: 063c addi a5,sp,776 - 7f3e: 10090003 lb zero,256(s2) - 7f42: 0100 addi s0,sp,128 - 7f44: 0200 addi s0,sp,256 - 7f46: 2c04 fld fs1,24(s0) - 7f48: 0c090003 lb zero,192(s2) - 7f4c: 0100 addi s0,sp,128 - 7f4e: 0200 addi s0,sp,256 - 7f50: 2c04 fld fs1,24(s0) - 7f52: 00090003 lb zero,0(s2) - 7f56: 0100 addi s0,sp,128 - 7f58: 0200 addi s0,sp,256 - 7f5a: 2c04 fld fs1,24(s0) - 7f5c: 00090003 lb zero,0(s2) - 7f60: 0100 addi s0,sp,128 - 7f62: 0200 addi s0,sp,256 - 7f64: 2c04 fld fs1,24(s0) - 7f66: 00090003 lb zero,0(s2) - 7f6a: 0100 addi s0,sp,128 - 7f6c: 0200 addi s0,sp,256 - 7f6e: 2c04 fld fs1,24(s0) - 7f70: 04090003 lb zero,64(s2) - 7f74: 0100 addi s0,sp,128 - 7f76: 0306 slli t1,t1,0x1 - 7f78: 0900 addi s0,sp,144 - 7f7a: 0014 0x14 - 7f7c: 0001 nop - 7f7e: 0402 c.slli64 s0 - 7f80: 0638 addi a4,sp,776 - 7f82: 04090003 lb zero,64(s2) - 7f86: 0100 addi s0,sp,128 - 7f88: 0200 addi s0,sp,256 - 7f8a: 3f04 fld fs1,56(a4) - 7f8c: 0306 slli t1,t1,0x1 - 7f8e: 0900 addi s0,sp,144 - 7f90: 001c 0x1c - 7f92: 0001 nop - 7f94: 0402 c.slli64 s0 - 7f96: 0003063f 01000409 0x10004090003063f - 7f9e: 0200 addi s0,sp,256 - 7fa0: 4004 lw s1,0(s0) - 7fa2: 18090003 lb zero,384(s2) - 7fa6: 0100 addi s0,sp,128 - 7fa8: 0200 addi s0,sp,256 - 7faa: 3b04 fld fs1,48(a4) - 7fac: 10090003 lb zero,256(s2) - 7fb0: 0100 addi s0,sp,128 - 7fb2: 0200 addi s0,sp,256 - 7fb4: 1004 addi s1,sp,32 - 7fb6: 24090003 lb zero,576(s2) - 7fba: 0100 addi s0,sp,128 - 7fbc: 0200 addi s0,sp,256 - 7fbe: 1004 addi s1,sp,32 - 7fc0: 00090003 lb zero,0(s2) - 7fc4: 0100 addi s0,sp,128 - 7fc6: 08090003 lb zero,128(s2) - 7fca: 0100 addi s0,sp,128 - 7fcc: 00090003 lb zero,0(s2) - 7fd0: 0100 addi s0,sp,128 - 7fd2: 10090003 lb zero,256(s2) - 7fd6: 0100 addi s0,sp,128 - 7fd8: 14090003 lb zero,320(s2) - 7fdc: 0100 addi s0,sp,128 - 7fde: 04090003 lb zero,64(s2) - 7fe2: 0100 addi s0,sp,128 - 7fe4: 00090003 lb zero,0(s2) - 7fe8: 0100 addi s0,sp,128 - 7fea: 00090003 lb zero,0(s2) - 7fee: 0100 addi s0,sp,128 - 7ff0: 00090003 lb zero,0(s2) - 7ff4: 0100 addi s0,sp,128 - 7ff6: 0c09 addi s8,s8,2 - 7ff8: 0000 unimp - 7ffa: 0101 addi sp,sp,0 - 7ffc: 057a slli a0,a0,0x1e - 7ffe: 0000 unimp - 8000: 00a10003 lb zero,10(sp) - 8004: 0000 unimp - 8006: 0101 addi sp,sp,0 - 8008: 000d0efb 0xd0efb - 800c: 0101 addi sp,sp,0 - 800e: 0101 addi sp,sp,0 - 8010: 0000 unimp - 8012: 0100 addi s0,sp,128 - 8014: 0000 unimp - 8016: 2e01 jal 8326 <_start-0x7fff7cda> - 8018: 2f2e fld ft10,200(sp) - 801a: 2e2e fld ft8,200(sp) - 801c: 2f2e2e2f 0x2f2e2e2f - 8020: 2e2e fld ft8,200(sp) - 8022: 7369722f 0x7369722f - 8026: 672d7663 bgeu s10,s2,8692 <_start-0x7fff796e> - 802a: 6c2f6363 bltu t5,sp,86f0 <_start-0x7fff7910> - 802e: 6269 lui tp,0x1a - 8030: 2f636367 0x2f636367 - 8034: 74666f73 csrrsi t5,0x746,12 - 8038: 662d lui a2,0xb - 803a: 0070 addi a2,sp,12 - 803c: 2e2e fld ft8,200(sp) - 803e: 2f2e2e2f 0x2f2e2e2f - 8042: 2e2e fld ft8,200(sp) - 8044: 2f2e2e2f 0x2f2e2e2f - 8048: 6972 flw fs2,28(sp) - 804a: 2d766373 csrrsi t1,0x2d7,12 - 804e: 2f636367 0x2f636367 - 8052: 696c flw fa1,84(a0) - 8054: 6762 flw fa4,24(sp) - 8056: 2e2f6363 bltu t5,sp,833c <_start-0x7fff7cc4> - 805a: 2f2e fld ft10,200(sp) - 805c: 6e69 lui t3,0x1a - 805e: 64756c63 bltu a0,t2,86b6 <_start-0x7fff794a> - 8062: 0065 c.nop 25 - 8064: 7400 flw fs0,40(s0) - 8066: 7572 flw fa0,60(sp) - 8068: 636e flw ft6,216(sp) - 806a: 6674 flw fa3,76(a2) - 806c: 6664 flw fs1,76(a2) - 806e: 2e32 fld ft8,264(sp) - 8070: 00010063 beqz sp,8070 <_start-0x7fff7f90> - 8074: 7300 flw fs0,32(a4) - 8076: 2d74666f jal a2,4eb4c <_start-0x7ffb14b4> - 807a: 7066 flw ft0,120(sp) - 807c: 682e flw fa6,200(sp) - 807e: 0100 addi s0,sp,128 - 8080: 0000 unimp - 8082: 6f64 flw fs1,92(a4) - 8084: 6275 lui tp,0x1d - 8086: 656c flw fa1,76(a0) - 8088: 682e flw fa6,200(sp) - 808a: 0100 addi s0,sp,128 - 808c: 0000 unimp - 808e: 7571 lui a0,0xffffc - 8090: 6461 lui s0,0x18 - 8092: 682e flw fa6,200(sp) - 8094: 0100 addi s0,sp,128 - 8096: 0000 unimp - 8098: 6f6c flw fa1,92(a4) - 809a: 676e flw fa4,216(sp) - 809c: 6f6c flw fa1,92(a4) - 809e: 676e flw fa4,216(sp) - 80a0: 682e flw fa6,200(sp) - 80a2: 0200 addi s0,sp,256 - 80a4: 0000 unimp - 80a6: 0500 addi s0,sp,640 - 80a8: 0001 nop - 80aa: 0205 addi tp,tp,1 - 80ac: 41c8 lw a0,4(a1) - 80ae: 8001 c.srli64 s0 - 80b0: 05012403 lw s0,80(sp) - 80b4: 09010303 lb t1,144(sp) - 80b8: 0000 unimp - 80ba: 0301 addi t1,t1,0 - 80bc: 0900 addi s0,sp,144 - 80be: 0000 unimp - 80c0: 0501 addi a0,a0,0 - 80c2: 030d addi t1,t1,3 - 80c4: 0900 addi s0,sp,144 - 80c6: 0000 unimp - 80c8: 0501 addi a0,a0,0 - 80ca: 09010303 lb t1,144(sp) - 80ce: 0000 unimp - 80d0: 0301 addi t1,t1,0 - 80d2: 0900 addi s0,sp,144 - 80d4: 0000 unimp - 80d6: 0301 addi t1,t1,0 - 80d8: 0900 addi s0,sp,144 - 80da: 0000 unimp - 80dc: 0301 addi t1,t1,0 - 80de: 0900 addi s0,sp,144 - 80e0: 0000 unimp - 80e2: 0301 addi t1,t1,0 - 80e4: 0901 addi s2,s2,0 - 80e6: 0000 unimp - 80e8: 0301 addi t1,t1,0 - 80ea: 0900 addi s0,sp,144 - 80ec: 0000 unimp - 80ee: 0301 addi t1,t1,0 - 80f0: 0900 addi s0,sp,144 - 80f2: 0000 unimp - 80f4: 0301 addi t1,t1,0 - 80f6: 0900 addi s0,sp,144 - 80f8: 0000 unimp - 80fa: 0301 addi t1,t1,0 - 80fc: 0901 addi s2,s2,0 - 80fe: 0000 unimp - 8100: 0301 addi t1,t1,0 - 8102: 0902 c.slli64 s2 - 8104: 0000 unimp - 8106: 0301 addi t1,t1,0 - 8108: 0901 addi s2,s2,0 - 810a: 0000 unimp - 810c: 0301 addi t1,t1,0 - 810e: 0900 addi s0,sp,144 - 8110: 0000 unimp - 8112: 0301 addi t1,t1,0 - 8114: 0900 addi s0,sp,144 - 8116: 0000 unimp - 8118: 0301 addi t1,t1,0 - 811a: 0900 addi s0,sp,144 - 811c: 0000 unimp - 811e: 0501 addi a0,a0,0 - 8120: 0601 addi a2,a2,0 - 8122: 00097903 0x97903 - 8126: 0100 addi s0,sp,128 - 8128: 10090003 lb zero,256(s2) - 812c: 0100 addi s0,sp,128 - 812e: 0305 addi t1,t1,1 - 8130: 04090703 lb a4,64(s2) - 8134: 0100 addi s0,sp,128 - 8136: 0306 slli t1,t1,0x1 - 8138: 0900 addi s0,sp,144 - 813a: 0020 addi s0,sp,8 - 813c: 0301 addi t1,t1,0 - 813e: 0900 addi s0,sp,144 - 8140: 0008 0x8 - 8142: 0301 addi t1,t1,0 - 8144: 0900 addi s0,sp,144 - 8146: 0000 unimp - 8148: 0301 addi t1,t1,0 - 814a: 0900 addi s0,sp,144 - 814c: 0000 unimp - 814e: 0301 addi t1,t1,0 - 8150: 0900 addi s0,sp,144 - 8152: 0004 0x4 - 8154: 0301 addi t1,t1,0 - 8156: 0900 addi s0,sp,144 - 8158: 0004 0x4 - 815a: 0301 addi t1,t1,0 - 815c: 0900 addi s0,sp,144 - 815e: 0004 0x4 - 8160: 0301 addi t1,t1,0 - 8162: 0900 addi s0,sp,144 - 8164: 0000 unimp - 8166: 0301 addi t1,t1,0 - 8168: 0900 addi s0,sp,144 - 816a: 0000 unimp - 816c: 0301 addi t1,t1,0 - 816e: 0900 addi s0,sp,144 - 8170: 0000 unimp - 8172: 0301 addi t1,t1,0 - 8174: 0900 addi s0,sp,144 - 8176: 0000 unimp - 8178: 0301 addi t1,t1,0 - 817a: 0900 addi s0,sp,144 - 817c: 0000 unimp - 817e: 0301 addi t1,t1,0 - 8180: 0900 addi s0,sp,144 - 8182: 0000 unimp - 8184: 0301 addi t1,t1,0 - 8186: 0900 addi s0,sp,144 - 8188: 0000 unimp - 818a: 0001 nop - 818c: 0402 c.slli64 s0 - 818e: 0308 addi a0,sp,384 - 8190: 0900 addi s0,sp,144 - 8192: 0008 0x8 - 8194: 0001 nop - 8196: 0402 c.slli64 s0 - 8198: 0309 addi t1,t1,2 - 819a: 0900 addi s0,sp,144 - 819c: 0020 addi s0,sp,8 - 819e: 0001 nop - 81a0: 0402 c.slli64 s0 - 81a2: 0609 addi a2,a2,2 - 81a4: 04090203 lb tp,64(s2) - 81a8: 0100 addi s0,sp,128 - 81aa: 0200 addi s0,sp,256 - 81ac: 0904 addi s1,sp,144 - 81ae: 04097e03 0x4097e03 - 81b2: 0100 addi s0,sp,128 - 81b4: 0200 addi s0,sp,256 - 81b6: 0904 addi s1,sp,144 - 81b8: 04090203 lb tp,64(s2) - 81bc: 0100 addi s0,sp,128 - 81be: 0200 addi s0,sp,256 - 81c0: 0904 addi s1,sp,144 - 81c2: 08097e03 0x8097e03 - 81c6: 0100 addi s0,sp,128 - 81c8: 0200 addi s0,sp,256 - 81ca: 0904 addi s1,sp,144 - 81cc: 0306 slli t1,t1,0x1 - 81ce: 0902 c.slli64 s2 - 81d0: 0004 0x4 - 81d2: 0001 nop - 81d4: 0402 c.slli64 s0 - 81d6: 0309 addi t1,t1,2 - 81d8: 0900 addi s0,sp,144 - 81da: 0000 unimp - 81dc: 0001 nop - 81de: 0402 c.slli64 s0 - 81e0: 0309 addi t1,t1,2 - 81e2: 0900 addi s0,sp,144 - 81e4: 0000 unimp - 81e6: 0001 nop - 81e8: 0402 c.slli64 s0 - 81ea: 0309 addi t1,t1,2 - 81ec: 0900 addi s0,sp,144 - 81ee: 0000 unimp - 81f0: 0001 nop - 81f2: 0402 c.slli64 s0 - 81f4: 0309 addi t1,t1,2 - 81f6: 0900 addi s0,sp,144 - 81f8: 0000 unimp - 81fa: 0001 nop - 81fc: 0402 c.slli64 s0 - 81fe: 0301 addi t1,t1,0 - 8200: 0900 addi s0,sp,144 - 8202: 0008 0x8 - 8204: 0001 nop - 8206: 0402 c.slli64 s0 - 8208: 0301 addi t1,t1,0 - 820a: 0900 addi s0,sp,144 - 820c: 000c 0xc - 820e: 0001 nop - 8210: 0402 c.slli64 s0 - 8212: 0304 addi s1,sp,384 - 8214: 0900 addi s0,sp,144 - 8216: 0008 0x8 - 8218: 0301 addi t1,t1,0 - 821a: 0900 addi s0,sp,144 - 821c: 0004 0x4 - 821e: 0301 addi t1,t1,0 - 8220: 0900 addi s0,sp,144 - 8222: 0000 unimp - 8224: 0301 addi t1,t1,0 - 8226: 0900 addi s0,sp,144 - 8228: 0000 unimp - 822a: 0301 addi t1,t1,0 - 822c: 0900 addi s0,sp,144 - 822e: 000c 0xc - 8230: 0301 addi t1,t1,0 - 8232: 0900 addi s0,sp,144 - 8234: 0000 unimp - 8236: 0301 addi t1,t1,0 - 8238: 0900 addi s0,sp,144 - 823a: 0000 unimp - 823c: 0301 addi t1,t1,0 - 823e: 0900 addi s0,sp,144 - 8240: 002c addi a1,sp,8 - 8242: 0301 addi t1,t1,0 - 8244: 0900 addi s0,sp,144 - 8246: 0000 unimp - 8248: 0301 addi t1,t1,0 - 824a: 0900 addi s0,sp,144 - 824c: 0000 unimp - 824e: 0001 nop - 8250: 0402 c.slli64 s0 - 8252: 033a slli t1,t1,0xe - 8254: 0900 addi s0,sp,144 - 8256: 0004 0x4 - 8258: 0001 nop - 825a: 0402 c.slli64 s0 - 825c: 033a slli t1,t1,0xe - 825e: 0900 addi s0,sp,144 - 8260: 0000 unimp - 8262: 0001 nop - 8264: 0402 c.slli64 s0 - 8266: 033a slli t1,t1,0xe - 8268: 0900 addi s0,sp,144 - 826a: 0004 0x4 - 826c: 0301 addi t1,t1,0 - 826e: 0904 addi s1,sp,144 - 8270: 0004 0x4 - 8272: 0301 addi t1,t1,0 - 8274: 0900 addi s0,sp,144 - 8276: 0000 unimp - 8278: 0301 addi t1,t1,0 - 827a: 0900 addi s0,sp,144 - 827c: 0000 unimp - 827e: 0301 addi t1,t1,0 - 8280: 0900 addi s0,sp,144 - 8282: 0000 unimp - 8284: 0301 addi t1,t1,0 - 8286: 0900 addi s0,sp,144 - 8288: 0000 unimp - 828a: 0001 nop - 828c: 0402 c.slli64 s0 - 828e: 0325 addi t1,t1,9 - 8290: 0900 addi s0,sp,144 - 8292: 0008 0x8 - 8294: 0001 nop - 8296: 0402 c.slli64 s0 - 8298: 0325 addi t1,t1,9 - 829a: 0900 addi s0,sp,144 - 829c: 0000 unimp - 829e: 0001 nop - 82a0: 0402 c.slli64 s0 - 82a2: 0325 addi t1,t1,9 - 82a4: 0900 addi s0,sp,144 - 82a6: 0000 unimp - 82a8: 0001 nop - 82aa: 0402 c.slli64 s0 - 82ac: 0325 addi t1,t1,9 - 82ae: 0900 addi s0,sp,144 - 82b0: 0000 unimp - 82b2: 0001 nop - 82b4: 0402 c.slli64 s0 - 82b6: 032c addi a1,sp,392 - 82b8: 0900 addi s0,sp,144 - 82ba: 000c 0xc - 82bc: 0001 nop - 82be: 0402 c.slli64 s0 - 82c0: 032c addi a1,sp,392 - 82c2: 0900 addi s0,sp,144 - 82c4: 0000 unimp - 82c6: 0001 nop - 82c8: 0402 c.slli64 s0 - 82ca: 032c addi a1,sp,392 - 82cc: 0900 addi s0,sp,144 - 82ce: 0000 unimp - 82d0: 0001 nop - 82d2: 0402 c.slli64 s0 - 82d4: 032c addi a1,sp,392 - 82d6: 0900 addi s0,sp,144 - 82d8: 0004 0x4 - 82da: 0001 nop - 82dc: 0402 c.slli64 s0 - 82de: 032c addi a1,sp,392 - 82e0: 0900 addi s0,sp,144 - 82e2: 0008 0x8 - 82e4: 0001 nop - 82e6: 0402 c.slli64 s0 - 82e8: 0311 addi t1,t1,4 - 82ea: 097c addi a5,sp,156 - 82ec: 0008 0x8 - 82ee: 0001 nop - 82f0: 0402 c.slli64 s0 - 82f2: 09000313 li t1,144 - 82f6: 0008 0x8 - 82f8: 0001 nop - 82fa: 0402 c.slli64 s0 - 82fc: 09000313 li t1,144 - 8300: 0004 0x4 - 8302: 0001 nop - 8304: 0402 c.slli64 s0 - 8306: 0626 slli a2,a2,0x9 - 8308: 04090003 lb zero,64(s2) - 830c: 0100 addi s0,sp,128 - 830e: 0200 addi s0,sp,256 - 8310: 1404 addi s1,sp,544 - 8312: 0306 slli t1,t1,0x1 - 8314: 0900 addi s0,sp,144 - 8316: 000c 0xc - 8318: 0001 nop - 831a: 0402 c.slli64 s0 - 831c: 0314 addi a3,sp,384 - 831e: 0900 addi s0,sp,144 - 8320: 0014 0x14 - 8322: 0001 nop - 8324: 0402 c.slli64 s0 - 8326: 0314 addi a3,sp,384 - 8328: 0900 addi s0,sp,144 - 832a: 0000 unimp - 832c: 0001 nop - 832e: 0402 c.slli64 s0 - 8330: 0314 addi a3,sp,384 - 8332: 0900 addi s0,sp,144 - 8334: 0000 unimp - 8336: 0001 nop - 8338: 0402 c.slli64 s0 - 833a: 0314 addi a3,sp,384 - 833c: 0900 addi s0,sp,144 - 833e: 0000 unimp - 8340: 0001 nop - 8342: 0402 c.slli64 s0 - 8344: 0314 addi a3,sp,384 - 8346: 0900 addi s0,sp,144 - 8348: 0000 unimp - 834a: 0001 nop - 834c: 0402 c.slli64 s0 - 834e: 0314 addi a3,sp,384 - 8350: 0900 addi s0,sp,144 - 8352: 0000 unimp - 8354: 0001 nop - 8356: 0402 c.slli64 s0 - 8358: 0314 addi a3,sp,384 - 835a: 0900 addi s0,sp,144 - 835c: 0000 unimp - 835e: 0001 nop - 8360: 0402 c.slli64 s0 - 8362: 0314 addi a3,sp,384 - 8364: 0900 addi s0,sp,144 - 8366: 000c 0xc - 8368: 0001 nop - 836a: 0402 c.slli64 s0 - 836c: 0314 addi a3,sp,384 - 836e: 0900 addi s0,sp,144 - 8370: 0008 0x8 - 8372: 0001 nop - 8374: 0402 c.slli64 s0 - 8376: 0314 addi a3,sp,384 - 8378: 0900 addi s0,sp,144 - 837a: 0000 unimp - 837c: 0001 nop - 837e: 0402 c.slli64 s0 - 8380: 0318 addi a4,sp,384 - 8382: 0900 addi s0,sp,144 - 8384: 0004 0x4 - 8386: 0001 nop - 8388: 0402 c.slli64 s0 - 838a: 0319 addi t1,t1,6 - 838c: 0900 addi s0,sp,144 - 838e: 0014 0x14 - 8390: 0601 addi a2,a2,0 - 8392: 08090003 lb zero,128(s2) - 8396: 0100 addi s0,sp,128 - 8398: 0200 addi s0,sp,256 - 839a: 1e04 addi s1,sp,816 - 839c: 0306 slli t1,t1,0x1 - 839e: 0900 addi s0,sp,144 - 83a0: 0008 0x8 - 83a2: 0001 nop - 83a4: 0402 c.slli64 s0 - 83a6: 0624 addi s1,sp,776 - 83a8: 18090003 lb zero,384(s2) - 83ac: 0100 addi s0,sp,128 - 83ae: 0200 addi s0,sp,256 - 83b0: 2504 fld fs1,8(a0) - 83b2: 0306 slli t1,t1,0x1 - 83b4: 0900 addi s0,sp,144 - 83b6: 0004 0x4 - 83b8: 0001 nop - 83ba: 0402 c.slli64 s0 - 83bc: 0326 slli t1,t1,0x9 - 83be: 0900 addi s0,sp,144 - 83c0: 0014 0x14 - 83c2: 0001 nop - 83c4: 0402 c.slli64 s0 - 83c6: 0326 slli t1,t1,0x9 - 83c8: 0900 addi s0,sp,144 - 83ca: 0000 unimp - 83cc: 0001 nop - 83ce: 0402 c.slli64 s0 - 83d0: 0003061b 0x3061b - 83d4: 1009 c.nop -30 - 83d6: 0100 addi s0,sp,128 - 83d8: 0200 addi s0,sp,256 - 83da: 1b04 addi s1,sp,432 - 83dc: 0306 slli t1,t1,0x1 - 83de: 0900 addi s0,sp,144 - 83e0: 0014 0x14 - 83e2: 0001 nop - 83e4: 0402 c.slli64 s0 - 83e6: 0900031b 0x900031b - 83ea: 0008 0x8 - 83ec: 0001 nop - 83ee: 0402 c.slli64 s0 - 83f0: 061f 0003 1409 0x14090003061f - 83f6: 0100 addi s0,sp,128 - 83f8: 0200 addi s0,sp,256 - 83fa: 2204 fld fs1,0(a2) - 83fc: 0306 slli t1,t1,0x1 - 83fe: 0900 addi s0,sp,144 - 8400: 0004 0x4 - 8402: 0001 nop - 8404: 0402 c.slli64 s0 - 8406: 0321 addi t1,t1,8 - 8408: 0900 addi s0,sp,144 - 840a: 0024 addi s1,sp,8 - 840c: 0001 nop - 840e: 0402 c.slli64 s0 - 8410: 0302 c.slli64 t1 - 8412: 0900 addi s0,sp,144 - 8414: 0028 addi a0,sp,8 - 8416: 0001 nop - 8418: 0402 c.slli64 s0 - 841a: 0900033f 0001001c 0x1001c0900033f - 8422: 0402 c.slli64 s0 - 8424: 0900033f 00010000 0x100000900033f - 842c: 0402 c.slli64 s0 - 842e: 0900033f 00010000 0x100000900033f - 8436: 0402 c.slli64 s0 - 8438: 0900033f 00010000 0x100000900033f - 8440: 0402 c.slli64 s0 - 8442: 033c addi a5,sp,392 - 8444: 0900 addi s0,sp,144 - 8446: 000c 0xc - 8448: 0001 nop - 844a: 0402 c.slli64 s0 - 844c: 033c addi a5,sp,392 - 844e: 0900 addi s0,sp,144 - 8450: 0000 unimp - 8452: 0301 addi t1,t1,0 - 8454: 0900 addi s0,sp,144 - 8456: 0004 0x4 - 8458: 0301 addi t1,t1,0 - 845a: 0900 addi s0,sp,144 - 845c: 0000 unimp - 845e: 0301 addi t1,t1,0 - 8460: 0900 addi s0,sp,144 - 8462: 0000 unimp - 8464: 0301 addi t1,t1,0 - 8466: 0900 addi s0,sp,144 - 8468: 0000 unimp - 846a: 0301 addi t1,t1,0 - 846c: 0900 addi s0,sp,144 - 846e: 0000 unimp - 8470: 0301 addi t1,t1,0 - 8472: 0900 addi s0,sp,144 - 8474: 0000 unimp - 8476: 0301 addi t1,t1,0 - 8478: 0900 addi s0,sp,144 - 847a: 0000 unimp - 847c: 0301 addi t1,t1,0 - 847e: 0900 addi s0,sp,144 - 8480: 0024 addi s1,sp,8 - 8482: 0301 addi t1,t1,0 - 8484: 0900 addi s0,sp,144 - 8486: 0000 unimp - 8488: 0301 addi t1,t1,0 - 848a: 0900 addi s0,sp,144 - 848c: 0000 unimp - 848e: 0001 nop - 8490: 0402 c.slli64 s0 - 8492: 0904032f 0x904032f - 8496: 0014 0x14 - 8498: 0001 nop - 849a: 0402 c.slli64 s0 - 849c: 0900032f 0x900032f - 84a0: 0000 unimp - 84a2: 0001 nop - 84a4: 0402 c.slli64 s0 - 84a6: 0900033f 00010008 0x100080900033f - 84ae: 0402 c.slli64 s0 - 84b0: 0900033f 00010000 0x100000900033f - 84b8: 0402 c.slli64 s0 - 84ba: 0900033f 06010004 0x60100040900033f - 84c2: 08090003 lb zero,128(s2) - 84c6: 0100 addi s0,sp,128 - 84c8: 0200 addi s0,sp,256 - 84ca: 4f04 lw s1,24(a4) - 84cc: 0306 slli t1,t1,0x1 - 84ce: 0900 addi s0,sp,144 - 84d0: 000c 0xc - 84d2: 0001 nop - 84d4: 0402 c.slli64 s0 - 84d6: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 84da: 0000 unimp - 84dc: 0001 nop - 84de: 0402 c.slli64 s0 - 84e0: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 84e4: 000c 0xc - 84e6: 0001 nop - 84e8: 0402 c.slli64 s0 - 84ea: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 84ee: 0008 0x8 - 84f0: 0001 nop - 84f2: 0402 c.slli64 s0 - 84f4: 0650 addi a2,sp,772 - 84f6: 04090003 lb zero,64(s2) - 84fa: 0100 addi s0,sp,128 - 84fc: 0c090003 lb zero,192(s2) - 8500: 0100 addi s0,sp,128 - 8502: 0200 addi s0,sp,256 - 8504: 5a04 lw s1,48(a2) - 8506: 0306 slli t1,t1,0x1 - 8508: 0900 addi s0,sp,144 - 850a: 000c 0xc - 850c: 0001 nop - 850e: 0402 c.slli64 s0 - 8510: 035a slli t1,t1,0x16 - 8512: 0900 addi s0,sp,144 - 8514: 0000 unimp - 8516: 0001 nop - 8518: 0402 c.slli64 s0 - 851a: 035a slli t1,t1,0x16 - 851c: 0900 addi s0,sp,144 - 851e: 0000 unimp - 8520: 0001 nop - 8522: 0402 c.slli64 s0 - 8524: 035a slli t1,t1,0x16 - 8526: 0900 addi s0,sp,144 - 8528: 0000 unimp - 852a: 0001 nop - 852c: 0402 c.slli64 s0 - 852e: 035a slli t1,t1,0x16 - 8530: 0900 addi s0,sp,144 - 8532: 0000 unimp - 8534: 0001 nop - 8536: 0402 c.slli64 s0 - 8538: 035a slli t1,t1,0x16 - 853a: 0900 addi s0,sp,144 - 853c: 0000 unimp - 853e: 0001 nop - 8540: 0402 c.slli64 s0 - 8542: 035a slli t1,t1,0x16 - 8544: 0900 addi s0,sp,144 - 8546: 0000 unimp - 8548: 0001 nop - 854a: 0402 c.slli64 s0 - 854c: 035a slli t1,t1,0x16 - 854e: 0901 addi s2,s2,0 - 8550: 001c 0x1c - 8552: 0001 nop - 8554: 0402 c.slli64 s0 - 8556: 035a slli t1,t1,0x16 - 8558: 0900 addi s0,sp,144 - 855a: 0000 unimp - 855c: 0001 nop - 855e: 0402 c.slli64 s0 - 8560: 035a slli t1,t1,0x16 - 8562: 0902 c.slli64 s2 - 8564: 0000 unimp - 8566: 0501 addi a0,a0,0 - 8568: 0001 nop - 856a: 0402 c.slli64 s0 - 856c: 065a slli a2,a2,0x16 - 856e: 00090103 lb sp,0(s2) - 8572: 0100 addi s0,sp,128 - 8574: 2409 jal 8776 <_start-0x7fff788a> - 8576: 0000 unimp - 8578: 0101 addi sp,sp,0 - 857a: 0216 slli tp,tp,0x5 - 857c: 0000 unimp - 857e: 02100003 lb zero,33(zero) # 21 <_start-0x7fffffdf> - 8582: 0000 unimp - 8584: 0101 addi sp,sp,0 - 8586: 000d0efb 0xd0efb - 858a: 0101 addi sp,sp,0 - 858c: 0101 addi sp,sp,0 - 858e: 0000 unimp - 8590: 0100 addi s0,sp,128 - 8592: 0000 unimp - 8594: 2f01 jal 8ca4 <_start-0x7fff735c> - 8596: 6f68 flw fa0,92(a4) - 8598: 656d lui a0,0x1b - 859a: 6972702f 0x6972702f - 859e: 6179 addi sp,sp,464 - 85a0: 7665642f 0x7665642f - 85a4: 7369722f 0x7369722f - 85a8: 765f7663 bgeu t5,t0,8d14 <_start-0x7fff72ec> - 85ac: 6365 lui t1,0x19 - 85ae: 7369722f 0x7369722f - 85b2: 672d7663 bgeu s10,s2,8c1e <_start-0x7fff73e2> - 85b6: 756e flw fa0,248(sp) - 85b8: 7369722f 0x7369722f - 85bc: 32337663 bgeu t1,gp,88e8 <_start-0x7fff7718> - 85c0: 752d lui a0,0xfffeb - 85c2: 6b6e flw fs6,216(sp) - 85c4: 6f6e flw ft10,216(sp) - 85c6: 652d6e77 0x652d6e77 - 85ca: 666c flw fa1,76(a2) - 85cc: 636e692f vamoandw.v zero,v22,(t3),v18 - 85d0: 756c flw fa1,108(a0) - 85d2: 6564 flw fs1,76(a0) - 85d4: 7379732f 0x7379732f - 85d8: 2f00 fld fs0,24(a4) - 85da: 6f68 flw fa0,92(a4) - 85dc: 656d lui a0,0x1b - 85de: 6972702f 0x6972702f - 85e2: 6179 addi sp,sp,464 - 85e4: 7365442f 0x7365442f - 85e8: 706f746b 0x706f746b - 85ec: 7369722f 0x7369722f - 85f0: 672d7663 bgeu s10,s2,8c5c <_start-0x7fff73a4> - 85f4: 756e flw fa0,248(sp) - 85f6: 742d lui s0,0xfffeb - 85f8: 636c6f6f jal t5,cec2e <_start-0x7ff313d2> - 85fc: 6168 flw fa0,68(a0) - 85fe: 6e69 lui t3,0x1a - 8600: 6975622f 0x6975622f - 8604: 646c flw fa1,76(s0) - 8606: 6975622f 0x6975622f - 860a: 646c flw fa1,76(s0) - 860c: 672d lui a4,0xb - 860e: 6e2d6363 bltu s10,sp,8cf4 <_start-0x7fff730c> - 8612: 7765 lui a4,0xffff9 - 8614: 696c flw fa1,84(a0) - 8616: 2d62 fld fs10,24(sp) - 8618: 67617473 csrrci s0,0x676,2 - 861c: 3265 jal 7fc4 <_start-0x7fff803c> - 861e: 6363672f vamoandw.v zero,v22,(t1),v14 - 8622: 636e692f vamoandw.v zero,v22,(t3),v18 - 8626: 756c flw fa1,108(a0) - 8628: 6564 flw fs1,76(a0) - 862a: 2f00 fld fs0,24(a4) - 862c: 6f68 flw fa0,92(a4) - 862e: 656d lui a0,0x1b - 8630: 6972702f 0x6972702f - 8634: 6179 addi sp,sp,464 - 8636: 7665642f 0x7665642f - 863a: 7369722f 0x7369722f - 863e: 765f7663 bgeu t5,t0,8daa <_start-0x7fff7256> - 8642: 6365 lui t1,0x19 - 8644: 7369722f 0x7369722f - 8648: 672d7663 bgeu s10,s2,8cb4 <_start-0x7fff734c> - 864c: 756e flw fa0,248(sp) - 864e: 7369722f 0x7369722f - 8652: 32337663 bgeu t1,gp,897e <_start-0x7fff7682> - 8656: 752d lui a0,0xfffeb - 8658: 6b6e flw fs6,216(sp) - 865a: 6f6e flw ft10,216(sp) - 865c: 652d6e77 0x652d6e77 - 8660: 666c flw fa1,76(a2) - 8662: 636e692f vamoandw.v zero,v22,(t3),v18 - 8666: 756c flw fa1,108(a0) - 8668: 6564 flw fs1,76(a0) - 866a: 2e00 fld fs0,24(a2) - 866c: 2f2e fld ft10,200(sp) - 866e: 2e2e fld ft8,200(sp) - 8670: 2f2e2e2f 0x2f2e2e2f - 8674: 2e2e fld ft8,200(sp) - 8676: 7369722f 0x7369722f - 867a: 672d7663 bgeu s10,s2,8ce6 <_start-0x7fff731a> - 867e: 6c2f6363 bltu t5,sp,8d44 <_start-0x7fff72bc> - 8682: 6269 lui tp,0x1a - 8684: 2f636367 0x2f636367 - 8688: 2e2e fld ft8,200(sp) - 868a: 636e692f vamoandw.v zero,v22,(t3),v18 - 868e: 756c flw fa1,108(a0) - 8690: 6564 flw fs1,76(a0) - 8692: 2e00 fld fs0,24(a2) - 8694: 2f2e fld ft10,200(sp) - 8696: 2e2e fld ft8,200(sp) - 8698: 2f2e2e2f 0x2f2e2e2f - 869c: 2e2e fld ft8,200(sp) - 869e: 7369722f 0x7369722f - 86a2: 672d7663 bgeu s10,s2,8d0e <_start-0x7fff72f2> - 86a6: 6c2f6363 bltu t5,sp,8d6c <_start-0x7fff7294> - 86aa: 6269 lui tp,0x1a - 86ac: 2f636367 0x2f636367 - 86b0: 2e2e fld ft8,200(sp) - 86b2: 6363672f vamoandw.v zero,v22,(t1),v14 - 86b6: 6e6f632f 0x6e6f632f - 86ba: 6966 flw fs2,88(sp) - 86bc: 69722f67 0x69722f67 - 86c0: 00766373 csrrsi t1,0x7,12 - 86c4: 2e2e fld ft8,200(sp) - 86c6: 2f2e2e2f 0x2f2e2e2f - 86ca: 2f2e fld ft10,200(sp) - 86cc: 00636367 0x636367 - 86d0: 2e2e fld ft8,200(sp) - 86d2: 2f2e2e2f 0x2f2e2e2f - 86d6: 2e2e fld ft8,200(sp) - 86d8: 2f2e2e2f 0x2f2e2e2f - 86dc: 6972 flw fs2,28(sp) - 86de: 2d766373 csrrsi t1,0x2d7,12 - 86e2: 2f636367 0x2f636367 - 86e6: 696c flw fa1,84(a0) - 86e8: 6762 flw fa4,24(sp) - 86ea: 00006363 bltu zero,zero,86f0 <_start-0x7fff7910> - 86ee: 6f6c flw fa1,92(a4) - 86f0: 682e6b63 bltu t3,sp,8d86 <_start-0x7fff727a> - 86f4: 0100 addi s0,sp,128 - 86f6: 0000 unimp - 86f8: 745f 7079 7365 0x73657079745f - 86fe: 682e flw fa6,200(sp) - 8700: 0100 addi s0,sp,128 - 8702: 0000 unimp - 8704: 64647473 csrrci s0,0x646,8 - 8708: 6665 lui a2,0x19 - 870a: 682e flw fa6,200(sp) - 870c: 0200 addi s0,sp,256 - 870e: 0000 unimp - 8710: 6572 flw fa0,28(sp) - 8712: 6e65 lui t3,0x19 - 8714: 2e74 fld fa3,216(a2) - 8716: 0068 addi a0,sp,12 - 8718: 0001 nop - 871a: 6500 flw fs0,8(a0) - 871c: 7272 flw ft4,60(sp) - 871e: 6f6e flw ft10,216(sp) - 8720: 682e flw fa6,200(sp) - 8722: 0100 addi s0,sp,128 - 8724: 0000 unimp - 8726: 6c647473 csrrci s0,0x6c6,8 - 872a: 6269 lui tp,0x1a - 872c: 682e flw fa6,200(sp) - 872e: 0300 addi s0,sp,384 - 8730: 0000 unimp - 8732: 6e75 lui t3,0x1d - 8734: 7369 lui t1,0xffffa - 8736: 6474 flw fa3,76(s0) - 8738: 682e flw fa6,200(sp) - 873a: 0100 addi s0,sp,128 - 873c: 0000 unimp - 873e: 6974 flw fa3,84(a0) - 8740: 656d lui a0,0x1b - 8742: 682e flw fa6,200(sp) - 8744: 0300 addi s0,sp,384 - 8746: 0000 unimp - 8748: 6168 flw fa0,68(a0) - 874a: 61746873 csrrsi a6,0x617,8 - 874e: 2e62 fld ft8,24(sp) - 8750: 0068 addi a0,sp,12 - 8752: 0004 0x4 - 8754: 7200 flw fs0,32(a2) - 8756: 7369 lui t1,0xffffa - 8758: 6f2d7663 bgeu s10,s2,8e44 <_start-0x7fff71bc> - 875c: 7470 flw fa2,108(s0) - 875e: 00682e73 csrrs t3,0x6,a6 - 8762: 0005 c.nop 1 - 8764: 6900 flw fs0,16(a0) - 8766: 736e flw ft6,248(sp) - 8768: 2d6e fld fs10,216(sp) - 876a: 736e6f63 bltu t3,s6,8ea8 <_start-0x7fff7158> - 876e: 6174 flw fa3,68(a0) - 8770: 746e flw fs0,248(sp) - 8772: 00682e73 csrrs t3,0x6,a6 - 8776: 0006 c.slli zero,0x1 - 8778: 6c00 flw fs0,24(s0) - 877a: 6269 lui tp,0x1a - 877c: 32636367 0x32636367 - 8780: 682e flw fa6,200(sp) - 8782: 0700 addi s0,sp,896 - 8784: 0000 unimp - 8786: 696c flw fa1,84(a0) - 8788: 6762 flw fa4,24(sp) - 878a: 2e326363 bltu tp,gp,8a70 <_start-0x7fff7590> - 878e: 00070063 beqz a4,878e <_start-0x7fff7872> - 8792: 0000 unimp - 8794: 0298 addi a4,sp,320 - 8796: 0000 unimp - 8798: 02100003 lb zero,33(zero) # 21 <_start-0x7fffffdf> - 879c: 0000 unimp - 879e: 0101 addi sp,sp,0 - 87a0: 000d0efb 0xd0efb - 87a4: 0101 addi sp,sp,0 - 87a6: 0101 addi sp,sp,0 - 87a8: 0000 unimp - 87aa: 0100 addi s0,sp,128 - 87ac: 0000 unimp - 87ae: 2e01 jal 8abe <_start-0x7fff7542> - 87b0: 2f2e fld ft10,200(sp) - 87b2: 2e2e fld ft8,200(sp) - 87b4: 2f2e2e2f 0x2f2e2e2f - 87b8: 2e2e fld ft8,200(sp) - 87ba: 7369722f 0x7369722f - 87be: 672d7663 bgeu s10,s2,8e2a <_start-0x7fff71d6> - 87c2: 6c2f6363 bltu t5,sp,8e88 <_start-0x7fff7178> - 87c6: 6269 lui tp,0x1a - 87c8: 00636367 0x636367 - 87cc: 6d6f682f 0x6d6f682f - 87d0: 2f65 jal 8f88 <_start-0x7fff7078> - 87d2: 7270 flw fa2,100(a2) - 87d4: 7969 lui s2,0xffffa - 87d6: 2f61 jal 8f6e <_start-0x7fff7092> - 87d8: 6564 flw fs1,76(a0) - 87da: 2f76 fld ft10,344(sp) - 87dc: 6972 flw fs2,28(sp) - 87de: 5f766373 csrrsi t1,0x5f7,12 - 87e2: 6576 flw fa0,92(sp) - 87e4: 69722f63 0x69722f63 - 87e8: 2d766373 csrrsi t1,0x2d7,12 - 87ec: 2f756e67 0x2f756e67 - 87f0: 6972 flw fs2,28(sp) - 87f2: 33766373 csrrsi t1,mhpmevent23,12 - 87f6: 2d32 fld fs10,264(sp) - 87f8: 6e75 lui t3,0x1d - 87fa: 776f6e6b 0x776f6e6b - 87fe: 2d6e fld fs10,216(sp) - 8800: 6c65 lui s8,0x19 - 8802: 2f66 fld ft10,88(sp) - 8804: 6e69 lui t3,0x1a - 8806: 64756c63 bltu a0,t2,8e5e <_start-0x7fff71a2> - 880a: 2f65 jal 8fc2 <_start-0x7fff703e> - 880c: 00737973 csrrci s2,0x7,6 - 8810: 6d6f682f 0x6d6f682f - 8814: 2f65 jal 8fcc <_start-0x7fff7034> - 8816: 7270 flw fa2,100(a2) - 8818: 7969 lui s2,0xffffa - 881a: 2f61 jal 8fb2 <_start-0x7fff704e> - 881c: 6544 flw fs1,12(a0) - 881e: 6f746b73 csrrsi s6,0x6f7,8 - 8822: 2f70 fld fa2,216(a4) - 8824: 6972 flw fs2,28(sp) - 8826: 2d766373 csrrsi t1,0x2d7,12 - 882a: 2d756e67 0x2d756e67 - 882e: 6f74 flw fa3,92(a4) - 8830: 68636c6f jal s8,3eeb6 <_start-0x7ffc114a> - 8834: 6961 lui s2,0x18 - 8836: 2f6e fld ft10,216(sp) - 8838: 7562 flw fa0,56(sp) - 883a: 6c69 lui s8,0x1a - 883c: 2f64 fld fs1,216(a4) - 883e: 7562 flw fa0,56(sp) - 8840: 6c69 lui s8,0x1a - 8842: 2d64 fld fs1,216(a0) - 8844: 2d636367 0x2d636367 - 8848: 656e flw fa0,216(sp) - 884a: 62696c77 0x62696c77 - 884e: 732d lui t1,0xfffeb - 8850: 6174 flw fa3,68(a0) - 8852: 2f326567 0x2f326567 - 8856: 2f636367 0x2f636367 - 885a: 6e69 lui t3,0x1a - 885c: 64756c63 bltu a0,t2,8eb4 <_start-0x7fff714c> - 8860: 0065 c.nop 25 - 8862: 6d6f682f 0x6d6f682f - 8866: 2f65 jal 901e <_start-0x7fff6fe2> - 8868: 7270 flw fa2,100(a2) - 886a: 7969 lui s2,0xffffa - 886c: 2f61 jal 9004 <_start-0x7fff6ffc> - 886e: 6564 flw fs1,76(a0) - 8870: 2f76 fld ft10,344(sp) - 8872: 6972 flw fs2,28(sp) - 8874: 5f766373 csrrsi t1,0x5f7,12 - 8878: 6576 flw fa0,92(sp) - 887a: 69722f63 0x69722f63 - 887e: 2d766373 csrrsi t1,0x2d7,12 - 8882: 2f756e67 0x2f756e67 - 8886: 6972 flw fs2,28(sp) - 8888: 33766373 csrrsi t1,mhpmevent23,12 - 888c: 2d32 fld fs10,264(sp) - 888e: 6e75 lui t3,0x1d - 8890: 776f6e6b 0x776f6e6b - 8894: 2d6e fld fs10,216(sp) - 8896: 6c65 lui s8,0x19 - 8898: 2f66 fld ft10,88(sp) - 889a: 6e69 lui t3,0x1a - 889c: 64756c63 bltu a0,t2,8ef4 <_start-0x7fff710c> - 88a0: 0065 c.nop 25 - 88a2: 2e2e fld ft8,200(sp) - 88a4: 2f2e2e2f 0x2f2e2e2f - 88a8: 2e2e fld ft8,200(sp) - 88aa: 2f2e2e2f 0x2f2e2e2f - 88ae: 6972 flw fs2,28(sp) - 88b0: 2d766373 csrrsi t1,0x2d7,12 - 88b4: 2f636367 0x2f636367 - 88b8: 696c flw fa1,84(a0) - 88ba: 6762 flw fa4,24(sp) - 88bc: 2e2f6363 bltu t5,sp,8ba2 <_start-0x7fff745e> - 88c0: 2f2e fld ft10,200(sp) - 88c2: 6e69 lui t3,0x1a - 88c4: 64756c63 bltu a0,t2,8f1c <_start-0x7fff70e4> - 88c8: 0065 c.nop 25 - 88ca: 2e2e fld ft8,200(sp) - 88cc: 2f2e2e2f 0x2f2e2e2f - 88d0: 2e2e fld ft8,200(sp) - 88d2: 2f2e2e2f 0x2f2e2e2f - 88d6: 6972 flw fs2,28(sp) - 88d8: 2d766373 csrrsi t1,0x2d7,12 - 88dc: 2f636367 0x2f636367 - 88e0: 696c flw fa1,84(a0) - 88e2: 6762 flw fa4,24(sp) - 88e4: 2e2f6363 bltu t5,sp,8bca <_start-0x7fff7436> - 88e8: 2f2e fld ft10,200(sp) - 88ea: 2f636367 0x2f636367 - 88ee: 666e6f63 bltu t3,t1,8f6c <_start-0x7fff7094> - 88f2: 6769 lui a4,0x1a - 88f4: 7369722f 0x7369722f - 88f8: 2e007663 bgeu zero,zero,8be4 <_start-0x7fff741c> - 88fc: 2f2e fld ft10,200(sp) - 88fe: 2e2e fld ft8,200(sp) - 8900: 672f2e2f amoand.w.aqrl t3,s2,(t5) - 8904: 00006363 bltu zero,zero,890a <_start-0x7fff76f6> - 8908: 696c flw fa1,84(a0) - 890a: 6762 flw fa4,24(sp) - 890c: 2e326363 bltu tp,gp,8bf2 <_start-0x7fff740e> - 8910: 00010063 beqz sp,8910 <_start-0x7fff76f0> - 8914: 6c00 flw fs0,24(s0) - 8916: 2e6b636f jal t1,bebfc <_start-0x7ff41404> - 891a: 0068 addi a0,sp,12 - 891c: 0002 c.slli64 zero - 891e: 5f00 lw s0,56(a4) - 8920: 7974 flw fa3,116(a0) - 8922: 6570 flw fa2,76(a0) - 8924: 00682e73 csrrs t3,0x6,a6 - 8928: 0002 c.slli64 zero - 892a: 7300 flw fs0,32(a4) - 892c: 6474 flw fa3,76(s0) - 892e: 6564 flw fs1,76(a0) - 8930: 2e66 fld ft8,88(sp) - 8932: 0068 addi a0,sp,12 - 8934: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> - 8938: 6565 lui a0,0x19 - 893a: 746e flw fs0,248(sp) - 893c: 682e flw fa6,200(sp) - 893e: 0200 addi s0,sp,256 - 8940: 0000 unimp - 8942: 7265 lui tp,0xffff9 - 8944: 6e72 flw ft8,28(sp) - 8946: 00682e6f jal t3,8a94c <_start-0x7ff756b4> - 894a: 0002 c.slli64 zero - 894c: 7300 flw fs0,32(a4) - 894e: 6474 flw fa3,76(s0) - 8950: 696c flw fa1,84(a0) - 8952: 2e62 fld ft8,24(sp) - 8954: 0068 addi a0,sp,12 - 8956: 0004 0x4 - 8958: 7500 flw fs0,40(a0) - 895a: 696e flw fs2,216(sp) - 895c: 2e647473 csrrci s0,0x2e6,8 - 8960: 0068 addi a0,sp,12 - 8962: 0002 c.slli64 zero - 8964: 7400 flw fs0,40(s0) - 8966: 6d69 lui s10,0x1a - 8968: 2e65 jal 8d20 <_start-0x7fff72e0> - 896a: 0068 addi a0,sp,12 - 896c: 0004 0x4 - 896e: 6800 flw fs0,16(s0) - 8970: 7361 lui t1,0xffff8 - 8972: 7468 flw fa0,108(s0) - 8974: 6261 lui tp,0x18 - 8976: 682e flw fa6,200(sp) - 8978: 0500 addi s0,sp,640 - 897a: 0000 unimp - 897c: 6972 flw fs2,28(sp) - 897e: 2d766373 csrrsi t1,0x2d7,12 - 8982: 7374706f j 508b8 <_start-0x7ffaf748> - 8986: 682e flw fa6,200(sp) - 8988: 0600 addi s0,sp,768 - 898a: 0000 unimp - 898c: 6e69 lui t3,0x1a - 898e: 632d6e73 csrrsi t3,0x632,26 - 8992: 74736e6f jal t3,3f8d8 <_start-0x7ffc0728> - 8996: 6e61 lui t3,0x18 - 8998: 7374 flw fa3,100(a4) - 899a: 682e flw fa6,200(sp) - 899c: 0700 addi s0,sp,896 - 899e: 0000 unimp - 89a0: 696c flw fa1,84(a0) - 89a2: 6762 flw fa4,24(sp) - 89a4: 2e326363 bltu tp,gp,8c8a <_start-0x7fff7376> - 89a8: 0068 addi a0,sp,12 - 89aa: 0001 nop - 89ac: 0000 unimp - 89ae: 0105 addi sp,sp,1 - 89b0: 0500 addi s0,sp,640 - 89b2: fc02 fsw ft0,56(sp) - 89b4: 0144 addi s1,sp,132 - 89b6: 0380 addi s0,sp,448 - 89b8: 05c2 slli a1,a1,0x10 - 89ba: 0501 addi a0,a0,0 - 89bc: 09010303 lb t1,144(sp) - 89c0: 0000 unimp - 89c2: 0301 addi t1,t1,0 - 89c4: 0902 c.slli64 s2 - 89c6: 0000 unimp - 89c8: 0301 addi t1,t1,0 - 89ca: 0900 addi s0,sp,144 - 89cc: 0000 unimp - 89ce: 0301 addi t1,t1,0 - 89d0: 0900 addi s0,sp,144 - 89d2: 0000 unimp - 89d4: 0301 addi t1,t1,0 - 89d6: 0900 addi s0,sp,144 - 89d8: 0000 unimp - 89da: 0301 addi t1,t1,0 - 89dc: 0900 addi s0,sp,144 - 89de: 0000 unimp - 89e0: 0001 nop - 89e2: 0402 c.slli64 s0 - 89e4: 00030603 lb a2,0(t1) # ffff8000 <__BSS_END__+0x7ffe1288> - 89e8: 0809 addi a6,a6,2 - 89ea: 0100 addi s0,sp,128 - 89ec: 0200 addi s0,sp,256 - 89ee: 0e04 addi s1,sp,784 - 89f0: 0306 slli t1,t1,0x1 - 89f2: 0900 addi s0,sp,144 - 89f4: 000c 0xc - 89f6: 0001 nop - 89f8: 0402 c.slli64 s0 - 89fa: 030e slli t1,t1,0x3 - 89fc: 0902 c.slli64 s2 - 89fe: 0000 unimp - 8a00: 0001 nop - 8a02: 0402 c.slli64 s0 - 8a04: 060e slli a2,a2,0x3 - 8a06: 00097e03 0x97e03 - 8a0a: 0100 addi s0,sp,128 - 8a0c: 0105 addi sp,sp,1 - 8a0e: 0200 addi s0,sp,256 - 8a10: 0e04 addi s1,sp,784 - 8a12: 1c090303 lb t1,448(s2) # ffffa1c0 <__BSS_END__+0x7ffe3448> - 8a16: 0100 addi s0,sp,128 - 8a18: 0305 addi t1,t1,1 - 8a1a: 0200 addi s0,sp,256 - 8a1c: 0404 addi s1,sp,512 - 8a1e: 08097d03 0x8097d03 - 8a22: 0100 addi s0,sp,128 - 8a24: 0c090003 lb zero,192(s2) - 8a28: 0100 addi s0,sp,128 - 8a2a: 0809 addi a6,a6,2 - 8a2c: 0000 unimp - 8a2e: 0101 addi sp,sp,0 - -Disassembly of section .debug_frame: - -00000000 <.debug_frame>: - 0: 000c 0xc - 2: 0000 unimp - 4: ffff 0xffff - 6: ffff 0xffff - 8: 0001 nop - a: 7c01 lui s8,0xfffe0 - c: 0d01 addi s10,s10,0 - e: 0002 c.slli64 zero - 10: 0040 addi s0,sp,4 - 12: 0000 unimp - 14: 0000 unimp - 16: 0000 unimp - 18: 07e8 addi a0,sp,972 - 1a: 8001 c.srli64 s0 - 1c: 06c8 addi a0,sp,836 - 1e: 0000 unimp - 20: 0e44 addi s1,sp,788 - 22: 5830 lw a2,112(s0) - 24: 0389 addi t2,t2,2 - 26: 06940593 addi a1,s0,105 # fffeb069 <__BSS_END__+0x7ffd42f1> - 2a: 0896 slli a7,a7,0x5 - 2c: 81540997 auipc s3,0x81540 - 30: 8801 andi s0,s0,0 - 32: 9202 jalr tp - 34: 9504 0x9504 - 36: 050c0307 0x50c0307 - 3a: c10a sw sp,128(sp) - 3c: c844 sw s1,20(s0) - 3e: c954 sw a3,20(a0) - 40: d244 sw s1,36(a2) - 42: d344 sw s1,36(a4) - 44: d444 sw s1,44(s0) - 46: d544 sw s1,44(a0) - 48: d644 sw s1,44(a2) - 4a: d744 sw s1,44(a4) - 4c: 0e4c addi a1,sp,788 - 4e: 4400 lw s0,8(s0) - 50: 0000000b 0xb - 54: 000c 0xc - 56: 0000 unimp - 58: ffff 0xffff - 5a: ffff 0xffff - 5c: 0001 nop - 5e: 7c01 lui s8,0xfffe0 - 60: 0d01 addi s10,s10,0 - 62: 0002 c.slli64 zero - 64: 0040 addi s0,sp,4 - 66: 0000 unimp - 68: 0054 addi a3,sp,4 - 6a: 0000 unimp - 6c: 0eb0 addi a2,sp,856 - 6e: 8001 c.srli64 s0 - 70: 05b8 addi a4,sp,712 - 72: 0000 unimp - 74: 0e44 addi s1,sp,788 - 76: 4430 lw a2,72(s0) - 78: 88580593 addi a1,a6,-1915 - 7c: 8902 jr s2 - 7e: 95069403 lh s0,-1712(a3) # 6cf0 <_start-0x7fff9310> - 82: 50089607 0x50089607 - 86: 0181 addi gp,gp,0 - 88: 0492 slli s1,s1,0x4 - 8a: 30030997 auipc s3,0x30030 - 8e: 0a04 addi s1,sp,272 - 90: 44c1 li s1,16 - 92: 44c8 lw a0,12(s1) - 94: 44c9 li s1,18 - 96: 44d2 lw s1,20(sp) - 98: 44d444d3 0x44d444d3 - 9c: 44d5 li s1,21 - 9e: 44d6 lw s1,84(sp) - a0: 000e4cd7 vadd.vx v25,v0,t3,v0.t - a4: 0b44 addi s1,sp,404 - a6: 0000 unimp - a8: 000c 0xc - aa: 0000 unimp - ac: ffff 0xffff - ae: ffff 0xffff - b0: 0001 nop - b2: 7c01 lui s8,0xfffe0 - b4: 0d01 addi s10,s10,0 - b6: 0002 c.slli64 zero - b8: 0018 0x18 - ba: 0000 unimp - bc: 00a8 addi a0,sp,72 - be: 0000 unimp - c0: 1468 addi a0,sp,556 - c2: 8001 c.srli64 s0 - c4: 00cc addi a1,sp,68 - c6: 0000 unimp - c8: 0e78 addi a4,sp,796 - ca: 0210 addi a2,sp,256 - cc: 0a88 addi a0,sp,336 - ce: 000e c.slli zero,0x3 - d0: 0b44 addi s1,sp,404 - d2: 0000 unimp - d4: 000c 0xc - d6: 0000 unimp - d8: ffff 0xffff - da: ffff 0xffff - dc: 0001 nop - de: 7c01 lui s8,0xfffe0 - e0: 0d01 addi s10,s10,0 - e2: 0002 c.slli64 zero - e4: 0018 0x18 - e6: 0000 unimp - e8: 00d4 addi a3,sp,68 - ea: 0000 unimp - ec: 1534 addi a3,sp,680 - ee: 8001 c.srli64 s0 - f0: 0144 addi s1,sp,132 - f2: 0000 unimp - f4: 4002 0x4002 - f6: 100e c.slli zero,0x23 - f8: 9002 ebreak - fa: 0e0a slli t3,t3,0x2 - fc: 4400 lw s0,8(s0) - fe: 000c000b 0xc000b - 102: 0000 unimp - 104: ffff 0xffff - 106: ffff 0xffff - 108: 0001 nop - 10a: 7c01 lui s8,0xfffe0 - 10c: 0d01 addi s10,s10,0 - 10e: 0002 c.slli64 zero - 110: 0018 0x18 - 112: 0000 unimp - 114: 0100 addi s0,sp,128 - 116: 0000 unimp - 118: 1678 addi a4,sp,812 - 11a: 8001 c.srli64 s0 - 11c: 0144 addi s1,sp,132 - 11e: 0000 unimp - 120: 4002 0x4002 - 122: 100e c.slli zero,0x23 - 124: 9002 ebreak - 126: 0e0a slli t3,t3,0x2 - 128: 4400 lw s0,8(s0) - 12a: 000c000b 0xc000b - 12e: 0000 unimp - 130: ffff 0xffff - 132: ffff 0xffff - 134: 0001 nop - 136: 7c01 lui s8,0xfffe0 - 138: 0d01 addi s10,s10,0 - 13a: 0002 c.slli64 zero - 13c: 0050 addi a2,sp,4 - 13e: 0000 unimp - 140: 012c addi a1,sp,136 - 142: 0000 unimp - 144: 17bc addi a5,sp,1000 - 146: 8001 c.srli64 s0 - 148: 1008 addi a0,sp,32 - 14a: 0000 unimp - 14c: 0e44 addi s1,sp,788 - 14e: 01c0 addi s0,sp,196 - 150: 9344 0x9344 - 152: 6805 lui a6,0x1 - 154: 0492 slli s1,s1,0x4 - 156: 0694 addi a3,sp,832 - 158: 0795 addi a5,a5,5 - 15a: 0896 slli a7,a7,0x5 - 15c: 895c 0x895c - 15e: 01816803 0x1816803 - 162: 0288 addi a0,sp,320 - 164: 0a980997 auipc s3,0xa980 - 168: 0b99 addi s7,s7,6 - 16a: 0c9a slli s9,s9,0x6 - 16c: 64030d9b 0x64030d9b - 170: 0a0c addi a1,sp,272 - 172: 44c1 li s1,16 - 174: 50c8 lw a0,36(s1) - 176: 4cc9 li s9,18 - 178: 44d2 lw s1,20(sp) - 17a: 44d448d3 0x44d448d3 - 17e: 44d5 li s1,21 - 180: 44d6 lw s1,84(sp) - 182: 44d844d7 0x44d844d7 - 186: 44d9 li s1,22 - 188: 44da lw s1,148(sp) - 18a: 000e48db 0xe48db - 18e: 0b44 addi s1,sp,404 - 190: 000c 0xc - 192: 0000 unimp - 194: ffff 0xffff - 196: ffff 0xffff - 198: 0001 nop - 19a: 7c01 lui s8,0xfffe0 - 19c: 0d01 addi s10,s10,0 - 19e: 0002 c.slli64 zero - 1a0: 0038 addi a4,sp,8 - 1a2: 0000 unimp - 1a4: 0190 addi a2,sp,192 - 1a6: 0000 unimp - 1a8: 27c4 fld fs1,136(a5) - 1aa: 8001 c.srli64 s0 - 1ac: 1520 addi s0,sp,680 - 1ae: 0000 unimp - 1b0: 0e44 addi s1,sp,788 - 1b2: 4860 lw s0,84(s0) - 1b4: 0492 slli s1,s1,0x4 - 1b6: 894c 0x894c - 1b8: 02886c03 0x2886c03 - 1bc: 8158 0x8158 - 1be: 9301 srli a4,a4,0x20 - 1c0: 9405 srai s0,s0,0x21 - 1c2: 9506 add a0,a0,ra - 1c4: 05800307 0x5800307 - 1c8: c10a sw sp,128(sp) - 1ca: c844 sw s1,20(s0) - 1cc: d24c sw a1,36(a2) - 1ce: c944 sw s1,20(a0) - 1d0: d344 sw s1,36(a4) - 1d2: d444 sw s1,44(s0) - 1d4: d544 sw s1,44(a0) - 1d6: 0e44 addi s1,sp,788 - 1d8: 4400 lw s0,8(s0) - 1da: 000c000b 0xc000b - 1de: 0000 unimp - 1e0: ffff 0xffff - 1e2: ffff 0xffff - 1e4: 0001 nop - 1e6: 7c01 lui s8,0xfffe0 - 1e8: 0d01 addi s10,s10,0 - 1ea: 0002 c.slli64 zero - 1ec: 0018 0x18 - 1ee: 0000 unimp - 1f0: 01dc addi a5,sp,196 - 1f2: 0000 unimp - 1f4: 3ce4 fld fs1,248(s1) - 1f6: 8001 c.srli64 s0 - 1f8: 0150 addi a2,sp,132 - 1fa: 0000 unimp - 1fc: 0e54 addi a3,sp,788 - 1fe: 0220 addi s0,sp,264 - 200: 0a54 addi a3,sp,276 - 202: 000e c.slli zero,0x3 - 204: 0b44 addi s1,sp,404 - 206: 0000 unimp - 208: 000c 0xc - 20a: 0000 unimp - 20c: ffff 0xffff - 20e: ffff 0xffff - 210: 0001 nop - 212: 7c01 lui s8,0xfffe0 - 214: 0d01 addi s10,s10,0 - 216: 0002 c.slli64 zero - 218: 0028 addi a0,sp,8 - 21a: 0000 unimp - 21c: 0208 addi a0,sp,256 - 21e: 0000 unimp - 220: 3e34 fld fa3,120(a2) - 222: 8001 c.srli64 s0 - 224: 0188 addi a0,sp,192 - 226: 0000 unimp - 228: 0e44 addi s1,sp,788 - 22a: 5030 lw a2,96(s0) - 22c: 0389 addi t2,t2,2 - 22e: 0181 addi gp,gp,0 - 230: 0288 addi a0,sp,320 - 232: 0492 slli s1,s1,0x4 - 234: 0a012c03 lw s8,160(sp) - 238: 44c1 li s1,16 - 23a: 60c8 flw fa0,4(s1) - 23c: 44d2 lw s1,20(sp) - 23e: 44c9 li s1,18 - 240: 000e c.slli zero,0x3 - 242: 0b44 addi s1,sp,404 - 244: 000c 0xc - 246: 0000 unimp - 248: ffff 0xffff - 24a: ffff 0xffff - 24c: 0001 nop - 24e: 7c01 lui s8,0xfffe0 - 250: 0d01 addi s10,s10,0 - 252: 0002 c.slli64 zero - 254: 0024 addi s1,sp,8 - 256: 0000 unimp - 258: 0244 addi s1,sp,260 - 25a: 0000 unimp - 25c: 3fbc fld fa5,120(a5) - 25e: 8001 c.srli64 s0 - 260: 020c addi a1,sp,256 - 262: 0000 unimp - 264: 0e50 addi a2,sp,788 - 266: 5430 lw a2,104(s0) - 268: 0288 addi a0,sp,320 - 26a: 0389 addi t2,t2,2 - 26c: 0181 addi gp,gp,0 - 26e: a002 fsd ft0,0(sp) - 270: c10a sw sp,128(sp) - 272: c844 sw s1,20(s0) - 274: c950 sw a2,20(a0) - 276: 0e44 addi s1,sp,788 - 278: 4400 lw s0,8(s0) - 27a: 000c000b 0xc000b - 27e: 0000 unimp - 280: ffff 0xffff - 282: ffff 0xffff - 284: 0001 nop - 286: 7c01 lui s8,0xfffe0 - 288: 0d01 addi s10,s10,0 - 28a: 0002 c.slli64 zero - 28c: 0018 0x18 - 28e: 0000 unimp - 290: 027c addi a5,sp,268 - 292: 0000 unimp - 294: 41c8 lw a0,4(a1) - 296: 8001 c.srli64 s0 - 298: 0334 addi a3,sp,392 - 29a: 0000 unimp - 29c: 0e50 addi a2,sp,788 - 29e: 0320 addi s0,sp,392 - 2a0: 030c addi a1,sp,384 - 2a2: 0e0a slli t3,t3,0x2 - 2a4: 4400 lw s0,8(s0) - 2a6: 000c000b 0xc000b - 2aa: 0000 unimp - 2ac: ffff 0xffff - 2ae: ffff 0xffff - 2b0: 0001 nop - 2b2: 7c01 lui s8,0xfffe0 - 2b4: 0d01 addi s10,s10,0 - 2b6: 0002 c.slli64 zero - 2b8: 000c 0xc - 2ba: 0000 unimp - 2bc: 02a8 addi a0,sp,328 - 2be: 0000 unimp - 2c0: 44fc lw a5,76(s1) - 2c2: 8001 c.srli64 s0 - 2c4: 004c addi a1,sp,4 - ... - -Disassembly of section .debug_str: - -00000000 <.debug_str>: - 0: 726f6873 csrrsi a6,0x726,30 - 4: 2074 fld fa3,192(s0) - 6: 6e69 lui t3,0x1a - 8: 0074 addi a3,sp,12 - a: 7468 flw fa0,108(s0) - c: 6261 lui tp,0x18 - e: 685f 7361 5f68 0x5f687361685f - 14: 6f70 flw fa2,92(a4) - 16: 6e69 lui t3,0x1a - 18: 6574 flw fa3,76(a0) - 1a: 0072 c.slli zero,0x1c - 1c: 725f 6e61 3464 0x34646e61725f - 22: 0038 addi a4,sp,8 - 24: 655f 656d 6772 0x6772656d655f - 2a: 6e65 lui t3,0x19 - 2c: 5f007963 bgeu zero,a6,61e <_start-0x7ffff9e2> - 30: 6164 flw fs1,68(a0) - 32: 6c79 lui s8,0x1e - 34: 6769 lui a4,0x1a - 36: 7468 flw fa0,108(s0) - 38: 6300 flw fs0,0(a4) - 3a: 6c706d6f jal s10,6f00 <_start-0x7fff9100> - 3e: 7865 lui a6,0xffff9 - 40: 6420 flw fs0,72(s0) - 42: 6c62756f jal a0,27708 <_start-0x7ffd88f8> - 46: 0065 c.nop 25 - 48: 675f 7465 6164 0x61647465675f - 4e: 6574 flw fa3,76(a0) - 50: 655f 7272 5f00 0x5f007272655f - 56: 6164 flw fs1,68(a0) - 58: 6174 flw fa3,68(a0) - 5a: 5f00 lw s0,56(a4) - 5c: 74726377 0x74726377 - 60: 5f626d6f jal s10,26656 <_start-0x7ffd99aa> - 64: 74617473 csrrci s0,0x746,2 - 68: 0065 c.nop 25 - 6a: 775f 7363 7472 0x74727363775f - 70: 73626d6f jal s10,267a6 <_start-0x7ffd985a> - 74: 735f 6174 6574 0x65746174735f - 7a: 5f00 lw s0,56(a4) - 7c: 645f 0030 5f5f 0x5f5f0030645f - 82: 3164 fld fs1,224(a0) - 84: 5f00 lw s0,56(a4) - 86: 626c flw fa1,68(a2) - 88: 7366 flw ft6,120(sp) - 8a: 7a69 lui s4,0xffffa - 8c: 0065 c.nop 25 - 8e: 6974706f j 47f24 <_start-0x7ffb80dc> - 92: 646e flw fs0,216(sp) - 94: 6300 flw fs0,0(a4) - 96: 6c706d6f jal s10,6f5c <_start-0x7fff90a4> - 9a: 7865 lui a6,0xffff9 - 9c: 6c20 flw fs0,88(s0) - 9e: 20676e6f jal t3,762a4 <_start-0x7ff89d5c> - a2: 6f64 flw fs1,92(a4) - a4: 6275 lui tp,0x1d - a6: 656c flw fa1,76(a0) - a8: 7200 flw fs0,32(a2) - aa: 7369 lui t1,0xffffa - ac: 615f7663 bgeu t5,s5,6b8 <_start-0x7ffff948> - b0: 6962 flw fs2,24(sp) - b2: 5f00 lw s0,56(a4) - b4: 6c5f 636f 6c61 0x6c61636f6c5f - ba: 5f65 li t5,-7 - bc: 0074 addi a3,sp,12 - be: 6d5f 7262 6f74 0x6f7472626d5f - c4: 735f6377 0x735f6377 - c8: 6174 flw fa3,68(a0) - ca: 6574 flw fa3,76(a0) - cc: 5f00 lw s0,56(a4) - ce: 7a74 flw fa3,116(a2) - d0: 616e flw ft2,216(sp) - d2: 656d lui a0,0x1b - d4: 5f00 lw s0,56(a4) - d6: 745f 5f6d 6573 0x65735f6d745f - dc: 635f0063 beq t5,s5,6fc <_start-0x7ffff904> - e0: 6f6c flw fa1,92(a4) - e2: 47006573 csrrsi a0,0x470,0 - e6: 554e lw a0,240(sp) - e8: 4320 lw s0,64(a4) - ea: 3731 jal fffffff6 <__BSS_END__+0x7ffe927e> - ec: 3820 fld fs0,112(s0) - ee: 332e fld ft6,232(sp) - f0: 302e fld ft0,232(sp) - f2: 2d20 fld fs0,88(a0) - f4: 636d lui t1,0x1b - f6: 6f6d lui t5,0x1b - f8: 6564 flw fs1,76(a0) - fa: 3d6c fld fa1,248(a0) - fc: 656d lui a0,0x1b - fe: 6c64 flw fs1,92(s0) - 100: 2d20776f jal a4,73d2 <_start-0x7fff8c2e> - 104: 636d lui t1,0x1b - 106: 6f6d lui t5,0x1b - 108: 6564 flw fs1,76(a0) - 10a: 3d6c fld fa1,248(a0) - 10c: 656d lui a0,0x1b - 10e: 6c64 flw fs1,92(s0) - 110: 2d20776f jal a4,73e2 <_start-0x7fff8c1e> - 114: 746d lui s0,0xffffb - 116: 6e75 lui t3,0x1d - 118: 3d65 jal ffffffd0 <__BSS_END__+0x7ffe9258> - 11a: 6f72 flw ft10,28(sp) - 11c: 74656b63 bltu a0,t1,872 <_start-0x7ffff78e> - 120: 2d20 fld fs0,88(a0) - 122: 616d addi sp,sp,240 - 124: 6372 flw ft6,28(sp) - 126: 3d68 fld fa0,248(a0) - 128: 7672 flw fa2,60(sp) - 12a: 6d693233 0x6d693233 - 12e: 2076 fld ft0,344(sp) - 130: 6d2d lui s10,0xb - 132: 6261 lui tp,0x18 - 134: 3d69 jal ffffffce <__BSS_END__+0x7ffe9256> - 136: 6c69 lui s8,0x1a - 138: 3370 fld fa2,224(a4) - 13a: 2032 fld ft0,264(sp) - 13c: 672d lui a4,0xb - 13e: 2d20 fld fs0,88(a0) - 140: 2d20734f 0x2d20734f - 144: 2d20324f 0x2d20324f - 148: 2d20734f 0x2d20734f - 14c: 6266 flw ft4,88(sp) - 14e: 6975 lui s2,0x1d - 150: 646c flw fa1,76(s0) - 152: 6e69 lui t3,0x1a - 154: 696c2d67 0x696c2d67 - 158: 6762 flw fa4,24(sp) - 15a: 2d206363 bltu zero,s2,420 <_start-0x7ffffbe0> - 15e: 6e66 flw ft8,88(sp) - 160: 74732d6f jal s10,330a6 <_start-0x7ffccf5a> - 164: 6361 lui t1,0x18 - 166: 72702d6b 0x72702d6b - 16a: 6365746f jal s0,577a0 <_start-0x7ffa8860> - 16e: 6f74 flw fa3,92(a4) - 170: 2072 fld ft0,280(sp) - 172: 662d lui a2,0xb - 174: 7865 lui a6,0xffff9 - 176: 74706563 bltu zero,t2,8c0 <_start-0x7ffff740> - 17a: 6f69 lui t5,0x1a - 17c: 736e flw ft6,248(sp) - 17e: 2d20 fld fs0,88(a0) - 180: 6e66 flw ft8,88(sp) - 182: 632d6e6f jal t3,d67b4 <_start-0x7ff2984c> - 186: 6c61 lui s8,0x18 - 188: 2d6c fld fa1,216(a0) - 18a: 7865 lui a6,0xffff9 - 18c: 74706563 bltu zero,t2,8d6 <_start-0x7ffff72a> - 190: 6f69 lui t5,0x1a - 192: 736e flw ft6,248(sp) - 194: 2d20 fld fs0,88(a0) - 196: 7666 flw fa2,120(sp) - 198: 7369 lui t1,0xffffa - 19a: 6269 lui tp,0x1a - 19c: 6c69 lui s8,0x1a - 19e: 7469 lui s0,0xffffa - 1a0: 3d79 jal 3e <_start-0x7fffffc2> - 1a2: 6968 flw fa0,84(a0) - 1a4: 6464 flw fs1,76(s0) - 1a6: 6e65 lui t3,0x19 - 1a8: 5f00 lw s0,56(a4) - 1aa: 6275 lui tp,0x1d - 1ac: 6675 lui a2,0x1d - 1ae: 5f00 lw s0,56(a4) - 1b0: 6162 flw ft2,24(sp) - 1b2: 5f006573 csrrsi a0,0x5f0,0 - 1b6: 745f 5f6d 6f68 0x6f685f6d745f - 1bc: 7275 lui tp,0xffffd - 1be: 5f00 lw s0,56(a4) - 1c0: 6f746377 0x6f746377 - 1c4: 626d lui tp,0x1b - 1c6: 735f 6174 6574 0x65746174735f - 1cc: 5f00 lw s0,56(a4) - 1ce: 735f 0066 6f5f 0x6f5f0066735f - 1d4: 5f6e lw t5,248(sp) - 1d6: 7865 lui a6,0xffff9 - 1d8: 7469 lui s0,0xffffa - 1da: 615f 6772 0073 0x736772615f - 1e0: 635f 6f6f 696b 0x696b6f6f635f - 1e6: 0065 c.nop 25 - 1e8: 5f5f 6773 756c 0x756c67735f5f - 1ee: 0065 c.nop 25 - 1f0: 665f 616c 7367 0x7367616c665f - 1f6: 5f00 lw s0,56(a4) - 1f8: 7369 lui t1,0xffffa - 1fa: 635f 6178 5f00 0x5f006178635f - 200: 00736477 0x736477 - 204: 5f5f 4946 454c 0x454c49465f5f - 20a: 5f00 lw s0,56(a4) - 20c: 6572 flw fa0,28(sp) - 20e: 746c7573 csrrci a0,0x746,24 - 212: 6b5f 5500 4953 0x495355006b5f - 218: 7974 flw fa3,116(a0) - 21a: 6570 flw fa2,76(a0) - 21c: 6c00 flw fs0,24(s0) - 21e: 20676e6f jal t3,76424 <_start-0x7ff89bdc> - 222: 6f6c flw fa1,92(a4) - 224: 676e flw fa4,216(sp) - 226: 6920 flw fs0,80(a0) - 228: 746e flw fs0,248(sp) - 22a: 5f00 lw s0,56(a4) - 22c: 5f737973 csrrci s2,0x5f7,6 - 230: 7265 lui tp,0xffff9 - 232: 6c72 flw fs8,28(sp) - 234: 7369 lui t1,0xffffa - 236: 0074 addi a3,sp,12 - 238: 635f 7476 7562 0x75627476635f - 23e: 0066 c.slli zero,0x19 - 240: 6d5f 7362 7472 0x747273626d5f - 246: 7363776f jal a4,3797c <_start-0x7ffc8684> - 24a: 735f 6174 6574 0x65746174735f - 250: 5f00 lw s0,56(a4) - 252: 626d lui tp,0x1b - 254: 6c72 flw fs8,28(sp) - 256: 6e65 lui t3,0x19 - 258: 735f 6174 6574 0x65746174735f - 25e: 7200 flw fs0,32(a2) - 260: 7369 lui t1,0xffffa - 262: 635f7663 bgeu t5,s5,88e <_start-0x7ffff772> - 266: 6f6d lui t5,0x1b - 268: 6564 flw fs1,76(a0) - 26a: 006c addi a1,sp,12 - 26c: 665f 616e 6772 0x6772616e665f - 272: 665f0073 0x665f0073 - 276: 736e flw ft6,248(sp) - 278: 5f00 lw s0,56(a4) - 27a: 6e676973 csrrsi s2,0x6e6,14 - 27e: 5f00 lw s0,56(a4) - 280: 65647473 csrrci s0,0x656,8 - 284: 7272 flw ft4,60(sp) - 286: 5f00 lw s0,56(a4) - 288: 6d6d6167 0x6d6d6167 - 28c: 5f61 li t5,-8 - 28e: 6e676973 csrrsi s2,0x6e6,14 - 292: 006d6167 0x6d6167 - 296: 6e5f 616d 6c6c 0x6c6c616d6e5f - 29c: 5f00636f jal t1,688c <_start-0x7fff9774> - 2a0: 6e75 lui t3,0x1d - 2a2: 63657073 csrci 0x636,10 - 2a6: 6669 lui a2,0x1a - 2a8: 6569 lui a0,0x1a - 2aa: 5f64 lw s1,124(a4) - 2ac: 6f6c flw fa1,92(a4) - 2ae: 656c6163 bltu s8,s6,8f0 <_start-0x7ffff710> - 2b2: 695f 666e 006f 0x6f666e695f - 2b8: 5f5f 6d74 7200 0x72006d745f5f - 2be: 7369 lui t1,0xffffa - 2c0: 615f7663 bgeu t5,s5,8cc <_start-0x7ffff734> - 2c4: 6962 flw fs2,24(sp) - 2c6: 745f 7079 0065 0x657079745f - 2cc: 6d5f 7362 6174 0x617473626d5f - 2d2: 6574 flw fa3,76(a0) - 2d4: 5f00 lw s0,56(a4) - 2d6: 775f 6863 0062 0x626863775f - 2dc: 635f 7476 656c 0x656c7476635f - 2e2: 006e c.slli zero,0x1b - 2e4: 665f 6c69 0065 0x656c69665f - 2ea: 6168 flw fa0,68(a0) - 2ec: 61766873 csrrsi a6,0x617,12 - 2f0: 5f6c lw a1,124(a4) - 2f2: 0074 addi a3,sp,12 - 2f4: 5744 lw s1,44(a4) - 2f6: 6e75 lui t3,0x1d - 2f8: 6f69 lui t5,0x1a - 2fa: 006e c.slli zero,0x1b - 2fc: 6d6f682f 0x6d6f682f - 300: 2f65 jal ab8 <_start-0x7ffff548> - 302: 7270 flw fa2,100(a2) - 304: 7969 lui s2,0xffffa - 306: 2f61 jal a9e <_start-0x7ffff562> - 308: 6544 flw fs1,12(a0) - 30a: 6f746b73 csrrsi s6,0x6f7,8 - 30e: 2f70 fld fa2,216(a4) - 310: 6972 flw fs2,28(sp) - 312: 2d766373 csrrsi t1,0x2d7,12 - 316: 2d756e67 0x2d756e67 - 31a: 6f74 flw fa3,92(a4) - 31c: 68636c6f jal s8,369a2 <_start-0x7ffc965e> - 320: 6961 lui s2,0x18 - 322: 2f6e fld ft10,216(sp) - 324: 7562 flw fa0,56(sp) - 326: 6c69 lui s8,0x1a - 328: 2f64 fld fs1,216(a4) - 32a: 7562 flw fa0,56(sp) - 32c: 6c69 lui s8,0x1a - 32e: 2d64 fld fs1,216(a0) - 330: 2d636367 0x2d636367 - 334: 656e flw fa0,216(sp) - 336: 62696c77 0x62696c77 - 33a: 732d lui t1,0xfffeb - 33c: 6174 flw fa3,68(a0) - 33e: 2f326567 0x2f326567 - 342: 6972 flw fs2,28(sp) - 344: 33766373 csrrsi t1,mhpmevent23,12 - 348: 2d32 fld fs10,264(sp) - 34a: 6e75 lui t3,0x1d - 34c: 776f6e6b 0x776f6e6b - 350: 2d6e fld fs10,216(sp) - 352: 6c65 lui s8,0x19 - 354: 2f66 fld ft10,88(sp) - 356: 696c flw fa1,84(a0) - 358: 6762 flw fa4,24(sp) - 35a: 5f006363 bltu zero,a6,940 <_start-0x7ffff6c0> - 35e: 696e flw fs2,216(sp) - 360: 0073626f jal tp,36b66 <_start-0x7ffc949a> - 364: 6f6c flw fa1,92(a4) - 366: 676e flw fa4,216(sp) - 368: 6c20 flw fs0,88(s0) - 36a: 20676e6f jal t3,76570 <_start-0x7ff89a90> - 36e: 6e75 lui t3,0x1d - 370: 6e676973 csrrsi s2,0x6e6,14 - 374: 6465 lui s0,0x19 - 376: 6920 flw fs0,80(a0) - 378: 746e flw fs0,248(sp) - 37a: 4400 lw s0,8(s0) - 37c: 72747357 vsetvli t1,s0,1831 - 380: 6375 lui t1,0x1d - 382: 0074 addi a3,sp,12 - 384: 726f6873 csrrsi a6,0x726,30 - 388: 2074 fld fa3,192(s0) - 38a: 6e75 lui t3,0x1d - 38c: 6e676973 csrrsi s2,0x6e6,14 - 390: 6465 lui s0,0x19 - 392: 6920 flw fs0,80(a0) - 394: 746e flw fs0,248(sp) - 396: 5f00 lw s0,56(a4) - 398: 635f 7a6c 745f 0x745f7a6c635f - 39e: 6261 lui tp,0x18 - 3a0: 5f00 lw s0,56(a4) - 3a2: 7461 lui s0,0xffff8 - 3a4: 7865 lui a6,0xffff9 - 3a6: 7469 lui s0,0xffffa - 3a8: 0030 addi a2,sp,8 - 3aa: 735f 6769 616e 0x616e6769735f - 3b0: 5f6c lw a1,124(a4) - 3b2: 7562 flw fa0,56(sp) - 3b4: 0066 c.slli zero,0x19 - 3b6: 615f 6373 6974 0x69746373615f - 3bc: 656d lui a0,0x1b - 3be: 625f 6675 5f00 0x5f006675625f - 3c4: 6572 flw fa0,28(sp) - 3c6: 746c7573 csrrci a0,0x746,24 - 3ca: 5f00 lw s0,56(a4) - 3cc: 775f 6863 4100 0x41006863775f - 3d2: 4942 lw s2,16(sp) - 3d4: 495f 504c 3233 0x3233504c495f - 3da: 0046 c.slli zero,0x11 - 3dc: 6e65 lui t3,0x19 - 3de: 6976 flw fs2,92(sp) - 3e0: 6f72 flw ft10,28(sp) - 3e2: 006e c.slli zero,0x1b - 3e4: 746e6977 0x746e6977 - 3e8: 745f 5f00 6f6c 0x6f6c5f00745f - 3ee: 5f006b63 bltu zero,a6,9e4 <_start-0x7ffff61c> - 3f2: 755f 0068 4241 0x42410068755f - 3f8: 5f49 li t5,-14 - 3fa: 4c49 li s8,18 - 3fc: 3350 fld fa2,160(a4) - 3fe: 4532 lw a0,12(sp) - 400: 5f00 lw s0,56(a4) - 402: 756d lui a0,0xffffb - 404: 746c flw fa1,108(s0) - 406: 5f00 lw s0,56(a4) - 408: 755f 006c 6e75 0x6e75006c755f - 40e: 63657073 csrci 0x636,10 - 412: 735f 7274 6e69 0x6e697274735f - 418: 6f007367 0x6f007367 - 41c: 7470 flw fa2,108(s0) - 41e: 6572 flw fa0,28(sp) - 420: 00746573 csrrsi a0,0x7,8 - 424: 775f 6972 6574 0x65746972775f - 42a: 5f00 lw s0,56(a4) - 42c: 745f 5f6d 6579 0x65795f6d745f - 432: 7261 lui tp,0xffff8 - 434: 5f00 lw s0,56(a4) - 436: 635f 756f 746e 0x746e756f635f - 43c: 5f00 lw s0,56(a4) - 43e: 6e75 lui t3,0x1d - 440: 7375 lui t1,0xffffd - 442: 6465 lui s0,0x19 - 444: 725f 6e61 0064 0x646e61725f - 44a: 4241 li tp,16 - 44c: 5f49 li t5,-14 - 44e: 4c49 li s8,18 - 450: 3350 fld fa2,160(a4) - 452: 4432 lw s0,12(sp) - 454: 7200 flw fs0,32(a2) - 456: 7369 lui t1,0xffffa - 458: 635f7663 bgeu t5,s5,a84 <_start-0x7ffff57c> - 45c: 5f65646f jal s0,56a52 <_start-0x7ffa95ae> - 460: 6f6d lui t5,0x1b - 462: 6564 flw fs1,76(a0) - 464: 006c addi a1,sp,12 - 466: 6f5f 6666 6573 0x657366666f5f - 46c: 0074 addi a3,sp,12 - 46e: 425f 6769 6e69 0x6e696769425f - 474: 0074 addi a3,sp,12 - 476: 6e5f 7865 6674 0x667478656e5f - 47c: 6300 flw fs0,0(a4) - 47e: 6c706d6f jal s10,7344 <_start-0x7fff8cbc> - 482: 7865 lui a6,0xffff9 - 484: 6620 flw fs0,72(a2) - 486: 6f6c flw fa1,92(a4) - 488: 7461 lui s0,0xffff8 - 48a: 5f00 lw s0,56(a4) - 48c: 745f 5f6d 6f6d 0x6f6d5f6d745f - 492: 006e c.slli zero,0x1b - 494: 615f 6574 6978 0x69786574615f - 49a: 0074 addi a3,sp,12 - 49c: 6f627573 csrrci a0,0x6f6,4 - 4a0: 7470 flw fa2,108(s0) - 4a2: 7261 lui tp,0xffff8 - 4a4: 5f5f0067 jr 1525(t5) # 1b5f5 <_start-0x7ffe4a0b> - 4a8: 64696473 csrrsi s0,0x646,18 - 4ac: 6e69 lui t3,0x1a - 4ae: 7469 lui s0,0xffffa - 4b0: 5f00 lw s0,56(a4) - 4b2: 5f66666f jal a2,66aa8 <_start-0x7ff99558> - 4b6: 0074 addi a3,sp,12 - 4b8: 5f5f 6876 5f00 0x5f0068765f5f - 4be: 765f 006c 665f 0x665f006c765f - 4c4: 6572 flw fa0,28(sp) - 4c6: 6c65 lui s8,0x19 - 4c8: 7369 lui t1,0xffffa - 4ca: 0074 addi a3,sp,12 - 4cc: 745f 6d69 7a65 0x7a656d69745f - 4d2: 00656e6f jal t3,564d8 <_start-0x7ffa9b28> - 4d6: 6d5f 7362 6174 0x617473626d5f - 4dc: 6574 flw fa3,76(a0) - 4de: 745f 5f00 4f4c 0x4f4c5f00745f - 4e4: 525f4b43 fmadd.d fs6,ft10,ft5,fa0,rmm - 4e8: 4345 li t1,17 - 4ea: 5255 li tp,-11 - 4ec: 45564953 0x45564953 - 4f0: 545f 5f00 6572 0x65725f00545f - 4f6: 6461 lui s0,0x18 - 4f8: 2e00 fld fs0,24(a2) - 4fa: 2f2e fld ft10,200(sp) - 4fc: 2e2e fld ft8,200(sp) - 4fe: 2f2e2e2f 0x2f2e2e2f - 502: 2e2e fld ft8,200(sp) - 504: 7369722f 0x7369722f - 508: 672d7663 bgeu s10,s2,b74 <_start-0x7ffff48c> - 50c: 6c2f6363 bltu t5,sp,bd2 <_start-0x7ffff42e> - 510: 6269 lui tp,0x1a - 512: 2f636367 0x2f636367 - 516: 696c flw fa1,84(a0) - 518: 6762 flw fa4,24(sp) - 51a: 2e326363 bltu tp,gp,800 <_start-0x7ffff800> - 51e: 42410063 beq sp,tp,93e <_start-0x7ffff6c2> - 522: 5f49 li t5,-14 - 524: 504c lw a1,36(s0) - 526: 3436 fld fs0,360(sp) - 528: 4100 lw s0,0(a0) - 52a: 4942 lw s2,16(sp) - 52c: 495f 504c 3233 0x3233504c495f - 532: 5f00 lw s0,56(a4) - 534: 7364 flw fs1,100(a4) - 536: 61685f6f jal t5,85b4c <_start-0x7ff7a4b4> - 53a: 646e flw fs0,216(sp) - 53c: 656c flw fa1,76(a0) - 53e: 4300 lw s0,0(a4) - 540: 5f4d li t5,-13 - 542: 454d li a0,19 - 544: 4144 lw s1,4(a0) - 546: 594e lw s2,240(sp) - 548: 5f00 lw s0,56(a4) - 54a: 656e flw fa0,216(sp) - 54c: 685f0077 0x685f0077 - 550: 655f 7272 6f6e 0x6f6e7272655f - 556: 5f00 lw s0,56(a4) - 558: 6c66 flw fs8,88(sp) - 55a: 5f6b636f jal t1,b6b50 <_start-0x7ff494b0> - 55e: 0074 addi a3,sp,12 - 560: 5f5f 6d74 795f 0x795f6d745f5f - 566: 6164 flw fs1,68(a0) - 568: 0079 c.nop 30 - 56a: 665f 616c 7367 0x7367616c665f - 570: 0032 c.slli zero,0xc - 572: 695f 626f 0073 0x73626f695f - 578: 4d5f4d43 0x4d5f4d43 - 57c: 4445 li s0,17 - 57e: 4f4c lw a1,28(a4) - 580: 74680057 vmsle.vv v0,v6,v16,v0.t - 584: 6261 lui tp,0x18 - 586: 685f 7361 0068 0x687361685f - 58c: 5f5f 4673 4c49 0x4c4946735f5f - 592: 0045 c.nop 17 - 594: 735f 7379 6e5f 0x6e5f7379735f - 59a: 7265 lui tp,0xffff9 - 59c: 0072 c.slli zero,0x1c - 59e: 6d5f 6c62 6e65 0x6e656c626d5f - 5a4: 735f 6174 6574 0x65746174735f - 5aa: 5f00 lw s0,56(a4) - 5ac: 6e69 lui t3,0x1a - 5ae: 695f0063 beq t5,s5,c2e <_start-0x7ffff3d2> - 5b2: 646e flw fs0,216(sp) - 5b4: 5f00 lw s0,56(a4) - 5b6: 755f 6964 6476 0x64766964755f - 5bc: 3369 jal 346 <_start-0x7ffffcba> - 5be: 5f00 lw s0,56(a4) - 5c0: 635f 656c 6e61 0x6e61656c635f - 5c6: 7075 c.lui zero,0xffffd - 5c8: 5f00 lw s0,56(a4) - 5ca: 616d addi sp,sp,240 - 5cc: 7778 flw fa4,108(a4) - 5ce: 7364 flw fs1,100(a4) - 5d0: 5f00 lw s0,56(a4) - 5d2: 6572 flw fa0,28(sp) - 5d4: 6e65 lui t3,0x19 - 5d6: 0074 addi a3,sp,12 - 5d8: 5f5f 3078 5f00 0x5f0030785f5f - 5de: 785f 0031 5f5f 0x5f5f0031785f - 5e4: 3278 fld fa4,224(a2) - 5e6: 5f00 lw s0,56(a4) - 5e8: 785f 0033 5f5f 0x5f5f0033785f - 5ee: 6176 flw ft2,92(sp) - 5f0: 756c flw fa1,108(a0) - 5f2: 0065 c.nop 25 - 5f4: 735f 6565 006b 0x6b6565735f - 5fa: 665f 6f70 5f73 0x5f736f70665f - 600: 0074 addi a3,sp,12 - 602: 625f 6b6c 6973 0x69736b6c625f - 608: 657a flw fa0,156(sp) - 60a: 5f00 lw s0,56(a4) - 60c: 657a6973 csrrsi s2,0x657,20 - 610: 5f00 lw s0,56(a4) - 612: 755f 6964 6d76 0x6d766964755f - 618: 6964646f jal s0,46cae <_start-0x7ffb9352> - 61c: 0034 addi a3,sp,8 - 61e: 6e75 lui t3,0x1d - 620: 63657073 csrci 0x636,10 - 624: 5f76 lw t5,124(sp) - 626: 69727473 csrrci s0,0x697,4 - 62a: 676e flw fa4,216(sp) - 62c: 735f0073 0x735f0073 - 630: 6565 lui a0,0x19 - 632: 0064 addi s1,sp,12 - 634: 6574706f j 4848a <_start-0x7ffb7b76> - 638: 7272 flw ft4,60(sp) - 63a: 6800 flw fs0,16(s0) - 63c: 6769 lui a4,0x1a - 63e: 0068 addi a0,sp,12 - 640: 5f5f 3071 5f00 0x5f0030715f5f - 646: 715f 0031 735f 0x735f0031715f - 64c: 7274 flw fa3,100(a2) - 64e: 6f74 flw fa3,92(a4) - 650: 616c5f6b 0x616c5f6b - 654: 43007473 csrrci s0,0x430,0 - 658: 5f4d li t5,-13 - 65a: 4950 lw a2,20(a0) - 65c: 665f0043 fmadd.q ft0,ft10,ft5,fa2,rne - 660: 746e flw fs0,248(sp) - 662: 7079 c.lui zero,0xffffe - 664: 7365 lui t1,0xffff9 - 666: 7500 flw fs0,40(a0) - 668: 736e flw ft6,248(sp) - 66a: 6769 lui a4,0x1a - 66c: 656e flw fa0,216(sp) - 66e: 2064 fld fs1,192(s0) - 670: 72616863 bltu sp,t1,da0 <_start-0x7ffff260> - 674: 5f00 lw s0,56(a4) - 676: 6461 lui s0,0x18 - 678: 0064 addi s1,sp,12 - 67a: 5f5f 4c55 6e6f 0x6e6f4c555f5f - 680: 74680067 jr 1862(a6) # ffff9746 <__BSS_END__+0x7ffe29ce> - 684: 6261 lui tp,0x18 - 686: 655f 5f71 6f70 0x6f705f71655f - 68c: 6e69 lui t3,0x1a - 68e: 6574 flw fa3,76(a0) - 690: 0072 c.slli zero,0x1c - 692: 5f5f 7278 5f00 0x5f0072785f5f - 698: 626f6c67 0x626f6c67 - 69c: 6c61 lui s8,0x18 - 69e: 695f 706d 7275 0x7275706d695f - 6a4: 5f65 li t5,-7 - 6a6: 7470 flw fa2,108(s0) - 6a8: 0072 c.slli zero,0x1c - 6aa: 4455 li s0,21 - 6ac: 7449 lui s0,0xffff2 - 6ae: 7079 c.lui zero,0xffffe - 6b0: 0065 c.nop 25 - 6b2: 735f 6474 756f 0x756f6474735f - 6b8: 0074 addi a3,sp,12 - 6ba: 5f5f 6d74 775f 0x775f6d745f5f - 6c0: 6164 flw fs1,68(a0) - 6c2: 0079 c.nop 30 - 6c4: 675f 756c 0065 0x65756c675f - 6ca: 735f 6474 6e69 0x6e696474735f - 6d0: 5f00 lw s0,56(a4) - 6d2: 7a697373 csrrci t1,0x7a6,18 - 6d6: 5f65 li t5,-7 - 6d8: 0074 addi a3,sp,12 - 6da: 6c5f 3436 5f61 0x5f6134366c5f - 6e0: 7562 flw fa0,56(sp) - 6e2: 0066 c.slli zero,0x19 - 6e4: 735f 6769 665f 0x665f6769735f - 6ea: 6e75 lui t3,0x1d - 6ec: 5f5f0063 beq t5,s5,ccc <_start-0x7ffff334> - 6f0: 6f70 flw fa2,92(a4) - 6f2: 6370 flw fa2,68(a4) - 6f4: 746e756f jal a0,e7e3a <_start-0x7ff181c6> - 6f8: 745f 6261 5f00 0x5f006261745f - 6fe: 626e flw ft4,216(sp) - 700: 6675 lui a2,0x1d - 702: 5f00 lw s0,56(a4) - 704: 6e75 lui t3,0x1d - 706: 7375 lui t1,0xffffd - 708: 6465 lui s0,0x19 - 70a: 5f00 lw s0,56(a4) - 70c: 725f 0030 5f5f 0x5f5f0030725f - 712: 3172 fld ft2,312(sp) - 714: 5f00 lw s0,56(a4) - 716: 745f 5f6d 7369 0x73695f6d745f - 71c: 7364 flw fs1,100(a4) - 71e: 0074 addi a3,sp,12 - 720: 6c5f 636f 6c61 0x6c61636f6c5f - 726: 6974 flw fa3,84(a0) - 728: 656d lui a0,0x1b - 72a: 625f 6675 5f00 0x5f006675625f - 730: 745f 5f6d 696d 0x696d5f6d745f - 736: 006e c.slli zero,0x1b - 738: 725f 3834 4100 0x41003834725f - 73e: 4942 lw s2,16(sp) - 740: 4c5f 3650 4434 0x443436504c5f - 746: 6f00 flw fs0,24(a4) - 748: 7470 flw fa2,108(s0) - 74a: 0074706f j 47f50 <_start-0x7ffb80b0> - 74e: 4241 li tp,16 - 750: 5f49 li t5,-14 - 752: 504c lw a1,36(s0) - 754: 3436 fld fs0,360(sp) - 756: 0046 c.slli zero,0x11 - 758: 6d5f 7462 776f 0x776f74626d5f - 75e: 74735f63 bge t1,t2,ebc <_start-0x7ffff144> - 762: 7461 lui s0,0xffff8 - 764: 0065 c.nop 25 - 766: 705f 7335 5f00 0x5f007335705f - 76c: 6f6c flw fa1,92(a4) - 76e: 656c6163 bltu s8,s6,db0 <_start-0x7ffff250> - 772: 5500 lw s0,40(a0) - 774: 4951 li s2,20 - 776: 7974 flw fa3,116(a0) - 778: 6570 flw fa2,76(a0) - 77a: 5f00 lw s0,56(a4) - 77c: 735f 7562 0066 0x667562735f - 782: 5f5f 6d74 6d5f 0x6d5f6d745f5f - 788: 6164 flw fs1,68(a0) - 78a: 0079 c.nop 30 - 78c: 725f 6e61 5f64 0x5f646e61725f - 792: 656e flw fa0,216(sp) - 794: 7478 flw fa4,108(s0) - 796: 6800 flw fs0,16(s0) - 798: 6174 flw fa3,68(a0) - 79a: 5f62 lw t5,56(sp) - 79c: 7165 addi sp,sp,-400 - 79e: 5f00 lw s0,56(a4) - 7a0: 755f 6f6d 6464 0x64646f6d755f - 7a6: 3369 jal 530 <_start-0x7ffffad0> - 7a8: 5f00 lw s0,56(a4) - 7aa: 5046 0x5046 - 7ac: 505f 4341 5f4b 0x5f4b4341505f - 7b2: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm - 7b6: 494e lw s2,208(sp) - 7b8: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - 7bc: 5f54 lw a3,60(a4) - 7be: 3066 fld ft0,120(sp) - 7c0: 5f00 lw s0,56(a4) - 7c2: 5046 0x5046 - 7c4: 505f 4341 5f4b 0x5f4b4341505f - 7ca: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm - 7ce: 494e lw s2,208(sp) - 7d0: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - 7d4: 5f54 lw a3,60(a4) - 7d6: 3166 fld ft2,120(sp) - 7d8: 5f00 lw s0,56(a4) - 7da: 5046 0x5046 - 7dc: 445f 5649 4d5f 0x4d5f5649445f - 7e2: 4145 li sp,17 - 7e4: 5f54 lw a3,60(a4) - 7e6: 5f32 lw t5,44(sp) - 7e8: 6475 lui s0,0x1d - 7ea: 7669 lui a2,0xffffa - 7ec: 6d5f 665f 0030 0x30665f6d5f - 7f2: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm - 7f6: 20373143 fmadd.s ft2,fa4,ft3,ft4,rup - 7fa: 2e38 fld fa4,88(a2) - 7fc: 20302e33 0x20302e33 - 800: 6d2d lui s10,0xb - 802: 646f6d63 bltu t5,t1,e5c <_start-0x7ffff1a4> - 806: 6c65 lui s8,0x19 - 808: 6d3d lui s10,0xf - 80a: 6465 lui s0,0x19 - 80c: 6f6c flw fa1,92(a4) - 80e: 6d2d2077 0x6d2d2077 - 812: 646f6d63 bltu t5,t1,e6c <_start-0x7ffff194> - 816: 6c65 lui s8,0x19 - 818: 6d3d lui s10,0xf - 81a: 6465 lui s0,0x19 - 81c: 6f6c flw fa1,92(a4) - 81e: 6d2d2077 0x6d2d2077 - 822: 7574 flw fa3,108(a0) - 824: 656e flw fa0,216(sp) - 826: 723d lui tp,0xfffef - 828: 656b636f jal t1,b6e7e <_start-0x7ff49182> - 82c: 2074 fld fa3,192(s0) - 82e: 6d2d lui s10,0xb - 830: 7261 lui tp,0xffff8 - 832: 723d6863 bltu s10,gp,f62 <_start-0x7ffff09e> - 836: 3376 fld ft6,376(sp) - 838: 6932 flw fs2,12(sp) - 83a: 766d lui a2,0xffffb - 83c: 2d20 fld fs0,88(a0) - 83e: 616d addi sp,sp,240 - 840: 6962 flw fs2,24(sp) - 842: 693d lui s2,0xf - 844: 706c flw fa1,100(s0) - 846: 2d203233 0x2d203233 - 84a: 4f2d2067 0x4f2d2067 - 84e: 4f2d2073 csrs 0x4f2,s10 - 852: 2032 fld ft0,264(sp) - 854: 4f2d li t5,11 - 856: 662d2073 csrs 0x662,s10 - 85a: 7562 flw fa0,56(sp) - 85c: 6c69 lui s8,0x1a - 85e: 6964 flw fs1,84(a0) - 860: 676e flw fa4,216(sp) - 862: 6c2d lui s8,0xb - 864: 6269 lui tp,0x1a - 866: 20636367 0x20636367 - 86a: 662d lui a2,0xb - 86c: 6f6e flw ft10,216(sp) - 86e: 732d lui t1,0xfffeb - 870: 6174 flw fa3,68(a0) - 872: 702d6b63 bltu s10,sp,f88 <_start-0x7ffff078> - 876: 6f72 flw ft10,28(sp) - 878: 6574 flw fa3,76(a0) - 87a: 726f7463 bgeu t5,t1,fa2 <_start-0x7ffff05e> - 87e: 2d20 fld fs0,88(a0) - 880: 7666 flw fa2,120(sp) - 882: 7369 lui t1,0xffffa - 884: 6269 lui tp,0x1a - 886: 6c69 lui s8,0x1a - 888: 7469 lui s0,0xffffa - 88a: 3d79 jal 728 <_start-0x7ffff8d8> - 88c: 6968 flw fa0,84(a0) - 88e: 6464 flw fs1,76(s0) - 890: 6e65 lui t3,0x19 - 892: 5f00 lw s0,56(a4) - 894: 645f 7669 6664 0x66647669645f - 89a: 48550033 0x48550033 - 89e: 70797457 vsetvli s0,s2,1799 - 8a2: 0065 c.nop 25 - 8a4: 465f 5f50 4944 0x49445f50465f - 8aa: 5f56 lw t5,116(sp) - 8ac: 454d li a0,19 - 8ae: 5441 li s0,-16 - 8b0: 325f 755f 6964 0x6964755f325f - 8b6: 5f76 lw t5,124(sp) - 8b8: 5f6d li t5,-5 - 8ba: 3166 fld ft2,120(sp) - 8bc: 6600 flw fs0,8(a2) - 8be: 6172 flw ft2,28(sp) - 8c0: 66003063 0x66003063 - 8c4: 6172 flw ft2,28(sp) - 8c6: 5f003163 0x5f003163 - 8ca: 5046 0x5046 - 8cc: 505f 4341 5f4b 0x5f4b4341505f - 8d2: 4152 lw sp,20(sp) - 8d4: 5f325f57 0x5f325f57 - 8d8: 6c66 flw fs8,88(sp) - 8da: 4644006f j 40d3e <_start-0x7ffbf2c2> - 8de: 7974 flw fa3,116(a0) - 8e0: 6570 flw fa2,76(a0) - 8e2: 5f00 lw s0,56(a4) - 8e4: 5046 0x5046 - 8e6: 555f 504e 4341 0x4341504e555f - 8ec: 41435f4b fnmsub.s ft10,ft6,fs4,fs0,unknown - 8f0: 4f4e lw t5,208(sp) - 8f2: 494e lw s2,208(sp) - 8f4: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - 8f8: 66696873 csrrsi a6,0x666,18 - 8fc: 0074 addi a3,sp,12 - 8fe: 465f 5f50 4944 0x49445f50465f - 904: 5f56 lw t5,116(sp) - 906: 454d li a0,19 - 908: 5441 li s0,-16 - 90a: 325f 755f 6964 0x6964755f325f - 910: 5f76 lw t5,124(sp) - 912: 5f72 lw t5,60(sp) - 914: 3066 fld ft0,120(sp) - 916: 5f00 lw s0,56(a4) - 918: 5046 0x5046 - 91a: 445f 5649 4d5f 0x4d5f5649445f - 920: 4145 li sp,17 - 922: 5f54 lw a3,60(a4) - 924: 5f32 lw t5,44(sp) - 926: 6475 lui s0,0x1d - 928: 7669 lui a2,0xffffa - 92a: 725f 665f 0031 0x31665f725f - 930: 5f52 lw t5,52(sp) - 932: 3066 fld ft0,120(sp) - 934: 5f00 lw s0,56(a4) - 936: 5046 0x5046 - 938: 555f 504e 4341 0x4341504e555f - 93e: 41525f4b fnmsub.s ft10,ft4,fs5,fs0,unknown - 942: 5f325f57 0x5f325f57 - 946: 6c66 flw fs8,88(sp) - 948: 5f41006f j 10f3c <_start-0x7ffef0c4> - 94c: 3166 fld ft2,120(sp) - 94e: 5f00 lw s0,56(a4) - 950: 6566 flw fa0,88(sp) - 952: 0078 addi a4,sp,12 - 954: 465f 5f50 4944 0x49445f50465f - 95a: 5f56 lw t5,116(sp) - 95c: 454d li a0,19 - 95e: 5441 li s0,-16 - 960: 325f 755f 6964 0x6964755f325f - 966: 5f76 lw t5,124(sp) - 968: 5f6e lw t5,248(sp) - 96a: 3066 fld ft0,120(sp) - 96c: 5f00 lw s0,56(a4) - 96e: 5046 0x5046 - 970: 445f 5649 4d5f 0x4d5f5649445f - 976: 4145 li sp,17 - 978: 5f54 lw a3,60(a4) - 97a: 5f32 lw t5,44(sp) - 97c: 6475 lui s0,0x1d - 97e: 7669 lui a2,0xffffa - 980: 6e5f 665f 0031 0x31665f6e5f - 986: 465f 5f50 4944 0x49445f50465f - 98c: 5f56 lw t5,116(sp) - 98e: 454d li a0,19 - 990: 5441 li s0,-16 - 992: 325f 755f 6964 0x6964755f325f - 998: 5f76 lw t5,124(sp) - 99a: 5f6e lw t5,248(sp) - 99c: 3266 fld ft4,120(sp) - 99e: 5f00 lw s0,56(a4) - 9a0: 5046 0x5046 - 9a2: 505f 4341 5f4b 0x5f4b4341505f - 9a8: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm - 9ac: 494e lw s2,208(sp) - 9ae: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - 9b2: 5f54 lw a3,60(a4) - 9b4: 465f0073 0x465f0073 - 9b8: 5f50 lw a2,60(a4) - 9ba: 4150 lw a2,4(a0) - 9bc: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm - 9c0: 4e41 li t3,16 - 9c2: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm - 9c6: 4c41 li s8,16 - 9c8: 695f 5f73 6974 0x69745f73695f - 9ce: 796e flw fs2,248(sp) - 9d0: 5f00 lw s0,56(a4) - 9d2: 5046 0x5046 - 9d4: 505f 4341 5f4b 0x5f4b4341505f - 9da: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm - 9de: 494e lw s2,208(sp) - 9e0: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - 9e4: 5f54 lw a3,60(a4) - 9e6: 5f410063 beq sp,s4,fc6 <_start-0x7ffff03a> - 9ea: 3066 fld ft0,120(sp) - 9ec: 4200 lw s0,0(a2) - 9ee: 665f 0030 5f42 0x5f420030665f - 9f4: 3166 fld ft2,120(sp) - 9f6: 2e00 fld fs0,24(a2) - 9f8: 2f2e fld ft10,200(sp) - 9fa: 2e2e fld ft8,200(sp) - 9fc: 2f2e2e2f 0x2f2e2e2f - a00: 2e2e fld ft8,200(sp) - a02: 7369722f 0x7369722f - a06: 672d7663 bgeu s10,s2,1072 <_start-0x7fffef8e> - a0a: 6c2f6363 bltu t5,sp,10d0 <_start-0x7fffef30> - a0e: 6269 lui tp,0x1a - a10: 2f636367 0x2f636367 - a14: 74666f73 csrrsi t5,0x746,12 - a18: 662d lui a2,0xb - a1a: 2f70 fld fa2,216(a4) - a1c: 6964 flw fs1,84(a0) - a1e: 6476 flw fs0,92(sp) - a20: 3366 fld ft6,120(sp) - a22: 632e flw ft6,200(sp) - a24: 5f00 lw s0,56(a4) - a26: 5046 0x5046 - a28: 555f 494e 4e4f 0x4e4f494e555f - a2e: 445f 5f00 5046 0x50465f00445f - a34: 505f 4341 5f4b 0x5f4b4341505f - a3a: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm - a3e: 494e lw s2,208(sp) - a40: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - a44: 5f54 lw a3,60(a4) - a46: 0065 c.nop 25 - a48: 6962 flw fs2,24(sp) - a4a: 7374 flw fa3,100(a4) - a4c: 5f00 lw s0,56(a4) - a4e: 7266 flw ft4,120(sp) - a50: 006d c.nop 27 - a52: 5f52 lw t5,52(sp) - a54: 3166 fld ft2,120(sp) - a56: 5f00 lw s0,56(a4) - a58: 5046 0x5046 - a5a: 465f 4152 5f43 0x5f434152465f - a60: 5f535253 0x5f535253 - a64: 5f34 lw a3,120(a4) - a66: 63697473 csrrci s0,0x636,18 - a6a: 5f00796b 0x5f00796b - a6e: 5046 0x5046 - a70: 465f 4152 5f43 0x5f434152465f - a76: 54535253 0x54535253 - a7a: 345f 645f 776f 0x776f645f345f - a80: 006e c.slli zero,0x1b - a82: 465f 5f50 5246 0x52465f50465f - a88: 4341 li t1,16 - a8a: 535f 5352 5f54 0x5f545352535f - a90: 5f34 lw a3,120(a4) - a92: 0069 c.nop 26 - a94: 465f 5f50 5246 0x52465f50465f - a9a: 4341 li t1,16 - a9c: 535f 5352 5f54 0x5f545352535f - aa2: 5f34 lw a3,120(a4) - aa4: 70696b73 csrrsi s6,0x706,18 - aa8: 5f00 lw s0,56(a4) - aaa: 5046 0x5046 - aac: 465f 4152 5f43 0x5f434152465f - ab2: 54535253 0x54535253 - ab6: 345f 735f 5f00 0x5f00735f345f - abc: 5046 0x5046 - abe: 4d5f 4c55 4d5f 0x4d5f4c554d5f - ac4: 4145 li sp,17 - ac6: 5f54 lw a3,60(a4) - ac8: 5744 lw s1,44(a4) - aca: 325f 775f 6469 0x6469775f325f - ad0: 5f65 li t5,-7 - ad2: 5f62 lw t5,56(sp) - ad4: 3166 fld ft2,120(sp) - ad6: 5f00 lw s0,56(a4) - ad8: 5046 0x5046 - ada: 465f 4152 5f43 0x5f434152465f - ae0: 54535253 0x54535253 - ae4: 345f 755f 0070 0x70755f345f - aea: 5f5f 756d 646c 0x646c756d5f5f - af0: 3366 fld ft6,120(sp) - af2: 5f00 lw s0,56(a4) - af4: 5046 0x5046 - af6: 4d5f 4c55 4d5f 0x4d5f4c554d5f - afc: 4145 li sp,17 - afe: 5f54 lw a3,60(a4) - b00: 5744 lw s1,44(a4) - b02: 325f 775f 6469 0x6469775f325f - b08: 5f65 li t5,-7 - b0a: 30665f63 bge a2,t1,e28 <_start-0x7ffff1d8> - b0e: 5f00 lw s0,56(a4) - b10: 5046 0x5046 - b12: 4d5f 4c55 4d5f 0x4d5f4c554d5f - b18: 4145 li sp,17 - b1a: 5f54 lw a3,60(a4) - b1c: 5744 lw s1,44(a4) - b1e: 325f 775f 6469 0x6469775f325f - b24: 5f65 li t5,-7 - b26: 31665f63 bge a2,s6,e44 <_start-0x7ffff1bc> - b2a: 5f00 lw s0,56(a4) - b2c: 465f 5f50 5246 0x52465f50465f - b32: 4341 li t1,16 - b34: 415f 4444 335f 0x335f4444415f - b3a: 635f 0032 465f 0x465f0032635f - b40: 5f50 lw a2,60(a4) - b42: 554d li a0,-13 - b44: 5f4c lw a1,60(a4) - b46: 454d li a0,19 - b48: 5441 li s0,-16 - b4a: 325f 775f 6469 0x6469775f325f - b50: 5f65 li t5,-7 - b52: 5f7a lw t5,188(sp) - b54: 0066 c.slli zero,0x19 - b56: 2e2e fld ft8,200(sp) - b58: 2f2e2e2f 0x2f2e2e2f - b5c: 2e2e fld ft8,200(sp) - b5e: 2f2e2e2f 0x2f2e2e2f - b62: 6972 flw fs2,28(sp) - b64: 2d766373 csrrsi t1,0x2d7,12 - b68: 2f636367 0x2f636367 - b6c: 696c flw fa1,84(a0) - b6e: 6762 flw fa4,24(sp) - b70: 732f6363 bltu t5,s2,1296 <_start-0x7fffed6a> - b74: 2d74666f jal a2,4764a <_start-0x7ffb89b6> - b78: 7066 flw ft0,120(sp) - b7a: 6c756d2f 0x6c756d2f - b7e: 6664 flw fs1,76(a2) - b80: 00632e33 slt t3,t1,t1 - b84: 5f5f 5046 465f 0x465f50465f5f - b8a: 4152 lw sp,20(sp) - b8c: 44415f43 0x44415f43 - b90: 5f44 lw s1,60(a4) - b92: 31635f33 0x31635f33 - b96: 5f00 lw s0,56(a4) - b98: 5046 0x5046 - b9a: 4d5f 4c55 4d5f 0x4d5f4c554d5f - ba0: 4145 li sp,17 - ba2: 5f54 lw a3,60(a4) - ba4: 5744 lw s1,44(a4) - ba6: 325f 775f 6469 0x6469775f325f - bac: 5f65 li t5,-7 - bae: 5f62 lw t5,56(sp) - bb0: 3066 fld ft0,120(sp) - bb2: 5f00 lw s0,56(a4) - bb4: 5046 0x5046 - bb6: 555f 504e 4341 0x4341504e555f - bbc: 41525f4b fnmsub.s ft10,ft4,fs5,fs0,unknown - bc0: 5f345f57 0x5f345f57 - bc4: 6c66 flw fs8,88(sp) - bc6: 2e2e006f j e0ea8 <_start-0x7ff1f158> - bca: 2f2e2e2f 0x2f2e2e2f - bce: 2e2e fld ft8,200(sp) - bd0: 2f2e2e2f 0x2f2e2e2f - bd4: 6972 flw fs2,28(sp) - bd6: 2d766373 csrrsi t1,0x2d7,12 - bda: 2f636367 0x2f636367 - bde: 696c flw fa1,84(a0) - be0: 6762 flw fa4,24(sp) - be2: 732f6363 bltu t5,s2,1308 <_start-0x7fffecf8> - be6: 2d74666f jal a2,476bc <_start-0x7ffb8944> - bea: 7066 flw ft0,120(sp) - bec: 7471652f 0x7471652f - bf0: 3266 fld ft4,120(sp) - bf2: 632e flw ft6,200(sp) - bf4: 6600 flw fs0,8(a2) - bf6: 6172 flw ft2,28(sp) - bf8: 66003263 0x66003263 - bfc: 6172 flw ft2,28(sp) - bfe: 54003363 0x54003363 - c02: 7446 flw fs0,112(sp) - c04: 7079 c.lui zero,0xffffe - c06: 0065 c.nop 25 - c08: 5f5f 6367 5f63 0x5f6363675f5f - c0e: 74504d43 0x74504d43 - c12: 7079 c.lui zero,0xffffe - c14: 0065 c.nop 25 - c16: 465f 5f50 5349 0x53495f50465f - c1c: 4e474953 0x4e474953 - c20: 4e41 li t3,16 - c22: 725f 7465 5f00 0x5f007465725f - c28: 655f 7471 3266 0x32667471655f - c2e: 5f00 lw s0,56(a4) - c30: 5046 0x5046 - c32: 555f 494e 4e4f 0x4e4f494e555f - c38: 515f 5f00 675f 0x675f5f00515f - c3e: 7465 lui s0,0xffff9 - c40: 3266 fld ft4,120(sp) - c42: 2e00 fld fs0,24(a2) - c44: 2f2e fld ft10,200(sp) - c46: 2e2e fld ft8,200(sp) - c48: 2f2e2e2f 0x2f2e2e2f - c4c: 2e2e fld ft8,200(sp) - c4e: 7369722f 0x7369722f - c52: 672d7663 bgeu s10,s2,12be <_start-0x7fffed42> - c56: 6c2f6363 bltu t5,sp,131c <_start-0x7fffece4> - c5a: 6269 lui tp,0x1a - c5c: 2f636367 0x2f636367 - c60: 74666f73 csrrsi t5,0x746,12 - c64: 662d lui a2,0xb - c66: 2f70 fld fa2,216(a4) - c68: 66746567 0x66746567 - c6c: 2e32 fld ft8,264(sp) - c6e: 465f0063 beq t5,t0,10ce <_start-0x7fffef32> - c72: 5f50 lw a2,60(a4) - c74: 5f504d43 fmadd.q fs10,ft0,fs5,fa1,rmm - c78: 7369 lui t1,0xffffa - c7a: 7a5f 7265 5f6f 0x5f6f72657a5f - c80: 0078 addi a4,sp,12 - c82: 465f 5f50 4d43 0x4d435f50465f - c88: 5f50 lw a2,60(a4) - c8a: 7369 lui t1,0xffffa - c8c: 7a5f 7265 5f6f 0x5f6f72657a5f - c92: 0079 c.nop 30 - c94: 5f5f 656c 6674 0x6674656c5f5f - c9a: 0032 c.slli zero,0xc - c9c: 2e2e fld ft8,200(sp) - c9e: 2f2e2e2f 0x2f2e2e2f - ca2: 2e2e fld ft8,200(sp) - ca4: 2f2e2e2f 0x2f2e2e2f - ca8: 6972 flw fs2,28(sp) - caa: 2d766373 csrrsi t1,0x2d7,12 - cae: 2f636367 0x2f636367 - cb2: 696c flw fa1,84(a0) - cb4: 6762 flw fa4,24(sp) - cb6: 732f6363 bltu t5,s2,13dc <_start-0x7fffec24> - cba: 2d74666f jal a2,47790 <_start-0x7ffb8870> - cbe: 7066 flw ft0,120(sp) - cc0: 74656c2f 0x74656c2f - cc4: 3266 fld ft4,120(sp) - cc6: 632e flw ft6,200(sp) - cc8: 5f00 lw s0,56(a4) - cca: 5046 0x5046 - ccc: 4d5f 4c55 4d5f 0x4d5f4c554d5f - cd2: 4145 li sp,17 - cd4: 5f54 lw a3,60(a4) - cd6: 5f34 lw a3,120(a4) - cd8: 65646977 0x65646977 - cdc: 7a5f 665f 5f00 0x5f00665f7a5f - ce2: 5046 0x5046 - ce4: 4d5f 4c55 4d5f 0x4d5f4c554d5f - cea: 4145 li sp,17 - cec: 5f54 lw a3,60(a4) - cee: 5744 lw s1,44(a4) - cf0: 345f 775f 6469 0x6469775f345f - cf6: 5f65 li t5,-7 - cf8: 30665f63 bge a2,t1,1016 <_start-0x7fffefea> - cfc: 5f00 lw s0,56(a4) - cfe: 5046 0x5046 - d00: 4d5f 4c55 4d5f 0x4d5f4c554d5f - d06: 4145 li sp,17 - d08: 5f54 lw a3,60(a4) - d0a: 5744 lw s1,44(a4) - d0c: 345f 775f 6469 0x6469775f345f - d12: 5f65 li t5,-7 - d14: 31665f63 bge a2,s6,1032 <_start-0x7fffefce> - d18: 5f00 lw s0,56(a4) - d1a: 5046 0x5046 - d1c: 4d5f 4c55 4d5f 0x4d5f4c554d5f - d22: 4145 li sp,17 - d24: 5f54 lw a3,60(a4) - d26: 5744 lw s1,44(a4) - d28: 345f 775f 6469 0x6469775f345f - d2e: 5f65 li t5,-7 - d30: 5f64 lw s1,124(a4) - d32: 3166 fld ft2,120(sp) - d34: 5f00 lw s0,56(a4) - d36: 6d5f 6c75 6674 0x66746c756d5f - d3c: 465f0033 0x465f0033 - d40: 5f50 lw a2,60(a4) - d42: 4150 lw a2,4(a0) - d44: 525f4b43 fmadd.d fs6,ft10,ft5,fa0,rmm - d48: 5741 li a4,-16 - d4a: 345f 665f 6f6c 0x6f6c665f345f - d50: 5f00 lw s0,56(a4) - d52: 5046 0x5046 - d54: 465f 4152 5f43 0x5f434152465f - d5a: 5f535253 0x5f535253 - d5e: 5f38 lw a4,120(a4) - d60: 7075 c.lui zero,0xffffd - d62: 5f00 lw s0,56(a4) - d64: 5046 0x5046 - d66: 465f 4152 5f43 0x5f434152465f - d6c: 5f4c4c53 0x5f4c4c53 - d70: 5f34 lw a3,120(a4) - d72: 70696b73 csrrsi s6,0x706,18 - d76: 5f00 lw s0,56(a4) - d78: 5046 0x5046 - d7a: 465f 4152 5f43 0x5f434152465f - d80: 5f4c4c53 0x5f4c4c53 - d84: 5f34 lw a3,120(a4) - d86: 6f64 flw fs1,92(a4) - d88: 5f006e77 0x5f006e77 - d8c: 5046 0x5046 - d8e: 4d5f 4c55 4d5f 0x4d5f4c554d5f - d94: 4145 li sp,17 - d96: 5f54 lw a3,60(a4) - d98: 5744 lw s1,44(a4) - d9a: 345f 775f 6469 0x6469775f345f - da0: 5f65 li t5,-7 - da2: 5f64 lw s1,124(a4) - da4: 3066 fld ft0,120(sp) - da6: 5f00 lw s0,56(a4) - da8: 5046 0x5046 - daa: 465f 4152 5f43 0x5f434152465f - db0: 5f4c5253 0x5f4c5253 - db4: 5f34 lw a3,120(a4) - db6: 0069 c.nop 26 - db8: 465f 5f50 5246 0x52465f50465f - dbe: 4341 li t1,16 - dc0: 535f 5352 385f 0x385f5352535f - dc6: 735f 5f00 5046 0x50465f00735f - dcc: 465f 4152 5f43 0x5f434152465f - dd2: 5f4c4c53 0x5f4c4c53 - dd6: 5f34 lw a3,120(a4) - dd8: 0069 c.nop 26 - dda: 465f 5f50 5246 0x52465f50465f - de0: 4341 li t1,16 - de2: 535f 5352 385f 0x385f5352535f - de8: 735f 696b 0070 0x70696b735f - dee: 465f 5f50 5246 0x52465f50465f - df4: 4341 li t1,16 - df6: 535f 4c52 345f 0x345f4c52535f - dfc: 645f 776f 006e 0x6e776f645f - e02: 465f 5f50 5246 0x52465f50465f - e08: 4341 li t1,16 - e0a: 535f 4c52 345f 0x345f4c52535f - e10: 735f 696b 0070 0x70696b735f - e16: 465f 5f50 554d 0x554d5f50465f - e1c: 5f4c lw a1,60(a4) - e1e: 454d li a0,19 - e20: 5441 li s0,-16 - e22: 445f 5f57 5f34 0x5f345f57445f - e28: 65646977 0x65646977 - e2c: 655f 665f 0030 0x30665f655f - e32: 465f 5f50 554d 0x554d5f50465f - e38: 5f4c lw a1,60(a4) - e3a: 454d li a0,19 - e3c: 5441 li s0,-16 - e3e: 445f 5f57 5f34 0x5f345f57445f - e44: 65646977 0x65646977 - e48: 655f 665f 0031 0x31665f655f - e4e: 465f 5f50 5246 0x52465f50465f - e54: 4341 li t1,16 - e56: 535f 4c52 345f 0x345f4c52535f - e5c: 755f 0070 465f 0x465f0070755f - e62: 5f50 lw a2,60(a4) - e64: 554d li a0,-13 - e66: 5f4c lw a1,60(a4) - e68: 454d li a0,19 - e6a: 5441 li s0,-16 - e6c: 445f 5f57 5f34 0x5f345f57445f - e72: 65646977 0x65646977 - e76: 625f 665f 0030 0x30665f625f - e7c: 465f 5f50 554d 0x554d5f50465f - e82: 5f4c lw a1,60(a4) - e84: 454d li a0,19 - e86: 5441 li s0,-16 - e88: 445f 5f57 5f34 0x5f345f57445f - e8e: 65646977 0x65646977 - e92: 625f 665f 0031 0x31665f625f - e98: 465f 5f50 5246 0x52465f50465f - e9e: 4341 li t1,16 - ea0: 535f 5352 385f 0x385f5352535f - ea6: 645f 776f 006e 0x6e776f645f - eac: 465f 5f50 4150 0x41505f50465f - eb2: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm - eb6: 4e41 li t3,16 - eb8: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm - ebc: 4c41 li s8,16 - ebe: 545f 665f 2e00 0x2e00665f545f - ec4: 2f2e fld ft10,200(sp) - ec6: 2e2e fld ft8,200(sp) - ec8: 2f2e2e2f 0x2f2e2e2f - ecc: 2e2e fld ft8,200(sp) - ece: 7369722f 0x7369722f - ed2: 672d7663 bgeu s10,s2,153e <_start-0x7fffeac2> - ed6: 6c2f6363 bltu t5,sp,159c <_start-0x7fffea64> - eda: 6269 lui tp,0x1a - edc: 2f636367 0x2f636367 - ee0: 74666f73 csrrsi t5,0x746,12 - ee4: 662d lui a2,0xb - ee6: 2f70 fld fa2,216(a4) - ee8: 756d lui a0,0xffffb - eea: 746c flw fa1,108(s0) - eec: 3366 fld ft6,120(sp) - eee: 632e flw ft6,200(sp) - ef0: 5f00 lw s0,56(a4) - ef2: 5046 0x5046 - ef4: 4d5f 4c55 4d5f 0x4d5f4c554d5f - efa: 4145 li sp,17 - efc: 5f54 lw a3,60(a4) - efe: 5744 lw s1,44(a4) - f00: 345f 775f 6469 0x6469775f345f - f06: 5f65 li t5,-7 - f08: 5f66 lw t5,120(sp) - f0a: 3066 fld ft0,120(sp) - f0c: 5f00 lw s0,56(a4) - f0e: 5046 0x5046 - f10: 4d5f 4c55 4d5f 0x4d5f4c554d5f - f16: 4145 li sp,17 - f18: 5f54 lw a3,60(a4) - f1a: 5744 lw s1,44(a4) - f1c: 345f 775f 6469 0x6469775f345f - f22: 5f65 li t5,-7 - f24: 5f66 lw t5,120(sp) - f26: 3166 fld ft2,120(sp) - f28: 5f00 lw s0,56(a4) - f2a: 465f 5f50 5246 0x52465f50465f - f30: 4341 li t1,16 - f32: 415f 4444 5f49 0x5f494444415f - f38: 5f34 lw a3,120(a4) - f3a: 0074 addi a3,sp,12 - f3c: 465f 5f50 5246 0x52465f50465f - f42: 4341 li t1,16 - f44: 535f 4c4c 345f 0x345f4c4c535f - f4a: 755f 0070 465f 0x465f0070755f - f50: 5f50 lw a2,60(a4) - f52: 5246 lw tp,112(sp) - f54: 4341 li t1,16 - f56: 535f 5352 385f 0x385f5352535f - f5c: 695f 5f00 735f 0x735f5f00695f - f62: 6275 lui tp,0x1d - f64: 6674 flw fa3,76(a2) - f66: 5f5f0033 0x5f5f0033 - f6a: 5046 0x5046 - f6c: 465f 4152 5f43 0x5f434152465f - f72: 5f425553 0x5f425553 - f76: 5f34 lw a3,120(a4) - f78: 61003363 0x61003363 - f7c: 6464 flw fs1,76(s0) - f7e: 0032 c.slli zero,0xc - f80: 6461 lui s0,0x18 - f82: 5f64 lw s1,124(a4) - f84: 6f64 flw fs1,92(a4) - f86: 656e flw fa0,216(sp) - f88: 7300 flw fs0,32(a4) - f8a: 6275 lui tp,0x1d - f8c: 0032 c.slli zero,0xc - f8e: 465f 5f50 4150 0x41505f50465f - f94: 535f4b43 fmadd.d fs6,ft10,fs5,fa0,rmm - f98: 4d45 li s10,17 - f9a: 5249 li tp,-14 - f9c: 5741 li a4,-16 - f9e: 545f 635f 7300 0x7300635f545f - fa4: 6275 lui tp,0x1d - fa6: 0031 c.nop 12 - fa8: 2e2e fld ft8,200(sp) - faa: 2f2e2e2f 0x2f2e2e2f - fae: 2e2e fld ft8,200(sp) - fb0: 2f2e2e2f 0x2f2e2e2f - fb4: 6972 flw fs2,28(sp) - fb6: 2d766373 csrrsi t1,0x2d7,12 - fba: 2f636367 0x2f636367 - fbe: 696c flw fa1,84(a0) - fc0: 6762 flw fa4,24(sp) - fc2: 732f6363 bltu t5,s2,16e8 <_start-0x7fffe918> - fc6: 2d74666f jal a2,47a9c <_start-0x7ffb8564> - fca: 7066 flw ft0,120(sp) - fcc: 6275732f vamoande.v zero,v7,(a0),v6 - fd0: 6674 flw fa3,76(a2) - fd2: 00632e33 slt t3,t1,t1 - fd6: 465f 5f50 4150 0x41505f50465f - fdc: 535f4b43 fmadd.d fs6,ft10,fs5,fa0,rmm - fe0: 4d45 li s10,17 - fe2: 5249 li tp,-14 - fe4: 5741 li a4,-16 - fe6: 545f 735f 5f00 0x5f00735f545f - fec: 465f 5f50 5246 0x52465f50465f - ff2: 4341 li t1,16 - ff4: 415f 4444 345f 0x345f4444415f - ffa: 635f 0031 5f5f 0x5f5f0031635f - 1000: 5046 0x5046 - 1002: 465f 4152 5f43 0x5f434152465f - 1008: 4441 li s0,16 - 100a: 5f44 lw s1,60(a4) - 100c: 5f34 lw a3,120(a4) - 100e: 5f003263 0x5f003263 - 1012: 465f 5f50 5246 0x52465f50465f - 1018: 4341 li t1,16 - 101a: 415f 4444 345f 0x345f4444415f - 1020: 635f 0033 465f 0x465f0033635f - 1026: 5f50 lw a2,60(a4) - 1028: 4150 lw a2,4(a0) - 102a: 535f4b43 fmadd.d fs6,ft10,fs5,fa0,rmm - 102e: 4d45 li s10,17 - 1030: 5249 li tp,-14 - 1032: 5741 li a4,-16 - 1034: 545f 655f 5f00 0x5f00655f545f - 103a: 5046 0x5046 - 103c: 505f 4341 5f4b 0x5f4b4341505f - 1042: 494d4553 0x494d4553 - 1046: 4152 lw sp,20(sp) - 1048: 73695f57 vmfne.vf v30,v22,fs2 - 104c: 745f 6e69 0079 0x796e69745f - 1052: 465f 5f50 4150 0x41505f50465f - 1058: 535f4b43 fmadd.d fs6,ft10,fs5,fa0,rmm - 105c: 4d45 li s10,17 - 105e: 5249 li tp,-14 - 1060: 5741 li a4,-16 - 1062: 545f 665f 5f00 0x5f00665f545f - 1068: 5046 0x5046 - 106a: 415f 4444 495f 0x495f4444415f - 1070: 544e lw s0,240(sp) - 1072: 5245 li tp,-15 - 1074: 414e lw sp,208(sp) - 1076: 5f4c lw a1,60(a4) - 1078: 6964 flw fs1,84(a0) - 107a: 6666 flw fa2,88(sp) - 107c: 7300 flw fs0,32(a4) - 107e: 6275 lui tp,0x1d - 1080: 465f0033 0x465f0033 - 1084: 5f50 lw a2,60(a4) - 1086: 4441 li s0,16 - 1088: 5f44 lw s1,60(a4) - 108a: 4e49 li t3,18 - 108c: 4554 lw a3,12(a0) - 108e: 4e52 lw t3,20(sp) - 1090: 4c41 li s8,16 - 1092: 655f 6964 6666 0x66666964655f - 1098: 7300 flw fs0,32(a4) - 109a: 6275 lui tp,0x1d - 109c: 645f 6e6f 0065 0x656e6f645f - 10a2: 5f5f 5046 465f 0x465f50465f5f - 10a8: 4152 lw sp,20(sp) - 10aa: 55535f43 0x55535f43 - 10ae: 5f42 lw t5,48(sp) - 10b0: 5f34 lw a3,120(a4) - 10b2: 61003163 0x61003163 - 10b6: 6464 flw fs1,76(s0) - 10b8: 0031 c.nop 12 - 10ba: 6461 lui s0,0x18 - 10bc: 3364 fld fs1,224(a4) - 10be: 6e00 flw fs0,24(a2) - 10c0: 006d726f jal tp,d80c6 <_start-0x7ff27f3a> - 10c4: 5f5f 5046 465f 0x465f50465f5f - 10ca: 4152 lw sp,20(sp) - 10cc: 55535f43 0x55535f43 - 10d0: 5f42 lw t5,48(sp) - 10d2: 5f34 lw a3,120(a4) - 10d4: 5f003263 0x5f003263 - 10d8: 5046 0x5046 - 10da: 545f 5f4f 4e49 0x4e495f4f545f - 10e0: 5f54 lw a3,60(a4) - 10e2: 6e69 lui t3,0x1a - 10e4: 7865 lui a6,0xffff9 - 10e6: 6361 lui t1,0x18 - 10e8: 0074 addi a3,sp,12 - 10ea: 2e2e fld ft8,200(sp) - 10ec: 2f2e2e2f 0x2f2e2e2f - 10f0: 2e2e fld ft8,200(sp) - 10f2: 2f2e2e2f 0x2f2e2e2f - 10f6: 6972 flw fs2,28(sp) - 10f8: 2d766373 csrrsi t1,0x2d7,12 - 10fc: 2f636367 0x2f636367 - 1100: 696c flw fa1,84(a0) - 1102: 6762 flw fa4,24(sp) - 1104: 732f6363 bltu t5,s2,182a <_start-0x7fffe7d6> - 1108: 2d74666f jal a2,47bde <_start-0x7ffb8422> - 110c: 7066 flw ft0,120(sp) - 110e: 7869662f 0x7869662f - 1112: 6674 flw fa3,76(a2) - 1114: 632e6973 csrrsi s2,0x632,28 - 1118: 5f00 lw s0,56(a4) - 111a: 665f 7869 6674 0x66747869665f - 1120: 2e006973 csrrsi s2,0x2e0,0 - 1124: 2f2e fld ft10,200(sp) - 1126: 2e2e fld ft8,200(sp) - 1128: 2f2e2e2f 0x2f2e2e2f - 112c: 2e2e fld ft8,200(sp) - 112e: 7369722f 0x7369722f - 1132: 672d7663 bgeu s10,s2,179e <_start-0x7fffe862> - 1136: 6c2f6363 bltu t5,sp,17fc <_start-0x7fffe804> - 113a: 6269 lui tp,0x1a - 113c: 2f636367 0x2f636367 - 1140: 74666f73 csrrsi t5,0x746,12 - 1144: 662d lui a2,0xb - 1146: 2f70 fld fa2,216(a4) - 1148: 6c66 flw fs8,88(sp) - 114a: 7374616f jal sp,48080 <_start-0x7ffb7f80> - 114e: 7469 lui s0,0xffffa - 1150: 2e66 fld ft8,88(sp) - 1152: 61700063 beq zero,s7,1752 <_start-0x7fffe8ae> - 1156: 735f6b63 bltu t5,s5,188c <_start-0x7fffe774> - 115a: 6d65 lui s10,0x19 - 115c: 7269 lui tp,0xffffa - 115e: 7761 lui a4,0xffff8 - 1160: 5f00 lw s0,56(a4) - 1162: 665f 6f6c 7461 0x74616f6c665f - 1168: 66746973 csrrsi s2,0x667,8 - 116c: 5f00 lw s0,56(a4) - 116e: 5046 0x5046 - 1170: 465f 4f52 5f4d 0x5f4d4f52465f - 1176: 4e49 li t3,18 - 1178: 5f54 lw a3,60(a4) - 117a: 7275 lui tp,0xffffd - 117c: 5f00 lw s0,56(a4) - 117e: 5046 0x5046 - 1180: 465f 4f52 5f4d 0x5f4d4f52465f - 1186: 4e49 li t3,18 - 1188: 5f54 lw a3,60(a4) - 118a: 7a6c flw fa1,116(a2) - 118c: 4600 lw s0,8(a2) - 118e: 5f50 lw a2,60(a4) - 1190: 5845 li a6,-15 - 1192: 4554 lw a3,12(a0) - 1194: 444e lw s0,208(sp) - 1196: 6c5f 007a 2e2e 0x2e2e007a6c5f - 119c: 2f2e2e2f 0x2f2e2e2f - 11a0: 2e2e fld ft8,200(sp) - 11a2: 2f2e2e2f 0x2f2e2e2f - 11a6: 6972 flw fs2,28(sp) - 11a8: 2d766373 csrrsi t1,0x2d7,12 - 11ac: 2f636367 0x2f636367 - 11b0: 696c flw fa1,84(a0) - 11b2: 6762 flw fa4,24(sp) - 11b4: 732f6363 bltu t5,s2,18da <_start-0x7fffe726> - 11b8: 2d74666f jal a2,47c8e <_start-0x7ffb8372> - 11bc: 7066 flw ft0,120(sp) - 11be: 7478652f 0x7478652f - 11c2: 6e65 lui t3,0x19 - 11c4: 6464 flw fs1,76(s0) - 11c6: 7466 flw fs0,120(sp) - 11c8: 3266 fld ft4,120(sp) - 11ca: 632e flw ft6,200(sp) - 11cc: 5f00 lw s0,56(a4) - 11ce: 655f 7478 6e65 0x6e657478655f - 11d4: 6464 flw fs1,76(s0) - 11d6: 7466 flw fs0,120(sp) - 11d8: 3266 fld ft4,120(sp) - 11da: 2e00 fld fs0,24(a2) - 11dc: 2f2e fld ft10,200(sp) - 11de: 2e2e fld ft8,200(sp) - 11e0: 2f2e2e2f 0x2f2e2e2f - 11e4: 2e2e fld ft8,200(sp) - 11e6: 7369722f 0x7369722f - 11ea: 672d7663 bgeu s10,s2,1856 <_start-0x7fffe7aa> - 11ee: 6c2f6363 bltu t5,sp,18b4 <_start-0x7fffe74c> - 11f2: 6269 lui tp,0x1a - 11f4: 2f636367 0x2f636367 - 11f8: 74666f73 csrrsi t5,0x746,12 - 11fc: 662d lui a2,0xb - 11fe: 2f70 fld fa2,216(a4) - 1200: 7274 flw fa3,100(a2) - 1202: 6e75 lui t3,0x1d - 1204: 64667463 bgeu a2,t1,184c <_start-0x7fffe7b4> - 1208: 3266 fld ft4,120(sp) - 120a: 632e flw ft6,200(sp) - 120c: 5f00 lw s0,56(a4) - 120e: 5046 0x5046 - 1210: 505f 4341 5f4b 0x5f4b4341505f - 1216: 494d4553 0x494d4553 - 121a: 4152 lw sp,20(sp) - 121c: 5f545f57 0x5f545f57 - 1220: 3066 fld ft0,120(sp) - 1222: 5f00 lw s0,56(a4) - 1224: 5046 0x5046 - 1226: 505f 4341 5f4b 0x5f4b4341505f - 122c: 494d4553 0x494d4553 - 1230: 4152 lw sp,20(sp) - 1232: 5f545f57 0x5f545f57 - 1236: 3166 fld ft2,120(sp) - 1238: 5f00 lw s0,56(a4) - 123a: 745f 7572 636e 0x636e7572745f - 1240: 6674 flw fa3,76(a2) - 1242: 6664 flw fs1,76(a2) - 1244: 0032 c.slli zero,0xc - 1246: 5f5f 6c63 737a 0x737a6c635f5f - 124c: 3269 jal bd6 <_start-0x7ffff42a> - ... - -Disassembly of section .debug_loc: - -00000000 <.debug_loc>: - 0: 0000 unimp - 2: 0000 unimp - 4: 0068 addi a0,sp,12 - 6: 0000 unimp - 8: 0006 c.slli zero,0x1 - a: 935a add t1,t1,s6 - c: 5b04 lw s1,48(a4) - e: 00680493 addi s1,a6,6 # ffff9006 <__BSS_END__+0x7ffe228e> - 12: 0000 unimp - 14: 00f4 addi a3,sp,76 - 16: 0000 unimp - 18: 0006 c.slli zero,0x1 - 1a: 0af503f3 0xaf503f3 - 1e: 9f25 0x9f25 - 20: 00f4 addi a3,sp,76 - 22: 0000 unimp - 24: 014c addi a1,sp,132 - 26: 0000 unimp - 28: 0006 c.slli zero,0x1 - 2a: 935a add t1,t1,s6 - 2c: 5b04 lw s1,48(a4) - 2e: 014c0493 addi s1,s8,20 # 1a014 <_start-0x7ffe5fec> - 32: 0000 unimp - 34: 01dc addi a5,sp,196 - 36: 0000 unimp - 38: 0006 c.slli zero,0x1 - 3a: 0af503f3 0xaf503f3 - 3e: 9f25 0x9f25 - 40: 01dc addi a5,sp,196 - 42: 0000 unimp - 44: 0204 addi s1,sp,256 - 46: 0000 unimp - 48: 0006 c.slli zero,0x1 - 4a: 935a add t1,t1,s6 - 4c: 5b04 lw s1,48(a4) - 4e: 02040493 addi s1,s0,32 # ffffa020 <__BSS_END__+0x7ffe32a8> - 52: 0000 unimp - 54: 029c addi a5,sp,320 - 56: 0000 unimp - 58: 0006 c.slli zero,0x1 - 5a: 0af503f3 0xaf503f3 - 5e: 9f25 0x9f25 - 60: 029c addi a5,sp,320 - 62: 0000 unimp - 64: 02e4 addi s1,sp,332 - 66: 0000 unimp - 68: 0006 c.slli zero,0x1 - 6a: 935a add t1,t1,s6 - 6c: 5b04 lw s1,48(a4) - 6e: 02e40493 addi s1,s0,46 - 72: 0000 unimp - 74: 02ec addi a1,sp,332 - 76: 0000 unimp - 78: 0006 c.slli zero,0x1 - 7a: 0af503f3 0xaf503f3 - 7e: 9f25 0x9f25 - 80: 02ec addi a1,sp,332 - 82: 0000 unimp - 84: 0414 addi a3,sp,512 - 86: 0000 unimp - 88: 0006 c.slli zero,0x1 - 8a: 935a add t1,t1,s6 - 8c: 5b04 lw s1,48(a4) - 8e: 04140493 addi s1,s0,65 - 92: 0000 unimp - 94: 0428 addi a0,sp,520 - 96: 0000 unimp - 98: 0006 c.slli zero,0x1 - 9a: 0af503f3 0xaf503f3 - 9e: 9f25 0x9f25 - a0: 0428 addi a0,sp,520 - a2: 0000 unimp - a4: 0434 addi a3,sp,520 - a6: 0000 unimp - a8: 0006 c.slli zero,0x1 - aa: 935a add t1,t1,s6 - ac: 5b04 lw s1,48(a4) - ae: 00000493 li s1,0 - ... - ba: 0000 unimp - bc: 0070 addi a2,sp,12 - be: 0000 unimp - c0: 0006 c.slli zero,0x1 - c2: 935c 0x935c - c4: 5d04 lw s1,56(a0) - c6: 00700493 li s1,7 - ca: 0000 unimp - cc: 00f4 addi a3,sp,76 - ce: 0000 unimp - d0: 0006 c.slli zero,0x1 - d2: 0cf503f3 0xcf503f3 - d6: 9f25 0x9f25 - d8: 00f4 addi a3,sp,76 - da: 0000 unimp - dc: 014c addi a1,sp,132 - de: 0000 unimp - e0: 0006 c.slli zero,0x1 - e2: 935c 0x935c - e4: 5d04 lw s1,56(a0) - e6: 014c0493 addi s1,s8,20 - ea: 0000 unimp - ec: 01dc addi a5,sp,196 - ee: 0000 unimp - f0: 0006 c.slli zero,0x1 - f2: 0cf503f3 0xcf503f3 - f6: 9f25 0x9f25 - f8: 01dc addi a5,sp,196 - fa: 0000 unimp - fc: 021c addi a5,sp,256 - fe: 0000 unimp - 100: 0006 c.slli zero,0x1 - 102: 935c 0x935c - 104: 5d04 lw s1,56(a0) - 106: 021c0493 addi s1,s8,33 - 10a: 0000 unimp - 10c: 029c addi a5,sp,320 - 10e: 0000 unimp - 110: 0006 c.slli zero,0x1 - 112: 0cf503f3 0xcf503f3 - 116: 9f25 0x9f25 - 118: 029c addi a5,sp,320 - 11a: 0000 unimp - 11c: 0334 addi a3,sp,392 - 11e: 0000 unimp - 120: 0006 c.slli zero,0x1 - 122: 935c 0x935c - 124: 5d04 lw s1,56(a0) - 126: 03340493 addi s1,s0,51 - 12a: 0000 unimp - 12c: 0428 addi a0,sp,520 - 12e: 0000 unimp - 130: 0006 c.slli zero,0x1 - 132: 0cf503f3 0xcf503f3 - 136: 9f25 0x9f25 - 138: 0428 addi a0,sp,520 - 13a: 0000 unimp - 13c: 0434 addi a3,sp,520 - 13e: 0000 unimp - 140: 0006 c.slli zero,0x1 - 142: 935c 0x935c - 144: 5d04 lw s1,56(a0) - 146: 00000493 li s1,0 - ... - 152: 0000 unimp - 154: 01d4 addi a3,sp,196 - 156: 0000 unimp - 158: 0002 c.slli64 zero - 15a: 9f30 0x9f30 - 15c: 01dc addi a5,sp,196 - 15e: 0000 unimp - 160: 0434 addi a3,sp,520 - 162: 0000 unimp - 164: 0002 c.slli64 zero - 166: 9f30 0x9f30 - ... - 174: 0024 addi s1,sp,8 - 176: 0000 unimp - 178: 0006 c.slli zero,0x1 - 17a: 935c 0x935c - 17c: 5d04 lw s1,56(a0) - 17e: 00240493 addi s1,s0,2 - 182: 0000 unimp - 184: 0034 addi a3,sp,8 - 186: 0000 unimp - 188: 0006 c.slli zero,0x1 - 18a: 935c 0x935c - 18c: 6104 flw fs1,0(a0) - 18e: 00f40493 addi s1,s0,15 - 192: 0000 unimp - 194: 00f8 addi a4,sp,76 - 196: 0000 unimp - 198: 0006 c.slli zero,0x1 - 19a: 935c 0x935c - 19c: 6104 flw fs1,0(a0) - 19e: 01080493 addi s1,a6,16 - 1a2: 0000 unimp - 1a4: 0110 addi a2,sp,128 - 1a6: 0000 unimp - 1a8: 0006 c.slli zero,0x1 - 1aa: 935c 0x935c - 1ac: 5d04 lw s1,56(a0) - 1ae: 01100493 li s1,17 - 1b2: 0000 unimp - 1b4: 0128 addi a0,sp,136 - 1b6: 0000 unimp - 1b8: 0006 c.slli zero,0x1 - 1ba: 935c 0x935c - 1bc: 6104 flw fs1,0(a0) - 1be: 01dc0493 addi s1,s8,29 - 1c2: 0000 unimp - 1c4: 01e4 addi s1,sp,204 - 1c6: 0000 unimp - 1c8: 0006 c.slli zero,0x1 - 1ca: 935c 0x935c - 1cc: 6104 flw fs1,0(a0) - 1ce: 029c0493 addi s1,s8,41 - 1d2: 0000 unimp - 1d4: 0308 addi a0,sp,384 - 1d6: 0000 unimp - 1d8: 0006 c.slli zero,0x1 - 1da: 935c 0x935c - 1dc: 5d04 lw s1,56(a0) - 1de: 03080493 addi s1,a6,48 - 1e2: 0000 unimp - 1e4: 0318 addi a4,sp,384 - 1e6: 0000 unimp - 1e8: 0006 c.slli zero,0x1 - 1ea: 935c 0x935c - 1ec: 6104 flw fs1,0(a0) - 1ee: 04280493 addi s1,a6,66 - 1f2: 0000 unimp - 1f4: 0434 addi a3,sp,520 - 1f6: 0000 unimp - 1f8: 0006 c.slli zero,0x1 - 1fa: 935c 0x935c - 1fc: 5d04 lw s1,56(a0) - 1fe: 00000493 li s1,0 - ... - 20a: 0000 unimp - 20c: 0060 addi s0,sp,12 - 20e: 0000 unimp - 210: 0006 c.slli zero,0x1 - 212: 935a add t1,t1,s6 - 214: 5b04 lw s1,48(a4) - 216: 00f40493 addi s1,s0,15 - 21a: 0000 unimp - 21c: 014c addi a1,sp,132 - 21e: 0000 unimp - 220: 0006 c.slli zero,0x1 - 222: 9356 add t1,t1,s5 - 224: 5b04 lw s1,48(a4) - 226: 01dc0493 addi s1,s8,29 - 22a: 0000 unimp - 22c: 01f8 addi a4,sp,204 - 22e: 0000 unimp - 230: 0006 c.slli zero,0x1 - 232: 9356 add t1,t1,s5 - 234: 5b04 lw s1,48(a4) - 236: 01f80493 addi s1,a6,31 - 23a: 0000 unimp - 23c: 01fc addi a5,sp,204 - 23e: 0000 unimp - 240: 0006 c.slli zero,0x1 - 242: 9356 add t1,t1,s5 - 244: 5f04 lw s1,56(a4) - 246: 01fc0493 addi s1,s8,31 - 24a: 0000 unimp - 24c: 0204 addi s1,sp,256 - 24e: 0000 unimp - 250: 0006 c.slli zero,0x1 - 252: 935a add t1,t1,s6 - 254: 5f04 lw s1,56(a4) - 256: 029c0493 addi s1,s8,41 - 25a: 0000 unimp - 25c: 02b4 addi a3,sp,328 - 25e: 0000 unimp - 260: 0006 c.slli zero,0x1 - 262: 9356 add t1,t1,s5 - 264: 5b04 lw s1,48(a4) - 266: 02b40493 addi s1,s0,43 - 26a: 0000 unimp - 26c: 02ec addi a1,sp,332 - 26e: 0000 unimp - 270: 0006 c.slli zero,0x1 - 272: 9356 add t1,t1,s5 - 274: 5f04 lw s1,56(a4) - 276: 02ec0493 addi s1,s8,46 - 27a: 0000 unimp - 27c: 02f0 addi a2,sp,332 - 27e: 0000 unimp - 280: 0006 c.slli zero,0x1 - 282: 9356 add t1,t1,s5 - 284: 5b04 lw s1,48(a4) - 286: 02f00493 li s1,47 - 28a: 0000 unimp - 28c: 031c addi a5,sp,384 - 28e: 0000 unimp - 290: 0006 c.slli zero,0x1 - 292: 9356 add t1,t1,s5 - 294: 5f04 lw s1,56(a4) - 296: 04280493 addi s1,a6,66 - 29a: 0000 unimp - 29c: 042c addi a1,sp,520 - 29e: 0000 unimp - 2a0: 0006 c.slli zero,0x1 - 2a2: 9356 add t1,t1,s5 - 2a4: 5b04 lw s1,48(a4) - 2a6: 042c0493 addi s1,s8,66 - 2aa: 0000 unimp - 2ac: 0434 addi a3,sp,520 - 2ae: 0000 unimp - 2b0: 0006 c.slli zero,0x1 - 2b2: 9356 add t1,t1,s5 - 2b4: 5f04 lw s1,56(a4) - 2b6: 00000493 li s1,0 - 2ba: 0000 unimp - 2bc: 0000 unimp - 2be: 0000 unimp - 2c0: 0008 0x8 - 2c2: 0000 unimp - 2c4: 0050 addi a2,sp,4 - 2c6: 0000 unimp - 2c8: 0001 nop - 2ca: 505c lw a5,36(s0) - 2cc: 0000 unimp - 2ce: 5c00 lw s0,56(s0) - 2d0: 0000 unimp - 2d2: 0900 addi s0,sp,144 - 2d4: 7c00 flw fs0,56(s0) - 2d6: 7e00 flw fs0,56(a2) - 2d8: 0800 addi s0,sp,16 - 2da: 1aff 0x1aff - 2dc: 9f24 0x9f24 - 2de: 005c addi a5,sp,4 - 2e0: 0000 unimp - 2e2: 00ec addi a1,sp,76 - 2e4: 0000 unimp - 2e6: 0001 nop - 2e8: f460 fsw fs0,108(s0) - 2ea: 0000 unimp - 2ec: 1000 addi s0,sp,32 - 2ee: 0001 nop - 2f0: 0100 addi s0,sp,128 - 2f2: 5c00 lw s0,56(s0) - 2f4: 0110 addi a2,sp,128 - 2f6: 0000 unimp - 2f8: 0114 addi a3,sp,128 - 2fa: 0000 unimp - 2fc: f731000b 0xf731000b - 300: 7c2c flw fa1,120(s0) - 302: f700 fsw fs0,40(a4) - 304: 1b2c addi a1,sp,440 - 306: 149f00f7 0x149f00f7 - 30a: 0001 nop - 30c: d400 sw s0,40(s0) - 30e: 0001 nop - 310: 0100 addi s0,sp,128 - 312: 6000 flw fs0,0(s0) - 314: 01dc addi a5,sp,196 - 316: 0000 unimp - 318: 01f0 addi a2,sp,204 - 31a: 0000 unimp - 31c: 0001 nop - 31e: f060 fsw fs0,100(s0) - 320: 0001 nop - 322: f400 fsw fs0,40(s0) - 324: 0001 nop - 326: 0900 addi s0,sp,144 - 328: 8000 0x8000 - 32a: 7e00 flw fs0,56(a2) - 32c: 0800 addi s0,sp,16 - 32e: 1aff 0x1aff - 330: 9f24 0x9f24 - 332: 01f4 addi a3,sp,204 - 334: 0000 unimp - 336: 029c addi a5,sp,320 - 338: 0000 unimp - 33a: 0001 nop - 33c: 9c60 0x9c60 - 33e: 0002 c.slli64 zero - 340: c800 sw s0,16(s0) - 342: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 346: 5c00 lw s0,56(s0) - 348: 0428 addi a0,sp,520 - 34a: 0000 unimp - 34c: 0434 addi a3,sp,520 - 34e: 0000 unimp - 350: 0001 nop - 352: 005c addi a5,sp,4 - 354: 0000 unimp - 356: 0000 unimp - 358: 0000 unimp - 35a: 0c00 addi s0,sp,528 - 35c: 0000 unimp - 35e: 2400 fld fs0,8(s0) - 360: 0000 unimp - 362: 0100 addi s0,sp,128 - 364: 5d00 lw s0,56(a0) - 366: 0024 addi s1,sp,8 - 368: 0000 unimp - 36a: 0034 addi a3,sp,8 - 36c: 0000 unimp - 36e: 0001 nop - 370: f461 bnez s0,338 <_start-0x7ffffcc8> - 372: 0000 unimp - 374: f800 fsw fs0,48(s0) - 376: 0000 unimp - 378: 0100 addi s0,sp,128 - 37a: 6100 flw fs0,0(a0) - 37c: 0108 addi a0,sp,128 - 37e: 0000 unimp - 380: 0110 addi a2,sp,128 - 382: 0000 unimp - 384: 0001 nop - 386: 105d c.nop -9 - 388: 0001 nop - 38a: 2800 fld fs0,16(s0) - 38c: 0001 nop - 38e: 0100 addi s0,sp,128 - 390: 6100 flw fs0,0(a0) - 392: 01dc addi a5,sp,196 - 394: 0000 unimp - 396: 01e4 addi s1,sp,204 - 398: 0000 unimp - 39a: 0001 nop - 39c: 9c61 0x9c61 - 39e: 0002 c.slli64 zero - 3a0: 0800 addi s0,sp,16 - 3a2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 3a6: 5d00 lw s0,56(a0) - 3a8: 0308 addi a0,sp,384 - 3aa: 0000 unimp - 3ac: 030c addi a1,sp,384 - 3ae: 0000 unimp - 3b0: 0001 nop - 3b2: 0c61 addi s8,s8,24 - 3b4: d4000003 lb zero,-704(zero) # fffffd40 <__BSS_END__+0x7ffe8fc8> - 3b8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 3bc: 5d00 lw s0,56(a0) - 3be: 0428 addi a0,sp,520 - 3c0: 0000 unimp - 3c2: 0434 addi a3,sp,520 - 3c4: 0000 unimp - 3c6: 0001 nop - 3c8: 005d c.nop 23 - 3ca: 0000 unimp - 3cc: 0000 unimp - 3ce: 0000 unimp - 3d0: 1000 addi s0,sp,32 - 3d2: 0000 unimp - 3d4: 6400 flw fs0,8(s0) - 3d6: 0000 unimp - 3d8: 0100 addi s0,sp,128 - 3da: 5a00 lw s0,48(a2) - 3dc: 0064 addi s1,sp,12 - 3de: 0000 unimp - 3e0: 00b4 addi a3,sp,72 - 3e2: 0000 unimp - 3e4: 0001 nop - 3e6: f456 fsw fs5,40(sp) - 3e8: 0000 unimp - 3ea: 9c00 0x9c00 - 3ec: 0001 nop - 3ee: 0100 addi s0,sp,128 - 3f0: 5600 lw s0,40(a2) - 3f2: 01dc addi a5,sp,196 - 3f4: 0000 unimp - 3f6: 01fc addi a5,sp,204 - 3f8: 0000 unimp - 3fa: 0001 nop - 3fc: fc56 fsw fs5,56(sp) - 3fe: 0001 nop - 400: 0400 addi s0,sp,512 - 402: 0002 c.slli64 zero - 404: 0100 addi s0,sp,128 - 406: 5a00 lw s0,48(a2) - 408: 0210 addi a2,sp,256 - 40a: 0000 unimp - 40c: 0324 addi s1,sp,392 - 40e: 0000 unimp - 410: 0001 nop - 412: 2456 fld fs0,336(sp) - 414: 34000003 lb zero,832(zero) # 340 <_start-0x7ffffcc0> - 418: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 41c: 5a00 lw s0,48(a2) - 41e: 0334 addi a3,sp,392 - 420: 0000 unimp - 422: 0414 addi a3,sp,512 - 424: 0000 unimp - 426: 0006 c.slli zero,0x1 - 428: 007a c.slli zero,0x1e - 42a: 9f24007b 0x9f24007b - 42e: 0428 addi a0,sp,520 - 430: 0000 unimp - 432: 0434 addi a3,sp,520 - 434: 0000 unimp - 436: 0001 nop - 438: 0056 c.slli zero,0x15 - 43a: 0000 unimp - 43c: 0000 unimp - 43e: 0000 unimp - 440: 1000 addi s0,sp,32 - 442: 0000 unimp - 444: 7c00 flw fs0,56(s0) - 446: 0000 unimp - 448: 0100 addi s0,sp,128 - 44a: 5b00 lw s0,48(a4) - 44c: 00f4 addi a3,sp,76 - 44e: 0000 unimp - 450: 0148 addi a0,sp,132 - 452: 0000 unimp - 454: 0001 nop - 456: 0001485b 0x1485b - 45a: 6400 flw fs0,8(s0) - 45c: 0001 nop - 45e: 0100 addi s0,sp,128 - 460: 5f00 lw s0,56(a4) - 462: 01dc addi a5,sp,196 - 464: 0000 unimp - 466: 01f8 addi a4,sp,204 - 468: 0000 unimp - 46a: 0001 nop - 46c: 0001f85b 0x1f85b - 470: 0800 addi s0,sp,16 - 472: 0002 c.slli64 zero - 474: 0100 addi s0,sp,128 - 476: 5f00 lw s0,56(a4) - 478: 0210 addi a2,sp,256 - 47a: 0000 unimp - 47c: 0258 addi a4,sp,260 - 47e: 0000 unimp - 480: 0001 nop - 482: 9861 andi s0,s0,-8 - 484: 0002 c.slli64 zero - 486: 9c00 0x9c00 - 488: 0002 c.slli64 zero - 48a: 0100 addi s0,sp,128 - 48c: 5f00 lw s0,56(a4) - 48e: 029c addi a5,sp,320 - 490: 0000 unimp - 492: 02b4 addi a3,sp,328 - 494: 0000 unimp - 496: 0001 nop - 498: 0002b45b 0x2b45b - 49c: ec00 fsw fs0,24(s0) - 49e: 0002 c.slli64 zero - 4a0: 0100 addi s0,sp,128 - 4a2: 5f00 lw s0,56(a4) - 4a4: 02ec addi a1,sp,332 - 4a6: 0000 unimp - 4a8: 02f0 addi a2,sp,332 - 4aa: 0000 unimp - 4ac: 0001 nop - 4ae: 0002f05b 0x2f05b - 4b2: 1c00 addi s0,sp,560 - 4b4: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4b8: 5f00 lw s0,56(a4) - 4ba: 0334 addi a3,sp,392 - 4bc: 0000 unimp - 4be: 03b4 addi a3,sp,456 - 4c0: 0000 unimp - 4c2: 0001 nop - 4c4: b456 fsd fs5,40(sp) - 4c6: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> - 4ca: 0004 0x4 - 4cc: 0100 addi s0,sp,128 - 4ce: 5f00 lw s0,56(a4) - 4d0: 0428 addi a0,sp,520 - 4d2: 0000 unimp - 4d4: 042c addi a1,sp,520 - 4d6: 0000 unimp - 4d8: 0001 nop - 4da: 00042c5b 0x42c5b - 4de: 3400 fld fs0,40(s0) - 4e0: 0004 0x4 - 4e2: 0100 addi s0,sp,128 - 4e4: 5f00 lw s0,56(a4) - ... - 4ee: 01f8 addi a4,sp,204 - 4f0: 0000 unimp - 4f2: 0220 addi s0,sp,264 - 4f4: 0000 unimp - 4f6: 0001 nop - 4f8: 0003345b 0x3345b - 4fc: 3800 fld fs0,48(s0) - 4fe: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 502: 5e00 lw s0,56(a2) - ... - 50c: 00ec addi a1,sp,76 - 50e: 0000 unimp - 510: 00f4 addi a3,sp,76 - 512: 0000 unimp - 514: 0001 nop - 516: b45e fsd fs7,40(sp) - 518: 28000003 lb zero,640(zero) # 280 <_start-0x7ffffd80> - 51c: 0004 0x4 - 51e: 0100 addi s0,sp,128 - 520: 5e00 lw s0,56(a2) - ... - 52a: 0148 addi a0,sp,132 - 52c: 0000 unimp - 52e: 014c addi a1,sp,132 - 530: 0000 unimp - 532: 0002 c.slli64 zero - 534: 9f31 0x9f31 - 536: 014c addi a1,sp,132 - 538: 0000 unimp - 53a: 01d4 addi a3,sp,196 - 53c: 0000 unimp - 53e: 0001 nop - 540: 0002985b 0x2985b - 544: 9c00 0x9c00 - 546: 0002 c.slli64 zero - 548: 0100 addi s0,sp,128 - 54a: 5b00 lw s0,48(a4) - ... - 554: 01f0 addi a2,sp,204 - 556: 0000 unimp - 558: 0200 addi s0,sp,256 - 55a: 0000 unimp - 55c: 0001 nop - 55e: 005d c.nop 23 - 560: 20000003 lb zero,512(zero) # 200 <_start-0x7ffffe00> - 564: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 568: 6000 flw fs0,0(s0) - ... - 572: 004c addi a1,sp,4 - 574: 0000 unimp - 576: 006c addi a1,sp,12 - 578: 0000 unimp - 57a: 0001 nop - 57c: 405e 0x405e - 57e: 0001 nop - 580: 4c00 lw s0,24(s0) - 582: 0001 nop - 584: 0100 addi s0,sp,128 - 586: 5e00 lw s0,56(a2) - 588: 01f0 addi a2,sp,204 - 58a: 0000 unimp - 58c: 020c addi a1,sp,256 - 58e: 0000 unimp - 590: 0001 nop - 592: d45e sw s7,40(sp) - 594: 0002 c.slli64 zero - 596: ec00 fsw fs0,24(s0) - 598: 0002 c.slli64 zero - 59a: 0100 addi s0,sp,128 - 59c: 5b00 lw s0,48(a4) - 59e: 0300 addi s0,sp,384 - 5a0: 0000 unimp - 5a2: 041c addi a5,sp,512 - 5a4: 0000 unimp - 5a6: 0001 nop - 5a8: 0000005b 0x5b - 5ac: 0000 unimp - 5ae: 0000 unimp - 5b0: 2000 fld fs0,0(s0) - 5b2: 0000 unimp - 5b4: 5000 lw s0,32(s0) - 5b6: 0000 unimp - 5b8: 0100 addi s0,sp,128 - 5ba: 5c00 lw s0,56(s0) - 5bc: 0050 addi a2,sp,4 - 5be: 0000 unimp - 5c0: 005c addi a5,sp,4 - 5c2: 0000 unimp - 5c4: 0009 c.nop 2 - 5c6: 007c addi a5,sp,12 - 5c8: 007e c.slli zero,0x1f - 5ca: ff08 fsw fa0,56(a4) - 5cc: 241a fld fs0,384(sp) - 5ce: 5c9f 0000 ec00 0xec0000005c9f - 5d4: 0000 unimp - 5d6: 0100 addi s0,sp,128 - 5d8: 6000 flw fs0,0(s0) - 5da: 00f4 addi a3,sp,76 - 5dc: 0000 unimp - 5de: 0108 addi a0,sp,128 - 5e0: 0000 unimp - 5e2: 0001 nop - 5e4: 005c addi a5,sp,4 - 5e6: 0000 unimp - 5e8: 0000 unimp - 5ea: 0000 unimp - 5ec: 3400 fld fs0,40(s0) - 5ee: 0000 unimp - 5f0: 4400 lw s0,8(s0) - 5f2: 0000 unimp - 5f4: 0100 addi s0,sp,128 - 5f6: 5d00 lw s0,56(a0) - ... - 600: 0068 addi a0,sp,12 - 602: 0000 unimp - 604: 00cc addi a1,sp,68 - 606: 0000 unimp - 608: 0001 nop - 60a: cc5a sw s6,24(sp) - 60c: 0000 unimp - 60e: ec00 fsw fs0,24(s0) - 610: 0000 unimp - 612: 0500 addi s0,sp,640 - 614: 8000 0x8000 - 616: 4000 lw s0,0(s0) - 618: 9f25 0x9f25 - ... - 622: 0074 addi a3,sp,12 - 624: 0000 unimp - 626: 00ec addi a1,sp,76 - 628: 0000 unimp - 62a: 0001 nop - 62c: 005c addi a5,sp,4 - 62e: 0000 unimp - 630: 0000 unimp - 632: 0000 unimp - 634: 7c00 flw fs0,56(s0) - 636: 0000 unimp - 638: 9800 0x9800 - 63a: 0000 unimp - 63c: 0100 addi s0,sp,128 - 63e: 5b00 lw s0,48(a4) - 640: 0098 addi a4,sp,64 - 642: 0000 unimp - 644: 00e8 addi a0,sp,76 - 646: 0000 unimp - 648: 0001 nop - 64a: 005e c.slli zero,0x17 - 64c: 0000 unimp - 64e: 0000 unimp - 650: 0000 unimp - 652: bc00 fsd fs0,56(s0) - 654: 0000 unimp - 656: d800 sw s0,48(s0) - 658: 0000 unimp - 65a: 0100 addi s0,sp,128 - 65c: 5d00 lw s0,56(a0) - 65e: 00d8 addi a4,sp,68 - 660: 0000 unimp - 662: 00ec addi a1,sp,76 - 664: 0000 unimp - 666: 0001 nop - 668: 005a c.slli zero,0x16 - 66a: 0000 unimp - 66c: 0000 unimp - 66e: 0000 unimp - 670: 7400 flw fs0,40(s0) - 672: 0000 unimp - 674: 8000 0x8000 - 676: 0000 unimp - 678: 0100 addi s0,sp,128 - 67a: 5e00 lw s0,56(a2) - 67c: 0088 addi a0,sp,64 - 67e: 0000 unimp - 680: 0094 addi a3,sp,64 - 682: 0000 unimp - 684: 0001 nop - 686: 985d andi s0,s0,-9 - 688: 0000 unimp - 68a: bc00 fsd fs0,56(s0) - 68c: 0000 unimp - 68e: 0100 addi s0,sp,128 - 690: 5d00 lw s0,56(a0) - ... - 69a: 00b0 addi a2,sp,72 - 69c: 0000 unimp - 69e: 00c0 addi s0,sp,68 - 6a0: 0000 unimp - 6a2: 0001 nop - 6a4: c85f 0000 d400 0xd4000000c85f - 6aa: 0000 unimp - 6ac: 0100 addi s0,sp,128 - 6ae: 5600 lw s0,40(a2) - ... - 6b8: 0088 addi a0,sp,64 - 6ba: 0000 unimp - 6bc: 00b0 addi a2,sp,72 - 6be: 0000 unimp - 6c0: 0001 nop - 6c2: b05f 0000 c800 0xc8000000b05f - 6c8: 0000 unimp - 6ca: 0600 addi s0,sp,768 - 6cc: 7c00 flw fs0,56(s0) - 6ce: 7b00 flw fs0,48(a4) - 6d0: 1e00 addi s0,sp,816 - 6d2: c89f 0000 ec00 0xec000000c89f - 6d8: 0000 unimp - 6da: 0100 addi s0,sp,128 - 6dc: 5b00 lw s0,48(a4) - ... - 6e6: 03f4 addi a3,sp,460 - 6e8: 0000 unimp - 6ea: 0424 addi s1,sp,520 - 6ec: 0000 unimp - 6ee: 0001 nop - 6f0: 0061 c.nop 24 - 6f2: 0000 unimp - 6f4: 0000 unimp - 6f6: 0000 unimp - 6f8: f400 fsw fs0,40(s0) - 6fa: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - 6fe: 0004 0x4 - 700: 1000 addi s0,sp,32 - 702: 8c00 0x8c00 - 704: 0a00 addi s0,sp,272 - 706: ffff 0xffff - 708: 7d1a flw fs10,164(sp) - 70a: 0a00 addi s0,sp,272 - 70c: ffff 0xffff - 70e: 401a 0x401a - 710: 2224 fld fs1,64(a2) - 712: 089f 0004 1000 0x10000004089f - 718: 0004 0x4 - 71a: 1500 addi s0,sp,672 - 71c: 8c00 0x8c00 - 71e: 0a00 addi s0,sp,272 - 720: ffff 0xffff - 722: 8c1a mv s8,t1 - 724: 4000 lw s0,0(s0) - 726: 7625 lui a2,0xfffe9 - 728: 2200 fld fs0,0(a2) - 72a: ff0a fsw ft2,188(sp) - 72c: 1aff 0x1aff - 72e: 2440 fld fs0,136(s0) - 730: 9f22 add t5,t5,s0 - ... - 73a: 0334 addi a3,sp,392 - 73c: 0000 unimp - 73e: 0378 addi a4,sp,396 - 740: 0000 unimp - 742: 0001 nop - 744: 786d lui a6,0xffffb - 746: d4000003 lb zero,-704(zero) # fffffd40 <__BSS_END__+0x7ffe8fc8> - 74a: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - 74e: 7d00 flw fs0,56(a0) - 750: 4000 lw s0,0(s0) - 752: 9f25 0x9f25 - ... - 75c: 0334 addi a3,sp,392 - 75e: 0000 unimp - 760: 037c addi a5,sp,396 - 762: 0000 unimp - 764: 0001 nop - 766: 7c5f 0003 d400 0xd40000037c5f - 76c: 07000003 lb zero,112(zero) # 70 <_start-0x7fffff90> - 770: 7d00 flw fs0,56(a0) - 772: 4000 lw s0,0(s0) - 774: 4024 lw s1,64(s0) - 776: 9f25 0x9f25 - ... - 780: 0338 addi a4,sp,392 - 782: 0000 unimp - 784: 0354 addi a3,sp,388 - 786: 0000 unimp - 788: 0001 nop - 78a: 545e lw s0,244(sp) - 78c: a8000003 lb zero,-1408(zero) # fffffa80 <__BSS_END__+0x7ffe8d08> - 790: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 794: 6c00 flw fs0,24(s0) - ... - 79e: 0370 addi a2,sp,396 - 7a0: 0000 unimp - 7a2: 0394 addi a3,sp,448 - 7a4: 0000 unimp - 7a6: 0001 nop - 7a8: 9460 0x9460 - 7aa: b4000003 lb zero,-1216(zero) # fffffb40 <__BSS_END__+0x7ffe8dc8> - 7ae: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 7b2: 5e00 lw s0,56(a2) - ... - 7bc: 0334 addi a3,sp,392 - 7be: 0000 unimp - 7c0: 033c addi a5,sp,392 - 7c2: 0000 unimp - 7c4: 0001 nop - 7c6: 4461 li s0,24 - 7c8: 50000003 lb zero,1280(zero) # 500 <_start-0x7ffffb00> - 7cc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 7d0: 6000 flw fs0,0(s0) - 7d2: 0350 addi a2,sp,388 - 7d4: 0000 unimp - 7d6: 0354 addi a3,sp,388 - 7d8: 0000 unimp - 7da: 0008 0x8 - 7dc: 0076 c.slli zero,0x1d - 7de: 2540 fld fs0,136(a0) - 7e0: 0081 addi ra,ra,0 - 7e2: 9f21 0x9f21 - 7e4: 0354 addi a3,sp,388 - 7e6: 0000 unimp - 7e8: 0370 addi a2,sp,396 - 7ea: 0000 unimp - 7ec: 0001 nop - 7ee: 0060 addi s0,sp,12 - 7f0: 0000 unimp - 7f2: 0000 unimp - 7f4: 0000 unimp - 7f6: 6c00 flw fs0,24(s0) - 7f8: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> - 7fc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 800: 6100 flw fs0,0(a0) - 802: 0384 addi s1,sp,448 - 804: 0000 unimp - 806: 0390 addi a2,sp,448 - 808: 0000 unimp - 80a: 0001 nop - 80c: 905f 0003 9400 0x94000003905f - 812: 0a000003 lb zero,160(zero) # a0 <_start-0x7fffff60> - 816: 7600 flw fs0,40(a2) - 818: 4000 lw s0,0(s0) - 81a: 4024 lw s1,64(s0) - 81c: 8125 srli a0,a0,0x9 - 81e: 2100 fld fs0,0(a0) - 820: 949f 0003 0000 0x3949f - 826: 0004 0x4 - 828: 0100 addi s0,sp,128 - 82a: 5f00 lw s0,56(a4) - ... - 834: 0344 addi s1,sp,388 - 836: 0000 unimp - 838: 0378 addi a4,sp,396 - 83a: 0000 unimp - 83c: 0001 nop - 83e: 786e flw fa6,248(sp) - 840: b0000003 lb zero,-1280(zero) # fffffb00 <__BSS_END__+0x7ffe8d88> - 844: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 848: 6d00 flw fs0,24(a0) - 84a: 03b0 addi a2,sp,456 - 84c: 0000 unimp - 84e: 03b8 addi a4,sp,456 - 850: 0000 unimp - 852: 000a c.slli zero,0x2 - 854: 007d c.nop 31 - 856: 2440 fld fs0,136(s0) - 858: 2540 fld fs0,136(a0) - 85a: 0080 addi s0,sp,64 - 85c: 9f1e add t5,t5,t2 - ... - 866: 03cc addi a1,sp,452 - 868: 0000 unimp - 86a: 0410 addi a2,sp,512 - 86c: 0000 unimp - 86e: 0001 nop - 870: 006c addi a1,sp,12 - 872: 0000 unimp - 874: 0000 unimp - 876: 0000 unimp - 878: cc00 sw s0,24(s0) - 87a: d8000003 lb zero,-640(zero) # fffffd80 <__BSS_END__+0x7ffe9008> - 87e: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 882: 7600 flw fs0,40(a2) - 884: 7c00 flw fs0,56(s0) - 886: 1e00 addi s0,sp,816 - 888: d89f 0003 dc00 0xdc000003d89f - 88e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 892: 5600 lw s0,40(a2) - 894: 03dc addi a5,sp,452 - 896: 0000 unimp - 898: 03e4 addi s1,sp,460 - 89a: 0000 unimp - 89c: 0009 c.nop 2 - 89e: 7f8d lui t6,0xfffe3 - 8a0: 007e c.slli zero,0x1f - 8a2: 7c1a flw fs8,164(sp) - 8a4: 1e00 addi s0,sp,816 - 8a6: e49f 0003 0800 0x8000003e49f - 8ac: 0004 0x4 - 8ae: 0100 addi s0,sp,128 - 8b0: 5d00 lw s0,56(a0) - 8b2: 0408 addi a0,sp,512 - 8b4: 0000 unimp - 8b6: 0410 addi a2,sp,512 - 8b8: 0000 unimp - 8ba: 0008 0x8 - 8bc: 008c addi a1,sp,64 - 8be: 2540 fld fs0,136(a0) - 8c0: 0076 c.slli zero,0x1d - 8c2: 9f22 add t5,t5,s0 - ... - 8cc: 03d0 addi a2,sp,452 - 8ce: 0000 unimp - 8d0: 0428 addi a0,sp,520 - 8d2: 0000 unimp - 8d4: 0001 nop - 8d6: 0060 addi s0,sp,12 - 8d8: 0000 unimp - 8da: 0000 unimp - 8dc: 0000 unimp - 8de: e400 fsw fs0,8(s0) - 8e0: f4000003 lb zero,-192(zero) # ffffff40 <__BSS_END__+0x7ffe91c8> - 8e4: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 8e8: 6100 flw fs0,0(a0) - ... - 8f2: 03bc addi a5,sp,456 - 8f4: 0000 unimp - 8f6: 03d8 addi a4,sp,452 - 8f8: 0000 unimp - 8fa: 0001 nop - 8fc: d856 sw s5,48(sp) - 8fe: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - 902: 0004 0x4 - 904: 0600 addi s0,sp,768 - 906: 8d00 0x8d00 - 908: 7e7f 0x7e7f - 90a: 1a00 addi s0,sp,304 - 90c: 049f 0004 2000 0x20000004049f - 912: 0004 0x4 - 914: 0600 addi s0,sp,768 - 916: 7e00 flw fs0,56(a2) - 918: 7f00 flw fs0,56(a4) - 91a: 1a00 addi s0,sp,304 - 91c: 209f 0004 2400 0x24000004209f - 922: 0004 0x4 - 924: 0600 addi s0,sp,768 - 926: 8d00 0x8d00 - 928: 7e7f 0x7e7f - 92a: 1a00 addi s0,sp,304 - 92c: 249f 0004 2800 0x28000004249f - 932: 0004 0x4 - 934: 0600 addi s0,sp,768 - 936: 7e00 flw fs0,56(a2) - 938: 8d01 sub a0,a0,s0 - 93a: 1a7f 0x1a7f - 93c: 009f 0000 0000 0x9f - 942: 0000 unimp - 944: c400 sw s0,8(s0) - 946: d0000003 lb zero,-768(zero) # fffffd00 <__BSS_END__+0x7ffe8f88> - 94a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 94e: 6000 flw fs0,0(s0) - ... - 958: 03c0 addi s0,sp,452 - 95a: 0000 unimp - 95c: 03e4 addi s1,sp,460 - 95e: 0000 unimp - 960: 0001 nop - 962: e461 bnez s0,a2a <_start-0x7ffff5d6> - 964: 24000003 lb zero,576(zero) # 240 <_start-0x7ffffdc0> - 968: 0004 0x4 - 96a: 0500 addi s0,sp,640 - 96c: 7e00 flw fs0,56(a2) - 96e: 4000 lw s0,0(s0) - 970: 9f25 0x9f25 - 972: 0424 addi s1,sp,520 - 974: 0000 unimp - 976: 0428 addi a0,sp,520 - 978: 0000 unimp - 97a: 0005 c.nop 1 - 97c: 017e slli sp,sp,0x1f - 97e: 2540 fld fs0,136(a0) - 980: 009f 0000 0000 0x9f - 986: 0000 unimp - 988: c800 sw s0,16(s0) - 98a: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe9188> - 98e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 992: 5c00 lw s0,56(s0) - ... - 99c: 0114 addi a3,sp,128 - 99e: 0000 unimp - 9a0: 01d4 addi a3,sp,196 - 9a2: 0000 unimp - 9a4: 0001 nop - 9a6: dc60 sw s0,124(s0) - 9a8: 0001 nop - 9aa: f000 fsw fs0,32(s0) - 9ac: 0001 nop - 9ae: 0100 addi s0,sp,128 - 9b0: 6000 flw fs0,0(s0) - 9b2: 01f0 addi a2,sp,204 - 9b4: 0000 unimp - 9b6: 01f4 addi a3,sp,204 - 9b8: 0000 unimp - 9ba: 0009 c.nop 2 - 9bc: 0080 addi s0,sp,64 - 9be: 007e c.slli zero,0x1f - 9c0: ff08 fsw fa0,56(a4) - 9c2: 241a fld fs0,384(sp) - 9c4: f49f 0001 9c00 0x9c000001f49f - 9ca: 0002 c.slli64 zero - 9cc: 0100 addi s0,sp,128 - 9ce: 6000 flw fs0,0(s0) - ... - 9d8: 0128 addi a0,sp,136 - 9da: 0000 unimp - 9dc: 014c addi a1,sp,132 - 9de: 0000 unimp - 9e0: 0001 nop - 9e2: f061 bnez s0,9a2 <_start-0x7ffff65e> - 9e4: 0001 nop - 9e6: 1000 addi s0,sp,32 - 9e8: 0002 c.slli64 zero - 9ea: 0100 addi s0,sp,128 - 9ec: 6100 flw fs0,0(a0) - ... - 9f6: 0150 addi a2,sp,132 - 9f8: 0000 unimp - 9fa: 01d4 addi a3,sp,196 - 9fc: 0000 unimp - 9fe: 0001 nop - a00: 005c addi a5,sp,4 - a02: 0000 unimp - a04: 0000 unimp - a06: 0000 unimp - a08: 5800 lw s0,48(s0) - a0a: 0001 nop - a0c: b000 fsd fs0,32(s0) - a0e: 0001 nop - a10: 0100 addi s0,sp,128 - a12: 6100 flw fs0,0(a0) - a14: 01b0 addi a2,sp,200 - a16: 0000 unimp - a18: 01d4 addi a3,sp,196 - a1a: 0000 unimp - a1c: 00800007 0x800007 - a20: 2440 fld fs0,136(s0) - a22: 2540 fld fs0,136(a0) - a24: 009f 0000 0000 0x9f - a2a: 0000 unimp - a2c: 6400 flw fs0,8(s0) - a2e: 0001 nop - a30: 8000 0x8000 - a32: 0001 nop - a34: 0100 addi s0,sp,128 - a36: 5f00 lw s0,56(a4) - a38: 0180 addi s0,sp,192 - a3a: 0000 unimp - a3c: 01d0 addi a2,sp,196 - a3e: 0000 unimp - a40: 0001 nop - a42: 005e c.slli zero,0x17 - a44: 0000 unimp - a46: 0000 unimp - a48: 0000 unimp - a4a: a400 fsd fs0,8(s0) - a4c: 0001 nop - a4e: c000 sw s0,0(s0) - a50: 0001 nop - a52: 0100 addi s0,sp,128 - a54: 5d00 lw s0,56(a0) - a56: 01c0 addi s0,sp,196 - a58: 0000 unimp - a5a: 01d4 addi a3,sp,196 - a5c: 0000 unimp - a5e: 0001 nop - a60: 005a c.slli zero,0x16 - a62: 0000 unimp - a64: 0000 unimp - a66: 0000 unimp - a68: 6000 flw fs0,0(s0) - a6a: 0001 nop - a6c: 6800 flw fs0,16(s0) - a6e: 0001 nop - a70: 0100 addi s0,sp,128 - a72: 5e00 lw s0,56(a2) - a74: 0170 addi a2,sp,140 - a76: 0000 unimp - a78: 017c addi a5,sp,140 - a7a: 0000 unimp - a7c: 0001 nop - a7e: 805d srli s0,s0,0x17 - a80: 0001 nop - a82: a400 fsd fs0,8(s0) - a84: 0001 nop - a86: 0100 addi s0,sp,128 - a88: 5d00 lw s0,56(a0) - ... - a92: 0198 addi a4,sp,192 - a94: 0000 unimp - a96: 01a8 addi a0,sp,200 - a98: 0000 unimp - a9a: 0001 nop - a9c: b05f 0001 bc00 0xbc000001b05f - aa2: 0001 nop - aa4: 0100 addi s0,sp,128 - aa6: 5600 lw s0,40(a2) - ... - ab0: 0170 addi a2,sp,140 - ab2: 0000 unimp - ab4: 01b0 addi a2,sp,200 - ab6: 0000 unimp - ab8: 0001 nop - aba: b05a fsd fs6,32(sp) - abc: 0001 nop - abe: d400 sw s0,40(s0) - ac0: 0001 nop - ac2: 0100 addi s0,sp,128 - ac4: 6100 flw fs0,0(a0) - ... - ace: 0210 addi a2,sp,256 - ad0: 0000 unimp - ad2: 029c addi a5,sp,320 - ad4: 0000 unimp - ad6: 0001 nop - ad8: 005a c.slli zero,0x16 - ada: 0000 unimp - adc: 0000 unimp - ade: 0000 unimp - ae0: 1800 addi s0,sp,48 - ae2: 0002 c.slli64 zero - ae4: 6c00 flw fs0,24(s0) - ae6: 0002 c.slli64 zero - ae8: 0100 addi s0,sp,128 - aea: 5f00 lw s0,56(a4) - aec: 026c addi a1,sp,268 - aee: 0000 unimp - af0: 029c addi a5,sp,320 - af2: 0000 unimp - af4: 00800007 0x800007 - af8: 2440 fld fs0,136(s0) - afa: 2540 fld fs0,136(a0) - afc: 009f 0000 0000 0x9f - b02: 0000 unimp - b04: 2000 fld fs0,0(s0) - b06: 0002 c.slli64 zero - b08: 3c00 fld fs0,56(s0) - b0a: 0002 c.slli64 zero - b0c: 0100 addi s0,sp,128 - b0e: 5b00 lw s0,48(a4) - b10: 023c addi a5,sp,264 - b12: 0000 unimp - b14: 029c addi a5,sp,320 - b16: 0000 unimp - b18: 0001 nop - b1a: 005c addi a5,sp,4 - b1c: 0000 unimp - b1e: 0000 unimp - b20: 0000 unimp - b22: 6000 flw fs0,0(s0) - b24: 0002 c.slli64 zero - b26: 7c00 flw fs0,56(s0) - b28: 0002 c.slli64 zero - b2a: 0100 addi s0,sp,128 - b2c: 5d00 lw s0,56(a0) - b2e: 027c addi a5,sp,268 - b30: 0000 unimp - b32: 029c addi a5,sp,320 - b34: 0000 unimp - b36: 0001 nop - b38: 005e c.slli zero,0x17 - b3a: 0000 unimp - b3c: 0000 unimp - b3e: 0000 unimp - b40: 1800 addi s0,sp,48 - b42: 0002 c.slli64 zero - b44: 2400 fld fs0,8(s0) - b46: 0002 c.slli64 zero - b48: 0100 addi s0,sp,128 - b4a: 5e00 lw s0,56(a2) - b4c: 022c addi a1,sp,264 - b4e: 0000 unimp - b50: 0238 addi a4,sp,264 - b52: 0000 unimp - b54: 0001 nop - b56: 3c5e fld fs8,496(sp) - b58: 0002 c.slli64 zero - b5a: 5000 lw s0,32(s0) - b5c: 0002 c.slli64 zero - b5e: 0100 addi s0,sp,128 - b60: 5e00 lw s0,56(a2) - b62: 0250 addi a2,sp,260 - b64: 0000 unimp - b66: 0260 addi s0,sp,268 - b68: 0000 unimp - b6a: 0001 nop - b6c: 005d c.nop 23 - b6e: 0000 unimp - b70: 0000 unimp - b72: 0000 unimp - b74: 5400 lw s0,40(s0) - b76: 0002 c.slli64 zero - b78: 6400 flw fs0,8(s0) - b7a: 0002 c.slli64 zero - b7c: 0100 addi s0,sp,128 - b7e: 5e00 lw s0,56(a2) - b80: 026c addi a1,sp,268 - b82: 0000 unimp - b84: 0278 addi a4,sp,268 - b86: 0000 unimp - b88: 0001 nop - b8a: 7c5f 0002 9c00 0x9c0000027c5f - b90: 0002 c.slli64 zero - b92: 0100 addi s0,sp,128 - b94: 5f00 lw s0,56(a4) - ... - b9e: 022c addi a1,sp,264 - ba0: 0000 unimp - ba2: 0250 addi a2,sp,260 - ba4: 0000 unimp - ba6: 0001 nop - ba8: 505d c.li zero,-9 - baa: 0002 c.slli64 zero - bac: 6800 flw fs0,16(s0) - bae: 0002 c.slli64 zero - bb0: 0600 addi s0,sp,768 - bb2: 7f00 flw fs0,56(a4) - bb4: 7b00 flw fs0,48(a4) - bb6: 1e00 addi s0,sp,816 - bb8: 689f 0002 9400 0x94000002689f - bbe: 0002 c.slli64 zero - bc0: 0100 addi s0,sp,128 - bc2: 5b00 lw s0,48(a4) - bc4: 0294 addi a3,sp,320 - bc6: 0000 unimp - bc8: 029c addi a5,sp,320 - bca: 0000 unimp - bcc: 000a c.slli zero,0x2 - bce: 0080 addi s0,sp,64 - bd0: 2440 fld fs0,136(s0) - bd2: 2540 fld fs0,136(a0) - bd4: 007d c.nop 31 - bd6: 9f1e add t5,t5,t2 - ... - be0: 02a0 addi s0,sp,328 - be2: 0000 unimp - be4: 0308 addi a0,sp,384 - be6: 0000 unimp - be8: 0001 nop - bea: 085d addi a6,a6,23 - bec: 18000003 lb zero,384(zero) # 180 <_start-0x7ffffe80> - bf0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - bf4: 6100 flw fs0,0(a0) - ... - bfe: 02b4 addi a3,sp,328 - c00: 0000 unimp - c02: 02dc addi a5,sp,324 - c04: 0000 unimp - c06: 0001 nop - c08: 005e c.slli zero,0x17 - c0a: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - c0e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - c12: 5e00 lw s0,56(a2) - ... - c20: 0070 addi a2,sp,12 - c22: 0000 unimp - c24: 0006 c.slli zero,0x1 - c26: 935a add t1,t1,s6 - c28: 5b04 lw s1,48(a4) - c2a: 00700493 li s1,7 - c2e: 0000 unimp - c30: 00e0 addi s0,sp,76 - c32: 0000 unimp - c34: 0006 c.slli zero,0x1 - c36: 0af503f3 0xaf503f3 - c3a: 9f25 0x9f25 - c3c: 00e0 addi s0,sp,76 - c3e: 0000 unimp - c40: 0134 addi a3,sp,136 - c42: 0000 unimp - c44: 0006 c.slli zero,0x1 - c46: 935a add t1,t1,s6 - c48: 5b04 lw s1,48(a4) - c4a: 01340493 addi s1,s0,19 - c4e: 0000 unimp - c50: 01a8 addi a0,sp,200 - c52: 0000 unimp - c54: 0006 c.slli zero,0x1 - c56: 0af503f3 0xaf503f3 - c5a: 9f25 0x9f25 - c5c: 01a8 addi a0,sp,200 - c5e: 0000 unimp - c60: 01d0 addi a2,sp,196 - c62: 0000 unimp - c64: 0006 c.slli zero,0x1 - c66: 935a add t1,t1,s6 - c68: 5b04 lw s1,48(a4) - c6a: 01d00493 li s1,29 - c6e: 0000 unimp - c70: 0248 addi a0,sp,260 - c72: 0000 unimp - c74: 0006 c.slli zero,0x1 - c76: 0af503f3 0xaf503f3 - c7a: 9f25 0x9f25 - c7c: 0248 addi a0,sp,260 - c7e: 0000 unimp - c80: 0298 addi a4,sp,320 - c82: 0000 unimp - c84: 0006 c.slli zero,0x1 - c86: 935a add t1,t1,s6 - c88: 5b04 lw s1,48(a4) - c8a: 02980493 addi s1,a6,41 # ffffb029 <__BSS_END__+0x7ffe42b1> - c8e: 0000 unimp - c90: 02a8 addi a0,sp,328 - c92: 0000 unimp - c94: 0006 c.slli zero,0x1 - c96: 0af503f3 0xaf503f3 - c9a: 9f25 0x9f25 - c9c: 02a8 addi a0,sp,328 - c9e: 0000 unimp - ca0: 02f4 addi a3,sp,332 - ca2: 0000 unimp - ca4: 0006 c.slli zero,0x1 - ca6: 935a add t1,t1,s6 - ca8: 5b04 lw s1,48(a4) - caa: 02f40493 addi s1,s0,47 - cae: 0000 unimp - cb0: 0410 addi a2,sp,512 - cb2: 0000 unimp - cb4: 0006 c.slli zero,0x1 - cb6: 0af503f3 0xaf503f3 - cba: 9f25 0x9f25 - ... - cc8: 0068 addi a0,sp,12 - cca: 0000 unimp - ccc: 0006 c.slli zero,0x1 - cce: 935c 0x935c - cd0: 5d04 lw s1,56(a0) - cd2: 00680493 addi s1,a6,6 - cd6: 0000 unimp - cd8: 00e0 addi s0,sp,76 - cda: 0000 unimp - cdc: 0006 c.slli zero,0x1 - cde: 0cf503f3 0xcf503f3 - ce2: 9f25 0x9f25 - ce4: 00e0 addi s0,sp,76 - ce6: 0000 unimp - ce8: 00fc addi a5,sp,76 - cea: 0000 unimp - cec: 0006 c.slli zero,0x1 - cee: 935c 0x935c - cf0: 5d04 lw s1,56(a0) - cf2: 00fc0493 addi s1,s8,15 - cf6: 0000 unimp - cf8: 0248 addi a0,sp,260 - cfa: 0000 unimp - cfc: 0006 c.slli zero,0x1 - cfe: 0cf503f3 0xcf503f3 - d02: 9f25 0x9f25 - d04: 0248 addi a0,sp,260 - d06: 0000 unimp - d08: 02f0 addi a2,sp,332 - d0a: 0000 unimp - d0c: 0006 c.slli zero,0x1 - d0e: 935c 0x935c - d10: 5d04 lw s1,56(a0) - d12: 02f00493 li s1,47 - d16: 0000 unimp - d18: 0410 addi a2,sp,512 - d1a: 0000 unimp - d1c: 0006 c.slli zero,0x1 - d1e: 0cf503f3 0xcf503f3 - d22: 9f25 0x9f25 - ... - d2c: 02a4 addi s1,sp,328 - d2e: 0000 unimp - d30: 02a8 addi a0,sp,328 - d32: 0000 unimp - d34: 0006 c.slli zero,0x1 - d36: 935f 6004 0493 0x4936004935f - ... - d48: 00dc addi a5,sp,68 - d4a: 0000 unimp - d4c: 0006 c.slli zero,0x1 - d4e: 19f2 slli s3,s3,0x3c - d50: 001e c.slli zero,0x7 - d52: 0000 unimp - d54: 00e0 addi s0,sp,76 - d56: 0000 unimp - d58: 040c addi a1,sp,512 - d5a: 0000 unimp - d5c: 0006 c.slli zero,0x1 - d5e: 19f2 slli s3,s3,0x3c - d60: 001e c.slli zero,0x7 - ... - d6e: 0000 unimp - d70: 0018 0x18 - d72: 0000 unimp - d74: 0006 c.slli zero,0x1 - d76: 935c 0x935c - d78: 5d04 lw s1,56(a0) - d7a: 00180493 addi s1,a6,1 - d7e: 0000 unimp - d80: 0034 addi a3,sp,8 - d82: 0000 unimp - d84: 0006 c.slli zero,0x1 - d86: 935c 0x935c - d88: 5e04 lw s1,56(a2) - d8a: 00e00493 li s1,14 - d8e: 0000 unimp - d90: 00e8 addi a0,sp,76 - d92: 0000 unimp - d94: 0006 c.slli zero,0x1 - d96: 935c 0x935c - d98: 5e04 lw s1,56(a2) - d9a: 00f40493 addi s1,s0,15 - d9e: 0000 unimp - da0: 00fc addi a5,sp,76 - da2: 0000 unimp - da4: 0006 c.slli zero,0x1 - da6: 935c 0x935c - da8: 5e04 lw s1,56(a2) - daa: 00fc0493 addi s1,s8,15 - dae: 0000 unimp - db0: 0100 addi s0,sp,128 - db2: 0000 unimp - db4: 0006 c.slli zero,0x1 - db6: 9361 srli a4,a4,0x38 - db8: 5e04 lw s1,56(a2) - dba: 02480493 addi s1,a6,36 - dbe: 0000 unimp - dc0: 02c4 addi s1,sp,324 - dc2: 0000 unimp - dc4: 0006 c.slli zero,0x1 - dc6: 935c 0x935c - dc8: 5d04 lw s1,56(a0) - dca: 00000493 li s1,0 - ... - dd6: 0000 unimp - dd8: 0054 addi a3,sp,4 - dda: 0000 unimp - ddc: 0006 c.slli zero,0x1 - dde: 935a add t1,t1,s6 - de0: 5b04 lw s1,48(a4) - de2: 00540493 addi s1,s0,5 - de6: 0000 unimp - de8: 0060 addi s0,sp,12 - dea: 0000 unimp - dec: 0006 c.slli zero,0x1 - dee: 935a add t1,t1,s6 - df0: 6004 flw fs1,0(s0) - df2: 00e00493 li s1,14 - df6: 0000 unimp - df8: 0134 addi a3,sp,136 - dfa: 0000 unimp - dfc: 0006 c.slli zero,0x1 - dfe: 935a add t1,t1,s6 - e00: 5b04 lw s1,48(a4) - e02: 01a80493 addi s1,a6,26 - e06: 0000 unimp - e08: 01d0 addi a2,sp,196 - e0a: 0000 unimp - e0c: 0006 c.slli zero,0x1 - e0e: 935a add t1,t1,s6 - e10: 5b04 lw s1,48(a4) - e12: 02480493 addi s1,a6,36 - e16: 0000 unimp - e18: 0294 addi a3,sp,320 - e1a: 0000 unimp - e1c: 0006 c.slli zero,0x1 - e1e: 935a add t1,t1,s6 - e20: 5b04 lw s1,48(a4) - e22: 02940493 addi s1,s0,41 - e26: 0000 unimp - e28: 0298 addi a4,sp,320 - e2a: 0000 unimp - e2c: 0006 c.slli zero,0x1 - e2e: 935a add t1,t1,s6 - e30: 6004 flw fs1,0(s0) - e32: 02a80493 addi s1,a6,42 - e36: 0000 unimp - e38: 02d8 addi a4,sp,324 - e3a: 0000 unimp - e3c: 0006 c.slli zero,0x1 - e3e: 935a add t1,t1,s6 - e40: 5b04 lw s1,48(a4) - e42: 00000493 li s1,0 - e46: 0000 unimp - e48: 0000 unimp - e4a: 0000 unimp - e4c: 0004 0x4 - e4e: 0000 unimp - e50: 005c addi a5,sp,4 - e52: 0000 unimp - e54: 0001 nop - e56: 5c5c lw a5,60(s0) - e58: 0000 unimp - e5a: dc00 sw s0,56(s0) - e5c: 0000 unimp - e5e: 0100 addi s0,sp,128 - e60: 6100 flw fs0,0(a0) - e62: 00e0 addi s0,sp,76 - e64: 0000 unimp - e66: 00fc addi a5,sp,76 - e68: 0000 unimp - e6a: 0001 nop - e6c: fc5c fsw fa5,60(s0) - e6e: 0000 unimp - e70: 4800 lw s0,16(s0) - e72: 0002 c.slli64 zero - e74: 0100 addi s0,sp,128 - e76: 6100 flw fs0,0(a0) - e78: 0248 addi a0,sp,260 - e7a: 0000 unimp - e7c: 03dc addi a5,sp,452 - e7e: 0000 unimp - e80: 0001 nop - e82: 005c addi a5,sp,4 - e84: 0000 unimp - e86: 0000 unimp - e88: 0000 unimp - e8a: 0800 addi s0,sp,16 - e8c: 0000 unimp - e8e: 1800 addi s0,sp,48 - e90: 0000 unimp - e92: 0100 addi s0,sp,128 - e94: 5d00 lw s0,56(a0) - e96: 0018 0x18 - e98: 0000 unimp - e9a: 0034 addi a3,sp,8 - e9c: 0000 unimp - e9e: 0001 nop - ea0: e05e fsw fs7,0(sp) - ea2: 0000 unimp - ea4: e800 fsw fs0,16(s0) - ea6: 0000 unimp - ea8: 0100 addi s0,sp,128 - eaa: 5e00 lw s0,56(a2) - eac: 00f4 addi a3,sp,76 - eae: 0000 unimp - eb0: 0114 addi a3,sp,128 - eb2: 0000 unimp - eb4: 0001 nop - eb6: a85e fsd fs7,16(sp) - eb8: 0001 nop - eba: b000 fsd fs0,32(s0) - ebc: 0001 nop - ebe: 0100 addi s0,sp,128 - ec0: 5e00 lw s0,56(a2) - ec2: 0248 addi a0,sp,260 - ec4: 0000 unimp - ec6: 02c4 addi s1,sp,324 - ec8: 0000 unimp - eca: 0001 nop - ecc: c85d beqz s0,f82 <_start-0x7ffff07e> - ece: 0002 c.slli64 zero - ed0: 0c00 addi s0,sp,528 - ed2: 0004 0x4 - ed4: 0100 addi s0,sp,128 - ed6: 5d00 lw s0,56(a0) - ... - ee0: 000c 0xc - ee2: 0000 unimp - ee4: 0064 addi s1,sp,12 - ee6: 0000 unimp - ee8: 0001 nop - eea: 645a flw fs0,148(sp) - eec: 0000 unimp - eee: a800 fsd fs0,16(s0) - ef0: 0000 unimp - ef2: 0100 addi s0,sp,128 - ef4: 5f00 lw s0,56(a4) - ef6: 00d4 addi a3,sp,68 - ef8: 0000 unimp - efa: 00dc addi a5,sp,68 - efc: 0000 unimp - efe: 0001 nop - f00: e05f 0000 3400 0x34000000e05f - f06: 0001 nop - f08: 0100 addi s0,sp,128 - f0a: 5a00 lw s0,48(a2) - f0c: 01a4 addi s1,sp,200 - f0e: 0000 unimp - f10: 01a8 addi a0,sp,200 - f12: 0000 unimp - f14: 0001 nop - f16: a85f 0001 d000 0xd0000001a85f - f1c: 0001 nop - f1e: 0100 addi s0,sp,128 - f20: 5a00 lw s0,48(a2) - f22: 0248 addi a0,sp,260 - f24: 0000 unimp - f26: 0298 addi a4,sp,320 - f28: 0000 unimp - f2a: 0001 nop - f2c: 9c5a add s8,s8,s6 - f2e: 0002 c.slli64 zero - f30: a800 fsd fs0,16(s0) - f32: 0002 c.slli64 zero - f34: 0100 addi s0,sp,128 - f36: 5f00 lw s0,56(a4) - f38: 02a8 addi a0,sp,328 - f3a: 0000 unimp - f3c: 03f4 addi a3,sp,460 - f3e: 0000 unimp - f40: 0001 nop - f42: fc5a fsw fs6,56(sp) - f44: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> - f48: 0004 0x4 - f4a: 0100 addi s0,sp,128 - f4c: 5e00 lw s0,56(a2) - ... - f56: 0010 0x10 - f58: 0000 unimp - f5a: 0054 addi a3,sp,4 - f5c: 0000 unimp - f5e: 0001 nop - f60: 0000545b 0x545b - f64: 7c00 flw fs0,56(s0) - f66: 0000 unimp - f68: 0100 addi s0,sp,128 - f6a: 6000 flw fs0,0(s0) - f6c: 00e0 addi s0,sp,76 - f6e: 0000 unimp - f70: 014c addi a1,sp,132 - f72: 0000 unimp - f74: 0001 nop - f76: 0001a85b 0x1a85b - f7a: d800 sw s0,48(s0) - f7c: 0001 nop - f7e: 0100 addi s0,sp,128 - f80: 5b00 lw s0,48(a4) - f82: 01d8 addi a4,sp,196 - f84: 0000 unimp - f86: 01dc addi a5,sp,196 - f88: 0000 unimp - f8a: 0001 nop - f8c: dc60 sw s0,124(s0) - f8e: 0001 nop - f90: 1800 addi s0,sp,48 - f92: 0002 c.slli64 zero - f94: 0100 addi s0,sp,128 - f96: 6c00 flw fs0,24(s0) - f98: 0244 addi s1,sp,260 - f9a: 0000 unimp - f9c: 0294 addi a3,sp,320 - f9e: 0000 unimp - fa0: 0001 nop - fa2: 0002945b 0x2945b - fa6: a800 fsd fs0,16(s0) - fa8: 0002 c.slli64 zero - faa: 0100 addi s0,sp,128 - fac: 6000 flw fs0,0(s0) - fae: 02a8 addi a0,sp,328 - fb0: 0000 unimp - fb2: 02d8 addi a4,sp,324 - fb4: 0000 unimp - fb6: 0001 nop - fb8: 0002f05b 0x2f05b - fbc: 4800 lw s0,16(s0) - fbe: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - fc2: 5f00 lw s0,56(a4) - fc4: 037c addi a5,sp,396 - fc6: 0000 unimp - fc8: 03f8 addi a4,sp,460 - fca: 0000 unimp - fcc: 0001 nop - fce: 0003fc5b 0x3fc5b - fd2: 0c00 addi s0,sp,528 - fd4: 0004 0x4 - fd6: 0100 addi s0,sp,128 - fd8: 5b00 lw s0,48(a4) - ... - fe2: 01c4 addi s1,sp,196 - fe4: 0000 unimp - fe6: 01ec addi a1,sp,204 - fe8: 0000 unimp - fea: 0001 nop - fec: f05e fsw fs7,32(sp) - fee: 0002 c.slli64 zero - ff0: f800 fsw fs0,48(s0) - ff2: 0002 c.slli64 zero - ff4: 0100 addi s0,sp,128 - ff6: 5e00 lw s0,56(a2) - ... - 1000: 028c addi a1,sp,320 - 1002: 0000 unimp - 1004: 029c addi a5,sp,320 - 1006: 0000 unimp - 1008: 0002 c.slli64 zero - 100a: 9f31 0x9f31 - ... - 1014: 029c addi a5,sp,320 - 1016: 0000 unimp - 1018: 02a8 addi a0,sp,328 - 101a: 0000 unimp - 101c: 0002 c.slli64 zero - 101e: 9f30 0x9f30 - 1020: 03ec addi a1,sp,460 - 1022: 0000 unimp - 1024: 040c addi a1,sp,512 - 1026: 0000 unimp - 1028: 0002 c.slli64 zero - 102a: 9f30 0x9f30 - ... - 1034: 01bc addi a5,sp,200 - 1036: 0000 unimp - 1038: 01cc addi a1,sp,196 - 103a: 0000 unimp - 103c: 0001 nop - 103e: bc6c fsd fa1,248(s0) - 1040: 0002 c.slli64 zero - 1042: 1000 addi s0,sp,32 - 1044: 0004 0x4 - 1046: 0100 addi s0,sp,128 - 1048: 6d00 flw fs0,24(a0) - ... - 1052: 004c addi a1,sp,4 - 1054: 0000 unimp - 1056: 00dc addi a5,sp,68 - 1058: 0000 unimp - 105a: 0001 nop - 105c: 2c56 fld fs8,336(sp) - 105e: 0001 nop - 1060: a800 fsd fs0,16(s0) - 1062: 0001 nop - 1064: 0100 addi s0,sp,128 - 1066: 5600 lw s0,40(a2) - 1068: 01bc addi a5,sp,200 - 106a: 0000 unimp - 106c: 0248 addi a0,sp,260 - 106e: 0000 unimp - 1070: 0001 nop - 1072: 8056 c.mv zero,s5 - 1074: 0002 c.slli64 zero - 1076: a800 fsd fs0,16(s0) - 1078: 0002 c.slli64 zero - 107a: 0100 addi s0,sp,128 - 107c: 6c00 flw fs0,24(s0) - 107e: 02bc addi a5,sp,328 - 1080: 0000 unimp - 1082: 040c addi a1,sp,512 - 1084: 0000 unimp - 1086: 0001 nop - 1088: 006c addi a1,sp,12 - 108a: 0000 unimp - 108c: 0000 unimp - 108e: 0000 unimp - 1090: 2000 fld fs0,0(s0) - 1092: 0000 unimp - 1094: 6800 flw fs0,16(s0) - 1096: 0000 unimp - 1098: 0100 addi s0,sp,128 - 109a: 5c00 lw s0,56(s0) - 109c: 00e0 addi s0,sp,76 - 109e: 0000 unimp - 10a0: 00f4 addi a3,sp,76 - 10a2: 0000 unimp - 10a4: 0001 nop - 10a6: 005c addi a5,sp,4 - 10a8: 0000 unimp - 10aa: 0000 unimp - 10ac: 0000 unimp - 10ae: 3400 fld fs0,40(s0) - 10b0: 0000 unimp - 10b2: 6c00 flw fs0,24(s0) - 10b4: 0000 unimp - 10b6: 0100 addi s0,sp,128 - 10b8: 5e00 lw s0,56(a2) - ... - 10c2: 0068 addi a0,sp,12 - 10c4: 0000 unimp - 10c6: 00d4 addi a3,sp,68 - 10c8: 0000 unimp - 10ca: 0001 nop - 10cc: 005c addi a5,sp,4 - 10ce: 0000 unimp - 10d0: 0000 unimp - 10d2: 0000 unimp - 10d4: 7400 flw fs0,40(s0) - 10d6: 0000 unimp - 10d8: b800 fsd fs0,48(s0) - 10da: 0000 unimp - 10dc: 0100 addi s0,sp,128 - 10de: 5a00 lw s0,48(a2) - 10e0: 00b8 addi a4,sp,72 - 10e2: 0000 unimp - 10e4: 00d4 addi a3,sp,68 - 10e6: 0000 unimp - 10e8: 00810007 0x810007 - 10ec: 2440 fld fs0,136(s0) - 10ee: 2540 fld fs0,136(a0) - 10f0: 009f 0000 0000 0x9f - 10f6: 0000 unimp - 10f8: b000 fsd fs0,32(s0) - 10fa: 0000 unimp - 10fc: b400 fsd fs0,40(s0) - 10fe: 0000 unimp - 1100: 0100 addi s0,sp,128 - 1102: 5d00 lw s0,56(a0) - ... - 110c: 0074 addi a3,sp,12 - 110e: 0000 unimp - 1110: 0080 addi s0,sp,64 - 1112: 0000 unimp - 1114: 0001 nop - 1116: 885e mv a6,s7 - 1118: 0000 unimp - 111a: b000 fsd fs0,32(s0) - 111c: 0000 unimp - 111e: 0100 addi s0,sp,128 - 1120: 5d00 lw s0,56(a0) - ... - 112a: 00a4 addi s1,sp,72 - 112c: 0000 unimp - 112e: 00bc addi a5,sp,72 - 1130: 0000 unimp - 1132: 0001 nop - 1134: bc5e fsd fs7,56(sp) - 1136: 0000 unimp - 1138: d400 sw s0,40(s0) - 113a: 0000 unimp - 113c: 0100 addi s0,sp,128 - 113e: 5f00 lw s0,56(a4) - ... - 1148: 0088 addi a0,sp,64 - 114a: 0000 unimp - 114c: 00b4 addi a3,sp,72 - 114e: 0000 unimp - 1150: 0001 nop - 1152: b460 fsd fs0,232(s0) - 1154: 0000 unimp - 1156: d400 sw s0,40(s0) - 1158: 0000 unimp - 115a: 0100 addi s0,sp,128 - 115c: 5d00 lw s0,56(a0) - ... - 1166: 0100 addi s0,sp,128 - 1168: 0000 unimp - 116a: 0134 addi a3,sp,136 - 116c: 0000 unimp - 116e: 0001 nop - 1170: a861 j 1208 <_start-0x7fffedf8> - 1172: 0001 nop - 1174: c000 sw s0,0(s0) - 1176: 0001 nop - 1178: 0100 addi s0,sp,128 - 117a: 6100 flw fs0,0(a0) - ... - 1184: 0114 addi a3,sp,128 - 1186: 0000 unimp - 1188: 0134 addi a3,sp,136 - 118a: 0000 unimp - 118c: 0001 nop - 118e: bc5e fsd fs7,56(sp) - 1190: 0001 nop - 1192: c400 sw s0,8(s0) - 1194: 0001 nop - 1196: 0100 addi s0,sp,128 - 1198: 5e00 lw s0,56(a2) - ... - 11a2: 0138 addi a4,sp,136 - 11a4: 0000 unimp - 11a6: 01a8 addi a0,sp,200 - 11a8: 0000 unimp - 11aa: 0001 nop - 11ac: 005e c.slli zero,0x17 - 11ae: 0000 unimp - 11b0: 0000 unimp - 11b2: 0000 unimp - 11b4: 4000 lw s0,0(s0) - 11b6: 0001 nop - 11b8: 8800 0x8800 - 11ba: 0001 nop - 11bc: 0100 addi s0,sp,128 - 11be: 5a00 lw s0,48(a2) - 11c0: 0188 addi a0,sp,192 - 11c2: 0000 unimp - 11c4: 01a8 addi a0,sp,200 - 11c6: 0000 unimp - 11c8: 00810007 0x810007 - 11cc: 2440 fld fs0,136(s0) - 11ce: 2540 fld fs0,136(a0) - 11d0: 009f 0000 0000 0x9f - 11d6: 0000 unimp - 11d8: 4c00 lw s0,24(s0) - 11da: 0001 nop - 11dc: 5800 lw s0,48(s0) - 11de: 0001 nop - 11e0: 0100 addi s0,sp,128 - 11e2: 5b00 lw s0,48(a4) - ... - 11ec: 0180 addi s0,sp,192 - 11ee: 0000 unimp - 11f0: 0184 addi s1,sp,192 - 11f2: 0000 unimp - 11f4: 0001 nop - 11f6: 0000005b 0x5b - 11fa: 0000 unimp - 11fc: 0000 unimp - 11fe: 4800 lw s0,16(s0) - 1200: 0001 nop - 1202: 5000 lw s0,32(s0) - 1204: 0001 nop - 1206: 0100 addi s0,sp,128 - 1208: 5d00 lw s0,56(a0) - 120a: 0158 addi a4,sp,132 - 120c: 0000 unimp - 120e: 0170 addi a2,sp,140 - 1210: 0000 unimp - 1212: 0001 nop - 1214: 705d c.lui zero,0xffff7 - 1216: 0001 nop - 1218: 8000 0x8000 - 121a: 0001 nop - 121c: 0100 addi s0,sp,128 - 121e: 5b00 lw s0,48(a4) - ... - 1228: 0174 addi a3,sp,140 - 122a: 0000 unimp - 122c: 018c addi a1,sp,192 - 122e: 0000 unimp - 1230: 0001 nop - 1232: 8c5d or s0,s0,a5 - 1234: 0001 nop - 1236: a800 fsd fs0,16(s0) - 1238: 0001 nop - 123a: 0100 addi s0,sp,128 - 123c: 5f00 lw s0,56(a4) - ... - 1246: 0158 addi a4,sp,132 - 1248: 0000 unimp - 124a: 0170 addi a2,sp,140 - 124c: 0000 unimp - 124e: 0001 nop - 1250: 0001845b 0x1845b - 1254: a800 fsd fs0,16(s0) - 1256: 0001 nop - 1258: 0100 addi s0,sp,128 - 125a: 5b00 lw s0,48(a4) - ... - 1264: 01dc addi a5,sp,196 - 1266: 0000 unimp - 1268: 0248 addi a0,sp,260 - 126a: 0000 unimp - 126c: 0001 nop - 126e: 005a c.slli zero,0x16 - 1270: 0000 unimp - 1272: 0000 unimp - 1274: 0000 unimp - 1276: e400 fsw fs0,8(s0) - 1278: 0001 nop - 127a: 2c00 fld fs0,24(s0) - 127c: 0002 c.slli64 zero - 127e: 0100 addi s0,sp,128 - 1280: 5b00 lw s0,48(a4) - 1282: 022c addi a1,sp,264 - 1284: 0000 unimp - 1286: 0248 addi a0,sp,260 - 1288: 0000 unimp - 128a: 00810007 0x810007 - 128e: 2440 fld fs0,136(s0) - 1290: 2540 fld fs0,136(a0) - 1292: 009f 0000 0000 0x9f - 1298: 0000 unimp - 129a: ec00 fsw fs0,24(s0) - 129c: 0001 nop - 129e: f800 fsw fs0,48(s0) - 12a0: 0001 nop - 12a2: 0100 addi s0,sp,128 - 12a4: 5e00 lw s0,56(a2) - ... - 12ae: 0220 addi s0,sp,264 - 12b0: 0000 unimp - 12b2: 0228 addi a0,sp,264 - 12b4: 0000 unimp - 12b6: 0001 nop - 12b8: 005c addi a5,sp,4 - 12ba: 0000 unimp - 12bc: 0000 unimp - 12be: 0000 unimp - 12c0: e400 fsw fs0,8(s0) - 12c2: 0001 nop - 12c4: f000 fsw fs0,32(s0) - 12c6: 0001 nop - 12c8: 0100 addi s0,sp,128 - 12ca: 5d00 lw s0,56(a0) - 12cc: 01f8 addi a4,sp,204 - 12ce: 0000 unimp - 12d0: 0210 addi a2,sp,256 - 12d2: 0000 unimp - 12d4: 0001 nop - 12d6: 105d c.nop -9 - 12d8: 0002 c.slli64 zero - 12da: 2000 fld fs0,0(s0) - 12dc: 0002 c.slli64 zero - 12de: 0100 addi s0,sp,128 - 12e0: 5c00 lw s0,56(s0) - ... - 12ea: 0214 addi a3,sp,256 - 12ec: 0000 unimp - 12ee: 0224 addi s1,sp,264 - 12f0: 0000 unimp - 12f2: 0001 nop - 12f4: 2c5d jal 15aa <_start-0x7fffea56> - 12f6: 0002 c.slli64 zero - 12f8: 4800 lw s0,16(s0) - 12fa: 0002 c.slli64 zero - 12fc: 0100 addi s0,sp,128 - 12fe: 5b00 lw s0,48(a4) - ... - 1308: 01f8 addi a4,sp,204 - 130a: 0000 unimp - 130c: 0228 addi a0,sp,264 - 130e: 0000 unimp - 1310: 0001 nop - 1312: 285e fld fa6,464(sp) - 1314: 0002 c.slli64 zero - 1316: 4800 lw s0,16(s0) - 1318: 0002 c.slli64 zero - 131a: 0100 addi s0,sp,128 - 131c: 5c00 lw s0,56(s0) - ... - 1326: 024c addi a1,sp,260 - 1328: 0000 unimp - 132a: 02c4 addi s1,sp,324 - 132c: 0000 unimp - 132e: 0001 nop - 1330: 005d c.nop 23 - 1332: 0000 unimp - 1334: 0000 unimp - 1336: 0000 unimp - 1338: 6000 flw fs0,0(s0) - 133a: 0002 c.slli64 zero - 133c: a800 fsd fs0,16(s0) - 133e: 0002 c.slli64 zero - 1340: 0100 addi s0,sp,128 - 1342: 5e00 lw s0,56(a2) - 1344: 02bc addi a5,sp,328 - 1346: 0000 unimp - 1348: 02c0 addi s0,sp,324 - 134a: 0000 unimp - 134c: 0001 nop - 134e: 005e c.slli zero,0x17 - 1350: 0000 unimp - 1352: 0000 unimp - 1354: 0000 unimp - 1356: 9000 0x9000 - 1358: 0002 c.slli64 zero - 135a: 9c00 0x9c00 - 135c: 0002 c.slli64 zero - 135e: 0100 addi s0,sp,128 - 1360: 5f00 lw s0,56(a4) - ... - 136a: 03b4 addi a3,sp,456 - 136c: 0000 unimp - 136e: 040c addi a1,sp,512 - 1370: 0000 unimp - 1372: 0001 nop - 1374: 0056 c.slli zero,0x15 - 1376: 0000 unimp - 1378: 0000 unimp - 137a: 0000 unimp - 137c: cc00 sw s0,24(s0) - 137e: e0000003 lb zero,-512(zero) # fffffe00 <__BSS_END__+0x7ffe9088> - 1382: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1386: 5e00 lw s0,56(a2) - 1388: 03e8 addi a0,sp,460 - 138a: 0000 unimp - 138c: 03ec addi a1,sp,460 - 138e: 0000 unimp - 1390: 0001 nop - 1392: ec5c fsw fa5,28(s0) - 1394: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe9188> - 1398: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 139c: 5e00 lw s0,56(a2) - ... - 13a6: 02f4 addi a3,sp,332 - 13a8: 0000 unimp - 13aa: 0338 addi a4,sp,392 - 13ac: 0000 unimp - 13ae: 0001 nop - 13b0: 3860 fld fs0,240(s0) - 13b2: 0c000003 lb zero,192(zero) # c0 <_start-0x7fffff40> - 13b6: 0004 0x4 - 13b8: 0500 addi s0,sp,640 - 13ba: 7d00 flw fs0,56(a0) - 13bc: 4000 lw s0,0(s0) - 13be: 9f25 0x9f25 - ... - 13c8: 02f4 addi a3,sp,332 - 13ca: 0000 unimp - 13cc: 033c addi a5,sp,392 - 13ce: 0000 unimp - 13d0: 0001 nop - 13d2: 00033c5b 0x33c5b - 13d6: 0c00 addi s0,sp,528 - 13d8: 0004 0x4 - 13da: 0700 addi s0,sp,896 - 13dc: 7d00 flw fs0,56(a0) - 13de: 4000 lw s0,0(s0) - 13e0: 4024 lw s1,64(s0) - 13e2: 9f25 0x9f25 - ... - 13ec: 02f8 addi a4,sp,332 - 13ee: 0000 unimp - 13f0: 0314 addi a3,sp,384 - 13f2: 0000 unimp - 13f4: 0001 nop - 13f6: 145e slli s0,s0,0x37 - 13f8: 68000003 lb zero,1664(zero) # 680 <_start-0x7ffff980> - 13fc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1400: 5600 lw s0,40(a2) - ... - 140a: 0330 addi a2,sp,392 - 140c: 0000 unimp - 140e: 0354 addi a3,sp,388 - 1410: 0000 unimp - 1412: 0001 nop - 1414: 5461 li s0,-8 - 1416: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> - 141a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 141e: 5f00 lw s0,56(a4) - ... - 1428: 02f4 addi a3,sp,332 - 142a: 0000 unimp - 142c: 02fc addi a5,sp,332 - 142e: 0000 unimp - 1430: 0001 nop - 1432: 0456 slli s0,s0,0x15 - 1434: 10000003 lb zero,256(zero) # 100 <_start-0x7fffff00> - 1438: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 143c: 6100 flw fs0,0(a0) - 143e: 0314 addi a3,sp,384 - 1440: 0000 unimp - 1442: 0330 addi a2,sp,392 - 1444: 0000 unimp - 1446: 0001 nop - 1448: 0061 c.nop 24 - 144a: 0000 unimp - 144c: 0000 unimp - 144e: 0000 unimp - 1450: 2c00 fld fs0,24(s0) - 1452: 34000003 lb zero,832(zero) # 340 <_start-0x7ffffcc0> - 1456: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 145a: 6e00 flw fs0,24(a2) - 145c: 0344 addi s1,sp,388 - 145e: 0000 unimp - 1460: 0350 addi a2,sp,388 - 1462: 0000 unimp - 1464: 0001 nop - 1466: 0003545b 0x3545b - 146a: f800 fsw fs0,48(s0) - 146c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1470: 5b00 lw s0,48(a4) - ... - 147a: 0304 addi s1,sp,384 - 147c: 0000 unimp - 147e: 032c addi a1,sp,392 - 1480: 0000 unimp - 1482: 0001 nop - 1484: 2c6e fld fs8,216(sp) - 1486: 38000003 lb zero,896(zero) # 380 <_start-0x7ffffc80> - 148a: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 148e: 7b00 flw fs0,48(a4) - 1490: 7e00 flw fs0,56(a2) - 1492: 1e00 addi s0,sp,816 - 1494: 389f 0003 8400 0x84000003389f - 149a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 149e: 6000 flw fs0,0(s0) - ... - 14a8: 038c addi a1,sp,448 - 14aa: 0000 unimp - 14ac: 03c8 addi a0,sp,452 - 14ae: 0000 unimp - 14b0: 0001 nop - 14b2: 005e c.slli zero,0x17 - 14b4: 0000 unimp - 14b6: 0000 unimp - 14b8: 0000 unimp - 14ba: a400 fsd fs0,8(s0) - 14bc: c0000003 lb zero,-1024(zero) # fffffc00 <__BSS_END__+0x7ffe8e88> - 14c0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 14c4: 6000 flw fs0,0(s0) - 14c6: 03c0 addi s0,sp,452 - 14c8: 0000 unimp - 14ca: 03c8 addi a0,sp,452 - 14cc: 0000 unimp - 14ce: 0008 0x8 - 14d0: 007e c.slli zero,0x1f - 14d2: 2540 fld fs0,136(a0) - 14d4: 0081 addi ra,ra,0 - 14d6: 9f22 add t5,t5,s0 - ... - 14e0: 0390 addi a2,sp,448 - 14e2: 0000 unimp - 14e4: 03b0 addi a2,sp,456 - 14e6: 0000 unimp - 14e8: 0001 nop - 14ea: 005f 0000 0000 0x5f - 14f0: 0000 unimp - 14f2: 9800 0x9800 - 14f4: b4000003 lb zero,-1216(zero) # fffffb40 <__BSS_END__+0x7ffe8dc8> - 14f8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 14fc: 5600 lw s0,40(a2) - ... - 1506: 037c addi a5,sp,396 - 1508: 0000 unimp - 150a: 0394 addi a3,sp,448 - 150c: 0000 unimp - 150e: 0001 nop - 1510: 0061 c.nop 24 - 1512: 0000 unimp - 1514: 0000 unimp - 1516: 0000 unimp - 1518: 8800 0x8800 - 151a: 90000003 lb zero,-1792(zero) # fffff900 <__BSS_END__+0x7ffe8b88> - 151e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1522: 5f00 lw s0,56(a4) - 1524: 0390 addi a2,sp,448 - 1526: 0000 unimp - 1528: 03bc addi a5,sp,456 - 152a: 0000 unimp - 152c: 0006 c.slli zero,0x1 - 152e: 7f8e flw ft11,224(sp) - 1530: 007c addi a5,sp,12 - 1532: 9f1a add t5,t5,t1 - 1534: 03bc addi a5,sp,456 - 1536: 0000 unimp - 1538: 03dc addi a5,sp,452 - 153a: 0000 unimp - 153c: 0006 c.slli zero,0x1 - 153e: 007c addi a5,sp,12 - 1540: 007f 0x7f - 1542: 9f1a add t5,t5,t1 - ... - 154c: 0380 addi s0,sp,448 - 154e: 0000 unimp - 1550: 0398 addi a4,sp,448 - 1552: 0000 unimp - 1554: 0001 nop - 1556: 0056 c.slli zero,0x15 - 1558: 0000 unimp - 155a: 0000 unimp - 155c: 0000 unimp - 155e: dc00 sw s0,56(s0) - 1560: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9148> - 1564: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1568: 5c00 lw s0,56(s0) - ... - 1572: 03f0 addi a2,sp,460 - 1574: 0000 unimp - 1576: 0404 addi s1,sp,512 - 1578: 0000 unimp - 157a: 0001 nop - 157c: 005e c.slli zero,0x17 - ... - 1586: 0000 unimp - 1588: 7000 flw fs0,32(s0) - 158a: 0000 unimp - 158c: 0600 addi s0,sp,768 - 158e: 5a00 lw s0,48(a2) - 1590: 935b0493 addi s1,s6,-1739 - 1594: 7004 flw fs1,32(s0) - 1596: 0000 unimp - 1598: e800 fsw fs0,16(s0) - 159a: 0000 unimp - 159c: 0600 addi s0,sp,768 - 159e: f300 fsw fs0,32(a4) - 15a0: 250af503 0x250af503 - 15a4: e89f 0000 f800 0xf8000000e89f - 15aa: 0000 unimp - 15ac: 0600 addi s0,sp,768 - 15ae: 5a00 lw s0,48(a2) - 15b0: 935b0493 addi s1,s6,-1739 - 15b4: f804 fsw fs1,48(s0) - 15b6: 0000 unimp - 15b8: 3000 fld fs0,32(s0) - 15ba: 0001 nop - 15bc: 0600 addi s0,sp,768 - 15be: f300 fsw fs0,32(a4) - 15c0: 250af503 0x250af503 - 15c4: 309f 0001 3300 0x33000001309f - 15ca: 0001 nop - 15cc: 0600 addi s0,sp,768 - 15ce: 5a00 lw s0,48(a2) - 15d0: 935b0493 addi s1,s6,-1739 - 15d4: 3304 fld fs1,32(a4) - 15d6: 0001 nop - 15d8: 4c00 lw s0,24(s0) - 15da: 0001 nop - 15dc: 0600 addi s0,sp,768 - 15de: f300 fsw fs0,32(a4) - 15e0: 250af503 0x250af503 - 15e4: 4c9f 0001 8800 0x880000014c9f - 15ea: 0001 nop - 15ec: 0600 addi s0,sp,768 - 15ee: 5a00 lw s0,48(a2) - 15f0: 935b0493 addi s1,s6,-1739 - 15f4: 8804 0x8804 - 15f6: 0001 nop - 15f8: c800 sw s0,16(s0) - 15fa: 0006 c.slli zero,0x1 - 15fc: 0600 addi s0,sp,768 - 15fe: f300 fsw fs0,32(a4) - 1600: 250af503 0x250af503 - 1604: 009f 0000 0000 0x9f - 160a: 0000 unimp - 160c: 0000 unimp - 160e: 0000 unimp - 1610: 7000 flw fs0,32(s0) - 1612: 0000 unimp - 1614: 0600 addi s0,sp,768 - 1616: 5c00 lw s0,56(s0) - 1618: 935d0493 addi s1,s10,-1739 # 18935 <_start-0x7ffe76cb> - 161c: 7004 flw fs1,32(s0) - 161e: 0000 unimp - 1620: e800 fsw fs0,16(s0) - 1622: 0000 unimp - 1624: 0600 addi s0,sp,768 - 1626: f300 fsw fs0,32(a4) - 1628: 250cf503 0x250cf503 - 162c: e89f 0000 fb00 0xfb000000e89f - 1632: 0000 unimp - 1634: 0600 addi s0,sp,768 - 1636: 5c00 lw s0,56(s0) - 1638: 935d0493 addi s1,s10,-1739 - 163c: fb04 fsw fs1,48(a4) - 163e: 0000 unimp - 1640: 3000 fld fs0,32(s0) - 1642: 0001 nop - 1644: 0600 addi s0,sp,768 - 1646: f300 fsw fs0,32(a4) - 1648: 250cf503 0x250cf503 - 164c: 309f 0001 3300 0x33000001309f - 1652: 0001 nop - 1654: 0600 addi s0,sp,768 - 1656: 5c00 lw s0,56(s0) - 1658: 935d0493 addi s1,s10,-1739 - 165c: 3304 fld fs1,32(a4) - 165e: 0001 nop - 1660: 4c00 lw s0,24(s0) - 1662: 0001 nop - 1664: 0600 addi s0,sp,768 - 1666: f300 fsw fs0,32(a4) - 1668: 250cf503 0x250cf503 - 166c: 4c9f 0001 8800 0x880000014c9f - 1672: 0001 nop - 1674: 0600 addi s0,sp,768 - 1676: 5c00 lw s0,56(s0) - 1678: 935d0493 addi s1,s10,-1739 - 167c: 8804 0x8804 - 167e: 0001 nop - 1680: c800 sw s0,16(s0) - 1682: 0006 c.slli zero,0x1 - 1684: 0600 addi s0,sp,768 - 1686: f300 fsw fs0,32(a4) - 1688: 250cf503 0x250cf503 - 168c: 009f 0000 0000 0x9f - 1692: 0000 unimp - 1694: 0000 unimp - 1696: 0000 unimp - 1698: 7400 flw fs0,40(s0) - 169a: 0000 unimp - 169c: 0200 addi s0,sp,256 - 169e: 3000 fld fs0,32(s0) - 16a0: e89f 0000 8800 0x88000000e89f - 16a6: 0001 nop - 16a8: 0200 addi s0,sp,256 - 16aa: 3000 fld fs0,32(s0) - 16ac: 009f 0000 0000 0x9f - 16b2: 0000 unimp - 16b4: 7000 flw fs0,32(s0) - 16b6: 0000 unimp - 16b8: 7400 flw fs0,40(s0) - 16ba: 0000 unimp - 16bc: 0200 addi s0,sp,256 - 16be: 3000 fld fs0,32(s0) - 16c0: 749f 0000 e800 0xe8000000749f - 16c6: 0000 unimp - 16c8: 0100 addi s0,sp,128 - 16ca: 6600 flw fs0,8(a2) - 16cc: 0188 addi a0,sp,192 - 16ce: 0000 unimp - 16d0: 0568 addi a0,sp,652 - 16d2: 0000 unimp - 16d4: 0001 nop - 16d6: 7c66 flw fs8,120(sp) - 16d8: 0005 c.nop 1 - 16da: c800 sw s0,16(s0) - 16dc: 0006 c.slli zero,0x1 - 16de: 0100 addi s0,sp,128 - 16e0: 6600 flw fs0,8(a2) - ... - 16ea: 0048 addi a0,sp,4 - 16ec: 0000 unimp - 16ee: 055c addi a5,sp,644 - 16f0: 0000 unimp - 16f2: 0006 c.slli zero,0x1 - 16f4: ff080083 lb ra,-16(a6) - 16f8: 9f1a add t5,t5,t1 - 16fa: 057c addi a5,sp,652 - 16fc: 0000 unimp - 16fe: 06c8 addi a0,sp,836 - 1700: 0000 unimp - 1702: 0006 c.slli zero,0x1 - 1704: ff080083 lb ra,-16(a6) - 1708: 9f1a add t5,t5,t1 - ... - 1712: 0044 addi s1,sp,4 - 1714: 0000 unimp - 1716: 0070 addi a2,sp,12 - 1718: 0000 unimp - 171a: 00800007 0x800007 - 171e: ff0a fsw ft2,188(sp) - 1720: 1aff 0x1aff - 1722: 709f 0000 e800 0xe8000000709f - 1728: 0000 unimp - 172a: 0100 addi s0,sp,128 - 172c: 6200 flw fs0,0(a2) - 172e: 00e8 addi a0,sp,76 - 1730: 0000 unimp - 1732: 000000fb 0xfb - 1736: 00800007 0x800007 - 173a: ff0a fsw ft2,188(sp) - 173c: 1aff 0x1aff - 173e: 309f 0001 3300 0x33000001309f - 1744: 0001 nop - 1746: 0700 addi s0,sp,896 - 1748: 8000 0x8000 - 174a: 0a00 addi s0,sp,272 - 174c: ffff 0xffff - 174e: 9f1a add t5,t5,t1 - 1750: 014c addi a1,sp,132 - 1752: 0000 unimp - 1754: 0188 addi a0,sp,192 - 1756: 0000 unimp - 1758: 00800007 0x800007 - 175c: ff0a fsw ft2,188(sp) - 175e: 1aff 0x1aff - 1760: 889f 0001 5800 0x58000001889f - 1766: 0005 c.nop 1 - 1768: 0100 addi s0,sp,128 - 176a: 6200 flw fs0,0(a2) - 176c: 057c addi a5,sp,652 - 176e: 0000 unimp - 1770: 06c8 addi a0,sp,836 - 1772: 0000 unimp - 1774: 0001 nop - 1776: 0062 c.slli zero,0x18 - ... - 1780: 0000 unimp - 1782: 6c00 flw fs0,24(s0) - 1784: 0000 unimp - 1786: 0100 addi s0,sp,128 - 1788: 5a00 lw s0,48(a2) - 178a: 006c addi a1,sp,12 - 178c: 0000 unimp - 178e: 00e8 addi a0,sp,76 - 1790: 0000 unimp - 1792: 0001 nop - 1794: e858 fsw fa4,20(s0) - 1796: 0000 unimp - 1798: f800 fsw fs0,48(s0) - 179a: 0000 unimp - 179c: 0100 addi s0,sp,128 - 179e: 5a00 lw s0,48(a2) - 17a0: 00f8 addi a4,sp,76 - 17a2: 0000 unimp - 17a4: 0124 addi s1,sp,136 - 17a6: 0000 unimp - 17a8: 0001 nop - 17aa: 2466 fld fs0,88(sp) - 17ac: 0001 nop - 17ae: 3000 fld fs0,32(s0) - 17b0: 0001 nop - 17b2: 0100 addi s0,sp,128 - 17b4: 5800 lw s0,48(s0) - 17b6: 0130 addi a2,sp,136 - 17b8: 0000 unimp - 17ba: 00000133 add sp,zero,zero - 17be: 0001 nop - 17c0: 335a fld ft6,432(sp) - 17c2: 0001 nop - 17c4: 4400 lw s0,8(s0) - 17c6: 0001 nop - 17c8: 0100 addi s0,sp,128 - 17ca: 6600 flw fs0,8(a2) - 17cc: 0144 addi s1,sp,132 - 17ce: 0000 unimp - 17d0: 014c addi a1,sp,132 - 17d2: 0000 unimp - 17d4: 0002 c.slli64 zero - 17d6: 9f30 0x9f30 - 17d8: 014c addi a1,sp,132 - 17da: 0000 unimp - 17dc: 0188 addi a0,sp,192 - 17de: 0000 unimp - 17e0: 0001 nop - 17e2: 885a mv a6,s6 - 17e4: 0001 nop - 17e6: 4800 lw s0,16(s0) - 17e8: 0002 c.slli64 zero - 17ea: 0100 addi s0,sp,128 - 17ec: 5800 lw s0,48(s0) - 17ee: 057c addi a5,sp,652 - 17f0: 0000 unimp - 17f2: 05b0 addi a2,sp,712 - 17f4: 0000 unimp - 17f6: 0001 nop - 17f8: bc58 fsd fa4,184(s0) - 17fa: 0005 c.nop 1 - 17fc: d800 sw s0,48(s0) - 17fe: 0005 c.nop 1 - 1800: 0100 addi s0,sp,128 - 1802: 5800 lw s0,48(s0) - 1804: 0688 addi a0,sp,832 - 1806: 0000 unimp - 1808: 069c addi a5,sp,832 - 180a: 0000 unimp - 180c: 0001 nop - 180e: 0058 addi a4,sp,4 - 1810: 0000 unimp - 1812: 0000 unimp - 1814: 0000 unimp - 1816: 4400 lw s0,8(s0) - 1818: 0000 unimp - 181a: 5400 lw s0,40(s0) - 181c: 0000 unimp - 181e: 0100 addi s0,sp,128 - 1820: 5900 lw s0,48(a0) - 1822: 0054 addi a3,sp,4 - 1824: 0000 unimp - 1826: 005c addi a5,sp,4 - 1828: 0000 unimp - 182a: 00790007 0x790007 - 182e: 4040 lw s0,4(s0) - 1830: 2124 fld fs1,64(a0) - 1832: 5c9f 0000 6800 0x680000005c9f - 1838: 0000 unimp - 183a: 0b00 addi s0,sp,400 - 183c: 7b00 flw fs0,48(a4) - 183e: 3c00 fld fs0,56(s0) - 1840: 3c24 fld fs1,120(s0) - 1842: 4025 c.li zero,9 - 1844: 2440 fld fs0,136(s0) - 1846: 9f21 0x9f21 - 1848: 0068 addi a0,sp,12 - 184a: 0000 unimp - 184c: 00e8 addi a0,sp,76 - 184e: 0000 unimp - 1850: 0001 nop - 1852: e865 bnez s0,1942 <_start-0x7fffe6be> - 1854: 0000 unimp - 1856: 1800 addi s0,sp,48 - 1858: 0001 nop - 185a: 0100 addi s0,sp,128 - 185c: 5900 lw s0,48(a0) - 185e: 0120 addi s0,sp,136 - 1860: 0000 unimp - 1862: 0130 addi a2,sp,136 - 1864: 0000 unimp - 1866: 0001 nop - 1868: 3065 jal 1110 <_start-0x7fffeef0> - 186a: 0001 nop - 186c: 4000 lw s0,0(s0) - 186e: 0001 nop - 1870: 0100 addi s0,sp,128 - 1872: 5900 lw s0,48(a0) - 1874: 0144 addi s1,sp,132 - 1876: 0000 unimp - 1878: 014c addi a1,sp,132 - 187a: 0000 unimp - 187c: 0001 nop - 187e: 4c65 li s8,25 - 1880: 0001 nop - 1882: 8800 0x8800 - 1884: 0001 nop - 1886: 0100 addi s0,sp,128 - 1888: 5900 lw s0,48(a0) - 188a: 0188 addi a0,sp,192 - 188c: 0000 unimp - 188e: 0244 addi s1,sp,260 - 1890: 0000 unimp - 1892: 0001 nop - 1894: 7c65 lui s8,0xffff9 - 1896: 0005 c.nop 1 - 1898: b000 fsd fs0,32(s0) - 189a: 0005 c.nop 1 - 189c: 0100 addi s0,sp,128 - 189e: 6500 flw fs0,8(a0) - 18a0: 05bc addi a5,sp,712 - 18a2: 0000 unimp - 18a4: 05d8 addi a4,sp,708 - 18a6: 0000 unimp - 18a8: 0001 nop - 18aa: 8865 andi s0,s0,25 - 18ac: 0006 c.slli zero,0x1 - 18ae: 9c00 0x9c00 - 18b0: 0006 c.slli zero,0x1 - 18b2: 0100 addi s0,sp,128 - 18b4: 6500 flw fs0,8(a0) - ... - 18be: 00b0 addi a2,sp,72 - 18c0: 0000 unimp - 18c2: 00b4 addi a3,sp,72 - 18c4: 0000 unimp - 18c6: 0002 c.slli64 zero - 18c8: 9f30 0x9f30 - 18ca: 00b4 addi a3,sp,72 - 18cc: 0000 unimp - 18ce: 00e8 addi a0,sp,76 - 18d0: 0000 unimp - 18d2: 0001 nop - 18d4: 285f 0002 4000 0x40000002285f - 18da: 0002 c.slli64 zero - 18dc: 0100 addi s0,sp,128 - 18de: 5f00 lw s0,56(a4) - 18e0: 057c addi a5,sp,652 - 18e2: 0000 unimp - 18e4: 0584 addi s1,sp,704 - 18e6: 0000 unimp - 18e8: 0001 nop - 18ea: 885f 0005 9800 0x98000005885f - 18f0: 0005 c.nop 1 - 18f2: 0100 addi s0,sp,128 - 18f4: 5f00 lw s0,56(a4) - 18f6: 05bc addi a5,sp,712 - 18f8: 0000 unimp - 18fa: 05d4 addi a3,sp,708 - 18fc: 0000 unimp - 18fe: 0001 nop - 1900: 005f 0000 0000 0x5f - 1906: 0000 unimp - 1908: 8800 0x8800 - 190a: 0000 unimp - 190c: e800 fsw fs0,16(s0) - 190e: 0000 unimp - 1910: 0600 addi s0,sp,768 - 1912: 8400 0x8400 - 1914: 0800 addi s0,sp,16 - 1916: 1aff 0x1aff - 1918: 889f 0001 6000 0x60000001889f - 191e: 0005 c.nop 1 - 1920: 0600 addi s0,sp,768 - 1922: 8400 0x8400 - 1924: 0800 addi s0,sp,16 - 1926: 1aff 0x1aff - 1928: 7c9f 0005 c800 0xc80000057c9f - 192e: 0006 c.slli zero,0x1 - 1930: 0600 addi s0,sp,768 - 1932: 8400 0x8400 - 1934: 0800 addi s0,sp,16 - 1936: 1aff 0x1aff - 1938: 009f 0000 0000 0x9f - 193e: 0000 unimp - 1940: 8400 0x8400 - 1942: 0000 unimp - 1944: b000 fsd fs0,32(s0) - 1946: 0000 unimp - 1948: 0700 addi s0,sp,896 - 194a: 8000 0x8000 - 194c: 0a00 addi s0,sp,272 - 194e: ffff 0xffff - 1950: 9f1a add t5,t5,t1 - 1952: 00b0 addi a2,sp,72 - 1954: 0000 unimp - 1956: 00e8 addi a0,sp,76 - 1958: 0000 unimp - 195a: 0001 nop - 195c: 885a mv a6,s6 - 195e: 0001 nop - 1960: 9b00 0x9b00 - 1962: 0001 nop - 1964: 0700 addi s0,sp,896 - 1966: 8000 0x8000 - 1968: 0a00 addi s0,sp,272 - 196a: ffff 0xffff - 196c: 9f1a add t5,t5,t1 - 196e: 01d0 addi a2,sp,196 - 1970: 0000 unimp - 1972: 000001d7 vadd.vv v3,v0,v0,v0.t - 1976: 00800007 0x800007 - 197a: ff0a fsw ft2,188(sp) - 197c: 1aff 0x1aff - 197e: f09f 0001 2800 0x28000001f09f - 1984: 0002 c.slli64 zero - 1986: 0700 addi s0,sp,896 - 1988: 8000 0x8000 - 198a: 0a00 addi s0,sp,272 - 198c: ffff 0xffff - 198e: 9f1a add t5,t5,t1 - 1990: 0228 addi a0,sp,264 - 1992: 0000 unimp - 1994: 024c addi a1,sp,260 - 1996: 0000 unimp - 1998: 0001 nop - 199a: 7c5a flw fs8,180(sp) - 199c: 0005 c.nop 1 - 199e: b000 fsd fs0,32(s0) - 19a0: 0005 c.nop 1 - 19a2: 0100 addi s0,sp,128 - 19a4: 5a00 lw s0,48(a2) - 19a6: 05bc addi a5,sp,712 - 19a8: 0000 unimp - 19aa: 05d8 addi a4,sp,708 - 19ac: 0000 unimp - 19ae: 0001 nop - 19b0: 885a mv a6,s6 - 19b2: 0006 c.slli zero,0x1 - 19b4: 8c00 0x8c00 - 19b6: 0006 c.slli zero,0x1 - 19b8: 0100 addi s0,sp,128 - 19ba: 5a00 lw s0,48(a2) - ... - 19c4: 0074 addi a3,sp,12 - 19c6: 0000 unimp - 19c8: 00ac addi a1,sp,72 - 19ca: 0000 unimp - 19cc: 0001 nop - 19ce: 0000ac67 0xac67 - 19d2: e800 fsw fs0,16(s0) - 19d4: 0000 unimp - 19d6: 0100 addi s0,sp,128 - 19d8: 6e00 flw fs0,24(a2) - 19da: 0188 addi a0,sp,192 - 19dc: 0000 unimp - 19de: 01c4 addi s1,sp,196 - 19e0: 0000 unimp - 19e2: 0001 nop - 19e4: 0001c467 0x1c467 - 19e8: d000 sw s0,32(s0) - 19ea: 0001 nop - 19ec: 0100 addi s0,sp,128 - 19ee: 6e00 flw fs0,24(a2) - 19f0: 01d0 addi a2,sp,196 - 19f2: 0000 unimp - 19f4: 01e8 addi a0,sp,204 - 19f6: 0000 unimp - 19f8: 0001 nop - 19fa: 0001e867 0x1e867 - 19fe: f000 fsw fs0,32(s0) - 1a00: 0001 nop - 1a02: 0200 addi s0,sp,256 - 1a04: 3000 fld fs0,32(s0) - 1a06: f09f 0001 2800 0x28000001f09f - 1a0c: 0002 c.slli64 zero - 1a0e: 0100 addi s0,sp,128 - 1a10: 6700 flw fs0,8(a4) - 1a12: 0228 addi a0,sp,264 - 1a14: 0000 unimp - 1a16: 026c addi a1,sp,268 - 1a18: 0000 unimp - 1a1a: 0001 nop - 1a1c: 6c6e flw fs8,216(sp) - 1a1e: 0002 c.slli64 zero - 1a20: b400 fsd fs0,40(s0) - 1a22: 0004 0x4 - 1a24: 0100 addi s0,sp,128 - 1a26: 5b00 lw s0,48(a4) - 1a28: 057c addi a5,sp,652 - 1a2a: 0000 unimp - 1a2c: 0594 addi a3,sp,704 - 1a2e: 0000 unimp - 1a30: 0001 nop - 1a32: bc6e fsd fs11,56(sp) - 1a34: 0005 c.nop 1 - 1a36: cc00 sw s0,24(s0) - 1a38: 0005 c.nop 1 - 1a3a: 0100 addi s0,sp,128 - 1a3c: 6e00 flw fs0,24(a2) - 1a3e: 06bc addi a5,sp,840 - 1a40: 0000 unimp - 1a42: 06c8 addi a0,sp,836 - 1a44: 0000 unimp - 1a46: 0001 nop - 1a48: 0000005b 0x5b - 1a4c: 0000 unimp - 1a4e: 0000 unimp - 1a50: 8400 0x8400 - 1a52: 0000 unimp - 1a54: 9400 0x9400 - 1a56: 0000 unimp - 1a58: 0100 addi s0,sp,128 - 1a5a: 5900 lw s0,48(a0) - 1a5c: 0094 addi a3,sp,64 - 1a5e: 0000 unimp - 1a60: 00a4 addi s1,sp,72 - 1a62: 0000 unimp - 1a64: 00790007 0x790007 - 1a68: 4040 lw s0,4(s0) - 1a6a: 2124 fld fs1,64(a0) - 1a6c: a89f 0000 e800 0xe8000000a89f - 1a72: 0000 unimp - 1a74: 0100 addi s0,sp,128 - 1a76: 5900 lw s0,48(a0) - 1a78: 0188 addi a0,sp,192 - 1a7a: 0000 unimp - 1a7c: 01b8 addi a4,sp,200 - 1a7e: 0000 unimp - 1a80: 0001 nop - 1a82: c059 beqz s0,1b08 <_start-0x7fffe4f8> - 1a84: 0001 nop - 1a86: e400 fsw fs0,8(s0) - 1a88: 0001 nop - 1a8a: 0100 addi s0,sp,128 - 1a8c: 5900 lw s0,48(a0) - 1a8e: 01e8 addi a0,sp,204 - 1a90: 0000 unimp - 1a92: 020c addi a1,sp,256 - 1a94: 0000 unimp - 1a96: 0001 nop - 1a98: 1859 addi a6,a6,-10 - 1a9a: 0002 c.slli64 zero - 1a9c: 1c00 addi s0,sp,560 - 1a9e: 0002 c.slli64 zero - 1aa0: 0100 addi s0,sp,128 - 1aa2: 5900 lw s0,48(a0) - 1aa4: 0228 addi a0,sp,264 - 1aa6: 0000 unimp - 1aa8: 0250 addi a2,sp,260 - 1aaa: 0000 unimp - 1aac: 0001 nop - 1aae: 5459 li s0,-10 - 1ab0: 0002 c.slli64 zero - 1ab2: b800 fsd fs0,48(s0) - 1ab4: 0004 0x4 - 1ab6: 0100 addi s0,sp,128 - 1ab8: 5a00 lw s0,48(a2) - 1aba: 057c addi a5,sp,652 - 1abc: 0000 unimp - 1abe: 0590 addi a2,sp,704 - 1ac0: 0000 unimp - 1ac2: 0001 nop - 1ac4: bc59 j 155a <_start-0x7fffeaa6> - 1ac6: 0005 c.nop 1 - 1ac8: c800 sw s0,16(s0) - 1aca: 0005 c.nop 1 - 1acc: 0100 addi s0,sp,128 - 1ace: 5900 lw s0,48(a0) - 1ad0: 06bc addi a5,sp,840 - 1ad2: 0000 unimp - 1ad4: 06c8 addi a0,sp,836 - 1ad6: 0000 unimp - 1ad8: 0001 nop - 1ada: 005a c.slli zero,0x16 - 1adc: 0000 unimp - 1ade: 0000 unimp - 1ae0: 0000 unimp - 1ae2: 2800 fld fs0,16(s0) - 1ae4: 0002 c.slli64 zero - 1ae6: d000 sw s0,32(s0) - 1ae8: 0004 0x4 - 1aea: 0200 addi s0,sp,256 - 1aec: 3000 fld fs0,32(s0) - 1aee: 7c9f 0005 8800 0x880000057c9f - 1af4: 0005 c.nop 1 - 1af6: 0200 addi s0,sp,256 - 1af8: 3000 fld fs0,32(s0) - 1afa: 8c9f 0005 9800 0x980000058c9f - 1b00: 0005 c.nop 1 - 1b02: 0100 addi s0,sp,128 - 1b04: 6600 flw fs0,8(a2) - 1b06: 0598 addi a4,sp,704 - 1b08: 0000 unimp - 1b0a: 05b0 addi a2,sp,712 - 1b0c: 0000 unimp - 1b0e: 0001 nop - 1b10: c05f 0005 c400 0xc4000005c05f - 1b16: 0005 c.nop 1 - 1b18: 0100 addi s0,sp,128 - 1b1a: 5f00 lw s0,56(a4) - 1b1c: 06bc addi a5,sp,840 - 1b1e: 0000 unimp - 1b20: 06c8 addi a0,sp,836 - 1b22: 0000 unimp - 1b24: 0002 c.slli64 zero - 1b26: 9f30 0x9f30 - ... - 1b30: 00c8 addi a0,sp,68 - 1b32: 0000 unimp - 1b34: 00e8 addi a0,sp,76 - 1b36: 0000 unimp - 1b38: 0001 nop - 1b3a: 285c fld fa5,144(s0) - 1b3c: 0002 c.slli64 zero - 1b3e: 4c00 lw s0,24(s0) - 1b40: 0005 c.nop 1 - 1b42: 0100 addi s0,sp,128 - 1b44: 5c00 lw s0,56(s0) - 1b46: 057c addi a5,sp,652 - 1b48: 0000 unimp - 1b4a: 058c addi a1,sp,704 - 1b4c: 0000 unimp - 1b4e: 0001 nop - 1b50: 8c5c 0x8c5c - 1b52: 0005 c.nop 1 - 1b54: 9800 0x9800 - 1b56: 0005 c.nop 1 - 1b58: 0600 addi s0,sp,768 - 1b5a: 8300 0x8300 - 1b5c: 0800 addi s0,sp,16 - 1b5e: 1aff 0x1aff - 1b60: 989f 0005 c000 0xc0000005989f - 1b66: 0005 c.nop 1 - 1b68: 0100 addi s0,sp,128 - 1b6a: 5c00 lw s0,56(s0) - 1b6c: 05c0 addi s0,sp,708 - 1b6e: 0000 unimp - 1b70: 05c4 addi s1,sp,708 - 1b72: 0000 unimp - 1b74: 0006 c.slli zero,0x1 - 1b76: 0084 addi s1,sp,64 - 1b78: ff08 fsw fa0,56(a4) - 1b7a: 9f1a add t5,t5,t1 - 1b7c: 05c4 addi s1,sp,708 - 1b7e: 0000 unimp - 1b80: 05d0 addi a2,sp,708 - 1b82: 0000 unimp - 1b84: 0001 nop - 1b86: d05c sw a5,36(s0) - 1b88: 0005 c.nop 1 - 1b8a: d800 sw s0,48(s0) - 1b8c: 0005 c.nop 1 - 1b8e: 0600 addi s0,sp,768 - 1b90: 8300 0x8300 - 1b92: 8400 0x8400 - 1b94: 2700 fld fs0,8(a4) - 1b96: d89f 0005 9800 0x98000005d89f - 1b9c: 0006 c.slli zero,0x1 - 1b9e: 0100 addi s0,sp,128 - 1ba0: 5c00 lw s0,56(s0) - 1ba2: 069c addi a5,sp,832 - 1ba4: 0000 unimp - 1ba6: 06c8 addi a0,sp,836 - 1ba8: 0000 unimp - 1baa: 0001 nop - 1bac: 005c addi a5,sp,4 - 1bae: 0000 unimp - 1bb0: 0000 unimp - 1bb2: 0000 unimp - 1bb4: cc00 sw s0,24(s0) - 1bb6: 0000 unimp - 1bb8: e800 fsw fs0,16(s0) - 1bba: 0000 unimp - 1bbc: 0100 addi s0,sp,128 - 1bbe: 6000 flw fs0,0(s0) - 1bc0: 0228 addi a0,sp,264 - 1bc2: 0000 unimp - 1bc4: 04d4 addi a3,sp,580 - 1bc6: 0000 unimp - 1bc8: 0001 nop - 1bca: d460 sw s0,108(s0) - 1bcc: 0004 0x4 - 1bce: 3400 fld fs0,40(s0) - 1bd0: 0005 c.nop 1 - 1bd2: 0100 addi s0,sp,128 - 1bd4: 5e00 lw s0,56(a2) - 1bd6: 057c addi a5,sp,652 - 1bd8: 0000 unimp - 1bda: 05b0 addi a2,sp,712 - 1bdc: 0000 unimp - 1bde: 0001 nop - 1be0: bc60 fsd fs0,248(s0) - 1be2: 0005 c.nop 1 - 1be4: d800 sw s0,48(s0) - 1be6: 0005 c.nop 1 - 1be8: 0100 addi s0,sp,128 - 1bea: 6000 flw fs0,0(s0) - 1bec: 05d8 addi a4,sp,708 - 1bee: 0000 unimp - 1bf0: 05e0 addi s0,sp,716 - 1bf2: 0000 unimp - 1bf4: 0001 nop - 1bf6: e05e fsw fs7,0(sp) - 1bf8: 0005 c.nop 1 - 1bfa: 1000 addi s0,sp,32 - 1bfc: 0006 c.slli zero,0x1 - 1bfe: 0100 addi s0,sp,128 - 1c00: 5a00 lw s0,48(a2) - 1c02: 063c addi a5,sp,776 - 1c04: 0000 unimp - 1c06: 064c addi a1,sp,772 - 1c08: 0000 unimp - 1c0a: 0002 c.slli64 zero - 1c0c: 9f30 0x9f30 - 1c0e: 0654 addi a3,sp,772 - 1c10: 0000 unimp - 1c12: 0684 addi s1,sp,832 - 1c14: 0000 unimp - 1c16: 0001 nop - 1c18: 885a mv a6,s6 - 1c1a: 0006 c.slli zero,0x1 - 1c1c: 9c00 0x9c00 - 1c1e: 0006 c.slli zero,0x1 - 1c20: 0100 addi s0,sp,128 - 1c22: 6000 flw fs0,0(s0) - 1c24: 06bc addi a5,sp,840 - 1c26: 0000 unimp - 1c28: 06c8 addi a0,sp,836 - 1c2a: 0000 unimp - 1c2c: 0001 nop - 1c2e: 0060 addi s0,sp,12 - 1c30: 0000 unimp - 1c32: 0000 unimp - 1c34: 0000 unimp - 1c36: 3800 fld fs0,48(s0) - 1c38: 0004 0x4 - 1c3a: 9c00 0x9c00 - 1c3c: 0004 0x4 - 1c3e: 0100 addi s0,sp,128 - 1c40: 5e00 lw s0,56(a2) - 1c42: 049c addi a5,sp,576 - 1c44: 0000 unimp - 1c46: 04f4 addi a3,sp,588 - 1c48: 0000 unimp - 1c4a: 0001 nop - 1c4c: f46e fsw fs11,40(sp) - 1c4e: 0004 0x4 - 1c50: f800 fsw fs0,48(s0) - 1c52: 0004 0x4 - 1c54: 0300 addi s0,sp,384 - 1c56: 7d00 flw fs0,56(a0) - 1c58: 9f7c 0x9f7c - 1c5a: 04f8 addi a4,sp,588 - 1c5c: 0000 unimp - 1c5e: 04fc addi a5,sp,588 - 1c60: 0000 unimp - 1c62: 0001 nop - 1c64: fc5d bnez s0,1c22 <_start-0x7fffe3de> - 1c66: 0004 0x4 - 1c68: 1400 addi s0,sp,544 - 1c6a: 0005 c.nop 1 - 1c6c: 0100 addi s0,sp,128 - 1c6e: 6e00 flw fs0,24(a2) - 1c70: 0514 addi a3,sp,640 - 1c72: 0000 unimp - 1c74: 0520 addi s0,sp,648 - 1c76: 0000 unimp - 1c78: 000a c.slli zero,0x2 - 1c7a: 008e slli ra,ra,0x3 - 1c7c: 00792533 slt a0,s2,t2 - 1c80: 244d jal 1f22 <_start-0x7fffe0de> - 1c82: 9f21 0x9f21 - 1c84: 0520 addi s0,sp,648 - 1c86: 0000 unimp - 1c88: 0524 addi s1,sp,648 - 1c8a: 0000 unimp - 1c8c: 0008 0x8 - 1c8e: 0079 c.nop 30 - 1c90: 244d jal 1f32 <_start-0x7fffe0ce> - 1c92: 008e slli ra,ra,0x3 - 1c94: 9f21 0x9f21 - 1c96: 0524 addi s1,sp,648 - 1c98: 0000 unimp - 1c9a: 0528 addi a0,sp,648 - 1c9c: 0000 unimp - 1c9e: 0006 c.slli zero,0x1 - 1ca0: 008e slli ra,ra,0x3 - 1ca2: 007f 0x7f - 1ca4: 9f21 0x9f21 - 1ca6: 0528 addi a0,sp,648 - 1ca8: 0000 unimp - 1caa: 052c addi a1,sp,648 - 1cac: 0000 unimp - 1cae: 0008 0x8 - 1cb0: 0079 c.nop 30 - 1cb2: 244d jal 1f54 <_start-0x7fffe0ac> - 1cb4: 008e slli ra,ra,0x3 - 1cb6: 9f21 0x9f21 - 1cb8: 052c addi a1,sp,648 - 1cba: 0000 unimp - 1cbc: 057c addi a5,sp,652 - 1cbe: 0000 unimp - 1cc0: 0001 nop - 1cc2: 8c5f 0005 9800 0x980000058c5f - 1cc8: 0005 c.nop 1 - 1cca: 0100 addi s0,sp,128 - 1ccc: 5800 lw s0,48(s0) - 1cce: 0598 addi a4,sp,704 - 1cd0: 0000 unimp - 1cd2: 05b0 addi a2,sp,712 - 1cd4: 0000 unimp - 1cd6: 0001 nop - 1cd8: c06e sw s11,0(sp) - 1cda: 0005 c.nop 1 - 1cdc: c400 sw s0,8(s0) - 1cde: 0005 c.nop 1 - 1ce0: 0100 addi s0,sp,128 - 1ce2: 6e00 flw fs0,24(a2) - 1ce4: 05d8 addi a4,sp,708 - 1ce6: 0000 unimp - 1ce8: 060c addi a1,sp,768 - 1cea: 0000 unimp - 1cec: 0001 nop - 1cee: 0c6e slli s8,s8,0x1b - 1cf0: 0006 c.slli zero,0x1 - 1cf2: 2c00 fld fs0,24(s0) - 1cf4: 0006 c.slli zero,0x1 - 1cf6: 0100 addi s0,sp,128 - 1cf8: 5f00 lw s0,56(a4) - 1cfa: 062c addi a1,sp,776 - 1cfc: 0000 unimp - 1cfe: 0630 addi a2,sp,776 - 1d00: 0000 unimp - 1d02: 7c7e0003 lb zero,1991(t3) # 1d7c7 <_start-0x7ffe2839> - 1d06: 309f 0006 3400 0x34000006309f - 1d0c: 0006 c.slli zero,0x1 - 1d0e: 0100 addi s0,sp,128 - 1d10: 5e00 lw s0,56(a2) - 1d12: 0634 addi a3,sp,776 - 1d14: 0000 unimp - 1d16: 0644 addi s1,sp,772 - 1d18: 0000 unimp - 1d1a: 0001 nop - 1d1c: 485f 0006 4c00 0x4c000006485f - 1d22: 0006 c.slli zero,0x1 - 1d24: 0100 addi s0,sp,128 - 1d26: 5f00 lw s0,56(a4) - 1d28: 0654 addi a3,sp,772 - 1d2a: 0000 unimp - 1d2c: 0678 addi a4,sp,780 - 1d2e: 0000 unimp - 1d30: 0001 nop - 1d32: 806e c.mv zero,s11 - 1d34: 0006 c.slli zero,0x1 - 1d36: 8800 0x8800 - 1d38: 0006 c.slli zero,0x1 - 1d3a: 0100 addi s0,sp,128 - 1d3c: 5f00 lw s0,56(a4) - 1d3e: 06ac addi a1,sp,840 - 1d40: 0000 unimp - 1d42: 06b4 addi a3,sp,840 - 1d44: 0000 unimp - 1d46: 0001 nop - 1d48: bc5f 0006 c000 0xc0000006bc5f - 1d4e: 0006 c.slli zero,0x1 - 1d50: 0100 addi s0,sp,128 - 1d52: 6e00 flw fs0,24(a2) - 1d54: 06c0 addi s0,sp,836 - 1d56: 0000 unimp - 1d58: 06c8 addi a0,sp,836 - 1d5a: 0000 unimp - 1d5c: 0001 nop - 1d5e: 005e c.slli zero,0x17 - 1d60: 0000 unimp - 1d62: 0000 unimp - 1d64: 0000 unimp - 1d66: ec00 fsw fs0,24(s0) - 1d68: 0002 c.slli64 zero - 1d6a: 5000 lw s0,32(s0) - 1d6c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1d70: 6f00 flw fs0,24(a4) - 1d72: 0350 addi a2,sp,388 - 1d74: 0000 unimp - 1d76: 0354 addi a3,sp,388 - 1d78: 0000 unimp - 1d7a: 0001 nop - 1d7c: 5459 li s0,-10 - 1d7e: 68000003 lb zero,1664(zero) # 680 <_start-0x7ffff980> - 1d82: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1d86: 6f00 flw fs0,24(a4) - 1d88: 0368 addi a0,sp,396 - 1d8a: 0000 unimp - 1d8c: 0514 addi a3,sp,640 - 1d8e: 0000 unimp - 1d90: 0001 nop - 1d92: 1459 addi s0,s0,-10 - 1d94: 0005 c.nop 1 - 1d96: 2c00 fld fs0,24(s0) - 1d98: 0005 c.nop 1 - 1d9a: 0500 addi s0,sp,640 - 1d9c: 7900 flw fs0,48(a0) - 1d9e: 3300 fld fs0,32(a4) - 1da0: 9f25 0x9f25 - 1da2: 052c addi a1,sp,648 - 1da4: 0000 unimp - 1da6: 0530 addi a2,sp,648 - 1da8: 0000 unimp - 1daa: 0001 nop - 1dac: 8c5a mv s8,s6 - 1dae: 0005 c.nop 1 - 1db0: 9800 0x9800 - 1db2: 0005 c.nop 1 - 1db4: 0100 addi s0,sp,128 - 1db6: 6500 flw fs0,8(a0) - 1db8: 0598 addi a4,sp,704 - 1dba: 0000 unimp - 1dbc: 05b0 addi a2,sp,712 - 1dbe: 0000 unimp - 1dc0: 0001 nop - 1dc2: c059 beqz s0,1e48 <_start-0x7fffe1b8> - 1dc4: 0005 c.nop 1 - 1dc6: c400 sw s0,8(s0) - 1dc8: 0005 c.nop 1 - 1dca: 0100 addi s0,sp,128 - 1dcc: 5900 lw s0,48(a0) - 1dce: 05d8 addi a4,sp,708 - 1dd0: 0000 unimp - 1dd2: 0610 addi a2,sp,768 - 1dd4: 0000 unimp - 1dd6: 0001 nop - 1dd8: 1059 c.nop -10 - 1dda: 0006 c.slli zero,0x1 - 1ddc: 4c00 lw s0,24(s0) - 1dde: 0006 c.slli zero,0x1 - 1de0: 0100 addi s0,sp,128 - 1de2: 5a00 lw s0,48(a2) - 1de4: 0654 addi a3,sp,772 - 1de6: 0000 unimp - 1de8: 0680 addi s0,sp,832 - 1dea: 0000 unimp - 1dec: 0001 nop - 1dee: 8059 srli s0,s0,0x16 - 1df0: 0006 c.slli zero,0x1 - 1df2: 8800 0x8800 - 1df4: 0006 c.slli zero,0x1 - 1df6: 0200 addi s0,sp,256 - 1df8: 3000 fld fs0,32(s0) - 1dfa: ac9f 0006 b000 0xb0000006ac9f - 1e00: 0006 c.slli zero,0x1 - 1e02: 0100 addi s0,sp,128 - 1e04: 5a00 lw s0,48(a2) - 1e06: 06bc addi a5,sp,840 - 1e08: 0000 unimp - 1e0a: 06c8 addi a0,sp,836 - 1e0c: 0000 unimp - 1e0e: 0001 nop - 1e10: 0059 c.nop 22 - 1e12: 0000 unimp - 1e14: 0000 unimp - 1e16: 0000 unimp - 1e18: fc00 fsw fs0,56(s0) - 1e1a: 0000 unimp - 1e1c: 0000 unimp - 1e1e: 0001 nop - 1e20: 0100 addi s0,sp,128 - 1e22: 5a00 lw s0,48(a2) - 1e24: 0100 addi s0,sp,128 - 1e26: 0000 unimp - 1e28: 0130 addi a2,sp,136 - 1e2a: 0000 unimp - 1e2c: 0001 nop - 1e2e: 345f 0001 3c00 0x3c000001345f - 1e34: 0001 nop - 1e36: 0100 addi s0,sp,128 - 1e38: 5a00 lw s0,48(a2) - 1e3a: 013c addi a5,sp,136 - 1e3c: 0000 unimp - 1e3e: 014c addi a1,sp,132 - 1e40: 0000 unimp - 1e42: 0001 nop - 1e44: 005f 0000 0000 0x5f - 1e4a: 0000 unimp - 1e4c: 9c00 0x9c00 - 1e4e: 0001 nop - 1e50: a000 fsd fs0,0(s0) - 1e52: 0001 nop - 1e54: 0100 addi s0,sp,128 - 1e56: 5a00 lw s0,48(a2) - 1e58: 01a0 addi s0,sp,200 - 1e5a: 0000 unimp - 1e5c: 01d0 addi a2,sp,196 - 1e5e: 0000 unimp - 1e60: 0001 nop - 1e62: d85f 0001 e000 0xe0000001d85f - 1e68: 0001 nop - 1e6a: 0100 addi s0,sp,128 - 1e6c: 5a00 lw s0,48(a2) - 1e6e: 01e0 addi s0,sp,204 - 1e70: 0000 unimp - 1e72: 01f0 addi a2,sp,204 - 1e74: 0000 unimp - 1e76: 0001 nop - 1e78: 005f 0000 0000 0x5f - 1e7e: 0000 unimp - 1e80: 3400 fld fs0,40(s0) - 1e82: 0002 c.slli64 zero - 1e84: 4400 lw s0,8(s0) - 1e86: 0002 c.slli64 zero - 1e88: 0500 addi s0,sp,640 - 1e8a: 8500 0x8500 - 1e8c: 3100 fld fs0,32(a0) - 1e8e: 9f25 0x9f25 - 1e90: 0244 addi s1,sp,260 - 1e92: 0000 unimp - 1e94: 027c addi a5,sp,268 - 1e96: 0000 unimp - 1e98: 0001 nop - 1e9a: 8065 srli s0,s0,0x19 - 1e9c: 0005 c.nop 1 - 1e9e: 8800 0x8800 - 1ea0: 0005 c.nop 1 - 1ea2: 0100 addi s0,sp,128 - 1ea4: 6500 flw fs0,8(a0) - ... - 1eae: 023c addi a5,sp,264 - 1eb0: 0000 unimp - 1eb2: 0248 addi a0,sp,260 - 1eb4: 0000 unimp - 1eb6: 0006 c.slli zero,0x1 - 1eb8: 007d c.nop 31 - 1eba: 007e c.slli zero,0x1f - 1ebc: 9f21 0x9f21 - 1ebe: 0248 addi a0,sp,260 - 1ec0: 0000 unimp - 1ec2: 02a8 addi a0,sp,328 - 1ec4: 0000 unimp - 1ec6: 0001 nop - 1ec8: 8058 0x8058 - 1eca: 0005 c.nop 1 - 1ecc: 8800 0x8800 - 1ece: 0005 c.nop 1 - 1ed0: 0100 addi s0,sp,128 - 1ed2: 5800 lw s0,48(s0) - ... - 1edc: 0240 addi s0,sp,260 - 1ede: 0000 unimp - 1ee0: 0358 addi a4,sp,388 - 1ee2: 0000 unimp - 1ee4: 0001 nop - 1ee6: 805f 0005 8800 0x88000005805f - 1eec: 0005 c.nop 1 - 1eee: 0200 addi s0,sp,256 - 1ef0: 3000 fld fs0,32(s0) - 1ef2: 009f 0000 0000 0x9f - 1ef8: 0000 unimp - 1efa: ec00 fsw fs0,24(s0) - 1efc: 0002 c.slli64 zero - 1efe: 6400 flw fs0,8(s0) - 1f00: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1f04: 5800 lw s0,48(s0) - 1f06: 0368 addi a0,sp,396 - 1f08: 0000 unimp - 1f0a: 039c addi a5,sp,448 - 1f0c: 0000 unimp - 1f0e: 0001 nop - 1f10: a458 fsd fa4,136(s0) - 1f12: b8000003 lb zero,-1152(zero) # fffffb80 <__BSS_END__+0x7ffe8e08> - 1f16: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1f1a: 5800 lw s0,48(s0) - 1f1c: 0438 addi a4,sp,520 - 1f1e: 0000 unimp - 1f20: 0498 addi a4,sp,576 - 1f22: 0000 unimp - 1f24: 0001 nop - 1f26: 9c58 0x9c58 - 1f28: 0004 0x4 - 1f2a: c800 sw s0,16(s0) - 1f2c: 0004 0x4 - 1f2e: 0100 addi s0,sp,128 - 1f30: 5800 lw s0,48(s0) - 1f32: 04c8 addi a0,sp,580 - 1f34: 0000 unimp - 1f36: 04cc addi a1,sp,580 - 1f38: 0000 unimp - 1f3a: 0001 nop - 1f3c: bc61 j 19d4 <_start-0x7fffe62c> - 1f3e: 0006 c.slli zero,0x1 - 1f40: c000 sw s0,0(s0) - 1f42: 0006 c.slli zero,0x1 - 1f44: 0100 addi s0,sp,128 - 1f46: 5800 lw s0,48(s0) - ... - 1f50: 0344 addi s1,sp,388 - 1f52: 0000 unimp - 1f54: 0358 addi a4,sp,388 - 1f56: 0000 unimp - 1f58: 0001 nop - 1f5a: 685f 0003 8400 0x84000003685f - 1f60: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1f64: 5f00 lw s0,56(a4) - 1f66: 0394 addi a3,sp,448 - 1f68: 0000 unimp - 1f6a: 03a0 addi s0,sp,456 - 1f6c: 0000 unimp - 1f6e: 0001 nop - 1f70: a45f 0003 f000 0xf0000003a45f - 1f76: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1f7a: 5d00 lw s0,56(a0) - 1f7c: 0484 addi s1,sp,576 - 1f7e: 0000 unimp - 1f80: 049c addi a5,sp,576 - 1f82: 0000 unimp - 1f84: 0002 c.slli64 zero - 1f86: 9f30 0x9f30 - 1f88: 049c addi a5,sp,576 - 1f8a: 0000 unimp - 1f8c: 04b4 addi a3,sp,584 - 1f8e: 0000 unimp - 1f90: 0001 nop - 1f92: 0004c05b 0x4c05b - 1f96: c400 sw s0,8(s0) - 1f98: 0004 0x4 - 1f9a: 0100 addi s0,sp,128 - 1f9c: 5f00 lw s0,56(a4) - 1f9e: 04c4 addi s1,sp,580 - 1fa0: 0000 unimp - 1fa2: 04cc addi a1,sp,580 - 1fa4: 0000 unimp - 1fa6: 0001 nop - 1fa8: 0006bc5b 0x6bc5b - 1fac: c000 sw s0,0(s0) - 1fae: 0006 c.slli zero,0x1 - 1fb0: 0100 addi s0,sp,128 - 1fb2: 5b00 lw s0,48(a4) - ... - 1fbc: 032c addi a1,sp,392 - 1fbe: 0000 unimp - 1fc0: 03a8 addi a0,sp,456 - 1fc2: 0000 unimp - 1fc4: 0001 nop - 1fc6: 6c6e flw fs8,216(sp) - 1fc8: 0004 0x4 - 1fca: d000 sw s0,32(s0) - 1fcc: 0004 0x4 - 1fce: 0100 addi s0,sp,128 - 1fd0: 6100 flw fs0,0(a0) - 1fd2: 06bc addi a5,sp,840 - 1fd4: 0000 unimp - 1fd6: 06c8 addi a0,sp,836 - 1fd8: 0000 unimp - 1fda: 0001 nop - 1fdc: 0061 c.nop 24 - 1fde: 0000 unimp - 1fe0: 0000 unimp - 1fe2: 0000 unimp - 1fe4: 4400 lw s0,8(s0) - 1fe6: 98000003 lb zero,-1664(zero) # fffff980 <__BSS_END__+0x7ffe8c08> - 1fea: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 1fee: 5d00 lw s0,56(a0) - 1ff0: 0398 addi a4,sp,448 - 1ff2: 0000 unimp - 1ff4: 0444 addi s1,sp,516 - 1ff6: 0000 unimp - 1ff8: 0024 addi s1,sp,8 - 1ffa: 0075008f 0x75008f - 1ffe: 8d1a mv s10,t1 - 2000: 1e00 addi s0,sp,816 - 2002: 2540008f 0x2540008f - 2006: 0081 addi ra,ra,0 - 2008: 221e fld ft4,448(sp) - 200a: 0075008f 0x75008f - 200e: 811a mv sp,t1 - 2010: 1e00 addi s0,sp,816 - 2012: 2540 fld fs0,136(a0) - 2014: 7522 flw fa0,40(sp) - 2016: 1a00 addi s0,sp,304 - 2018: 2440 fld fs0,136(s0) - 201a: 9f220077 0x9f220077 - 201e: 0444 addi s1,sp,516 - 2020: 0000 unimp - 2022: 044c addi a1,sp,516 - 2024: 0000 unimp - 2026: 002a c.slli zero,0xa - 2028: 0075008f 0x75008f - 202c: 8d1a mv s10,t1 - 202e: 1e00 addi s0,sp,816 - 2030: 0075007b 0x75007b - 2034: 8f1a mv t5,t1 - 2036: 4000 lw s0,0(s0) - 2038: 1e25 addi t3,t3,-23 - 203a: 8f22 mv t5,s0 - 203c: 7500 flw fs0,40(a0) - 203e: 1a00 addi s0,sp,304 - 2040: 0075007b 0x75007b - 2044: 1e1a slli t3,t3,0x26 - 2046: 2540 fld fs0,136(a0) - 2048: 7522 flw fa0,40(sp) - 204a: 1a00 addi s0,sp,304 - 204c: 2440 fld fs0,136(s0) - 204e: 9f220077 0x9f220077 - 2052: 044c addi a1,sp,516 - 2054: 0000 unimp - 2056: 0484 addi s1,sp,576 - 2058: 0000 unimp - 205a: 002c addi a1,sp,8 - 205c: 0075008f 0x75008f - 2060: 7b1a flw fs6,164(sp) - 2062: 4000 lw s0,0(s0) - 2064: 1e25 addi t3,t3,-23 - 2066: 0075007b 0x75007b - 206a: 8f1a mv t5,t1 - 206c: 4000 lw s0,0(s0) - 206e: 1e25 addi t3,t3,-23 - 2070: 8f22 mv t5,s0 - 2072: 7500 flw fs0,40(a0) - 2074: 1a00 addi s0,sp,304 - 2076: 0075007b 0x75007b - 207a: 1e1a slli t3,t3,0x26 - 207c: 2540 fld fs0,136(a0) - 207e: 7522 flw fa0,40(sp) - 2080: 1a00 addi s0,sp,304 - 2082: 2440 fld fs0,136(s0) - 2084: 9f220077 0x9f220077 - 2088: 0484 addi s1,sp,576 - 208a: 0000 unimp - 208c: 04d0 addi a2,sp,580 - 208e: 0000 unimp - 2090: 0001 nop - 2092: bc5d j 1b48 <_start-0x7fffe4b8> - 2094: 0006 c.slli zero,0x1 - 2096: c800 sw s0,16(s0) - 2098: 0006 c.slli zero,0x1 - 209a: 0100 addi s0,sp,128 - 209c: 5d00 lw s0,56(a0) - ... - 20a6: 026c addi a1,sp,268 - 20a8: 0000 unimp - 20aa: 0440 addi s0,sp,516 - 20ac: 0000 unimp - 20ae: 0001 nop - 20b0: 406c lw a1,68(s0) - 20b2: 0004 0x4 - 20b4: b800 fsd fs0,48(s0) - 20b6: 0004 0x4 - 20b8: 0500 addi s0,sp,640 - 20ba: 7a00 flw fs0,48(a2) - 20bc: 4000 lw s0,0(s0) - 20be: 9f25 0x9f25 - 20c0: 06bc addi a5,sp,840 - 20c2: 0000 unimp - 20c4: 06c8 addi a0,sp,836 - 20c6: 0000 unimp - 20c8: 0005 c.nop 1 - 20ca: 007a c.slli zero,0x1e - 20cc: 2540 fld fs0,136(a0) - 20ce: 009f 0000 0000 0x9f - 20d4: 0000 unimp - 20d6: 6c00 flw fs0,24(s0) - 20d8: 0002 c.slli64 zero - 20da: 0000 unimp - 20dc: 0004 0x4 - 20de: 0100 addi s0,sp,128 - 20e0: 5600 lw s0,40(a2) - 20e2: 0400 addi s0,sp,512 - 20e4: 0000 unimp - 20e6: 04b8 addi a4,sp,584 - 20e8: 0000 unimp - 20ea: 007a0007 0x7a0007 - 20ee: 2440 fld fs0,136(s0) - 20f0: 2540 fld fs0,136(a0) - 20f2: bc9f 0006 c800 0xc8000006bc9f - 20f8: 0006 c.slli zero,0x1 - 20fa: 0700 addi s0,sp,896 - 20fc: 7a00 flw fs0,48(a2) - 20fe: 4000 lw s0,0(s0) - 2100: 4024 lw s1,64(s0) - 2102: 9f25 0x9f25 - ... - 210c: 026c addi a1,sp,268 - 210e: 0000 unimp - 2110: 028c addi a1,sp,320 - 2112: 0000 unimp - 2114: 0001 nop - 2116: 8c61 and s0,s0,s0 - 2118: 0002 c.slli64 zero - 211a: e000 fsw fs0,0(s0) - 211c: 0002 c.slli64 zero - 211e: 0100 addi s0,sp,128 - 2120: 6f00 flw fs0,24(a4) - ... - 212a: 02a4 addi s1,sp,328 - 212c: 0000 unimp - 212e: 02cc addi a1,sp,324 - 2130: 0000 unimp - 2132: 0001 nop - 2134: cc6d beqz s0,222e <_start-0x7fffddd2> - 2136: 0002 c.slli64 zero - 2138: e800 fsw fs0,16(s0) - 213a: 0002 c.slli64 zero - 213c: 0100 addi s0,sp,128 - 213e: 5d00 lw s0,56(a0) - ... - 2148: 026c addi a1,sp,268 - 214a: 0000 unimp - 214c: 0270 addi a2,sp,268 - 214e: 0000 unimp - 2150: 0006 c.slli zero,0x1 - 2152: 0085 addi ra,ra,1 - 2154: 008c addi a1,sp,64 - 2156: 9f1d 0x9f1d - 2158: 0270 addi a2,sp,268 - 215a: 0000 unimp - 215c: 0280 addi s0,sp,320 - 215e: 0000 unimp - 2160: 0001 nop - 2162: 8059 srli s0,s0,0x16 - 2164: 0002 c.slli64 zero - 2166: 8800 0x8800 - 2168: 0002 c.slli64 zero - 216a: 0100 addi s0,sp,128 - 216c: 5e00 lw s0,56(a2) - 216e: 0288 addi a0,sp,320 - 2170: 0000 unimp - 2172: 028c addi a1,sp,320 - 2174: 0000 unimp - 2176: 0008 0x8 - 2178: 0078 addi a4,sp,12 - 217a: 2540 fld fs0,136(a0) - 217c: 0085 addi ra,ra,1 - 217e: 9f21 0x9f21 - 2180: 028c addi a1,sp,320 - 2182: 0000 unimp - 2184: 02b0 addi a2,sp,328 - 2186: 0000 unimp - 2188: 0001 nop - 218a: 005e c.slli zero,0x17 - 218c: 0000 unimp - 218e: 0000 unimp - 2190: 0000 unimp - 2192: a000 fsd fs0,0(s0) - 2194: 0002 c.slli64 zero - 2196: b000 fsd fs0,32(s0) - 2198: 0002 c.slli64 zero - 219a: 0600 addi s0,sp,768 - 219c: 7e00 flw fs0,56(a2) - 219e: 8c00 0x8c00 - 21a0: 1d00 addi s0,sp,688 - 21a2: b09f 0002 bc00 0xbc000002b09f - 21a8: 0002 c.slli64 zero - 21aa: 0100 addi s0,sp,128 - 21ac: 5e00 lw s0,56(a2) - 21ae: 02c0 addi s0,sp,324 - 21b0: 0000 unimp - 21b2: 02c8 addi a0,sp,324 - 21b4: 0000 unimp - 21b6: 0001 nop - 21b8: cc5e sw s7,24(sp) - 21ba: 0002 c.slli64 zero - 21bc: ec00 fsw fs0,24(s0) - 21be: 0002 c.slli64 zero - 21c0: 0100 addi s0,sp,128 - 21c2: 5e00 lw s0,56(a2) - 21c4: 02ec addi a1,sp,332 - 21c6: 0000 unimp - 21c8: 0364 addi s1,sp,396 - 21ca: 0000 unimp - 21cc: 0001 nop - 21ce: 0058 addi a4,sp,4 - 21d0: 0000 unimp - 21d2: 0000 unimp - 21d4: 0000 unimp - 21d6: 7800 flw fs0,48(s0) - 21d8: 0002 c.slli64 zero - 21da: b400 fsd fs0,40(s0) - 21dc: 0002 c.slli64 zero - 21de: 0100 addi s0,sp,128 - 21e0: 5d00 lw s0,56(a0) - 21e2: 02b4 addi a3,sp,328 - 21e4: 0000 unimp - 21e6: 02b8 addi a4,sp,328 - 21e8: 0000 unimp - 21ea: 0006 c.slli zero,0x1 - 21ec: 0076 c.slli zero,0x1d - 21ee: 0081 addi ra,ra,0 - 21f0: 9f1e add t5,t5,t2 - 21f2: 02b8 addi a4,sp,328 - 21f4: 0000 unimp - 21f6: 02f0 addi a2,sp,332 - 21f8: 0000 unimp - 21fa: 0001 nop - 21fc: f061 bnez s0,21bc <_start-0x7fffde44> - 21fe: 0002 c.slli64 zero - 2200: fc00 fsw fs0,56(s0) - 2202: 0002 c.slli64 zero - 2204: 0600 addi s0,sp,768 - 2206: 7600 flw fs0,40(a2) - 2208: 8d00 0x8d00 - 220a: 1e00 addi s0,sp,816 - 220c: 009f 0000 0000 0x9f - 2212: 0000 unimp - 2214: 0400 addi s0,sp,512 - 2216: 40000003 lb zero,1024(zero) # 400 <_start-0x7ffffc00> - 221a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 221e: 5700 lw s0,40(a4) - 2220: 0340 addi s0,sp,388 - 2222: 0000 unimp - 2224: 0350 addi a2,sp,388 - 2226: 0000 unimp - 2228: 0009 c.nop 2 - 222a: 0075008f 0x75008f - 222e: 811a mv sp,t1 - 2230: 1e00 addi s0,sp,816 - 2232: 509f 0003 5400 0x54000003509f - 2238: 09000003 lb zero,144(zero) # 90 <_start-0x7fffff70> - 223c: 7900 flw fs0,48(a0) - 223e: 7500 flw fs0,40(a0) - 2240: 1a00 addi s0,sp,304 - 2242: 0081 addi ra,ra,0 - 2244: 9f1e add t5,t5,t2 - 2246: 0354 addi a3,sp,388 - 2248: 0000 unimp - 224a: 0444 addi s1,sp,516 - 224c: 0000 unimp - 224e: 0009 c.nop 2 - 2250: 0075008f 0x75008f - 2254: 811a mv sp,t1 - 2256: 1e00 addi s0,sp,816 - 2258: 449f 0004 b400 0xb4000004449f - 225e: 0004 0x4 - 2260: 0c00 addi s0,sp,528 - 2262: 8f00 0x8f00 - 2264: 7500 flw fs0,40(a0) - 2266: 1a00 addi s0,sp,304 - 2268: 0075007b 0x75007b - 226c: 1e1a slli t3,t3,0x26 - 226e: bc9f 0006 c800 0xc8000006bc9f - 2274: 0006 c.slli zero,0x1 - 2276: 0c00 addi s0,sp,528 - 2278: 8f00 0x8f00 - 227a: 7500 flw fs0,40(a0) - 227c: 1a00 addi s0,sp,304 - 227e: 0075007b 0x75007b - 2282: 1e1a slli t3,t3,0x26 - 2284: 009f 0000 0000 0x9f - 228a: 0000 unimp - 228c: 0400 addi s0,sp,512 - 228e: 0c000003 lb zero,192(zero) # c0 <_start-0x7fffff40> - 2292: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 2296: 8d00 0x8d00 - 2298: 7e00 flw fs0,56(a2) - 229a: 1e00 addi s0,sp,816 - 229c: 0c9f 0003 1400 0x140000030c9f - 22a2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 22a6: 5e00 lw s0,56(a2) - 22a8: 031c addi a5,sp,384 - 22aa: 0000 unimp - 22ac: 035c addi a5,sp,388 - 22ae: 0000 unimp - 22b0: 0001 nop - 22b2: 5c5e lw s8,244(sp) - 22b4: 44000003 lb zero,1088(zero) # 440 <_start-0x7ffffbc0> - 22b8: 0004 0x4 - 22ba: 1c00 addi s0,sp,560 - 22bc: 8f00 0x8f00 - 22be: 7500 flw fs0,40(a0) - 22c0: 1a00 addi s0,sp,304 - 22c2: 008d addi ra,ra,3 - 22c4: 8f1e mv t5,t2 - 22c6: 4000 lw s0,0(s0) - 22c8: 8125 srli a0,a0,0x9 - 22ca: 1e00 addi s0,sp,816 - 22cc: 8f22 mv t5,s0 - 22ce: 7500 flw fs0,40(a0) - 22d0: 1a00 addi s0,sp,304 - 22d2: 0081 addi ra,ra,0 - 22d4: 401e 0x401e - 22d6: 2225 jal 23fe <_start-0x7fffdc02> - 22d8: 449f 0004 4c00 0x4c000004449f - 22de: 0004 0x4 - 22e0: 2200 fld fs0,0(a2) - 22e2: 8f00 0x8f00 - 22e4: 7500 flw fs0,40(a0) - 22e6: 1a00 addi s0,sp,304 - 22e8: 008d addi ra,ra,3 - 22ea: 7b1e flw fs6,228(sp) - 22ec: 7500 flw fs0,40(a0) - 22ee: 1a00 addi s0,sp,304 - 22f0: 2540008f 0x2540008f - 22f4: 221e fld ft4,448(sp) - 22f6: 0075008f 0x75008f - 22fa: 7b1a flw fs6,164(sp) - 22fc: 7500 flw fs0,40(a0) - 22fe: 1a00 addi s0,sp,304 - 2300: 401e 0x401e - 2302: 2225 jal 242a <_start-0x7fffdbd6> - 2304: 4c9f 0004 b400 0xb40000044c9f - 230a: 0004 0x4 - 230c: 2400 fld fs0,8(s0) - 230e: 8f00 0x8f00 - 2310: 7500 flw fs0,40(a0) - 2312: 1a00 addi s0,sp,304 - 2314: 2540007b 0x2540007b - 2318: 7b1e flw fs6,228(sp) - 231a: 7500 flw fs0,40(a0) - 231c: 1a00 addi s0,sp,304 - 231e: 2540008f 0x2540008f - 2322: 221e fld ft4,448(sp) - 2324: 0075008f 0x75008f - 2328: 7b1a flw fs6,164(sp) - 232a: 7500 flw fs0,40(a0) - 232c: 1a00 addi s0,sp,304 - 232e: 401e 0x401e - 2330: 2225 jal 2458 <_start-0x7fffdba8> - 2332: bc9f 0006 c800 0xc8000006bc9f - 2338: 0006 c.slli zero,0x1 - 233a: 2400 fld fs0,8(s0) - 233c: 8f00 0x8f00 - 233e: 7500 flw fs0,40(a0) - 2340: 1a00 addi s0,sp,304 - 2342: 2540007b 0x2540007b - 2346: 7b1e flw fs6,228(sp) - 2348: 7500 flw fs0,40(a0) - 234a: 1a00 addi s0,sp,304 - 234c: 2540008f 0x2540008f - 2350: 221e fld ft4,448(sp) - 2352: 0075008f 0x75008f - 2356: 7b1a flw fs6,164(sp) - 2358: 7500 flw fs0,40(a0) - 235a: 1a00 addi s0,sp,304 - 235c: 401e 0x401e - 235e: 2225 jal 2486 <_start-0x7fffdb7a> - 2360: 009f 0000 0000 0x9f - 2366: 0000 unimp - 2368: 0800 addi s0,sp,16 - 236a: 4c000003 lb zero,1216(zero) # 4c0 <_start-0x7ffffb40> - 236e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 2372: 5900 lw s0,48(a0) - 2374: 034c addi a1,sp,388 - 2376: 0000 unimp - 2378: 0350 addi a2,sp,388 - 237a: 0000 unimp - 237c: 0008 0x8 - 237e: 2540008f 0x2540008f - 2382: 0081 addi ra,ra,0 - 2384: 9f1e add t5,t5,t2 - 2386: 0350 addi a2,sp,388 - 2388: 0000 unimp - 238a: 0354 addi a3,sp,388 - 238c: 0000 unimp - 238e: 0008 0x8 - 2390: 0079 c.nop 30 - 2392: 2540 fld fs0,136(a0) - 2394: 0081 addi ra,ra,0 - 2396: 9f1e add t5,t5,t2 - 2398: 0354 addi a3,sp,388 - 239a: 0000 unimp - 239c: 0444 addi s1,sp,516 - 239e: 0000 unimp - 23a0: 0008 0x8 - 23a2: 2540008f 0x2540008f - 23a6: 0081 addi ra,ra,0 - 23a8: 9f1e add t5,t5,t2 - 23aa: 0444 addi s1,sp,516 - 23ac: 0000 unimp - 23ae: 04b4 addi a3,sp,584 - 23b0: 0000 unimp - 23b2: 007b000b 0x7b000b - 23b6: 0075 c.nop 29 - 23b8: 8f1a mv t5,t1 - 23ba: 4000 lw s0,0(s0) - 23bc: 1e25 addi t3,t3,-23 - 23be: bc9f 0006 c800 0xc8000006bc9f - 23c4: 0006 c.slli zero,0x1 - 23c6: 0b00 addi s0,sp,400 - 23c8: 7b00 flw fs0,48(a4) - 23ca: 7500 flw fs0,40(a0) - 23cc: 1a00 addi s0,sp,304 - 23ce: 2540008f 0x2540008f - 23d2: 9f1e add t5,t5,t2 - ... - 23dc: 0310 addi a2,sp,384 - 23de: 0000 unimp - 23e0: 0330 addi a2,sp,392 - 23e2: 0000 unimp - 23e4: 0001 nop - 23e6: 0055 c.nop 21 - 23e8: 0000 unimp - 23ea: 0000 unimp - 23ec: 0000 unimp - 23ee: ec00 fsw fs0,24(s0) - 23f0: 0002 c.slli64 zero - 23f2: d000 sw s0,32(s0) - 23f4: 0004 0x4 - 23f6: 0100 addi s0,sp,128 - 23f8: 6f00 flw fs0,24(a4) - 23fa: 06bc addi a5,sp,840 - 23fc: 0000 unimp - 23fe: 06c8 addi a0,sp,836 - 2400: 0000 unimp - 2402: 0001 nop - 2404: 0000006f j 2404 <_start-0x7fffdbfc> - 2408: 0000 unimp - 240a: 0000 unimp - 240c: f400 fsw fs0,40(s0) - 240e: 0002 c.slli64 zero - 2410: b400 fsd fs0,40(s0) - 2412: 0004 0x4 - 2414: 0100 addi s0,sp,128 - 2416: 5b00 lw s0,48(a4) - 2418: 06bc addi a5,sp,840 - 241a: 0000 unimp - 241c: 06c8 addi a0,sp,836 - 241e: 0000 unimp - 2420: 0001 nop - 2422: 0000005b 0x5b - 2426: 0000 unimp - 2428: 0000 unimp - 242a: f400 fsw fs0,40(s0) - 242c: 0002 c.slli64 zero - 242e: 1400 addi s0,sp,544 - 2430: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 2434: 6e00 flw fs0,24(a2) - 2436: 0314 addi a3,sp,384 - 2438: 0000 unimp - 243a: 0350 addi a2,sp,388 - 243c: 0000 unimp - 243e: 0005 c.nop 1 - 2440: 2540008f 0x2540008f - 2444: 509f 0003 5400 0x54000003509f - 244a: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - 244e: 7900 flw fs0,48(a0) - 2450: 4000 lw s0,0(s0) - 2452: 9f25 0x9f25 - 2454: 0354 addi a3,sp,388 - 2456: 0000 unimp - 2458: 04d0 addi a2,sp,580 - 245a: 0000 unimp - 245c: 0005 c.nop 1 - 245e: 2540008f 0x2540008f - 2462: bc9f 0006 c800 0xc8000006bc9f - 2468: 0006 c.slli zero,0x1 - 246a: 0500 addi s0,sp,640 - 246c: 8f00 0x8f00 - 246e: 4000 lw s0,0(s0) - 2470: 9f25 0x9f25 - ... - 247a: 02fc addi a5,sp,332 - 247c: 0000 unimp - 247e: 044c addi a1,sp,516 - 2480: 0000 unimp - 2482: 0001 nop - 2484: 4c6d li s8,27 - 2486: 0004 0x4 - 2488: b400 fsd fs0,40(s0) - 248a: 0004 0x4 - 248c: 0500 addi s0,sp,640 - 248e: 7b00 flw fs0,48(a4) - 2490: 4000 lw s0,0(s0) - 2492: 9f25 0x9f25 - 2494: 06bc addi a5,sp,840 - 2496: 0000 unimp - 2498: 06c8 addi a0,sp,836 - 249a: 0000 unimp - 249c: 0005 c.nop 1 - 249e: 2540007b 0x2540007b - 24a2: 009f 0000 0000 0x9f - 24a8: 0000 unimp - 24aa: 6800 flw fs0,16(s0) - 24ac: 84000003 lb zero,-1984(zero) # fffff840 <__BSS_END__+0x7ffe8ac8> - 24b0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 24b4: 5f00 lw s0,56(a4) - ... - 24be: 0390 addi a2,sp,448 - 24c0: 0000 unimp - 24c2: 0394 addi a3,sp,448 - 24c4: 0000 unimp - 24c6: 0001 nop - 24c8: 005f 0000 0000 0x5f - 24ce: 0000 unimp - 24d0: 9800 0x9800 - 24d2: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe9188> - 24d6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 24da: 5d00 lw s0,56(a0) - ... - 24e4: 03ac addi a1,sp,456 - 24e6: 0000 unimp - 24e8: 0440 addi s0,sp,516 - 24ea: 0000 unimp - 24ec: 0001 nop - 24ee: 406c lw a1,68(s0) - 24f0: 0004 0x4 - 24f2: b800 fsd fs0,48(s0) - 24f4: 0004 0x4 - 24f6: 0500 addi s0,sp,640 - 24f8: 7a00 flw fs0,48(a2) - 24fa: 4000 lw s0,0(s0) - 24fc: 9f25 0x9f25 - 24fe: 06bc addi a5,sp,840 - 2500: 0000 unimp - 2502: 06c8 addi a0,sp,836 - 2504: 0000 unimp - 2506: 0005 c.nop 1 - 2508: 007a c.slli zero,0x1e - 250a: 2540 fld fs0,136(a0) - 250c: 009f 0000 0000 0x9f - 2512: 0000 unimp - 2514: ac00 fsd fs0,24(s0) - 2516: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> - 251a: 0004 0x4 - 251c: 0100 addi s0,sp,128 - 251e: 5600 lw s0,40(a2) - 2520: 0400 addi s0,sp,512 - 2522: 0000 unimp - 2524: 04b8 addi a4,sp,584 - 2526: 0000 unimp - 2528: 007a0007 0x7a0007 - 252c: 2440 fld fs0,136(s0) - 252e: 2540 fld fs0,136(a0) - 2530: bc9f 0006 c800 0xc8000006bc9f - 2536: 0006 c.slli zero,0x1 - 2538: 0700 addi s0,sp,896 - 253a: 7a00 flw fs0,48(a2) - 253c: 4000 lw s0,0(s0) - 253e: 4024 lw s1,64(s0) - 2540: 9f25 0x9f25 - ... - 254a: 03b0 addi a2,sp,456 - 254c: 0000 unimp - 254e: 03d4 addi a3,sp,452 - 2550: 0000 unimp - 2552: 0001 nop - 2554: d46e sw s11,40(sp) - 2556: 28000003 lb zero,640(zero) # 280 <_start-0x7ffffd80> - 255a: 0004 0x4 - 255c: 0100 addi s0,sp,128 - 255e: 5e00 lw s0,56(a2) - ... - 2568: 03ec addi a1,sp,460 - 256a: 0000 unimp - 256c: 0414 addi a3,sp,512 - 256e: 0000 unimp - 2570: 0001 nop - 2572: 146e slli s0,s0,0x3b - 2574: 0004 0x4 - 2576: 3000 fld fs0,32(s0) - 2578: 0004 0x4 - 257a: 0100 addi s0,sp,128 - 257c: 5f00 lw s0,56(a4) - ... - 2586: 03ac addi a1,sp,456 - 2588: 0000 unimp - 258a: 03b8 addi a4,sp,456 - 258c: 0000 unimp - 258e: 0006 c.slli zero,0x1 - 2590: 0078 addi a4,sp,12 - 2592: 008c addi a1,sp,64 - 2594: 9f1d 0x9f1d - 2596: 03b8 addi a4,sp,456 - 2598: 0000 unimp - 259a: 03c0 addi s0,sp,452 - 259c: 0000 unimp - 259e: 0001 nop - 25a0: c458 sw a4,12(s0) - 25a2: d0000003 lb zero,-768(zero) # fffffd00 <__BSS_END__+0x7ffe8f88> - 25a6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 25aa: 5800 lw s0,48(s0) - 25ac: 03d4 addi a3,sp,452 - 25ae: 0000 unimp - 25b0: 03f8 addi a4,sp,460 - 25b2: 0000 unimp - 25b4: 0001 nop - 25b6: 0058 addi a4,sp,4 - 25b8: 0000 unimp - 25ba: 0000 unimp - 25bc: 0000 unimp - 25be: e800 fsw fs0,16(s0) - 25c0: f8000003 lb zero,-128(zero) # ffffff80 <__BSS_END__+0x7ffe9208> - 25c4: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 25c8: 7800 flw fs0,48(s0) - 25ca: 8c00 0x8c00 - 25cc: 1d00 addi s0,sp,688 - 25ce: f89f 0003 0400 0x4000003f89f - 25d4: 0004 0x4 - 25d6: 0100 addi s0,sp,128 - 25d8: 5800 lw s0,48(s0) - 25da: 0408 addi a0,sp,512 - 25dc: 0000 unimp - 25de: 0410 addi a2,sp,512 - 25e0: 0000 unimp - 25e2: 0001 nop - 25e4: 1458 addi a4,sp,548 - 25e6: 0004 0x4 - 25e8: 9800 0x9800 - 25ea: 0004 0x4 - 25ec: 0100 addi s0,sp,128 - 25ee: 5800 lw s0,48(s0) - ... - 25f8: 03bc addi a5,sp,456 - 25fa: 0000 unimp - 25fc: 03fc addi a5,sp,460 - 25fe: 0000 unimp - 2600: 0001 nop - 2602: 005f 0004 3c00 0x3c000004005f - 2608: 0004 0x4 - 260a: 0100 addi s0,sp,128 - 260c: 5600 lw s0,40(a2) - 260e: 043c addi a5,sp,520 - 2610: 0000 unimp - 2612: 0490 addi a2,sp,576 - 2614: 0000 unimp - 2616: 000a c.slli zero,0x2 - 2618: 007a c.slli zero,0x1e - 261a: 2440 fld fs0,136(s0) - 261c: 2540 fld fs0,136(a0) - 261e: 008e slli ra,ra,0x3 - 2620: 9f1e add t5,t5,t2 - ... - 262a: 0440 addi s0,sp,516 - 262c: 0000 unimp - 262e: 0480 addi s0,sp,576 - 2630: 0000 unimp - 2632: 0001 nop - 2634: 806c 0x806c - 2636: 0004 0x4 - 2638: b400 fsd fs0,40(s0) - 263a: 0004 0x4 - 263c: 0d00 addi s0,sp,656 - 263e: 7b00 flw fs0,48(a4) - 2640: 7500 flw fs0,40(a0) - 2642: 1a00 addi s0,sp,304 - 2644: 007e c.slli zero,0x1f - 2646: 2440 fld fs0,136(s0) - 2648: 2540 fld fs0,136(a0) - 264a: 9f1e add t5,t5,t2 - 264c: 06bc addi a5,sp,840 - 264e: 0000 unimp - 2650: 06c0 addi s0,sp,836 - 2652: 0000 unimp - 2654: 000d c.nop 3 - 2656: 0075007b 0x75007b - 265a: 7e1a flw ft8,164(sp) - 265c: 4000 lw s0,0(s0) - 265e: 4024 lw s1,64(s0) - 2660: 1e25 addi t3,t3,-23 - 2662: 009f 0000 0000 0x9f - 2668: 0000 unimp - 266a: 4000 lw s0,0(s0) - 266c: 0004 0x4 - 266e: 4c00 lw s0,24(s0) - 2670: 0004 0x4 - 2672: 0600 addi s0,sp,768 - 2674: 8d00 0x8d00 - 2676: 7f00 flw fs0,56(a4) - 2678: 1e00 addi s0,sp,816 - 267a: 4c9f 0004 5400 0x540000044c9f - 2680: 0004 0x4 - 2682: 0100 addi s0,sp,128 - 2684: 6d00 flw fs0,24(a0) - 2686: 0454 addi a3,sp,516 - 2688: 0000 unimp - 268a: 0458 addi a4,sp,516 - 268c: 0000 unimp - 268e: 0011 c.nop 4 - 2690: 2540007b 0x2540007b - 2694: 007e c.slli zero,0x1f - 2696: 2440 fld fs0,136(s0) - 2698: 2540 fld fs0,136(a0) - 269a: 8c1e mv s8,t2 - 269c: 4000 lw s0,0(s0) - 269e: 2225 jal 27c6 <_start-0x7fffd83a> - 26a0: 589f 0004 b000 0xb0000004589f - 26a6: 0004 0x4 - 26a8: 0100 addi s0,sp,128 - 26aa: 5f00 lw s0,56(a4) - 26ac: 04b0 addi a2,sp,584 - 26ae: 0000 unimp - 26b0: 04b4 addi a3,sp,584 - 26b2: 0000 unimp - 26b4: 0012 c.slli zero,0x4 - 26b6: 0075007b 0x75007b - 26ba: 7e1a flw ft8,164(sp) - 26bc: 4000 lw s0,0(s0) - 26be: 4024 lw s1,64(s0) - 26c0: 1e25 addi t3,t3,-23 - 26c2: 2540 fld fs0,136(a0) - 26c4: 008d addi ra,ra,3 - 26c6: 9f22 add t5,t5,s0 - 26c8: 06bc addi a5,sp,840 - 26ca: 0000 unimp - 26cc: 06c8 addi a0,sp,836 - 26ce: 0000 unimp - 26d0: 0001 nop - 26d2: 005f 0000 0000 0x5f - 26d8: 0000 unimp - 26da: 4400 lw s0,8(s0) - 26dc: 0004 0x4 - 26de: 6800 flw fs0,16(s0) - 26e0: 0004 0x4 - 26e2: 0100 addi s0,sp,128 - 26e4: 6100 flw fs0,0(a0) - 26e6: 0468 addi a0,sp,524 - 26e8: 0000 unimp - 26ea: 04b4 addi a3,sp,584 - 26ec: 0000 unimp - 26ee: 007b000b 0x7b000b - 26f2: 0075 c.nop 29 - 26f4: 7e1a flw ft8,164(sp) - 26f6: 4000 lw s0,0(s0) - 26f8: 1e25 addi t3,t3,-23 - 26fa: bc9f 0006 c000 0xc0000006bc9f - 2700: 0006 c.slli zero,0x1 - 2702: 0b00 addi s0,sp,400 - 2704: 7b00 flw fs0,48(a4) - 2706: 7500 flw fs0,40(a0) - 2708: 1a00 addi s0,sp,304 - 270a: 007e c.slli zero,0x1f - 270c: 2540 fld fs0,136(a0) - 270e: 9f1e add t5,t5,t2 - ... - 2718: 0448 addi a0,sp,516 - 271a: 0000 unimp - 271c: 0470 addi a2,sp,524 - 271e: 0000 unimp - 2720: 0001 nop - 2722: 0056 c.slli zero,0x15 - 2724: 0000 unimp - 2726: 0000 unimp - 2728: 0000 unimp - 272a: 3800 fld fs0,48(s0) - 272c: 0004 0x4 - 272e: cc00 sw s0,24(s0) - 2730: 0004 0x4 - 2732: 0100 addi s0,sp,128 - 2734: 5e00 lw s0,56(a2) - 2736: 06bc addi a5,sp,840 - 2738: 0000 unimp - 273a: 06c0 addi s0,sp,836 - 273c: 0000 unimp - 273e: 0001 nop - 2740: 005e c.slli zero,0x17 - 2742: 0000 unimp - 2744: 0000 unimp - 2746: 0000 unimp - 2748: 3c00 fld fs0,56(s0) - 274a: 0004 0x4 - 274c: b400 fsd fs0,40(s0) - 274e: 0004 0x4 - 2750: 0100 addi s0,sp,128 - 2752: 5b00 lw s0,48(a4) - 2754: 06bc addi a5,sp,840 - 2756: 0000 unimp - 2758: 06c8 addi a0,sp,836 - 275a: 0000 unimp - 275c: 0001 nop - 275e: 0000005b 0x5b - 2762: 0000 unimp - 2764: 0000 unimp - 2766: 3c00 fld fs0,56(s0) - 2768: 0004 0x4 - 276a: 4800 lw s0,16(s0) - 276c: 0004 0x4 - 276e: 0100 addi s0,sp,128 - 2770: 5600 lw s0,40(a2) - 2772: 0448 addi a0,sp,516 - 2774: 0000 unimp - 2776: 04cc addi a1,sp,580 - 2778: 0000 unimp - 277a: 0005 c.nop 1 - 277c: 007e c.slli zero,0x1f - 277e: 2540 fld fs0,136(a0) - 2780: bc9f 0006 c000 0xc0000006bc9f - 2786: 0006 c.slli zero,0x1 - 2788: 0500 addi s0,sp,640 - 278a: 7e00 flw fs0,56(a2) - 278c: 4000 lw s0,0(s0) - 278e: 9f25 0x9f25 - ... - 2798: 043c addi a5,sp,520 - 279a: 0000 unimp - 279c: 044c addi a1,sp,516 - 279e: 0000 unimp - 27a0: 0001 nop - 27a2: 4c6d li s8,27 - 27a4: 0004 0x4 - 27a6: b400 fsd fs0,40(s0) - 27a8: 0004 0x4 - 27aa: 0500 addi s0,sp,640 - 27ac: 7b00 flw fs0,48(a4) - 27ae: 4000 lw s0,0(s0) - 27b0: 9f25 0x9f25 - 27b2: 06bc addi a5,sp,840 - 27b4: 0000 unimp - 27b6: 06c8 addi a0,sp,836 - 27b8: 0000 unimp - 27ba: 0005 c.nop 1 - 27bc: 2540007b 0x2540007b - 27c0: 009f 0000 0000 0x9f - 27c6: 0000 unimp - 27c8: 9c00 0x9c00 - 27ca: 0004 0x4 - 27cc: b400 fsd fs0,40(s0) - 27ce: 0004 0x4 - 27d0: 0100 addi s0,sp,128 - 27d2: 5b00 lw s0,48(a4) - 27d4: 06bc addi a5,sp,840 - 27d6: 0000 unimp - 27d8: 06c0 addi s0,sp,836 - 27da: 0000 unimp - 27dc: 0001 nop - 27de: 0000005b 0x5b - 27e2: 0000 unimp - 27e4: 0000 unimp - 27e6: bc00 fsd fs0,56(s0) - 27e8: 0004 0x4 - 27ea: c400 sw s0,8(s0) - 27ec: 0004 0x4 - 27ee: 0100 addi s0,sp,128 - 27f0: 5f00 lw s0,56(a4) - ... - 27fa: 04f0 addi a2,sp,588 - 27fc: 0000 unimp - 27fe: 04fc addi a5,sp,588 - 2800: 0000 unimp - 2802: 0001 nop - 2804: 005d c.nop 23 - 2806: 0000 unimp - 2808: 0000 unimp - 280a: 0000 unimp - 280c: 2800 fld fs0,16(s0) - 280e: 0006 c.slli zero,0x1 - 2810: 3400 fld fs0,40(s0) - 2812: 0006 c.slli zero,0x1 - 2814: 0100 addi s0,sp,128 - 2816: 5e00 lw s0,56(a2) - ... - 2824: 0070 addi a2,sp,12 - 2826: 0000 unimp - 2828: 0006 c.slli zero,0x1 - 282a: 935a add t1,t1,s6 - 282c: 5b04 lw s1,48(a4) - 282e: 00700493 li s1,7 - 2832: 0000 unimp - 2834: 00ec addi a1,sp,76 - 2836: 0000 unimp - 2838: 0006 c.slli zero,0x1 - 283a: 0af503f3 0xaf503f3 - 283e: 9f25 0x9f25 - 2840: 00ec addi a1,sp,76 - 2842: 0000 unimp - 2844: 00fc addi a5,sp,76 - 2846: 0000 unimp - 2848: 0006 c.slli zero,0x1 - 284a: 935a add t1,t1,s6 - 284c: 5b04 lw s1,48(a4) - 284e: 00fc0493 addi s1,s8,15 # ffff900f <__BSS_END__+0x7ffe2297> - 2852: 0000 unimp - 2854: 0134 addi a3,sp,136 - 2856: 0000 unimp - 2858: 0006 c.slli zero,0x1 - 285a: 0af503f3 0xaf503f3 - 285e: 9f25 0x9f25 - 2860: 0134 addi a3,sp,136 - 2862: 0000 unimp - 2864: 00000137 lui sp,0x0 - 2868: 0006 c.slli zero,0x1 - 286a: 935a add t1,t1,s6 - 286c: 5b04 lw s1,48(a4) - 286e: 01370493 addi s1,a4,19 # ffff8013 <__BSS_END__+0x7ffe129b> - 2872: 0000 unimp - 2874: 0150 addi a2,sp,132 - 2876: 0000 unimp - 2878: 0006 c.slli zero,0x1 - 287a: 0af503f3 0xaf503f3 - 287e: 9f25 0x9f25 - 2880: 0150 addi a2,sp,132 - 2882: 0000 unimp - 2884: 0188 addi a0,sp,192 - 2886: 0000 unimp - 2888: 0006 c.slli zero,0x1 - 288a: 935a add t1,t1,s6 - 288c: 5b04 lw s1,48(a4) - 288e: 01880493 addi s1,a6,24 - 2892: 0000 unimp - 2894: 05b8 addi a4,sp,712 - 2896: 0000 unimp - 2898: 0006 c.slli zero,0x1 - 289a: 0af503f3 0xaf503f3 - 289e: 9f25 0x9f25 - ... - 28ac: 0070 addi a2,sp,12 - 28ae: 0000 unimp - 28b0: 0006 c.slli zero,0x1 - 28b2: 935c 0x935c - 28b4: 5d04 lw s1,56(a0) - 28b6: 00700493 li s1,7 - 28ba: 0000 unimp - 28bc: 00ec addi a1,sp,76 - 28be: 0000 unimp - 28c0: 0006 c.slli zero,0x1 - 28c2: 0cf503f3 0xcf503f3 - 28c6: 9f25 0x9f25 - 28c8: 00ec addi a1,sp,76 - 28ca: 0000 unimp - 28cc: 00ff 0xff - 28ce: 0000 unimp - 28d0: 0006 c.slli zero,0x1 - 28d2: 935c 0x935c - 28d4: 5d04 lw s1,56(a0) - 28d6: 00ff0493 addi s1,t5,15 - 28da: 0000 unimp - 28dc: 0134 addi a3,sp,136 - 28de: 0000 unimp - 28e0: 0006 c.slli zero,0x1 - 28e2: 0cf503f3 0xcf503f3 - 28e6: 9f25 0x9f25 - 28e8: 0134 addi a3,sp,136 - 28ea: 0000 unimp - 28ec: 00000137 lui sp,0x0 - 28f0: 0006 c.slli zero,0x1 - 28f2: 935c 0x935c - 28f4: 5d04 lw s1,56(a0) - 28f6: 01370493 addi s1,a4,19 - 28fa: 0000 unimp - 28fc: 0150 addi a2,sp,132 - 28fe: 0000 unimp - 2900: 0006 c.slli zero,0x1 - 2902: 0cf503f3 0xcf503f3 - 2906: 9f25 0x9f25 - 2908: 0150 addi a2,sp,132 - 290a: 0000 unimp - 290c: 0188 addi a0,sp,192 - 290e: 0000 unimp - 2910: 0006 c.slli zero,0x1 - 2912: 935c 0x935c - 2914: 5d04 lw s1,56(a0) - 2916: 01880493 addi s1,a6,24 - 291a: 0000 unimp - 291c: 05b8 addi a4,sp,712 - 291e: 0000 unimp - 2920: 0006 c.slli zero,0x1 - 2922: 0cf503f3 0xcf503f3 - 2926: 9f25 0x9f25 - ... - 2934: 0074 addi a3,sp,12 - 2936: 0000 unimp - 2938: 0002 c.slli64 zero - 293a: 9f30 0x9f30 - 293c: 00ec addi a1,sp,76 - 293e: 0000 unimp - 2940: 0188 addi a0,sp,192 - 2942: 0000 unimp - 2944: 0002 c.slli64 zero - 2946: 9f30 0x9f30 - ... - 2950: 0070 addi a2,sp,12 - 2952: 0000 unimp - 2954: 0074 addi a3,sp,12 - 2956: 0000 unimp - 2958: 0002 c.slli64 zero - 295a: 9f30 0x9f30 - 295c: 0074 addi a3,sp,12 - 295e: 0000 unimp - 2960: 00ec addi a1,sp,76 - 2962: 0000 unimp - 2964: 0001 nop - 2966: 00018867 jalr a6,gp # 80016b68 <__global_pointer$> - 296a: 8000 0x8000 - 296c: 0004 0x4 - 296e: 0100 addi s0,sp,128 - 2970: 6700 flw fs0,8(a4) - 2972: 0490 addi a2,sp,576 - 2974: 0000 unimp - 2976: 05b8 addi a4,sp,712 - 2978: 0000 unimp - 297a: 0001 nop - 297c: 00000067 jr zero # 0 <_start-0x80000000> - 2980: 0000 unimp - 2982: 0000 unimp - 2984: 4800 lw s0,16(s0) - 2986: 0000 unimp - 2988: 7400 flw fs0,40(s0) - 298a: 0004 0x4 - 298c: 0600 addi s0,sp,768 - 298e: 8400 0x8400 - 2990: 0800 addi s0,sp,16 - 2992: 1aff 0x1aff - 2994: 909f 0004 b800 0xb8000004909f - 299a: 0005 c.nop 1 - 299c: 0600 addi s0,sp,768 - 299e: 8400 0x8400 - 29a0: 0800 addi s0,sp,16 - 29a2: 1aff 0x1aff - 29a4: 009f 0000 0000 0x9f - 29aa: 0000 unimp - 29ac: 4400 lw s0,8(s0) - 29ae: 0000 unimp - 29b0: 7000 flw fs0,32(s0) - 29b2: 0000 unimp - 29b4: 0700 addi s0,sp,896 - 29b6: 8300 0x8300 - 29b8: 0a00 addi s0,sp,272 - 29ba: ffff 0xffff - 29bc: 9f1a add t5,t5,t1 - 29be: 0070 addi a2,sp,12 - 29c0: 0000 unimp - 29c2: 00ec addi a1,sp,76 - 29c4: 0000 unimp - 29c6: 0001 nop - 29c8: 0000ec63 bltu ra,zero,29e0 <_start-0x7fffd620> - 29cc: 2c00 fld fs0,24(s0) - 29ce: 0001 nop - 29d0: 0700 addi s0,sp,896 - 29d2: 8300 0x8300 - 29d4: 0a00 addi s0,sp,272 - 29d6: ffff 0xffff - 29d8: 9f1a add t5,t5,t1 - 29da: 0134 addi a3,sp,136 - 29dc: 0000 unimp - 29de: 0160 addi s0,sp,140 - 29e0: 0000 unimp - 29e2: 00830007 0x830007 - 29e6: ff0a fsw ft2,188(sp) - 29e8: 1aff 0x1aff - 29ea: 609f 0001 6800 0x68000001609f - 29f0: 0001 nop - 29f2: 0900 addi s0,sp,144 - 29f4: 7b00 flw fs0,48(a4) - 29f6: 4400 lw s0,8(s0) - 29f8: 0a25 addi s4,s4,9 - 29fa: 07ff 0x7ff - 29fc: 9f1a add t5,t5,t1 - 29fe: 0168 addi a0,sp,140 - 2a00: 0000 unimp - 2a02: 0170 addi a2,sp,140 - 2a04: 0000 unimp - 2a06: 00830007 0x830007 - 2a0a: ff0a fsw ft2,188(sp) - 2a0c: 1aff 0x1aff - 2a0e: 709f 0001 7800 0x78000001709f - 2a14: 0001 nop - 2a16: 0900 addi s0,sp,144 - 2a18: 7b00 flw fs0,48(a4) - 2a1a: 4400 lw s0,8(s0) - 2a1c: 0a25 addi s4,s4,9 - 2a1e: 07ff 0x7ff - 2a20: 9f1a add t5,t5,t1 - 2a22: 0178 addi a4,sp,140 - 2a24: 0000 unimp - 2a26: 0180 addi s0,sp,192 - 2a28: 0000 unimp - 2a2a: 00830007 0x830007 - 2a2e: ff0a fsw ft2,188(sp) - 2a30: 1aff 0x1aff - 2a32: 809f 0001 8800 0x88000001809f - 2a38: 0001 nop - 2a3a: 0900 addi s0,sp,144 - 2a3c: 7b00 flw fs0,48(a4) - 2a3e: 4400 lw s0,8(s0) - 2a40: 0a25 addi s4,s4,9 - 2a42: 07ff 0x7ff - 2a44: 9f1a add t5,t5,t1 - 2a46: 0188 addi a0,sp,192 - 2a48: 0000 unimp - 2a4a: 02b0 addi a2,sp,328 - 2a4c: 0000 unimp - 2a4e: 0001 nop - 2a50: 00049063 bnez s1,2a50 <_start-0x7fffd5b0> - 2a54: b800 fsd fs0,48(s0) - 2a56: 0004 0x4 - 2a58: 0100 addi s0,sp,128 - 2a5a: 6300 flw fs0,0(a4) - 2a5c: 04c4 addi s1,sp,580 - 2a5e: 0000 unimp - 2a60: 04cc addi a1,sp,580 - 2a62: 0000 unimp - 2a64: 0001 nop - 2a66: 00058463 beqz a1,2a6e <_start-0x7fffd592> - 2a6a: 9800 0x9800 - 2a6c: 0005 c.nop 1 - 2a6e: 0100 addi s0,sp,128 - 2a70: 6300 flw fs0,0(a4) - ... - 2a7e: 006c addi a1,sp,12 - 2a80: 0000 unimp - 2a82: 0001 nop - 2a84: 6c5a flw fs8,148(sp) - 2a86: 0000 unimp - 2a88: ec00 fsw fs0,24(s0) - 2a8a: 0000 unimp - 2a8c: 0100 addi s0,sp,128 - 2a8e: 6200 flw fs0,0(a2) - 2a90: 00ec addi a1,sp,76 - 2a92: 0000 unimp - 2a94: 0128 addi a0,sp,136 - 2a96: 0000 unimp - 2a98: 0001 nop - 2a9a: 2858 fld fa4,144(s0) - 2a9c: 0001 nop - 2a9e: 3400 fld fs0,40(s0) - 2aa0: 0001 nop - 2aa2: 0100 addi s0,sp,128 - 2aa4: 6200 flw fs0,0(a2) - 2aa6: 0134 addi a3,sp,136 - 2aa8: 0000 unimp - 2aaa: 0148 addi a0,sp,132 - 2aac: 0000 unimp - 2aae: 0001 nop - 2ab0: 4858 lw a4,20(s0) - 2ab2: 0001 nop - 2ab4: 5000 lw s0,32(s0) - 2ab6: 0001 nop - 2ab8: 0200 addi s0,sp,256 - 2aba: 3000 fld fs0,32(s0) - 2abc: 509f 0001 8800 0x88000001509f - 2ac2: 0001 nop - 2ac4: 0100 addi s0,sp,128 - 2ac6: 5800 lw s0,48(s0) - 2ac8: 0188 addi a0,sp,192 - 2aca: 0000 unimp - 2acc: 023c addi a5,sp,264 - 2ace: 0000 unimp - 2ad0: 0001 nop - 2ad2: 9062 c.add zero,s8 - 2ad4: 0004 0x4 - 2ad6: b800 fsd fs0,48(s0) - 2ad8: 0004 0x4 - 2ada: 0100 addi s0,sp,128 - 2adc: 6200 flw fs0,0(a2) - 2ade: 04c4 addi s1,sp,580 - 2ae0: 0000 unimp - 2ae2: 04cc addi a1,sp,580 - 2ae4: 0000 unimp - 2ae6: 0001 nop - 2ae8: 8462 mv s0,s8 - 2aea: 0005 c.nop 1 - 2aec: 9800 0x9800 - 2aee: 0005 c.nop 1 - 2af0: 0100 addi s0,sp,128 - 2af2: 6200 flw fs0,0(a2) - ... - 2afc: 0044 addi s1,sp,4 - 2afe: 0000 unimp - 2b00: 0054 addi a3,sp,4 - 2b02: 0000 unimp - 2b04: 0001 nop - 2b06: 5459 li s0,-10 - 2b08: 0000 unimp - 2b0a: 5c00 lw s0,56(s0) - 2b0c: 0000 unimp - 2b0e: 0700 addi s0,sp,896 - 2b10: 7900 flw fs0,48(a0) - 2b12: 4000 lw s0,0(s0) - 2b14: 2440 fld fs0,136(s0) - 2b16: 9f21 0x9f21 - 2b18: 005c addi a5,sp,4 - 2b1a: 0000 unimp - 2b1c: 0068 addi a0,sp,12 - 2b1e: 0000 unimp - 2b20: 007b000b 0x7b000b - 2b24: 243c fld fa5,72(s0) - 2b26: 253c fld fa5,72(a0) - 2b28: 4040 lw s0,4(s0) - 2b2a: 2124 fld fs1,64(a0) - 2b2c: 689f 0000 1c00 0x1c000000689f - 2b32: 0001 nop - 2b34: 0100 addi s0,sp,128 - 2b36: 5900 lw s0,48(a0) - 2b38: 0124 addi s1,sp,136 - 2b3a: 0000 unimp - 2b3c: 0144 addi s1,sp,132 - 2b3e: 0000 unimp - 2b40: 0001 nop - 2b42: 4859 li a6,22 - 2b44: 0001 nop - 2b46: 6c00 flw fs0,24(s0) - 2b48: 0001 nop - 2b4a: 0100 addi s0,sp,128 - 2b4c: 5900 lw s0,48(a0) - 2b4e: 016c addi a1,sp,140 - 2b50: 0000 unimp - 2b52: 0178 addi a4,sp,140 - 2b54: 0000 unimp - 2b56: 007b0007 0x7b0007 - 2b5a: 243c fld fa5,72(s0) - 2b5c: 253c fld fa5,72(a0) - 2b5e: 789f 0001 7c00 0x7c000001789f - 2b64: 0001 nop - 2b66: 0100 addi s0,sp,128 - 2b68: 5900 lw s0,48(a0) - 2b6a: 017c addi a5,sp,140 - 2b6c: 0000 unimp - 2b6e: 0188 addi a0,sp,192 - 2b70: 0000 unimp - 2b72: 007b0007 0x7b0007 - 2b76: 243c fld fa5,72(s0) - 2b78: 253c fld fa5,72(a0) - 2b7a: 889f 0001 cc00 0xcc000001889f - 2b80: 0002 c.slli64 zero - 2b82: 0100 addi s0,sp,128 - 2b84: 5900 lw s0,48(a0) - 2b86: 0490 addi a2,sp,576 - 2b88: 0000 unimp - 2b8a: 04b8 addi a4,sp,584 - 2b8c: 0000 unimp - 2b8e: 0001 nop - 2b90: c459 beqz s0,2c1e <_start-0x7fffd3e2> - 2b92: 0004 0x4 - 2b94: cc00 sw s0,24(s0) - 2b96: 0004 0x4 - 2b98: 0100 addi s0,sp,128 - 2b9a: 5900 lw s0,48(a0) - 2b9c: 0584 addi s1,sp,704 - 2b9e: 0000 unimp - 2ba0: 0598 addi a4,sp,704 - 2ba2: 0000 unimp - 2ba4: 0001 nop - 2ba6: 0059 c.nop 22 - 2ba8: 0000 unimp - 2baa: 0000 unimp - 2bac: 0000 unimp - 2bae: b000 fsd fs0,32(s0) - 2bb0: 0000 unimp - 2bb2: b400 fsd fs0,40(s0) - 2bb4: 0000 unimp - 2bb6: 0200 addi s0,sp,256 - 2bb8: 3000 fld fs0,32(s0) - 2bba: b49f 0000 ec00 0xec000000b49f - 2bc0: 0000 unimp - 2bc2: 0100 addi s0,sp,128 - 2bc4: 5e00 lw s0,56(a2) - 2bc6: 0228 addi a0,sp,264 - 2bc8: 0000 unimp - 2bca: 0234 addi a3,sp,264 - 2bcc: 0000 unimp - 2bce: 0001 nop - 2bd0: 905e c.add zero,s7 - 2bd2: 0004 0x4 - 2bd4: a000 fsd fs0,0(s0) - 2bd6: 0004 0x4 - 2bd8: 0100 addi s0,sp,128 - 2bda: 5e00 lw s0,56(a2) - 2bdc: 04c4 addi s1,sp,580 - 2bde: 0000 unimp - 2be0: 04cc addi a1,sp,580 - 2be2: 0000 unimp - 2be4: 0001 nop - 2be6: 005e c.slli zero,0x17 - 2be8: 0000 unimp - 2bea: 0000 unimp - 2bec: 0000 unimp - 2bee: 8800 0x8800 - 2bf0: 0000 unimp - 2bf2: ec00 fsw fs0,24(s0) - 2bf4: 0000 unimp - 2bf6: 0600 addi s0,sp,768 - 2bf8: 8500 0x8500 - 2bfa: 0800 addi s0,sp,16 - 2bfc: 1aff 0x1aff - 2bfe: 889f 0001 7800 0x78000001889f - 2c04: 0004 0x4 - 2c06: 0600 addi s0,sp,768 - 2c08: 8500 0x8500 - 2c0a: 0800 addi s0,sp,16 - 2c0c: 1aff 0x1aff - 2c0e: 909f 0004 b800 0xb8000004909f - 2c14: 0005 c.nop 1 - 2c16: 0600 addi s0,sp,768 - 2c18: 8500 0x8500 - 2c1a: 0800 addi s0,sp,16 - 2c1c: 1aff 0x1aff - 2c1e: 009f 0000 0000 0x9f - 2c24: 0000 unimp - 2c26: 8400 0x8400 - 2c28: 0000 unimp - 2c2a: ac00 fsd fs0,24(s0) - 2c2c: 0000 unimp - 2c2e: 0700 addi s0,sp,896 - 2c30: 7a00 flw fs0,48(a2) - 2c32: 0a00 addi s0,sp,272 - 2c34: ffff 0xffff - 2c36: 9f1a add t5,t5,t1 - 2c38: 00ac addi a1,sp,72 - 2c3a: 0000 unimp - 2c3c: 00b0 addi a2,sp,72 - 2c3e: 0000 unimp - 2c40: 0008 0x8 - 2c42: ff7a fsw ft10,188(sp) - 2c44: ffff0a07 vlxseg8b.v v20,(t5),v31 - 2c48: 9f1a add t5,t5,t1 - 2c4a: 00b0 addi a2,sp,72 - 2c4c: 0000 unimp - 2c4e: 00c0 addi s0,sp,68 - 2c50: 0000 unimp - 2c52: 0001 nop - 2c54: 885a mv a6,s6 - 2c56: 0001 nop - 2c58: 9800 0x9800 - 2c5a: 0001 nop - 2c5c: 0700 addi s0,sp,896 - 2c5e: 7a00 flw fs0,48(a2) - 2c60: 0a00 addi s0,sp,272 - 2c62: ffff 0xffff - 2c64: 9f1a add t5,t5,t1 - 2c66: 01d0 addi a2,sp,196 - 2c68: 0000 unimp - 2c6a: 01d4 addi a3,sp,196 - 2c6c: 0000 unimp - 2c6e: 007a0007 0x7a0007 - 2c72: ff0a fsw ft2,188(sp) - 2c74: 1aff 0x1aff - 2c76: f09f 0001 0000 0x1f09f - 2c7c: 0002 c.slli64 zero - 2c7e: 0700 addi s0,sp,896 - 2c80: 7a00 flw fs0,48(a2) - 2c82: 0a00 addi s0,sp,272 - 2c84: ffff 0xffff - 2c86: 9f1a add t5,t5,t1 - 2c88: 0208 addi a0,sp,256 - 2c8a: 0000 unimp - 2c8c: 0210 addi a2,sp,256 - 2c8e: 0000 unimp - 2c90: 007a0007 0x7a0007 - 2c94: ff0a fsw ft2,188(sp) - 2c96: 1aff 0x1aff - 2c98: 189f 0002 2000 0x20000002189f - 2c9e: 0002 c.slli64 zero - 2ca0: 0700 addi s0,sp,896 - 2ca2: 7a00 flw fs0,48(a2) - 2ca4: 0a00 addi s0,sp,272 - 2ca6: ffff 0xffff - 2ca8: 9f1a add t5,t5,t1 - ... - 2cb2: 0074 addi a3,sp,12 - 2cb4: 0000 unimp - 2cb6: 00b0 addi a2,sp,72 - 2cb8: 0000 unimp - 2cba: 0001 nop - 2cbc: b066 fsd fs9,32(sp) - 2cbe: 0000 unimp - 2cc0: ec00 fsw fs0,24(s0) - 2cc2: 0000 unimp - 2cc4: 0100 addi s0,sp,128 - 2cc6: 5f00 lw s0,56(a4) - 2cc8: 0188 addi a0,sp,192 - 2cca: 0000 unimp - 2ccc: 01c4 addi s1,sp,196 - 2cce: 0000 unimp - 2cd0: 0001 nop - 2cd2: c466 sw s9,8(sp) - 2cd4: 0001 nop - 2cd6: d000 sw s0,32(s0) - 2cd8: 0001 nop - 2cda: 0100 addi s0,sp,128 - 2cdc: 5f00 lw s0,56(a4) - 2cde: 01d0 addi a2,sp,196 - 2ce0: 0000 unimp - 2ce2: 01e8 addi a0,sp,204 - 2ce4: 0000 unimp - 2ce6: 0001 nop - 2ce8: e866 fsw fs9,16(sp) - 2cea: 0001 nop - 2cec: f000 fsw fs0,32(s0) - 2cee: 0001 nop - 2cf0: 0200 addi s0,sp,256 - 2cf2: 3000 fld fs0,32(s0) - 2cf4: f09f 0001 2800 0x28000001f09f - 2cfa: 0002 c.slli64 zero - 2cfc: 0100 addi s0,sp,128 - 2cfe: 6600 flw fs0,8(a2) - 2d00: 0228 addi a0,sp,264 - 2d02: 0000 unimp - 2d04: 0240 addi s0,sp,260 - 2d06: 0000 unimp - 2d08: 0001 nop - 2d0a: 905f 0004 9c00 0x9c000004905f - 2d10: 0004 0x4 - 2d12: 0100 addi s0,sp,128 - 2d14: 5f00 lw s0,56(a4) - 2d16: 04c4 addi s1,sp,580 - 2d18: 0000 unimp - 2d1a: 04cc addi a1,sp,580 - 2d1c: 0000 unimp - 2d1e: 0001 nop - 2d20: 005f 0000 0000 0x5f - 2d26: 0000 unimp - 2d28: 8400 0x8400 - 2d2a: 0000 unimp - 2d2c: 9400 0x9400 - 2d2e: 0000 unimp - 2d30: 0100 addi s0,sp,128 - 2d32: 5800 lw s0,48(s0) - 2d34: 0094 addi a3,sp,64 - 2d36: 0000 unimp - 2d38: 009c addi a5,sp,64 - 2d3a: 0000 unimp - 2d3c: 00780007 0x780007 - 2d40: 4040 lw s0,4(s0) - 2d42: 2124 fld fs1,64(a0) - 2d44: a89f 0000 ec00 0xec000000a89f - 2d4a: 0000 unimp - 2d4c: 0100 addi s0,sp,128 - 2d4e: 5800 lw s0,48(s0) - 2d50: 0188 addi a0,sp,192 - 2d52: 0000 unimp - 2d54: 01b8 addi a4,sp,200 - 2d56: 0000 unimp - 2d58: 0001 nop - 2d5a: c058 sw a4,4(s0) - 2d5c: 0001 nop - 2d5e: e400 fsw fs0,8(s0) - 2d60: 0001 nop - 2d62: 0100 addi s0,sp,128 - 2d64: 5800 lw s0,48(s0) - 2d66: 01e8 addi a0,sp,204 - 2d68: 0000 unimp - 2d6a: 020c addi a1,sp,256 - 2d6c: 0000 unimp - 2d6e: 0001 nop - 2d70: 1858 addi a4,sp,52 - 2d72: 0002 c.slli64 zero - 2d74: 1c00 addi s0,sp,560 - 2d76: 0002 c.slli64 zero - 2d78: 0100 addi s0,sp,128 - 2d7a: 5800 lw s0,48(s0) - 2d7c: 0228 addi a0,sp,264 - 2d7e: 0000 unimp - 2d80: 02c4 addi s1,sp,324 - 2d82: 0000 unimp - 2d84: 0001 nop - 2d86: 9058 0x9058 - 2d88: 0004 0x4 - 2d8a: 9800 0x9800 - 2d8c: 0004 0x4 - 2d8e: 0100 addi s0,sp,128 - 2d90: 5800 lw s0,48(s0) - 2d92: 04c4 addi s1,sp,580 - 2d94: 0000 unimp - 2d96: 04cc addi a1,sp,580 - 2d98: 0000 unimp - 2d9a: 0001 nop - 2d9c: 0058 addi a4,sp,4 - 2d9e: 0000 unimp - 2da0: 0000 unimp - 2da2: 0000 unimp - 2da4: 2800 fld fs0,16(s0) - 2da6: 0002 c.slli64 zero - 2da8: e400 fsw fs0,8(s0) - 2daa: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 2dae: 3000 fld fs0,32(s0) - 2db0: a09f 0004 b800 0xb8000004a09f - 2db6: 0004 0x4 - 2db8: 0100 addi s0,sp,128 - 2dba: 5e00 lw s0,56(a2) - 2dbc: 04cc addi a1,sp,580 - 2dbe: 0000 unimp - 2dc0: 04d4 addi a3,sp,580 - 2dc2: 0000 unimp - 2dc4: 0002 c.slli64 zero - 2dc6: 9f30 0x9f30 - ... - 2dd0: 00cc addi a1,sp,68 - 2dd2: 0000 unimp - 2dd4: 00ec addi a1,sp,76 - 2dd6: 0000 unimp - 2dd8: 0001 nop - 2dda: 285c fld fa5,144(s0) - 2ddc: 0002 c.slli64 zero - 2dde: 5800 lw s0,48(s0) - 2de0: 0004 0x4 - 2de2: 0100 addi s0,sp,128 - 2de4: 5c00 lw s0,56(s0) - 2de6: 0490 addi a2,sp,576 - 2de8: 0000 unimp - 2dea: 0494 addi a3,sp,576 - 2dec: 0000 unimp - 2dee: 0001 nop - 2df0: 945c 0x945c - 2df2: 0004 0x4 - 2df4: a000 fsd fs0,0(s0) - 2df6: 0004 0x4 - 2df8: 0600 addi s0,sp,768 - 2dfa: 8400 0x8400 - 2dfc: 0800 addi s0,sp,16 - 2dfe: 1aff 0x1aff - 2e00: a09f 0004 c800 0xc8000004a09f - 2e06: 0004 0x4 - 2e08: 0100 addi s0,sp,128 - 2e0a: 5c00 lw s0,56(s0) - 2e0c: 04c8 addi a0,sp,580 - 2e0e: 0000 unimp - 2e10: 04cc addi a1,sp,580 - 2e12: 0000 unimp - 2e14: 0006 c.slli zero,0x1 - 2e16: 0085 addi ra,ra,1 - 2e18: ff08 fsw fa0,56(a4) - 2e1a: 9f1a add t5,t5,t1 - 2e1c: 04cc addi a1,sp,580 - 2e1e: 0000 unimp - 2e20: 0594 addi a3,sp,704 - 2e22: 0000 unimp - 2e24: 0001 nop - 2e26: 985c 0x985c - 2e28: 0005 c.nop 1 - 2e2a: b800 fsd fs0,48(s0) - 2e2c: 0005 c.nop 1 - 2e2e: 0100 addi s0,sp,128 - 2e30: 5c00 lw s0,56(s0) - ... - 2e3a: 00d0 addi a2,sp,68 - 2e3c: 0000 unimp - 2e3e: 00ec addi a1,sp,76 - 2e40: 0000 unimp - 2e42: 0001 nop - 2e44: 2860 fld fs0,208(s0) - 2e46: 0002 c.slli64 zero - 2e48: e800 fsw fs0,16(s0) - 2e4a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 2e4e: 6000 flw fs0,0(s0) - 2e50: 03e8 addi a0,sp,460 - 2e52: 0000 unimp - 2e54: 0490 addi a2,sp,576 - 2e56: 0000 unimp - 2e58: 0001 nop - 2e5a: 905d srli s0,s0,0x37 - 2e5c: 0004 0x4 - 2e5e: b800 fsd fs0,48(s0) - 2e60: 0004 0x4 - 2e62: 0100 addi s0,sp,128 - 2e64: 6000 flw fs0,0(s0) - 2e66: 04c4 addi s1,sp,580 - 2e68: 0000 unimp - 2e6a: 04d0 addi a2,sp,580 - 2e6c: 0000 unimp - 2e6e: 0001 nop - 2e70: d060 sw s0,100(s0) - 2e72: 0004 0x4 - 2e74: d400 sw s0,40(s0) - 2e76: 0004 0x4 - 2e78: 0300 addi s0,sp,384 - 2e7a: 7a00 flw fs0,48(a2) - 2e7c: 9f01 0x9f01 - 2e7e: 04d4 addi a3,sp,580 - 2e80: 0000 unimp - 2e82: 04dc addi a5,sp,580 - 2e84: 0000 unimp - 2e86: 0001 nop - 2e88: dc5d beqz s0,2e46 <_start-0x7fffd1ba> - 2e8a: 0004 0x4 - 2e8c: 3800 fld fs0,48(s0) - 2e8e: 0005 c.nop 1 - 2e90: 0100 addi s0,sp,128 - 2e92: 5b00 lw s0,48(a4) - 2e94: 0538 addi a4,sp,648 - 2e96: 0000 unimp - 2e98: 0548 addi a0,sp,644 - 2e9a: 0000 unimp - 2e9c: 0002 c.slli64 zero - 2e9e: 9f30 0x9f30 - 2ea0: 0550 addi a2,sp,644 - 2ea2: 0000 unimp - 2ea4: 0584 addi s1,sp,704 - 2ea6: 0000 unimp - 2ea8: 0001 nop - 2eaa: 0005845b 0x5845b - 2eae: 9800 0x9800 - 2eb0: 0005 c.nop 1 - 2eb2: 0100 addi s0,sp,128 - 2eb4: 6000 flw fs0,0(s0) - 2eb6: 05a8 addi a0,sp,712 - 2eb8: 0000 unimp - 2eba: 05b8 addi a4,sp,712 - 2ebc: 0000 unimp - 2ebe: 0001 nop - 2ec0: 0000005b 0x5b - 2ec4: 0000 unimp - 2ec6: 0000 unimp - 2ec8: c400 sw s0,8(s0) - 2eca: d4000003 lb zero,-704(zero) # fffffd40 <__BSS_END__+0x7ffe8fc8> - 2ece: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 2ed2: 5f00 lw s0,56(a4) - 2ed4: 03e0 addi s0,sp,460 - 2ed6: 0000 unimp - 2ed8: 0408 addi a0,sp,512 - 2eda: 0000 unimp - 2edc: 0001 nop - 2ede: 085f 0004 0c00 0xc000004085f - 2ee4: 0004 0x4 - 2ee6: 0300 addi s0,sp,384 - 2ee8: 7e00 flw fs0,56(a2) - 2eea: 9f7c 0x9f7c - 2eec: 040c addi a1,sp,512 - 2eee: 0000 unimp - 2ef0: 0410 addi a2,sp,512 - 2ef2: 0000 unimp - 2ef4: 0001 nop - 2ef6: 105e c.slli zero,0x37 - 2ef8: 0004 0x4 - 2efa: 2800 fld fs0,16(s0) - 2efc: 0004 0x4 - 2efe: 0100 addi s0,sp,128 - 2f00: 5f00 lw s0,56(a4) - 2f02: 0428 addi a0,sp,520 - 2f04: 0000 unimp - 2f06: 0434 addi a3,sp,520 - 2f08: 0000 unimp - 2f0a: 000a c.slli zero,0x2 - 2f0c: 007f 0x7f - 2f0e: 00782533 slt a0,a6,t2 - 2f12: 244d jal 31b4 <_start-0x7fffce4c> - 2f14: 9f21 0x9f21 - 2f16: 0434 addi a3,sp,520 - 2f18: 0000 unimp - 2f1a: 0438 addi a4,sp,520 - 2f1c: 0000 unimp - 2f1e: 0008 0x8 - 2f20: 0078 addi a4,sp,12 - 2f22: 244d jal 31c4 <_start-0x7fffce3c> - 2f24: 007e c.slli zero,0x1f - 2f26: 9f21 0x9f21 - 2f28: 0438 addi a4,sp,520 - 2f2a: 0000 unimp - 2f2c: 043c addi a5,sp,520 - 2f2e: 0000 unimp - 2f30: 0006 c.slli zero,0x1 - 2f32: 007e c.slli zero,0x1f - 2f34: 007f 0x7f - 2f36: 9f21 0x9f21 - 2f38: 043c addi a5,sp,520 - 2f3a: 0000 unimp - 2f3c: 0440 addi s0,sp,516 - 2f3e: 0000 unimp - 2f40: 0008 0x8 - 2f42: 0078 addi a4,sp,12 - 2f44: 244d jal 31e6 <_start-0x7fffce1a> - 2f46: 007e c.slli zero,0x1f - 2f48: 9f21 0x9f21 - 2f4a: 0440 addi s0,sp,516 - 2f4c: 0000 unimp - 2f4e: 0490 addi a2,sp,576 - 2f50: 0000 unimp - 2f52: 0001 nop - 2f54: a05f 0004 c000 0xc0000004a05f - 2f5a: 0004 0x4 - 2f5c: 0100 addi s0,sp,128 - 2f5e: 5f00 lw s0,56(a4) - 2f60: 04cc addi a1,sp,580 - 2f62: 0000 unimp - 2f64: 04fc addi a5,sp,588 - 2f66: 0000 unimp - 2f68: 0001 nop - 2f6a: 085f 0005 2800 0x28000005085f - 2f70: 0005 c.nop 1 - 2f72: 0100 addi s0,sp,128 - 2f74: 5f00 lw s0,56(a4) - 2f76: 0528 addi a0,sp,648 - 2f78: 0000 unimp - 2f7a: 052c addi a1,sp,648 - 2f7c: 0000 unimp - 2f7e: 7c7e0003 lb zero,1991(t3) - 2f82: 2c9f 0005 3000 0x300000052c9f - 2f88: 0005 c.nop 1 - 2f8a: 0100 addi s0,sp,128 - 2f8c: 5e00 lw s0,56(a2) - 2f8e: 0530 addi a2,sp,648 - 2f90: 0000 unimp - 2f92: 0540 addi s0,sp,644 - 2f94: 0000 unimp - 2f96: 0001 nop - 2f98: 445f 0005 4800 0x48000005445f - 2f9e: 0005 c.nop 1 - 2fa0: 0100 addi s0,sp,128 - 2fa2: 5f00 lw s0,56(a4) - 2fa4: 0550 addi a2,sp,644 - 2fa6: 0000 unimp - 2fa8: 0574 addi a3,sp,652 - 2faa: 0000 unimp - 2fac: 0001 nop - 2fae: 7c5f 0005 8400 0x840000057c5f - 2fb4: 0005 c.nop 1 - 2fb6: 0100 addi s0,sp,128 - 2fb8: 5f00 lw s0,56(a4) - 2fba: 05a8 addi a0,sp,712 - 2fbc: 0000 unimp - 2fbe: 05b0 addi a2,sp,712 - 2fc0: 0000 unimp - 2fc2: 0001 nop - 2fc4: 005f 0000 0000 0x5f - 2fca: 0000 unimp - 2fcc: c400 sw s0,8(s0) - 2fce: 28000003 lb zero,640(zero) # 280 <_start-0x7ffffd80> - 2fd2: 0004 0x4 - 2fd4: 0100 addi s0,sp,128 - 2fd6: 5800 lw s0,48(s0) - 2fd8: 0428 addi a0,sp,520 - 2fda: 0000 unimp - 2fdc: 0440 addi s0,sp,516 - 2fde: 0000 unimp - 2fe0: 0005 c.nop 1 - 2fe2: 0078 addi a4,sp,12 - 2fe4: 409f2533 0x409f2533 - 2fe8: 0004 0x4 - 2fea: 4400 lw s0,8(s0) - 2fec: 0004 0x4 - 2fee: 0100 addi s0,sp,128 - 2ff0: 5800 lw s0,48(s0) - 2ff2: 04a0 addi s0,sp,584 - 2ff4: 0000 unimp - 2ff6: 04bc addi a5,sp,584 - 2ff8: 0000 unimp - 2ffa: 0001 nop - 2ffc: cc58 sw a4,28(s0) - 2ffe: 0004 0x4 - 3000: 4800 lw s0,16(s0) - 3002: 0005 c.nop 1 - 3004: 0100 addi s0,sp,128 - 3006: 5800 lw s0,48(s0) - 3008: 0550 addi a2,sp,644 - 300a: 0000 unimp - 300c: 057c addi a5,sp,652 - 300e: 0000 unimp - 3010: 0001 nop - 3012: 7c58 flw fa4,60(s0) - 3014: 0005 c.nop 1 - 3016: 8400 0x8400 - 3018: 0005 c.nop 1 - 301a: 0200 addi s0,sp,256 - 301c: 3000 fld fs0,32(s0) - 301e: a89f 0005 ac00 0xac000005a89f - 3024: 0005 c.nop 1 - 3026: 0100 addi s0,sp,128 - 3028: 5800 lw s0,48(s0) - ... - 3032: 0100 addi s0,sp,128 - 3034: 0000 unimp - 3036: 0104 addi s1,sp,128 - 3038: 0000 unimp - 303a: 0001 nop - 303c: 045a slli s0,s0,0x16 - 303e: 0001 nop - 3040: 3400 fld fs0,40(s0) - 3042: 0001 nop - 3044: 0100 addi s0,sp,128 - 3046: 5e00 lw s0,56(a2) - 3048: 0138 addi a4,sp,136 - 304a: 0000 unimp - 304c: 0140 addi s0,sp,132 - 304e: 0000 unimp - 3050: 0001 nop - 3052: 405a 0x405a - 3054: 0001 nop - 3056: 5000 lw s0,32(s0) - 3058: 0001 nop - 305a: 0100 addi s0,sp,128 - 305c: 5e00 lw s0,56(a2) - ... - 3066: 019c addi a5,sp,192 - 3068: 0000 unimp - 306a: 01a0 addi s0,sp,200 - 306c: 0000 unimp - 306e: 0001 nop - 3070: a05a fsd fs6,0(sp) - 3072: 0001 nop - 3074: d000 sw s0,32(s0) - 3076: 0001 nop - 3078: 0100 addi s0,sp,128 - 307a: 5d00 lw s0,56(a0) - 307c: 01d8 addi a4,sp,196 - 307e: 0000 unimp - 3080: 01e0 addi s0,sp,204 - 3082: 0000 unimp - 3084: 0001 nop - 3086: e05a fsw fs6,0(sp) - 3088: 0001 nop - 308a: f000 fsw fs0,32(s0) - 308c: 0001 nop - 308e: 0100 addi s0,sp,128 - 3090: 5d00 lw s0,56(a0) - ... - 309a: 02d8 addi a4,sp,324 - 309c: 0000 unimp - 309e: 035c addi a5,sp,388 - 30a0: 0000 unimp - 30a2: 0001 nop - 30a4: 0062 c.slli zero,0x18 - 30a6: 0000 unimp - 30a8: 0000 unimp - 30aa: 0000 unimp - 30ac: b400 fsd fs0,40(s0) - 30ae: 0002 c.slli64 zero - 30b0: e400 fsw fs0,8(s0) - 30b2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 30b6: 6d00 flw fs0,24(a0) - 30b8: 04cc addi a1,sp,580 - 30ba: 0000 unimp - 30bc: 04d4 addi a3,sp,580 - 30be: 0000 unimp - 30c0: 0001 nop - 30c2: 006d c.nop 27 - 30c4: 0000 unimp - 30c6: 0000 unimp - 30c8: 0000 unimp - 30ca: 1c00 addi s0,sp,560 - 30cc: 6c000003 lb zero,1728(zero) # 6c0 <_start-0x7ffff940> - 30d0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 30d4: 5d00 lw s0,56(a0) - ... - 30de: 0304 addi s1,sp,384 - 30e0: 0000 unimp - 30e2: 03e4 addi s1,sp,460 - 30e4: 0000 unimp - 30e6: 0001 nop - 30e8: 0004cc6f jal s8,4f0e8 <_start-0x7ffb0f18> - 30ec: d400 sw s0,40(s0) - 30ee: 0004 0x4 - 30f0: 0100 addi s0,sp,128 - 30f2: 6f00 flw fs0,24(a4) - ... - 30fc: 0248 addi a0,sp,260 - 30fe: 0000 unimp - 3100: 0270 addi a2,sp,268 - 3102: 0000 unimp - 3104: 0001 nop - 3106: 705d c.lui zero,0xffff7 - 3108: 0002 c.slli64 zero - 310a: 8c00 0x8c00 - 310c: 0002 c.slli64 zero - 310e: 0600 addi s0,sp,768 - 3110: 7f00 flw fs0,56(a4) - 3112: 8200 0x8200 - 3114: 1e00 addi s0,sp,816 - 3116: 009f 0000 0000 0x9f - 311c: 0000 unimp - 311e: 4800 lw s0,16(s0) - 3120: 0002 c.slli64 zero - 3122: 5400 lw s0,40(s0) - 3124: 0002 c.slli64 zero - 3126: 0100 addi s0,sp,128 - 3128: 5b00 lw s0,48(a4) - 312a: 0254 addi a3,sp,260 - 312c: 0000 unimp - 312e: 025c addi a5,sp,260 - 3130: 0000 unimp - 3132: 0006 c.slli zero,0x1 - 3134: 0081 addi ra,ra,0 - 3136: 0082 c.slli64 ra - 3138: 9f1e add t5,t5,t2 - 313a: 025c addi a5,sp,260 - 313c: 0000 unimp - 313e: 026c addi a1,sp,268 - 3140: 0000 unimp - 3142: 0001 nop - 3144: 00026c5b 0x26c5b - 3148: 7000 flw fs0,32(s0) - 314a: 0002 c.slli64 zero - 314c: 0800 addi s0,sp,16 - 314e: 7d00 flw fs0,56(a0) - 3150: 4000 lw s0,0(s0) - 3152: 7625 lui a2,0xfffe9 - 3154: 2200 fld fs0,0(a2) - 3156: 709f 0002 8c00 0x8c000002709f - 315c: 0002 c.slli64 zero - 315e: 0b00 addi s0,sp,400 - 3160: 7f00 flw fs0,56(a4) - 3162: 8200 0x8200 - 3164: 1e00 addi s0,sp,816 - 3166: 2540 fld fs0,136(a0) - 3168: 0076 c.slli zero,0x1d - 316a: 9f22 add t5,t5,s0 - ... - 3174: 024c addi a1,sp,260 - 3176: 0000 unimp - 3178: 0304 addi s1,sp,384 - 317a: 0000 unimp - 317c: 0001 nop - 317e: 0000006f j 317e <_start-0x7fffce82> - 3182: 0000 unimp - 3184: 0000 unimp - 3186: 5c00 lw s0,56(s0) - 3188: 0002 c.slli64 zero - 318a: 5400 lw s0,40(s0) - 318c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 3190: 6c00 flw fs0,24(s0) - ... - 319a: 0228 addi a0,sp,264 - 319c: 0000 unimp - 319e: 023c addi a5,sp,264 - 31a0: 0000 unimp - 31a2: 0001 nop - 31a4: 0062 c.slli zero,0x18 - 31a6: 0000 unimp - 31a8: 0000 unimp - 31aa: 0000 unimp - 31ac: 3400 fld fs0,40(s0) - 31ae: 0002 c.slli64 zero - 31b0: 4000 lw s0,0(s0) - 31b2: 0002 c.slli64 zero - 31b4: 0100 addi s0,sp,128 - 31b6: 5f00 lw s0,56(a4) - ... - 31c0: 0234 addi a3,sp,264 - 31c2: 0000 unimp - 31c4: 029c addi a5,sp,320 - 31c6: 0000 unimp - 31c8: 0001 nop - 31ca: 005e c.slli zero,0x17 - 31cc: 0000 unimp - 31ce: 0000 unimp - 31d0: 0000 unimp - 31d2: 3800 fld fs0,48(s0) - 31d4: 0002 c.slli64 zero - 31d6: e800 fsw fs0,16(s0) - 31d8: 0002 c.slli64 zero - 31da: 0100 addi s0,sp,128 - 31dc: 6100 flw fs0,0(a0) - ... - 31e6: 0288 addi a0,sp,320 - 31e8: 0000 unimp - 31ea: 02c0 addi s0,sp,324 - 31ec: 0000 unimp - 31ee: 0001 nop - 31f0: 005d c.nop 23 - 31f2: 0000 unimp - 31f4: 0000 unimp - 31f6: 0000 unimp - 31f8: 8800 0x8800 - 31fa: 0002 c.slli64 zero - 31fc: 8c00 0x8c00 - 31fe: 0002 c.slli64 zero - 3200: 0600 addi s0,sp,768 - 3202: 8e00 0x8e00 - 3204: 8200 0x8200 - 3206: 1e00 addi s0,sp,816 - 3208: 8c9f 0002 9400 0x940000028c9f - 320e: 0002 c.slli64 zero - 3210: 0100 addi s0,sp,128 - 3212: 6200 flw fs0,0(a2) - 3214: 029c addi a5,sp,320 - 3216: 0000 unimp - 3218: 02bc addi a5,sp,328 - 321a: 0000 unimp - 321c: 0001 nop - 321e: 0062 c.slli zero,0x18 - 3220: 0000 unimp - 3222: 0000 unimp - 3224: 0000 unimp - 3226: 8800 0x8800 - 3228: 0002 c.slli64 zero - 322a: ac00 fsd fs0,24(s0) - 322c: 0002 c.slli64 zero - 322e: 0100 addi s0,sp,128 - 3230: 6d00 flw fs0,24(a0) - ... - 323a: 029c addi a5,sp,320 - 323c: 0000 unimp - 323e: 02b8 addi a4,sp,328 - 3240: 0000 unimp - 3242: 0001 nop - 3244: 005e c.slli zero,0x17 - 3246: 0000 unimp - 3248: 0000 unimp - 324a: 0000 unimp - 324c: 8000 0x8000 - 324e: 0002 c.slli64 zero - 3250: c400 sw s0,8(s0) - 3252: 0002 c.slli64 zero - 3254: 0100 addi s0,sp,128 - 3256: 5800 lw s0,48(s0) - ... - 3260: 0280 addi s0,sp,320 - 3262: 0000 unimp - 3264: 029c addi a5,sp,320 - 3266: 0000 unimp - 3268: 0001 nop - 326a: 005e c.slli zero,0x17 - 326c: 0000 unimp - 326e: 0000 unimp - 3270: 0000 unimp - 3272: 8000 0x8000 - 3274: 0002 c.slli64 zero - 3276: 7400 flw fs0,40(s0) - 3278: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 327c: 6e00 flw fs0,24(a2) - ... - 3286: 02d8 addi a4,sp,324 - 3288: 0000 unimp - 328a: 0310 addi a2,sp,384 - 328c: 0000 unimp - 328e: 0001 nop - 3290: 005e c.slli zero,0x17 - 3292: 0000 unimp - 3294: 0000 unimp - 3296: 0000 unimp - 3298: d800 sw s0,48(s0) - 329a: 0002 c.slli64 zero - 329c: e000 fsw fs0,0(s0) - 329e: 0002 c.slli64 zero - 32a0: 0600 addi s0,sp,768 - 32a2: 8100 0x8100 - 32a4: 7900 flw fs0,48(a0) - 32a6: 1e00 addi s0,sp,816 - 32a8: e09f 0002 e800 0xe8000002e09f - 32ae: 0002 c.slli64 zero - 32b0: 0100 addi s0,sp,128 - 32b2: 5d00 lw s0,56(a0) - 32b4: 02e8 addi a0,sp,332 - 32b6: 0000 unimp - 32b8: 02ec addi a1,sp,332 - 32ba: 0000 unimp - 32bc: 0008 0x8 - 32be: 007e c.slli zero,0x1f - 32c0: 2540 fld fs0,136(a0) - 32c2: 007d c.nop 31 - 32c4: 9f22 add t5,t5,s0 - 32c6: 02f0 addi a2,sp,332 - 32c8: 0000 unimp - 32ca: 030c addi a1,sp,384 - 32cc: 0000 unimp - 32ce: 0001 nop - 32d0: 005d c.nop 23 - 32d2: 0000 unimp - 32d4: 0000 unimp - 32d6: 0000 unimp - 32d8: dc00 sw s0,56(s0) - 32da: 0002 c.slli64 zero - 32dc: 2800 fld fs0,16(s0) - 32de: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 32e2: 5600 lw s0,40(a2) - ... - 32ec: 02e4 addi s1,sp,332 - 32ee: 0000 unimp - 32f0: 0308 addi a0,sp,384 - 32f2: 0000 unimp - 32f4: 0001 nop - 32f6: 005f 0000 0000 0x5f - 32fc: 0000 unimp - 32fe: d800 sw s0,48(s0) - 3300: 0002 c.slli64 zero - 3302: 3000 fld fs0,32(s0) - 3304: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 3308: 5800 lw s0,48(s0) - ... - 3312: 02d8 addi a4,sp,324 - 3314: 0000 unimp - 3316: 02e8 addi a0,sp,332 - 3318: 0000 unimp - 331a: 0001 nop - 331c: 0061 c.nop 24 - 331e: 0000 unimp - 3320: 0000 unimp - 3322: 0000 unimp - 3324: 1c00 addi s0,sp,560 - 3326: 4c000003 lb zero,1216(zero) # 4c0 <_start-0x7ffffb40> - 332a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 332e: 6100 flw fs0,0(a0) - ... - 3338: 031c addi a5,sp,384 - 333a: 0000 unimp - 333c: 0324 addi s1,sp,392 - 333e: 0000 unimp - 3340: 0006 c.slli zero,0x1 - 3342: 008e slli ra,ra,0x3 - 3344: 0079 c.nop 30 - 3346: 9f1e add t5,t5,t2 - 3348: 0324 addi s1,sp,392 - 334a: 0000 unimp - 334c: 032c addi a1,sp,392 - 334e: 0000 unimp - 3350: 0001 nop - 3352: 3459 jal 2dd8 <_start-0x7fffd228> - 3354: 84000003 lb zero,-1984(zero) # fffff840 <__BSS_END__+0x7ffe8ac8> - 3358: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 335c: 5900 lw s0,48(a0) - ... - 3366: 0320 addi s0,sp,392 - 3368: 0000 unimp - 336a: 0340 addi s0,sp,388 - 336c: 0000 unimp - 336e: 0001 nop - 3370: 005f 0000 0000 0x5f - 3376: 0000 unimp - 3378: 2800 fld fs0,16(s0) - 337a: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe90c8> - 337e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 3382: 5600 lw s0,40(a2) - 3384: 04cc addi a1,sp,580 - 3386: 0000 unimp - 3388: 04d4 addi a3,sp,580 - 338a: 0000 unimp - 338c: 0001 nop - 338e: 0056 c.slli zero,0x15 - 3390: 0000 unimp - 3392: 0000 unimp - 3394: 0000 unimp - 3396: 1c00 addi s0,sp,560 - 3398: 30000003 lb zero,768(zero) # 300 <_start-0x7ffffd00> - 339c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 33a0: 5800 lw s0,48(s0) - ... - 33aa: 031c addi a5,sp,384 - 33ac: 0000 unimp - 33ae: 0374 addi a3,sp,396 - 33b0: 0000 unimp - 33b2: 0001 nop - 33b4: 006e c.slli zero,0x1b - 33b6: 0000 unimp - 33b8: 0000 unimp - 33ba: 0000 unimp - 33bc: 5c00 lw s0,56(s0) - 33be: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe90c8> - 33c2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 33c6: 6200 flw fs0,0(a2) - 33c8: 04cc addi a1,sp,580 - 33ca: 0000 unimp - 33cc: 04d4 addi a3,sp,580 - 33ce: 0000 unimp - 33d0: 0001 nop - 33d2: 0062 c.slli zero,0x18 - 33d4: 0000 unimp - 33d6: 0000 unimp - 33d8: 0000 unimp - 33da: 6000 flw fs0,0(s0) - 33dc: 64000003 lb zero,1600(zero) # 640 <_start-0x7ffff9c0> - 33e0: 11000003 lb zero,272(zero) # 110 <_start-0x7ffffef0> - 33e4: 7e00 flw fs0,56(a2) - 33e6: 4000 lw s0,0(s0) - 33e8: 8d22244b 0x8d22244b - 33ec: 4000 lw s0,0(s0) - 33ee: 2d22244b 0x2d22244b - 33f2: ff08 fsw fa0,56(a4) - 33f4: 9f1a add t5,t5,t1 - 33f6: 0364 addi s1,sp,396 - 33f8: 0000 unimp - 33fa: 0378 addi a4,sp,396 - 33fc: 0000 unimp - 33fe: 001f 007e 4b40 0x4b40007e001f - 3404: 2224 fld fs1,64(a2) - 3406: 008d addi ra,ra,3 - 3408: 4b40 lw s0,20(a4) - 340a: 2224 fld fs1,64(a2) - 340c: 782d lui a6,0xfffeb - 340e: 4000 lw s0,0(s0) - 3410: 8222244b fnmsub.d fs0,ft4,ft2,fa6,rdn - 3414: 4000 lw s0,0(s0) - 3416: 2d22244b 0x2d22244b - 341a: 0821 addi a6,a6,8 - 341c: 1aff 0x1aff - 341e: 009f 0000 0000 0x9f - 3424: 0000 unimp - 3426: 6c00 flw fs0,24(s0) - 3428: 8c000003 lb zero,-1856(zero) # fffff8c0 <__BSS_END__+0x7ffe8b48> - 342c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 3430: 5d00 lw s0,56(a0) - ... - 343a: 0370 addi a2,sp,396 - 343c: 0000 unimp - 343e: 0374 addi a3,sp,396 - 3440: 0000 unimp - 3442: 0011 c.nop 4 - 3444: 0081 addi ra,ra,0 - 3446: 4b40 lw s0,20(a4) - 3448: 2224 fld fs1,64(a2) - 344a: 4b40008f 0x4b40008f - 344e: 2224 fld fs1,64(a2) - 3450: 082d addi a6,a6,11 - 3452: 1aff 0x1aff - 3454: 749f 0003 8800 0x88000003749f - 345a: 1f000003 lb zero,496(zero) # 1f0 <_start-0x7ffffe10> - 345e: 8100 0x8100 - 3460: 4000 lw s0,0(s0) - 3462: 8f22244b fnmsub.q fs0,ft4,fs2,fa7,rdn - 3466: 4000 lw s0,0(s0) - 3468: 2d22244b 0x2d22244b - 346c: 008e slli ra,ra,0x3 - 346e: 4b40 lw s0,20(a4) - 3470: 2224 fld fs1,64(a2) - 3472: 007d c.nop 31 - 3474: 4b40 lw s0,20(a4) - 3476: 2224 fld fs1,64(a2) - 3478: 212d jal 38a2 <_start-0x7fffc75e> - 347a: ff08 fsw fa0,56(a4) - 347c: 9f1a add t5,t5,t1 - ... - 3486: 03a8 addi a0,sp,456 - 3488: 0000 unimp - 348a: 03b8 addi a4,sp,456 - 348c: 0000 unimp - 348e: 000d c.nop 3 - 3490: 008c addi a1,sp,64 - 3492: 2439 jal 36a0 <_start-0x7fffc960> - 3494: 3021007b 0x3021007b - 3498: 082e slli a6,a6,0xb - 349a: 1aff 0x1aff - 349c: 009f 0000 0000 0x9f - 34a2: 0000 unimp - 34a4: 7400 flw fs0,40(s0) - 34a6: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe90c8> - 34aa: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 34ae: 3900 fld fs0,48(a0) - 34b0: cc9f 0004 d400 0xd4000004cc9f - 34b6: 0004 0x4 - 34b8: 0200 addi s0,sp,256 - 34ba: 3900 fld fs0,48(a0) - 34bc: 009f 0000 0000 0x9f - 34c2: 0000 unimp - 34c4: 7400 flw fs0,40(s0) - 34c6: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe90c8> - 34ca: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 34ce: 4700 lw s0,8(a4) - 34d0: cc9f 0004 d400 0xd4000004cc9f - 34d6: 0004 0x4 - 34d8: 0200 addi s0,sp,256 - 34da: 4700 lw s0,8(a4) - 34dc: 009f 0000 0000 0x9f - 34e2: 0000 unimp - 34e4: 7400 flw fs0,40(s0) - 34e6: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe90c8> - 34ea: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 34ee: 3100 fld fs0,32(a0) - 34f0: cc9f 0004 d400 0xd4000004cc9f - 34f6: 0004 0x4 - 34f8: 0200 addi s0,sp,256 - 34fa: 3100 fld fs0,32(a0) - 34fc: 009f 0000 0000 0x9f - 3502: 0000 unimp - 3504: 7400 flw fs0,40(s0) - 3506: a8000003 lb zero,-1408(zero) # fffffa80 <__BSS_END__+0x7ffe8d08> - 350a: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 350e: 3100 fld fs0,32(a0) - 3510: a89f 0003 e400 0xe4000003a89f - 3516: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 351a: 3300 fld fs0,32(a4) - 351c: cc9f 0004 d400 0xd4000004cc9f - 3522: 0004 0x4 - 3524: 0200 addi s0,sp,256 - 3526: 3300 fld fs0,32(a4) - 3528: 009f 0000 0000 0x9f - 352e: 0000 unimp - 3530: 7400 flw fs0,40(s0) - 3532: b0000003 lb zero,-1280(zero) # fffffb00 <__BSS_END__+0x7ffe8d88> - 3536: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - 353a: 8c00 0x8c00 - 353c: 3900 fld fs0,48(a0) - 353e: 7b24 flw fs1,112(a4) - 3540: 2100 fld fs0,0(a0) - 3542: b09f 0003 b400 0xb4000003b09f - 3548: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 354c: 5f00 lw s0,56(a4) - 354e: 03b4 addi a3,sp,456 - 3550: 0000 unimp - 3552: 03b8 addi a4,sp,456 - 3554: 0000 unimp - 3556: 0008 0x8 - 3558: 008c addi a1,sp,64 - 355a: 2439 jal 3768 <_start-0x7fffc898> - 355c: 9f21007b 0x9f21007b - ... - 3568: 0404 addi s1,sp,512 - 356a: 0000 unimp - 356c: 0410 addi a2,sp,512 - 356e: 0000 unimp - 3570: 0001 nop - 3572: 005e c.slli zero,0x17 - 3574: 0000 unimp - 3576: 0000 unimp - 3578: 0000 unimp - 357a: 2400 fld fs0,8(s0) - 357c: 0005 c.nop 1 - 357e: 3000 fld fs0,32(s0) - 3580: 0005 c.nop 1 - 3582: 0100 addi s0,sp,128 - 3584: 5e00 lw s0,56(a2) - ... - 358e: 003c addi a5,sp,8 - 3590: 0000 unimp - 3592: 0040 addi s0,sp,4 - 3594: 0000 unimp - 3596: 0005 c.nop 1 - 3598: 9361 srli a4,a4,0x38 - 359a: 9304 0x9304 - 359c: 400c lw a1,0(s0) - 359e: 0000 unimp - 35a0: 4400 lw s0,8(s0) - 35a2: 0000 unimp - 35a4: 0800 addi s0,sp,16 - 35a6: 6100 flw fs0,0(a0) - 35a8: 93560493 addi s1,a2,-1739 # fffe8935 <__BSS_END__+0x7ffd1bbd> - 35ac: 9304 0x9304 - 35ae: 4408 lw a0,8(s0) - 35b0: 0000 unimp - 35b2: 4800 lw s0,16(s0) - 35b4: 0000 unimp - 35b6: 0b00 addi s0,sp,400 - 35b8: 6100 flw fs0,0(a0) - 35ba: 93560493 addi s1,a2,-1739 - 35be: 6c04 flw fs1,24(s0) - 35c0: 04930493 addi s1,t1,73 # 18049 <_start-0x7ffe7fb7> - 35c4: 0048 addi a0,sp,4 - 35c6: 0000 unimp - 35c8: 00cc addi a1,sp,68 - 35ca: 0000 unimp - 35cc: 000c 0xc - 35ce: 9361 srli a4,a4,0x38 - 35d0: 5604 lw s1,40(a2) - 35d2: 936c0493 addi s1,s8,-1738 - 35d6: 6004 flw fs1,0(s0) - 35d8: 00000493 li s1,0 - 35dc: 0000 unimp - 35de: 0000 unimp - 35e0: 0000 unimp - 35e2: 0048 addi a0,sp,4 - 35e4: 0000 unimp - 35e6: 004c addi a1,sp,4 - 35e8: 0000 unimp - 35ea: 936e000b 0x936e000b - 35ee: 6f04 flw fs1,24(a4) - 35f0: 93550493 addi s1,a0,-1739 # ffffa935 <__BSS_END__+0x7ffe3bbd> - 35f4: 9304 0x9304 - 35f6: 4c04 lw s1,24(s0) - 35f8: 0000 unimp - 35fa: cc00 sw s0,24(s0) - 35fc: 0000 unimp - 35fe: 0c00 addi s0,sp,528 - 3600: 6e00 flw fs0,24(a2) - 3602: 936f0493 addi s1,t5,-1738 - 3606: 5504 lw s1,40(a0) - 3608: 936d0493 addi s1,s10,-1738 - 360c: 0004 0x4 - 360e: 0000 unimp - 3610: 0000 unimp - 3612: 0000 unimp - 3614: 4800 lw s0,16(s0) - 3616: 0000 unimp - 3618: 6c00 flw fs0,24(s0) - 361a: 0000 unimp - 361c: 0100 addi s0,sp,128 - 361e: 5a00 lw s0,48(a2) - 3620: 0070 addi a2,sp,12 - 3622: 0000 unimp - 3624: 00bc addi a5,sp,72 - 3626: 0000 unimp - 3628: 0001 nop - 362a: c05a sw s6,0(sp) - 362c: 0000 unimp - 362e: c400 sw s0,8(s0) - 3630: 0000 unimp - 3632: 0100 addi s0,sp,128 - 3634: 5a00 lw s0,48(a2) - 3636: 00d4 addi a3,sp,68 - 3638: 0000 unimp - 363a: 0110 addi a2,sp,128 - 363c: 0000 unimp - 363e: 0001 nop - 3640: 145a slli s0,s0,0x36 - 3642: 0001 nop - 3644: 1800 addi s0,sp,48 - 3646: 0001 nop - 3648: 0100 addi s0,sp,128 - 364a: 5a00 lw s0,48(a2) - 364c: 011c addi a5,sp,128 - 364e: 0000 unimp - 3650: 0144 addi s1,sp,132 - 3652: 0000 unimp - 3654: 0001 nop - 3656: 005a c.slli zero,0x16 - 3658: 0000 unimp - 365a: 0000 unimp - 365c: 0000 unimp - 365e: 0400 addi s0,sp,512 - 3660: 0000 unimp - 3662: 0800 addi s0,sp,16 - 3664: 0000 unimp - 3666: 0500 addi s0,sp,640 - 3668: 6f00 flw fs0,24(a4) - 366a: 0c930493 addi s1,t1,201 - 366e: 0008 0x8 - 3670: 0000 unimp - 3672: 000c 0xc - 3674: 0000 unimp - 3676: 0008 0x8 - 3678: 6004936f jal t1,4cc78 <_start-0x7ffb3388> - 367c: 08930493 addi s1,t1,137 - 3680: 000c 0xc - 3682: 0000 unimp - 3684: 0044 addi s1,sp,4 - 3686: 0000 unimp - 3688: 936f000b 0x936f000b - 368c: 6004 flw fs1,0(s0) - 368e: 936c0493 addi s1,s8,-1738 - 3692: 9304 0x9304 - 3694: 4404 lw s1,8(s0) - 3696: 0000 unimp - 3698: 4400 lw s0,8(s0) - 369a: 0001 nop - 369c: 0c00 addi s0,sp,528 - 369e: 6f00 flw fs0,24(a4) - 36a0: 93600493 li s1,-1738 - 36a4: 6c04 flw fs1,24(s0) - 36a6: 935b0493 addi s1,s6,-1739 - 36aa: 0004 0x4 - 36ac: 0000 unimp - 36ae: 0000 unimp - 36b0: 0000 unimp - 36b2: 4800 lw s0,16(s0) - 36b4: 0000 unimp - 36b6: 4c00 lw s0,24(s0) - 36b8: 0000 unimp - 36ba: 0b00 addi s0,sp,400 - 36bc: 5500 lw s0,40(a0) - 36be: 93610493 addi s1,sp,-1738 # fffff936 <__BSS_END__+0x7ffe8bbe> - 36c2: 6d04 flw fs1,24(a0) - 36c4: 04930493 addi s1,t1,73 - 36c8: 004c addi a1,sp,4 - 36ca: 0000 unimp - 36cc: 0144 addi s1,sp,132 - 36ce: 0000 unimp - 36d0: 000c 0xc - 36d2: 9355 srli a4,a4,0x35 - 36d4: 6104 flw fs1,0(a0) - 36d6: 936d0493 addi s1,s10,-1738 - 36da: 5604 lw s1,40(a2) - 36dc: 00000493 li s1,0 - 36e0: 0000 unimp - 36e2: 0000 unimp - 36e4: 0000 unimp - 36e6: 0098 addi a4,sp,64 - 36e8: 0000 unimp - 36ea: 009c addi a5,sp,64 - 36ec: 0000 unimp - 36ee: 0001 nop - 36f0: 385f 0001 4400 0x44000001385f - 36f6: 0001 nop - 36f8: 0200 addi s0,sp,256 - 36fa: 3000 fld fs0,32(s0) - 36fc: 009f 0000 0000 0x9f - 3702: 0000 unimp - 3704: ac00 fsd fs0,24(s0) - 3706: 0000 unimp - 3708: b400 fsd fs0,40(s0) - 370a: 0000 unimp - 370c: 0200 addi s0,sp,256 - 370e: 3000 fld fs0,32(s0) - 3710: c09f 0000 cc00 0xcc000000c09f - 3716: 0000 unimp - 3718: 0200 addi s0,sp,256 - 371a: 3000 fld fs0,32(s0) - 371c: d49f 0000 0c00 0xc000000d49f - 3722: 0001 nop - 3724: 0200 addi s0,sp,256 - 3726: 3000 fld fs0,32(s0) - 3728: 1c9f 0001 2400 0x240000011c9f - 372e: 0001 nop - 3730: 0200 addi s0,sp,256 - 3732: 3100 fld fs0,32(a0) - 3734: 249f 0001 3400 0x34000001249f - 373a: 0001 nop - 373c: 0200 addi s0,sp,256 - 373e: 3000 fld fs0,32(s0) - 3740: 009f 0000 0000 0x9f - 3746: 0000 unimp - 3748: 4800 lw s0,16(s0) - 374a: 0000 unimp - 374c: 6c00 flw fs0,24(s0) - 374e: 0000 unimp - 3750: 0100 addi s0,sp,128 - 3752: 5a00 lw s0,48(a2) - 3754: 0070 addi a2,sp,12 - 3756: 0000 unimp - 3758: 00bc addi a5,sp,72 - 375a: 0000 unimp - 375c: 0001 nop - 375e: c05a sw s6,0(sp) - 3760: 0000 unimp - 3762: c400 sw s0,8(s0) - 3764: 0000 unimp - 3766: 0100 addi s0,sp,128 - 3768: 5a00 lw s0,48(a2) - 376a: 00d4 addi a3,sp,68 - 376c: 0000 unimp - 376e: 0110 addi a2,sp,128 - 3770: 0000 unimp - 3772: 0001 nop - 3774: 145a slli s0,s0,0x36 - 3776: 0001 nop - 3778: 1800 addi s0,sp,48 - 377a: 0001 nop - 377c: 0100 addi s0,sp,128 - 377e: 5a00 lw s0,48(a2) - 3780: 011c addi a5,sp,128 - 3782: 0000 unimp - 3784: 0144 addi s1,sp,132 - 3786: 0000 unimp - 3788: 0001 nop - 378a: 005a c.slli zero,0x16 - 378c: 0000 unimp - 378e: 0000 unimp - 3790: 0000 unimp - 3792: 0400 addi s0,sp,512 - 3794: 0000 unimp - 3796: 0800 addi s0,sp,16 - 3798: 0000 unimp - 379a: 0500 addi s0,sp,640 - 379c: 6f00 flw fs0,24(a4) - 379e: 0c930493 addi s1,t1,201 - 37a2: 0008 0x8 - 37a4: 0000 unimp - 37a6: 000c 0xc - 37a8: 0000 unimp - 37aa: 0008 0x8 - 37ac: 6004936f jal t1,4cdac <_start-0x7ffb3254> - 37b0: 08930493 addi s1,t1,137 - 37b4: 000c 0xc - 37b6: 0000 unimp - 37b8: 0044 addi s1,sp,4 - 37ba: 0000 unimp - 37bc: 936f000b 0x936f000b - 37c0: 6004 flw fs1,0(s0) - 37c2: 936c0493 addi s1,s8,-1738 - 37c6: 9304 0x9304 - 37c8: 4404 lw s1,8(s0) - 37ca: 0000 unimp - 37cc: 4400 lw s0,8(s0) - 37ce: 0001 nop - 37d0: 0c00 addi s0,sp,528 - 37d2: 6f00 flw fs0,24(a4) - 37d4: 93600493 li s1,-1738 - 37d8: 6c04 flw fs1,24(s0) - 37da: 935b0493 addi s1,s6,-1739 - 37de: 0004 0x4 - 37e0: 0000 unimp - 37e2: 0000 unimp - 37e4: 0000 unimp - 37e6: 4800 lw s0,16(s0) - 37e8: 0000 unimp - 37ea: 4c00 lw s0,24(s0) - 37ec: 0000 unimp - 37ee: 0b00 addi s0,sp,400 - 37f0: 5500 lw s0,40(a0) - 37f2: 93610493 addi s1,sp,-1738 - 37f6: 6d04 flw fs1,24(a0) - 37f8: 04930493 addi s1,t1,73 - 37fc: 004c addi a1,sp,4 - 37fe: 0000 unimp - 3800: 0144 addi s1,sp,132 - 3802: 0000 unimp - 3804: 000c 0xc - 3806: 9355 srli a4,a4,0x35 - 3808: 6104 flw fs1,0(a0) - 380a: 936d0493 addi s1,s10,-1738 - 380e: 5604 lw s1,40(a2) - 3810: 00000493 li s1,0 - 3814: 0000 unimp - 3816: 0000 unimp - 3818: 0000 unimp - 381a: 0098 addi a4,sp,64 - 381c: 0000 unimp - 381e: 009c addi a5,sp,64 - 3820: 0000 unimp - 3822: 0001 nop - 3824: 385f 0001 4400 0x44000001385f - 382a: 0001 nop - 382c: 0200 addi s0,sp,256 - 382e: 3000 fld fs0,32(s0) - 3830: 009f 0000 0000 0x9f - 3836: 0000 unimp - 3838: ac00 fsd fs0,24(s0) - 383a: 0000 unimp - 383c: b400 fsd fs0,40(s0) - 383e: 0000 unimp - 3840: 0200 addi s0,sp,256 - 3842: 3000 fld fs0,32(s0) - 3844: c09f 0000 cc00 0xcc000000c09f - 384a: 0000 unimp - 384c: 0200 addi s0,sp,256 - 384e: 3000 fld fs0,32(s0) - 3850: d49f 0000 0c00 0xc000000d49f - 3856: 0001 nop - 3858: 0200 addi s0,sp,256 - 385a: 3000 fld fs0,32(s0) - 385c: 1c9f 0001 2400 0x240000011c9f - 3862: 0001 nop - 3864: 0200 addi s0,sp,256 - 3866: 3100 fld fs0,32(a0) - 3868: 249f 0001 3400 0x34000001249f - 386e: 0001 nop - 3870: 0200 addi s0,sp,256 - 3872: 3000 fld fs0,32(s0) - 3874: 009f 0000 0000 0x9f - 387a: 0000 unimp - 387c: 0000 unimp - 387e: 0000 unimp - 3880: f000 fsw fs0,32(s0) - 3882: 0000 unimp - 3884: 0200 addi s0,sp,256 - 3886: 3000 fld fs0,32(s0) - 3888: c89f 0001 1000 0x10000001c89f - 388e: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - 3892: 3000 fld fs0,32(s0) - 3894: 009f 0000 0000 0x9f - 389a: 0000 unimp - 389c: ec00 fsw fs0,24(s0) - 389e: 0000 unimp - 38a0: f000 fsw fs0,32(s0) - 38a2: 0000 unimp - 38a4: 0200 addi s0,sp,256 - 38a6: 3000 fld fs0,32(s0) - 38a8: f09f 0000 c800 0xc8000000f09f - 38ae: 0001 nop - 38b0: 0100 addi s0,sp,128 - 38b2: 6700 flw fs0,8(a4) - 38b4: 0310 addi a2,sp,384 - 38b6: 0000 unimp - 38b8: 05bc addi a5,sp,712 - 38ba: 0000 unimp - 38bc: 0001 nop - 38be: 000d2c67 0xd2c67 - 38c2: 5000 lw s0,32(s0) - 38c4: 000d c.nop 3 - 38c6: 0100 addi s0,sp,128 - 38c8: 6700 flw fs0,8(a4) - 38ca: 0d7c addi a5,sp,668 - 38cc: 0000 unimp - 38ce: 0d88 addi a0,sp,720 - 38d0: 0000 unimp - 38d2: 0001 nop - 38d4: 00000067 jr zero # 0 <_start-0x80000000> - 38d8: 0000 unimp - 38da: 0000 unimp - 38dc: 9800 0x9800 - 38de: 0000 unimp - 38e0: 4000 lw s0,0(s0) - 38e2: 0005 c.nop 1 - 38e4: 0600 addi s0,sp,768 - 38e6: 8300 0x8300 - 38e8: 0800 addi s0,sp,16 - 38ea: 1aff 0x1aff - 38ec: 2c9f 000d a800 0xa800000d2c9f - 38f2: 000d c.nop 3 - 38f4: 0600 addi s0,sp,768 - 38f6: 8300 0x8300 - 38f8: 0800 addi s0,sp,16 - 38fa: 1aff 0x1aff - 38fc: cc9f 000f 0800 0x800000fcc9f - 3902: 0010 0x10 - 3904: 0600 addi s0,sp,768 - 3906: 8300 0x8300 - 3908: 0800 addi s0,sp,16 - 390a: 1aff 0x1aff - 390c: 009f 0000 0000 0x9f - 3912: 0000 unimp - 3914: 9400 0x9400 - 3916: 0000 unimp - 3918: ec00 fsw fs0,24(s0) - 391a: 0000 unimp - 391c: 0700 addi s0,sp,896 - 391e: 7900 flw fs0,48(a0) - 3920: 0a00 addi s0,sp,272 - 3922: ffff 0xffff - 3924: 9f1a add t5,t5,t1 - 3926: 00ec addi a1,sp,76 - 3928: 0000 unimp - 392a: 01c8 addi a0,sp,196 - 392c: 0000 unimp - 392e: 0001 nop - 3930: c859 beqz s0,39c6 <_start-0x7fffc63a> - 3932: 0001 nop - 3934: dc00 sw s0,56(s0) - 3936: 0002 c.slli64 zero - 3938: 0700 addi s0,sp,896 - 393a: 7900 flw fs0,48(a0) - 393c: 0a00 addi s0,sp,272 - 393e: ffff 0xffff - 3940: 9f1a add t5,t5,t1 - 3942: 02dc addi a5,sp,324 - 3944: 0000 unimp - 3946: 02e8 addi a0,sp,332 - 3948: 0000 unimp - 394a: ac91000b 0xac91000b - 394e: 067f 0x67f - 3950: 2540 fld fs0,136(a0) - 3952: ff0a fsw ft2,188(sp) - 3954: 1a7f 0x1a7f - 3956: e89f 0002 0800 0x8000002e89f - 395c: 07000003 lb zero,112(zero) # 70 <_start-0x7fffff90> - 3960: 7900 flw fs0,48(a0) - 3962: 0a00 addi s0,sp,272 - 3964: ffff 0xffff - 3966: 9f1a add t5,t5,t1 - 3968: 0308 addi a0,sp,384 - 396a: 0000 unimp - 396c: 0310 addi a2,sp,384 - 396e: 0000 unimp - 3970: ac91000b 0xac91000b - 3974: 067f 0x67f - 3976: 2540 fld fs0,136(a0) - 3978: ff0a fsw ft2,188(sp) - 397a: 1a7f 0x1a7f - 397c: 109f 0003 b800 0xb8000003109f - 3982: 0004 0x4 - 3984: 0100 addi s0,sp,128 - 3986: 5900 lw s0,48(a0) - 3988: 0d2c addi a1,sp,664 - 398a: 0000 unimp - 398c: 0da8 addi a0,sp,728 - 398e: 0000 unimp - 3990: 0001 nop - 3992: cc59 beqz s0,3a30 <_start-0x7fffc5d0> - 3994: 0800000f fence i,unknown - 3998: 0010 0x10 - 399a: 0100 addi s0,sp,128 - 399c: 5900 lw s0,48(a0) - ... - 39a6: 0180 addi s0,sp,192 - 39a8: 0000 unimp - 39aa: 0184 addi s1,sp,192 - 39ac: 0000 unimp - 39ae: 0002 c.slli64 zero - 39b0: 9f30 0x9f30 - 39b2: 0184 addi s1,sp,192 - 39b4: 0000 unimp - 39b6: 01c8 addi a0,sp,196 - 39b8: 0000 unimp - 39ba: 0001 nop - 39bc: 585e lw a6,244(sp) - 39be: 0004 0x4 - 39c0: 5c00 lw s0,56(s0) - 39c2: 0004 0x4 - 39c4: 0100 addi s0,sp,128 - 39c6: 5e00 lw s0,56(a2) - 39c8: 0d2c addi a1,sp,664 - 39ca: 0000 unimp - 39cc: 0da8 addi a0,sp,728 - 39ce: 0000 unimp - 39d0: 0001 nop - 39d2: cc5e sw s7,24(sp) - 39d4: 0800000f fence i,unknown - 39d8: 0010 0x10 - 39da: 0100 addi s0,sp,128 - 39dc: 5e00 lw s0,56(a2) - ... - 39e6: 012c addi a1,sp,136 - 39e8: 0000 unimp - 39ea: 01c8 addi a0,sp,196 - 39ec: 0000 unimp - 39ee: 0006 c.slli zero,0x1 - 39f0: 0082 c.slli64 ra - 39f2: ff08 fsw fa0,56(a4) - 39f4: 9f1a add t5,t5,t1 - 39f6: 0310 addi a2,sp,384 - 39f8: 0000 unimp - 39fa: 050c addi a1,sp,640 - 39fc: 0000 unimp - 39fe: 0006 c.slli zero,0x1 - 3a00: 0082 c.slli64 ra - 3a02: ff08 fsw fa0,56(a4) - 3a04: 9f1a add t5,t5,t1 - 3a06: 050c addi a1,sp,640 - 3a08: 0000 unimp - 3a0a: 08c0 addi s0,sp,84 - 3a0c: 0000 unimp - 3a0e: ac910007 vlxseg6bu.v v0,(sp),v9,v0.t - 3a12: 067f 0x67f - 3a14: 2c9f254f 0x2c9f254f - 3a18: 000d c.nop 3 - 3a1a: a800 fsd fs0,16(s0) - 3a1c: 000d c.nop 3 - 3a1e: 0600 addi s0,sp,768 - 3a20: 8200 0x8200 - 3a22: 0800 addi s0,sp,16 - 3a24: 1aff 0x1aff - 3a26: cc9f 000f 0800 0x800000fcc9f - 3a2c: 0010 0x10 - 3a2e: 0600 addi s0,sp,768 - 3a30: 8200 0x8200 - 3a32: 0800 addi s0,sp,16 - 3a34: 1aff 0x1aff - 3a36: 009f 0000 0000 0x9f - 3a3c: 0000 unimp - 3a3e: 2800 fld fs0,16(s0) - 3a40: 0001 nop - 3a42: 8000 0x8000 - 3a44: 0001 nop - 3a46: 0700 addi s0,sp,896 - 3a48: 7f00 flw fs0,56(a4) - 3a4a: 0a00 addi s0,sp,272 - 3a4c: ffff 0xffff - 3a4e: 9f1a add t5,t5,t1 - 3a50: 0180 addi s0,sp,192 - 3a52: 0000 unimp - 3a54: 0188 addi a0,sp,192 - 3a56: 0000 unimp - 3a58: 0001 nop - 3a5a: 105f 0003 1400 0x14000003105f - 3a60: 07000003 lb zero,112(zero) # 70 <_start-0x7fffff90> - 3a64: 7f00 flw fs0,56(a4) - 3a66: 0a00 addi s0,sp,272 - 3a68: ffff 0xffff - 3a6a: 9f1a add t5,t5,t1 - 3a6c: 0314 addi a3,sp,384 - 3a6e: 0000 unimp - 3a70: 00000327 vsb.v v6,(zero),v0.t - 3a74: 000a c.slli zero,0x2 - 3a76: ac91 j 3cca <_start-0x7fffc336> - 3a78: 067f 0x67f - 3a7a: 2540 fld fs0,136(a0) - 3a7c: 007e c.slli zero,0x1f - 3a7e: 9f1a add t5,t5,t1 - 3a80: 00000327 vsb.v v6,(zero),v0.t - 3a84: 037c addi a5,sp,396 - 3a86: 0000 unimp - 3a88: ac91000b 0xac91000b - 3a8c: 067f 0x67f - 3a8e: 2540 fld fs0,136(a0) - 3a90: ff0a fsw ft2,188(sp) - 3a92: 1a7f 0x1a7f - 3a94: 7c9f 0003 8700 0x870000037c9f - 3a9a: 0a000003 lb zero,160(zero) # a0 <_start-0x7fffff60> - 3a9e: 9100 0x9100 - 3aa0: 7fac flw fa1,120(a5) - 3aa2: 4006 0x4006 - 3aa4: 7e25 lui t3,0xfffe9 - 3aa6: 1a00 addi s0,sp,304 - 3aa8: 879f 0003 9000 0x90000003879f - 3aae: 0b000003 lb zero,176(zero) # b0 <_start-0x7fffff50> - 3ab2: 9100 0x9100 - 3ab4: 7fac flw fa1,120(a5) - 3ab6: 4006 0x4006 - 3ab8: 0a25 addi s4,s4,9 - 3aba: 7fff 0x7fff - 3abc: 9f1a add t5,t5,t1 - 3abe: 0390 addi a2,sp,448 - 3ac0: 0000 unimp - 3ac2: 0000039b 0x39b - 3ac6: 000a c.slli zero,0x2 - 3ac8: ac91 j 3d1c <_start-0x7fffc2e4> - 3aca: 067f 0x67f - 3acc: 2540 fld fs0,136(a0) - 3ace: 007e c.slli zero,0x1f - 3ad0: 9f1a add t5,t5,t1 - 3ad2: 0000039b 0x39b - 3ad6: 03a4 addi s1,sp,456 - 3ad8: 0000 unimp - 3ada: ac91000b 0xac91000b - 3ade: 067f 0x67f - 3ae0: 2540 fld fs0,136(a0) - 3ae2: ff0a fsw ft2,188(sp) - 3ae4: 1a7f 0x1a7f - 3ae6: a49f 0003 ab00 0xab000003a49f - 3aec: 0a000003 lb zero,160(zero) # a0 <_start-0x7fffff60> - 3af0: 9100 0x9100 - 3af2: 7fac flw fa1,120(a5) - 3af4: 4006 0x4006 - 3af6: 7e25 lui t3,0xfffe9 - 3af8: 1a00 addi s0,sp,304 - 3afa: ab9f 0003 3000 0x30000003ab9f - 3b00: 0004 0x4 - 3b02: 0b00 addi s0,sp,400 - 3b04: 9100 0x9100 - 3b06: 7fac flw fa1,120(a5) - 3b08: 4006 0x4006 - 3b0a: 0a25 addi s4,s4,9 - 3b0c: 7fff 0x7fff - 3b0e: 9f1a add t5,t5,t1 - 3b10: 0430 addi a2,sp,520 - 3b12: 0000 unimp - 3b14: 044c addi a1,sp,516 - 3b16: 0000 unimp - 3b18: 007f0007 0x7f0007 - 3b1c: ff0a fsw ft2,188(sp) - 3b1e: 1aff 0x1aff - 3b20: 4c9f 0004 5400 0x540000044c9f - 3b26: 0004 0x4 - 3b28: 0a00 addi s0,sp,272 - 3b2a: 9100 0x9100 - 3b2c: 7fac flw fa1,120(a5) - 3b2e: 4006 0x4006 - 3b30: 7e25 lui t3,0xfffe9 - 3b32: 1a00 addi s0,sp,304 - 3b34: 549f 0004 5800 0x58000004549f - 3b3a: 0004 0x4 - 3b3c: 0b00 addi s0,sp,400 - 3b3e: 9100 0x9100 - 3b40: 7fac flw fa1,120(a5) - 3b42: 4006 0x4006 - 3b44: 0a25 addi s4,s4,9 - 3b46: 7fff 0x7fff - 3b48: 9f1a add t5,t5,t1 - ... - 3b52: 0458 addi a4,sp,516 - 3b54: 0000 unimp - 3b56: 0bc4 addi s1,sp,468 - 3b58: 0000 unimp - 3b5a: 0002 c.slli64 zero - 3b5c: 9f30 0x9f30 - 3b5e: 0d50 addi a2,sp,660 - 3b60: 0000 unimp - 3b62: 0d7c addi a5,sp,668 - 3b64: 0000 unimp - 3b66: 0001 nop - 3b68: 000da467 0xda467 - 3b6c: a800 fsd fs0,16(s0) - 3b6e: 000d c.nop 3 - 3b70: 0100 addi s0,sp,128 - 3b72: 6700 flw fs0,8(a4) - 3b74: 0da8 addi a0,sp,728 - 3b76: 0000 unimp - 3b78: 0db4 addi a3,sp,728 - 3b7a: 0000 unimp - 3b7c: 0002 c.slli64 zero - 3b7e: 9f30 0x9f30 - 3b80: 0db4 addi a3,sp,728 - 3b82: 0000 unimp - 3b84: 0dcc addi a1,sp,724 - 3b86: 0000 unimp - 3b88: 0002 c.slli64 zero - 3b8a: 9f32 add t5,t5,a2 - 3b8c: 0fcc addi a1,sp,980 - 3b8e: 0000 unimp - 3b90: 0fe8 addi a0,sp,988 - 3b92: 0000 unimp - 3b94: 0001 nop - 3b96: 00000067 jr zero # 0 <_start-0x80000000> - 3b9a: 0000 unimp - 3b9c: 0000 unimp - 3b9e: a400 fsd fs0,8(s0) - 3ba0: 0001 nop - 3ba2: ac00 fsd fs0,24(s0) - 3ba4: 0001 nop - 3ba6: 0100 addi s0,sp,128 - 3ba8: 5d00 lw s0,56(a0) - 3baa: 01ac addi a1,sp,200 - 3bac: 0000 unimp - 3bae: 01c8 addi a0,sp,196 - 3bb0: 0000 unimp - 3bb2: d0910003 lb zero,-759(sp) - 3bb6: 587e lw a6,252(sp) - 3bb8: 0004 0x4 - 3bba: 2800 fld fs0,16(s0) - 3bbc: 000d c.nop 3 - 3bbe: 0300 addi s0,sp,384 - 3bc0: 9100 0x9100 - 3bc2: 7ed0 flw fa2,60(a3) - 3bc4: 0d28 addi a0,sp,664 - 3bc6: 0000 unimp - 3bc8: 0d2c addi a1,sp,664 - 3bca: 0000 unimp - 3bcc: d0720003 lb zero,-761(tp) # 19d07 <_start-0x7ffe62f9> - 3bd0: 2c7e fld fs8,472(sp) - 3bd2: 000d c.nop 3 - 3bd4: e800 fsw fs0,16(s0) - 3bd6: 0300000f fence rw,unknown - 3bda: 9100 0x9100 - 3bdc: 7ed0 flw fa2,60(a3) - 3bde: 0ffc addi a5,sp,988 - 3be0: 0000 unimp - 3be2: 1008 addi a0,sp,32 - 3be4: 0000 unimp - 3be6: 0002 c.slli64 zero - 3be8: 9f30 0x9f30 - ... - 3bf2: 01a4 addi s1,sp,200 - 3bf4: 0000 unimp - 3bf6: 01c8 addi a0,sp,196 - 3bf8: 0000 unimp - 3bfa: dc910003 lb zero,-567(sp) - 3bfe: 587e lw a6,252(sp) - 3c00: 0004 0x4 - 3c02: d400 sw s0,40(s0) - 3c04: 0300000b 0x300000b - 3c08: 9100 0x9100 - 3c0a: 7edc flw fa5,60(a3) - 3c0c: 0bd4 addi a3,sp,468 - 3c0e: 0000 unimp - 3c10: 0c38 addi a4,sp,536 - 3c12: 0000 unimp - 3c14: 0001 nop - 3c16: 385f 000c 4c00 0x4c00000c385f - 3c1c: 000c 0xc - 3c1e: 0800 addi s0,sp,16 - 3c20: 9100 0x9100 - 3c22: 7edc flw fa5,60(a3) - 3c24: 2306 fld ft6,64(sp) - 3c26: 7fff 0x7fff - 3c28: 4c9f 000c 5000 0x5000000c4c9f - 3c2e: 000c 0xc - 3c30: 0a00 addi s0,sp,272 - 3c32: 7f00 flw fs0,56(a4) - 3c34: 9100 0x9100 - 3c36: 7edc flw fa5,60(a3) - 3c38: 2206 fld ft4,64(sp) - 3c3a: 1c31 addi s8,s8,-20 - 3c3c: 509f 000c 9800 0x9800000c509f - 3c42: 000c 0xc - 3c44: 0100 addi s0,sp,128 - 3c46: 5f00 lw s0,56(a4) - 3c48: 0d2c addi a1,sp,664 - 3c4a: 0000 unimp - 3c4c: 0d68 addi a0,sp,668 - 3c4e: 0000 unimp - 3c50: dc910003 lb zero,-567(sp) - 3c54: 687e flw fa6,220(sp) - 3c56: 000d c.nop 3 - 3c58: 7c00 flw fs0,56(s0) - 3c5a: 000d c.nop 3 - 3c5c: 0200 addi s0,sp,256 - 3c5e: 3000 fld fs0,32(s0) - 3c60: 7c9f 000d b000 0xb000000d7c9f - 3c66: 000d c.nop 3 - 3c68: 0300 addi s0,sp,384 - 3c6a: 9100 0x9100 - 3c6c: 7edc flw fa5,60(a3) - 3c6e: 0db0 addi a2,sp,728 - 3c70: 0000 unimp - 3c72: 0db4 addi a3,sp,728 - 3c74: 0000 unimp - 3c76: e0910007 0xe0910007 - 3c7a: 067e slli a2,a2,0x1f - 3c7c: b49f0123 sb s1,-1214(t5) - 3c80: 000d c.nop 3 - 3c82: cc00 sw s0,24(s0) - 3c84: 000d c.nop 3 - 3c86: 0400 addi s0,sp,512 - 3c88: 0a00 addi s0,sp,272 - 3c8a: 7fff 0x7fff - 3c8c: cc9f 000d e800 0xe800000dcc9f - 3c92: 000d c.nop 3 - 3c94: 0100 addi s0,sp,128 - 3c96: 5f00 lw s0,56(a4) - 3c98: 0de8 addi a0,sp,732 - 3c9a: 0000 unimp - 3c9c: 0f40 addi s0,sp,916 - 3c9e: 0000 unimp - 3ca0: 0009 c.nop 2 - 3ca2: 91c0020b 0x91c0020b - 3ca6: 7edc flw fa5,60(a3) - 3ca8: 1c06 slli s8,s8,0x21 - 3caa: 409f 000f 5800 0x5800000f409f - 3cb0: 0200000f fence r,unknown - 3cb4: 3100 fld fs0,32(a0) - 3cb6: 589f 000f 8c00 0x8c00000f589f - 3cbc: 0900000f fence iw,unknown - 3cc0: 0b00 addi s0,sp,400 - 3cc2: c002 sw zero,0(sp) - 3cc4: dc91 beqz s1,3be0 <_start-0x7fffc420> - 3cc6: 067e slli a2,a2,0x1f - 3cc8: 9f1c 0x9f1c - 3cca: 0f94 addi a3,sp,976 - 3ccc: 0000 unimp - 3cce: 0fcc addi a1,sp,980 - 3cd0: 0000 unimp - 3cd2: 0002 c.slli64 zero - 3cd4: 9f30 0x9f30 - 3cd6: 0fcc addi a1,sp,980 - 3cd8: 0000 unimp - 3cda: 1008 addi a0,sp,32 - 3cdc: 0000 unimp - 3cde: 0004 0x4 - 3ce0: ff0a fsw ft2,188(sp) - 3ce2: 9f7f 0x9f7f - ... - 3cec: 0cd0 addi a2,sp,596 - 3cee: 0000 unimp - 3cf0: 0d28 addi a0,sp,664 - 3cf2: 0000 unimp - 3cf4: 0012 c.slli zero,0x4 - 3cf6: 9091 srli s1,s1,0x24 - 3cf8: 937f 0x937f - 3cfa: 9104 0x9104 - 3cfc: 7f94 flw fa3,56(a5) - 3cfe: 98910493 addi s1,sp,-1655 - 3d02: 937f 0x937f - 3d04: 5f04 lw s1,56(a4) - 3d06: 0d280493 addi s1,a6,210 # fffeb0d2 <__BSS_END__+0x7ffd435a> - 3d0a: 0000 unimp - 3d0c: 0d2c addi a1,sp,664 - 3d0e: 0000 unimp - 3d10: 0010 0x10 - 3d12: 9072 c.add zero,t3 - 3d14: 937f 0x937f - 3d16: 7204 flw fs1,32(a2) - 3d18: 7f94 flw fa3,56(a5) - 3d1a: 935e0493 addi s1,t3,-1739 # fffe8935 <__BSS_END__+0x7ffd1bbd> - 3d1e: 5f04 lw s1,56(a4) - 3d20: 00000493 li s1,0 - 3d24: 0000 unimp - 3d26: 0000 unimp - 3d28: 0000 unimp - 3d2a: 00ac addi a1,sp,72 - 3d2c: 0000 unimp - 3d2e: 00ec addi a1,sp,76 - 3d30: 0000 unimp - 3d32: 0002 c.slli64 zero - 3d34: 00009f33 sll t5,ra,zero - 3d38: 0000 unimp - 3d3a: 0000 unimp - 3d3c: 0000 unimp - 3d3e: 00ac addi a1,sp,72 - 3d40: 0000 unimp - 3d42: 00ec addi a1,sp,76 - 3d44: 0000 unimp - 3d46: 0002 c.slli64 zero - 3d48: 9f4d 0x9f4d - ... - 3d52: 00ac addi a1,sp,72 - 3d54: 0000 unimp - 3d56: 00ec addi a1,sp,76 - 3d58: 0000 unimp - 3d5a: 0002 c.slli64 zero - 3d5c: 9f30 0x9f30 - ... - 3d66: 00ac addi a1,sp,72 - 3d68: 0000 unimp - 3d6a: 00b4 addi a3,sp,72 - 3d6c: 0000 unimp - 3d6e: 0002 c.slli64 zero - 3d70: 00d49f33 sll t5,s1,a3 - 3d74: 0000 unimp - 3d76: 00ec addi a1,sp,76 - 3d78: 0000 unimp - 3d7a: ff090003 lb zero,-16(s2) # eff0 <_start-0x7fff1010> - 3d7e: 009f 0000 0000 0x9f - 3d84: 0000 unimp - 3d86: e400 fsw fs0,8(s0) - 3d88: 0001 nop - 3d8a: 3800 fld fs0,48(s0) - 3d8c: 0002 c.slli64 zero - 3d8e: 0300 addi s0,sp,384 - 3d90: 7a00 flw fs0,48(a2) - 3d92: 9f71 0x9f71 - 3d94: 0240 addi s0,sp,260 - 3d96: 0000 unimp - 3d98: 0248 addi a0,sp,260 - 3d9a: 0000 unimp - 3d9c: 0001 nop - 3d9e: 545a lw s0,180(sp) - 3da0: 0002 c.slli64 zero - 3da2: 5c00 lw s0,56(s0) - 3da4: 0002 c.slli64 zero - 3da6: 0100 addi s0,sp,128 - 3da8: 5a00 lw s0,48(a2) - 3daa: 0264 addi s1,sp,268 - 3dac: 0000 unimp - 3dae: 026c addi a1,sp,268 - 3db0: 0000 unimp - 3db2: 0001 nop - 3db4: 6c5a flw fs8,148(sp) - 3db6: 0002 c.slli64 zero - 3db8: e800 fsw fs0,16(s0) - 3dba: 0002 c.slli64 zero - 3dbc: 0300 addi s0,sp,384 - 3dbe: 7a00 flw fs0,48(a2) - 3dc0: 9f71 0x9f71 - ... - 3dca: 01f0 addi a2,sp,204 - 3dcc: 0000 unimp - 3dce: 022c addi a1,sp,264 - 3dd0: 0000 unimp - 3dd2: 0001 nop - 3dd4: 2c5d jal 408a <_start-0x7fffbf76> - 3dd6: 0002 c.slli64 zero - 3dd8: 3800 fld fs0,48(s0) - 3dda: 0002 c.slli64 zero - 3ddc: 0500 addi s0,sp,640 - 3dde: 7a00 flw fs0,48(a2) - 3de0: 4f74 lw a3,92(a4) - 3de2: 9f1a add t5,t5,t1 - 3de4: 026c addi a1,sp,268 - 3de6: 0000 unimp - 3de8: 027c addi a5,sp,268 - 3dea: 0000 unimp - 3dec: 0001 nop - 3dee: 7c5d lui s8,0xffff7 - 3df0: 0002 c.slli64 zero - 3df2: 9c00 0x9c00 - 3df4: 0002 c.slli64 zero - 3df6: 0500 addi s0,sp,640 - 3df8: 7a00 flw fs0,48(a2) - 3dfa: 4f74 lw a3,92(a4) - 3dfc: 9f1a add t5,t5,t1 - 3dfe: 029c addi a5,sp,320 - 3e00: 0000 unimp - 3e02: 02c0 addi s0,sp,324 - 3e04: 0000 unimp - 3e06: 0001 nop - 3e08: c05d beqz s0,3eae <_start-0x7fffc152> - 3e0a: 0002 c.slli64 zero - 3e0c: e800 fsw fs0,16(s0) - 3e0e: 0002 c.slli64 zero - 3e10: 0500 addi s0,sp,640 - 3e12: 7a00 flw fs0,48(a2) - 3e14: 4f74 lw a3,92(a4) - 3e16: 9f1a add t5,t5,t1 - ... - 3e20: 01f0 addi a2,sp,204 - 3e22: 0000 unimp - 3e24: 020c addi a1,sp,256 - 3e26: 0000 unimp - 3e28: 0006 c.slli zero,0x1 - 3e2a: 2008 fld fa0,0(s0) - 3e2c: 007d c.nop 31 - 3e2e: 9f1c 0x9f1c - 3e30: 020c addi a1,sp,256 - 3e32: 0000 unimp - 3e34: 0230 addi a2,sp,264 - 3e36: 0000 unimp - 3e38: 0001 nop - 3e3a: 3060 fld fs0,224(s0) - 3e3c: 0002 c.slli64 zero - 3e3e: 3800 fld fs0,48(s0) - 3e40: 0002 c.slli64 zero - 3e42: 0800 addi s0,sp,16 - 3e44: 0800 addi s0,sp,16 - 3e46: 7a20 flw fs0,112(a2) - 3e48: 4f74 lw a3,92(a4) - 3e4a: 1c1a slli s8,s8,0x26 - 3e4c: 6c9f 0002 7c00 0x7c0000026c9f - 3e52: 0002 c.slli64 zero - 3e54: 0600 addi s0,sp,768 - 3e56: 0800 addi s0,sp,16 - 3e58: 7d20 flw fs0,120(a0) - 3e5a: 1c00 addi s0,sp,560 - 3e5c: 7c9f 0002 9c00 0x9c0000027c9f - 3e62: 0002 c.slli64 zero - 3e64: 0800 addi s0,sp,16 - 3e66: 0800 addi s0,sp,16 - 3e68: 7a20 flw fs0,112(a2) - 3e6a: 4f74 lw a3,92(a4) - 3e6c: 1c1a slli s8,s8,0x26 - 3e6e: 9c9f 0002 c000 0xc00000029c9f - 3e74: 0002 c.slli64 zero - 3e76: 0100 addi s0,sp,128 - 3e78: 6000 flw fs0,0(s0) - 3e7a: 02c0 addi s0,sp,324 - 3e7c: 0000 unimp - 3e7e: 02e8 addi a0,sp,332 - 3e80: 0000 unimp - 3e82: 0008 0x8 - 3e84: 2008 fld fa0,0(s0) - 3e86: 747a flw fs0,188(sp) - 3e88: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - ... - 3e94: 01ec addi a1,sp,204 - 3e96: 0000 unimp - 3e98: 0228 addi a0,sp,264 - 3e9a: 0000 unimp - 3e9c: 0001 nop - 3e9e: 285f 0002 3000 0x30000002285f - 3ea4: 0002 c.slli64 zero - 3ea6: 0300 addi s0,sp,384 - 3ea8: 7f00 flw fs0,56(a4) - 3eaa: 9f01 0x9f01 - 3eac: 0230 addi a2,sp,264 - 3eae: 0000 unimp - 3eb0: 0238 addi a4,sp,264 - 3eb2: 0000 unimp - 3eb4: 0005 c.nop 1 - 3eb6: 747a flw fs0,188(sp) - 3eb8: 2635 jal 41e4 <_start-0x7fffbe1c> - 3eba: 6c9f 0002 9800 0x980000026c9f - 3ec0: 0002 c.slli64 zero - 3ec2: 0100 addi s0,sp,128 - 3ec4: 5f00 lw s0,56(a4) - 3ec6: 0298 addi a4,sp,320 - 3ec8: 0000 unimp - 3eca: 029c addi a5,sp,320 - 3ecc: 0000 unimp - 3ece: 017f0003 lb zero,23(t5) - 3ed2: 9c9f 0002 c000 0xc00000029c9f - 3ed8: 0002 c.slli64 zero - 3eda: 0100 addi s0,sp,128 - 3edc: 5f00 lw s0,56(a4) - 3ede: 02c0 addi s0,sp,324 - 3ee0: 0000 unimp - 3ee2: 02e8 addi a0,sp,332 - 3ee4: 0000 unimp - 3ee6: 0005 c.nop 1 - 3ee8: 747a flw fs0,188(sp) - 3eea: 2635 jal 4216 <_start-0x7fffbdea> - 3eec: 009f 0000 0000 0x9f - 3ef2: 0000 unimp - 3ef4: 2800 fld fs0,16(s0) - 3ef6: 0002 c.slli64 zero - 3ef8: 3000 fld fs0,32(s0) - 3efa: 0002 c.slli64 zero - 3efc: 0100 addi s0,sp,128 - 3efe: 5f00 lw s0,56(a4) - 3f00: 027c addi a5,sp,268 - 3f02: 0000 unimp - 3f04: 029c addi a5,sp,320 - 3f06: 0000 unimp - 3f08: 0001 nop - 3f0a: c05d beqz s0,3fb0 <_start-0x7fffc050> - 3f0c: 0002 c.slli64 zero - 3f0e: e800 fsw fs0,16(s0) - 3f10: 0002 c.slli64 zero - 3f12: 0100 addi s0,sp,128 - 3f14: 5f00 lw s0,56(a4) - ... - 3f1e: 0140 addi s0,sp,132 - 3f20: 0000 unimp - 3f22: 0180 addi s0,sp,192 - 3f24: 0000 unimp - 3f26: 0002 c.slli64 zero - 3f28: 00009f33 sll t5,ra,zero - 3f2c: 0000 unimp - 3f2e: 0000 unimp - 3f30: 0000 unimp - 3f32: 0140 addi s0,sp,132 - 3f34: 0000 unimp - 3f36: 0180 addi s0,sp,192 - 3f38: 0000 unimp - 3f3a: 0002 c.slli64 zero - 3f3c: 9f4d 0x9f4d - ... - 3f46: 0140 addi s0,sp,132 - 3f48: 0000 unimp - 3f4a: 0180 addi s0,sp,192 - 3f4c: 0000 unimp - 3f4e: 0002 c.slli64 zero - 3f50: 9f30 0x9f30 - ... - 3f5a: 0140 addi s0,sp,132 - 3f5c: 0000 unimp - 3f5e: 0148 addi a0,sp,132 - 3f60: 0000 unimp - 3f62: 0002 c.slli64 zero - 3f64: 01689f33 sll t5,a7,s6 - 3f68: 0000 unimp - 3f6a: 0180 addi s0,sp,192 - 3f6c: 0000 unimp - 3f6e: ff090003 lb zero,-16(s2) - 3f72: 009f 0000 0000 0x9f - 3f78: 0000 unimp - 3f7a: 2800 fld fs0,16(s0) - 3f7c: 7c000003 lb zero,1984(zero) # 7c0 <_start-0x7ffff840> - 3f80: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 3f84: 7a00 flw fs0,48(a2) - 3f86: 9f71 0x9f71 - 3f88: 0388 addi a0,sp,448 - 3f8a: 0000 unimp - 3f8c: 0390 addi a2,sp,448 - 3f8e: 0000 unimp - 3f90: 0001 nop - 3f92: 9c5a add s8,s8,s6 - 3f94: a4000003 lb zero,-1472(zero) # fffffa40 <__BSS_END__+0x7ffe8cc8> - 3f98: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 3f9c: 5a00 lw s0,48(a2) - 3f9e: 03ac addi a1,sp,456 - 3fa0: 0000 unimp - 3fa2: 03b4 addi a3,sp,456 - 3fa4: 0000 unimp - 3fa6: 0001 nop - 3fa8: b45a fsd fs6,40(sp) - 3faa: 30000003 lb zero,768(zero) # 300 <_start-0x7ffffd00> - 3fae: 0004 0x4 - 3fb0: 0300 addi s0,sp,384 - 3fb2: 7a00 flw fs0,48(a2) - 3fb4: 9f71 0x9f71 - ... - 3fbe: 0334 addi a3,sp,392 - 3fc0: 0000 unimp - 3fc2: 0370 addi a2,sp,396 - 3fc4: 0000 unimp - 3fc6: 0001 nop - 3fc8: 705c flw fa5,36(s0) - 3fca: 7c000003 lb zero,1984(zero) # 7c0 <_start-0x7ffff840> - 3fce: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - 3fd2: 7a00 flw fs0,48(a2) - 3fd4: 4f74 lw a3,92(a4) - 3fd6: 9f1a add t5,t5,t1 - 3fd8: 03b4 addi a3,sp,456 - 3fda: 0000 unimp - 3fdc: 03b8 addi a4,sp,456 - 3fde: 0000 unimp - 3fe0: 0001 nop - 3fe2: b85c fsd fa5,176(s0) - 3fe4: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe90c8> - 3fe8: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - 3fec: 7a00 flw fs0,48(a2) - 3fee: 4f74 lw a3,92(a4) - 3ff0: 9f1a add t5,t5,t1 - 3ff2: 03e4 addi s1,sp,460 - 3ff4: 0000 unimp - 3ff6: 0408 addi a0,sp,512 - 3ff8: 0000 unimp - 3ffa: 0001 nop - 3ffc: 085c addi a5,sp,20 - 3ffe: 0004 0x4 - 4000: 3000 fld fs0,32(s0) - 4002: 0004 0x4 - 4004: 0500 addi s0,sp,640 - 4006: 7a00 flw fs0,48(a2) - 4008: 4f74 lw a3,92(a4) - 400a: 9f1a add t5,t5,t1 - ... - 4014: 0334 addi a3,sp,392 - 4016: 0000 unimp - 4018: 0350 addi a2,sp,388 - 401a: 0000 unimp - 401c: 0006 c.slli zero,0x1 - 401e: 2008 fld fa0,0(s0) - 4020: 007c addi a5,sp,12 - 4022: 9f1c 0x9f1c - 4024: 0350 addi a2,sp,388 - 4026: 0000 unimp - 4028: 0360 addi s0,sp,396 - 402a: 0000 unimp - 402c: 0001 nop - 402e: 605f 0003 7000 0x70000003605f - 4034: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 4038: 0800 addi s0,sp,16 - 403a: 7c20 flw fs0,120(s0) - 403c: 1c00 addi s0,sp,560 - 403e: 709f 0003 7c00 0x7c000003709f - 4044: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - 4048: 0800 addi s0,sp,16 - 404a: 7a20 flw fs0,112(a2) - 404c: 4f74 lw a3,92(a4) - 404e: 1c1a slli s8,s8,0x26 - 4050: b49f 0003 b800 0xb8000003b49f - 4056: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - 405a: 0800 addi s0,sp,16 - 405c: 7c20 flw fs0,120(s0) - 405e: 1c00 addi s0,sp,560 - 4060: b89f 0003 e400 0xe4000003b89f - 4066: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - 406a: 0800 addi s0,sp,16 - 406c: 7a20 flw fs0,112(a2) - 406e: 4f74 lw a3,92(a4) - 4070: 1c1a slli s8,s8,0x26 - 4072: e49f 0003 0800 0x8000003e49f - 4078: 0004 0x4 - 407a: 0100 addi s0,sp,128 - 407c: 5f00 lw s0,56(a4) - 407e: 0408 addi a0,sp,512 - 4080: 0000 unimp - 4082: 0430 addi a2,sp,520 - 4084: 0000 unimp - 4086: 0008 0x8 - 4088: 2008 fld fa0,0(s0) - 408a: 747a flw fs0,188(sp) - 408c: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - ... - 4098: 0330 addi a2,sp,392 - 409a: 0000 unimp - 409c: 036c addi a1,sp,396 - 409e: 0000 unimp - 40a0: 0001 nop - 40a2: 6c5e flw fs8,212(sp) - 40a4: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> - 40a8: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 40ac: 7e00 flw fs0,56(a2) - 40ae: 9f01 0x9f01 - 40b0: 0374 addi a3,sp,396 - 40b2: 0000 unimp - 40b4: 037c addi a5,sp,396 - 40b6: 0000 unimp - 40b8: 0005 c.nop 1 - 40ba: 747a flw fs0,188(sp) - 40bc: 2635 jal 43e8 <_start-0x7fffbc18> - 40be: b49f 0003 e000 0xe0000003b49f - 40c4: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 40c8: 5e00 lw s0,56(a2) - 40ca: 03e0 addi s0,sp,460 - 40cc: 0000 unimp - 40ce: 03e4 addi s1,sp,460 - 40d0: 0000 unimp - 40d2: 017e0003 lb zero,23(t3) - 40d6: e49f 0003 0800 0x8000003e49f - 40dc: 0004 0x4 - 40de: 0100 addi s0,sp,128 - 40e0: 5e00 lw s0,56(a2) - 40e2: 0408 addi a0,sp,512 - 40e4: 0000 unimp - 40e6: 0430 addi a2,sp,520 - 40e8: 0000 unimp - 40ea: 0005 c.nop 1 - 40ec: 747a flw fs0,188(sp) - 40ee: 2635 jal 441a <_start-0x7fffbbe6> - 40f0: 009f 0000 0000 0x9f - 40f6: 0000 unimp - 40f8: 6c00 flw fs0,24(s0) - 40fa: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> - 40fe: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - 4102: 5e00 lw s0,56(a2) - 4104: 03c4 addi s1,sp,452 - 4106: 0000 unimp - 4108: 03e4 addi s1,sp,460 - 410a: 0000 unimp - 410c: 0001 nop - 410e: 085f 0004 3000 0x30000004085f - 4114: 0004 0x4 - 4116: 0100 addi s0,sp,128 - 4118: 5e00 lw s0,56(a2) - ... - 4122: 051c addi a5,sp,640 - 4124: 0000 unimp - 4126: 0640 addi s0,sp,772 - 4128: 0000 unimp - 412a: 0001 nop - 412c: 405a 0x405a - 412e: 0006 c.slli zero,0x1 - 4130: 0c00 addi s0,sp,528 - 4132: 22000007 vlseg2bu.v v0,(zero) - 4136: 8e00 0x8e00 - 4138: 7e00 flw fs0,56(a2) - 413a: 1e00 addi s0,sp,816 - 413c: 0089 addi ra,ra,2 - 413e: 791a flw fs2,164(sp) - 4140: 7e00 flw fs0,56(a2) - 4142: 1e00 addi s0,sp,816 - 4144: 008e008f 0x8e008f - 4148: 221e fld ft4,448(sp) - 414a: 008e slli ra,ra,0x3 - 414c: 007e c.slli zero,0x1f - 414e: 401e 0x401e - 4150: 2225 jal 4278 <_start-0x7fffbd88> - 4152: 0089 addi ra,ra,2 - 4154: 401a 0x401a - 4156: 2224 fld fs1,64(a2) - 4158: 0c9f 0007 2000 0x200000070c9f - 415e: 31000007 vlseg2bff.v v0,(zero),v0.t - 4162: 9100 0x9100 - 4164: 7ef0 flw fa2,124(a3) - 4166: 8906 mv s2,ra - 4168: 1a00 addi s0,sp,304 - 416a: 008e slli ra,ra,0x3 - 416c: 891e mv s2,t2 - 416e: 1a00 addi s0,sp,304 - 4170: f091 bnez s1,4074 <_start-0x7fffbf8c> - 4172: 067e slli a2,a2,0x1f - 4174: 0089 addi ra,ra,2 - 4176: 791a flw fs2,164(sp) - 4178: 1e00 addi s0,sp,816 - 417a: 008e008f 0x8e008f - 417e: 221e fld ft4,448(sp) - 4180: f091 bnez s1,4084 <_start-0x7fffbf7c> - 4182: 067e slli a2,a2,0x1f - 4184: 0089 addi ra,ra,2 - 4186: 8e1a mv t3,t1 - 4188: 1e00 addi s0,sp,816 - 418a: 2540 fld fs0,136(a0) - 418c: 8922 mv s2,s0 - 418e: 1a00 addi s0,sp,304 - 4190: 2440 fld fs0,136(s0) - 4192: 9f22 add t5,t5,s0 - 4194: 0720 addi s0,sp,904 - 4196: 0000 unimp - 4198: 075c addi a5,sp,900 - 419a: 0000 unimp - 419c: 0035 c.nop 13 - 419e: f091 bnez s1,40a2 <_start-0x7fffbf5e> - 41a0: 067e slli a2,a2,0x1f - 41a2: 0089 addi ra,ra,2 - 41a4: 8e1a mv t3,t1 - 41a6: 1e00 addi s0,sp,816 - 41a8: 0089 addi ra,ra,2 - 41aa: 911a add sp,sp,t1 - 41ac: 7ef0 flw fa2,124(a3) - 41ae: 8906 mv s2,ra - 41b0: 1a00 addi s0,sp,304 - 41b2: 0079 c.nop 30 - 41b4: 911e add sp,sp,t2 - 41b6: 7ef0 flw fa2,124(a3) - 41b8: 4006 0x4006 - 41ba: 8e25 xor a2,a2,s1 - 41bc: 1e00 addi s0,sp,816 - 41be: 9122 add sp,sp,s0 - 41c0: 7ef0 flw fa2,124(a3) - 41c2: 8906 mv s2,ra - 41c4: 1a00 addi s0,sp,304 - 41c6: 008e slli ra,ra,0x3 - 41c8: 401e 0x401e - 41ca: 2225 jal 42f2 <_start-0x7fffbd0e> - 41cc: 0089 addi ra,ra,2 - 41ce: 401a 0x401a - 41d0: 2224 fld fs1,64(a2) - 41d2: 5c9f 0007 2800 0x280000075c9f - 41d8: 0008 0x8 - 41da: 0100 addi s0,sp,128 - 41dc: 6100 flw fs0,0(a0) - 41de: 0828 addi a0,sp,24 - 41e0: 0000 unimp - 41e2: 0860 addi s0,sp,28 - 41e4: 0000 unimp - 41e6: 0035 c.nop 13 - 41e8: f091 bnez s1,40ec <_start-0x7fffbf14> - 41ea: 067e slli a2,a2,0x1f - 41ec: 0089 addi ra,ra,2 - 41ee: 761a flw fa2,164(sp) - 41f0: 1e00 addi s0,sp,816 - 41f2: 0089 addi ra,ra,2 - 41f4: 911a add sp,sp,t1 - 41f6: 7ef0 flw fa2,124(a3) - 41f8: 8906 mv s2,ra - 41fa: 1a00 addi s0,sp,304 - 41fc: 0075 c.nop 29 - 41fe: 911e add sp,sp,t2 - 4200: 7ef0 flw fa2,124(a3) - 4202: 4006 0x4006 - 4204: 7625 lui a2,0xfffe9 - 4206: 1e00 addi s0,sp,816 - 4208: 9122 add sp,sp,s0 - 420a: 7ef0 flw fa2,124(a3) - 420c: 8906 mv s2,ra - 420e: 1a00 addi s0,sp,304 - 4210: 0076 c.slli zero,0x1d - 4212: 401e 0x401e - 4214: 2225 jal 433c <_start-0x7fffbcc4> - 4216: 0089 addi ra,ra,2 - 4218: 401a 0x401a - 421a: 2224 fld fs1,64(a2) - 421c: 609f 0008 9400 0x94000008609f - 4222: 0008 0x8 - 4224: 3500 fld fs0,40(a0) - 4226: 9100 0x9100 - 4228: 7ef0 flw fa2,124(a3) - 422a: 8c06 mv s8,ra - 422c: 1a00 addi s0,sp,304 - 422e: 0076 c.slli zero,0x1d - 4230: 8c1e mv s8,t2 - 4232: 1a00 addi s0,sp,304 - 4234: f091 bnez s1,4138 <_start-0x7fffbec8> - 4236: 067e slli a2,a2,0x1f - 4238: 008c addi a1,sp,64 - 423a: 751a flw fa0,164(sp) - 423c: 1e00 addi s0,sp,816 - 423e: f091 bnez s1,4142 <_start-0x7fffbebe> - 4240: 067e slli a2,a2,0x1f - 4242: 2540 fld fs0,136(a0) - 4244: 0076 c.slli zero,0x1d - 4246: 221e fld ft4,448(sp) - 4248: f091 bnez s1,414c <_start-0x7fffbeb4> - 424a: 067e slli a2,a2,0x1f - 424c: 008c addi a1,sp,64 - 424e: 761a flw fa2,164(sp) - 4250: 1e00 addi s0,sp,816 - 4252: 2540 fld fs0,136(a0) - 4254: 8c22 mv s8,s0 - 4256: 1a00 addi s0,sp,304 - 4258: 2440 fld fs0,136(s0) - 425a: 9f22 add t5,t5,s0 - 425c: 0894 addi a3,sp,80 - 425e: 0000 unimp - 4260: 08e0 addi s0,sp,92 - 4262: 0000 unimp - 4264: 003a c.slli zero,0xe - 4266: f091 bnez s1,416a <_start-0x7fffbe96> - 4268: 067e slli a2,a2,0x1f - 426a: ff0a fsw ft2,188(sp) - 426c: 1aff 0x1aff - 426e: 0076 c.slli zero,0x1d - 4270: 0a1e slli s4,s4,0x7 - 4272: ffff 0xffff - 4274: 911a add sp,sp,t1 - 4276: 7ef0 flw fa2,124(a3) - 4278: 0a06 slli s4,s4,0x1 - 427a: ffff 0xffff - 427c: 751a flw fa0,164(sp) - 427e: 1e00 addi s0,sp,816 - 4280: f091 bnez s1,4184 <_start-0x7fffbe7c> - 4282: 067e slli a2,a2,0x1f - 4284: 2540 fld fs0,136(a0) - 4286: 0076 c.slli zero,0x1d - 4288: 221e fld ft4,448(sp) - 428a: f091 bnez s1,418e <_start-0x7fffbe72> - 428c: 067e slli a2,a2,0x1f - 428e: ff0a fsw ft2,188(sp) - 4290: 1aff 0x1aff - 4292: 0076 c.slli zero,0x1d - 4294: 401e 0x401e - 4296: 2225 jal 43be <_start-0x7fffbc42> - 4298: ff0a fsw ft2,188(sp) - 429a: 1aff 0x1aff - 429c: 2440 fld fs0,136(s0) - 429e: 9f22 add t5,t5,s0 - 42a0: 08e0 addi s0,sp,92 - 42a2: 0000 unimp - 42a4: 08e4 addi s1,sp,92 - 42a6: 0000 unimp - 42a8: 0035 c.nop 13 - 42aa: 7f7a flw ft10,188(sp) - 42ac: f091 bnez s1,41b0 <_start-0x7fffbe50> - 42ae: 067e slli a2,a2,0x1f - 42b0: 761a flw fa2,164(sp) - 42b2: 1e00 addi s0,sp,816 - 42b4: 7f7a flw ft10,188(sp) - 42b6: 7a1a flw fs4,164(sp) - 42b8: 917f 0x917f - 42ba: 7ef0 flw fa2,124(a3) - 42bc: 1a06 slli s4,s4,0x21 - 42be: 0075 c.nop 29 - 42c0: 911e add sp,sp,t2 - 42c2: 7ef0 flw fa2,124(a3) - 42c4: 4006 0x4006 - 42c6: 7625 lui a2,0xfffe9 - 42c8: 1e00 addi s0,sp,816 - 42ca: 7a22 flw fs4,40(sp) - 42cc: 917f 0x917f - 42ce: 7ef0 flw fa2,124(a3) - 42d0: 1a06 slli s4,s4,0x21 - 42d2: 0076 c.slli zero,0x1d - 42d4: 401e 0x401e - 42d6: 2225 jal 43fe <_start-0x7fffbc02> - 42d8: 7f7a flw ft10,188(sp) - 42da: 401a 0x401a - 42dc: 2224 fld fs1,64(a2) - 42de: e49f 0008 e800 0xe8000008e49f - 42e4: 0008 0x8 - 42e6: 3a00 fld fs0,48(a2) - 42e8: 9100 0x9100 - 42ea: 7ef0 flw fa2,124(a3) - 42ec: 0a06 slli s4,s4,0x1 - 42ee: ffff 0xffff - 42f0: 761a flw fa2,164(sp) - 42f2: 1e00 addi s0,sp,816 - 42f4: ff0a fsw ft2,188(sp) - 42f6: 1aff 0x1aff - 42f8: f091 bnez s1,41fc <_start-0x7fffbe04> - 42fa: 067e slli a2,a2,0x1f - 42fc: ff0a fsw ft2,188(sp) - 42fe: 1aff 0x1aff - 4300: 0075 c.nop 29 - 4302: 911e add sp,sp,t2 - 4304: 7ef0 flw fa2,124(a3) - 4306: 4006 0x4006 - 4308: 7625 lui a2,0xfffe9 - 430a: 1e00 addi s0,sp,816 - 430c: 9122 add sp,sp,s0 - 430e: 7ef0 flw fa2,124(a3) - 4310: 0a06 slli s4,s4,0x1 - 4312: ffff 0xffff - 4314: 761a flw fa2,164(sp) - 4316: 1e00 addi s0,sp,816 - 4318: 2540 fld fs0,136(a0) - 431a: 0a22 slli s4,s4,0x8 - 431c: ffff 0xffff - 431e: 401a 0x401a - 4320: 2224 fld fs1,64(a2) - 4322: e89f 0008 0800 0x8000008e89f - 4328: 0009 c.nop 2 - 432a: 3500 fld fs0,40(a0) - 432c: 8400 0x8400 - 432e: 917f 0x917f - 4330: 7ef0 flw fa2,124(a3) - 4332: 1a06 slli s4,s4,0x21 - 4334: 0076 c.slli zero,0x1d - 4336: 841e mv s0,t2 - 4338: 1a7f 0x1a7f - 433a: 7f84 flw fs1,56(a5) - 433c: f091 bnez s1,4240 <_start-0x7fffbdc0> - 433e: 067e slli a2,a2,0x1f - 4340: 751a flw fa0,164(sp) - 4342: 1e00 addi s0,sp,816 - 4344: f091 bnez s1,4248 <_start-0x7fffbdb8> - 4346: 067e slli a2,a2,0x1f - 4348: 2540 fld fs0,136(a0) - 434a: 0076 c.slli zero,0x1d - 434c: 221e fld ft4,448(sp) - 434e: 7f84 flw fs1,56(a5) - 4350: f091 bnez s1,4254 <_start-0x7fffbdac> - 4352: 067e slli a2,a2,0x1f - 4354: 761a flw fa2,164(sp) - 4356: 1e00 addi s0,sp,816 - 4358: 2540 fld fs0,136(a0) - 435a: 8422 mv s0,s0 - 435c: 1a7f 0x1a7f - 435e: 2440 fld fs0,136(s0) - 4360: 9f22 add t5,t5,s0 - 4362: 0908 addi a0,sp,144 - 4364: 0000 unimp - 4366: 0a0c addi a1,sp,272 - 4368: 0000 unimp - 436a: 0001 nop - 436c: 0c5a slli s8,s8,0x16 - 436e: 000a c.slli zero,0x2 - 4370: 4800 lw s0,16(s0) - 4372: 000a c.slli zero,0x2 - 4374: 4400 lw s0,8(s0) - 4376: 8400 0x8400 - 4378: 917f 0x917f - 437a: 7f88 flw fa0,56(a5) - 437c: 1a06 slli s4,s4,0x21 - 437e: 7f84 flw fs1,56(a5) - 4380: f891 bnez s1,4294 <_start-0x7fffbd6c> - 4382: 067e slli a2,a2,0x1f - 4384: 1e1a slli t3,t3,0x26 - 4386: 7f84 flw fs1,56(a5) - 4388: 841a mv s0,t1 - 438a: 917f 0x917f - 438c: 7ef8 flw fa4,124(a3) - 438e: 1a06 slli s4,s4,0x21 - 4390: 0078 addi a4,sp,12 - 4392: 841e mv s0,t2 - 4394: 917f 0x917f - 4396: 7f88 flw fa0,56(a5) - 4398: 1a06 slli s4,s4,0x21 - 439a: f891 bnez s1,42ae <_start-0x7fffbd52> - 439c: 067e slli a2,a2,0x1f - 439e: 2540 fld fs0,136(a0) - 43a0: 221e fld ft4,448(sp) - 43a2: 7f84 flw fs1,56(a5) - 43a4: 8891 andi s1,s1,4 - 43a6: 067f 0x67f - 43a8: 841a mv s0,t1 - 43aa: 917f 0x917f - 43ac: 7ef8 flw fa4,124(a3) - 43ae: 1a06 slli s4,s4,0x21 - 43b0: 401e 0x401e - 43b2: 2225 jal 44da <_start-0x7fffbb26> - 43b4: 7f84 flw fs1,56(a5) - 43b6: 401a 0x401a - 43b8: 2224 fld fs1,64(a2) - 43ba: 489f 000a e000 0xe000000a489f - 43c0: 000a c.slli zero,0x2 - 43c2: 4400 lw s0,8(s0) - 43c4: 9100 0x9100 - 43c6: 7f88 flw fa0,56(a5) - 43c8: 7906 flw fs2,96(sp) - 43ca: 1a00 addi s0,sp,304 - 43cc: f891 bnez s1,42e0 <_start-0x7fffbd20> - 43ce: 067e slli a2,a2,0x1f - 43d0: 0079 c.nop 30 - 43d2: 1e1a slli t3,t3,0x26 - 43d4: 0079 c.nop 30 - 43d6: 911a add sp,sp,t1 - 43d8: 7ef8 flw fa4,124(a3) - 43da: 7906 flw fs2,96(sp) - 43dc: 1a00 addi s0,sp,304 - 43de: 0078 addi a4,sp,12 - 43e0: 911e add sp,sp,t2 - 43e2: 7f88 flw fa0,56(a5) - 43e4: 7906 flw fs2,96(sp) - 43e6: 1a00 addi s0,sp,304 - 43e8: f891 bnez s1,42fc <_start-0x7fffbd04> - 43ea: 067e slli a2,a2,0x1f - 43ec: 2540 fld fs0,136(a0) - 43ee: 221e fld ft4,448(sp) - 43f0: 8891 andi s1,s1,4 - 43f2: 067f 0x67f - 43f4: 0079 c.nop 30 - 43f6: 911a add sp,sp,t1 - 43f8: 7ef8 flw fa4,124(a3) - 43fa: 7906 flw fs2,96(sp) - 43fc: 1a00 addi s0,sp,304 - 43fe: 401e 0x401e - 4400: 2225 jal 4528 <_start-0x7fffbad8> - 4402: 0079 c.nop 30 - 4404: 401a 0x401a - 4406: 2224 fld fs1,64(a2) - 4408: e09f 000a e400 0xe400000ae09f - 440e: 000a c.slli zero,0x2 - 4410: 4400 lw s0,8(s0) - 4412: 8900 0x8900 - 4414: 917f 0x917f - 4416: 7f88 flw fa0,56(a5) - 4418: 1a06 slli s4,s4,0x21 - 441a: 7f89 lui t6,0xfffe2 - 441c: f891 bnez s1,4330 <_start-0x7fffbcd0> - 441e: 067e slli a2,a2,0x1f - 4420: 1e1a slli t3,t3,0x26 - 4422: 7f89 lui t6,0xfffe2 - 4424: 891a mv s2,t1 - 4426: 917f 0x917f - 4428: 7ef8 flw fa4,124(a3) - 442a: 1a06 slli s4,s4,0x21 - 442c: 0078 addi a4,sp,12 - 442e: 891e mv s2,t2 - 4430: 917f 0x917f - 4432: 7f88 flw fa0,56(a5) - 4434: 1a06 slli s4,s4,0x21 - 4436: f891 bnez s1,434a <_start-0x7fffbcb6> - 4438: 067e slli a2,a2,0x1f - 443a: 2540 fld fs0,136(a0) - 443c: 221e fld ft4,448(sp) - 443e: 7f89 lui t6,0xfffe2 - 4440: 8891 andi s1,s1,4 - 4442: 067f 0x67f - 4444: 891a mv s2,t1 - 4446: 917f 0x917f - 4448: 7ef8 flw fa4,124(a3) - 444a: 1a06 slli s4,s4,0x21 - 444c: 401e 0x401e - 444e: 2225 jal 4576 <_start-0x7fffba8a> - 4450: 7f89 lui t6,0xfffe2 - 4452: 401a 0x401a - 4454: 2224 fld fs1,64(a2) - 4456: e49f 000a fc00 0xfc00000ae49f - 445c: 000a c.slli zero,0x2 - 445e: 0100 addi s0,sp,128 - 4460: 5900 lw s0,48(a0) - 4462: 0afc addi a5,sp,348 - 4464: 0000 unimp - 4466: 0bc4 addi s1,sp,468 - 4468: 0000 unimp - 446a: 7f890013 addi zero,s2,2040 - 446e: 007a c.slli zero,0x1e - 4470: 7a1a flw fs4,164(sp) - 4472: 4000 lw s0,0(s0) - 4474: 8325 srli a4,a4,0x9 - 4476: 2200 fld fs0,0(a2) - 4478: 7f89 lui t6,0xfffe2 - 447a: 401a 0x401a - 447c: 2224 fld fs1,64(a2) - 447e: a89f 000d b400 0xb400000da89f - 4484: 000d c.nop 3 - 4486: 1300 addi s0,sp,416 - 4488: 8900 0x8900 - 448a: 7a7f 0x7a7f - 448c: 1a00 addi s0,sp,304 - 448e: 007a c.slli zero,0x1e - 4490: 2540 fld fs0,136(a0) - 4492: 89220083 lb ra,-1902(tp) # fffff892 <__BSS_END__+0x7ffe8b1a> - 4496: 1a7f 0x1a7f - 4498: 2440 fld fs0,136(s0) - 449a: 9f22 add t5,t5,s0 - ... - 44a4: 04fc addi a5,sp,588 - 44a6: 0000 unimp - 44a8: 0648 addi a0,sp,772 - 44aa: 0000 unimp - 44ac: 0006 c.slli zero,0x1 - 44ae: 0084008b 0x84008b - 44b2: 9f22 add t5,t5,s0 - 44b4: 0648 addi a0,sp,772 - 44b6: 0000 unimp - 44b8: 0654 addi a3,sp,772 - 44ba: 0000 unimp - 44bc: 0019 c.nop 6 - 44be: 0079 c.nop 30 - 44c0: 007e c.slli zero,0x1f - 44c2: 8f1e mv t5,t2 - 44c4: 8e00 0x8e00 - 44c6: 1e00 addi s0,sp,816 - 44c8: 8e22 mv t3,s0 - 44ca: 7e00 flw fs0,56(a2) - 44cc: 1e00 addi s0,sp,816 - 44ce: 2540 fld fs0,136(a0) - 44d0: 4022 0x4022 - 44d2: 8425 srai s0,s0,0x9 - 44d4: 2200 fld fs0,0(a2) - 44d6: 5c9f 0007 8400 0x840000075c9f - 44dc: 01000007 vlbuff.v v0,(zero),v0.t - 44e0: 5e00 lw s0,56(a2) - 44e2: 0784 addi s1,sp,960 - 44e4: 0000 unimp - 44e6: 08f4 addi a3,sp,92 - 44e8: 0000 unimp - 44ea: 0001 nop - 44ec: 0008f46b 0x8f46b - 44f0: d400 sw s0,40(s0) - 44f2: 000a c.slli zero,0x2 - 44f4: 0100 addi s0,sp,128 - 44f6: 6100 flw fs0,0(a0) - 44f8: 0ad4 addi a3,sp,340 - 44fa: 0000 unimp - 44fc: 0ae8 addi a0,sp,348 - 44fe: 0000 unimp - 4500: 0008 0x8 - 4502: 0075 c.nop 29 - 4504: 2540 fld fs0,136(a0) - 4506: 9f22008f 0x9f22008f - 450a: 0ae8 addi a0,sp,348 - 450c: 0000 unimp - 450e: 0af0 addi a2,sp,348 - 4510: 0000 unimp - 4512: 0006 c.slli zero,0x1 - 4514: 0075 c.nop 29 - 4516: 9f22008f 0x9f22008f - 451a: 0af0 addi a2,sp,348 - 451c: 0000 unimp - 451e: 0b08 addi a0,sp,400 - 4520: 0000 unimp - 4522: 000d c.nop 3 - 4524: 007a c.slli zero,0x1e - 4526: 2540 fld fs0,136(a0) - 4528: 40220083 lb ra,1026(tp) # 402 <_start-0x7ffffbfe> - 452c: 8f25 xor a4,a4,s1 - 452e: 2200 fld fs0,0(a2) - 4530: 009f 0000 0000 0x9f - 4536: 0000 unimp - 4538: 5c00 lw s0,56(s0) - 453a: 0005 c.nop 1 - 453c: 6000 flw fs0,0(s0) - 453e: 0006 c.slli zero,0x1 - 4540: 0100 addi s0,sp,128 - 4542: 6000 flw fs0,0(s0) - 4544: 0660 addi s0,sp,780 - 4546: 0000 unimp - 4548: 0764 addi s1,sp,908 - 454a: 0000 unimp - 454c: 0022 c.slli zero,0x8 - 454e: 008c addi a1,sp,64 - 4550: 891e007b 0x891e007b - 4554: 1a00 addi s0,sp,304 - 4556: 0085 addi ra,ra,1 - 4558: 821e007b 0x821e007b - 455c: 8c00 0x8c00 - 455e: 1e00 addi s0,sp,816 - 4560: 8c22 mv s8,s0 - 4562: 7b00 flw fs0,48(a4) - 4564: 1e00 addi s0,sp,816 - 4566: 2540 fld fs0,136(a0) - 4568: 8922 mv s2,s0 - 456a: 1a00 addi s0,sp,304 - 456c: 2440 fld fs0,136(s0) - 456e: 9f22 add t5,t5,s0 - 4570: 0764 addi s1,sp,908 - 4572: 0000 unimp - 4574: 076c addi a1,sp,908 - 4576: 0000 unimp - 4578: 0026 c.slli zero,0x9 - 457a: 008c addi a1,sp,64 - 457c: 891e007b 0x891e007b - 4580: 1a00 addi s0,sp,304 - 4582: 8091 srli s1,s1,0x4 - 4584: 067f 0x67f - 4586: 2540 fld fs0,136(a0) - 4588: 821e007b 0x821e007b - 458c: 8c00 0x8c00 - 458e: 1e00 addi s0,sp,816 - 4590: 8c22 mv s8,s0 - 4592: 7b00 flw fs0,48(a4) - 4594: 1e00 addi s0,sp,816 - 4596: 2540 fld fs0,136(a0) - 4598: 8922 mv s2,s0 - 459a: 1a00 addi s0,sp,304 - 459c: 2440 fld fs0,136(s0) - 459e: 9f22 add t5,t5,s0 - 45a0: 076c addi a1,sp,908 - 45a2: 0000 unimp - 45a4: 07a0 addi s0,sp,968 - 45a6: 0000 unimp - 45a8: 0035 c.nop 13 - 45aa: 8091 srli s1,s1,0x4 - 45ac: 067f 0x67f - 45ae: 0089 addi ra,ra,2 - 45b0: 7b1a flw fs6,164(sp) - 45b2: 1e00 addi s0,sp,816 - 45b4: 0089 addi ra,ra,2 - 45b6: 911a add sp,sp,t1 - 45b8: 7f80 flw fs0,56(a5) - 45ba: 4006 0x4006 - 45bc: 7b25 lui s6,0xfffe9 - 45be: 1e00 addi s0,sp,816 - 45c0: 8091 srli s1,s1,0x4 - 45c2: 067f 0x67f - 45c4: 0089 addi ra,ra,2 - 45c6: 821a mv tp,t1 - 45c8: 1e00 addi s0,sp,816 - 45ca: 9122 add sp,sp,s0 - 45cc: 7f80 flw fs0,56(a5) - 45ce: 8906 mv s2,ra - 45d0: 1a00 addi s0,sp,304 - 45d2: 401e007b 0x401e007b - 45d6: 2225 jal 46fe <_start-0x7fffb902> - 45d8: 0089 addi ra,ra,2 - 45da: 401a 0x401a - 45dc: 2224 fld fs1,64(a2) - 45de: a09f 0007 5400 0x54000007a09f - 45e4: 0008 0x8 - 45e6: 0100 addi s0,sp,128 - 45e8: 6000 flw fs0,0(s0) - 45ea: 0854 addi a3,sp,20 - 45ec: 0000 unimp - 45ee: 0860 addi s0,sp,28 - 45f0: 0000 unimp - 45f2: 0035 c.nop 13 - 45f4: 8091 srli s1,s1,0x4 - 45f6: 067f 0x67f - 45f8: 0089 addi ra,ra,2 - 45fa: 831a mv t1,t1 - 45fc: 1e00 addi s0,sp,816 - 45fe: 0089 addi ra,ra,2 - 4600: 911a add sp,sp,t1 - 4602: 7f80 flw fs0,56(a5) - 4604: 4006 0x4006 - 4606: 8325 srli a4,a4,0x9 - 4608: 1e00 addi s0,sp,816 - 460a: 8091 srli s1,s1,0x4 - 460c: 067f 0x67f - 460e: 0089 addi ra,ra,2 - 4610: 8f1a mv t5,t1 - 4612: 1e00 addi s0,sp,816 - 4614: 9122 add sp,sp,s0 - 4616: 7f80 flw fs0,56(a5) - 4618: 8906 mv s2,ra - 461a: 1a00 addi s0,sp,304 - 461c: 401e0083 lb ra,1025(t3) - 4620: 2225 jal 4748 <_start-0x7fffb8b8> - 4622: 0089 addi ra,ra,2 - 4624: 401a 0x401a - 4626: 2224 fld fs1,64(a2) - 4628: 609f 0008 9400 0x94000008609f - 462e: 0008 0x8 - 4630: 3500 fld fs0,40(a0) - 4632: 9100 0x9100 - 4634: 7f80 flw fs0,56(a5) - 4636: 8c06 mv s8,ra - 4638: 1a00 addi s0,sp,304 - 463a: 8c1e0083 lb ra,-1855(t3) - 463e: 1a00 addi s0,sp,304 - 4640: 8091 srli s1,s1,0x4 - 4642: 067f 0x67f - 4644: 2540 fld fs0,136(a0) - 4646: 911e0083 lb ra,-1775(t3) - 464a: 7f80 flw fs0,56(a5) - 464c: 8c06 mv s8,ra - 464e: 1a00 addi s0,sp,304 - 4650: 221e008f 0x221e008f - 4654: 8091 srli s1,s1,0x4 - 4656: 067f 0x67f - 4658: 008c addi a1,sp,64 - 465a: 831a mv t1,t1 - 465c: 1e00 addi s0,sp,816 - 465e: 2540 fld fs0,136(a0) - 4660: 8c22 mv s8,s0 - 4662: 1a00 addi s0,sp,304 - 4664: 2440 fld fs0,136(s0) - 4666: 9f22 add t5,t5,s0 - 4668: 0894 addi a3,sp,80 - 466a: 0000 unimp - 466c: 08e0 addi s0,sp,92 - 466e: 0000 unimp - 4670: 003a c.slli zero,0xe - 4672: 8091 srli s1,s1,0x4 - 4674: 067f 0x67f - 4676: ff0a fsw ft2,188(sp) - 4678: 1aff 0x1aff - 467a: 0a1e0083 lb ra,161(t3) - 467e: ffff 0xffff - 4680: 911a add sp,sp,t1 - 4682: 7f80 flw fs0,56(a5) - 4684: 4006 0x4006 - 4686: 8325 srli a4,a4,0x9 - 4688: 1e00 addi s0,sp,816 - 468a: 8091 srli s1,s1,0x4 - 468c: 067f 0x67f - 468e: ff0a fsw ft2,188(sp) - 4690: 1aff 0x1aff - 4692: 221e008f 0x221e008f - 4696: 8091 srli s1,s1,0x4 - 4698: 067f 0x67f - 469a: ff0a fsw ft2,188(sp) - 469c: 1aff 0x1aff - 469e: 401e0083 lb ra,1025(t3) - 46a2: 2225 jal 47ca <_start-0x7fffb836> - 46a4: ff0a fsw ft2,188(sp) - 46a6: 1aff 0x1aff - 46a8: 2440 fld fs0,136(s0) - 46aa: 9f22 add t5,t5,s0 - 46ac: 08e0 addi s0,sp,92 - 46ae: 0000 unimp - 46b0: 08e4 addi s1,sp,92 - 46b2: 0000 unimp - 46b4: 0035 c.nop 13 - 46b6: 7f7a flw ft10,188(sp) - 46b8: 8091 srli s1,s1,0x4 - 46ba: 067f 0x67f - 46bc: 831a mv t1,t1 - 46be: 1e00 addi s0,sp,816 - 46c0: 7f7a flw ft10,188(sp) - 46c2: 911a add sp,sp,t1 - 46c4: 7f80 flw fs0,56(a5) - 46c6: 4006 0x4006 - 46c8: 8325 srli a4,a4,0x9 - 46ca: 1e00 addi s0,sp,816 - 46cc: 7f7a flw ft10,188(sp) - 46ce: 8091 srli s1,s1,0x4 - 46d0: 067f 0x67f - 46d2: 8f1a mv t5,t1 - 46d4: 1e00 addi s0,sp,816 - 46d6: 7a22 flw fs4,40(sp) - 46d8: 917f 0x917f - 46da: 7f80 flw fs0,56(a5) - 46dc: 1a06 slli s4,s4,0x21 - 46de: 401e0083 lb ra,1025(t3) - 46e2: 2225 jal 480a <_start-0x7fffb7f6> - 46e4: 7f7a flw ft10,188(sp) - 46e6: 401a 0x401a - 46e8: 2224 fld fs1,64(a2) - 46ea: e49f 0008 e800 0xe8000008e49f - 46f0: 0008 0x8 - 46f2: 3a00 fld fs0,48(a2) - 46f4: 9100 0x9100 - 46f6: 7f80 flw fs0,56(a5) - 46f8: 0a06 slli s4,s4,0x1 - 46fa: ffff 0xffff - 46fc: 831a mv t1,t1 - 46fe: 1e00 addi s0,sp,816 - 4700: ff0a fsw ft2,188(sp) - 4702: 1aff 0x1aff - 4704: 8091 srli s1,s1,0x4 - 4706: 067f 0x67f - 4708: 2540 fld fs0,136(a0) - 470a: 911e0083 lb ra,-1775(t3) - 470e: 7f80 flw fs0,56(a5) - 4710: 0a06 slli s4,s4,0x1 - 4712: ffff 0xffff - 4714: 8f1a mv t5,t1 - 4716: 1e00 addi s0,sp,816 - 4718: 9122 add sp,sp,s0 - 471a: 7f80 flw fs0,56(a5) - 471c: 0a06 slli s4,s4,0x1 - 471e: ffff 0xffff - 4720: 831a mv t1,t1 - 4722: 1e00 addi s0,sp,816 - 4724: 2540 fld fs0,136(a0) - 4726: 0a22 slli s4,s4,0x8 - 4728: ffff 0xffff - 472a: 401a 0x401a - 472c: 2224 fld fs1,64(a2) - 472e: e89f 0008 3400 0x34000008e89f - 4734: 0009 c.nop 2 - 4736: 3500 fld fs0,40(a0) - 4738: 8400 0x8400 - 473a: 917f 0x917f - 473c: 7f80 flw fs0,56(a5) - 473e: 1a06 slli s4,s4,0x21 - 4740: 841e0083 lb ra,-1983(t3) - 4744: 1a7f 0x1a7f - 4746: 8091 srli s1,s1,0x4 - 4748: 067f 0x67f - 474a: 2540 fld fs0,136(a0) - 474c: 841e0083 lb ra,-1983(t3) - 4750: 917f 0x917f - 4752: 7f80 flw fs0,56(a5) - 4754: 1a06 slli s4,s4,0x21 - 4756: 221e008f 0x221e008f - 475a: 7f84 flw fs1,56(a5) - 475c: 8091 srli s1,s1,0x4 - 475e: 067f 0x67f - 4760: 831a mv t1,t1 - 4762: 1e00 addi s0,sp,816 - 4764: 2540 fld fs0,136(a0) - 4766: 8422 mv s0,s0 - 4768: 1a7f 0x1a7f - 476a: 2440 fld fs0,136(s0) - 476c: 9f22 add t5,t5,s0 - 476e: 0934 addi a3,sp,152 - 4770: 0000 unimp - 4772: 094c addi a1,sp,148 - 4774: 0000 unimp - 4776: 0035 c.nop 13 - 4778: 8091 srli s1,s1,0x4 - 477a: 067f 0x67f - 477c: 0084 addi s1,sp,64 - 477e: 831a mv t1,t1 - 4780: 1e00 addi s0,sp,816 - 4782: 0084 addi s1,sp,64 - 4784: 911a add sp,sp,t1 - 4786: 7f80 flw fs0,56(a5) - 4788: 4006 0x4006 - 478a: 8325 srli a4,a4,0x9 - 478c: 1e00 addi s0,sp,816 - 478e: 8091 srli s1,s1,0x4 - 4790: 067f 0x67f - 4792: 0084 addi s1,sp,64 - 4794: 8f1a mv t5,t1 - 4796: 1e00 addi s0,sp,816 - 4798: 9122 add sp,sp,s0 - 479a: 7f80 flw fs0,56(a5) - 479c: 8406 mv s0,ra - 479e: 1a00 addi s0,sp,304 - 47a0: 401e0083 lb ra,1025(t3) - 47a4: 2225 jal 48cc <_start-0x7fffb734> - 47a6: 0084 addi s1,sp,64 - 47a8: 401a 0x401a - 47aa: 2224 fld fs1,64(a2) - 47ac: 4c9f 0009 2c00 0x2c0000094c9f - 47b2: 000a c.slli zero,0x2 - 47b4: 0100 addi s0,sp,128 - 47b6: 5b00 lw s0,48(a4) - 47b8: 0a2c addi a1,sp,280 - 47ba: 0000 unimp - 47bc: 0a48 addi a0,sp,276 - 47be: 0000 unimp - 47c0: 0035 c.nop 13 - 47c2: 7f84 flw fs1,56(a5) - 47c4: f491 bnez s1,46d0 <_start-0x7fffb930> - 47c6: 067e slli a2,a2,0x1f - 47c8: 761a flw fa2,164(sp) - 47ca: 1e00 addi s0,sp,816 - 47cc: 7f84 flw fs1,56(a5) - 47ce: 841a mv s0,t1 - 47d0: 917f 0x917f - 47d2: 7ef4 flw fa3,124(a3) - 47d4: 1a06 slli s4,s4,0x21 - 47d6: 0075 c.nop 29 - 47d8: 911e add sp,sp,t2 - 47da: 7ef4 flw fa3,124(a3) - 47dc: 4006 0x4006 - 47de: 7625 lui a2,0xfffe9 - 47e0: 1e00 addi s0,sp,816 - 47e2: 8422 mv s0,s0 - 47e4: 917f 0x917f - 47e6: 7ef4 flw fa3,124(a3) - 47e8: 1a06 slli s4,s4,0x21 - 47ea: 0076 c.slli zero,0x1d - 47ec: 401e 0x401e - 47ee: 2225 jal 4916 <_start-0x7fffb6ea> - 47f0: 7f84 flw fs1,56(a5) - 47f2: 401a 0x401a - 47f4: 2224 fld fs1,64(a2) - 47f6: 489f 000a b400 0xb400000a489f - 47fc: 000a c.slli zero,0x2 - 47fe: 3500 fld fs0,40(a0) - 4800: 9100 0x9100 - 4802: 7ef4 flw fa3,124(a3) - 4804: 7906 flw fs2,96(sp) - 4806: 1a00 addi s0,sp,304 - 4808: 0076 c.slli zero,0x1d - 480a: 791e flw fs2,228(sp) - 480c: 1a00 addi s0,sp,304 - 480e: f491 bnez s1,471a <_start-0x7fffb8e6> - 4810: 067e slli a2,a2,0x1f - 4812: 0079 c.nop 30 - 4814: 751a flw fa0,164(sp) - 4816: 1e00 addi s0,sp,816 - 4818: f491 bnez s1,4724 <_start-0x7fffb8dc> - 481a: 067e slli a2,a2,0x1f - 481c: 2540 fld fs0,136(a0) - 481e: 0076 c.slli zero,0x1d - 4820: 221e fld ft4,448(sp) - 4822: f491 bnez s1,472e <_start-0x7fffb8d2> - 4824: 067e slli a2,a2,0x1f - 4826: 0079 c.nop 30 - 4828: 761a flw fa2,164(sp) - 482a: 1e00 addi s0,sp,816 - 482c: 2540 fld fs0,136(a0) - 482e: 7922 flw fs2,40(sp) - 4830: 1a00 addi s0,sp,304 - 4832: 2440 fld fs0,136(s0) - 4834: 9f22 add t5,t5,s0 - 4836: 0ab4 addi a3,sp,344 - 4838: 0000 unimp - 483a: 0acc addi a1,sp,340 - 483c: 0000 unimp - 483e: 0044 addi s1,sp,4 - 4840: 8c91 sub s1,s1,a2 - 4842: 067f 0x67f - 4844: 0079 c.nop 30 - 4846: 911a add sp,sp,t1 - 4848: 7ef4 flw fa3,124(a3) - 484a: 7906 flw fs2,96(sp) - 484c: 1a00 addi s0,sp,304 - 484e: 791e flw fs2,228(sp) - 4850: 1a00 addi s0,sp,304 - 4852: f491 bnez s1,475e <_start-0x7fffb8a2> - 4854: 067e slli a2,a2,0x1f - 4856: 0079 c.nop 30 - 4858: 751a flw fa0,164(sp) - 485a: 1e00 addi s0,sp,816 - 485c: 8c91 sub s1,s1,a2 - 485e: 067f 0x67f - 4860: 0079 c.nop 30 - 4862: 911a add sp,sp,t1 - 4864: 7ef4 flw fa3,124(a3) - 4866: 4006 0x4006 - 4868: 1e25 addi t3,t3,-23 - 486a: 9122 add sp,sp,s0 - 486c: 7f8c flw fa1,56(a5) - 486e: 7906 flw fs2,96(sp) - 4870: 1a00 addi s0,sp,304 - 4872: f491 bnez s1,477e <_start-0x7fffb882> - 4874: 067e slli a2,a2,0x1f - 4876: 0079 c.nop 30 - 4878: 1e1a slli t3,t3,0x26 - 487a: 2540 fld fs0,136(a0) - 487c: 7922 flw fs2,40(sp) - 487e: 1a00 addi s0,sp,304 - 4880: 2440 fld fs0,136(s0) - 4882: 9f22 add t5,t5,s0 - 4884: 0acc addi a1,sp,340 - 4886: 0000 unimp - 4888: 0ae0 addi s0,sp,348 - 488a: 0000 unimp - 488c: 0048 addi a0,sp,4 - 488e: 8c91 sub s1,s1,a2 - 4890: 067f 0x67f - 4892: 0079 c.nop 30 - 4894: 911a add sp,sp,t1 - 4896: 7ef4 flw fa3,124(a3) - 4898: 7906 flw fs2,96(sp) - 489a: 1a00 addi s0,sp,304 - 489c: 791e flw fs2,228(sp) - 489e: 1a00 addi s0,sp,304 - 48a0: f491 bnez s1,47ac <_start-0x7fffb854> - 48a2: 067e slli a2,a2,0x1f - 48a4: 0079 c.nop 30 - 48a6: 911a add sp,sp,t1 - 48a8: 7f8c flw fa1,56(a5) - 48aa: 4006 0x4006 - 48ac: 1e25 addi t3,t3,-23 - 48ae: 8c91 sub s1,s1,a2 - 48b0: 067f 0x67f - 48b2: 0079 c.nop 30 - 48b4: 911a add sp,sp,t1 - 48b6: 7ef4 flw fa3,124(a3) - 48b8: 4006 0x4006 - 48ba: 1e25 addi t3,t3,-23 - 48bc: 9122 add sp,sp,s0 - 48be: 7f8c flw fa1,56(a5) - 48c0: 7906 flw fs2,96(sp) - 48c2: 1a00 addi s0,sp,304 - 48c4: f491 bnez s1,47d0 <_start-0x7fffb830> - 48c6: 067e slli a2,a2,0x1f - 48c8: 0079 c.nop 30 - 48ca: 1e1a slli t3,t3,0x26 - 48cc: 2540 fld fs0,136(a0) - 48ce: 7922 flw fs2,40(sp) - 48d0: 1a00 addi s0,sp,304 - 48d2: 2440 fld fs0,136(s0) - 48d4: 9f22 add t5,t5,s0 - 48d6: 0ae0 addi s0,sp,348 - 48d8: 0000 unimp - 48da: 0bc4 addi s1,sp,468 - 48dc: 0000 unimp - 48de: 0048 addi a0,sp,4 - 48e0: 7f89 lui t6,0xfffe2 - 48e2: 8c91 sub s1,s1,a2 - 48e4: 067f 0x67f - 48e6: 891a mv s2,t1 - 48e8: 917f 0x917f - 48ea: 7ef4 flw fa3,124(a3) - 48ec: 1a06 slli s4,s4,0x21 - 48ee: 891e mv s2,t2 - 48f0: 1a7f 0x1a7f - 48f2: 7f89 lui t6,0xfffe2 - 48f4: f491 bnez s1,4800 <_start-0x7fffb800> - 48f6: 067e slli a2,a2,0x1f - 48f8: 911a add sp,sp,t1 - 48fa: 7f8c flw fa1,56(a5) - 48fc: 4006 0x4006 - 48fe: 1e25 addi t3,t3,-23 - 4900: 7f89 lui t6,0xfffe2 - 4902: 8c91 sub s1,s1,a2 - 4904: 067f 0x67f - 4906: 911a add sp,sp,t1 - 4908: 7ef4 flw fa3,124(a3) - 490a: 4006 0x4006 - 490c: 1e25 addi t3,t3,-23 - 490e: 8922 mv s2,s0 - 4910: 917f 0x917f - 4912: 7f8c flw fa1,56(a5) - 4914: 1a06 slli s4,s4,0x21 - 4916: 7f89 lui t6,0xfffe2 - 4918: f491 bnez s1,4824 <_start-0x7fffb7dc> - 491a: 067e slli a2,a2,0x1f - 491c: 1e1a slli t3,t3,0x26 - 491e: 2540 fld fs0,136(a0) - 4920: 8922 mv s2,s0 - 4922: 1a7f 0x1a7f - 4924: 2440 fld fs0,136(s0) - 4926: 9f22 add t5,t5,s0 - 4928: 0da8 addi a0,sp,728 - 492a: 0000 unimp - 492c: 0db4 addi a3,sp,728 - 492e: 0000 unimp - 4930: 0048 addi a0,sp,4 - 4932: 7f89 lui t6,0xfffe2 - 4934: 8c91 sub s1,s1,a2 - 4936: 067f 0x67f - 4938: 891a mv s2,t1 - 493a: 917f 0x917f - 493c: 7ef4 flw fa3,124(a3) - 493e: 1a06 slli s4,s4,0x21 - 4940: 891e mv s2,t2 - 4942: 1a7f 0x1a7f - 4944: 7f89 lui t6,0xfffe2 - 4946: f491 bnez s1,4852 <_start-0x7fffb7ae> - 4948: 067e slli a2,a2,0x1f - 494a: 911a add sp,sp,t1 - 494c: 7f8c flw fa1,56(a5) - 494e: 4006 0x4006 - 4950: 1e25 addi t3,t3,-23 - 4952: 7f89 lui t6,0xfffe2 - 4954: 8c91 sub s1,s1,a2 - 4956: 067f 0x67f - 4958: 911a add sp,sp,t1 - 495a: 7ef4 flw fa3,124(a3) - 495c: 4006 0x4006 - 495e: 1e25 addi t3,t3,-23 - 4960: 8922 mv s2,s0 - 4962: 917f 0x917f - 4964: 7f8c flw fa1,56(a5) - 4966: 1a06 slli s4,s4,0x21 - 4968: 7f89 lui t6,0xfffe2 - 496a: f491 bnez s1,4876 <_start-0x7fffb78a> - 496c: 067e slli a2,a2,0x1f - 496e: 1e1a slli t3,t3,0x26 - 4970: 2540 fld fs0,136(a0) - 4972: 8922 mv s2,s0 - 4974: 1a7f 0x1a7f - 4976: 2440 fld fs0,136(s0) - 4978: 9f22 add t5,t5,s0 - ... - 4982: 0544 addi s1,sp,644 - 4984: 0000 unimp - 4986: 0674 addi a3,sp,780 - 4988: 0000 unimp - 498a: 0001 nop - 498c: 00078c63 beqz a5,49a4 <_start-0x7fffb65c> - 4990: 9000 0x9000 - 4992: 01000007 vlbuff.v v0,(zero),v0.t - 4996: 5e00 lw s0,56(a2) - 4998: 0790 addi a2,sp,960 - 499a: 0000 unimp - 499c: 093c addi a5,sp,152 - 499e: 0000 unimp - 49a0: e8910003 lb zero,-375(sp) - 49a4: 3c7e fld fs8,504(sp) - 49a6: 0009 c.nop 2 - 49a8: 5800 lw s0,48(s0) - 49aa: 000a c.slli zero,0x2 - 49ac: 0100 addi s0,sp,128 - 49ae: 6200 flw fs0,0(a2) - ... - 49b8: 05b4 addi a3,sp,712 - 49ba: 0000 unimp - 49bc: 0694 addi a3,sp,832 - 49be: 0000 unimp - 49c0: 0001 nop - 49c2: 945d srai s0,s0,0x37 - 49c4: 0006 c.slli zero,0x1 - 49c6: ec00 fsw fs0,24(s0) - 49c8: 22000007 vlseg2bu.v v0,(zero) - 49cc: 7b00 flw fs0,48(a4) - 49ce: 8e00 0x8e00 - 49d0: 1e00 addi s0,sp,816 - 49d2: 0089 addi ra,ra,2 - 49d4: 791a flw fs2,164(sp) - 49d6: 7b00 flw fs0,48(a4) - 49d8: 1e00 addi s0,sp,816 - 49da: 0082 c.slli64 ra - 49dc: 008e slli ra,ra,0x3 - 49de: 221e fld ft4,448(sp) - 49e0: 008e007b 0x8e007b - 49e4: 401e 0x401e - 49e6: 2225 jal 4b0e <_start-0x7fffb4f2> - 49e8: 0089 addi ra,ra,2 - 49ea: 401a 0x401a - 49ec: 2224 fld fs1,64(a2) - 49ee: ec9f 0007 7000 0x70000007ec9f - 49f4: 0008 0x8 - 49f6: 0100 addi s0,sp,128 - 49f8: 5a00 lw s0,48(a2) - 49fa: 0870 addi a2,sp,28 - 49fc: 0000 unimp - 49fe: 0894 addi a3,sp,80 - 4a00: 0000 unimp - 4a02: 0022 c.slli zero,0x8 - 4a04: 008d addi ra,ra,3 - 4a06: 8c1e007b 0x8c1e007b - 4a0a: 1a00 addi s0,sp,304 - 4a0c: 0078 addi a4,sp,12 - 4a0e: 821e007b 0x821e007b - 4a12: 8d00 0x8d00 - 4a14: 1e00 addi s0,sp,816 - 4a16: 8d22 mv s10,s0 - 4a18: 7b00 flw fs0,48(a4) - 4a1a: 1e00 addi s0,sp,816 - 4a1c: 2540 fld fs0,136(a0) - 4a1e: 8c22 mv s8,s0 - 4a20: 1a00 addi s0,sp,304 - 4a22: 2440 fld fs0,136(s0) - 4a24: 9f22 add t5,t5,s0 - 4a26: 0894 addi a3,sp,80 - 4a28: 0000 unimp - 4a2a: 08e0 addi s0,sp,92 - 4a2c: 0000 unimp - 4a2e: 0024 addi s1,sp,8 - 4a30: 008d addi ra,ra,3 - 4a32: 0a1e007b 0xa1e007b - 4a36: ffff 0xffff - 4a38: 781a flw fa6,164(sp) - 4a3a: 7b00 flw fs0,48(a4) - 4a3c: 1e00 addi s0,sp,816 - 4a3e: 0082 c.slli64 ra - 4a40: 008d addi ra,ra,3 - 4a42: 221e fld ft4,448(sp) - 4a44: 008d addi ra,ra,3 - 4a46: 401e007b 0x401e007b - 4a4a: 2225 jal 4b72 <_start-0x7fffb48e> - 4a4c: ff0a fsw ft2,188(sp) - 4a4e: 1aff 0x1aff - 4a50: 2440 fld fs0,136(s0) - 4a52: 9f22 add t5,t5,s0 - 4a54: 08e0 addi s0,sp,92 - 4a56: 0000 unimp - 4a58: 08e4 addi s1,sp,92 - 4a5a: 0000 unimp - 4a5c: 0022 c.slli zero,0x8 - 4a5e: 008d addi ra,ra,3 - 4a60: 7a1e007b 0x7a1e007b - 4a64: 1a7f 0x1a7f - 4a66: 0078 addi a4,sp,12 - 4a68: 821e007b 0x821e007b - 4a6c: 8d00 0x8d00 - 4a6e: 1e00 addi s0,sp,816 - 4a70: 8d22 mv s10,s0 - 4a72: 7b00 flw fs0,48(a4) - 4a74: 1e00 addi s0,sp,816 - 4a76: 2540 fld fs0,136(a0) - 4a78: 7a22 flw fs4,40(sp) - 4a7a: 1a7f 0x1a7f - 4a7c: 2440 fld fs0,136(s0) - 4a7e: 9f22 add t5,t5,s0 - 4a80: 08e4 addi s1,sp,92 - 4a82: 0000 unimp - 4a84: 08e8 addi a0,sp,92 - 4a86: 0000 unimp - 4a88: 0024 addi s1,sp,8 - 4a8a: 008d addi ra,ra,3 - 4a8c: 0a1e007b 0xa1e007b - 4a90: ffff 0xffff - 4a92: 781a flw fa6,164(sp) - 4a94: 7b00 flw fs0,48(a4) - 4a96: 1e00 addi s0,sp,816 - 4a98: 0082 c.slli64 ra - 4a9a: 008d addi ra,ra,3 - 4a9c: 221e fld ft4,448(sp) - 4a9e: 008d addi ra,ra,3 - 4aa0: 401e007b 0x401e007b - 4aa4: 2225 jal 4bcc <_start-0x7fffb434> - 4aa6: ff0a fsw ft2,188(sp) - 4aa8: 1aff 0x1aff - 4aaa: 2440 fld fs0,136(s0) - 4aac: 9f22 add t5,t5,s0 - 4aae: 08e8 addi a0,sp,92 - 4ab0: 0000 unimp - 4ab2: 0910 addi a2,sp,144 - 4ab4: 0000 unimp - 4ab6: 0022 c.slli zero,0x8 - 4ab8: 008d addi ra,ra,3 - 4aba: 841e007b 0x841e007b - 4abe: 1a7f 0x1a7f - 4ac0: 0078 addi a4,sp,12 - 4ac2: 821e007b 0x821e007b - 4ac6: 8d00 0x8d00 - 4ac8: 1e00 addi s0,sp,816 - 4aca: 8d22 mv s10,s0 - 4acc: 7b00 flw fs0,48(a4) - 4ace: 1e00 addi s0,sp,816 - 4ad0: 2540 fld fs0,136(a0) - 4ad2: 8422 mv s0,s0 - 4ad4: 1a7f 0x1a7f - 4ad6: 2440 fld fs0,136(s0) - 4ad8: 9f22 add t5,t5,s0 - 4ada: 0910 addi a2,sp,144 - 4adc: 0000 unimp - 4ade: 0920 addi s0,sp,152 - 4ae0: 0000 unimp - 4ae2: 0031 c.nop 12 - 4ae4: 7f84 flw fs1,56(a5) - 4ae6: f491 bnez s1,49f2 <_start-0x7fffb60e> - 4ae8: 067e slli a2,a2,0x1f - 4aea: 8d1a mv s10,t1 - 4aec: 1e00 addi s0,sp,816 - 4aee: 7f84 flw fs1,56(a5) - 4af0: 841a mv s0,t1 - 4af2: 917f 0x917f - 4af4: 7ef4 flw fa3,124(a3) - 4af6: 1a06 slli s4,s4,0x21 - 4af8: 0078 addi a4,sp,12 - 4afa: 821e mv tp,t2 - 4afc: 8d00 0x8d00 - 4afe: 1e00 addi s0,sp,816 - 4b00: 8422 mv s0,s0 - 4b02: 917f 0x917f - 4b04: 7ef4 flw fa3,124(a3) - 4b06: 1a06 slli s4,s4,0x21 - 4b08: 008d addi ra,ra,3 - 4b0a: 401e 0x401e - 4b0c: 2225 jal 4c34 <_start-0x7fffb3cc> - 4b0e: 7f84 flw fs1,56(a5) - 4b10: 401a 0x401a - 4b12: 2224 fld fs1,64(a2) - 4b14: 209f 0009 3400 0x34000009209f - 4b1a: 0009 c.nop 2 - 4b1c: 3500 fld fs0,40(a0) - 4b1e: 8400 0x8400 - 4b20: 917f 0x917f - 4b22: 7ef4 flw fa3,124(a3) - 4b24: 1a06 slli s4,s4,0x21 - 4b26: 008d addi ra,ra,3 - 4b28: 841e mv s0,t2 - 4b2a: 1a7f 0x1a7f - 4b2c: 7f84 flw fs1,56(a5) - 4b2e: f491 bnez s1,4a3a <_start-0x7fffb5c6> - 4b30: 067e slli a2,a2,0x1f - 4b32: 781a flw fa6,164(sp) - 4b34: 1e00 addi s0,sp,816 - 4b36: f491 bnez s1,4a42 <_start-0x7fffb5be> - 4b38: 067e slli a2,a2,0x1f - 4b3a: 2540 fld fs0,136(a0) - 4b3c: 008d addi ra,ra,3 - 4b3e: 221e fld ft4,448(sp) - 4b40: 7f84 flw fs1,56(a5) - 4b42: f491 bnez s1,4a4e <_start-0x7fffb5b2> - 4b44: 067e slli a2,a2,0x1f - 4b46: 8d1a mv s10,t1 - 4b48: 1e00 addi s0,sp,816 - 4b4a: 2540 fld fs0,136(a0) - 4b4c: 8422 mv s0,s0 - 4b4e: 1a7f 0x1a7f - 4b50: 2440 fld fs0,136(s0) - 4b52: 9f22 add t5,t5,s0 - 4b54: 0934 addi a3,sp,152 - 4b56: 0000 unimp - 4b58: 0958 addi a4,sp,148 - 4b5a: 0000 unimp - 4b5c: 0035 c.nop 13 - 4b5e: f491 bnez s1,4a6a <_start-0x7fffb596> - 4b60: 067e slli a2,a2,0x1f - 4b62: 0084 addi s1,sp,64 - 4b64: 8d1a mv s10,t1 - 4b66: 1e00 addi s0,sp,816 - 4b68: 0084 addi s1,sp,64 - 4b6a: 911a add sp,sp,t1 - 4b6c: 7ef4 flw fa3,124(a3) - 4b6e: 8406 mv s0,ra - 4b70: 1a00 addi s0,sp,304 - 4b72: 0078 addi a4,sp,12 - 4b74: 911e add sp,sp,t2 - 4b76: 7ef4 flw fa3,124(a3) - 4b78: 4006 0x4006 - 4b7a: 8d25 xor a0,a0,s1 - 4b7c: 1e00 addi s0,sp,816 - 4b7e: 9122 add sp,sp,s0 - 4b80: 7ef4 flw fa3,124(a3) - 4b82: 8406 mv s0,ra - 4b84: 1a00 addi s0,sp,304 - 4b86: 008d addi ra,ra,3 - 4b88: 401e 0x401e - 4b8a: 2225 jal 4cb2 <_start-0x7fffb34e> - 4b8c: 0084 addi s1,sp,64 - 4b8e: 401a 0x401a - 4b90: 2224 fld fs1,64(a2) - 4b92: 589f 0009 9000 0x90000009589f - 4b98: 0009 c.nop 2 - 4b9a: 3500 fld fs0,40(a0) - 4b9c: 8500 0x8500 - 4b9e: 917f 0x917f - 4ba0: 7ef4 flw fa3,124(a3) - 4ba2: 1a06 slli s4,s4,0x21 - 4ba4: 008d addi ra,ra,3 - 4ba6: 851e mv a0,t2 - 4ba8: 1a7f 0x1a7f - 4baa: 7f85 lui t6,0xfffe1 - 4bac: f491 bnez s1,4ab8 <_start-0x7fffb548> - 4bae: 067e slli a2,a2,0x1f - 4bb0: 781a flw fa6,164(sp) - 4bb2: 1e00 addi s0,sp,816 - 4bb4: f491 bnez s1,4ac0 <_start-0x7fffb540> - 4bb6: 067e slli a2,a2,0x1f - 4bb8: 2540 fld fs0,136(a0) - 4bba: 008d addi ra,ra,3 - 4bbc: 221e fld ft4,448(sp) - 4bbe: 7f85 lui t6,0xfffe1 - 4bc0: f491 bnez s1,4acc <_start-0x7fffb534> - 4bc2: 067e slli a2,a2,0x1f - 4bc4: 8d1a mv s10,t1 - 4bc6: 1e00 addi s0,sp,816 - 4bc8: 2540 fld fs0,136(a0) - 4bca: 8522 mv a0,s0 - 4bcc: 1a7f 0x1a7f - 4bce: 2440 fld fs0,136(s0) - 4bd0: 9f22 add t5,t5,s0 - 4bd2: 0990 addi a2,sp,208 - 4bd4: 0000 unimp - 4bd6: 0a74 addi a3,sp,284 - 4bd8: 0000 unimp - 4bda: 0001 nop - 4bdc: 7460 flw fs0,108(s0) - 4bde: 000a c.slli zero,0x2 - 4be0: c000 sw s0,0(s0) - 4be2: 000a c.slli zero,0x2 - 4be4: 3500 fld fs0,40(a0) - 4be6: 9100 0x9100 - 4be8: 7f84 flw fs1,56(a5) - 4bea: 7906 flw fs2,96(sp) - 4bec: 1a00 addi s0,sp,304 - 4bee: 791e0083 lb ra,1937(t3) - 4bf2: 1a00 addi s0,sp,304 - 4bf4: 8491 srai s1,s1,0x4 - 4bf6: 067f 0x67f - 4bf8: 2540 fld fs0,136(a0) - 4bfa: 911e0083 lb ra,-1775(t3) - 4bfe: 7f84 flw fs1,56(a5) - 4c00: 7906 flw fs2,96(sp) - 4c02: 1a00 addi s0,sp,304 - 4c04: 221e008f 0x221e008f - 4c08: 8491 srai s1,s1,0x4 - 4c0a: 067f 0x67f - 4c0c: 0079 c.nop 30 - 4c0e: 831a mv t1,t1 - 4c10: 1e00 addi s0,sp,816 - 4c12: 2540 fld fs0,136(a0) - 4c14: 7922 flw fs2,40(sp) - 4c16: 1a00 addi s0,sp,304 - 4c18: 2440 fld fs0,136(s0) - 4c1a: 9f22 add t5,t5,s0 - 4c1c: 0ac0 addi s0,sp,340 - 4c1e: 0000 unimp - 4c20: 0ac8 addi a0,sp,340 - 4c22: 0000 unimp - 4c24: 0044 addi s1,sp,4 - 4c26: fc91 bnez s1,4b42 <_start-0x7fffb4be> - 4c28: 067e slli a2,a2,0x1f - 4c2a: 0079 c.nop 30 - 4c2c: 911a add sp,sp,t1 - 4c2e: 7f84 flw fs1,56(a5) - 4c30: 7906 flw fs2,96(sp) - 4c32: 1a00 addi s0,sp,304 - 4c34: 791e flw fs2,228(sp) - 4c36: 1a00 addi s0,sp,304 - 4c38: fc91 bnez s1,4b54 <_start-0x7fffb4ac> - 4c3a: 067e slli a2,a2,0x1f - 4c3c: 0079 c.nop 30 - 4c3e: 911a add sp,sp,t1 - 4c40: 7f84 flw fs1,56(a5) - 4c42: 4006 0x4006 - 4c44: 1e25 addi t3,t3,-23 - 4c46: 8491 srai s1,s1,0x4 - 4c48: 067f 0x67f - 4c4a: 0079 c.nop 30 - 4c4c: 8f1a mv t5,t1 - 4c4e: 1e00 addi s0,sp,816 - 4c50: 9122 add sp,sp,s0 - 4c52: 7efc flw fa5,124(a3) - 4c54: 7906 flw fs2,96(sp) - 4c56: 1a00 addi s0,sp,304 - 4c58: 8491 srai s1,s1,0x4 - 4c5a: 067f 0x67f - 4c5c: 0079 c.nop 30 - 4c5e: 1e1a slli t3,t3,0x26 - 4c60: 2540 fld fs0,136(a0) - 4c62: 7922 flw fs2,40(sp) - 4c64: 1a00 addi s0,sp,304 - 4c66: 2440 fld fs0,136(s0) - 4c68: 9f22 add t5,t5,s0 - 4c6a: 0ac8 addi a0,sp,340 - 4c6c: 0000 unimp - 4c6e: 0ae0 addi s0,sp,348 - 4c70: 0000 unimp - 4c72: 0048 addi a0,sp,4 - 4c74: fc91 bnez s1,4b90 <_start-0x7fffb470> - 4c76: 067e slli a2,a2,0x1f - 4c78: 0079 c.nop 30 - 4c7a: 911a add sp,sp,t1 - 4c7c: 7f84 flw fs1,56(a5) - 4c7e: 7906 flw fs2,96(sp) - 4c80: 1a00 addi s0,sp,304 - 4c82: 791e flw fs2,228(sp) - 4c84: 1a00 addi s0,sp,304 - 4c86: fc91 bnez s1,4ba2 <_start-0x7fffb45e> - 4c88: 067e slli a2,a2,0x1f - 4c8a: 0079 c.nop 30 - 4c8c: 911a add sp,sp,t1 - 4c8e: 7f84 flw fs1,56(a5) - 4c90: 4006 0x4006 - 4c92: 1e25 addi t3,t3,-23 - 4c94: 8491 srai s1,s1,0x4 - 4c96: 067f 0x67f - 4c98: 0079 c.nop 30 - 4c9a: 911a add sp,sp,t1 - 4c9c: 7efc flw fa5,124(a3) - 4c9e: 4006 0x4006 - 4ca0: 1e25 addi t3,t3,-23 - 4ca2: 9122 add sp,sp,s0 - 4ca4: 7efc flw fa5,124(a3) - 4ca6: 7906 flw fs2,96(sp) - 4ca8: 1a00 addi s0,sp,304 - 4caa: 8491 srai s1,s1,0x4 - 4cac: 067f 0x67f - 4cae: 0079 c.nop 30 - 4cb0: 1e1a slli t3,t3,0x26 - 4cb2: 2540 fld fs0,136(a0) - 4cb4: 7922 flw fs2,40(sp) - 4cb6: 1a00 addi s0,sp,304 - 4cb8: 2440 fld fs0,136(s0) - 4cba: 9f22 add t5,t5,s0 - 4cbc: 0ae0 addi s0,sp,348 - 4cbe: 0000 unimp - 4cc0: 0bc4 addi s1,sp,468 - 4cc2: 0000 unimp - 4cc4: 0048 addi a0,sp,4 - 4cc6: 7f89 lui t6,0xfffe2 - 4cc8: fc91 bnez s1,4be4 <_start-0x7fffb41c> - 4cca: 067e slli a2,a2,0x1f - 4ccc: 891a mv s2,t1 - 4cce: 917f 0x917f - 4cd0: 7f84 flw fs1,56(a5) - 4cd2: 1a06 slli s4,s4,0x21 - 4cd4: 891e mv s2,t2 - 4cd6: 1a7f 0x1a7f - 4cd8: 7f89 lui t6,0xfffe2 - 4cda: fc91 bnez s1,4bf6 <_start-0x7fffb40a> - 4cdc: 067e slli a2,a2,0x1f - 4cde: 911a add sp,sp,t1 - 4ce0: 7f84 flw fs1,56(a5) - 4ce2: 4006 0x4006 - 4ce4: 1e25 addi t3,t3,-23 - 4ce6: 7f89 lui t6,0xfffe2 - 4ce8: 8491 srai s1,s1,0x4 - 4cea: 067f 0x67f - 4cec: 911a add sp,sp,t1 - 4cee: 7efc flw fa5,124(a3) - 4cf0: 4006 0x4006 - 4cf2: 1e25 addi t3,t3,-23 - 4cf4: 8922 mv s2,s0 - 4cf6: 917f 0x917f - 4cf8: 7efc flw fa5,124(a3) - 4cfa: 1a06 slli s4,s4,0x21 - 4cfc: 7f89 lui t6,0xfffe2 - 4cfe: 8491 srai s1,s1,0x4 - 4d00: 067f 0x67f - 4d02: 1e1a slli t3,t3,0x26 - 4d04: 2540 fld fs0,136(a0) - 4d06: 8922 mv s2,s0 - 4d08: 1a7f 0x1a7f - 4d0a: 2440 fld fs0,136(s0) - 4d0c: 9f22 add t5,t5,s0 - 4d0e: 0da8 addi a0,sp,728 - 4d10: 0000 unimp - 4d12: 0db4 addi a3,sp,728 - 4d14: 0000 unimp - 4d16: 0048 addi a0,sp,4 - 4d18: 7f89 lui t6,0xfffe2 - 4d1a: fc91 bnez s1,4c36 <_start-0x7fffb3ca> - 4d1c: 067e slli a2,a2,0x1f - 4d1e: 891a mv s2,t1 - 4d20: 917f 0x917f - 4d22: 7f84 flw fs1,56(a5) - 4d24: 1a06 slli s4,s4,0x21 - 4d26: 891e mv s2,t2 - 4d28: 1a7f 0x1a7f - 4d2a: 7f89 lui t6,0xfffe2 - 4d2c: fc91 bnez s1,4c48 <_start-0x7fffb3b8> - 4d2e: 067e slli a2,a2,0x1f - 4d30: 911a add sp,sp,t1 - 4d32: 7f84 flw fs1,56(a5) - 4d34: 4006 0x4006 - 4d36: 1e25 addi t3,t3,-23 - 4d38: 7f89 lui t6,0xfffe2 - 4d3a: 8491 srai s1,s1,0x4 - 4d3c: 067f 0x67f - 4d3e: 911a add sp,sp,t1 - 4d40: 7efc flw fa5,124(a3) - 4d42: 4006 0x4006 - 4d44: 1e25 addi t3,t3,-23 - 4d46: 8922 mv s2,s0 - 4d48: 917f 0x917f - 4d4a: 7efc flw fa5,124(a3) - 4d4c: 1a06 slli s4,s4,0x21 - 4d4e: 7f89 lui t6,0xfffe2 - 4d50: 8491 srai s1,s1,0x4 - 4d52: 067f 0x67f - 4d54: 1e1a slli t3,t3,0x26 - 4d56: 2540 fld fs0,136(a0) - 4d58: 8922 mv s2,s0 - 4d5a: 1a7f 0x1a7f - 4d5c: 2440 fld fs0,136(s0) - 4d5e: 9f22 add t5,t5,s0 - ... - 4d68: 0594 addi a3,sp,704 - 4d6a: 0000 unimp - 4d6c: 0598 addi a4,sp,704 - 4d6e: 0000 unimp - 4d70: 0001 nop - 4d72: 985f 0005 8c00 0x8c000005985f - 4d78: 03000007 vlbuff.v v0,(zero) - 4d7c: 9100 0x9100 - 4d7e: 7ee8 flw fa0,124(a3) - 4d80: 07d4 addi a3,sp,964 - 4d82: 0000 unimp - 4d84: 07d8 addi a4,sp,964 - 4d86: 0000 unimp - 4d88: 0001 nop - 4d8a: d85e sw s7,48(sp) - 4d8c: 74000007 0x74000007 - 4d90: 0009 c.nop 2 - 4d92: 0300 addi s0,sp,384 - 4d94: 9100 0x9100 - 4d96: 7eec flw fa1,124(a3) - 4d98: 0974 addi a3,sp,156 - 4d9a: 0000 unimp - 4d9c: 0bc4 addi s1,sp,468 - 4d9e: 0000 unimp - 4da0: 0001 nop - 4da2: a866 fsd fs9,16(sp) - 4da4: 000d c.nop 3 - 4da6: b400 fsd fs0,40(s0) - 4da8: 000d c.nop 3 - 4daa: 0100 addi s0,sp,128 - 4dac: 6600 flw fs0,8(a2) - ... - 4db6: 0604 addi s1,sp,768 - 4db8: 0000 unimp - 4dba: 06b0 addi a2,sp,840 - 4dbc: 0000 unimp - 4dbe: 0001 nop - 4dc0: b05f 0006 0c00 0xc000006b05f - 4dc6: 22000007 vlseg2bu.v v0,(zero) - 4dca: 8d00 0x8d00 - 4dcc: 7e00 flw fs0,56(a2) - 4dce: 1e00 addi s0,sp,816 - 4dd0: 0089 addi ra,ra,2 - 4dd2: 781a flw fa6,164(sp) - 4dd4: 7e00 flw fs0,56(a2) - 4dd6: 1e00 addi s0,sp,816 - 4dd8: 008d008f 0x8d008f - 4ddc: 221e fld ft4,448(sp) - 4dde: 008d addi ra,ra,3 - 4de0: 007e c.slli zero,0x1f - 4de2: 401e 0x401e - 4de4: 2225 jal 4f0c <_start-0x7fffb0f4> - 4de6: 0089 addi ra,ra,2 - 4de8: 401a 0x401a - 4dea: 2224 fld fs1,64(a2) - 4dec: 0c9f 0007 2000 0x200000070c9f - 4df2: 31000007 vlseg2bff.v v0,(zero),v0.t - 4df6: 9100 0x9100 - 4df8: 7ef0 flw fa2,124(a3) - 4dfa: 8906 mv s2,ra - 4dfc: 1a00 addi s0,sp,304 - 4dfe: 008d addi ra,ra,3 - 4e00: 891e mv s2,t2 - 4e02: 1a00 addi s0,sp,304 - 4e04: f091 bnez s1,4d08 <_start-0x7fffb2f8> - 4e06: 067e slli a2,a2,0x1f - 4e08: 0089 addi ra,ra,2 - 4e0a: 781a flw fa6,164(sp) - 4e0c: 1e00 addi s0,sp,816 - 4e0e: 008d008f 0x8d008f - 4e12: 221e fld ft4,448(sp) - 4e14: f091 bnez s1,4d18 <_start-0x7fffb2e8> - 4e16: 067e slli a2,a2,0x1f - 4e18: 0089 addi ra,ra,2 - 4e1a: 8d1a mv s10,t1 - 4e1c: 1e00 addi s0,sp,816 - 4e1e: 2540 fld fs0,136(a0) - 4e20: 8922 mv s2,s0 - 4e22: 1a00 addi s0,sp,304 - 4e24: 2440 fld fs0,136(s0) - 4e26: 9f22 add t5,t5,s0 - 4e28: 0720 addi s0,sp,904 - 4e2a: 0000 unimp - 4e2c: 0860 addi s0,sp,28 - 4e2e: 0000 unimp - 4e30: 0035 c.nop 13 - 4e32: f091 bnez s1,4d36 <_start-0x7fffb2ca> - 4e34: 067e slli a2,a2,0x1f - 4e36: 0089 addi ra,ra,2 - 4e38: 8d1a mv s10,t1 - 4e3a: 1e00 addi s0,sp,816 - 4e3c: 0089 addi ra,ra,2 - 4e3e: 911a add sp,sp,t1 - 4e40: 7ef0 flw fa2,124(a3) - 4e42: 8906 mv s2,ra - 4e44: 1a00 addi s0,sp,304 - 4e46: 0078 addi a4,sp,12 - 4e48: 911e add sp,sp,t2 - 4e4a: 7ef0 flw fa2,124(a3) - 4e4c: 4006 0x4006 - 4e4e: 8d25 xor a0,a0,s1 - 4e50: 1e00 addi s0,sp,816 - 4e52: 9122 add sp,sp,s0 - 4e54: 7ef0 flw fa2,124(a3) - 4e56: 8906 mv s2,ra - 4e58: 1a00 addi s0,sp,304 - 4e5a: 008d addi ra,ra,3 - 4e5c: 401e 0x401e - 4e5e: 2225 jal 4f86 <_start-0x7fffb07a> - 4e60: 0089 addi ra,ra,2 - 4e62: 401a 0x401a - 4e64: 2224 fld fs1,64(a2) - 4e66: 609f 0008 8400 0x84000008609f - 4e6c: 0008 0x8 - 4e6e: 3500 fld fs0,40(a0) - 4e70: 9100 0x9100 - 4e72: 7ef0 flw fa2,124(a3) - 4e74: 8c06 mv s8,ra - 4e76: 1a00 addi s0,sp,304 - 4e78: 008d addi ra,ra,3 - 4e7a: 8c1e mv s8,t2 - 4e7c: 1a00 addi s0,sp,304 - 4e7e: f091 bnez s1,4d82 <_start-0x7fffb27e> - 4e80: 067e slli a2,a2,0x1f - 4e82: 008c addi a1,sp,64 - 4e84: 781a flw fa6,164(sp) - 4e86: 1e00 addi s0,sp,816 - 4e88: f091 bnez s1,4d8c <_start-0x7fffb274> - 4e8a: 067e slli a2,a2,0x1f - 4e8c: 2540 fld fs0,136(a0) - 4e8e: 008d addi ra,ra,3 - 4e90: 221e fld ft4,448(sp) - 4e92: f091 bnez s1,4d96 <_start-0x7fffb26a> - 4e94: 067e slli a2,a2,0x1f - 4e96: 008c addi a1,sp,64 - 4e98: 8d1a mv s10,t1 - 4e9a: 1e00 addi s0,sp,816 - 4e9c: 2540 fld fs0,136(a0) - 4e9e: 8c22 mv s8,s0 - 4ea0: 1a00 addi s0,sp,304 - 4ea2: 2440 fld fs0,136(s0) - 4ea4: 9f22 add t5,t5,s0 - 4ea6: 0884 addi s1,sp,80 - 4ea8: 0000 unimp - 4eaa: 088c addi a1,sp,80 - 4eac: 0000 unimp - 4eae: 0001 nop - 4eb0: 8c5d or s0,s0,a5 - 4eb2: 0008 0x8 - 4eb4: 9400 0x9400 - 4eb6: 0008 0x8 - 4eb8: 2200 fld fs0,0(a2) - 4eba: 7c00 flw fs0,56(s0) - 4ebc: 8e00 0x8e00 - 4ebe: 1e00 addi s0,sp,816 - 4ec0: 008c addi a1,sp,64 - 4ec2: 791a flw fs2,164(sp) - 4ec4: 7c00 flw fs0,56(s0) - 4ec6: 1e00 addi s0,sp,816 - 4ec8: 008e0077 0x8e0077 - 4ecc: 221e fld ft4,448(sp) - 4ece: 007c addi a5,sp,12 - 4ed0: 008e slli ra,ra,0x3 - 4ed2: 401e 0x401e - 4ed4: 2225 jal 4ffc <_start-0x7fffb004> - 4ed6: 008c addi a1,sp,64 - 4ed8: 401a 0x401a - 4eda: 2224 fld fs1,64(a2) - 4edc: 949f 0008 e000 0xe0000008949f - 4ee2: 0008 0x8 - 4ee4: 2400 fld fs0,8(s0) - 4ee6: 7c00 flw fs0,56(s0) - 4ee8: 8e00 0x8e00 - 4eea: 1e00 addi s0,sp,816 - 4eec: ff0a fsw ft2,188(sp) - 4eee: 1aff 0x1aff - 4ef0: 0079 c.nop 30 - 4ef2: 007c addi a5,sp,12 - 4ef4: 771e flw fa4,228(sp) - 4ef6: 8e00 0x8e00 - 4ef8: 1e00 addi s0,sp,816 - 4efa: 7c22 flw fs8,40(sp) - 4efc: 8e00 0x8e00 - 4efe: 1e00 addi s0,sp,816 - 4f00: 2540 fld fs0,136(a0) - 4f02: 0a22 slli s4,s4,0x8 - 4f04: ffff 0xffff - 4f06: 401a 0x401a - 4f08: 2224 fld fs1,64(a2) - 4f0a: e09f 0008 e400 0xe4000008e09f - 4f10: 0008 0x8 - 4f12: 2200 fld fs0,0(a2) - 4f14: 7c00 flw fs0,56(s0) - 4f16: 8e00 0x8e00 - 4f18: 1e00 addi s0,sp,816 - 4f1a: 7f7a flw ft10,188(sp) - 4f1c: 791a flw fs2,164(sp) - 4f1e: 7c00 flw fs0,56(s0) - 4f20: 1e00 addi s0,sp,816 - 4f22: 008e0077 0x8e0077 - 4f26: 221e fld ft4,448(sp) - 4f28: 007c addi a5,sp,12 - 4f2a: 008e slli ra,ra,0x3 - 4f2c: 401e 0x401e - 4f2e: 2225 jal 5056 <_start-0x7fffafaa> - 4f30: 7f7a flw ft10,188(sp) - 4f32: 401a 0x401a - 4f34: 2224 fld fs1,64(a2) - 4f36: e49f 0008 e800 0xe8000008e49f - 4f3c: 0008 0x8 - 4f3e: 2400 fld fs0,8(s0) - 4f40: 7c00 flw fs0,56(s0) - 4f42: 8e00 0x8e00 - 4f44: 1e00 addi s0,sp,816 - 4f46: ff0a fsw ft2,188(sp) - 4f48: 1aff 0x1aff - 4f4a: 0079 c.nop 30 - 4f4c: 007c addi a5,sp,12 - 4f4e: 771e flw fa4,228(sp) - 4f50: 8e00 0x8e00 - 4f52: 1e00 addi s0,sp,816 - 4f54: 7c22 flw fs8,40(sp) - 4f56: 8e00 0x8e00 - 4f58: 1e00 addi s0,sp,816 - 4f5a: 2540 fld fs0,136(a0) - 4f5c: 0a22 slli s4,s4,0x8 - 4f5e: ffff 0xffff - 4f60: 401a 0x401a - 4f62: 2224 fld fs1,64(a2) - 4f64: e89f 0008 3400 0x34000008e89f - 4f6a: 0009 c.nop 2 - 4f6c: 2200 fld fs0,0(a2) - 4f6e: 7c00 flw fs0,56(s0) - 4f70: 8e00 0x8e00 - 4f72: 1e00 addi s0,sp,816 - 4f74: 7f84 flw fs1,56(a5) - 4f76: 791a flw fs2,164(sp) - 4f78: 7c00 flw fs0,56(s0) - 4f7a: 1e00 addi s0,sp,816 - 4f7c: 008e0077 0x8e0077 - 4f80: 221e fld ft4,448(sp) - 4f82: 007c addi a5,sp,12 - 4f84: 008e slli ra,ra,0x3 - 4f86: 401e 0x401e - 4f88: 2225 jal 50b0 <_start-0x7fffaf50> - 4f8a: 7f84 flw fs1,56(a5) - 4f8c: 401a 0x401a - 4f8e: 2224 fld fs1,64(a2) - 4f90: 349f 0009 5000 0x50000009349f - 4f96: 0009 c.nop 2 - 4f98: 2200 fld fs0,0(a2) - 4f9a: 7c00 flw fs0,56(s0) - 4f9c: 8e00 0x8e00 - 4f9e: 1e00 addi s0,sp,816 - 4fa0: 0084 addi s1,sp,64 - 4fa2: 791a flw fs2,164(sp) - 4fa4: 7c00 flw fs0,56(s0) - 4fa6: 1e00 addi s0,sp,816 - 4fa8: 008e0077 0x8e0077 - 4fac: 221e fld ft4,448(sp) - 4fae: 007c addi a5,sp,12 - 4fb0: 008e slli ra,ra,0x3 - 4fb2: 401e 0x401e - 4fb4: 2225 jal 50dc <_start-0x7fffaf24> - 4fb6: 0084 addi s1,sp,64 - 4fb8: 401a 0x401a - 4fba: 2224 fld fs1,64(a2) - 4fbc: 509f 0009 5800 0x58000009509f - 4fc2: 0009 c.nop 2 - 4fc4: 3100 fld fs0,32(a0) - 4fc6: 9100 0x9100 - 4fc8: 7f84 flw fs1,56(a5) - 4fca: 8406 mv s0,ra - 4fcc: 1a00 addi s0,sp,304 - 4fce: 007c addi a5,sp,12 - 4fd0: 841e mv s0,t2 - 4fd2: 1a00 addi s0,sp,304 - 4fd4: 0079 c.nop 30 - 4fd6: 007c addi a5,sp,12 - 4fd8: 911e add sp,sp,t2 - 4fda: 7f84 flw fs1,56(a5) - 4fdc: 8406 mv s0,ra - 4fde: 1a00 addi s0,sp,304 - 4fe0: 221e0077 0x221e0077 - 4fe4: 8491 srai s1,s1,0x4 - 4fe6: 067f 0x67f - 4fe8: 0084 addi s1,sp,64 - 4fea: 7c1a flw fs8,164(sp) - 4fec: 1e00 addi s0,sp,816 - 4fee: 2540 fld fs0,136(a0) - 4ff0: 8422 mv s0,s0 - 4ff2: 1a00 addi s0,sp,304 - 4ff4: 2440 fld fs0,136(s0) - 4ff6: 9f22 add t5,t5,s0 - 4ff8: 0958 addi a4,sp,148 - 4ffa: 0000 unimp - 4ffc: 095c addi a5,sp,148 - 4ffe: 0000 unimp - 5000: 0031 c.nop 12 - 5002: 7f85 lui t6,0xfffe1 - 5004: 8491 srai s1,s1,0x4 - 5006: 067f 0x67f - 5008: 7c1a flw fs8,164(sp) - 500a: 1e00 addi s0,sp,816 - 500c: 7f85 lui t6,0xfffe1 - 500e: 791a flw fs2,164(sp) - 5010: 7c00 flw fs0,56(s0) - 5012: 1e00 addi s0,sp,816 - 5014: 7f85 lui t6,0xfffe1 - 5016: 8491 srai s1,s1,0x4 - 5018: 067f 0x67f - 501a: 771a flw fa4,164(sp) - 501c: 1e00 addi s0,sp,816 - 501e: 8522 mv a0,s0 - 5020: 917f 0x917f - 5022: 7f84 flw fs1,56(a5) - 5024: 1a06 slli s4,s4,0x21 - 5026: 007c addi a5,sp,12 - 5028: 401e 0x401e - 502a: 2225 jal 5152 <_start-0x7fffaeae> - 502c: 7f85 lui t6,0xfffe1 - 502e: 401a 0x401a - 5030: 2224 fld fs1,64(a2) - 5032: 5c9f 0009 9800 0x980000095c9f - 5038: 0009 c.nop 2 - 503a: 3500 fld fs0,40(a0) - 503c: 8500 0x8500 - 503e: 917f 0x917f - 5040: 7f84 flw fs1,56(a5) - 5042: 1a06 slli s4,s4,0x21 - 5044: 007c addi a5,sp,12 - 5046: 851e mv a0,t2 - 5048: 1a7f 0x1a7f - 504a: 8491 srai s1,s1,0x4 - 504c: 067f 0x67f - 504e: 2540 fld fs0,136(a0) - 5050: 007c addi a5,sp,12 - 5052: 851e mv a0,t2 - 5054: 917f 0x917f - 5056: 7f84 flw fs1,56(a5) - 5058: 1a06 slli s4,s4,0x21 - 505a: 221e0077 0x221e0077 - 505e: 7f85 lui t6,0xfffe1 - 5060: 8491 srai s1,s1,0x4 - 5062: 067f 0x67f - 5064: 7c1a flw fs8,164(sp) - 5066: 1e00 addi s0,sp,816 - 5068: 2540 fld fs0,136(a0) - 506a: 8522 mv a0,s0 - 506c: 1a7f 0x1a7f - 506e: 2440 fld fs0,136(s0) - 5070: 9f22 add t5,t5,s0 - 5072: 0998 addi a4,sp,208 - 5074: 0000 unimp - 5076: 09a8 addi a0,sp,216 - 5078: 0000 unimp - 507a: 0044 addi s1,sp,4 - 507c: 7f85 lui t6,0xfffe1 - 507e: f891 bnez s1,4f92 <_start-0x7fffb06e> - 5080: 067e slli a2,a2,0x1f - 5082: 851a mv a0,t1 - 5084: 917f 0x917f - 5086: 7f84 flw fs1,56(a5) - 5088: 1a06 slli s4,s4,0x21 - 508a: 851e mv a0,t2 - 508c: 1a7f 0x1a7f - 508e: 7f85 lui t6,0xfffe1 - 5090: f891 bnez s1,4fa4 <_start-0x7fffb05c> - 5092: 067e slli a2,a2,0x1f - 5094: 911a add sp,sp,t1 - 5096: 7f84 flw fs1,56(a5) - 5098: 4006 0x4006 - 509a: 1e25 addi t3,t3,-23 - 509c: 7f85 lui t6,0xfffe1 - 509e: 8491 srai s1,s1,0x4 - 50a0: 067f 0x67f - 50a2: 771a flw fa4,164(sp) - 50a4: 1e00 addi s0,sp,816 - 50a6: 8522 mv a0,s0 - 50a8: 917f 0x917f - 50aa: 7ef8 flw fa4,124(a3) - 50ac: 1a06 slli s4,s4,0x21 - 50ae: 7f85 lui t6,0xfffe1 - 50b0: 8491 srai s1,s1,0x4 - 50b2: 067f 0x67f - 50b4: 1e1a slli t3,t3,0x26 - 50b6: 2540 fld fs0,136(a0) - 50b8: 8522 mv a0,s0 - 50ba: 1a7f 0x1a7f - 50bc: 2440 fld fs0,136(s0) - 50be: 9f22 add t5,t5,s0 - 50c0: 09a8 addi a0,sp,216 - 50c2: 0000 unimp - 50c4: 09d0 addi a2,sp,212 - 50c6: 0000 unimp - 50c8: 0048 addi a0,sp,4 - 50ca: 7f85 lui t6,0xfffe1 - 50cc: f891 bnez s1,4fe0 <_start-0x7fffb020> - 50ce: 067e slli a2,a2,0x1f - 50d0: 851a mv a0,t1 - 50d2: 917f 0x917f - 50d4: 7f84 flw fs1,56(a5) - 50d6: 1a06 slli s4,s4,0x21 - 50d8: 851e mv a0,t2 - 50da: 1a7f 0x1a7f - 50dc: 7f85 lui t6,0xfffe1 - 50de: f891 bnez s1,4ff2 <_start-0x7fffb00e> - 50e0: 067e slli a2,a2,0x1f - 50e2: 911a add sp,sp,t1 - 50e4: 7f84 flw fs1,56(a5) - 50e6: 4006 0x4006 - 50e8: 1e25 addi t3,t3,-23 - 50ea: 7f85 lui t6,0xfffe1 - 50ec: 8491 srai s1,s1,0x4 - 50ee: 067f 0x67f - 50f0: 911a add sp,sp,t1 - 50f2: 7ef8 flw fa4,124(a3) - 50f4: 4006 0x4006 - 50f6: 1e25 addi t3,t3,-23 - 50f8: 8522 mv a0,s0 - 50fa: 917f 0x917f - 50fc: 7ef8 flw fa4,124(a3) - 50fe: 1a06 slli s4,s4,0x21 - 5100: 7f85 lui t6,0xfffe1 - 5102: 8491 srai s1,s1,0x4 - 5104: 067f 0x67f - 5106: 1e1a slli t3,t3,0x26 - 5108: 2540 fld fs0,136(a0) - 510a: 8522 mv a0,s0 - 510c: 1a7f 0x1a7f - 510e: 2440 fld fs0,136(s0) - 5110: 9f22 add t5,t5,s0 - 5112: 09d0 addi a2,sp,212 - 5114: 0000 unimp - 5116: 0a7c addi a5,sp,284 - 5118: 0000 unimp - 511a: 0001 nop - 511c: 7c5e flw fs8,244(sp) - 511e: 000a c.slli zero,0x2 - 5120: b400 fsd fs0,40(s0) - 5122: 000a c.slli zero,0x2 - 5124: 3500 fld fs0,40(a0) - 5126: 9100 0x9100 - 5128: 7ef8 flw fa4,124(a3) - 512a: 7906 flw fs2,96(sp) - 512c: 1a00 addi s0,sp,304 - 512e: 0076 c.slli zero,0x1d - 5130: 791e flw fs2,228(sp) - 5132: 1a00 addi s0,sp,304 - 5134: f891 bnez s1,5048 <_start-0x7fffafb8> - 5136: 067e slli a2,a2,0x1f - 5138: 0079 c.nop 30 - 513a: 751a flw fa0,164(sp) - 513c: 1e00 addi s0,sp,816 - 513e: f891 bnez s1,5052 <_start-0x7fffafae> - 5140: 067e slli a2,a2,0x1f - 5142: 2540 fld fs0,136(a0) - 5144: 0076 c.slli zero,0x1d - 5146: 221e fld ft4,448(sp) - 5148: f891 bnez s1,505c <_start-0x7fffafa4> - 514a: 067e slli a2,a2,0x1f - 514c: 0079 c.nop 30 - 514e: 761a flw fa2,164(sp) - 5150: 1e00 addi s0,sp,816 - 5152: 2540 fld fs0,136(a0) - 5154: 7922 flw fs2,40(sp) - 5156: 1a00 addi s0,sp,304 - 5158: 2440 fld fs0,136(s0) - 515a: 9f22 add t5,t5,s0 - 515c: 0ab4 addi a3,sp,344 - 515e: 0000 unimp - 5160: 0acc addi a1,sp,340 - 5162: 0000 unimp - 5164: 0044 addi s1,sp,4 - 5166: f891 bnez s1,507a <_start-0x7fffaf86> - 5168: 067e slli a2,a2,0x1f - 516a: 0079 c.nop 30 - 516c: 911a add sp,sp,t1 - 516e: 7f8c flw fa1,56(a5) - 5170: 7906 flw fs2,96(sp) - 5172: 1a00 addi s0,sp,304 - 5174: 791e flw fs2,228(sp) - 5176: 1a00 addi s0,sp,304 - 5178: f891 bnez s1,508c <_start-0x7fffaf74> - 517a: 067e slli a2,a2,0x1f - 517c: 0079 c.nop 30 - 517e: 751a flw fa0,164(sp) - 5180: 1e00 addi s0,sp,816 - 5182: 8c91 sub s1,s1,a2 - 5184: 067f 0x67f - 5186: 0079 c.nop 30 - 5188: 911a add sp,sp,t1 - 518a: 7ef8 flw fa4,124(a3) - 518c: 4006 0x4006 - 518e: 1e25 addi t3,t3,-23 - 5190: 9122 add sp,sp,s0 - 5192: 7ef8 flw fa4,124(a3) - 5194: 7906 flw fs2,96(sp) - 5196: 1a00 addi s0,sp,304 - 5198: 8c91 sub s1,s1,a2 - 519a: 067f 0x67f - 519c: 0079 c.nop 30 - 519e: 1e1a slli t3,t3,0x26 - 51a0: 2540 fld fs0,136(a0) - 51a2: 7922 flw fs2,40(sp) - 51a4: 1a00 addi s0,sp,304 - 51a6: 2440 fld fs0,136(s0) - 51a8: 9f22 add t5,t5,s0 - 51aa: 0acc addi a1,sp,340 - 51ac: 0000 unimp - 51ae: 0ae0 addi s0,sp,348 - 51b0: 0000 unimp - 51b2: 0048 addi a0,sp,4 - 51b4: f891 bnez s1,50c8 <_start-0x7fffaf38> - 51b6: 067e slli a2,a2,0x1f - 51b8: 0079 c.nop 30 - 51ba: 911a add sp,sp,t1 - 51bc: 7f8c flw fa1,56(a5) - 51be: 7906 flw fs2,96(sp) - 51c0: 1a00 addi s0,sp,304 - 51c2: 791e flw fs2,228(sp) - 51c4: 1a00 addi s0,sp,304 - 51c6: f891 bnez s1,50da <_start-0x7fffaf26> - 51c8: 067e slli a2,a2,0x1f - 51ca: 0079 c.nop 30 - 51cc: 911a add sp,sp,t1 - 51ce: 7f8c flw fa1,56(a5) - 51d0: 4006 0x4006 - 51d2: 1e25 addi t3,t3,-23 - 51d4: 8c91 sub s1,s1,a2 - 51d6: 067f 0x67f - 51d8: 0079 c.nop 30 - 51da: 911a add sp,sp,t1 - 51dc: 7ef8 flw fa4,124(a3) - 51de: 4006 0x4006 - 51e0: 1e25 addi t3,t3,-23 - 51e2: 9122 add sp,sp,s0 - 51e4: 7ef8 flw fa4,124(a3) - 51e6: 7906 flw fs2,96(sp) - 51e8: 1a00 addi s0,sp,304 - 51ea: 8c91 sub s1,s1,a2 - 51ec: 067f 0x67f - 51ee: 0079 c.nop 30 - 51f0: 1e1a slli t3,t3,0x26 - 51f2: 2540 fld fs0,136(a0) - 51f4: 7922 flw fs2,40(sp) - 51f6: 1a00 addi s0,sp,304 - 51f8: 2440 fld fs0,136(s0) - 51fa: 9f22 add t5,t5,s0 - 51fc: 0ae0 addi s0,sp,348 - 51fe: 0000 unimp - 5200: 0bc4 addi s1,sp,468 - 5202: 0000 unimp - 5204: 0048 addi a0,sp,4 - 5206: 7f89 lui t6,0xfffe2 - 5208: f891 bnez s1,511c <_start-0x7fffaee4> - 520a: 067e slli a2,a2,0x1f - 520c: 891a mv s2,t1 - 520e: 917f 0x917f - 5210: 7f8c flw fa1,56(a5) - 5212: 1a06 slli s4,s4,0x21 - 5214: 891e mv s2,t2 - 5216: 1a7f 0x1a7f - 5218: 7f89 lui t6,0xfffe2 - 521a: f891 bnez s1,512e <_start-0x7fffaed2> - 521c: 067e slli a2,a2,0x1f - 521e: 911a add sp,sp,t1 - 5220: 7f8c flw fa1,56(a5) - 5222: 4006 0x4006 - 5224: 1e25 addi t3,t3,-23 - 5226: 7f89 lui t6,0xfffe2 - 5228: 8c91 sub s1,s1,a2 - 522a: 067f 0x67f - 522c: 911a add sp,sp,t1 - 522e: 7ef8 flw fa4,124(a3) - 5230: 4006 0x4006 - 5232: 1e25 addi t3,t3,-23 - 5234: 8922 mv s2,s0 - 5236: 917f 0x917f - 5238: 7ef8 flw fa4,124(a3) - 523a: 1a06 slli s4,s4,0x21 - 523c: 7f89 lui t6,0xfffe2 - 523e: 8c91 sub s1,s1,a2 - 5240: 067f 0x67f - 5242: 1e1a slli t3,t3,0x26 - 5244: 2540 fld fs0,136(a0) - 5246: 8922 mv s2,s0 - 5248: 1a7f 0x1a7f - 524a: 2440 fld fs0,136(s0) - 524c: 9f22 add t5,t5,s0 - 524e: 0da8 addi a0,sp,728 - 5250: 0000 unimp - 5252: 0db4 addi a3,sp,728 - 5254: 0000 unimp - 5256: 0048 addi a0,sp,4 - 5258: 7f89 lui t6,0xfffe2 - 525a: f891 bnez s1,516e <_start-0x7fffae92> - 525c: 067e slli a2,a2,0x1f - 525e: 891a mv s2,t1 - 5260: 917f 0x917f - 5262: 7f8c flw fa1,56(a5) - 5264: 1a06 slli s4,s4,0x21 - 5266: 891e mv s2,t2 - 5268: 1a7f 0x1a7f - 526a: 7f89 lui t6,0xfffe2 - 526c: f891 bnez s1,5180 <_start-0x7fffae80> - 526e: 067e slli a2,a2,0x1f - 5270: 911a add sp,sp,t1 - 5272: 7f8c flw fa1,56(a5) - 5274: 4006 0x4006 - 5276: 1e25 addi t3,t3,-23 - 5278: 7f89 lui t6,0xfffe2 - 527a: 8c91 sub s1,s1,a2 - 527c: 067f 0x67f - 527e: 911a add sp,sp,t1 - 5280: 7ef8 flw fa4,124(a3) - 5282: 4006 0x4006 - 5284: 1e25 addi t3,t3,-23 - 5286: 8922 mv s2,s0 - 5288: 917f 0x917f - 528a: 7ef8 flw fa4,124(a3) - 528c: 1a06 slli s4,s4,0x21 - 528e: 7f89 lui t6,0xfffe2 - 5290: 8c91 sub s1,s1,a2 - 5292: 067f 0x67f - 5294: 1e1a slli t3,t3,0x26 - 5296: 2540 fld fs0,136(a0) - 5298: 8922 mv s2,s0 - 529a: 1a7f 0x1a7f - 529c: 2440 fld fs0,136(s0) - 529e: 9f22 add t5,t5,s0 - ... - 52a8: 05e8 addi a0,sp,716 - 52aa: 0000 unimp - 52ac: 05ec addi a1,sp,716 - 52ae: 0000 unimp - 52b0: 0001 nop - 52b2: ec5f 0005 d400 0xd4000005ec5f - 52b8: 03000007 vlbuff.v v0,(zero) - 52bc: 9100 0x9100 - 52be: 7eec flw fa1,124(a3) - 52c0: 0884 addi s1,sp,80 - 52c2: 0000 unimp - 52c4: 09c0 addi s0,sp,212 - 52c6: 0000 unimp - 52c8: 0001 nop - 52ca: 0009c067 0x9c067 - 52ce: 8800 0x8800 - 52d0: 000a c.slli zero,0x2 - 52d2: 0100 addi s0,sp,128 - 52d4: 5700 lw s0,40(a4) - ... - 52de: 0658 addi a4,sp,772 - 52e0: 0000 unimp - 52e2: 06c8 addi a0,sp,836 - 52e4: 0000 unimp - 52e6: 0001 nop - 52e8: c861 beqz s0,53b8 <_start-0x7fffac48> - 52ea: 0006 c.slli zero,0x1 - 52ec: e000 fsw fs0,0(s0) - 52ee: 0006 c.slli zero,0x1 - 52f0: 1d00 addi s0,sp,688 - 52f2: 7c00 flw fs0,56(s0) - 52f4: 8c00 0x8c00 - 52f6: 1e00 addi s0,sp,816 - 52f8: 0089 addi ra,ra,2 - 52fa: 851a mv a0,t1 - 52fc: 7c00 flw fs0,56(s0) - 52fe: 1e00 addi s0,sp,816 - 5300: 008c0077 0x8c0077 - 5304: 221e fld ft4,448(sp) - 5306: 008a slli ra,ra,0x2 - 5308: 8922 mv s2,s0 - 530a: 1a00 addi s0,sp,304 - 530c: 2440 fld fs0,136(s0) - 530e: 9f22 add t5,t5,s0 - 5310: 06e0 addi s0,sp,844 - 5312: 0000 unimp - 5314: 0764 addi s1,sp,908 - 5316: 0000 unimp - 5318: 0022 c.slli zero,0x8 - 531a: 007c addi a5,sp,12 - 531c: 008c addi a1,sp,64 - 531e: 891e mv s2,t2 - 5320: 1a00 addi s0,sp,304 - 5322: 0085 addi ra,ra,1 - 5324: 007c addi a5,sp,12 - 5326: 771e flw fa4,228(sp) - 5328: 8c00 0x8c00 - 532a: 1e00 addi s0,sp,816 - 532c: 7c22 flw fs8,40(sp) - 532e: 8c00 0x8c00 - 5330: 1e00 addi s0,sp,816 - 5332: 2540 fld fs0,136(a0) - 5334: 8922 mv s2,s0 - 5336: 1a00 addi s0,sp,304 - 5338: 2440 fld fs0,136(s0) - 533a: 9f22 add t5,t5,s0 - 533c: 0764 addi s1,sp,908 - 533e: 0000 unimp - 5340: 076c addi a1,sp,908 - 5342: 0000 unimp - 5344: 0026 c.slli zero,0x9 - 5346: 007c addi a5,sp,12 - 5348: 008c addi a1,sp,64 - 534a: 891e mv s2,t2 - 534c: 1a00 addi s0,sp,304 - 534e: 8091 srli s1,s1,0x4 - 5350: 067f 0x67f - 5352: 2540 fld fs0,136(a0) - 5354: 007c addi a5,sp,12 - 5356: 771e flw fa4,228(sp) - 5358: 8c00 0x8c00 - 535a: 1e00 addi s0,sp,816 - 535c: 7c22 flw fs8,40(sp) - 535e: 8c00 0x8c00 - 5360: 1e00 addi s0,sp,816 - 5362: 2540 fld fs0,136(a0) - 5364: 8922 mv s2,s0 - 5366: 1a00 addi s0,sp,304 - 5368: 2440 fld fs0,136(s0) - 536a: 9f22 add t5,t5,s0 - 536c: 076c addi a1,sp,908 - 536e: 0000 unimp - 5370: 0860 addi s0,sp,28 - 5372: 0000 unimp - 5374: 0035 c.nop 13 - 5376: 8091 srli s1,s1,0x4 - 5378: 067f 0x67f - 537a: 0089 addi ra,ra,2 - 537c: 7c1a flw fs8,164(sp) - 537e: 1e00 addi s0,sp,816 - 5380: 0089 addi ra,ra,2 - 5382: 911a add sp,sp,t1 - 5384: 7f80 flw fs0,56(a5) - 5386: 4006 0x4006 - 5388: 7c25 lui s8,0xfffe9 - 538a: 1e00 addi s0,sp,816 - 538c: 8091 srli s1,s1,0x4 - 538e: 067f 0x67f - 5390: 0089 addi ra,ra,2 - 5392: 771a flw fa4,164(sp) - 5394: 1e00 addi s0,sp,816 - 5396: 9122 add sp,sp,s0 - 5398: 7f80 flw fs0,56(a5) - 539a: 8906 mv s2,ra - 539c: 1a00 addi s0,sp,304 - 539e: 007c addi a5,sp,12 - 53a0: 401e 0x401e - 53a2: 2225 jal 54ca <_start-0x7fffab36> - 53a4: 0089 addi ra,ra,2 - 53a6: 401a 0x401a - 53a8: 2224 fld fs1,64(a2) - 53aa: 609f 0008 9400 0x94000008609f - 53b0: 0008 0x8 - 53b2: 3500 fld fs0,40(a0) - 53b4: 9100 0x9100 - 53b6: 7f80 flw fs0,56(a5) - 53b8: 8c06 mv s8,ra - 53ba: 1a00 addi s0,sp,304 - 53bc: 007c addi a5,sp,12 - 53be: 8c1e mv s8,t2 - 53c0: 1a00 addi s0,sp,304 - 53c2: 8091 srli s1,s1,0x4 - 53c4: 067f 0x67f - 53c6: 2540 fld fs0,136(a0) - 53c8: 007c addi a5,sp,12 - 53ca: 911e add sp,sp,t2 - 53cc: 7f80 flw fs0,56(a5) - 53ce: 8c06 mv s8,ra - 53d0: 1a00 addi s0,sp,304 - 53d2: 221e0077 0x221e0077 - 53d6: 8091 srli s1,s1,0x4 - 53d8: 067f 0x67f - 53da: 008c addi a1,sp,64 - 53dc: 7c1a flw fs8,164(sp) - 53de: 1e00 addi s0,sp,816 - 53e0: 2540 fld fs0,136(a0) - 53e2: 8c22 mv s8,s0 - 53e4: 1a00 addi s0,sp,304 - 53e6: 2440 fld fs0,136(s0) - 53e8: 9f22 add t5,t5,s0 - 53ea: 0894 addi a3,sp,80 - 53ec: 0000 unimp - 53ee: 08e0 addi s0,sp,92 - 53f0: 0000 unimp - 53f2: 003a c.slli zero,0xe - 53f4: 8091 srli s1,s1,0x4 - 53f6: 067f 0x67f - 53f8: ff0a fsw ft2,188(sp) - 53fa: 1aff 0x1aff - 53fc: 007c addi a5,sp,12 - 53fe: 0a1e slli s4,s4,0x7 - 5400: ffff 0xffff - 5402: 911a add sp,sp,t1 - 5404: 7f80 flw fs0,56(a5) - 5406: 4006 0x4006 - 5408: 7c25 lui s8,0xfffe9 - 540a: 1e00 addi s0,sp,816 - 540c: 8091 srli s1,s1,0x4 - 540e: 067f 0x67f - 5410: ff0a fsw ft2,188(sp) - 5412: 1aff 0x1aff - 5414: 221e0077 0x221e0077 - 5418: 8091 srli s1,s1,0x4 - 541a: 067f 0x67f - 541c: ff0a fsw ft2,188(sp) - 541e: 1aff 0x1aff - 5420: 007c addi a5,sp,12 - 5422: 401e 0x401e - 5424: 2225 jal 554c <_start-0x7fffaab4> - 5426: ff0a fsw ft2,188(sp) - 5428: 1aff 0x1aff - 542a: 2440 fld fs0,136(s0) - 542c: 9f22 add t5,t5,s0 - 542e: 08e0 addi s0,sp,92 - 5430: 0000 unimp - 5432: 08e4 addi s1,sp,92 - 5434: 0000 unimp - 5436: 0035 c.nop 13 - 5438: 7f7a flw ft10,188(sp) - 543a: 8091 srli s1,s1,0x4 - 543c: 067f 0x67f - 543e: 7c1a flw fs8,164(sp) - 5440: 1e00 addi s0,sp,816 - 5442: 7f7a flw ft10,188(sp) - 5444: 911a add sp,sp,t1 - 5446: 7f80 flw fs0,56(a5) - 5448: 4006 0x4006 - 544a: 7c25 lui s8,0xfffe9 - 544c: 1e00 addi s0,sp,816 - 544e: 7f7a flw ft10,188(sp) - 5450: 8091 srli s1,s1,0x4 - 5452: 067f 0x67f - 5454: 771a flw fa4,164(sp) - 5456: 1e00 addi s0,sp,816 - 5458: 7a22 flw fs4,40(sp) - 545a: 917f 0x917f - 545c: 7f80 flw fs0,56(a5) - 545e: 1a06 slli s4,s4,0x21 - 5460: 007c addi a5,sp,12 - 5462: 401e 0x401e - 5464: 2225 jal 558c <_start-0x7fffaa74> - 5466: 7f7a flw ft10,188(sp) - 5468: 401a 0x401a - 546a: 2224 fld fs1,64(a2) - 546c: e49f 0008 e800 0xe8000008e49f - 5472: 0008 0x8 - 5474: 3a00 fld fs0,48(a2) - 5476: 9100 0x9100 - 5478: 7f80 flw fs0,56(a5) - 547a: 0a06 slli s4,s4,0x1 - 547c: ffff 0xffff - 547e: 7c1a flw fs8,164(sp) - 5480: 1e00 addi s0,sp,816 - 5482: ff0a fsw ft2,188(sp) - 5484: 1aff 0x1aff - 5486: 8091 srli s1,s1,0x4 - 5488: 067f 0x67f - 548a: 2540 fld fs0,136(a0) - 548c: 007c addi a5,sp,12 - 548e: 911e add sp,sp,t2 - 5490: 7f80 flw fs0,56(a5) - 5492: 0a06 slli s4,s4,0x1 - 5494: ffff 0xffff - 5496: 771a flw fa4,164(sp) - 5498: 1e00 addi s0,sp,816 - 549a: 9122 add sp,sp,s0 - 549c: 7f80 flw fs0,56(a5) - 549e: 0a06 slli s4,s4,0x1 - 54a0: ffff 0xffff - 54a2: 7c1a flw fs8,164(sp) - 54a4: 1e00 addi s0,sp,816 - 54a6: 2540 fld fs0,136(a0) - 54a8: 0a22 slli s4,s4,0x8 - 54aa: ffff 0xffff - 54ac: 401a 0x401a - 54ae: 2224 fld fs1,64(a2) - 54b0: e89f 0008 3400 0x34000008e89f - 54b6: 0009 c.nop 2 - 54b8: 3500 fld fs0,40(a0) - 54ba: 8400 0x8400 - 54bc: 917f 0x917f - 54be: 7f80 flw fs0,56(a5) - 54c0: 1a06 slli s4,s4,0x21 - 54c2: 007c addi a5,sp,12 - 54c4: 841e mv s0,t2 - 54c6: 1a7f 0x1a7f - 54c8: 8091 srli s1,s1,0x4 - 54ca: 067f 0x67f - 54cc: 2540 fld fs0,136(a0) - 54ce: 007c addi a5,sp,12 - 54d0: 841e mv s0,t2 - 54d2: 917f 0x917f - 54d4: 7f80 flw fs0,56(a5) - 54d6: 1a06 slli s4,s4,0x21 - 54d8: 221e0077 0x221e0077 - 54dc: 7f84 flw fs1,56(a5) - 54de: 8091 srli s1,s1,0x4 - 54e0: 067f 0x67f - 54e2: 7c1a flw fs8,164(sp) - 54e4: 1e00 addi s0,sp,816 - 54e6: 2540 fld fs0,136(a0) - 54e8: 8422 mv s0,s0 - 54ea: 1a7f 0x1a7f - 54ec: 2440 fld fs0,136(s0) - 54ee: 9f22 add t5,t5,s0 - 54f0: 0934 addi a3,sp,152 - 54f2: 0000 unimp - 54f4: 0958 addi a4,sp,148 - 54f6: 0000 unimp - 54f8: 0035 c.nop 13 - 54fa: 8091 srli s1,s1,0x4 - 54fc: 067f 0x67f - 54fe: 0084 addi s1,sp,64 - 5500: 7c1a flw fs8,164(sp) - 5502: 1e00 addi s0,sp,816 - 5504: 0084 addi s1,sp,64 - 5506: 911a add sp,sp,t1 - 5508: 7f80 flw fs0,56(a5) - 550a: 4006 0x4006 - 550c: 7c25 lui s8,0xfffe9 - 550e: 1e00 addi s0,sp,816 - 5510: 8091 srli s1,s1,0x4 - 5512: 067f 0x67f - 5514: 0084 addi s1,sp,64 - 5516: 771a flw fa4,164(sp) - 5518: 1e00 addi s0,sp,816 - 551a: 9122 add sp,sp,s0 - 551c: 7f80 flw fs0,56(a5) - 551e: 8406 mv s0,ra - 5520: 1a00 addi s0,sp,304 - 5522: 007c addi a5,sp,12 - 5524: 401e 0x401e - 5526: 2225 jal 564e <_start-0x7fffa9b2> - 5528: 0084 addi s1,sp,64 - 552a: 401a 0x401a - 552c: 2224 fld fs1,64(a2) - 552e: 589f 0009 9800 0x98000009589f - 5534: 0009 c.nop 2 - 5536: 3500 fld fs0,40(a0) - 5538: 8500 0x8500 - 553a: 917f 0x917f - 553c: 7f80 flw fs0,56(a5) - 553e: 1a06 slli s4,s4,0x21 - 5540: 007c addi a5,sp,12 - 5542: 851e mv a0,t2 - 5544: 1a7f 0x1a7f - 5546: 8091 srli s1,s1,0x4 - 5548: 067f 0x67f - 554a: 2540 fld fs0,136(a0) - 554c: 007c addi a5,sp,12 - 554e: 851e mv a0,t2 - 5550: 917f 0x917f - 5552: 7f80 flw fs0,56(a5) - 5554: 1a06 slli s4,s4,0x21 - 5556: 221e0077 0x221e0077 - 555a: 7f85 lui t6,0xfffe1 - 555c: 8091 srli s1,s1,0x4 - 555e: 067f 0x67f - 5560: 7c1a flw fs8,164(sp) - 5562: 1e00 addi s0,sp,816 - 5564: 2540 fld fs0,136(a0) - 5566: 8522 mv a0,s0 - 5568: 1a7f 0x1a7f - 556a: 2440 fld fs0,136(s0) - 556c: 9f22 add t5,t5,s0 - 556e: 0998 addi a4,sp,208 - 5570: 0000 unimp - 5572: 09a8 addi a0,sp,216 - 5574: 0000 unimp - 5576: 0044 addi s1,sp,4 - 5578: 7f85 lui t6,0xfffe1 - 557a: f891 bnez s1,548e <_start-0x7fffab72> - 557c: 067e slli a2,a2,0x1f - 557e: 851a mv a0,t1 - 5580: 917f 0x917f - 5582: 7f80 flw fs0,56(a5) - 5584: 1a06 slli s4,s4,0x21 - 5586: 851e mv a0,t2 - 5588: 1a7f 0x1a7f - 558a: 7f85 lui t6,0xfffe1 - 558c: f891 bnez s1,54a0 <_start-0x7fffab60> - 558e: 067e slli a2,a2,0x1f - 5590: 911a add sp,sp,t1 - 5592: 7f80 flw fs0,56(a5) - 5594: 4006 0x4006 - 5596: 1e25 addi t3,t3,-23 - 5598: 7f85 lui t6,0xfffe1 - 559a: 8091 srli s1,s1,0x4 - 559c: 067f 0x67f - 559e: 771a flw fa4,164(sp) - 55a0: 1e00 addi s0,sp,816 - 55a2: 8522 mv a0,s0 - 55a4: 917f 0x917f - 55a6: 7ef8 flw fa4,124(a3) - 55a8: 1a06 slli s4,s4,0x21 - 55aa: 7f85 lui t6,0xfffe1 - 55ac: 8091 srli s1,s1,0x4 - 55ae: 067f 0x67f - 55b0: 1e1a slli t3,t3,0x26 - 55b2: 2540 fld fs0,136(a0) - 55b4: 8522 mv a0,s0 - 55b6: 1a7f 0x1a7f - 55b8: 2440 fld fs0,136(s0) - 55ba: 9f22 add t5,t5,s0 - 55bc: 09a8 addi a0,sp,216 - 55be: 0000 unimp - 55c0: 09e0 addi s0,sp,220 - 55c2: 0000 unimp - 55c4: 0048 addi a0,sp,4 - 55c6: 7f85 lui t6,0xfffe1 - 55c8: f891 bnez s1,54dc <_start-0x7fffab24> - 55ca: 067e slli a2,a2,0x1f - 55cc: 851a mv a0,t1 - 55ce: 917f 0x917f - 55d0: 7f80 flw fs0,56(a5) - 55d2: 1a06 slli s4,s4,0x21 - 55d4: 851e mv a0,t2 - 55d6: 1a7f 0x1a7f - 55d8: 7f85 lui t6,0xfffe1 - 55da: f891 bnez s1,54ee <_start-0x7fffab12> - 55dc: 067e slli a2,a2,0x1f - 55de: 911a add sp,sp,t1 - 55e0: 7f80 flw fs0,56(a5) - 55e2: 4006 0x4006 - 55e4: 1e25 addi t3,t3,-23 - 55e6: 7f85 lui t6,0xfffe1 - 55e8: 8091 srli s1,s1,0x4 - 55ea: 067f 0x67f - 55ec: 911a add sp,sp,t1 - 55ee: 7ef8 flw fa4,124(a3) - 55f0: 4006 0x4006 - 55f2: 1e25 addi t3,t3,-23 - 55f4: 8522 mv a0,s0 - 55f6: 917f 0x917f - 55f8: 7ef8 flw fa4,124(a3) - 55fa: 1a06 slli s4,s4,0x21 - 55fc: 7f85 lui t6,0xfffe1 - 55fe: 8091 srli s1,s1,0x4 - 5600: 067f 0x67f - 5602: 1e1a slli t3,t3,0x26 - 5604: 2540 fld fs0,136(a0) - 5606: 8522 mv a0,s0 - 5608: 1a7f 0x1a7f - 560a: 2440 fld fs0,136(s0) - 560c: 9f22 add t5,t5,s0 - 560e: 09e0 addi s0,sp,220 - 5610: 0000 unimp - 5612: 09ec addi a1,sp,220 - 5614: 0000 unimp - 5616: 0048 addi a0,sp,4 - 5618: f891 bnez s1,552c <_start-0x7fffaad4> - 561a: 067e slli a2,a2,0x1f - 561c: 0079 c.nop 30 - 561e: 911a add sp,sp,t1 - 5620: 7f80 flw fs0,56(a5) - 5622: 7906 flw fs2,96(sp) - 5624: 1a00 addi s0,sp,304 - 5626: 791e flw fs2,228(sp) - 5628: 1a00 addi s0,sp,304 - 562a: f891 bnez s1,553e <_start-0x7fffaac2> - 562c: 067e slli a2,a2,0x1f - 562e: 0079 c.nop 30 - 5630: 911a add sp,sp,t1 - 5632: 7f80 flw fs0,56(a5) - 5634: 4006 0x4006 - 5636: 1e25 addi t3,t3,-23 - 5638: 8091 srli s1,s1,0x4 - 563a: 067f 0x67f - 563c: 0079 c.nop 30 - 563e: 911a add sp,sp,t1 - 5640: 7ef8 flw fa4,124(a3) - 5642: 4006 0x4006 - 5644: 1e25 addi t3,t3,-23 - 5646: 9122 add sp,sp,s0 - 5648: 7ef8 flw fa4,124(a3) - 564a: 7906 flw fs2,96(sp) - 564c: 1a00 addi s0,sp,304 - 564e: 8091 srli s1,s1,0x4 - 5650: 067f 0x67f - 5652: 0079 c.nop 30 - 5654: 1e1a slli t3,t3,0x26 - 5656: 2540 fld fs0,136(a0) - 5658: 7922 flw fs2,40(sp) - 565a: 1a00 addi s0,sp,304 - 565c: 2440 fld fs0,136(s0) - 565e: 9f22 add t5,t5,s0 - 5660: 09ec addi a1,sp,220 - 5662: 0000 unimp - 5664: 0a28 addi a0,sp,280 - 5666: 0000 unimp - 5668: 0048 addi a0,sp,4 - 566a: 7f84 flw fs1,56(a5) - 566c: f891 bnez s1,5580 <_start-0x7fffaa80> - 566e: 067e slli a2,a2,0x1f - 5670: 841a mv s0,t1 - 5672: 917f 0x917f - 5674: 7f80 flw fs0,56(a5) - 5676: 1a06 slli s4,s4,0x21 - 5678: 841e mv s0,t2 - 567a: 1a7f 0x1a7f - 567c: 7f84 flw fs1,56(a5) - 567e: f891 bnez s1,5592 <_start-0x7fffaa6e> - 5680: 067e slli a2,a2,0x1f - 5682: 911a add sp,sp,t1 - 5684: 7f80 flw fs0,56(a5) - 5686: 4006 0x4006 - 5688: 1e25 addi t3,t3,-23 - 568a: 7f84 flw fs1,56(a5) - 568c: 8091 srli s1,s1,0x4 - 568e: 067f 0x67f - 5690: 911a add sp,sp,t1 - 5692: 7ef8 flw fa4,124(a3) - 5694: 4006 0x4006 - 5696: 1e25 addi t3,t3,-23 - 5698: 8422 mv s0,s0 - 569a: 917f 0x917f - 569c: 7ef8 flw fa4,124(a3) - 569e: 1a06 slli s4,s4,0x21 - 56a0: 7f84 flw fs1,56(a5) - 56a2: 8091 srli s1,s1,0x4 - 56a4: 067f 0x67f - 56a6: 1e1a slli t3,t3,0x26 - 56a8: 2540 fld fs0,136(a0) - 56aa: 8422 mv s0,s0 - 56ac: 1a7f 0x1a7f - 56ae: 2440 fld fs0,136(s0) - 56b0: 9f22 add t5,t5,s0 - 56b2: 0a28 addi a0,sp,280 - 56b4: 0000 unimp - 56b6: 0a98 addi a4,sp,336 - 56b8: 0000 unimp - 56ba: 0001 nop - 56bc: 985c 0x985c - 56be: 000a c.slli zero,0x2 - 56c0: c000 sw s0,0(s0) - 56c2: 000a c.slli zero,0x2 - 56c4: 2700 fld fs0,8(a4) - 56c6: 9100 0x9100 - 56c8: 7f88 flw fa0,56(a5) - 56ca: 7906 flw fs2,96(sp) - 56cc: 1a00 addi s0,sp,304 - 56ce: 791e0083 lb ra,1937(t3) - 56d2: 1a00 addi s0,sp,304 - 56d4: 0078 addi a4,sp,12 - 56d6: 911e0083 lb ra,-1775(t3) - 56da: 7f88 flw fa0,56(a5) - 56dc: 7906 flw fs2,96(sp) - 56de: 1a00 addi s0,sp,304 - 56e0: 221e008f 0x221e008f - 56e4: 0085 addi ra,ra,1 - 56e6: 7922 flw fs2,40(sp) - 56e8: 1a00 addi s0,sp,304 - 56ea: 2440 fld fs0,136(s0) - 56ec: 9f22 add t5,t5,s0 - 56ee: 0ac0 addi s0,sp,340 - 56f0: 0000 unimp - 56f2: 0ac8 addi a0,sp,340 - 56f4: 0000 unimp - 56f6: 0031 c.nop 12 - 56f8: 8891 andi s1,s1,4 - 56fa: 067f 0x67f - 56fc: 0079 c.nop 30 - 56fe: 911a add sp,sp,t1 - 5700: 7efc flw fa5,124(a3) - 5702: 7906 flw fs2,96(sp) - 5704: 1a00 addi s0,sp,304 - 5706: 791e flw fs2,228(sp) - 5708: 1a00 addi s0,sp,304 - 570a: fc91 bnez s1,5626 <_start-0x7fffa9da> - 570c: 067e slli a2,a2,0x1f - 570e: 0079 c.nop 30 - 5710: 781a flw fa6,164(sp) - 5712: 1e00 addi s0,sp,816 - 5714: 8891 andi s1,s1,4 - 5716: 067f 0x67f - 5718: 0079 c.nop 30 - 571a: 8f1a mv t5,t1 - 571c: 1e00 addi s0,sp,816 - 571e: 8522 mv a0,s0 - 5720: 2200 fld fs0,0(a2) - 5722: 0079 c.nop 30 - 5724: 401a 0x401a - 5726: 2224 fld fs1,64(a2) - 5728: c89f 000a e000 0xe000000ac89f - 572e: 000a c.slli zero,0x2 - 5730: 3500 fld fs0,40(a0) - 5732: 9100 0x9100 - 5734: 7f88 flw fa0,56(a5) - 5736: 7906 flw fs2,96(sp) - 5738: 1a00 addi s0,sp,304 - 573a: fc91 bnez s1,5656 <_start-0x7fffa9aa> - 573c: 067e slli a2,a2,0x1f - 573e: 0079 c.nop 30 - 5740: 1e1a slli t3,t3,0x26 - 5742: 0079 c.nop 30 - 5744: 911a add sp,sp,t1 - 5746: 7efc flw fa5,124(a3) - 5748: 7906 flw fs2,96(sp) - 574a: 1a00 addi s0,sp,304 - 574c: 0078 addi a4,sp,12 - 574e: 911e add sp,sp,t2 - 5750: 7f88 flw fa0,56(a5) - 5752: 7906 flw fs2,96(sp) - 5754: 1a00 addi s0,sp,304 - 5756: fc91 bnez s1,5672 <_start-0x7fffa98e> - 5758: 067e slli a2,a2,0x1f - 575a: 2540 fld fs0,136(a0) - 575c: 221e fld ft4,448(sp) - 575e: 0085 addi ra,ra,1 - 5760: 7922 flw fs2,40(sp) - 5762: 1a00 addi s0,sp,304 - 5764: 2440 fld fs0,136(s0) - 5766: 9f22 add t5,t5,s0 - 5768: 0ae0 addi s0,sp,348 - 576a: 0000 unimp - 576c: 0bc4 addi s1,sp,468 - 576e: 0000 unimp - 5770: 0035 c.nop 13 - 5772: 7f89 lui t6,0xfffe2 - 5774: 8891 andi s1,s1,4 - 5776: 067f 0x67f - 5778: 891a mv s2,t1 - 577a: 917f 0x917f - 577c: 7efc flw fa5,124(a3) - 577e: 1a06 slli s4,s4,0x21 - 5780: 891e mv s2,t2 - 5782: 1a7f 0x1a7f - 5784: 7f89 lui t6,0xfffe2 - 5786: fc91 bnez s1,56a2 <_start-0x7fffa95e> - 5788: 067e slli a2,a2,0x1f - 578a: 781a flw fa6,164(sp) - 578c: 1e00 addi s0,sp,816 - 578e: 7f89 lui t6,0xfffe2 - 5790: 8891 andi s1,s1,4 - 5792: 067f 0x67f - 5794: 911a add sp,sp,t1 - 5796: 7efc flw fa5,124(a3) - 5798: 4006 0x4006 - 579a: 1e25 addi t3,t3,-23 - 579c: 8522 mv a0,s0 - 579e: 2200 fld fs0,0(a2) - 57a0: 7f89 lui t6,0xfffe2 - 57a2: 401a 0x401a - 57a4: 2224 fld fs1,64(a2) - 57a6: a89f 000d b400 0xb400000da89f - 57ac: 000d c.nop 3 - 57ae: 3500 fld fs0,40(a0) - 57b0: 8900 0x8900 - 57b2: 917f 0x917f - 57b4: 7f88 flw fa0,56(a5) - 57b6: 1a06 slli s4,s4,0x21 - 57b8: 7f89 lui t6,0xfffe2 - 57ba: fc91 bnez s1,56d6 <_start-0x7fffa92a> - 57bc: 067e slli a2,a2,0x1f - 57be: 1e1a slli t3,t3,0x26 - 57c0: 7f89 lui t6,0xfffe2 - 57c2: 891a mv s2,t1 - 57c4: 917f 0x917f - 57c6: 7efc flw fa5,124(a3) - 57c8: 1a06 slli s4,s4,0x21 - 57ca: 0078 addi a4,sp,12 - 57cc: 891e mv s2,t2 - 57ce: 917f 0x917f - 57d0: 7f88 flw fa0,56(a5) - 57d2: 1a06 slli s4,s4,0x21 - 57d4: fc91 bnez s1,56f0 <_start-0x7fffa910> - 57d6: 067e slli a2,a2,0x1f - 57d8: 2540 fld fs0,136(a0) - 57da: 221e fld ft4,448(sp) - 57dc: 0085 addi ra,ra,1 - 57de: 8922 mv s2,s0 - 57e0: 1a7f 0x1a7f - 57e2: 2440 fld fs0,136(s0) - 57e4: 9f22 add t5,t5,s0 - ... - 57ee: 0630 addi a2,sp,776 - 57f0: 0000 unimp - 57f2: 06ec addi a1,sp,844 - 57f4: 0000 unimp - 57f6: 0001 nop - 57f8: 000a0067 jr s4 # ffffa000 <__BSS_END__+0x7ffe3288> - 57fc: a400 fsd fs0,8(s0) - 57fe: 000a c.slli zero,0x2 - 5800: 0100 addi s0,sp,128 - 5802: 6800 flw fs0,16(s0) - ... - 580c: 0480 addi s0,sp,576 - 580e: 0000 unimp - 5810: 04ac addi a1,sp,584 - 5812: 0000 unimp - 5814: 0001 nop - 5816: ac5c fsd fa5,152(s0) - 5818: 0004 0x4 - 581a: 0c00 addi s0,sp,528 - 581c: 06000007 0x6000007 - 5820: 8c00 0x8c00 - 5822: 7e00 flw fs0,56(a2) - 5824: 1e00 addi s0,sp,816 - 5826: 0c9f 0007 6c00 0x6c0000070c9f - 582c: 0b000007 vlsbu.v v0,(zero),a6 - 5830: 9100 0x9100 - 5832: 7ef0 flw fa2,124(a3) - 5834: 8906 mv s2,ra - 5836: 1a00 addi s0,sp,304 - 5838: 008c addi a1,sp,64 - 583a: 9f1e add t5,t5,t2 - 583c: 076c addi a1,sp,908 - 583e: 0000 unimp - 5840: 0860 addi s0,sp,28 - 5842: 0000 unimp - 5844: 0010 0x10 - 5846: 8091 srli s1,s1,0x4 - 5848: 067f 0x67f - 584a: 0089 addi ra,ra,2 - 584c: 911a add sp,sp,t1 - 584e: 7ef0 flw fa2,124(a3) - 5850: 8906 mv s2,ra - 5852: 1a00 addi s0,sp,304 - 5854: 9f1e add t5,t5,t2 - 5856: 0860 addi s0,sp,28 - 5858: 0000 unimp - 585a: 0894 addi a3,sp,80 - 585c: 0000 unimp - 585e: 0010 0x10 - 5860: 8091 srli s1,s1,0x4 - 5862: 067f 0x67f - 5864: 008c addi a1,sp,64 - 5866: 911a add sp,sp,t1 - 5868: 7ef0 flw fa2,124(a3) - 586a: 8c06 mv s8,ra - 586c: 1a00 addi s0,sp,304 - 586e: 9f1e add t5,t5,t2 - 5870: 0894 addi a3,sp,80 - 5872: 0000 unimp - 5874: 08e0 addi s0,sp,92 - 5876: 0000 unimp - 5878: 0012 c.slli zero,0x4 - 587a: 8091 srli s1,s1,0x4 - 587c: 067f 0x67f - 587e: ff0a fsw ft2,188(sp) - 5880: 1aff 0x1aff - 5882: f091 bnez s1,5786 <_start-0x7fffa87a> - 5884: 067e slli a2,a2,0x1f - 5886: ff0a fsw ft2,188(sp) - 5888: 1aff 0x1aff - 588a: 9f1e add t5,t5,t2 - 588c: 08e0 addi s0,sp,92 - 588e: 0000 unimp - 5890: 08e4 addi s1,sp,92 - 5892: 0000 unimp - 5894: 0010 0x10 - 5896: 7f7a flw ft10,188(sp) - 5898: 8091 srli s1,s1,0x4 - 589a: 067f 0x67f - 589c: 7a1a flw fs4,164(sp) - 589e: 917f 0x917f - 58a0: 7ef0 flw fa2,124(a3) - 58a2: 1a06 slli s4,s4,0x21 - 58a4: 9f1e add t5,t5,t2 - 58a6: 08e4 addi s1,sp,92 - 58a8: 0000 unimp - 58aa: 08e8 addi a0,sp,92 - 58ac: 0000 unimp - 58ae: 0012 c.slli zero,0x4 - 58b0: 8091 srli s1,s1,0x4 - 58b2: 067f 0x67f - 58b4: ff0a fsw ft2,188(sp) - 58b6: 1aff 0x1aff - 58b8: f091 bnez s1,57bc <_start-0x7fffa844> - 58ba: 067e slli a2,a2,0x1f - 58bc: ff0a fsw ft2,188(sp) - 58be: 1aff 0x1aff - 58c0: 9f1e add t5,t5,t2 - 58c2: 08e8 addi a0,sp,92 - 58c4: 0000 unimp - 58c6: 0934 addi a3,sp,152 - 58c8: 0000 unimp - 58ca: 0010 0x10 - 58cc: 7f84 flw fs1,56(a5) - 58ce: 8091 srli s1,s1,0x4 - 58d0: 067f 0x67f - 58d2: 841a mv s0,t1 - 58d4: 917f 0x917f - 58d6: 7ef0 flw fa2,124(a3) - 58d8: 1a06 slli s4,s4,0x21 - 58da: 9f1e add t5,t5,t2 - 58dc: 0934 addi a3,sp,152 - 58de: 0000 unimp - 58e0: 0958 addi a4,sp,148 - 58e2: 0000 unimp - 58e4: 0010 0x10 - 58e6: 8091 srli s1,s1,0x4 - 58e8: 067f 0x67f - 58ea: 0084 addi s1,sp,64 - 58ec: 911a add sp,sp,t1 - 58ee: 7ef0 flw fa2,124(a3) - 58f0: 8406 mv s0,ra - 58f2: 1a00 addi s0,sp,304 - 58f4: 9f1e add t5,t5,t2 - 58f6: 0958 addi a4,sp,148 - 58f8: 0000 unimp - 58fa: 09e0 addi s0,sp,220 - 58fc: 0000 unimp - 58fe: 0010 0x10 - 5900: 7f85 lui t6,0xfffe1 - 5902: 8091 srli s1,s1,0x4 - 5904: 067f 0x67f - 5906: 851a mv a0,t1 - 5908: 917f 0x917f - 590a: 7ef0 flw fa2,124(a3) - 590c: 1a06 slli s4,s4,0x21 - 590e: 9f1e add t5,t5,t2 - 5910: 09e0 addi s0,sp,220 - 5912: 0000 unimp - 5914: 09ec addi a1,sp,220 - 5916: 0000 unimp - 5918: 0010 0x10 - 591a: 8091 srli s1,s1,0x4 - 591c: 067f 0x67f - 591e: 0079 c.nop 30 - 5920: 911a add sp,sp,t1 - 5922: 7ef0 flw fa2,124(a3) - 5924: 7906 flw fs2,96(sp) - 5926: 1a00 addi s0,sp,304 - 5928: 9f1e add t5,t5,t2 - 592a: 09ec addi a1,sp,220 - 592c: 0000 unimp - 592e: 0a48 addi a0,sp,276 - 5930: 0000 unimp - 5932: 0010 0x10 - 5934: 7f84 flw fs1,56(a5) - 5936: 8091 srli s1,s1,0x4 - 5938: 067f 0x67f - 593a: 841a mv s0,t1 - 593c: 917f 0x917f - 593e: 7ef0 flw fa2,124(a3) - 5940: 1a06 slli s4,s4,0x21 - 5942: 9f1e add t5,t5,t2 - 5944: 0a48 addi a0,sp,276 - 5946: 0000 unimp - 5948: 0ae0 addi s0,sp,348 - 594a: 0000 unimp - 594c: 0010 0x10 - 594e: 8091 srli s1,s1,0x4 - 5950: 067f 0x67f - 5952: 0079 c.nop 30 - 5954: 911a add sp,sp,t1 - 5956: 7ef0 flw fa2,124(a3) - 5958: 7906 flw fs2,96(sp) - 595a: 1a00 addi s0,sp,304 - 595c: 9f1e add t5,t5,t2 - 595e: 0ae0 addi s0,sp,348 - 5960: 0000 unimp - 5962: 0bc4 addi s1,sp,468 - 5964: 0000 unimp - 5966: 0010 0x10 - 5968: 7f89 lui t6,0xfffe2 - 596a: 8091 srli s1,s1,0x4 - 596c: 067f 0x67f - 596e: 891a mv s2,t1 - 5970: 917f 0x917f - 5972: 7ef0 flw fa2,124(a3) - 5974: 1a06 slli s4,s4,0x21 - 5976: 9f1e add t5,t5,t2 - 5978: 0da8 addi a0,sp,728 - 597a: 0000 unimp - 597c: 0db4 addi a3,sp,728 - 597e: 0000 unimp - 5980: 0010 0x10 - 5982: 7f89 lui t6,0xfffe2 - 5984: 8091 srli s1,s1,0x4 - 5986: 067f 0x67f - 5988: 891a mv s2,t1 - 598a: 917f 0x917f - 598c: 7ef0 flw fa2,124(a3) - 598e: 1a06 slli s4,s4,0x21 - 5990: 9f1e add t5,t5,t2 - ... - 599a: 0480 addi s0,sp,576 - 599c: 0000 unimp - 599e: 048c addi a1,sp,576 - 59a0: 0000 unimp - 59a2: 0001 nop - 59a4: 8c5f 0004 9400 0x940000048c5f - 59aa: 0004 0x4 - 59ac: 0600 addi s0,sp,768 - 59ae: 8500 0x8500 - 59b0: 7e00 flw fs0,56(a2) - 59b2: 1e00 addi s0,sp,816 - 59b4: 949f 0004 a800 0xa8000004949f - 59ba: 0004 0x4 - 59bc: 0100 addi s0,sp,128 - 59be: 5f00 lw s0,56(a4) - 59c0: 04a8 addi a0,sp,584 - 59c2: 0000 unimp - 59c4: 04ac addi a1,sp,584 - 59c6: 0000 unimp - 59c8: 0008 0x8 - 59ca: 007c addi a5,sp,12 - 59cc: 2540 fld fs0,136(a0) - 59ce: 9f22007b 0x9f22007b - 59d2: 04ac addi a1,sp,584 - 59d4: 0000 unimp - 59d6: 04f4 addi a3,sp,588 - 59d8: 0000 unimp - 59da: 008c000b 0x8c000b - 59de: 007e c.slli zero,0x1f - 59e0: 401e 0x401e - 59e2: 7b25 lui s6,0xfffe9 - 59e4: 2200 fld fs0,0(a2) - 59e6: f49f 0004 2800 0x28000004f49f - 59ec: 0005 c.nop 1 - 59ee: 1100 addi s0,sp,160 - 59f0: 8500 0x8500 - 59f2: 7e00 flw fs0,56(a2) - 59f4: 1e00 addi s0,sp,816 - 59f6: 008c addi a1,sp,64 - 59f8: 007e c.slli zero,0x1f - 59fa: 401e 0x401e - 59fc: 2225 jal 5b24 <_start-0x7fffa4dc> - 59fe: 0080 addi s0,sp,64 - 5a00: 9f22 add t5,t5,s0 - 5a02: 0528 addi a0,sp,648 - 5a04: 0000 unimp - 5a06: 070c addi a1,sp,896 - 5a08: 0000 unimp - 5a0a: 0014 0x14 - 5a0c: 0085 addi ra,ra,1 - 5a0e: 007e c.slli zero,0x1f - 5a10: 8f1e mv t5,t2 - 5a12: 8c00 0x8c00 - 5a14: 1e00 addi s0,sp,816 - 5a16: 8c22 mv s8,s0 - 5a18: 7e00 flw fs0,56(a2) - 5a1a: 1e00 addi s0,sp,816 - 5a1c: 2540 fld fs0,136(a0) - 5a1e: 9f22 add t5,t5,s0 - 5a20: 070c addi a1,sp,896 - 5a22: 0000 unimp - 5a24: 0720 addi s0,sp,904 - 5a26: 0000 unimp - 5a28: 001e c.slli zero,0x7 - 5a2a: f091 bnez s1,592e <_start-0x7fffa6d2> - 5a2c: 067e slli a2,a2,0x1f - 5a2e: 0089 addi ra,ra,2 - 5a30: 851a mv a0,t1 - 5a32: 1e00 addi s0,sp,816 - 5a34: 008c008f 0x8c008f - 5a38: 221e fld ft4,448(sp) - 5a3a: f091 bnez s1,593e <_start-0x7fffa6c2> - 5a3c: 067e slli a2,a2,0x1f - 5a3e: 0089 addi ra,ra,2 - 5a40: 8c1a mv s8,t1 - 5a42: 1e00 addi s0,sp,816 - 5a44: 2540 fld fs0,136(a0) - 5a46: 9f22 add t5,t5,s0 - 5a48: 0720 addi s0,sp,904 - 5a4a: 0000 unimp - 5a4c: 0764 addi s1,sp,908 - 5a4e: 0000 unimp - 5a50: 0022 c.slli zero,0x8 - 5a52: f091 bnez s1,5956 <_start-0x7fffa6aa> - 5a54: 067e slli a2,a2,0x1f - 5a56: 0089 addi ra,ra,2 - 5a58: 851a mv a0,t1 - 5a5a: 1e00 addi s0,sp,816 - 5a5c: f091 bnez s1,5960 <_start-0x7fffa6a0> - 5a5e: 067e slli a2,a2,0x1f - 5a60: 2540 fld fs0,136(a0) - 5a62: 008c addi a1,sp,64 - 5a64: 221e fld ft4,448(sp) - 5a66: f091 bnez s1,596a <_start-0x7fffa696> - 5a68: 067e slli a2,a2,0x1f - 5a6a: 0089 addi ra,ra,2 - 5a6c: 8c1a mv s8,t1 - 5a6e: 1e00 addi s0,sp,816 - 5a70: 2540 fld fs0,136(a0) - 5a72: 9f22 add t5,t5,s0 - 5a74: 0764 addi s1,sp,908 - 5a76: 0000 unimp - 5a78: 076c addi a1,sp,908 - 5a7a: 0000 unimp - 5a7c: 0026 c.slli zero,0x9 - 5a7e: f091 bnez s1,5982 <_start-0x7fffa67e> - 5a80: 067e slli a2,a2,0x1f - 5a82: 0089 addi ra,ra,2 - 5a84: 911a add sp,sp,t1 - 5a86: 7f80 flw fs0,56(a5) - 5a88: 4006 0x4006 - 5a8a: 1e25 addi t3,t3,-23 - 5a8c: f091 bnez s1,5990 <_start-0x7fffa670> - 5a8e: 067e slli a2,a2,0x1f - 5a90: 2540 fld fs0,136(a0) - 5a92: 008c addi a1,sp,64 - 5a94: 221e fld ft4,448(sp) - 5a96: f091 bnez s1,599a <_start-0x7fffa666> - 5a98: 067e slli a2,a2,0x1f - 5a9a: 0089 addi ra,ra,2 - 5a9c: 8c1a mv s8,t1 - 5a9e: 1e00 addi s0,sp,816 - 5aa0: 2540 fld fs0,136(a0) - 5aa2: 9f22 add t5,t5,s0 - 5aa4: 076c addi a1,sp,908 - 5aa6: 0000 unimp - 5aa8: 0860 addi s0,sp,28 - 5aaa: 0000 unimp - 5aac: 0030 addi a2,sp,8 - 5aae: f091 bnez s1,59b2 <_start-0x7fffa64e> - 5ab0: 067e slli a2,a2,0x1f - 5ab2: 0089 addi ra,ra,2 - 5ab4: 911a add sp,sp,t1 - 5ab6: 7f80 flw fs0,56(a5) - 5ab8: 4006 0x4006 - 5aba: 1e25 addi t3,t3,-23 - 5abc: 8091 srli s1,s1,0x4 - 5abe: 067f 0x67f - 5ac0: 0089 addi ra,ra,2 - 5ac2: 911a add sp,sp,t1 - 5ac4: 7ef0 flw fa2,124(a3) - 5ac6: 4006 0x4006 - 5ac8: 1e25 addi t3,t3,-23 - 5aca: 9122 add sp,sp,s0 - 5acc: 7f80 flw fs0,56(a5) - 5ace: 8906 mv s2,ra - 5ad0: 1a00 addi s0,sp,304 - 5ad2: f091 bnez s1,59d6 <_start-0x7fffa62a> - 5ad4: 067e slli a2,a2,0x1f - 5ad6: 0089 addi ra,ra,2 - 5ad8: 1e1a slli t3,t3,0x26 - 5ada: 2540 fld fs0,136(a0) - 5adc: 9f22 add t5,t5,s0 - 5ade: 0860 addi s0,sp,28 - 5ae0: 0000 unimp - 5ae2: 0894 addi a3,sp,80 - 5ae4: 0000 unimp - 5ae6: 0030 addi a2,sp,8 - 5ae8: f091 bnez s1,59ec <_start-0x7fffa614> - 5aea: 067e slli a2,a2,0x1f - 5aec: 008c addi a1,sp,64 - 5aee: 911a add sp,sp,t1 - 5af0: 7f80 flw fs0,56(a5) - 5af2: 4006 0x4006 - 5af4: 1e25 addi t3,t3,-23 - 5af6: 8091 srli s1,s1,0x4 - 5af8: 067f 0x67f - 5afa: 008c addi a1,sp,64 - 5afc: 911a add sp,sp,t1 - 5afe: 7ef0 flw fa2,124(a3) - 5b00: 4006 0x4006 - 5b02: 1e25 addi t3,t3,-23 - 5b04: 9122 add sp,sp,s0 - 5b06: 7f80 flw fs0,56(a5) - 5b08: 8c06 mv s8,ra - 5b0a: 1a00 addi s0,sp,304 - 5b0c: f091 bnez s1,5a10 <_start-0x7fffa5f0> - 5b0e: 067e slli a2,a2,0x1f - 5b10: 008c addi a1,sp,64 - 5b12: 1e1a slli t3,t3,0x26 - 5b14: 2540 fld fs0,136(a0) - 5b16: 9f22 add t5,t5,s0 - 5b18: 0894 addi a3,sp,80 - 5b1a: 0000 unimp - 5b1c: 08e0 addi s0,sp,92 - 5b1e: 0000 unimp - 5b20: 0034 addi a3,sp,8 - 5b22: f091 bnez s1,5a26 <_start-0x7fffa5da> - 5b24: 067e slli a2,a2,0x1f - 5b26: ff0a fsw ft2,188(sp) - 5b28: 1aff 0x1aff - 5b2a: 8091 srli s1,s1,0x4 - 5b2c: 067f 0x67f - 5b2e: 2540 fld fs0,136(a0) - 5b30: 911e add sp,sp,t2 - 5b32: 7f80 flw fs0,56(a5) - 5b34: 0a06 slli s4,s4,0x1 - 5b36: ffff 0xffff - 5b38: 911a add sp,sp,t1 - 5b3a: 7ef0 flw fa2,124(a3) - 5b3c: 4006 0x4006 - 5b3e: 1e25 addi t3,t3,-23 - 5b40: 9122 add sp,sp,s0 - 5b42: 7f80 flw fs0,56(a5) - 5b44: 0a06 slli s4,s4,0x1 - 5b46: ffff 0xffff - 5b48: 911a add sp,sp,t1 - 5b4a: 7ef0 flw fa2,124(a3) - 5b4c: 0a06 slli s4,s4,0x1 - 5b4e: ffff 0xffff - 5b50: 1e1a slli t3,t3,0x26 - 5b52: 2540 fld fs0,136(a0) - 5b54: 9f22 add t5,t5,s0 - 5b56: 08e0 addi s0,sp,92 - 5b58: 0000 unimp - 5b5a: 08e4 addi s1,sp,92 - 5b5c: 0000 unimp - 5b5e: 0030 addi a2,sp,8 - 5b60: 7f7a flw ft10,188(sp) - 5b62: f091 bnez s1,5a66 <_start-0x7fffa59a> - 5b64: 067e slli a2,a2,0x1f - 5b66: 911a add sp,sp,t1 - 5b68: 7f80 flw fs0,56(a5) - 5b6a: 4006 0x4006 - 5b6c: 1e25 addi t3,t3,-23 - 5b6e: 7f7a flw ft10,188(sp) - 5b70: 8091 srli s1,s1,0x4 - 5b72: 067f 0x67f - 5b74: 911a add sp,sp,t1 - 5b76: 7ef0 flw fa2,124(a3) - 5b78: 4006 0x4006 - 5b7a: 1e25 addi t3,t3,-23 - 5b7c: 7a22 flw fs4,40(sp) - 5b7e: 917f 0x917f - 5b80: 7f80 flw fs0,56(a5) - 5b82: 1a06 slli s4,s4,0x21 - 5b84: 7f7a flw ft10,188(sp) - 5b86: f091 bnez s1,5a8a <_start-0x7fffa576> - 5b88: 067e slli a2,a2,0x1f - 5b8a: 1e1a slli t3,t3,0x26 - 5b8c: 2540 fld fs0,136(a0) - 5b8e: 9f22 add t5,t5,s0 - 5b90: 08e4 addi s1,sp,92 - 5b92: 0000 unimp - 5b94: 08e8 addi a0,sp,92 - 5b96: 0000 unimp - 5b98: 0034 addi a3,sp,8 - 5b9a: f091 bnez s1,5a9e <_start-0x7fffa562> - 5b9c: 067e slli a2,a2,0x1f - 5b9e: ff0a fsw ft2,188(sp) - 5ba0: 1aff 0x1aff - 5ba2: 8091 srli s1,s1,0x4 - 5ba4: 067f 0x67f - 5ba6: 2540 fld fs0,136(a0) - 5ba8: 911e add sp,sp,t2 - 5baa: 7f80 flw fs0,56(a5) - 5bac: 0a06 slli s4,s4,0x1 - 5bae: ffff 0xffff - 5bb0: 911a add sp,sp,t1 - 5bb2: 7ef0 flw fa2,124(a3) - 5bb4: 4006 0x4006 - 5bb6: 1e25 addi t3,t3,-23 - 5bb8: 9122 add sp,sp,s0 - 5bba: 7f80 flw fs0,56(a5) - 5bbc: 0a06 slli s4,s4,0x1 - 5bbe: ffff 0xffff - 5bc0: 911a add sp,sp,t1 - 5bc2: 7ef0 flw fa2,124(a3) - 5bc4: 0a06 slli s4,s4,0x1 - 5bc6: ffff 0xffff - 5bc8: 1e1a slli t3,t3,0x26 - 5bca: 2540 fld fs0,136(a0) - 5bcc: 9f22 add t5,t5,s0 - 5bce: 08e8 addi a0,sp,92 - 5bd0: 0000 unimp - 5bd2: 0934 addi a3,sp,152 - 5bd4: 0000 unimp - 5bd6: 0030 addi a2,sp,8 - 5bd8: 7f84 flw fs1,56(a5) - 5bda: f091 bnez s1,5ade <_start-0x7fffa522> - 5bdc: 067e slli a2,a2,0x1f - 5bde: 911a add sp,sp,t1 - 5be0: 7f80 flw fs0,56(a5) - 5be2: 4006 0x4006 - 5be4: 1e25 addi t3,t3,-23 - 5be6: 7f84 flw fs1,56(a5) - 5be8: 8091 srli s1,s1,0x4 - 5bea: 067f 0x67f - 5bec: 911a add sp,sp,t1 - 5bee: 7ef0 flw fa2,124(a3) - 5bf0: 4006 0x4006 - 5bf2: 1e25 addi t3,t3,-23 - 5bf4: 8422 mv s0,s0 - 5bf6: 917f 0x917f - 5bf8: 7f80 flw fs0,56(a5) - 5bfa: 1a06 slli s4,s4,0x21 - 5bfc: 7f84 flw fs1,56(a5) - 5bfe: f091 bnez s1,5b02 <_start-0x7fffa4fe> - 5c00: 067e slli a2,a2,0x1f - 5c02: 1e1a slli t3,t3,0x26 - 5c04: 2540 fld fs0,136(a0) - 5c06: 9f22 add t5,t5,s0 - 5c08: 0934 addi a3,sp,152 - 5c0a: 0000 unimp - 5c0c: 0958 addi a4,sp,148 - 5c0e: 0000 unimp - 5c10: 0030 addi a2,sp,8 - 5c12: f091 bnez s1,5b16 <_start-0x7fffa4ea> - 5c14: 067e slli a2,a2,0x1f - 5c16: 0084 addi s1,sp,64 - 5c18: 911a add sp,sp,t1 - 5c1a: 7f80 flw fs0,56(a5) - 5c1c: 4006 0x4006 - 5c1e: 1e25 addi t3,t3,-23 - 5c20: 8091 srli s1,s1,0x4 - 5c22: 067f 0x67f - 5c24: 0084 addi s1,sp,64 - 5c26: 911a add sp,sp,t1 - 5c28: 7ef0 flw fa2,124(a3) - 5c2a: 4006 0x4006 - 5c2c: 1e25 addi t3,t3,-23 - 5c2e: 9122 add sp,sp,s0 - 5c30: 7f80 flw fs0,56(a5) - 5c32: 8406 mv s0,ra - 5c34: 1a00 addi s0,sp,304 - 5c36: f091 bnez s1,5b3a <_start-0x7fffa4c6> - 5c38: 067e slli a2,a2,0x1f - 5c3a: 0084 addi s1,sp,64 - 5c3c: 1e1a slli t3,t3,0x26 - 5c3e: 2540 fld fs0,136(a0) - 5c40: 9f22 add t5,t5,s0 - 5c42: 0958 addi a4,sp,148 - 5c44: 0000 unimp - 5c46: 09e0 addi s0,sp,220 - 5c48: 0000 unimp - 5c4a: 0030 addi a2,sp,8 - 5c4c: 7f85 lui t6,0xfffe1 - 5c4e: f091 bnez s1,5b52 <_start-0x7fffa4ae> - 5c50: 067e slli a2,a2,0x1f - 5c52: 911a add sp,sp,t1 - 5c54: 7f80 flw fs0,56(a5) - 5c56: 4006 0x4006 - 5c58: 1e25 addi t3,t3,-23 - 5c5a: 7f85 lui t6,0xfffe1 - 5c5c: 8091 srli s1,s1,0x4 - 5c5e: 067f 0x67f - 5c60: 911a add sp,sp,t1 - 5c62: 7ef0 flw fa2,124(a3) - 5c64: 4006 0x4006 - 5c66: 1e25 addi t3,t3,-23 - 5c68: 8522 mv a0,s0 - 5c6a: 917f 0x917f - 5c6c: 7f80 flw fs0,56(a5) - 5c6e: 1a06 slli s4,s4,0x21 - 5c70: 7f85 lui t6,0xfffe1 - 5c72: f091 bnez s1,5b76 <_start-0x7fffa48a> - 5c74: 067e slli a2,a2,0x1f - 5c76: 1e1a slli t3,t3,0x26 - 5c78: 2540 fld fs0,136(a0) - 5c7a: 9f22 add t5,t5,s0 - 5c7c: 09e0 addi s0,sp,220 - 5c7e: 0000 unimp - 5c80: 09ec addi a1,sp,220 - 5c82: 0000 unimp - 5c84: 0030 addi a2,sp,8 - 5c86: f091 bnez s1,5b8a <_start-0x7fffa476> - 5c88: 067e slli a2,a2,0x1f - 5c8a: 0079 c.nop 30 - 5c8c: 911a add sp,sp,t1 - 5c8e: 7f80 flw fs0,56(a5) - 5c90: 4006 0x4006 - 5c92: 1e25 addi t3,t3,-23 - 5c94: 8091 srli s1,s1,0x4 - 5c96: 067f 0x67f - 5c98: 0079 c.nop 30 - 5c9a: 911a add sp,sp,t1 - 5c9c: 7ef0 flw fa2,124(a3) - 5c9e: 4006 0x4006 - 5ca0: 1e25 addi t3,t3,-23 - 5ca2: 9122 add sp,sp,s0 - 5ca4: 7f80 flw fs0,56(a5) - 5ca6: 7906 flw fs2,96(sp) - 5ca8: 1a00 addi s0,sp,304 - 5caa: f091 bnez s1,5bae <_start-0x7fffa452> - 5cac: 067e slli a2,a2,0x1f - 5cae: 0079 c.nop 30 - 5cb0: 1e1a slli t3,t3,0x26 - 5cb2: 2540 fld fs0,136(a0) - 5cb4: 9f22 add t5,t5,s0 - 5cb6: 09ec addi a1,sp,220 - 5cb8: 0000 unimp - 5cba: 0a48 addi a0,sp,276 - 5cbc: 0000 unimp - 5cbe: 0030 addi a2,sp,8 - 5cc0: 7f84 flw fs1,56(a5) - 5cc2: f091 bnez s1,5bc6 <_start-0x7fffa43a> - 5cc4: 067e slli a2,a2,0x1f - 5cc6: 911a add sp,sp,t1 - 5cc8: 7f80 flw fs0,56(a5) - 5cca: 4006 0x4006 - 5ccc: 1e25 addi t3,t3,-23 - 5cce: 7f84 flw fs1,56(a5) - 5cd0: 8091 srli s1,s1,0x4 - 5cd2: 067f 0x67f - 5cd4: 911a add sp,sp,t1 - 5cd6: 7ef0 flw fa2,124(a3) - 5cd8: 4006 0x4006 - 5cda: 1e25 addi t3,t3,-23 - 5cdc: 8422 mv s0,s0 - 5cde: 917f 0x917f - 5ce0: 7f80 flw fs0,56(a5) - 5ce2: 1a06 slli s4,s4,0x21 - 5ce4: 7f84 flw fs1,56(a5) - 5ce6: f091 bnez s1,5bea <_start-0x7fffa416> - 5ce8: 067e slli a2,a2,0x1f - 5cea: 1e1a slli t3,t3,0x26 - 5cec: 2540 fld fs0,136(a0) - 5cee: 9f22 add t5,t5,s0 - 5cf0: 0a48 addi a0,sp,276 - 5cf2: 0000 unimp - 5cf4: 0ae0 addi s0,sp,348 - 5cf6: 0000 unimp - 5cf8: 0030 addi a2,sp,8 - 5cfa: f091 bnez s1,5bfe <_start-0x7fffa402> - 5cfc: 067e slli a2,a2,0x1f - 5cfe: 0079 c.nop 30 - 5d00: 911a add sp,sp,t1 - 5d02: 7f80 flw fs0,56(a5) - 5d04: 4006 0x4006 - 5d06: 1e25 addi t3,t3,-23 - 5d08: 8091 srli s1,s1,0x4 - 5d0a: 067f 0x67f - 5d0c: 0079 c.nop 30 - 5d0e: 911a add sp,sp,t1 - 5d10: 7ef0 flw fa2,124(a3) - 5d12: 4006 0x4006 - 5d14: 1e25 addi t3,t3,-23 - 5d16: 9122 add sp,sp,s0 - 5d18: 7f80 flw fs0,56(a5) - 5d1a: 7906 flw fs2,96(sp) - 5d1c: 1a00 addi s0,sp,304 - 5d1e: f091 bnez s1,5c22 <_start-0x7fffa3de> - 5d20: 067e slli a2,a2,0x1f - 5d22: 0079 c.nop 30 - 5d24: 1e1a slli t3,t3,0x26 - 5d26: 2540 fld fs0,136(a0) - 5d28: 9f22 add t5,t5,s0 - 5d2a: 0ae0 addi s0,sp,348 - 5d2c: 0000 unimp - 5d2e: 0bc4 addi s1,sp,468 - 5d30: 0000 unimp - 5d32: 0030 addi a2,sp,8 - 5d34: 7f89 lui t6,0xfffe2 - 5d36: f091 bnez s1,5c3a <_start-0x7fffa3c6> - 5d38: 067e slli a2,a2,0x1f - 5d3a: 911a add sp,sp,t1 - 5d3c: 7f80 flw fs0,56(a5) - 5d3e: 4006 0x4006 - 5d40: 1e25 addi t3,t3,-23 - 5d42: 7f89 lui t6,0xfffe2 - 5d44: 8091 srli s1,s1,0x4 - 5d46: 067f 0x67f - 5d48: 911a add sp,sp,t1 - 5d4a: 7ef0 flw fa2,124(a3) - 5d4c: 4006 0x4006 - 5d4e: 1e25 addi t3,t3,-23 - 5d50: 8922 mv s2,s0 - 5d52: 917f 0x917f - 5d54: 7f80 flw fs0,56(a5) - 5d56: 1a06 slli s4,s4,0x21 - 5d58: 7f89 lui t6,0xfffe2 - 5d5a: f091 bnez s1,5c5e <_start-0x7fffa3a2> - 5d5c: 067e slli a2,a2,0x1f - 5d5e: 1e1a slli t3,t3,0x26 - 5d60: 2540 fld fs0,136(a0) - 5d62: 9f22 add t5,t5,s0 - 5d64: 0da8 addi a0,sp,728 - 5d66: 0000 unimp - 5d68: 0db4 addi a3,sp,728 - 5d6a: 0000 unimp - 5d6c: 0030 addi a2,sp,8 - 5d6e: 7f89 lui t6,0xfffe2 - 5d70: f091 bnez s1,5c74 <_start-0x7fffa38c> - 5d72: 067e slli a2,a2,0x1f - 5d74: 911a add sp,sp,t1 - 5d76: 7f80 flw fs0,56(a5) - 5d78: 4006 0x4006 - 5d7a: 1e25 addi t3,t3,-23 - 5d7c: 7f89 lui t6,0xfffe2 - 5d7e: 8091 srli s1,s1,0x4 - 5d80: 067f 0x67f - 5d82: 911a add sp,sp,t1 - 5d84: 7ef0 flw fa2,124(a3) - 5d86: 4006 0x4006 - 5d88: 1e25 addi t3,t3,-23 - 5d8a: 8922 mv s2,s0 - 5d8c: 917f 0x917f - 5d8e: 7f80 flw fs0,56(a5) - 5d90: 1a06 slli s4,s4,0x21 - 5d92: 7f89 lui t6,0xfffe2 - 5d94: f091 bnez s1,5c98 <_start-0x7fffa368> - 5d96: 067e slli a2,a2,0x1f - 5d98: 1e1a slli t3,t3,0x26 - 5d9a: 2540 fld fs0,136(a0) - 5d9c: 9f22 add t5,t5,s0 - ... - 5da6: 0484 addi s1,sp,576 - 5da8: 0000 unimp - 5daa: 0528 addi a0,sp,648 - 5dac: 0000 unimp - 5dae: 0001 nop - 5db0: 2860 fld fs0,208(s0) - 5db2: 0005 c.nop 1 - 5db4: 2000 fld fs0,0(s0) - 5db6: 06000007 0x6000007 - 5dba: 8f00 0x8f00 - 5dbc: 8c00 0x8c00 - 5dbe: 1e00 addi s0,sp,816 - 5dc0: 209f 0007 6c00 0x6c000007209f - 5dc6: 0a000007 vlsbu.v v0,(zero),zero - 5dca: 9100 0x9100 - 5dcc: 7ef0 flw fa2,124(a3) - 5dce: 4006 0x4006 - 5dd0: 8c25 xor s0,s0,s1 - 5dd2: 1e00 addi s0,sp,816 - 5dd4: 6c9f 0007 6000 0x600000076c9f - 5dda: 0008 0x8 - 5ddc: 0f00 addi s0,sp,912 - 5dde: 9100 0x9100 - 5de0: 7f80 flw fs0,56(a5) - 5de2: 8906 mv s2,ra - 5de4: 1a00 addi s0,sp,304 - 5de6: f091 bnez s1,5cea <_start-0x7fffa316> - 5de8: 067e slli a2,a2,0x1f - 5dea: 2540 fld fs0,136(a0) - 5dec: 9f1e add t5,t5,t2 - 5dee: 0860 addi s0,sp,28 - 5df0: 0000 unimp - 5df2: 0894 addi a3,sp,80 - 5df4: 0000 unimp - 5df6: 8091000f 0x8091000f - 5dfa: 067f 0x67f - 5dfc: 008c addi a1,sp,64 - 5dfe: 911a add sp,sp,t1 - 5e00: 7ef0 flw fa2,124(a3) - 5e02: 4006 0x4006 - 5e04: 1e25 addi t3,t3,-23 - 5e06: 949f 0008 e000 0xe0000008949f - 5e0c: 0008 0x8 - 5e0e: 1000 addi s0,sp,32 - 5e10: 9100 0x9100 - 5e12: 7f80 flw fs0,56(a5) - 5e14: 0a06 slli s4,s4,0x1 - 5e16: ffff 0xffff - 5e18: 911a add sp,sp,t1 - 5e1a: 7ef0 flw fa2,124(a3) - 5e1c: 4006 0x4006 - 5e1e: 1e25 addi t3,t3,-23 - 5e20: e09f 0008 e400 0xe4000008e09f - 5e26: 0008 0x8 - 5e28: 0f00 addi s0,sp,912 - 5e2a: 7a00 flw fs0,48(a2) - 5e2c: 917f 0x917f - 5e2e: 7f80 flw fs0,56(a5) - 5e30: 1a06 slli s4,s4,0x21 - 5e32: f091 bnez s1,5d36 <_start-0x7fffa2ca> - 5e34: 067e slli a2,a2,0x1f - 5e36: 2540 fld fs0,136(a0) - 5e38: 9f1e add t5,t5,t2 - 5e3a: 08e4 addi s1,sp,92 - 5e3c: 0000 unimp - 5e3e: 08e8 addi a0,sp,92 - 5e40: 0000 unimp - 5e42: 0010 0x10 - 5e44: 8091 srli s1,s1,0x4 - 5e46: 067f 0x67f - 5e48: ff0a fsw ft2,188(sp) - 5e4a: 1aff 0x1aff - 5e4c: f091 bnez s1,5d50 <_start-0x7fffa2b0> - 5e4e: 067e slli a2,a2,0x1f - 5e50: 2540 fld fs0,136(a0) - 5e52: 9f1e add t5,t5,t2 - 5e54: 08e8 addi a0,sp,92 - 5e56: 0000 unimp - 5e58: 0934 addi a3,sp,152 - 5e5a: 0000 unimp - 5e5c: 7f84000f 0x7f84000f - 5e60: 8091 srli s1,s1,0x4 - 5e62: 067f 0x67f - 5e64: 911a add sp,sp,t1 - 5e66: 7ef0 flw fa2,124(a3) - 5e68: 4006 0x4006 - 5e6a: 1e25 addi t3,t3,-23 - 5e6c: 349f 0009 5800 0x58000009349f - 5e72: 0009 c.nop 2 - 5e74: 0f00 addi s0,sp,912 - 5e76: 9100 0x9100 - 5e78: 7f80 flw fs0,56(a5) - 5e7a: 8406 mv s0,ra - 5e7c: 1a00 addi s0,sp,304 - 5e7e: f091 bnez s1,5d82 <_start-0x7fffa27e> - 5e80: 067e slli a2,a2,0x1f - 5e82: 2540 fld fs0,136(a0) - 5e84: 9f1e add t5,t5,t2 - 5e86: 0958 addi a4,sp,148 - 5e88: 0000 unimp - 5e8a: 09e0 addi s0,sp,220 - 5e8c: 0000 unimp - 5e8e: 7f85000f 0x7f85000f - 5e92: 8091 srli s1,s1,0x4 - 5e94: 067f 0x67f - 5e96: 911a add sp,sp,t1 - 5e98: 7ef0 flw fa2,124(a3) - 5e9a: 4006 0x4006 - 5e9c: 1e25 addi t3,t3,-23 - 5e9e: e09f 0009 ec00 0xec000009e09f - 5ea4: 0009 c.nop 2 - 5ea6: 0f00 addi s0,sp,912 - 5ea8: 9100 0x9100 - 5eaa: 7f80 flw fs0,56(a5) - 5eac: 7906 flw fs2,96(sp) - 5eae: 1a00 addi s0,sp,304 - 5eb0: f091 bnez s1,5db4 <_start-0x7fffa24c> - 5eb2: 067e slli a2,a2,0x1f - 5eb4: 2540 fld fs0,136(a0) - 5eb6: 9f1e add t5,t5,t2 - 5eb8: 09ec addi a1,sp,220 - 5eba: 0000 unimp - 5ebc: 0a48 addi a0,sp,276 - 5ebe: 0000 unimp - 5ec0: 7f84000f 0x7f84000f - 5ec4: 8091 srli s1,s1,0x4 - 5ec6: 067f 0x67f - 5ec8: 911a add sp,sp,t1 - 5eca: 7ef0 flw fa2,124(a3) - 5ecc: 4006 0x4006 - 5ece: 1e25 addi t3,t3,-23 - 5ed0: 489f 000a e000 0xe000000a489f - 5ed6: 000a c.slli zero,0x2 - 5ed8: 0f00 addi s0,sp,912 - 5eda: 9100 0x9100 - 5edc: 7f80 flw fs0,56(a5) - 5ede: 7906 flw fs2,96(sp) - 5ee0: 1a00 addi s0,sp,304 - 5ee2: f091 bnez s1,5de6 <_start-0x7fffa21a> - 5ee4: 067e slli a2,a2,0x1f - 5ee6: 2540 fld fs0,136(a0) - 5ee8: 9f1e add t5,t5,t2 - 5eea: 0ae0 addi s0,sp,348 - 5eec: 0000 unimp - 5eee: 0bc4 addi s1,sp,468 - 5ef0: 0000 unimp - 5ef2: 7f89000f 0x7f89000f - 5ef6: 8091 srli s1,s1,0x4 - 5ef8: 067f 0x67f - 5efa: 911a add sp,sp,t1 - 5efc: 7ef0 flw fa2,124(a3) - 5efe: 4006 0x4006 - 5f00: 1e25 addi t3,t3,-23 - 5f02: a89f 000d b400 0xb400000da89f - 5f08: 000d c.nop 3 - 5f0a: 0f00 addi s0,sp,912 - 5f0c: 8900 0x8900 - 5f0e: 917f 0x917f - 5f10: 7f80 flw fs0,56(a5) - 5f12: 1a06 slli s4,s4,0x21 - 5f14: f091 bnez s1,5e18 <_start-0x7fffa1e8> - 5f16: 067e slli a2,a2,0x1f - 5f18: 2540 fld fs0,136(a0) - 5f1a: 9f1e add t5,t5,t2 - ... - 5f24: 0494 addi a3,sp,576 - 5f26: 0000 unimp - 5f28: 0670 addi a2,sp,780 - 5f2a: 0000 unimp - 5f2c: 0001 nop - 5f2e: 0066 c.slli zero,0x19 - 5f30: 0000 unimp - 5f32: 0000 unimp - 5f34: 0000 unimp - 5f36: 5c00 lw s0,56(s0) - 5f38: 0004 0x4 - 5f3a: 7400 flw fs0,40(s0) - 5f3c: 0004 0x4 - 5f3e: 0100 addi s0,sp,128 - 5f40: 5e00 lw s0,56(a2) - 5f42: 0474 addi a3,sp,524 - 5f44: 0000 unimp - 5f46: 0bc4 addi s1,sp,468 - 5f48: 0000 unimp - 5f4a: f0910003 lb zero,-247(sp) - 5f4e: a87e fsd ft11,16(sp) - 5f50: 000d c.nop 3 - 5f52: b400 fsd fs0,40(s0) - 5f54: 000d c.nop 3 - 5f56: 0300 addi s0,sp,384 - 5f58: 9100 0x9100 - 5f5a: 7ef0 flw fa2,124(a3) - ... - 5f64: 046c addi a1,sp,524 - 5f66: 0000 unimp - 5f68: 0478 addi a4,sp,524 - 5f6a: 0000 unimp - 5f6c: 0001 nop - 5f6e: 786c flw fa1,116(s0) - 5f70: 0004 0x4 - 5f72: c400 sw s0,8(s0) - 5f74: 0300000b 0x300000b - 5f78: 9100 0x9100 - 5f7a: 7f80 flw fs0,56(a5) - 5f7c: 0da8 addi a0,sp,728 - 5f7e: 0000 unimp - 5f80: 0db4 addi a3,sp,728 - 5f82: 0000 unimp - 5f84: 80910003 lb zero,-2039(sp) - 5f88: 007f 0x7f - 5f8a: 0000 unimp - 5f8c: 0000 unimp - 5f8e: 0000 unimp - 5f90: 6c00 flw fs0,24(s0) - 5f92: 0004 0x4 - 5f94: 2000 fld fs0,0(s0) - 5f96: 01000007 vlbuff.v v0,(zero),v0.t - 5f9a: 6f00 flw fs0,24(a4) - 5f9c: 0720 addi s0,sp,904 - 5f9e: 0000 unimp - 5fa0: 0bc4 addi s1,sp,468 - 5fa2: 0000 unimp - 5fa4: f2910003 lb zero,-215(sp) - 5fa8: a87e fsd ft11,16(sp) - 5faa: 000d c.nop 3 - 5fac: b400 fsd fs0,40(s0) - 5fae: 000d c.nop 3 - 5fb0: 0300 addi s0,sp,384 - 5fb2: 9100 0x9100 - 5fb4: 7ef2 flw ft9,60(sp) - ... - 5fbe: 0470 addi a2,sp,524 - 5fc0: 0000 unimp - 5fc2: 0764 addi s1,sp,908 - 5fc4: 0000 unimp - 5fc6: 0001 nop - 5fc8: 6465 lui s0,0x19 - 5fca: c4000007 0xc4000007 - 5fce: 0300000b 0x300000b - 5fd2: 9100 0x9100 - 5fd4: 7f82 flw ft11,32(sp) - 5fd6: 0da8 addi a0,sp,728 - 5fd8: 0000 unimp - 5fda: 0db4 addi a3,sp,728 - 5fdc: 0000 unimp - 5fde: 82910003 lb zero,-2007(sp) - 5fe2: 007f 0x7f - 5fe4: 0000 unimp - 5fe6: 0000 unimp - 5fe8: 0000 unimp - 5fea: c800 sw s0,16(s0) - 5fec: 0004 0x4 - 5fee: 0400 addi s0,sp,512 - 5ff0: 0005 c.nop 1 - 5ff2: 0100 addi s0,sp,128 - 5ff4: 5d00 lw s0,56(a0) - 5ff6: 0504 addi s1,sp,640 - 5ff8: 0000 unimp - 5ffa: 070c addi a1,sp,896 - 5ffc: 0000 unimp - 5ffe: 0006 c.slli zero,0x1 - 6000: 008e slli ra,ra,0x3 - 6002: 007e c.slli zero,0x1f - 6004: 9f1e add t5,t5,t2 - 6006: 070c addi a1,sp,896 - 6008: 0000 unimp - 600a: 0860 addi s0,sp,28 - 600c: 0000 unimp - 600e: f091000b 0xf091000b - 6012: 067e slli a2,a2,0x1f - 6014: 0089 addi ra,ra,2 - 6016: 8e1a mv t3,t1 - 6018: 1e00 addi s0,sp,816 - 601a: 609f 0008 9400 0x94000008609f - 6020: 0008 0x8 - 6022: 0b00 addi s0,sp,400 - 6024: 9100 0x9100 - 6026: 7ef0 flw fa2,124(a3) - 6028: 8c06 mv s8,ra - 602a: 1a00 addi s0,sp,304 - 602c: 008e slli ra,ra,0x3 - 602e: 9f1e add t5,t5,t2 - 6030: 0894 addi a3,sp,80 - 6032: 0000 unimp - 6034: 08e0 addi s0,sp,92 - 6036: 0000 unimp - 6038: 000c 0xc - 603a: f091 bnez s1,5f3e <_start-0x7fffa0c2> - 603c: 067e slli a2,a2,0x1f - 603e: ff0a fsw ft2,188(sp) - 6040: 1aff 0x1aff - 6042: 008e slli ra,ra,0x3 - 6044: 9f1e add t5,t5,t2 - 6046: 08e0 addi s0,sp,92 - 6048: 0000 unimp - 604a: 08e4 addi s1,sp,92 - 604c: 0000 unimp - 604e: 7f7a000b 0x7f7a000b - 6052: f091 bnez s1,5f56 <_start-0x7fffa0aa> - 6054: 067e slli a2,a2,0x1f - 6056: 8e1a mv t3,t1 - 6058: 1e00 addi s0,sp,816 - 605a: e49f 0008 e800 0xe8000008e49f - 6060: 0008 0x8 - 6062: 0c00 addi s0,sp,528 - 6064: 9100 0x9100 - 6066: 7ef0 flw fa2,124(a3) - 6068: 0a06 slli s4,s4,0x1 - 606a: ffff 0xffff - 606c: 8e1a mv t3,t1 - 606e: 1e00 addi s0,sp,816 - 6070: e89f 0008 3400 0x34000008e89f - 6076: 0009 c.nop 2 - 6078: 0b00 addi s0,sp,400 - 607a: 8400 0x8400 - 607c: 917f 0x917f - 607e: 7ef0 flw fa2,124(a3) - 6080: 1a06 slli s4,s4,0x21 - 6082: 008e slli ra,ra,0x3 - 6084: 9f1e add t5,t5,t2 - 6086: 0934 addi a3,sp,152 - 6088: 0000 unimp - 608a: 0950 addi a2,sp,148 - 608c: 0000 unimp - 608e: f091000b 0xf091000b - 6092: 067e slli a2,a2,0x1f - 6094: 0084 addi s1,sp,64 - 6096: 8e1a mv t3,t1 - 6098: 1e00 addi s0,sp,816 - 609a: 509f 0009 5800 0x58000009509f - 60a0: 0009 c.nop 2 - 60a2: 1000 addi s0,sp,32 - 60a4: 9100 0x9100 - 60a6: 7f84 flw fs1,56(a5) - 60a8: 8406 mv s0,ra - 60aa: 1a00 addi s0,sp,304 - 60ac: f091 bnez s1,5fb0 <_start-0x7fffa050> - 60ae: 067e slli a2,a2,0x1f - 60b0: 0084 addi s1,sp,64 - 60b2: 1e1a slli t3,t3,0x26 - 60b4: 589f 0009 e000 0xe0000009589f - 60ba: 0009 c.nop 2 - 60bc: 1000 addi s0,sp,32 - 60be: 8500 0x8500 - 60c0: 917f 0x917f - 60c2: 7f84 flw fs1,56(a5) - 60c4: 1a06 slli s4,s4,0x21 - 60c6: 7f85 lui t6,0xfffe1 - 60c8: f091 bnez s1,5fcc <_start-0x7fffa034> - 60ca: 067e slli a2,a2,0x1f - 60cc: 1e1a slli t3,t3,0x26 - 60ce: e09f 0009 ec00 0xec000009e09f - 60d4: 0009 c.nop 2 - 60d6: 1000 addi s0,sp,32 - 60d8: 9100 0x9100 - 60da: 7f84 flw fs1,56(a5) - 60dc: 7906 flw fs2,96(sp) - 60de: 1a00 addi s0,sp,304 - 60e0: f091 bnez s1,5fe4 <_start-0x7fffa01c> - 60e2: 067e slli a2,a2,0x1f - 60e4: 0079 c.nop 30 - 60e6: 1e1a slli t3,t3,0x26 - 60e8: ec9f 0009 4800 0x48000009ec9f - 60ee: 000a c.slli zero,0x2 - 60f0: 1000 addi s0,sp,32 - 60f2: 8400 0x8400 - 60f4: 917f 0x917f - 60f6: 7f84 flw fs1,56(a5) - 60f8: 1a06 slli s4,s4,0x21 - 60fa: 7f84 flw fs1,56(a5) - 60fc: f091 bnez s1,6000 <_start-0x7fffa000> - 60fe: 067e slli a2,a2,0x1f - 6100: 1e1a slli t3,t3,0x26 - 6102: 489f 000a e000 0xe000000a489f - 6108: 000a c.slli zero,0x2 - 610a: 1000 addi s0,sp,32 - 610c: 9100 0x9100 - 610e: 7f84 flw fs1,56(a5) - 6110: 7906 flw fs2,96(sp) - 6112: 1a00 addi s0,sp,304 - 6114: f091 bnez s1,6018 <_start-0x7fff9fe8> - 6116: 067e slli a2,a2,0x1f - 6118: 0079 c.nop 30 - 611a: 1e1a slli t3,t3,0x26 - 611c: e09f 000a c400 0xc400000ae09f - 6122: 1000000b 0x1000000b - 6126: 8900 0x8900 - 6128: 917f 0x917f - 612a: 7f84 flw fs1,56(a5) - 612c: 1a06 slli s4,s4,0x21 - 612e: 7f89 lui t6,0xfffe2 - 6130: f091 bnez s1,6034 <_start-0x7fff9fcc> - 6132: 067e slli a2,a2,0x1f - 6134: 1e1a slli t3,t3,0x26 - 6136: a89f 000d b400 0xb400000da89f - 613c: 000d c.nop 3 - 613e: 1000 addi s0,sp,32 - 6140: 8900 0x8900 - 6142: 917f 0x917f - 6144: 7f84 flw fs1,56(a5) - 6146: 1a06 slli s4,s4,0x21 - 6148: 7f89 lui t6,0xfffe2 - 614a: f091 bnez s1,604e <_start-0x7fff9fb2> - 614c: 067e slli a2,a2,0x1f - 614e: 1e1a slli t3,t3,0x26 - 6150: 009f 0000 0000 0x9f - 6156: 0000 unimp - 6158: c800 sw s0,16(s0) - 615a: 0004 0x4 - 615c: cc00 sw s0,24(s0) - 615e: 0004 0x4 - 6160: 0600 addi s0,sp,768 - 6162: 7900 flw fs0,48(a0) - 6164: 7e00 flw fs0,56(a2) - 6166: 1e00 addi s0,sp,816 - 6168: cc9f 0004 d800 0xd8000004cc9f - 616e: 0004 0x4 - 6170: 0100 addi s0,sp,128 - 6172: 5f00 lw s0,56(a4) - 6174: 04d8 addi a4,sp,580 - 6176: 0000 unimp - 6178: 04e0 addi s0,sp,588 - 617a: 0000 unimp - 617c: 0006 c.slli zero,0x1 - 617e: 0079 c.nop 30 - 6180: 007e c.slli zero,0x1f - 6182: 9f1e add t5,t5,t2 - 6184: 04e0 addi s0,sp,588 - 6186: 0000 unimp - 6188: 0500 addi s0,sp,640 - 618a: 0000 unimp - 618c: 0001 nop - 618e: 005f 0005 0400 0x4000005005f - 6194: 0005 c.nop 1 - 6196: 1100 addi s0,sp,160 - 6198: 7900 flw fs0,48(a0) - 619a: 7e00 flw fs0,56(a2) - 619c: 1e00 addi s0,sp,816 - 619e: 008e008f 0x8e008f - 61a2: 221e fld ft4,448(sp) - 61a4: 007d c.nop 31 - 61a6: 2540 fld fs0,136(a0) - 61a8: 9f22 add t5,t5,s0 - 61aa: 0504 addi s1,sp,640 - 61ac: 0000 unimp - 61ae: 070c addi a1,sp,896 - 61b0: 0000 unimp - 61b2: 0014 0x14 - 61b4: 0079 c.nop 30 - 61b6: 007e c.slli zero,0x1f - 61b8: 8f1e mv t5,t2 - 61ba: 8e00 0x8e00 - 61bc: 1e00 addi s0,sp,816 - 61be: 8e22 mv t3,s0 - 61c0: 7e00 flw fs0,56(a2) - 61c2: 1e00 addi s0,sp,816 - 61c4: 2540 fld fs0,136(a0) - 61c6: 9f22 add t5,t5,s0 - 61c8: 070c addi a1,sp,896 - 61ca: 0000 unimp - 61cc: 0720 addi s0,sp,904 - 61ce: 0000 unimp - 61d0: 001e c.slli zero,0x7 - 61d2: f091 bnez s1,60d6 <_start-0x7fff9f2a> - 61d4: 067e slli a2,a2,0x1f - 61d6: 0089 addi ra,ra,2 - 61d8: 791a flw fs2,164(sp) - 61da: 1e00 addi s0,sp,816 - 61dc: 008e008f 0x8e008f - 61e0: 221e fld ft4,448(sp) - 61e2: f091 bnez s1,60e6 <_start-0x7fff9f1a> - 61e4: 067e slli a2,a2,0x1f - 61e6: 0089 addi ra,ra,2 - 61e8: 8e1a mv t3,t1 - 61ea: 1e00 addi s0,sp,816 - 61ec: 2540 fld fs0,136(a0) - 61ee: 9f22 add t5,t5,s0 - 61f0: 0720 addi s0,sp,904 - 61f2: 0000 unimp - 61f4: 0860 addi s0,sp,28 - 61f6: 0000 unimp - 61f8: 0022 c.slli zero,0x8 - 61fa: f091 bnez s1,60fe <_start-0x7fff9f02> - 61fc: 067e slli a2,a2,0x1f - 61fe: 0089 addi ra,ra,2 - 6200: 791a flw fs2,164(sp) - 6202: 1e00 addi s0,sp,816 - 6204: f091 bnez s1,6108 <_start-0x7fff9ef8> - 6206: 067e slli a2,a2,0x1f - 6208: 2540 fld fs0,136(a0) - 620a: 008e slli ra,ra,0x3 - 620c: 221e fld ft4,448(sp) - 620e: f091 bnez s1,6112 <_start-0x7fff9eee> - 6210: 067e slli a2,a2,0x1f - 6212: 0089 addi ra,ra,2 - 6214: 8e1a mv t3,t1 - 6216: 1e00 addi s0,sp,816 - 6218: 2540 fld fs0,136(a0) - 621a: 9f22 add t5,t5,s0 - 621c: 0860 addi s0,sp,28 - 621e: 0000 unimp - 6220: 0894 addi a3,sp,80 - 6222: 0000 unimp - 6224: 0022 c.slli zero,0x8 - 6226: f091 bnez s1,612a <_start-0x7fff9ed6> - 6228: 067e slli a2,a2,0x1f - 622a: 008c addi a1,sp,64 - 622c: 791a flw fs2,164(sp) - 622e: 1e00 addi s0,sp,816 - 6230: f091 bnez s1,6134 <_start-0x7fff9ecc> - 6232: 067e slli a2,a2,0x1f - 6234: 2540 fld fs0,136(a0) - 6236: 008e slli ra,ra,0x3 - 6238: 221e fld ft4,448(sp) - 623a: f091 bnez s1,613e <_start-0x7fff9ec2> - 623c: 067e slli a2,a2,0x1f - 623e: 008c addi a1,sp,64 - 6240: 8e1a mv t3,t1 - 6242: 1e00 addi s0,sp,816 - 6244: 2540 fld fs0,136(a0) - 6246: 9f22 add t5,t5,s0 - 6248: 0894 addi a3,sp,80 - 624a: 0000 unimp - 624c: 08e0 addi s0,sp,92 - 624e: 0000 unimp - 6250: 0024 addi s1,sp,8 - 6252: f091 bnez s1,6156 <_start-0x7fff9eaa> - 6254: 067e slli a2,a2,0x1f - 6256: ff0a fsw ft2,188(sp) - 6258: 1aff 0x1aff - 625a: 0079 c.nop 30 - 625c: 911e add sp,sp,t2 - 625e: 7ef0 flw fa2,124(a3) - 6260: 4006 0x4006 - 6262: 8e25 xor a2,a2,s1 - 6264: 1e00 addi s0,sp,816 - 6266: 9122 add sp,sp,s0 - 6268: 7ef0 flw fa2,124(a3) - 626a: 0a06 slli s4,s4,0x1 - 626c: ffff 0xffff - 626e: 8e1a mv t3,t1 - 6270: 1e00 addi s0,sp,816 - 6272: 2540 fld fs0,136(a0) - 6274: 9f22 add t5,t5,s0 - 6276: 08e0 addi s0,sp,92 - 6278: 0000 unimp - 627a: 08e4 addi s1,sp,92 - 627c: 0000 unimp - 627e: 0022 c.slli zero,0x8 - 6280: 7f7a flw ft10,188(sp) - 6282: f091 bnez s1,6186 <_start-0x7fff9e7a> - 6284: 067e slli a2,a2,0x1f - 6286: 791a flw fs2,164(sp) - 6288: 1e00 addi s0,sp,816 - 628a: f091 bnez s1,618e <_start-0x7fff9e72> - 628c: 067e slli a2,a2,0x1f - 628e: 2540 fld fs0,136(a0) - 6290: 008e slli ra,ra,0x3 - 6292: 221e fld ft4,448(sp) - 6294: 7f7a flw ft10,188(sp) - 6296: f091 bnez s1,619a <_start-0x7fff9e66> - 6298: 067e slli a2,a2,0x1f - 629a: 8e1a mv t3,t1 - 629c: 1e00 addi s0,sp,816 - 629e: 2540 fld fs0,136(a0) - 62a0: 9f22 add t5,t5,s0 - 62a2: 08e4 addi s1,sp,92 - 62a4: 0000 unimp - 62a6: 08e8 addi a0,sp,92 - 62a8: 0000 unimp - 62aa: 0024 addi s1,sp,8 - 62ac: f091 bnez s1,61b0 <_start-0x7fff9e50> - 62ae: 067e slli a2,a2,0x1f - 62b0: ff0a fsw ft2,188(sp) - 62b2: 1aff 0x1aff - 62b4: 0079 c.nop 30 - 62b6: 911e add sp,sp,t2 - 62b8: 7ef0 flw fa2,124(a3) - 62ba: 4006 0x4006 - 62bc: 8e25 xor a2,a2,s1 - 62be: 1e00 addi s0,sp,816 - 62c0: 9122 add sp,sp,s0 - 62c2: 7ef0 flw fa2,124(a3) - 62c4: 0a06 slli s4,s4,0x1 - 62c6: ffff 0xffff - 62c8: 8e1a mv t3,t1 - 62ca: 1e00 addi s0,sp,816 - 62cc: 2540 fld fs0,136(a0) - 62ce: 9f22 add t5,t5,s0 - 62d0: 08e8 addi a0,sp,92 - 62d2: 0000 unimp - 62d4: 0934 addi a3,sp,152 - 62d6: 0000 unimp - 62d8: 0022 c.slli zero,0x8 - 62da: 7f84 flw fs1,56(a5) - 62dc: f091 bnez s1,61e0 <_start-0x7fff9e20> - 62de: 067e slli a2,a2,0x1f - 62e0: 791a flw fs2,164(sp) - 62e2: 1e00 addi s0,sp,816 - 62e4: f091 bnez s1,61e8 <_start-0x7fff9e18> - 62e6: 067e slli a2,a2,0x1f - 62e8: 2540 fld fs0,136(a0) - 62ea: 008e slli ra,ra,0x3 - 62ec: 221e fld ft4,448(sp) - 62ee: 7f84 flw fs1,56(a5) - 62f0: f091 bnez s1,61f4 <_start-0x7fff9e0c> - 62f2: 067e slli a2,a2,0x1f - 62f4: 8e1a mv t3,t1 - 62f6: 1e00 addi s0,sp,816 - 62f8: 2540 fld fs0,136(a0) - 62fa: 9f22 add t5,t5,s0 - 62fc: 0934 addi a3,sp,152 - 62fe: 0000 unimp - 6300: 0950 addi a2,sp,148 - 6302: 0000 unimp - 6304: 0022 c.slli zero,0x8 - 6306: f091 bnez s1,620a <_start-0x7fff9df6> - 6308: 067e slli a2,a2,0x1f - 630a: 0084 addi s1,sp,64 - 630c: 791a flw fs2,164(sp) - 630e: 1e00 addi s0,sp,816 - 6310: f091 bnez s1,6214 <_start-0x7fff9dec> - 6312: 067e slli a2,a2,0x1f - 6314: 2540 fld fs0,136(a0) - 6316: 008e slli ra,ra,0x3 - 6318: 221e fld ft4,448(sp) - 631a: f091 bnez s1,621e <_start-0x7fff9de2> - 631c: 067e slli a2,a2,0x1f - 631e: 0084 addi s1,sp,64 - 6320: 8e1a mv t3,t1 - 6322: 1e00 addi s0,sp,816 - 6324: 2540 fld fs0,136(a0) - 6326: 9f22 add t5,t5,s0 - 6328: 0950 addi a2,sp,148 - 632a: 0000 unimp - 632c: 0958 addi a4,sp,148 - 632e: 0000 unimp - 6330: 002c addi a1,sp,8 - 6332: f091 bnez s1,6236 <_start-0x7fff9dca> - 6334: 067e slli a2,a2,0x1f - 6336: 0084 addi s1,sp,64 - 6338: 791a flw fs2,164(sp) - 633a: 1e00 addi s0,sp,816 - 633c: 8491 srai s1,s1,0x4 - 633e: 067f 0x67f - 6340: 0084 addi s1,sp,64 - 6342: 911a add sp,sp,t1 - 6344: 7ef0 flw fa2,124(a3) - 6346: 4006 0x4006 - 6348: 1e25 addi t3,t3,-23 - 634a: 9122 add sp,sp,s0 - 634c: 7f84 flw fs1,56(a5) - 634e: 8406 mv s0,ra - 6350: 1a00 addi s0,sp,304 - 6352: f091 bnez s1,6256 <_start-0x7fff9daa> - 6354: 067e slli a2,a2,0x1f - 6356: 0084 addi s1,sp,64 - 6358: 1e1a slli t3,t3,0x26 - 635a: 2540 fld fs0,136(a0) - 635c: 9f22 add t5,t5,s0 - 635e: 0958 addi a4,sp,148 - 6360: 0000 unimp - 6362: 095c addi a5,sp,148 - 6364: 0000 unimp - 6366: 002c addi a1,sp,8 - 6368: 7f85 lui t6,0xfffe1 - 636a: f091 bnez s1,626e <_start-0x7fff9d92> - 636c: 067e slli a2,a2,0x1f - 636e: 791a flw fs2,164(sp) - 6370: 1e00 addi s0,sp,816 - 6372: 7f85 lui t6,0xfffe1 - 6374: 8491 srai s1,s1,0x4 - 6376: 067f 0x67f - 6378: 911a add sp,sp,t1 - 637a: 7ef0 flw fa2,124(a3) - 637c: 4006 0x4006 - 637e: 1e25 addi t3,t3,-23 - 6380: 8522 mv a0,s0 - 6382: 917f 0x917f - 6384: 7f84 flw fs1,56(a5) - 6386: 1a06 slli s4,s4,0x21 - 6388: 7f85 lui t6,0xfffe1 - 638a: f091 bnez s1,628e <_start-0x7fff9d72> - 638c: 067e slli a2,a2,0x1f - 638e: 1e1a slli t3,t3,0x26 - 6390: 2540 fld fs0,136(a0) - 6392: 9f22 add t5,t5,s0 - 6394: 095c addi a5,sp,148 - 6396: 0000 unimp - 6398: 09e0 addi s0,sp,220 - 639a: 0000 unimp - 639c: 0030 addi a2,sp,8 - 639e: 7f85 lui t6,0xfffe1 - 63a0: f091 bnez s1,62a4 <_start-0x7fff9d5c> - 63a2: 067e slli a2,a2,0x1f - 63a4: 911a add sp,sp,t1 - 63a6: 7f84 flw fs1,56(a5) - 63a8: 4006 0x4006 - 63aa: 1e25 addi t3,t3,-23 - 63ac: 7f85 lui t6,0xfffe1 - 63ae: 8491 srai s1,s1,0x4 - 63b0: 067f 0x67f - 63b2: 911a add sp,sp,t1 - 63b4: 7ef0 flw fa2,124(a3) - 63b6: 4006 0x4006 - 63b8: 1e25 addi t3,t3,-23 - 63ba: 8522 mv a0,s0 - 63bc: 917f 0x917f - 63be: 7f84 flw fs1,56(a5) - 63c0: 1a06 slli s4,s4,0x21 - 63c2: 7f85 lui t6,0xfffe1 - 63c4: f091 bnez s1,62c8 <_start-0x7fff9d38> - 63c6: 067e slli a2,a2,0x1f - 63c8: 1e1a slli t3,t3,0x26 - 63ca: 2540 fld fs0,136(a0) - 63cc: 9f22 add t5,t5,s0 - 63ce: 09e0 addi s0,sp,220 - 63d0: 0000 unimp - 63d2: 09ec addi a1,sp,220 - 63d4: 0000 unimp - 63d6: 0030 addi a2,sp,8 - 63d8: f091 bnez s1,62dc <_start-0x7fff9d24> - 63da: 067e slli a2,a2,0x1f - 63dc: 0079 c.nop 30 - 63de: 911a add sp,sp,t1 - 63e0: 7f84 flw fs1,56(a5) - 63e2: 4006 0x4006 - 63e4: 1e25 addi t3,t3,-23 - 63e6: 8491 srai s1,s1,0x4 - 63e8: 067f 0x67f - 63ea: 0079 c.nop 30 - 63ec: 911a add sp,sp,t1 - 63ee: 7ef0 flw fa2,124(a3) - 63f0: 4006 0x4006 - 63f2: 1e25 addi t3,t3,-23 - 63f4: 9122 add sp,sp,s0 - 63f6: 7f84 flw fs1,56(a5) - 63f8: 7906 flw fs2,96(sp) - 63fa: 1a00 addi s0,sp,304 - 63fc: f091 bnez s1,6300 <_start-0x7fff9d00> - 63fe: 067e slli a2,a2,0x1f - 6400: 0079 c.nop 30 - 6402: 1e1a slli t3,t3,0x26 - 6404: 2540 fld fs0,136(a0) - 6406: 9f22 add t5,t5,s0 - 6408: 09ec addi a1,sp,220 - 640a: 0000 unimp - 640c: 0a48 addi a0,sp,276 - 640e: 0000 unimp - 6410: 0030 addi a2,sp,8 - 6412: 7f84 flw fs1,56(a5) - 6414: f091 bnez s1,6318 <_start-0x7fff9ce8> - 6416: 067e slli a2,a2,0x1f - 6418: 911a add sp,sp,t1 - 641a: 7f84 flw fs1,56(a5) - 641c: 4006 0x4006 - 641e: 1e25 addi t3,t3,-23 - 6420: 7f84 flw fs1,56(a5) - 6422: 8491 srai s1,s1,0x4 - 6424: 067f 0x67f - 6426: 911a add sp,sp,t1 - 6428: 7ef0 flw fa2,124(a3) - 642a: 4006 0x4006 - 642c: 1e25 addi t3,t3,-23 - 642e: 8422 mv s0,s0 - 6430: 917f 0x917f - 6432: 7f84 flw fs1,56(a5) - 6434: 1a06 slli s4,s4,0x21 - 6436: 7f84 flw fs1,56(a5) - 6438: f091 bnez s1,633c <_start-0x7fff9cc4> - 643a: 067e slli a2,a2,0x1f - 643c: 1e1a slli t3,t3,0x26 - 643e: 2540 fld fs0,136(a0) - 6440: 9f22 add t5,t5,s0 - 6442: 0a48 addi a0,sp,276 - 6444: 0000 unimp - 6446: 0ae0 addi s0,sp,348 - 6448: 0000 unimp - 644a: 0030 addi a2,sp,8 - 644c: f091 bnez s1,6350 <_start-0x7fff9cb0> - 644e: 067e slli a2,a2,0x1f - 6450: 0079 c.nop 30 - 6452: 911a add sp,sp,t1 - 6454: 7f84 flw fs1,56(a5) - 6456: 4006 0x4006 - 6458: 1e25 addi t3,t3,-23 - 645a: 8491 srai s1,s1,0x4 - 645c: 067f 0x67f - 645e: 0079 c.nop 30 - 6460: 911a add sp,sp,t1 - 6462: 7ef0 flw fa2,124(a3) - 6464: 4006 0x4006 - 6466: 1e25 addi t3,t3,-23 - 6468: 9122 add sp,sp,s0 - 646a: 7f84 flw fs1,56(a5) - 646c: 7906 flw fs2,96(sp) - 646e: 1a00 addi s0,sp,304 - 6470: f091 bnez s1,6374 <_start-0x7fff9c8c> - 6472: 067e slli a2,a2,0x1f - 6474: 0079 c.nop 30 - 6476: 1e1a slli t3,t3,0x26 - 6478: 2540 fld fs0,136(a0) - 647a: 9f22 add t5,t5,s0 - 647c: 0ae0 addi s0,sp,348 - 647e: 0000 unimp - 6480: 0bc4 addi s1,sp,468 - 6482: 0000 unimp - 6484: 0030 addi a2,sp,8 - 6486: 7f89 lui t6,0xfffe2 - 6488: f091 bnez s1,638c <_start-0x7fff9c74> - 648a: 067e slli a2,a2,0x1f - 648c: 911a add sp,sp,t1 - 648e: 7f84 flw fs1,56(a5) - 6490: 4006 0x4006 - 6492: 1e25 addi t3,t3,-23 - 6494: 7f89 lui t6,0xfffe2 - 6496: 8491 srai s1,s1,0x4 - 6498: 067f 0x67f - 649a: 911a add sp,sp,t1 - 649c: 7ef0 flw fa2,124(a3) - 649e: 4006 0x4006 - 64a0: 1e25 addi t3,t3,-23 - 64a2: 8922 mv s2,s0 - 64a4: 917f 0x917f - 64a6: 7f84 flw fs1,56(a5) - 64a8: 1a06 slli s4,s4,0x21 - 64aa: 7f89 lui t6,0xfffe2 - 64ac: f091 bnez s1,63b0 <_start-0x7fff9c50> - 64ae: 067e slli a2,a2,0x1f - 64b0: 1e1a slli t3,t3,0x26 - 64b2: 2540 fld fs0,136(a0) - 64b4: 9f22 add t5,t5,s0 - 64b6: 0da8 addi a0,sp,728 - 64b8: 0000 unimp - 64ba: 0db4 addi a3,sp,728 - 64bc: 0000 unimp - 64be: 0030 addi a2,sp,8 - 64c0: 7f89 lui t6,0xfffe2 - 64c2: f091 bnez s1,63c6 <_start-0x7fff9c3a> - 64c4: 067e slli a2,a2,0x1f - 64c6: 911a add sp,sp,t1 - 64c8: 7f84 flw fs1,56(a5) - 64ca: 4006 0x4006 - 64cc: 1e25 addi t3,t3,-23 - 64ce: 7f89 lui t6,0xfffe2 - 64d0: 8491 srai s1,s1,0x4 - 64d2: 067f 0x67f - 64d4: 911a add sp,sp,t1 - 64d6: 7ef0 flw fa2,124(a3) - 64d8: 4006 0x4006 - 64da: 1e25 addi t3,t3,-23 - 64dc: 8922 mv s2,s0 - 64de: 917f 0x917f - 64e0: 7f84 flw fs1,56(a5) - 64e2: 1a06 slli s4,s4,0x21 - 64e4: 7f89 lui t6,0xfffe2 - 64e6: f091 bnez s1,63ea <_start-0x7fff9c16> - 64e8: 067e slli a2,a2,0x1f - 64ea: 1e1a slli t3,t3,0x26 - 64ec: 2540 fld fs0,136(a0) - 64ee: 9f22 add t5,t5,s0 - ... - 64f8: 04d0 addi a2,sp,580 - 64fa: 0000 unimp - 64fc: 04e8 addi a0,sp,588 - 64fe: 0000 unimp - 6500: 0001 nop - 6502: e85c fsw fa5,20(s0) - 6504: 0004 0x4 - 6506: 2000 fld fs0,0(s0) - 6508: 06000007 0x6000007 - 650c: 8f00 0x8f00 - 650e: 8e00 0x8e00 - 6510: 1e00 addi s0,sp,816 - 6512: 209f 0007 5000 0x50000007209f - 6518: 0009 c.nop 2 - 651a: 0a00 addi s0,sp,272 - 651c: 9100 0x9100 - 651e: 7ef0 flw fa2,124(a3) - 6520: 4006 0x4006 - 6522: 8e25 xor a2,a2,s1 - 6524: 1e00 addi s0,sp,816 - 6526: 509f 0009 5800 0x58000009509f - 652c: 0009 c.nop 2 - 652e: 0f00 addi s0,sp,912 - 6530: 9100 0x9100 - 6532: 7f84 flw fs1,56(a5) - 6534: 8406 mv s0,ra - 6536: 1a00 addi s0,sp,304 - 6538: f091 bnez s1,643c <_start-0x7fff9bc4> - 653a: 067e slli a2,a2,0x1f - 653c: 2540 fld fs0,136(a0) - 653e: 9f1e add t5,t5,t2 - 6540: 0958 addi a4,sp,148 - 6542: 0000 unimp - 6544: 09e0 addi s0,sp,220 - 6546: 0000 unimp - 6548: 7f85000f 0x7f85000f - 654c: 8491 srai s1,s1,0x4 - 654e: 067f 0x67f - 6550: 911a add sp,sp,t1 - 6552: 7ef0 flw fa2,124(a3) - 6554: 4006 0x4006 - 6556: 1e25 addi t3,t3,-23 - 6558: e09f 0009 ec00 0xec000009e09f - 655e: 0009 c.nop 2 - 6560: 0f00 addi s0,sp,912 - 6562: 9100 0x9100 - 6564: 7f84 flw fs1,56(a5) - 6566: 7906 flw fs2,96(sp) - 6568: 1a00 addi s0,sp,304 - 656a: f091 bnez s1,646e <_start-0x7fff9b92> - 656c: 067e slli a2,a2,0x1f - 656e: 2540 fld fs0,136(a0) - 6570: 9f1e add t5,t5,t2 - 6572: 09ec addi a1,sp,220 - 6574: 0000 unimp - 6576: 0a48 addi a0,sp,276 - 6578: 0000 unimp - 657a: 7f84000f 0x7f84000f - 657e: 8491 srai s1,s1,0x4 - 6580: 067f 0x67f - 6582: 911a add sp,sp,t1 - 6584: 7ef0 flw fa2,124(a3) - 6586: 4006 0x4006 - 6588: 1e25 addi t3,t3,-23 - 658a: 489f 000a e000 0xe000000a489f - 6590: 000a c.slli zero,0x2 - 6592: 0f00 addi s0,sp,912 - 6594: 9100 0x9100 - 6596: 7f84 flw fs1,56(a5) - 6598: 7906 flw fs2,96(sp) - 659a: 1a00 addi s0,sp,304 - 659c: f091 bnez s1,64a0 <_start-0x7fff9b60> - 659e: 067e slli a2,a2,0x1f - 65a0: 2540 fld fs0,136(a0) - 65a2: 9f1e add t5,t5,t2 - 65a4: 0ae0 addi s0,sp,348 - 65a6: 0000 unimp - 65a8: 0bc4 addi s1,sp,468 - 65aa: 0000 unimp - 65ac: 7f89000f 0x7f89000f - 65b0: 8491 srai s1,s1,0x4 - 65b2: 067f 0x67f - 65b4: 911a add sp,sp,t1 - 65b6: 7ef0 flw fa2,124(a3) - 65b8: 4006 0x4006 - 65ba: 1e25 addi t3,t3,-23 - 65bc: a89f 000d b400 0xb400000da89f - 65c2: 000d c.nop 3 - 65c4: 0f00 addi s0,sp,912 - 65c6: 8900 0x8900 - 65c8: 917f 0x917f - 65ca: 7f84 flw fs1,56(a5) - 65cc: 1a06 slli s4,s4,0x21 - 65ce: f091 bnez s1,64d2 <_start-0x7fff9b2e> - 65d0: 067e slli a2,a2,0x1f - 65d2: 2540 fld fs0,136(a0) - 65d4: 9f1e add t5,t5,t2 - ... - 65de: 04e0 addi s0,sp,588 - 65e0: 0000 unimp - 65e2: 0654 addi a3,sp,772 - 65e4: 0000 unimp - 65e6: 0001 nop - 65e8: 0064 addi s1,sp,12 - 65ea: 0000 unimp - 65ec: 0000 unimp - 65ee: 0000 unimp - 65f0: c400 sw s0,8(s0) - 65f2: 0004 0x4 - 65f4: c400 sw s0,8(s0) - 65f6: 0300000b 0x300000b - 65fa: 9100 0x9100 - 65fc: 7ef0 flw fa2,124(a3) - 65fe: 0da8 addi a0,sp,728 - 6600: 0000 unimp - 6602: 0db4 addi a3,sp,728 - 6604: 0000 unimp - 6606: f0910003 lb zero,-247(sp) - 660a: 007e c.slli zero,0x1f - 660c: 0000 unimp - 660e: 0000 unimp - 6610: 0000 unimp - 6612: c400 sw s0,8(s0) - 6614: 0004 0x4 - 6616: 2000 fld fs0,0(s0) - 6618: 01000007 vlbuff.v v0,(zero),v0.t - 661c: 6f00 flw fs0,24(a4) - 661e: 0720 addi s0,sp,904 - 6620: 0000 unimp - 6622: 0bc4 addi s1,sp,468 - 6624: 0000 unimp - 6626: f2910003 lb zero,-215(sp) - 662a: a87e fsd ft11,16(sp) - 662c: 000d c.nop 3 - 662e: b400 fsd fs0,40(s0) - 6630: 000d c.nop 3 - 6632: 0300 addi s0,sp,384 - 6634: 9100 0x9100 - 6636: 7ef2 flw ft9,60(sp) - ... - 6640: 04c4 addi s1,sp,580 - 6642: 0000 unimp - 6644: 095c addi a5,sp,148 - 6646: 0000 unimp - 6648: 0001 nop - 664a: 5c59 li s8,-10 - 664c: 0009 c.nop 2 - 664e: c400 sw s0,8(s0) - 6650: 0300000b 0x300000b - 6654: 9100 0x9100 - 6656: 7f86 flw ft11,96(sp) - 6658: 0da8 addi a0,sp,728 - 665a: 0000 unimp - 665c: 0db4 addi a3,sp,728 - 665e: 0000 unimp - 6660: 86910003 lb zero,-1943(sp) - 6664: 007f 0x7f - 6666: 0000 unimp - 6668: 0000 unimp - 666a: 0000 unimp - 666c: 2000 fld fs0,0(s0) - 666e: 0005 c.nop 1 - 6670: 6c00 flw fs0,24(s0) - 6672: 0005 c.nop 1 - 6674: 0100 addi s0,sp,128 - 6676: 5d00 lw s0,56(a0) - 6678: 056c addi a1,sp,652 - 667a: 0000 unimp - 667c: 076c addi a1,sp,908 - 667e: 0000 unimp - 6680: 0006 c.slli zero,0x1 - 6682: 008c addi a1,sp,64 - 6684: 9f1e007b 0x9f1e007b - 6688: 076c addi a1,sp,908 - 668a: 0000 unimp - 668c: 0860 addi s0,sp,28 - 668e: 0000 unimp - 6690: 8091000b 0x8091000b - 6694: 067f 0x67f - 6696: 0089 addi ra,ra,2 - 6698: 7b1a flw fs6,164(sp) - 669a: 1e00 addi s0,sp,816 - 669c: 609f 0008 9400 0x94000008609f - 66a2: 0008 0x8 - 66a4: 0b00 addi s0,sp,400 - 66a6: 9100 0x9100 - 66a8: 7f80 flw fs0,56(a5) - 66aa: 8c06 mv s8,ra - 66ac: 1a00 addi s0,sp,304 - 66ae: 9f1e007b 0x9f1e007b - 66b2: 0894 addi a3,sp,80 - 66b4: 0000 unimp - 66b6: 08e0 addi s0,sp,92 - 66b8: 0000 unimp - 66ba: 000c 0xc - 66bc: 8091 srli s1,s1,0x4 - 66be: 067f 0x67f - 66c0: ff0a fsw ft2,188(sp) - 66c2: 1aff 0x1aff - 66c4: 9f1e007b 0x9f1e007b - 66c8: 08e0 addi s0,sp,92 - 66ca: 0000 unimp - 66cc: 08e4 addi s1,sp,92 - 66ce: 0000 unimp - 66d0: 7f7a000b 0x7f7a000b - 66d4: 8091 srli s1,s1,0x4 - 66d6: 067f 0x67f - 66d8: 7b1a flw fs6,164(sp) - 66da: 1e00 addi s0,sp,816 - 66dc: e49f 0008 e800 0xe8000008e49f - 66e2: 0008 0x8 - 66e4: 0c00 addi s0,sp,528 - 66e6: 9100 0x9100 - 66e8: 7f80 flw fs0,56(a5) - 66ea: 0a06 slli s4,s4,0x1 - 66ec: ffff 0xffff - 66ee: 7b1a flw fs6,164(sp) - 66f0: 1e00 addi s0,sp,816 - 66f2: e89f 0008 1000 0x10000008e89f - 66f8: 0009 c.nop 2 - 66fa: 0b00 addi s0,sp,400 - 66fc: 8400 0x8400 - 66fe: 917f 0x917f - 6700: 7f80 flw fs0,56(a5) - 6702: 1a06 slli s4,s4,0x21 - 6704: 9f1e007b 0x9f1e007b - 6708: 0910 addi a2,sp,144 - 670a: 0000 unimp - 670c: 0934 addi a3,sp,152 - 670e: 0000 unimp - 6710: 0010 0x10 - 6712: 7f84 flw fs1,56(a5) - 6714: 8091 srli s1,s1,0x4 - 6716: 067f 0x67f - 6718: 841a mv s0,t1 - 671a: 917f 0x917f - 671c: 7ef4 flw fa3,124(a3) - 671e: 1a06 slli s4,s4,0x21 - 6720: 9f1e add t5,t5,t2 - 6722: 0934 addi a3,sp,152 - 6724: 0000 unimp - 6726: 0958 addi a4,sp,148 - 6728: 0000 unimp - 672a: 0010 0x10 - 672c: 8091 srli s1,s1,0x4 - 672e: 067f 0x67f - 6730: 0084 addi s1,sp,64 - 6732: 911a add sp,sp,t1 - 6734: 7ef4 flw fa3,124(a3) - 6736: 8406 mv s0,ra - 6738: 1a00 addi s0,sp,304 - 673a: 9f1e add t5,t5,t2 - 673c: 0958 addi a4,sp,148 - 673e: 0000 unimp - 6740: 09e0 addi s0,sp,220 - 6742: 0000 unimp - 6744: 0010 0x10 - 6746: 7f85 lui t6,0xfffe1 - 6748: 8091 srli s1,s1,0x4 - 674a: 067f 0x67f - 674c: 851a mv a0,t1 - 674e: 917f 0x917f - 6750: 7ef4 flw fa3,124(a3) - 6752: 1a06 slli s4,s4,0x21 - 6754: 9f1e add t5,t5,t2 - 6756: 09e0 addi s0,sp,220 - 6758: 0000 unimp - 675a: 09ec addi a1,sp,220 - 675c: 0000 unimp - 675e: 0010 0x10 - 6760: 8091 srli s1,s1,0x4 - 6762: 067f 0x67f - 6764: 0079 c.nop 30 - 6766: 911a add sp,sp,t1 - 6768: 7ef4 flw fa3,124(a3) - 676a: 7906 flw fs2,96(sp) - 676c: 1a00 addi s0,sp,304 - 676e: 9f1e add t5,t5,t2 - 6770: 09ec addi a1,sp,220 - 6772: 0000 unimp - 6774: 0a48 addi a0,sp,276 - 6776: 0000 unimp - 6778: 0010 0x10 - 677a: 7f84 flw fs1,56(a5) - 677c: 8091 srli s1,s1,0x4 - 677e: 067f 0x67f - 6780: 841a mv s0,t1 - 6782: 917f 0x917f - 6784: 7ef4 flw fa3,124(a3) - 6786: 1a06 slli s4,s4,0x21 - 6788: 9f1e add t5,t5,t2 - 678a: 0a48 addi a0,sp,276 - 678c: 0000 unimp - 678e: 0ae0 addi s0,sp,348 - 6790: 0000 unimp - 6792: 0010 0x10 - 6794: 8091 srli s1,s1,0x4 - 6796: 067f 0x67f - 6798: 0079 c.nop 30 - 679a: 911a add sp,sp,t1 - 679c: 7ef4 flw fa3,124(a3) - 679e: 7906 flw fs2,96(sp) - 67a0: 1a00 addi s0,sp,304 - 67a2: 9f1e add t5,t5,t2 - 67a4: 0ae0 addi s0,sp,348 - 67a6: 0000 unimp - 67a8: 0bc4 addi s1,sp,468 - 67aa: 0000 unimp - 67ac: 0010 0x10 - 67ae: 7f89 lui t6,0xfffe2 - 67b0: 8091 srli s1,s1,0x4 - 67b2: 067f 0x67f - 67b4: 891a mv s2,t1 - 67b6: 917f 0x917f - 67b8: 7ef4 flw fa3,124(a3) - 67ba: 1a06 slli s4,s4,0x21 - 67bc: 9f1e add t5,t5,t2 - 67be: 0da8 addi a0,sp,728 - 67c0: 0000 unimp - 67c2: 0db4 addi a3,sp,728 - 67c4: 0000 unimp - 67c6: 0010 0x10 - 67c8: 7f89 lui t6,0xfffe2 - 67ca: 8091 srli s1,s1,0x4 - 67cc: 067f 0x67f - 67ce: 891a mv s2,t1 - 67d0: 917f 0x917f - 67d2: 7ef4 flw fa3,124(a3) - 67d4: 1a06 slli s4,s4,0x21 - 67d6: 9f1e add t5,t5,t2 - ... - 67e0: 0520 addi s0,sp,648 - 67e2: 0000 unimp - 67e4: 052c addi a1,sp,648 - 67e6: 0000 unimp - 67e8: 0001 nop - 67ea: 2c5f 0005 3400 0x340000052c5f - 67f0: 0005 c.nop 1 - 67f2: 0600 addi s0,sp,768 - 67f4: 8500 0x8500 - 67f6: 7b00 flw fs0,48(a4) - 67f8: 1e00 addi s0,sp,816 - 67fa: 349f 0005 5800 0x58000005349f - 6800: 0005 c.nop 1 - 6802: 0100 addi s0,sp,128 - 6804: 5f00 lw s0,56(a4) - 6806: 0558 addi a4,sp,644 - 6808: 0000 unimp - 680a: 056c addi a1,sp,652 - 680c: 0000 unimp - 680e: 000e c.slli zero,0x3 - 6810: 0085 addi ra,ra,1 - 6812: 7d1e007b 0x7d1e007b - 6816: 4000 lw s0,0(s0) - 6818: 2225 jal 6940 <_start-0x7fff96c0> - 681a: 0076 c.slli zero,0x1d - 681c: 9f22 add t5,t5,s0 - 681e: 056c addi a1,sp,652 - 6820: 0000 unimp - 6822: 0578 addi a4,sp,652 - 6824: 0000 unimp - 6826: 0011 c.nop 4 - 6828: 0085 addi ra,ra,1 - 682a: 8c1e007b 0x8c1e007b - 682e: 7b00 flw fs0,48(a4) - 6830: 1e00 addi s0,sp,816 - 6832: 2540 fld fs0,136(a0) - 6834: 7622 flw fa2,40(sp) - 6836: 2200 fld fs0,0(a2) - 6838: 789f 0005 6400 0x64000005789f - 683e: 14000007 0x14000007 - 6842: 8500 0x8500 - 6844: 7b00 flw fs0,48(a4) - 6846: 1e00 addi s0,sp,816 - 6848: 0082 c.slli64 ra - 684a: 008c addi a1,sp,64 - 684c: 221e fld ft4,448(sp) - 684e: 008c addi a1,sp,64 - 6850: 401e007b 0x401e007b - 6854: 2225 jal 697c <_start-0x7fff9684> - 6856: 649f 0007 6c00 0x6c000007649f - 685c: 18000007 vlsb.v v0,(zero),zero,v0.t - 6860: 9100 0x9100 - 6862: 7f80 flw fs0,56(a5) - 6864: 4006 0x4006 - 6866: 7b25 lui s6,0xfffe9 - 6868: 1e00 addi s0,sp,816 - 686a: 0082 c.slli64 ra - 686c: 008c addi a1,sp,64 - 686e: 221e fld ft4,448(sp) - 6870: 008c addi a1,sp,64 - 6872: 401e007b 0x401e007b - 6876: 2225 jal 699e <_start-0x7fff9662> - 6878: 6c9f 0007 6000 0x600000076c9f - 687e: 0008 0x8 - 6880: 2200 fld fs0,0(a2) - 6882: 9100 0x9100 - 6884: 7f80 flw fs0,56(a5) - 6886: 4006 0x4006 - 6888: 7b25 lui s6,0xfffe9 - 688a: 1e00 addi s0,sp,816 - 688c: 8091 srli s1,s1,0x4 - 688e: 067f 0x67f - 6890: 0089 addi ra,ra,2 - 6892: 821a mv tp,t1 - 6894: 1e00 addi s0,sp,816 - 6896: 9122 add sp,sp,s0 - 6898: 7f80 flw fs0,56(a5) - 689a: 8906 mv s2,ra - 689c: 1a00 addi s0,sp,304 - 689e: 401e007b 0x401e007b - 68a2: 2225 jal 69ca <_start-0x7fff9636> - 68a4: 609f 0008 9400 0x94000008609f - 68aa: 0008 0x8 - 68ac: 2200 fld fs0,0(a2) - 68ae: 9100 0x9100 - 68b0: 7f80 flw fs0,56(a5) - 68b2: 4006 0x4006 - 68b4: 7b25 lui s6,0xfffe9 - 68b6: 1e00 addi s0,sp,816 - 68b8: 8091 srli s1,s1,0x4 - 68ba: 067f 0x67f - 68bc: 008c addi a1,sp,64 - 68be: 821a mv tp,t1 - 68c0: 1e00 addi s0,sp,816 - 68c2: 9122 add sp,sp,s0 - 68c4: 7f80 flw fs0,56(a5) - 68c6: 8c06 mv s8,ra - 68c8: 1a00 addi s0,sp,304 - 68ca: 401e007b 0x401e007b - 68ce: 2225 jal 69f6 <_start-0x7fff960a> - 68d0: 949f 0008 e000 0xe0000008949f - 68d6: 0008 0x8 - 68d8: 2400 fld fs0,8(s0) - 68da: 9100 0x9100 - 68dc: 7f80 flw fs0,56(a5) - 68de: 4006 0x4006 - 68e0: 7b25 lui s6,0xfffe9 - 68e2: 1e00 addi s0,sp,816 - 68e4: 8091 srli s1,s1,0x4 - 68e6: 067f 0x67f - 68e8: ff0a fsw ft2,188(sp) - 68ea: 1aff 0x1aff - 68ec: 0082 c.slli64 ra - 68ee: 221e fld ft4,448(sp) - 68f0: 8091 srli s1,s1,0x4 - 68f2: 067f 0x67f - 68f4: ff0a fsw ft2,188(sp) - 68f6: 1aff 0x1aff - 68f8: 401e007b 0x401e007b - 68fc: 2225 jal 6a24 <_start-0x7fff95dc> - 68fe: e09f 0008 e400 0xe4000008e09f - 6904: 0008 0x8 - 6906: 2200 fld fs0,0(a2) - 6908: 9100 0x9100 - 690a: 7f80 flw fs0,56(a5) - 690c: 4006 0x4006 - 690e: 7b25 lui s6,0xfffe9 - 6910: 1e00 addi s0,sp,816 - 6912: 7f7a flw ft10,188(sp) - 6914: 8091 srli s1,s1,0x4 - 6916: 067f 0x67f - 6918: 821a mv tp,t1 - 691a: 1e00 addi s0,sp,816 - 691c: 7a22 flw fs4,40(sp) - 691e: 917f 0x917f - 6920: 7f80 flw fs0,56(a5) - 6922: 1a06 slli s4,s4,0x21 - 6924: 401e007b 0x401e007b - 6928: 2225 jal 6a50 <_start-0x7fff95b0> - 692a: e49f 0008 e800 0xe8000008e49f - 6930: 0008 0x8 - 6932: 2400 fld fs0,8(s0) - 6934: 9100 0x9100 - 6936: 7f80 flw fs0,56(a5) - 6938: 4006 0x4006 - 693a: 7b25 lui s6,0xfffe9 - 693c: 1e00 addi s0,sp,816 - 693e: 8091 srli s1,s1,0x4 - 6940: 067f 0x67f - 6942: ff0a fsw ft2,188(sp) - 6944: 1aff 0x1aff - 6946: 0082 c.slli64 ra - 6948: 221e fld ft4,448(sp) - 694a: 8091 srli s1,s1,0x4 - 694c: 067f 0x67f - 694e: ff0a fsw ft2,188(sp) - 6950: 1aff 0x1aff - 6952: 401e007b 0x401e007b - 6956: 2225 jal 6a7e <_start-0x7fff9582> - 6958: e89f 0008 1000 0x10000008e89f - 695e: 0009 c.nop 2 - 6960: 2200 fld fs0,0(a2) - 6962: 9100 0x9100 - 6964: 7f80 flw fs0,56(a5) - 6966: 4006 0x4006 - 6968: 7b25 lui s6,0xfffe9 - 696a: 1e00 addi s0,sp,816 - 696c: 7f84 flw fs1,56(a5) - 696e: 8091 srli s1,s1,0x4 - 6970: 067f 0x67f - 6972: 821a mv tp,t1 - 6974: 1e00 addi s0,sp,816 - 6976: 8422 mv s0,s0 - 6978: 917f 0x917f - 697a: 7f80 flw fs0,56(a5) - 697c: 1a06 slli s4,s4,0x21 - 697e: 401e007b 0x401e007b - 6982: 2225 jal 6aaa <_start-0x7fff9556> - 6984: 109f 0009 2000 0x20000009109f - 698a: 0009 c.nop 2 - 698c: 2c00 fld fs0,24(s0) - 698e: 8400 0x8400 - 6990: 917f 0x917f - 6992: 7ef4 flw fa3,124(a3) - 6994: 1a06 slli s4,s4,0x21 - 6996: 8091 srli s1,s1,0x4 - 6998: 067f 0x67f - 699a: 2540 fld fs0,136(a0) - 699c: 841e mv s0,t2 - 699e: 917f 0x917f - 69a0: 7f80 flw fs0,56(a5) - 69a2: 1a06 slli s4,s4,0x21 - 69a4: 0082 c.slli64 ra - 69a6: 221e fld ft4,448(sp) - 69a8: 7f84 flw fs1,56(a5) - 69aa: 8091 srli s1,s1,0x4 - 69ac: 067f 0x67f - 69ae: 841a mv s0,t1 - 69b0: 917f 0x917f - 69b2: 7ef4 flw fa3,124(a3) - 69b4: 1a06 slli s4,s4,0x21 - 69b6: 401e 0x401e - 69b8: 2225 jal 6ae0 <_start-0x7fff9520> - 69ba: 209f 0009 3400 0x34000009209f - 69c0: 0009 c.nop 2 - 69c2: 3000 fld fs0,32(s0) - 69c4: 8400 0x8400 - 69c6: 917f 0x917f - 69c8: 7ef4 flw fa3,124(a3) - 69ca: 1a06 slli s4,s4,0x21 - 69cc: 8091 srli s1,s1,0x4 - 69ce: 067f 0x67f - 69d0: 2540 fld fs0,136(a0) - 69d2: 841e mv s0,t2 - 69d4: 917f 0x917f - 69d6: 7f80 flw fs0,56(a5) - 69d8: 1a06 slli s4,s4,0x21 - 69da: f491 bnez s1,68e6 <_start-0x7fff971a> - 69dc: 067e slli a2,a2,0x1f - 69de: 2540 fld fs0,136(a0) - 69e0: 221e fld ft4,448(sp) - 69e2: 7f84 flw fs1,56(a5) - 69e4: 8091 srli s1,s1,0x4 - 69e6: 067f 0x67f - 69e8: 841a mv s0,t1 - 69ea: 917f 0x917f - 69ec: 7ef4 flw fa3,124(a3) - 69ee: 1a06 slli s4,s4,0x21 - 69f0: 401e 0x401e - 69f2: 2225 jal 6b1a <_start-0x7fff94e6> - 69f4: 349f 0009 5800 0x58000009349f - 69fa: 0009 c.nop 2 - 69fc: 3000 fld fs0,32(s0) - 69fe: 9100 0x9100 - 6a00: 7ef4 flw fa3,124(a3) - 6a02: 8406 mv s0,ra - 6a04: 1a00 addi s0,sp,304 - 6a06: 8091 srli s1,s1,0x4 - 6a08: 067f 0x67f - 6a0a: 2540 fld fs0,136(a0) - 6a0c: 911e add sp,sp,t2 - 6a0e: 7f80 flw fs0,56(a5) - 6a10: 8406 mv s0,ra - 6a12: 1a00 addi s0,sp,304 - 6a14: f491 bnez s1,6920 <_start-0x7fff96e0> - 6a16: 067e slli a2,a2,0x1f - 6a18: 2540 fld fs0,136(a0) - 6a1a: 221e fld ft4,448(sp) - 6a1c: 8091 srli s1,s1,0x4 - 6a1e: 067f 0x67f - 6a20: 0084 addi s1,sp,64 - 6a22: 911a add sp,sp,t1 - 6a24: 7ef4 flw fa3,124(a3) - 6a26: 8406 mv s0,ra - 6a28: 1a00 addi s0,sp,304 - 6a2a: 401e 0x401e - 6a2c: 2225 jal 6b54 <_start-0x7fff94ac> - 6a2e: 589f 0009 e000 0xe0000009589f - 6a34: 0009 c.nop 2 - 6a36: 3000 fld fs0,32(s0) - 6a38: 8500 0x8500 - 6a3a: 917f 0x917f - 6a3c: 7ef4 flw fa3,124(a3) - 6a3e: 1a06 slli s4,s4,0x21 - 6a40: 8091 srli s1,s1,0x4 - 6a42: 067f 0x67f - 6a44: 2540 fld fs0,136(a0) - 6a46: 851e mv a0,t2 - 6a48: 917f 0x917f - 6a4a: 7f80 flw fs0,56(a5) - 6a4c: 1a06 slli s4,s4,0x21 - 6a4e: f491 bnez s1,695a <_start-0x7fff96a6> - 6a50: 067e slli a2,a2,0x1f - 6a52: 2540 fld fs0,136(a0) - 6a54: 221e fld ft4,448(sp) - 6a56: 7f85 lui t6,0xfffe1 - 6a58: 8091 srli s1,s1,0x4 - 6a5a: 067f 0x67f - 6a5c: 851a mv a0,t1 - 6a5e: 917f 0x917f - 6a60: 7ef4 flw fa3,124(a3) - 6a62: 1a06 slli s4,s4,0x21 - 6a64: 401e 0x401e - 6a66: 2225 jal 6b8e <_start-0x7fff9472> - 6a68: e09f 0009 ec00 0xec000009e09f - 6a6e: 0009 c.nop 2 - 6a70: 3000 fld fs0,32(s0) - 6a72: 9100 0x9100 - 6a74: 7ef4 flw fa3,124(a3) - 6a76: 7906 flw fs2,96(sp) - 6a78: 1a00 addi s0,sp,304 - 6a7a: 8091 srli s1,s1,0x4 - 6a7c: 067f 0x67f - 6a7e: 2540 fld fs0,136(a0) - 6a80: 911e add sp,sp,t2 - 6a82: 7f80 flw fs0,56(a5) - 6a84: 7906 flw fs2,96(sp) - 6a86: 1a00 addi s0,sp,304 - 6a88: f491 bnez s1,6994 <_start-0x7fff966c> - 6a8a: 067e slli a2,a2,0x1f - 6a8c: 2540 fld fs0,136(a0) - 6a8e: 221e fld ft4,448(sp) - 6a90: 8091 srli s1,s1,0x4 - 6a92: 067f 0x67f - 6a94: 0079 c.nop 30 - 6a96: 911a add sp,sp,t1 - 6a98: 7ef4 flw fa3,124(a3) - 6a9a: 7906 flw fs2,96(sp) - 6a9c: 1a00 addi s0,sp,304 - 6a9e: 401e 0x401e - 6aa0: 2225 jal 6bc8 <_start-0x7fff9438> - 6aa2: ec9f 0009 4800 0x48000009ec9f - 6aa8: 000a c.slli zero,0x2 - 6aaa: 3000 fld fs0,32(s0) - 6aac: 8400 0x8400 - 6aae: 917f 0x917f - 6ab0: 7ef4 flw fa3,124(a3) - 6ab2: 1a06 slli s4,s4,0x21 - 6ab4: 8091 srli s1,s1,0x4 - 6ab6: 067f 0x67f - 6ab8: 2540 fld fs0,136(a0) - 6aba: 841e mv s0,t2 - 6abc: 917f 0x917f - 6abe: 7f80 flw fs0,56(a5) - 6ac0: 1a06 slli s4,s4,0x21 - 6ac2: f491 bnez s1,69ce <_start-0x7fff9632> - 6ac4: 067e slli a2,a2,0x1f - 6ac6: 2540 fld fs0,136(a0) - 6ac8: 221e fld ft4,448(sp) - 6aca: 7f84 flw fs1,56(a5) - 6acc: 8091 srli s1,s1,0x4 - 6ace: 067f 0x67f - 6ad0: 841a mv s0,t1 - 6ad2: 917f 0x917f - 6ad4: 7ef4 flw fa3,124(a3) - 6ad6: 1a06 slli s4,s4,0x21 - 6ad8: 401e 0x401e - 6ada: 2225 jal 6c02 <_start-0x7fff93fe> - 6adc: 489f 000a e000 0xe000000a489f - 6ae2: 000a c.slli zero,0x2 - 6ae4: 3000 fld fs0,32(s0) - 6ae6: 9100 0x9100 - 6ae8: 7ef4 flw fa3,124(a3) - 6aea: 7906 flw fs2,96(sp) - 6aec: 1a00 addi s0,sp,304 - 6aee: 8091 srli s1,s1,0x4 - 6af0: 067f 0x67f - 6af2: 2540 fld fs0,136(a0) - 6af4: 911e add sp,sp,t2 - 6af6: 7f80 flw fs0,56(a5) - 6af8: 7906 flw fs2,96(sp) - 6afa: 1a00 addi s0,sp,304 - 6afc: f491 bnez s1,6a08 <_start-0x7fff95f8> - 6afe: 067e slli a2,a2,0x1f - 6b00: 2540 fld fs0,136(a0) - 6b02: 221e fld ft4,448(sp) - 6b04: 8091 srli s1,s1,0x4 - 6b06: 067f 0x67f - 6b08: 0079 c.nop 30 - 6b0a: 911a add sp,sp,t1 - 6b0c: 7ef4 flw fa3,124(a3) - 6b0e: 7906 flw fs2,96(sp) - 6b10: 1a00 addi s0,sp,304 - 6b12: 401e 0x401e - 6b14: 2225 jal 6c3c <_start-0x7fff93c4> - 6b16: e09f 000a c400 0xc400000ae09f - 6b1c: 3000000b 0x3000000b - 6b20: 8900 0x8900 - 6b22: 917f 0x917f - 6b24: 7ef4 flw fa3,124(a3) - 6b26: 1a06 slli s4,s4,0x21 - 6b28: 8091 srli s1,s1,0x4 - 6b2a: 067f 0x67f - 6b2c: 2540 fld fs0,136(a0) - 6b2e: 891e mv s2,t2 - 6b30: 917f 0x917f - 6b32: 7f80 flw fs0,56(a5) - 6b34: 1a06 slli s4,s4,0x21 - 6b36: f491 bnez s1,6a42 <_start-0x7fff95be> - 6b38: 067e slli a2,a2,0x1f - 6b3a: 2540 fld fs0,136(a0) - 6b3c: 221e fld ft4,448(sp) - 6b3e: 7f89 lui t6,0xfffe2 - 6b40: 8091 srli s1,s1,0x4 - 6b42: 067f 0x67f - 6b44: 891a mv s2,t1 - 6b46: 917f 0x917f - 6b48: 7ef4 flw fa3,124(a3) - 6b4a: 1a06 slli s4,s4,0x21 - 6b4c: 401e 0x401e - 6b4e: 2225 jal 6c76 <_start-0x7fff938a> - 6b50: a89f 000d b400 0xb400000da89f - 6b56: 000d c.nop 3 - 6b58: 3000 fld fs0,32(s0) - 6b5a: 8900 0x8900 - 6b5c: 917f 0x917f - 6b5e: 7ef4 flw fa3,124(a3) - 6b60: 1a06 slli s4,s4,0x21 - 6b62: 8091 srli s1,s1,0x4 - 6b64: 067f 0x67f - 6b66: 2540 fld fs0,136(a0) - 6b68: 891e mv s2,t2 - 6b6a: 917f 0x917f - 6b6c: 7f80 flw fs0,56(a5) - 6b6e: 1a06 slli s4,s4,0x21 - 6b70: f491 bnez s1,6a7c <_start-0x7fff9584> - 6b72: 067e slli a2,a2,0x1f - 6b74: 2540 fld fs0,136(a0) - 6b76: 221e fld ft4,448(sp) - 6b78: 7f89 lui t6,0xfffe2 - 6b7a: 8091 srli s1,s1,0x4 - 6b7c: 067f 0x67f - 6b7e: 891a mv s2,t1 - 6b80: 917f 0x917f - 6b82: 7ef4 flw fa3,124(a3) - 6b84: 1a06 slli s4,s4,0x21 - 6b86: 401e 0x401e - 6b88: 2225 jal 6cb0 <_start-0x7fff9350> - 6b8a: 009f 0000 0000 0x9f - 6b90: 0000 unimp - 6b92: 2400 fld fs0,8(s0) - 6b94: 0005 c.nop 1 - 6b96: 7800 flw fs0,48(s0) - 6b98: 0005 c.nop 1 - 6b9a: 0100 addi s0,sp,128 - 6b9c: 5600 lw s0,40(a2) - 6b9e: 0578 addi a4,sp,652 - 6ba0: 0000 unimp - 6ba2: 076c addi a1,sp,908 - 6ba4: 0000 unimp - 6ba6: 0006 c.slli zero,0x1 - 6ba8: 0082 c.slli64 ra - 6baa: 008c addi a1,sp,64 - 6bac: 9f1e add t5,t5,t2 - 6bae: 076c addi a1,sp,908 - 6bb0: 0000 unimp - 6bb2: 0860 addi s0,sp,28 - 6bb4: 0000 unimp - 6bb6: 8091000b 0x8091000b - 6bba: 067f 0x67f - 6bbc: 0089 addi ra,ra,2 - 6bbe: 821a mv tp,t1 - 6bc0: 1e00 addi s0,sp,816 - 6bc2: 609f 0008 9400 0x94000008609f - 6bc8: 0008 0x8 - 6bca: 0b00 addi s0,sp,400 - 6bcc: 9100 0x9100 - 6bce: 7f80 flw fs0,56(a5) - 6bd0: 8c06 mv s8,ra - 6bd2: 1a00 addi s0,sp,304 - 6bd4: 0082 c.slli64 ra - 6bd6: 9f1e add t5,t5,t2 - 6bd8: 0894 addi a3,sp,80 - 6bda: 0000 unimp - 6bdc: 08e0 addi s0,sp,92 - 6bde: 0000 unimp - 6be0: 000c 0xc - 6be2: 8091 srli s1,s1,0x4 - 6be4: 067f 0x67f - 6be6: ff0a fsw ft2,188(sp) - 6be8: 1aff 0x1aff - 6bea: 0082 c.slli64 ra - 6bec: 9f1e add t5,t5,t2 - 6bee: 08e0 addi s0,sp,92 - 6bf0: 0000 unimp - 6bf2: 08e4 addi s1,sp,92 - 6bf4: 0000 unimp - 6bf6: 7f7a000b 0x7f7a000b - 6bfa: 8091 srli s1,s1,0x4 - 6bfc: 067f 0x67f - 6bfe: 821a mv tp,t1 - 6c00: 1e00 addi s0,sp,816 - 6c02: e49f 0008 e800 0xe8000008e49f - 6c08: 0008 0x8 - 6c0a: 0c00 addi s0,sp,528 - 6c0c: 9100 0x9100 - 6c0e: 7f80 flw fs0,56(a5) - 6c10: 0a06 slli s4,s4,0x1 - 6c12: ffff 0xffff - 6c14: 821a mv tp,t1 - 6c16: 1e00 addi s0,sp,816 - 6c18: e89f 0008 2000 0x20000008e89f - 6c1e: 0009 c.nop 2 - 6c20: 0b00 addi s0,sp,400 - 6c22: 8400 0x8400 - 6c24: 917f 0x917f - 6c26: 7f80 flw fs0,56(a5) - 6c28: 1a06 slli s4,s4,0x21 - 6c2a: 0082 c.slli64 ra - 6c2c: 9f1e add t5,t5,t2 - 6c2e: 0920 addi s0,sp,152 - 6c30: 0000 unimp - 6c32: 0934 addi a3,sp,152 - 6c34: 0000 unimp - 6c36: 7f84000f 0x7f84000f - 6c3a: 8091 srli s1,s1,0x4 - 6c3c: 067f 0x67f - 6c3e: 911a add sp,sp,t1 - 6c40: 7ef4 flw fa3,124(a3) - 6c42: 4006 0x4006 - 6c44: 1e25 addi t3,t3,-23 - 6c46: 349f 0009 5800 0x58000009349f - 6c4c: 0009 c.nop 2 - 6c4e: 0f00 addi s0,sp,912 - 6c50: 9100 0x9100 - 6c52: 7f80 flw fs0,56(a5) - 6c54: 8406 mv s0,ra - 6c56: 1a00 addi s0,sp,304 - 6c58: f491 bnez s1,6b64 <_start-0x7fff949c> - 6c5a: 067e slli a2,a2,0x1f - 6c5c: 2540 fld fs0,136(a0) - 6c5e: 9f1e add t5,t5,t2 - 6c60: 0958 addi a4,sp,148 - 6c62: 0000 unimp - 6c64: 09e0 addi s0,sp,220 - 6c66: 0000 unimp - 6c68: 7f85000f 0x7f85000f - 6c6c: 8091 srli s1,s1,0x4 - 6c6e: 067f 0x67f - 6c70: 911a add sp,sp,t1 - 6c72: 7ef4 flw fa3,124(a3) - 6c74: 4006 0x4006 - 6c76: 1e25 addi t3,t3,-23 - 6c78: e09f 0009 ec00 0xec000009e09f - 6c7e: 0009 c.nop 2 - 6c80: 0f00 addi s0,sp,912 - 6c82: 9100 0x9100 - 6c84: 7f80 flw fs0,56(a5) - 6c86: 7906 flw fs2,96(sp) - 6c88: 1a00 addi s0,sp,304 - 6c8a: f491 bnez s1,6b96 <_start-0x7fff946a> - 6c8c: 067e slli a2,a2,0x1f - 6c8e: 2540 fld fs0,136(a0) - 6c90: 9f1e add t5,t5,t2 - 6c92: 09ec addi a1,sp,220 - 6c94: 0000 unimp - 6c96: 0a48 addi a0,sp,276 - 6c98: 0000 unimp - 6c9a: 7f84000f 0x7f84000f - 6c9e: 8091 srli s1,s1,0x4 - 6ca0: 067f 0x67f - 6ca2: 911a add sp,sp,t1 - 6ca4: 7ef4 flw fa3,124(a3) - 6ca6: 4006 0x4006 - 6ca8: 1e25 addi t3,t3,-23 - 6caa: 489f 000a e000 0xe000000a489f - 6cb0: 000a c.slli zero,0x2 - 6cb2: 0f00 addi s0,sp,912 - 6cb4: 9100 0x9100 - 6cb6: 7f80 flw fs0,56(a5) - 6cb8: 7906 flw fs2,96(sp) - 6cba: 1a00 addi s0,sp,304 - 6cbc: f491 bnez s1,6bc8 <_start-0x7fff9438> - 6cbe: 067e slli a2,a2,0x1f - 6cc0: 2540 fld fs0,136(a0) - 6cc2: 9f1e add t5,t5,t2 - 6cc4: 0ae0 addi s0,sp,348 - 6cc6: 0000 unimp - 6cc8: 0bc4 addi s1,sp,468 - 6cca: 0000 unimp - 6ccc: 7f89000f 0x7f89000f - 6cd0: 8091 srli s1,s1,0x4 - 6cd2: 067f 0x67f - 6cd4: 911a add sp,sp,t1 - 6cd6: 7ef4 flw fa3,124(a3) - 6cd8: 4006 0x4006 - 6cda: 1e25 addi t3,t3,-23 - 6cdc: a89f 000d b400 0xb400000da89f - 6ce2: 000d c.nop 3 - 6ce4: 0f00 addi s0,sp,912 - 6ce6: 8900 0x8900 - 6ce8: 917f 0x917f - 6cea: 7f80 flw fs0,56(a5) - 6cec: 1a06 slli s4,s4,0x21 - 6cee: f491 bnez s1,6bfa <_start-0x7fff9406> - 6cf0: 067e slli a2,a2,0x1f - 6cf2: 2540 fld fs0,136(a0) - 6cf4: 9f1e add t5,t5,t2 - ... - 6cfe: 0534 addi a3,sp,648 - 6d00: 0000 unimp - 6d02: 0548 addi a0,sp,644 - 6d04: 0000 unimp - 6d06: 0001 nop - 6d08: 0061 c.nop 24 - 6d0a: 0000 unimp - 6d0c: 0000 unimp - 6d0e: 0000 unimp - 6d10: 1c00 addi s0,sp,560 - 6d12: 0005 c.nop 1 - 6d14: c400 sw s0,8(s0) - 6d16: 0300000b 0x300000b - 6d1a: 9100 0x9100 - 6d1c: 7f80 flw fs0,56(a5) - 6d1e: 0da8 addi a0,sp,728 - 6d20: 0000 unimp - 6d22: 0db4 addi a3,sp,728 - 6d24: 0000 unimp - 6d26: 80910003 lb zero,-2039(sp) - 6d2a: 007f 0x7f - 6d2c: 0000 unimp - 6d2e: 0000 unimp - 6d30: 0000 unimp - 6d32: 1c00 addi s0,sp,560 - 6d34: 0005 c.nop 1 - 6d36: 2000 fld fs0,0(s0) - 6d38: 0009 c.nop 2 - 6d3a: 0100 addi s0,sp,128 - 6d3c: 6200 flw fs0,0(a2) - 6d3e: 0920 addi s0,sp,152 - 6d40: 0000 unimp - 6d42: 0bc4 addi s1,sp,468 - 6d44: 0000 unimp - 6d46: f6910003 lb zero,-151(sp) - 6d4a: a87e fsd ft11,16(sp) - 6d4c: 000d c.nop 3 - 6d4e: b400 fsd fs0,40(s0) - 6d50: 000d c.nop 3 - 6d52: 0300 addi s0,sp,384 - 6d54: 9100 0x9100 - 6d56: 7ef6 flw ft9,124(sp) - ... - 6d60: 051c addi a5,sp,640 - 6d62: 0000 unimp - 6d64: 0764 addi s1,sp,908 - 6d66: 0000 unimp - 6d68: 0001 nop - 6d6a: 6465 lui s0,0x19 - 6d6c: c4000007 0xc4000007 - 6d70: 0300000b 0x300000b - 6d74: 9100 0x9100 - 6d76: 7f82 flw ft11,32(sp) - 6d78: 0da8 addi a0,sp,728 - 6d7a: 0000 unimp - 6d7c: 0db4 addi a3,sp,728 - 6d7e: 0000 unimp - 6d80: 82910003 lb zero,-2007(sp) - 6d84: 007f 0x7f - 6d86: 0000 unimp - 6d88: 0000 unimp - 6d8a: 0000 unimp - 6d8c: 6000 flw fs0,0(s0) - 6d8e: 0005 c.nop 1 - 6d90: a800 fsd fs0,16(s0) - 6d92: 0005 c.nop 1 - 6d94: 0100 addi s0,sp,128 - 6d96: 5c00 lw s0,56(s0) - 6d98: 05a8 addi a0,sp,712 - 6d9a: 0000 unimp - 6d9c: 0910 addi a2,sp,144 - 6d9e: 0000 unimp - 6da0: 0006 c.slli zero,0x1 - 6da2: 008e007b 0x8e007b - 6da6: 9f1e add t5,t5,t2 - 6da8: 0910 addi a2,sp,144 - 6daa: 0000 unimp - 6dac: 0934 addi a3,sp,152 - 6dae: 0000 unimp - 6db0: 7f84000b 0x7f84000b - 6db4: f491 bnez s1,6cc0 <_start-0x7fff9340> - 6db6: 067e slli a2,a2,0x1f - 6db8: 8e1a mv t3,t1 - 6dba: 1e00 addi s0,sp,816 - 6dbc: 349f 0009 5000 0x50000009349f - 6dc2: 0009 c.nop 2 - 6dc4: 0b00 addi s0,sp,400 - 6dc6: 9100 0x9100 - 6dc8: 7ef4 flw fa3,124(a3) - 6dca: 8406 mv s0,ra - 6dcc: 1a00 addi s0,sp,304 - 6dce: 008e slli ra,ra,0x3 - 6dd0: 9f1e add t5,t5,t2 - 6dd2: 0950 addi a2,sp,148 - 6dd4: 0000 unimp - 6dd6: 0958 addi a4,sp,148 - 6dd8: 0000 unimp - 6dda: 0010 0x10 - 6ddc: f491 bnez s1,6ce8 <_start-0x7fff9318> - 6dde: 067e slli a2,a2,0x1f - 6de0: 0084 addi s1,sp,64 - 6de2: 911a add sp,sp,t1 - 6de4: 7f84 flw fs1,56(a5) - 6de6: 8406 mv s0,ra - 6de8: 1a00 addi s0,sp,304 - 6dea: 9f1e add t5,t5,t2 - 6dec: 0958 addi a4,sp,148 - 6dee: 0000 unimp - 6df0: 09e0 addi s0,sp,220 - 6df2: 0000 unimp - 6df4: 0010 0x10 - 6df6: 7f85 lui t6,0xfffe1 - 6df8: f491 bnez s1,6d04 <_start-0x7fff92fc> - 6dfa: 067e slli a2,a2,0x1f - 6dfc: 851a mv a0,t1 - 6dfe: 917f 0x917f - 6e00: 7f84 flw fs1,56(a5) - 6e02: 1a06 slli s4,s4,0x21 - 6e04: 9f1e add t5,t5,t2 - 6e06: 09e0 addi s0,sp,220 - 6e08: 0000 unimp - 6e0a: 09ec addi a1,sp,220 - 6e0c: 0000 unimp - 6e0e: 0010 0x10 - 6e10: f491 bnez s1,6d1c <_start-0x7fff92e4> - 6e12: 067e slli a2,a2,0x1f - 6e14: 0079 c.nop 30 - 6e16: 911a add sp,sp,t1 - 6e18: 7f84 flw fs1,56(a5) - 6e1a: 7906 flw fs2,96(sp) - 6e1c: 1a00 addi s0,sp,304 - 6e1e: 9f1e add t5,t5,t2 - 6e20: 09ec addi a1,sp,220 - 6e22: 0000 unimp - 6e24: 0a48 addi a0,sp,276 - 6e26: 0000 unimp - 6e28: 0010 0x10 - 6e2a: 7f84 flw fs1,56(a5) - 6e2c: f491 bnez s1,6d38 <_start-0x7fff92c8> - 6e2e: 067e slli a2,a2,0x1f - 6e30: 841a mv s0,t1 - 6e32: 917f 0x917f - 6e34: 7f84 flw fs1,56(a5) - 6e36: 1a06 slli s4,s4,0x21 - 6e38: 9f1e add t5,t5,t2 - 6e3a: 0a48 addi a0,sp,276 - 6e3c: 0000 unimp - 6e3e: 0ae0 addi s0,sp,348 - 6e40: 0000 unimp - 6e42: 0010 0x10 - 6e44: f491 bnez s1,6d50 <_start-0x7fff92b0> - 6e46: 067e slli a2,a2,0x1f - 6e48: 0079 c.nop 30 - 6e4a: 911a add sp,sp,t1 - 6e4c: 7f84 flw fs1,56(a5) - 6e4e: 7906 flw fs2,96(sp) - 6e50: 1a00 addi s0,sp,304 - 6e52: 9f1e add t5,t5,t2 - 6e54: 0ae0 addi s0,sp,348 - 6e56: 0000 unimp - 6e58: 0bc4 addi s1,sp,468 - 6e5a: 0000 unimp - 6e5c: 0010 0x10 - 6e5e: 7f89 lui t6,0xfffe2 - 6e60: f491 bnez s1,6d6c <_start-0x7fff9294> - 6e62: 067e slli a2,a2,0x1f - 6e64: 891a mv s2,t1 - 6e66: 917f 0x917f - 6e68: 7f84 flw fs1,56(a5) - 6e6a: 1a06 slli s4,s4,0x21 - 6e6c: 9f1e add t5,t5,t2 - 6e6e: 0da8 addi a0,sp,728 - 6e70: 0000 unimp - 6e72: 0db4 addi a3,sp,728 - 6e74: 0000 unimp - 6e76: 0010 0x10 - 6e78: 7f89 lui t6,0xfffe2 - 6e7a: f491 bnez s1,6d86 <_start-0x7fff927a> - 6e7c: 067e slli a2,a2,0x1f - 6e7e: 891a mv s2,t1 - 6e80: 917f 0x917f - 6e82: 7f84 flw fs1,56(a5) - 6e84: 1a06 slli s4,s4,0x21 - 6e86: 9f1e add t5,t5,t2 - ... - 6e90: 0560 addi s0,sp,652 - 6e92: 0000 unimp - 6e94: 056c addi a1,sp,652 - 6e96: 0000 unimp - 6e98: 0006 c.slli zero,0x1 - 6e9a: 0079 c.nop 30 - 6e9c: 9f1e007b 0x9f1e007b - 6ea0: 056c addi a1,sp,652 - 6ea2: 0000 unimp - 6ea4: 0570 addi a2,sp,652 - 6ea6: 0000 unimp - 6ea8: 0001 nop - 6eaa: 705d c.lui zero,0xffff7 - 6eac: 0005 c.nop 1 - 6eae: 7800 flw fs0,48(s0) - 6eb0: 0005 c.nop 1 - 6eb2: 0600 addi s0,sp,768 - 6eb4: 7900 flw fs0,48(a0) - 6eb6: 7b00 flw fs0,48(a4) - 6eb8: 1e00 addi s0,sp,816 - 6eba: 789f 0005 ac00 0xac000005789f - 6ec0: 0005 c.nop 1 - 6ec2: 0100 addi s0,sp,128 - 6ec4: 5d00 lw s0,56(a0) - 6ec6: 05ac addi a1,sp,712 - 6ec8: 0000 unimp - 6eca: 0910 addi a2,sp,144 - 6ecc: 0000 unimp - 6ece: 0014 0x14 - 6ed0: 0079 c.nop 30 - 6ed2: 821e007b 0x821e007b - 6ed6: 8e00 0x8e00 - 6ed8: 1e00 addi s0,sp,816 - 6eda: 7b22 flw fs6,40(sp) - 6edc: 8e00 0x8e00 - 6ede: 1e00 addi s0,sp,816 - 6ee0: 2540 fld fs0,136(a0) - 6ee2: 9f22 add t5,t5,s0 - 6ee4: 0910 addi a2,sp,144 - 6ee6: 0000 unimp - 6ee8: 0920 addi s0,sp,152 - 6eea: 0000 unimp - 6eec: 001e c.slli zero,0x7 - 6eee: 7f84 flw fs1,56(a5) - 6ef0: f491 bnez s1,6dfc <_start-0x7fff9204> - 6ef2: 067e slli a2,a2,0x1f - 6ef4: 791a flw fs2,164(sp) - 6ef6: 1e00 addi s0,sp,816 - 6ef8: 0082 c.slli64 ra - 6efa: 008e slli ra,ra,0x3 - 6efc: 221e fld ft4,448(sp) - 6efe: 7f84 flw fs1,56(a5) - 6f00: f491 bnez s1,6e0c <_start-0x7fff91f4> - 6f02: 067e slli a2,a2,0x1f - 6f04: 8e1a mv t3,t1 - 6f06: 1e00 addi s0,sp,816 - 6f08: 2540 fld fs0,136(a0) - 6f0a: 9f22 add t5,t5,s0 - 6f0c: 0920 addi s0,sp,152 - 6f0e: 0000 unimp - 6f10: 0934 addi a3,sp,152 - 6f12: 0000 unimp - 6f14: 0022 c.slli zero,0x8 - 6f16: 7f84 flw fs1,56(a5) - 6f18: f491 bnez s1,6e24 <_start-0x7fff91dc> - 6f1a: 067e slli a2,a2,0x1f - 6f1c: 791a flw fs2,164(sp) - 6f1e: 1e00 addi s0,sp,816 - 6f20: f491 bnez s1,6e2c <_start-0x7fff91d4> - 6f22: 067e slli a2,a2,0x1f - 6f24: 2540 fld fs0,136(a0) - 6f26: 008e slli ra,ra,0x3 - 6f28: 221e fld ft4,448(sp) - 6f2a: 7f84 flw fs1,56(a5) - 6f2c: f491 bnez s1,6e38 <_start-0x7fff91c8> - 6f2e: 067e slli a2,a2,0x1f - 6f30: 8e1a mv t3,t1 - 6f32: 1e00 addi s0,sp,816 - 6f34: 2540 fld fs0,136(a0) - 6f36: 9f22 add t5,t5,s0 - 6f38: 0934 addi a3,sp,152 - 6f3a: 0000 unimp - 6f3c: 0950 addi a2,sp,148 - 6f3e: 0000 unimp - 6f40: 0022 c.slli zero,0x8 - 6f42: f491 bnez s1,6e4e <_start-0x7fff91b2> - 6f44: 067e slli a2,a2,0x1f - 6f46: 0084 addi s1,sp,64 - 6f48: 791a flw fs2,164(sp) - 6f4a: 1e00 addi s0,sp,816 - 6f4c: f491 bnez s1,6e58 <_start-0x7fff91a8> - 6f4e: 067e slli a2,a2,0x1f - 6f50: 2540 fld fs0,136(a0) - 6f52: 008e slli ra,ra,0x3 - 6f54: 221e fld ft4,448(sp) - 6f56: f491 bnez s1,6e62 <_start-0x7fff919e> - 6f58: 067e slli a2,a2,0x1f - 6f5a: 0084 addi s1,sp,64 - 6f5c: 8e1a mv t3,t1 - 6f5e: 1e00 addi s0,sp,816 - 6f60: 2540 fld fs0,136(a0) - 6f62: 9f22 add t5,t5,s0 - 6f64: 0950 addi a2,sp,148 - 6f66: 0000 unimp - 6f68: 0958 addi a4,sp,148 - 6f6a: 0000 unimp - 6f6c: 002c addi a1,sp,8 - 6f6e: f491 bnez s1,6e7a <_start-0x7fff9186> - 6f70: 067e slli a2,a2,0x1f - 6f72: 0084 addi s1,sp,64 - 6f74: 791a flw fs2,164(sp) - 6f76: 1e00 addi s0,sp,816 - 6f78: 8491 srai s1,s1,0x4 - 6f7a: 067f 0x67f - 6f7c: 0084 addi s1,sp,64 - 6f7e: 911a add sp,sp,t1 - 6f80: 7ef4 flw fa3,124(a3) - 6f82: 4006 0x4006 - 6f84: 1e25 addi t3,t3,-23 - 6f86: 9122 add sp,sp,s0 - 6f88: 7ef4 flw fa3,124(a3) - 6f8a: 8406 mv s0,ra - 6f8c: 1a00 addi s0,sp,304 - 6f8e: 8491 srai s1,s1,0x4 - 6f90: 067f 0x67f - 6f92: 0084 addi s1,sp,64 - 6f94: 1e1a slli t3,t3,0x26 - 6f96: 2540 fld fs0,136(a0) - 6f98: 9f22 add t5,t5,s0 - 6f9a: 0958 addi a4,sp,148 - 6f9c: 0000 unimp - 6f9e: 095c addi a5,sp,148 - 6fa0: 0000 unimp - 6fa2: 002c addi a1,sp,8 - 6fa4: 7f85 lui t6,0xfffe1 - 6fa6: f491 bnez s1,6eb2 <_start-0x7fff914e> - 6fa8: 067e slli a2,a2,0x1f - 6faa: 791a flw fs2,164(sp) - 6fac: 1e00 addi s0,sp,816 - 6fae: 7f85 lui t6,0xfffe1 - 6fb0: 8491 srai s1,s1,0x4 - 6fb2: 067f 0x67f - 6fb4: 911a add sp,sp,t1 - 6fb6: 7ef4 flw fa3,124(a3) - 6fb8: 4006 0x4006 - 6fba: 1e25 addi t3,t3,-23 - 6fbc: 8522 mv a0,s0 - 6fbe: 917f 0x917f - 6fc0: 7ef4 flw fa3,124(a3) - 6fc2: 1a06 slli s4,s4,0x21 - 6fc4: 7f85 lui t6,0xfffe1 - 6fc6: 8491 srai s1,s1,0x4 - 6fc8: 067f 0x67f - 6fca: 1e1a slli t3,t3,0x26 - 6fcc: 2540 fld fs0,136(a0) - 6fce: 9f22 add t5,t5,s0 - 6fd0: 095c addi a5,sp,148 - 6fd2: 0000 unimp - 6fd4: 09e0 addi s0,sp,220 - 6fd6: 0000 unimp - 6fd8: 0030 addi a2,sp,8 - 6fda: 7f85 lui t6,0xfffe1 - 6fdc: f491 bnez s1,6ee8 <_start-0x7fff9118> - 6fde: 067e slli a2,a2,0x1f - 6fe0: 911a add sp,sp,t1 - 6fe2: 7f84 flw fs1,56(a5) - 6fe4: 4006 0x4006 - 6fe6: 1e25 addi t3,t3,-23 - 6fe8: 7f85 lui t6,0xfffe1 - 6fea: 8491 srai s1,s1,0x4 - 6fec: 067f 0x67f - 6fee: 911a add sp,sp,t1 - 6ff0: 7ef4 flw fa3,124(a3) - 6ff2: 4006 0x4006 - 6ff4: 1e25 addi t3,t3,-23 - 6ff6: 8522 mv a0,s0 - 6ff8: 917f 0x917f - 6ffa: 7ef4 flw fa3,124(a3) - 6ffc: 1a06 slli s4,s4,0x21 - 6ffe: 7f85 lui t6,0xfffe1 - 7000: 8491 srai s1,s1,0x4 - 7002: 067f 0x67f - 7004: 1e1a slli t3,t3,0x26 - 7006: 2540 fld fs0,136(a0) - 7008: 9f22 add t5,t5,s0 - 700a: 09e0 addi s0,sp,220 - 700c: 0000 unimp - 700e: 09ec addi a1,sp,220 - 7010: 0000 unimp - 7012: 0030 addi a2,sp,8 - 7014: f491 bnez s1,6f20 <_start-0x7fff90e0> - 7016: 067e slli a2,a2,0x1f - 7018: 0079 c.nop 30 - 701a: 911a add sp,sp,t1 - 701c: 7f84 flw fs1,56(a5) - 701e: 4006 0x4006 - 7020: 1e25 addi t3,t3,-23 - 7022: 8491 srai s1,s1,0x4 - 7024: 067f 0x67f - 7026: 0079 c.nop 30 - 7028: 911a add sp,sp,t1 - 702a: 7ef4 flw fa3,124(a3) - 702c: 4006 0x4006 - 702e: 1e25 addi t3,t3,-23 - 7030: 9122 add sp,sp,s0 - 7032: 7ef4 flw fa3,124(a3) - 7034: 7906 flw fs2,96(sp) - 7036: 1a00 addi s0,sp,304 - 7038: 8491 srai s1,s1,0x4 - 703a: 067f 0x67f - 703c: 0079 c.nop 30 - 703e: 1e1a slli t3,t3,0x26 - 7040: 2540 fld fs0,136(a0) - 7042: 9f22 add t5,t5,s0 - 7044: 09ec addi a1,sp,220 - 7046: 0000 unimp - 7048: 0a48 addi a0,sp,276 - 704a: 0000 unimp - 704c: 0030 addi a2,sp,8 - 704e: 7f84 flw fs1,56(a5) - 7050: f491 bnez s1,6f5c <_start-0x7fff90a4> - 7052: 067e slli a2,a2,0x1f - 7054: 911a add sp,sp,t1 - 7056: 7f84 flw fs1,56(a5) - 7058: 4006 0x4006 - 705a: 1e25 addi t3,t3,-23 - 705c: 7f84 flw fs1,56(a5) - 705e: 8491 srai s1,s1,0x4 - 7060: 067f 0x67f - 7062: 911a add sp,sp,t1 - 7064: 7ef4 flw fa3,124(a3) - 7066: 4006 0x4006 - 7068: 1e25 addi t3,t3,-23 - 706a: 8422 mv s0,s0 - 706c: 917f 0x917f - 706e: 7ef4 flw fa3,124(a3) - 7070: 1a06 slli s4,s4,0x21 - 7072: 7f84 flw fs1,56(a5) - 7074: 8491 srai s1,s1,0x4 - 7076: 067f 0x67f - 7078: 1e1a slli t3,t3,0x26 - 707a: 2540 fld fs0,136(a0) - 707c: 9f22 add t5,t5,s0 - 707e: 0a48 addi a0,sp,276 - 7080: 0000 unimp - 7082: 0ae0 addi s0,sp,348 - 7084: 0000 unimp - 7086: 0030 addi a2,sp,8 - 7088: f491 bnez s1,6f94 <_start-0x7fff906c> - 708a: 067e slli a2,a2,0x1f - 708c: 0079 c.nop 30 - 708e: 911a add sp,sp,t1 - 7090: 7f84 flw fs1,56(a5) - 7092: 4006 0x4006 - 7094: 1e25 addi t3,t3,-23 - 7096: 8491 srai s1,s1,0x4 - 7098: 067f 0x67f - 709a: 0079 c.nop 30 - 709c: 911a add sp,sp,t1 - 709e: 7ef4 flw fa3,124(a3) - 70a0: 4006 0x4006 - 70a2: 1e25 addi t3,t3,-23 - 70a4: 9122 add sp,sp,s0 - 70a6: 7ef4 flw fa3,124(a3) - 70a8: 7906 flw fs2,96(sp) - 70aa: 1a00 addi s0,sp,304 - 70ac: 8491 srai s1,s1,0x4 - 70ae: 067f 0x67f - 70b0: 0079 c.nop 30 - 70b2: 1e1a slli t3,t3,0x26 - 70b4: 2540 fld fs0,136(a0) - 70b6: 9f22 add t5,t5,s0 - 70b8: 0ae0 addi s0,sp,348 - 70ba: 0000 unimp - 70bc: 0bc4 addi s1,sp,468 - 70be: 0000 unimp - 70c0: 0030 addi a2,sp,8 - 70c2: 7f89 lui t6,0xfffe2 - 70c4: f491 bnez s1,6fd0 <_start-0x7fff9030> - 70c6: 067e slli a2,a2,0x1f - 70c8: 911a add sp,sp,t1 - 70ca: 7f84 flw fs1,56(a5) - 70cc: 4006 0x4006 - 70ce: 1e25 addi t3,t3,-23 - 70d0: 7f89 lui t6,0xfffe2 - 70d2: 8491 srai s1,s1,0x4 - 70d4: 067f 0x67f - 70d6: 911a add sp,sp,t1 - 70d8: 7ef4 flw fa3,124(a3) - 70da: 4006 0x4006 - 70dc: 1e25 addi t3,t3,-23 - 70de: 8922 mv s2,s0 - 70e0: 917f 0x917f - 70e2: 7ef4 flw fa3,124(a3) - 70e4: 1a06 slli s4,s4,0x21 - 70e6: 7f89 lui t6,0xfffe2 - 70e8: 8491 srai s1,s1,0x4 - 70ea: 067f 0x67f - 70ec: 1e1a slli t3,t3,0x26 - 70ee: 2540 fld fs0,136(a0) - 70f0: 9f22 add t5,t5,s0 - 70f2: 0da8 addi a0,sp,728 - 70f4: 0000 unimp - 70f6: 0db4 addi a3,sp,728 - 70f8: 0000 unimp - 70fa: 0030 addi a2,sp,8 - 70fc: 7f89 lui t6,0xfffe2 - 70fe: f491 bnez s1,700a <_start-0x7fff8ff6> - 7100: 067e slli a2,a2,0x1f - 7102: 911a add sp,sp,t1 - 7104: 7f84 flw fs1,56(a5) - 7106: 4006 0x4006 - 7108: 1e25 addi t3,t3,-23 - 710a: 7f89 lui t6,0xfffe2 - 710c: 8491 srai s1,s1,0x4 - 710e: 067f 0x67f - 7110: 911a add sp,sp,t1 - 7112: 7ef4 flw fa3,124(a3) - 7114: 4006 0x4006 - 7116: 1e25 addi t3,t3,-23 - 7118: 8922 mv s2,s0 - 711a: 917f 0x917f - 711c: 7ef4 flw fa3,124(a3) - 711e: 1a06 slli s4,s4,0x21 - 7120: 7f89 lui t6,0xfffe2 - 7122: 8491 srai s1,s1,0x4 - 7124: 067f 0x67f - 7126: 1e1a slli t3,t3,0x26 - 7128: 2540 fld fs0,136(a0) - 712a: 9f22 add t5,t5,s0 - ... - 7134: 0578 addi a4,sp,652 - 7136: 0000 unimp - 7138: 05b8 addi a4,sp,712 - 713a: 0000 unimp - 713c: 0001 nop - 713e: 0056 c.slli zero,0x15 - 7140: 0000 unimp - 7142: 0000 unimp - 7144: 0000 unimp - 7146: 5c00 lw s0,56(s0) - 7148: 0005 c.nop 1 - 714a: 2000 fld fs0,0(s0) - 714c: 0009 c.nop 2 - 714e: 0100 addi s0,sp,128 - 7150: 6200 flw fs0,0(a2) - 7152: 0920 addi s0,sp,152 - 7154: 0000 unimp - 7156: 0bc4 addi s1,sp,468 - 7158: 0000 unimp - 715a: f6910003 lb zero,-151(sp) - 715e: a87e fsd ft11,16(sp) - 7160: 000d c.nop 3 - 7162: b400 fsd fs0,40(s0) - 7164: 000d c.nop 3 - 7166: 0300 addi s0,sp,384 - 7168: 9100 0x9100 - 716a: 7ef6 flw ft9,124(sp) - ... - 7174: 055c addi a5,sp,644 - 7176: 0000 unimp - 7178: 095c addi a5,sp,148 - 717a: 0000 unimp - 717c: 0001 nop - 717e: 5c59 li s8,-10 - 7180: 0009 c.nop 2 - 7182: c400 sw s0,8(s0) - 7184: 0300000b 0x300000b - 7188: 9100 0x9100 - 718a: 7f86 flw ft11,96(sp) - 718c: 0da8 addi a0,sp,728 - 718e: 0000 unimp - 7190: 0db4 addi a3,sp,728 - 7192: 0000 unimp - 7194: 86910003 lb zero,-1943(sp) - 7198: 007f 0x7f - 719a: 0000 unimp - 719c: 0000 unimp - 719e: 0000 unimp - 71a0: b800 fsd fs0,48(s0) - 71a2: 0005 c.nop 1 - 71a4: f400 fsw fs0,40(s0) - 71a6: 0005 c.nop 1 - 71a8: 0100 addi s0,sp,128 - 71aa: 5600 lw s0,40(a2) - 71ac: 05f4 addi a3,sp,716 - 71ae: 0000 unimp - 71b0: 070c addi a1,sp,896 - 71b2: 0000 unimp - 71b4: 0006 c.slli zero,0x1 - 71b6: 008d addi ra,ra,3 - 71b8: 007e c.slli zero,0x1f - 71ba: 9f1e add t5,t5,t2 - 71bc: 070c addi a1,sp,896 - 71be: 0000 unimp - 71c0: 0860 addi s0,sp,28 - 71c2: 0000 unimp - 71c4: f091000b 0xf091000b - 71c8: 067e slli a2,a2,0x1f - 71ca: 0089 addi ra,ra,2 - 71cc: 8d1a mv s10,t1 - 71ce: 1e00 addi s0,sp,816 - 71d0: 609f 0008 9400 0x94000008609f - 71d6: 0008 0x8 - 71d8: 0b00 addi s0,sp,400 - 71da: 9100 0x9100 - 71dc: 7ef0 flw fa2,124(a3) - 71de: 8c06 mv s8,ra - 71e0: 1a00 addi s0,sp,304 - 71e2: 008d addi ra,ra,3 - 71e4: 9f1e add t5,t5,t2 - 71e6: 0894 addi a3,sp,80 - 71e8: 0000 unimp - 71ea: 08e0 addi s0,sp,92 - 71ec: 0000 unimp - 71ee: 000c 0xc - 71f0: f091 bnez s1,70f4 <_start-0x7fff8f0c> - 71f2: 067e slli a2,a2,0x1f - 71f4: ff0a fsw ft2,188(sp) - 71f6: 1aff 0x1aff - 71f8: 008d addi ra,ra,3 - 71fa: 9f1e add t5,t5,t2 - 71fc: 08e0 addi s0,sp,92 - 71fe: 0000 unimp - 7200: 08e4 addi s1,sp,92 - 7202: 0000 unimp - 7204: 7f7a000b 0x7f7a000b - 7208: f091 bnez s1,710c <_start-0x7fff8ef4> - 720a: 067e slli a2,a2,0x1f - 720c: 8d1a mv s10,t1 - 720e: 1e00 addi s0,sp,816 - 7210: e49f 0008 e800 0xe8000008e49f - 7216: 0008 0x8 - 7218: 0c00 addi s0,sp,528 - 721a: 9100 0x9100 - 721c: 7ef0 flw fa2,124(a3) - 721e: 0a06 slli s4,s4,0x1 - 7220: ffff 0xffff - 7222: 8d1a mv s10,t1 - 7224: 1e00 addi s0,sp,816 - 7226: e89f 0008 3400 0x34000008e89f - 722c: 0009 c.nop 2 - 722e: 0b00 addi s0,sp,400 - 7230: 8400 0x8400 - 7232: 917f 0x917f - 7234: 7ef0 flw fa2,124(a3) - 7236: 1a06 slli s4,s4,0x21 - 7238: 008d addi ra,ra,3 - 723a: 9f1e add t5,t5,t2 - 723c: 0934 addi a3,sp,152 - 723e: 0000 unimp - 7240: 0958 addi a4,sp,148 - 7242: 0000 unimp - 7244: f091000b 0xf091000b - 7248: 067e slli a2,a2,0x1f - 724a: 0084 addi s1,sp,64 - 724c: 8d1a mv s10,t1 - 724e: 1e00 addi s0,sp,816 - 7250: 589f 0009 dc00 0xdc000009589f - 7256: 0009 c.nop 2 - 7258: 0b00 addi s0,sp,400 - 725a: 8500 0x8500 - 725c: 917f 0x917f - 725e: 7ef0 flw fa2,124(a3) - 7260: 1a06 slli s4,s4,0x21 - 7262: 008d addi ra,ra,3 - 7264: 9f1e add t5,t5,t2 - 7266: 09dc addi a5,sp,212 - 7268: 0000 unimp - 726a: 09e0 addi s0,sp,220 - 726c: 0000 unimp - 726e: 0010 0x10 - 7270: 7f85 lui t6,0xfffe1 - 7272: 8891 andi s1,s1,4 - 7274: 067f 0x67f - 7276: 851a mv a0,t1 - 7278: 917f 0x917f - 727a: 7ef0 flw fa2,124(a3) - 727c: 1a06 slli s4,s4,0x21 - 727e: 9f1e add t5,t5,t2 - 7280: 09e0 addi s0,sp,220 - 7282: 0000 unimp - 7284: 09ec addi a1,sp,220 - 7286: 0000 unimp - 7288: 0010 0x10 - 728a: 8891 andi s1,s1,4 - 728c: 067f 0x67f - 728e: 0079 c.nop 30 - 7290: 911a add sp,sp,t1 - 7292: 7ef0 flw fa2,124(a3) - 7294: 7906 flw fs2,96(sp) - 7296: 1a00 addi s0,sp,304 - 7298: 9f1e add t5,t5,t2 - 729a: 09ec addi a1,sp,220 - 729c: 0000 unimp - 729e: 0a48 addi a0,sp,276 - 72a0: 0000 unimp - 72a2: 0010 0x10 - 72a4: 7f84 flw fs1,56(a5) - 72a6: 8891 andi s1,s1,4 - 72a8: 067f 0x67f - 72aa: 841a mv s0,t1 - 72ac: 917f 0x917f - 72ae: 7ef0 flw fa2,124(a3) - 72b0: 1a06 slli s4,s4,0x21 - 72b2: 9f1e add t5,t5,t2 - 72b4: 0a48 addi a0,sp,276 - 72b6: 0000 unimp - 72b8: 0ae0 addi s0,sp,348 - 72ba: 0000 unimp - 72bc: 0010 0x10 - 72be: 8891 andi s1,s1,4 - 72c0: 067f 0x67f - 72c2: 0079 c.nop 30 - 72c4: 911a add sp,sp,t1 - 72c6: 7ef0 flw fa2,124(a3) - 72c8: 7906 flw fs2,96(sp) - 72ca: 1a00 addi s0,sp,304 - 72cc: 9f1e add t5,t5,t2 - 72ce: 0ae0 addi s0,sp,348 - 72d0: 0000 unimp - 72d2: 0bc4 addi s1,sp,468 - 72d4: 0000 unimp - 72d6: 0010 0x10 - 72d8: 7f89 lui t6,0xfffe2 - 72da: 8891 andi s1,s1,4 - 72dc: 067f 0x67f - 72de: 891a mv s2,t1 - 72e0: 917f 0x917f - 72e2: 7ef0 flw fa2,124(a3) - 72e4: 1a06 slli s4,s4,0x21 - 72e6: 9f1e add t5,t5,t2 - 72e8: 0da8 addi a0,sp,728 - 72ea: 0000 unimp - 72ec: 0db4 addi a3,sp,728 - 72ee: 0000 unimp - 72f0: 0010 0x10 - 72f2: 7f89 lui t6,0xfffe2 - 72f4: 8891 andi s1,s1,4 - 72f6: 067f 0x67f - 72f8: 891a mv s2,t1 - 72fa: 917f 0x917f - 72fc: 7ef0 flw fa2,124(a3) - 72fe: 1a06 slli s4,s4,0x21 - 7300: 9f1e add t5,t5,t2 - ... - 730a: 05b8 addi a4,sp,712 - 730c: 0000 unimp - 730e: 05c4 addi s1,sp,708 - 7310: 0000 unimp - 7312: 0001 nop - 7314: c461 beqz s0,73dc <_start-0x7fff8c24> - 7316: 0005 c.nop 1 - 7318: cc00 sw s0,24(s0) - 731a: 0005 c.nop 1 - 731c: 0600 addi s0,sp,768 - 731e: 7800 flw fs0,48(s0) - 7320: 7e00 flw fs0,56(a2) - 7322: 1e00 addi s0,sp,816 - 7324: cc9f 0005 f000 0xf0000005cc9f - 732a: 0005 c.nop 1 - 732c: 0100 addi s0,sp,128 - 732e: 6100 flw fs0,0(a0) - 7330: 05f0 addi a2,sp,716 - 7332: 0000 unimp - 7334: 05f4 addi a3,sp,716 - 7336: 0000 unimp - 7338: 000e c.slli zero,0x3 - 733a: 0078 addi a4,sp,12 - 733c: 007e c.slli zero,0x1f - 733e: 761e flw fa2,228(sp) - 7340: 4000 lw s0,0(s0) - 7342: 2225 jal 746a <_start-0x7fff8b96> - 7344: 9f220087 vlxseg5b.v v1,(tp),v18 - 7348: 05f4 addi a3,sp,716 - 734a: 0000 unimp - 734c: 0620 addi s0,sp,776 - 734e: 0000 unimp - 7350: 0011 c.nop 4 - 7352: 0078 addi a4,sp,12 - 7354: 007e c.slli zero,0x1f - 7356: 8d1e mv s10,t2 - 7358: 7e00 flw fs0,56(a2) - 735a: 1e00 addi s0,sp,816 - 735c: 2540 fld fs0,136(a0) - 735e: 8722 mv a4,s0 - 7360: 2200 fld fs0,0(a2) - 7362: 209f 0006 0c00 0xc000006209f - 7368: 14000007 0x14000007 - 736c: 7800 flw fs0,48(s0) - 736e: 7e00 flw fs0,56(a2) - 7370: 1e00 addi s0,sp,816 - 7372: 008d008f 0x8d008f - 7376: 221e fld ft4,448(sp) - 7378: 008d addi ra,ra,3 - 737a: 007e c.slli zero,0x1f - 737c: 401e 0x401e - 737e: 2225 jal 74a6 <_start-0x7fff8b5a> - 7380: 0c9f 0007 2000 0x200000070c9f - 7386: 1e000007 vlxb.v v0,(zero),v0 - 738a: 9100 0x9100 - 738c: 7ef0 flw fa2,124(a3) - 738e: 8906 mv s2,ra - 7390: 1a00 addi s0,sp,304 - 7392: 0078 addi a4,sp,12 - 7394: 8f1e mv t5,t2 - 7396: 8d00 0x8d00 - 7398: 1e00 addi s0,sp,816 - 739a: 9122 add sp,sp,s0 - 739c: 7ef0 flw fa2,124(a3) - 739e: 8906 mv s2,ra - 73a0: 1a00 addi s0,sp,304 - 73a2: 008d addi ra,ra,3 - 73a4: 401e 0x401e - 73a6: 2225 jal 74ce <_start-0x7fff8b32> - 73a8: 209f 0007 6000 0x60000007209f - 73ae: 0008 0x8 - 73b0: 2200 fld fs0,0(a2) - 73b2: 9100 0x9100 - 73b4: 7ef0 flw fa2,124(a3) - 73b6: 8906 mv s2,ra - 73b8: 1a00 addi s0,sp,304 - 73ba: 0078 addi a4,sp,12 - 73bc: 911e add sp,sp,t2 - 73be: 7ef0 flw fa2,124(a3) - 73c0: 4006 0x4006 - 73c2: 8d25 xor a0,a0,s1 - 73c4: 1e00 addi s0,sp,816 - 73c6: 9122 add sp,sp,s0 - 73c8: 7ef0 flw fa2,124(a3) - 73ca: 8906 mv s2,ra - 73cc: 1a00 addi s0,sp,304 - 73ce: 008d addi ra,ra,3 - 73d0: 401e 0x401e - 73d2: 2225 jal 74fa <_start-0x7fff8b06> - 73d4: 609f 0008 9400 0x94000008609f - 73da: 0008 0x8 - 73dc: 2200 fld fs0,0(a2) - 73de: 9100 0x9100 - 73e0: 7ef0 flw fa2,124(a3) - 73e2: 8c06 mv s8,ra - 73e4: 1a00 addi s0,sp,304 - 73e6: 0078 addi a4,sp,12 - 73e8: 911e add sp,sp,t2 - 73ea: 7ef0 flw fa2,124(a3) - 73ec: 4006 0x4006 - 73ee: 8d25 xor a0,a0,s1 - 73f0: 1e00 addi s0,sp,816 - 73f2: 9122 add sp,sp,s0 - 73f4: 7ef0 flw fa2,124(a3) - 73f6: 8c06 mv s8,ra - 73f8: 1a00 addi s0,sp,304 - 73fa: 008d addi ra,ra,3 - 73fc: 401e 0x401e - 73fe: 2225 jal 7526 <_start-0x7fff8ada> - 7400: 949f 0008 e000 0xe0000008949f - 7406: 0008 0x8 - 7408: 2400 fld fs0,8(s0) - 740a: 9100 0x9100 - 740c: 7ef0 flw fa2,124(a3) - 740e: 0a06 slli s4,s4,0x1 - 7410: ffff 0xffff - 7412: 781a flw fa6,164(sp) - 7414: 1e00 addi s0,sp,816 - 7416: f091 bnez s1,731a <_start-0x7fff8ce6> - 7418: 067e slli a2,a2,0x1f - 741a: 2540 fld fs0,136(a0) - 741c: 008d addi ra,ra,3 - 741e: 221e fld ft4,448(sp) - 7420: f091 bnez s1,7324 <_start-0x7fff8cdc> - 7422: 067e slli a2,a2,0x1f - 7424: ff0a fsw ft2,188(sp) - 7426: 1aff 0x1aff - 7428: 008d addi ra,ra,3 - 742a: 401e 0x401e - 742c: 2225 jal 7554 <_start-0x7fff8aac> - 742e: e09f 0008 e400 0xe4000008e09f - 7434: 0008 0x8 - 7436: 2200 fld fs0,0(a2) - 7438: 7a00 flw fs0,48(a2) - 743a: 917f 0x917f - 743c: 7ef0 flw fa2,124(a3) - 743e: 1a06 slli s4,s4,0x21 - 7440: 0078 addi a4,sp,12 - 7442: 911e add sp,sp,t2 - 7444: 7ef0 flw fa2,124(a3) - 7446: 4006 0x4006 - 7448: 8d25 xor a0,a0,s1 - 744a: 1e00 addi s0,sp,816 - 744c: 7a22 flw fs4,40(sp) - 744e: 917f 0x917f - 7450: 7ef0 flw fa2,124(a3) - 7452: 1a06 slli s4,s4,0x21 - 7454: 008d addi ra,ra,3 - 7456: 401e 0x401e - 7458: 2225 jal 7580 <_start-0x7fff8a80> - 745a: e49f 0008 e800 0xe8000008e49f - 7460: 0008 0x8 - 7462: 2400 fld fs0,8(s0) - 7464: 9100 0x9100 - 7466: 7ef0 flw fa2,124(a3) - 7468: 0a06 slli s4,s4,0x1 - 746a: ffff 0xffff - 746c: 781a flw fa6,164(sp) - 746e: 1e00 addi s0,sp,816 - 7470: f091 bnez s1,7374 <_start-0x7fff8c8c> - 7472: 067e slli a2,a2,0x1f - 7474: 2540 fld fs0,136(a0) - 7476: 008d addi ra,ra,3 - 7478: 221e fld ft4,448(sp) - 747a: f091 bnez s1,737e <_start-0x7fff8c82> - 747c: 067e slli a2,a2,0x1f - 747e: ff0a fsw ft2,188(sp) - 7480: 1aff 0x1aff - 7482: 008d addi ra,ra,3 - 7484: 401e 0x401e - 7486: 2225 jal 75ae <_start-0x7fff8a52> - 7488: e89f 0008 3400 0x34000008e89f - 748e: 0009 c.nop 2 - 7490: 2200 fld fs0,0(a2) - 7492: 8400 0x8400 - 7494: 917f 0x917f - 7496: 7ef0 flw fa2,124(a3) - 7498: 1a06 slli s4,s4,0x21 - 749a: 0078 addi a4,sp,12 - 749c: 911e add sp,sp,t2 - 749e: 7ef0 flw fa2,124(a3) - 74a0: 4006 0x4006 - 74a2: 8d25 xor a0,a0,s1 - 74a4: 1e00 addi s0,sp,816 - 74a6: 8422 mv s0,s0 - 74a8: 917f 0x917f - 74aa: 7ef0 flw fa2,124(a3) - 74ac: 1a06 slli s4,s4,0x21 - 74ae: 008d addi ra,ra,3 - 74b0: 401e 0x401e - 74b2: 2225 jal 75da <_start-0x7fff8a26> - 74b4: 349f 0009 5800 0x58000009349f - 74ba: 0009 c.nop 2 - 74bc: 2200 fld fs0,0(a2) - 74be: 9100 0x9100 - 74c0: 7ef0 flw fa2,124(a3) - 74c2: 8406 mv s0,ra - 74c4: 1a00 addi s0,sp,304 - 74c6: 0078 addi a4,sp,12 - 74c8: 911e add sp,sp,t2 - 74ca: 7ef0 flw fa2,124(a3) - 74cc: 4006 0x4006 - 74ce: 8d25 xor a0,a0,s1 - 74d0: 1e00 addi s0,sp,816 - 74d2: 9122 add sp,sp,s0 - 74d4: 7ef0 flw fa2,124(a3) - 74d6: 8406 mv s0,ra - 74d8: 1a00 addi s0,sp,304 - 74da: 008d addi ra,ra,3 - 74dc: 401e 0x401e - 74de: 2225 jal 7606 <_start-0x7fff89fa> - 74e0: 589f 0009 dc00 0xdc000009589f - 74e6: 0009 c.nop 2 - 74e8: 2200 fld fs0,0(a2) - 74ea: 8500 0x8500 - 74ec: 917f 0x917f - 74ee: 7ef0 flw fa2,124(a3) - 74f0: 1a06 slli s4,s4,0x21 - 74f2: 0078 addi a4,sp,12 - 74f4: 911e add sp,sp,t2 - 74f6: 7ef0 flw fa2,124(a3) - 74f8: 4006 0x4006 - 74fa: 8d25 xor a0,a0,s1 - 74fc: 1e00 addi s0,sp,816 - 74fe: 8522 mv a0,s0 - 7500: 917f 0x917f - 7502: 7ef0 flw fa2,124(a3) - 7504: 1a06 slli s4,s4,0x21 - 7506: 008d addi ra,ra,3 - 7508: 401e 0x401e - 750a: 2225 jal 7632 <_start-0x7fff89ce> - 750c: dc9f 0009 e000 0xe0000009dc9f - 7512: 0009 c.nop 2 - 7514: 2c00 fld fs0,24(s0) - 7516: 8500 0x8500 - 7518: 917f 0x917f - 751a: 7ef0 flw fa2,124(a3) - 751c: 1a06 slli s4,s4,0x21 - 751e: 0078 addi a4,sp,12 - 7520: 851e mv a0,t2 - 7522: 917f 0x917f - 7524: 7f88 flw fa0,56(a5) - 7526: 1a06 slli s4,s4,0x21 - 7528: f091 bnez s1,742c <_start-0x7fff8bd4> - 752a: 067e slli a2,a2,0x1f - 752c: 2540 fld fs0,136(a0) - 752e: 221e fld ft4,448(sp) - 7530: 7f85 lui t6,0xfffe1 - 7532: 8891 andi s1,s1,4 - 7534: 067f 0x67f - 7536: 851a mv a0,t1 - 7538: 917f 0x917f - 753a: 7ef0 flw fa2,124(a3) - 753c: 1a06 slli s4,s4,0x21 - 753e: 401e 0x401e - 7540: 2225 jal 7668 <_start-0x7fff8998> - 7542: e09f 0009 ec00 0xec000009e09f - 7548: 0009 c.nop 2 - 754a: 2c00 fld fs0,24(s0) - 754c: 9100 0x9100 - 754e: 7ef0 flw fa2,124(a3) - 7550: 7906 flw fs2,96(sp) - 7552: 1a00 addi s0,sp,304 - 7554: 0078 addi a4,sp,12 - 7556: 911e add sp,sp,t2 - 7558: 7f88 flw fa0,56(a5) - 755a: 7906 flw fs2,96(sp) - 755c: 1a00 addi s0,sp,304 - 755e: f091 bnez s1,7462 <_start-0x7fff8b9e> - 7560: 067e slli a2,a2,0x1f - 7562: 2540 fld fs0,136(a0) - 7564: 221e fld ft4,448(sp) - 7566: 8891 andi s1,s1,4 - 7568: 067f 0x67f - 756a: 0079 c.nop 30 - 756c: 911a add sp,sp,t1 - 756e: 7ef0 flw fa2,124(a3) - 7570: 7906 flw fs2,96(sp) - 7572: 1a00 addi s0,sp,304 - 7574: 401e 0x401e - 7576: 2225 jal 769e <_start-0x7fff8962> - 7578: ec9f 0009 4800 0x48000009ec9f - 757e: 000a c.slli zero,0x2 - 7580: 2c00 fld fs0,24(s0) - 7582: 8400 0x8400 - 7584: 917f 0x917f - 7586: 7ef0 flw fa2,124(a3) - 7588: 1a06 slli s4,s4,0x21 - 758a: 0078 addi a4,sp,12 - 758c: 841e mv s0,t2 - 758e: 917f 0x917f - 7590: 7f88 flw fa0,56(a5) - 7592: 1a06 slli s4,s4,0x21 - 7594: f091 bnez s1,7498 <_start-0x7fff8b68> - 7596: 067e slli a2,a2,0x1f - 7598: 2540 fld fs0,136(a0) - 759a: 221e fld ft4,448(sp) - 759c: 7f84 flw fs1,56(a5) - 759e: 8891 andi s1,s1,4 - 75a0: 067f 0x67f - 75a2: 841a mv s0,t1 - 75a4: 917f 0x917f - 75a6: 7ef0 flw fa2,124(a3) - 75a8: 1a06 slli s4,s4,0x21 - 75aa: 401e 0x401e - 75ac: 2225 jal 76d4 <_start-0x7fff892c> - 75ae: 489f 000a e000 0xe000000a489f - 75b4: 000a c.slli zero,0x2 - 75b6: 2c00 fld fs0,24(s0) - 75b8: 9100 0x9100 - 75ba: 7ef0 flw fa2,124(a3) - 75bc: 7906 flw fs2,96(sp) - 75be: 1a00 addi s0,sp,304 - 75c0: 0078 addi a4,sp,12 - 75c2: 911e add sp,sp,t2 - 75c4: 7f88 flw fa0,56(a5) - 75c6: 7906 flw fs2,96(sp) - 75c8: 1a00 addi s0,sp,304 - 75ca: f091 bnez s1,74ce <_start-0x7fff8b32> - 75cc: 067e slli a2,a2,0x1f - 75ce: 2540 fld fs0,136(a0) - 75d0: 221e fld ft4,448(sp) - 75d2: 8891 andi s1,s1,4 - 75d4: 067f 0x67f - 75d6: 0079 c.nop 30 - 75d8: 911a add sp,sp,t1 - 75da: 7ef0 flw fa2,124(a3) - 75dc: 7906 flw fs2,96(sp) - 75de: 1a00 addi s0,sp,304 - 75e0: 401e 0x401e - 75e2: 2225 jal 770a <_start-0x7fff88f6> - 75e4: e09f 000a c400 0xc400000ae09f - 75ea: 2c00000b 0x2c00000b - 75ee: 8900 0x8900 - 75f0: 917f 0x917f - 75f2: 7ef0 flw fa2,124(a3) - 75f4: 1a06 slli s4,s4,0x21 - 75f6: 0078 addi a4,sp,12 - 75f8: 891e mv s2,t2 - 75fa: 917f 0x917f - 75fc: 7f88 flw fa0,56(a5) - 75fe: 1a06 slli s4,s4,0x21 - 7600: f091 bnez s1,7504 <_start-0x7fff8afc> - 7602: 067e slli a2,a2,0x1f - 7604: 2540 fld fs0,136(a0) - 7606: 221e fld ft4,448(sp) - 7608: 7f89 lui t6,0xfffe2 - 760a: 8891 andi s1,s1,4 - 760c: 067f 0x67f - 760e: 891a mv s2,t1 - 7610: 917f 0x917f - 7612: 7ef0 flw fa2,124(a3) - 7614: 1a06 slli s4,s4,0x21 - 7616: 401e 0x401e - 7618: 2225 jal 7740 <_start-0x7fff88c0> - 761a: a89f 000d b400 0xb400000da89f - 7620: 000d c.nop 3 - 7622: 2c00 fld fs0,24(s0) - 7624: 8900 0x8900 - 7626: 917f 0x917f - 7628: 7ef0 flw fa2,124(a3) - 762a: 1a06 slli s4,s4,0x21 - 762c: 0078 addi a4,sp,12 - 762e: 891e mv s2,t2 - 7630: 917f 0x917f - 7632: 7f88 flw fa0,56(a5) - 7634: 1a06 slli s4,s4,0x21 - 7636: f091 bnez s1,753a <_start-0x7fff8ac6> - 7638: 067e slli a2,a2,0x1f - 763a: 2540 fld fs0,136(a0) - 763c: 221e fld ft4,448(sp) - 763e: 7f89 lui t6,0xfffe2 - 7640: 8891 andi s1,s1,4 - 7642: 067f 0x67f - 7644: 891a mv s2,t1 - 7646: 917f 0x917f - 7648: 7ef0 flw fa2,124(a3) - 764a: 1a06 slli s4,s4,0x21 - 764c: 401e 0x401e - 764e: 2225 jal 7776 <_start-0x7fff888a> - 7650: 009f 0000 0000 0x9f - 7656: 0000 unimp - 7658: bc00 fsd fs0,56(s0) - 765a: 0005 c.nop 1 - 765c: 2000 fld fs0,0(s0) - 765e: 0006 c.slli zero,0x1 - 7660: 0100 addi s0,sp,128 - 7662: 6700 flw fs0,8(a4) - 7664: 0620 addi s0,sp,776 - 7666: 0000 unimp - 7668: 0720 addi s0,sp,904 - 766a: 0000 unimp - 766c: 0006 c.slli zero,0x1 - 766e: 008d008f 0x8d008f - 7672: 9f1e add t5,t5,t2 - 7674: 0720 addi s0,sp,904 - 7676: 0000 unimp - 7678: 09dc addi a5,sp,212 - 767a: 0000 unimp - 767c: 000a c.slli zero,0x2 - 767e: f091 bnez s1,7582 <_start-0x7fff8a7e> - 7680: 067e slli a2,a2,0x1f - 7682: 2540 fld fs0,136(a0) - 7684: 008d addi ra,ra,3 - 7686: 9f1e add t5,t5,t2 - 7688: 09dc addi a5,sp,212 - 768a: 0000 unimp - 768c: 09e0 addi s0,sp,220 - 768e: 0000 unimp - 7690: 7f85000f 0x7f85000f - 7694: 8891 andi s1,s1,4 - 7696: 067f 0x67f - 7698: 911a add sp,sp,t1 - 769a: 7ef0 flw fa2,124(a3) - 769c: 4006 0x4006 - 769e: 1e25 addi t3,t3,-23 - 76a0: e09f 0009 ec00 0xec000009e09f - 76a6: 0009 c.nop 2 - 76a8: 0f00 addi s0,sp,912 - 76aa: 9100 0x9100 - 76ac: 7f88 flw fa0,56(a5) - 76ae: 7906 flw fs2,96(sp) - 76b0: 1a00 addi s0,sp,304 - 76b2: f091 bnez s1,75b6 <_start-0x7fff8a4a> - 76b4: 067e slli a2,a2,0x1f - 76b6: 2540 fld fs0,136(a0) - 76b8: 9f1e add t5,t5,t2 - 76ba: 09ec addi a1,sp,220 - 76bc: 0000 unimp - 76be: 0a48 addi a0,sp,276 - 76c0: 0000 unimp - 76c2: 7f84000f 0x7f84000f - 76c6: 8891 andi s1,s1,4 - 76c8: 067f 0x67f - 76ca: 911a add sp,sp,t1 - 76cc: 7ef0 flw fa2,124(a3) - 76ce: 4006 0x4006 - 76d0: 1e25 addi t3,t3,-23 - 76d2: 489f 000a e000 0xe000000a489f - 76d8: 000a c.slli zero,0x2 - 76da: 0f00 addi s0,sp,912 - 76dc: 9100 0x9100 - 76de: 7f88 flw fa0,56(a5) - 76e0: 7906 flw fs2,96(sp) - 76e2: 1a00 addi s0,sp,304 - 76e4: f091 bnez s1,75e8 <_start-0x7fff8a18> - 76e6: 067e slli a2,a2,0x1f - 76e8: 2540 fld fs0,136(a0) - 76ea: 9f1e add t5,t5,t2 - 76ec: 0ae0 addi s0,sp,348 - 76ee: 0000 unimp - 76f0: 0bc4 addi s1,sp,468 - 76f2: 0000 unimp - 76f4: 7f89000f 0x7f89000f - 76f8: 8891 andi s1,s1,4 - 76fa: 067f 0x67f - 76fc: 911a add sp,sp,t1 - 76fe: 7ef0 flw fa2,124(a3) - 7700: 4006 0x4006 - 7702: 1e25 addi t3,t3,-23 - 7704: a89f 000d b400 0xb400000da89f - 770a: 000d c.nop 3 - 770c: 0f00 addi s0,sp,912 - 770e: 8900 0x8900 - 7710: 917f 0x917f - 7712: 7f88 flw fa0,56(a5) - 7714: 1a06 slli s4,s4,0x21 - 7716: f091 bnez s1,761a <_start-0x7fff89e6> - 7718: 067e slli a2,a2,0x1f - 771a: 2540 fld fs0,136(a0) - 771c: 9f1e add t5,t5,t2 - ... - 7726: 05cc addi a1,sp,708 - 7728: 0000 unimp - 772a: 05e4 addi s1,sp,716 - 772c: 0000 unimp - 772e: 0001 nop - 7730: 005c addi a5,sp,4 - 7732: 0000 unimp - 7734: 0000 unimp - 7736: 0000 unimp - 7738: b400 fsd fs0,40(s0) - 773a: 0005 c.nop 1 - 773c: c400 sw s0,8(s0) - 773e: 0300000b 0x300000b - 7742: 9100 0x9100 - 7744: 7ef0 flw fa2,124(a3) - 7746: 0da8 addi a0,sp,728 - 7748: 0000 unimp - 774a: 0db4 addi a3,sp,728 - 774c: 0000 unimp - 774e: f0910003 lb zero,-247(sp) - 7752: 007e c.slli zero,0x1f - 7754: 0000 unimp - 7756: 0000 unimp - 7758: 0000 unimp - 775a: b400 fsd fs0,40(s0) - 775c: 0005 c.nop 1 - 775e: 2000 fld fs0,0(s0) - 7760: 01000007 vlbuff.v v0,(zero),v0.t - 7764: 6f00 flw fs0,24(a4) - 7766: 0720 addi s0,sp,904 - 7768: 0000 unimp - 776a: 0bc4 addi s1,sp,468 - 776c: 0000 unimp - 776e: f2910003 lb zero,-215(sp) - 7772: a87e fsd ft11,16(sp) - 7774: 000d c.nop 3 - 7776: b400 fsd fs0,40(s0) - 7778: 000d c.nop 3 - 777a: 0300 addi s0,sp,384 - 777c: 9100 0x9100 - 777e: 7ef2 flw ft9,60(sp) - ... - 7788: 05b4 addi a3,sp,712 - 778a: 0000 unimp - 778c: 0bc4 addi s1,sp,468 - 778e: 0000 unimp - 7790: 0001 nop - 7792: a858 fsd fa4,144(s0) - 7794: 000d c.nop 3 - 7796: b400 fsd fs0,40(s0) - 7798: 000d c.nop 3 - 779a: 0100 addi s0,sp,128 - 779c: 5800 lw s0,48(s0) - ... - 77a6: 0608 addi a0,sp,768 - 77a8: 0000 unimp - 77aa: 0650 addi a2,sp,772 - 77ac: 0000 unimp - 77ae: 0001 nop - 77b0: 5061 c.li zero,-8 - 77b2: 0006 c.slli zero,0x1 - 77b4: 6c00 flw fs0,24(s0) - 77b6: 06000007 0x6000007 - 77ba: 7c00 flw fs0,56(s0) - 77bc: 8c00 0x8c00 - 77be: 1e00 addi s0,sp,816 - 77c0: 6c9f 0007 6000 0x600000076c9f - 77c6: 0008 0x8 - 77c8: 0b00 addi s0,sp,400 - 77ca: 9100 0x9100 - 77cc: 7f80 flw fs0,56(a5) - 77ce: 8906 mv s2,ra - 77d0: 1a00 addi s0,sp,304 - 77d2: 007c addi a5,sp,12 - 77d4: 9f1e add t5,t5,t2 - 77d6: 0860 addi s0,sp,28 - 77d8: 0000 unimp - 77da: 0894 addi a3,sp,80 - 77dc: 0000 unimp - 77de: 8091000b 0x8091000b - 77e2: 067f 0x67f - 77e4: 008c addi a1,sp,64 - 77e6: 7c1a flw fs8,164(sp) - 77e8: 1e00 addi s0,sp,816 - 77ea: 949f 0008 e000 0xe0000008949f - 77f0: 0008 0x8 - 77f2: 0c00 addi s0,sp,528 - 77f4: 9100 0x9100 - 77f6: 7f80 flw fs0,56(a5) - 77f8: 0a06 slli s4,s4,0x1 - 77fa: ffff 0xffff - 77fc: 7c1a flw fs8,164(sp) - 77fe: 1e00 addi s0,sp,816 - 7800: e09f 0008 e400 0xe4000008e09f - 7806: 0008 0x8 - 7808: 0b00 addi s0,sp,400 - 780a: 7a00 flw fs0,48(a2) - 780c: 917f 0x917f - 780e: 7f80 flw fs0,56(a5) - 7810: 1a06 slli s4,s4,0x21 - 7812: 007c addi a5,sp,12 - 7814: 9f1e add t5,t5,t2 - 7816: 08e4 addi s1,sp,92 - 7818: 0000 unimp - 781a: 08e8 addi a0,sp,92 - 781c: 0000 unimp - 781e: 000c 0xc - 7820: 8091 srli s1,s1,0x4 - 7822: 067f 0x67f - 7824: ff0a fsw ft2,188(sp) - 7826: 1aff 0x1aff - 7828: 007c addi a5,sp,12 - 782a: 9f1e add t5,t5,t2 - 782c: 08e8 addi a0,sp,92 - 782e: 0000 unimp - 7830: 0934 addi a3,sp,152 - 7832: 0000 unimp - 7834: 7f84000b 0x7f84000b - 7838: 8091 srli s1,s1,0x4 - 783a: 067f 0x67f - 783c: 7c1a flw fs8,164(sp) - 783e: 1e00 addi s0,sp,816 - 7840: 349f 0009 5800 0x58000009349f - 7846: 0009 c.nop 2 - 7848: 0b00 addi s0,sp,400 - 784a: 9100 0x9100 - 784c: 7f80 flw fs0,56(a5) - 784e: 8406 mv s0,ra - 7850: 1a00 addi s0,sp,304 - 7852: 007c addi a5,sp,12 - 7854: 9f1e add t5,t5,t2 - 7856: 0958 addi a4,sp,148 - 7858: 0000 unimp - 785a: 0998 addi a4,sp,208 - 785c: 0000 unimp - 785e: 7f85000b 0x7f85000b - 7862: 8091 srli s1,s1,0x4 - 7864: 067f 0x67f - 7866: 7c1a flw fs8,164(sp) - 7868: 1e00 addi s0,sp,816 - 786a: 989f 0009 e000 0xe0000009989f - 7870: 0009 c.nop 2 - 7872: 1000 addi s0,sp,32 - 7874: 8500 0x8500 - 7876: 917f 0x917f - 7878: 7ef8 flw fa4,124(a3) - 787a: 1a06 slli s4,s4,0x21 - 787c: 7f85 lui t6,0xfffe1 - 787e: 8091 srli s1,s1,0x4 - 7880: 067f 0x67f - 7882: 1e1a slli t3,t3,0x26 - 7884: e09f 0009 ec00 0xec000009e09f - 788a: 0009 c.nop 2 - 788c: 1000 addi s0,sp,32 - 788e: 9100 0x9100 - 7890: 7ef8 flw fa4,124(a3) - 7892: 7906 flw fs2,96(sp) - 7894: 1a00 addi s0,sp,304 - 7896: 8091 srli s1,s1,0x4 - 7898: 067f 0x67f - 789a: 0079 c.nop 30 - 789c: 1e1a slli t3,t3,0x26 - 789e: ec9f 0009 4800 0x48000009ec9f - 78a4: 000a c.slli zero,0x2 - 78a6: 1000 addi s0,sp,32 - 78a8: 8400 0x8400 - 78aa: 917f 0x917f - 78ac: 7ef8 flw fa4,124(a3) - 78ae: 1a06 slli s4,s4,0x21 - 78b0: 7f84 flw fs1,56(a5) - 78b2: 8091 srli s1,s1,0x4 - 78b4: 067f 0x67f - 78b6: 1e1a slli t3,t3,0x26 - 78b8: 489f 000a e000 0xe000000a489f - 78be: 000a c.slli zero,0x2 - 78c0: 1000 addi s0,sp,32 - 78c2: 9100 0x9100 - 78c4: 7ef8 flw fa4,124(a3) - 78c6: 7906 flw fs2,96(sp) - 78c8: 1a00 addi s0,sp,304 - 78ca: 8091 srli s1,s1,0x4 - 78cc: 067f 0x67f - 78ce: 0079 c.nop 30 - 78d0: 1e1a slli t3,t3,0x26 - 78d2: e09f 000a c400 0xc400000ae09f - 78d8: 1000000b 0x1000000b - 78dc: 8900 0x8900 - 78de: 917f 0x917f - 78e0: 7ef8 flw fa4,124(a3) - 78e2: 1a06 slli s4,s4,0x21 - 78e4: 7f89 lui t6,0xfffe2 - 78e6: 8091 srli s1,s1,0x4 - 78e8: 067f 0x67f - 78ea: 1e1a slli t3,t3,0x26 - 78ec: a89f 000d b400 0xb400000da89f - 78f2: 000d c.nop 3 - 78f4: 1000 addi s0,sp,32 - 78f6: 8900 0x8900 - 78f8: 917f 0x917f - 78fa: 7ef8 flw fa4,124(a3) - 78fc: 1a06 slli s4,s4,0x21 - 78fe: 7f89 lui t6,0xfffe2 - 7900: 8091 srli s1,s1,0x4 - 7902: 067f 0x67f - 7904: 1e1a slli t3,t3,0x26 - 7906: 009f 0000 0000 0x9f - 790c: 0000 unimp - 790e: 0800 addi s0,sp,16 - 7910: 0006 c.slli zero,0x1 - 7912: 1400 addi s0,sp,544 - 7914: 0006 c.slli zero,0x1 - 7916: 0600 addi s0,sp,768 - 7918: 8500 0x8500 - 791a: 7c00 flw fs0,56(s0) - 791c: 1e00 addi s0,sp,816 - 791e: 149f 0006 1800 0x18000006149f - 7924: 0006 c.slli zero,0x1 - 7926: 0100 addi s0,sp,128 - 7928: 5600 lw s0,40(a2) - 792a: 0618 addi a4,sp,768 - 792c: 0000 unimp - 792e: 0620 addi s0,sp,776 - 7930: 0000 unimp - 7932: 0006 c.slli zero,0x1 - 7934: 0085 addi ra,ra,1 - 7936: 007c addi a5,sp,12 - 7938: 9f1e add t5,t5,t2 - 793a: 0620 addi s0,sp,776 - 793c: 0000 unimp - 793e: 0644 addi s1,sp,772 - 7940: 0000 unimp - 7942: 0001 nop - 7944: 4456 lw s0,84(sp) - 7946: 0006 c.slli zero,0x1 - 7948: e000 fsw fs0,0(s0) - 794a: 0006 c.slli zero,0x1 - 794c: 0f00 addi s0,sp,912 - 794e: 8500 0x8500 - 7950: 7c00 flw fs0,56(s0) - 7952: 1e00 addi s0,sp,816 - 7954: 008c0077 0x8c0077 - 7958: 221e fld ft4,448(sp) - 795a: 008a slli ra,ra,0x2 - 795c: 9f22 add t5,t5,s0 - 795e: 06e0 addi s0,sp,844 - 7960: 0000 unimp - 7962: 0764 addi s1,sp,908 - 7964: 0000 unimp - 7966: 0014 0x14 - 7968: 0085 addi ra,ra,1 - 796a: 007c addi a5,sp,12 - 796c: 771e flw fa4,228(sp) - 796e: 8c00 0x8c00 - 7970: 1e00 addi s0,sp,816 - 7972: 7c22 flw fs8,40(sp) - 7974: 8c00 0x8c00 - 7976: 1e00 addi s0,sp,816 - 7978: 2540 fld fs0,136(a0) - 797a: 9f22 add t5,t5,s0 - 797c: 0764 addi s1,sp,908 - 797e: 0000 unimp - 7980: 076c addi a1,sp,908 - 7982: 0000 unimp - 7984: 0018 0x18 - 7986: 8091 srli s1,s1,0x4 - 7988: 067f 0x67f - 798a: 2540 fld fs0,136(a0) - 798c: 007c addi a5,sp,12 - 798e: 771e flw fa4,228(sp) - 7990: 8c00 0x8c00 - 7992: 1e00 addi s0,sp,816 - 7994: 7c22 flw fs8,40(sp) - 7996: 8c00 0x8c00 - 7998: 1e00 addi s0,sp,816 - 799a: 2540 fld fs0,136(a0) - 799c: 9f22 add t5,t5,s0 - 799e: 076c addi a1,sp,908 - 79a0: 0000 unimp - 79a2: 0860 addi s0,sp,28 - 79a4: 0000 unimp - 79a6: 0022 c.slli zero,0x8 - 79a8: 8091 srli s1,s1,0x4 - 79aa: 067f 0x67f - 79ac: 2540 fld fs0,136(a0) - 79ae: 007c addi a5,sp,12 - 79b0: 911e add sp,sp,t2 - 79b2: 7f80 flw fs0,56(a5) - 79b4: 8906 mv s2,ra - 79b6: 1a00 addi s0,sp,304 - 79b8: 221e0077 0x221e0077 - 79bc: 8091 srli s1,s1,0x4 - 79be: 067f 0x67f - 79c0: 0089 addi ra,ra,2 - 79c2: 7c1a flw fs8,164(sp) - 79c4: 1e00 addi s0,sp,816 - 79c6: 2540 fld fs0,136(a0) - 79c8: 9f22 add t5,t5,s0 - 79ca: 0860 addi s0,sp,28 - 79cc: 0000 unimp - 79ce: 0894 addi a3,sp,80 - 79d0: 0000 unimp - 79d2: 0022 c.slli zero,0x8 - 79d4: 8091 srli s1,s1,0x4 - 79d6: 067f 0x67f - 79d8: 2540 fld fs0,136(a0) - 79da: 007c addi a5,sp,12 - 79dc: 911e add sp,sp,t2 - 79de: 7f80 flw fs0,56(a5) - 79e0: 8c06 mv s8,ra - 79e2: 1a00 addi s0,sp,304 - 79e4: 221e0077 0x221e0077 - 79e8: 8091 srli s1,s1,0x4 - 79ea: 067f 0x67f - 79ec: 008c addi a1,sp,64 - 79ee: 7c1a flw fs8,164(sp) - 79f0: 1e00 addi s0,sp,816 - 79f2: 2540 fld fs0,136(a0) - 79f4: 9f22 add t5,t5,s0 - 79f6: 0894 addi a3,sp,80 - 79f8: 0000 unimp - 79fa: 08e0 addi s0,sp,92 - 79fc: 0000 unimp - 79fe: 0024 addi s1,sp,8 - 7a00: 8091 srli s1,s1,0x4 - 7a02: 067f 0x67f - 7a04: 2540 fld fs0,136(a0) - 7a06: 007c addi a5,sp,12 - 7a08: 911e add sp,sp,t2 - 7a0a: 7f80 flw fs0,56(a5) - 7a0c: 0a06 slli s4,s4,0x1 - 7a0e: ffff 0xffff - 7a10: 771a flw fa4,164(sp) - 7a12: 1e00 addi s0,sp,816 - 7a14: 9122 add sp,sp,s0 - 7a16: 7f80 flw fs0,56(a5) - 7a18: 0a06 slli s4,s4,0x1 - 7a1a: ffff 0xffff - 7a1c: 7c1a flw fs8,164(sp) - 7a1e: 1e00 addi s0,sp,816 - 7a20: 2540 fld fs0,136(a0) - 7a22: 9f22 add t5,t5,s0 - 7a24: 08e0 addi s0,sp,92 - 7a26: 0000 unimp - 7a28: 08e4 addi s1,sp,92 - 7a2a: 0000 unimp - 7a2c: 0022 c.slli zero,0x8 - 7a2e: 8091 srli s1,s1,0x4 - 7a30: 067f 0x67f - 7a32: 2540 fld fs0,136(a0) - 7a34: 007c addi a5,sp,12 - 7a36: 7a1e flw fs4,228(sp) - 7a38: 917f 0x917f - 7a3a: 7f80 flw fs0,56(a5) - 7a3c: 1a06 slli s4,s4,0x21 - 7a3e: 221e0077 0x221e0077 - 7a42: 7f7a flw ft10,188(sp) - 7a44: 8091 srli s1,s1,0x4 - 7a46: 067f 0x67f - 7a48: 7c1a flw fs8,164(sp) - 7a4a: 1e00 addi s0,sp,816 - 7a4c: 2540 fld fs0,136(a0) - 7a4e: 9f22 add t5,t5,s0 - 7a50: 08e4 addi s1,sp,92 - 7a52: 0000 unimp - 7a54: 08e8 addi a0,sp,92 - 7a56: 0000 unimp - 7a58: 0024 addi s1,sp,8 - 7a5a: 8091 srli s1,s1,0x4 - 7a5c: 067f 0x67f - 7a5e: 2540 fld fs0,136(a0) - 7a60: 007c addi a5,sp,12 - 7a62: 911e add sp,sp,t2 - 7a64: 7f80 flw fs0,56(a5) - 7a66: 0a06 slli s4,s4,0x1 - 7a68: ffff 0xffff - 7a6a: 771a flw fa4,164(sp) - 7a6c: 1e00 addi s0,sp,816 - 7a6e: 9122 add sp,sp,s0 - 7a70: 7f80 flw fs0,56(a5) - 7a72: 0a06 slli s4,s4,0x1 - 7a74: ffff 0xffff - 7a76: 7c1a flw fs8,164(sp) - 7a78: 1e00 addi s0,sp,816 - 7a7a: 2540 fld fs0,136(a0) - 7a7c: 9f22 add t5,t5,s0 - 7a7e: 08e8 addi a0,sp,92 - 7a80: 0000 unimp - 7a82: 0934 addi a3,sp,152 - 7a84: 0000 unimp - 7a86: 0022 c.slli zero,0x8 - 7a88: 8091 srli s1,s1,0x4 - 7a8a: 067f 0x67f - 7a8c: 2540 fld fs0,136(a0) - 7a8e: 007c addi a5,sp,12 - 7a90: 841e mv s0,t2 - 7a92: 917f 0x917f - 7a94: 7f80 flw fs0,56(a5) - 7a96: 1a06 slli s4,s4,0x21 - 7a98: 221e0077 0x221e0077 - 7a9c: 7f84 flw fs1,56(a5) - 7a9e: 8091 srli s1,s1,0x4 - 7aa0: 067f 0x67f - 7aa2: 7c1a flw fs8,164(sp) - 7aa4: 1e00 addi s0,sp,816 - 7aa6: 2540 fld fs0,136(a0) - 7aa8: 9f22 add t5,t5,s0 - 7aaa: 0934 addi a3,sp,152 - 7aac: 0000 unimp - 7aae: 0958 addi a4,sp,148 - 7ab0: 0000 unimp - 7ab2: 0022 c.slli zero,0x8 - 7ab4: 8091 srli s1,s1,0x4 - 7ab6: 067f 0x67f - 7ab8: 2540 fld fs0,136(a0) - 7aba: 007c addi a5,sp,12 - 7abc: 911e add sp,sp,t2 - 7abe: 7f80 flw fs0,56(a5) - 7ac0: 8406 mv s0,ra - 7ac2: 1a00 addi s0,sp,304 - 7ac4: 221e0077 0x221e0077 - 7ac8: 8091 srli s1,s1,0x4 - 7aca: 067f 0x67f - 7acc: 0084 addi s1,sp,64 - 7ace: 7c1a flw fs8,164(sp) - 7ad0: 1e00 addi s0,sp,816 - 7ad2: 2540 fld fs0,136(a0) - 7ad4: 9f22 add t5,t5,s0 - 7ad6: 0958 addi a4,sp,148 - 7ad8: 0000 unimp - 7ada: 0998 addi a4,sp,208 - 7adc: 0000 unimp - 7ade: 0022 c.slli zero,0x8 - 7ae0: 8091 srli s1,s1,0x4 - 7ae2: 067f 0x67f - 7ae4: 2540 fld fs0,136(a0) - 7ae6: 007c addi a5,sp,12 - 7ae8: 851e mv a0,t2 - 7aea: 917f 0x917f - 7aec: 7f80 flw fs0,56(a5) - 7aee: 1a06 slli s4,s4,0x21 - 7af0: 221e0077 0x221e0077 - 7af4: 7f85 lui t6,0xfffe1 - 7af6: 8091 srli s1,s1,0x4 - 7af8: 067f 0x67f - 7afa: 7c1a flw fs8,164(sp) - 7afc: 1e00 addi s0,sp,816 - 7afe: 2540 fld fs0,136(a0) - 7b00: 9f22 add t5,t5,s0 - 7b02: 0998 addi a4,sp,208 - 7b04: 0000 unimp - 7b06: 09a8 addi a0,sp,216 - 7b08: 0000 unimp - 7b0a: 002c addi a1,sp,8 - 7b0c: 7f85 lui t6,0xfffe1 - 7b0e: f891 bnez s1,7a22 <_start-0x7fff85de> - 7b10: 067e slli a2,a2,0x1f - 7b12: 911a add sp,sp,t1 - 7b14: 7f80 flw fs0,56(a5) - 7b16: 4006 0x4006 - 7b18: 1e25 addi t3,t3,-23 - 7b1a: 7f85 lui t6,0xfffe1 - 7b1c: 8091 srli s1,s1,0x4 - 7b1e: 067f 0x67f - 7b20: 771a flw fa4,164(sp) - 7b22: 1e00 addi s0,sp,816 - 7b24: 8522 mv a0,s0 - 7b26: 917f 0x917f - 7b28: 7ef8 flw fa4,124(a3) - 7b2a: 1a06 slli s4,s4,0x21 - 7b2c: 7f85 lui t6,0xfffe1 - 7b2e: 8091 srli s1,s1,0x4 - 7b30: 067f 0x67f - 7b32: 1e1a slli t3,t3,0x26 - 7b34: 2540 fld fs0,136(a0) - 7b36: 9f22 add t5,t5,s0 - 7b38: 09a8 addi a0,sp,216 - 7b3a: 0000 unimp - 7b3c: 09e0 addi s0,sp,220 - 7b3e: 0000 unimp - 7b40: 0030 addi a2,sp,8 - 7b42: 7f85 lui t6,0xfffe1 - 7b44: f891 bnez s1,7a58 <_start-0x7fff85a8> - 7b46: 067e slli a2,a2,0x1f - 7b48: 911a add sp,sp,t1 - 7b4a: 7f80 flw fs0,56(a5) - 7b4c: 4006 0x4006 - 7b4e: 1e25 addi t3,t3,-23 - 7b50: 7f85 lui t6,0xfffe1 - 7b52: 8091 srli s1,s1,0x4 - 7b54: 067f 0x67f - 7b56: 911a add sp,sp,t1 - 7b58: 7ef8 flw fa4,124(a3) - 7b5a: 4006 0x4006 - 7b5c: 1e25 addi t3,t3,-23 - 7b5e: 8522 mv a0,s0 - 7b60: 917f 0x917f - 7b62: 7ef8 flw fa4,124(a3) - 7b64: 1a06 slli s4,s4,0x21 - 7b66: 7f85 lui t6,0xfffe1 - 7b68: 8091 srli s1,s1,0x4 - 7b6a: 067f 0x67f - 7b6c: 1e1a slli t3,t3,0x26 - 7b6e: 2540 fld fs0,136(a0) - 7b70: 9f22 add t5,t5,s0 - 7b72: 09e0 addi s0,sp,220 - 7b74: 0000 unimp - 7b76: 09ec addi a1,sp,220 - 7b78: 0000 unimp - 7b7a: 0030 addi a2,sp,8 - 7b7c: f891 bnez s1,7a90 <_start-0x7fff8570> - 7b7e: 067e slli a2,a2,0x1f - 7b80: 0079 c.nop 30 - 7b82: 911a add sp,sp,t1 - 7b84: 7f80 flw fs0,56(a5) - 7b86: 4006 0x4006 - 7b88: 1e25 addi t3,t3,-23 - 7b8a: 8091 srli s1,s1,0x4 - 7b8c: 067f 0x67f - 7b8e: 0079 c.nop 30 - 7b90: 911a add sp,sp,t1 - 7b92: 7ef8 flw fa4,124(a3) - 7b94: 4006 0x4006 - 7b96: 1e25 addi t3,t3,-23 - 7b98: 9122 add sp,sp,s0 - 7b9a: 7ef8 flw fa4,124(a3) - 7b9c: 7906 flw fs2,96(sp) - 7b9e: 1a00 addi s0,sp,304 - 7ba0: 8091 srli s1,s1,0x4 - 7ba2: 067f 0x67f - 7ba4: 0079 c.nop 30 - 7ba6: 1e1a slli t3,t3,0x26 - 7ba8: 2540 fld fs0,136(a0) - 7baa: 9f22 add t5,t5,s0 - 7bac: 09ec addi a1,sp,220 - 7bae: 0000 unimp - 7bb0: 0a48 addi a0,sp,276 - 7bb2: 0000 unimp - 7bb4: 0030 addi a2,sp,8 - 7bb6: 7f84 flw fs1,56(a5) - 7bb8: f891 bnez s1,7acc <_start-0x7fff8534> - 7bba: 067e slli a2,a2,0x1f - 7bbc: 911a add sp,sp,t1 - 7bbe: 7f80 flw fs0,56(a5) - 7bc0: 4006 0x4006 - 7bc2: 1e25 addi t3,t3,-23 - 7bc4: 7f84 flw fs1,56(a5) - 7bc6: 8091 srli s1,s1,0x4 - 7bc8: 067f 0x67f - 7bca: 911a add sp,sp,t1 - 7bcc: 7ef8 flw fa4,124(a3) - 7bce: 4006 0x4006 - 7bd0: 1e25 addi t3,t3,-23 - 7bd2: 8422 mv s0,s0 - 7bd4: 917f 0x917f - 7bd6: 7ef8 flw fa4,124(a3) - 7bd8: 1a06 slli s4,s4,0x21 - 7bda: 7f84 flw fs1,56(a5) - 7bdc: 8091 srli s1,s1,0x4 - 7bde: 067f 0x67f - 7be0: 1e1a slli t3,t3,0x26 - 7be2: 2540 fld fs0,136(a0) - 7be4: 9f22 add t5,t5,s0 - 7be6: 0a48 addi a0,sp,276 - 7be8: 0000 unimp - 7bea: 0ae0 addi s0,sp,348 - 7bec: 0000 unimp - 7bee: 0030 addi a2,sp,8 - 7bf0: f891 bnez s1,7b04 <_start-0x7fff84fc> - 7bf2: 067e slli a2,a2,0x1f - 7bf4: 0079 c.nop 30 - 7bf6: 911a add sp,sp,t1 - 7bf8: 7f80 flw fs0,56(a5) - 7bfa: 4006 0x4006 - 7bfc: 1e25 addi t3,t3,-23 - 7bfe: 8091 srli s1,s1,0x4 - 7c00: 067f 0x67f - 7c02: 0079 c.nop 30 - 7c04: 911a add sp,sp,t1 - 7c06: 7ef8 flw fa4,124(a3) - 7c08: 4006 0x4006 - 7c0a: 1e25 addi t3,t3,-23 - 7c0c: 9122 add sp,sp,s0 - 7c0e: 7ef8 flw fa4,124(a3) - 7c10: 7906 flw fs2,96(sp) - 7c12: 1a00 addi s0,sp,304 - 7c14: 8091 srli s1,s1,0x4 - 7c16: 067f 0x67f - 7c18: 0079 c.nop 30 - 7c1a: 1e1a slli t3,t3,0x26 - 7c1c: 2540 fld fs0,136(a0) - 7c1e: 9f22 add t5,t5,s0 - 7c20: 0ae0 addi s0,sp,348 - 7c22: 0000 unimp - 7c24: 0bc4 addi s1,sp,468 - 7c26: 0000 unimp - 7c28: 0030 addi a2,sp,8 - 7c2a: 7f89 lui t6,0xfffe2 - 7c2c: f891 bnez s1,7b40 <_start-0x7fff84c0> - 7c2e: 067e slli a2,a2,0x1f - 7c30: 911a add sp,sp,t1 - 7c32: 7f80 flw fs0,56(a5) - 7c34: 4006 0x4006 - 7c36: 1e25 addi t3,t3,-23 - 7c38: 7f89 lui t6,0xfffe2 - 7c3a: 8091 srli s1,s1,0x4 - 7c3c: 067f 0x67f - 7c3e: 911a add sp,sp,t1 - 7c40: 7ef8 flw fa4,124(a3) - 7c42: 4006 0x4006 - 7c44: 1e25 addi t3,t3,-23 - 7c46: 8922 mv s2,s0 - 7c48: 917f 0x917f - 7c4a: 7ef8 flw fa4,124(a3) - 7c4c: 1a06 slli s4,s4,0x21 - 7c4e: 7f89 lui t6,0xfffe2 - 7c50: 8091 srli s1,s1,0x4 - 7c52: 067f 0x67f - 7c54: 1e1a slli t3,t3,0x26 - 7c56: 2540 fld fs0,136(a0) - 7c58: 9f22 add t5,t5,s0 - 7c5a: 0da8 addi a0,sp,728 - 7c5c: 0000 unimp - 7c5e: 0db4 addi a3,sp,728 - 7c60: 0000 unimp - 7c62: 0030 addi a2,sp,8 - 7c64: 7f89 lui t6,0xfffe2 - 7c66: f891 bnez s1,7b7a <_start-0x7fff8486> - 7c68: 067e slli a2,a2,0x1f - 7c6a: 911a add sp,sp,t1 - 7c6c: 7f80 flw fs0,56(a5) - 7c6e: 4006 0x4006 - 7c70: 1e25 addi t3,t3,-23 - 7c72: 7f89 lui t6,0xfffe2 - 7c74: 8091 srli s1,s1,0x4 - 7c76: 067f 0x67f - 7c78: 911a add sp,sp,t1 - 7c7a: 7ef8 flw fa4,124(a3) - 7c7c: 4006 0x4006 - 7c7e: 1e25 addi t3,t3,-23 - 7c80: 8922 mv s2,s0 - 7c82: 917f 0x917f - 7c84: 7ef8 flw fa4,124(a3) - 7c86: 1a06 slli s4,s4,0x21 - 7c88: 7f89 lui t6,0xfffe2 - 7c8a: 8091 srli s1,s1,0x4 - 7c8c: 067f 0x67f - 7c8e: 1e1a slli t3,t3,0x26 - 7c90: 2540 fld fs0,136(a0) - 7c92: 9f22 add t5,t5,s0 - ... - 7c9c: 060c addi a1,sp,768 - 7c9e: 0000 unimp - 7ca0: 063c addi a5,sp,776 - 7ca2: 0000 unimp - 7ca4: 0001 nop - 7ca6: 3c69 jal 7740 <_start-0x7fff88c0> - 7ca8: 0006 c.slli zero,0x1 - 7caa: 6c00 flw fs0,24(s0) - 7cac: 06000007 0x6000007 - 7cb0: 7700 flw fs0,40(a4) - 7cb2: 8c00 0x8c00 - 7cb4: 1e00 addi s0,sp,816 - 7cb6: 6c9f 0007 6000 0x600000076c9f - 7cbc: 0008 0x8 - 7cbe: 0b00 addi s0,sp,400 - 7cc0: 9100 0x9100 - 7cc2: 7f80 flw fs0,56(a5) - 7cc4: 8906 mv s2,ra - 7cc6: 1a00 addi s0,sp,304 - 7cc8: 9f1e0077 0x9f1e0077 - 7ccc: 0860 addi s0,sp,28 - 7cce: 0000 unimp - 7cd0: 0894 addi a3,sp,80 - 7cd2: 0000 unimp - 7cd4: 8091000b 0x8091000b - 7cd8: 067f 0x67f - 7cda: 008c addi a1,sp,64 - 7cdc: 771a flw fa4,164(sp) - 7cde: 1e00 addi s0,sp,816 - 7ce0: 949f 0008 e000 0xe0000008949f - 7ce6: 0008 0x8 - 7ce8: 0c00 addi s0,sp,528 - 7cea: 9100 0x9100 - 7cec: 7f80 flw fs0,56(a5) - 7cee: 0a06 slli s4,s4,0x1 - 7cf0: ffff 0xffff - 7cf2: 771a flw fa4,164(sp) - 7cf4: 1e00 addi s0,sp,816 - 7cf6: e09f 0008 e400 0xe4000008e09f - 7cfc: 0008 0x8 - 7cfe: 0b00 addi s0,sp,400 - 7d00: 7a00 flw fs0,48(a2) - 7d02: 917f 0x917f - 7d04: 7f80 flw fs0,56(a5) - 7d06: 1a06 slli s4,s4,0x21 - 7d08: 9f1e0077 0x9f1e0077 - 7d0c: 08e4 addi s1,sp,92 - 7d0e: 0000 unimp - 7d10: 08e8 addi a0,sp,92 - 7d12: 0000 unimp - 7d14: 000c 0xc - 7d16: 8091 srli s1,s1,0x4 - 7d18: 067f 0x67f - 7d1a: ff0a fsw ft2,188(sp) - 7d1c: 1aff 0x1aff - 7d1e: 9f1e0077 0x9f1e0077 - 7d22: 08e8 addi a0,sp,92 - 7d24: 0000 unimp - 7d26: 0934 addi a3,sp,152 - 7d28: 0000 unimp - 7d2a: 7f84000b 0x7f84000b - 7d2e: 8091 srli s1,s1,0x4 - 7d30: 067f 0x67f - 7d32: 771a flw fa4,164(sp) - 7d34: 1e00 addi s0,sp,816 - 7d36: 349f 0009 5800 0x58000009349f - 7d3c: 0009 c.nop 2 - 7d3e: 0b00 addi s0,sp,400 - 7d40: 9100 0x9100 - 7d42: 7f80 flw fs0,56(a5) - 7d44: 8406 mv s0,ra - 7d46: 1a00 addi s0,sp,304 - 7d48: 9f1e0077 0x9f1e0077 - 7d4c: 0958 addi a4,sp,148 - 7d4e: 0000 unimp - 7d50: 09a8 addi a0,sp,216 - 7d52: 0000 unimp - 7d54: 7f85000b 0x7f85000b - 7d58: 8091 srli s1,s1,0x4 - 7d5a: 067f 0x67f - 7d5c: 771a flw fa4,164(sp) - 7d5e: 1e00 addi s0,sp,816 - 7d60: a89f 0009 e000 0xe0000009a89f - 7d66: 0009 c.nop 2 - 7d68: 0f00 addi s0,sp,912 - 7d6a: 8500 0x8500 - 7d6c: 917f 0x917f - 7d6e: 7f80 flw fs0,56(a5) - 7d70: 1a06 slli s4,s4,0x21 - 7d72: f891 bnez s1,7c86 <_start-0x7fff837a> - 7d74: 067e slli a2,a2,0x1f - 7d76: 2540 fld fs0,136(a0) - 7d78: 9f1e add t5,t5,t2 - 7d7a: 09e0 addi s0,sp,220 - 7d7c: 0000 unimp - 7d7e: 09ec addi a1,sp,220 - 7d80: 0000 unimp - 7d82: 8091000f 0x8091000f - 7d86: 067f 0x67f - 7d88: 0079 c.nop 30 - 7d8a: 911a add sp,sp,t1 - 7d8c: 7ef8 flw fa4,124(a3) - 7d8e: 4006 0x4006 - 7d90: 1e25 addi t3,t3,-23 - 7d92: ec9f 0009 4800 0x48000009ec9f - 7d98: 000a c.slli zero,0x2 - 7d9a: 0f00 addi s0,sp,912 - 7d9c: 8400 0x8400 - 7d9e: 917f 0x917f - 7da0: 7f80 flw fs0,56(a5) - 7da2: 1a06 slli s4,s4,0x21 - 7da4: f891 bnez s1,7cb8 <_start-0x7fff8348> - 7da6: 067e slli a2,a2,0x1f - 7da8: 2540 fld fs0,136(a0) - 7daa: 9f1e add t5,t5,t2 - 7dac: 0a48 addi a0,sp,276 - 7dae: 0000 unimp - 7db0: 0ae0 addi s0,sp,348 - 7db2: 0000 unimp - 7db4: 8091000f 0x8091000f - 7db8: 067f 0x67f - 7dba: 0079 c.nop 30 - 7dbc: 911a add sp,sp,t1 - 7dbe: 7ef8 flw fa4,124(a3) - 7dc0: 4006 0x4006 - 7dc2: 1e25 addi t3,t3,-23 - 7dc4: e09f 000a c400 0xc400000ae09f - 7dca: 0f00000b 0xf00000b - 7dce: 8900 0x8900 - 7dd0: 917f 0x917f - 7dd2: 7f80 flw fs0,56(a5) - 7dd4: 1a06 slli s4,s4,0x21 - 7dd6: f891 bnez s1,7cea <_start-0x7fff8316> - 7dd8: 067e slli a2,a2,0x1f - 7dda: 2540 fld fs0,136(a0) - 7ddc: 9f1e add t5,t5,t2 - 7dde: 0da8 addi a0,sp,728 - 7de0: 0000 unimp - 7de2: 0db4 addi a3,sp,728 - 7de4: 0000 unimp - 7de6: 7f89000f 0x7f89000f - 7dea: 8091 srli s1,s1,0x4 - 7dec: 067f 0x67f - 7dee: 911a add sp,sp,t1 - 7df0: 7ef8 flw fa4,124(a3) - 7df2: 4006 0x4006 - 7df4: 1e25 addi t3,t3,-23 - 7df6: 009f 0000 0000 0x9f - 7dfc: 0000 unimp - 7dfe: 2000 fld fs0,0(s0) - 7e00: 0006 c.slli zero,0x1 - 7e02: 3000 fld fs0,32(s0) - 7e04: 0006 c.slli zero,0x1 - 7e06: 0100 addi s0,sp,128 - 7e08: 6700 flw fs0,8(a4) - ... - 7e12: 0604 addi s1,sp,768 - 7e14: 0000 unimp - 7e16: 0608 addi a0,sp,768 - 7e18: 0000 unimp - 7e1a: 0001 nop - 7e1c: 0861 addi a6,a6,24 - 7e1e: 0006 c.slli zero,0x1 - 7e20: c400 sw s0,8(s0) - 7e22: 0300000b 0x300000b - 7e26: 9100 0x9100 - 7e28: 7ef8 flw fa4,124(a3) - 7e2a: 0da8 addi a0,sp,728 - 7e2c: 0000 unimp - 7e2e: 0db4 addi a3,sp,728 - 7e30: 0000 unimp - 7e32: f8910003 lb zero,-119(sp) - 7e36: 007e c.slli zero,0x1f - 7e38: 0000 unimp - 7e3a: 0000 unimp - 7e3c: 0000 unimp - 7e3e: 0400 addi s0,sp,512 - 7e40: 0006 c.slli zero,0x1 - 7e42: c400 sw s0,8(s0) - 7e44: 0300000b 0x300000b - 7e48: 9100 0x9100 - 7e4a: 7f80 flw fs0,56(a5) - 7e4c: 0da8 addi a0,sp,728 - 7e4e: 0000 unimp - 7e50: 0db4 addi a3,sp,728 - 7e52: 0000 unimp - 7e54: 80910003 lb zero,-2039(sp) - 7e58: 007f 0x7f - 7e5a: 0000 unimp - 7e5c: 0000 unimp - 7e5e: 0000 unimp - 7e60: 0400 addi s0,sp,512 - 7e62: 0006 c.slli zero,0x1 - 7e64: a800 fsd fs0,16(s0) - 7e66: 0009 c.nop 2 - 7e68: 0100 addi s0,sp,128 - 7e6a: 5700 lw s0,40(a4) - 7e6c: 09a8 addi a0,sp,216 - 7e6e: 0000 unimp - 7e70: 0bc4 addi s1,sp,468 - 7e72: 0000 unimp - 7e74: fa910003 lb zero,-87(sp) - 7e78: a87e fsd ft11,16(sp) - 7e7a: 000d c.nop 3 - 7e7c: b400 fsd fs0,40(s0) - 7e7e: 000d c.nop 3 - 7e80: 0300 addi s0,sp,384 - 7e82: 9100 0x9100 - 7e84: 7efa flw ft9,188(sp) - ... - 7e8e: 0604 addi s1,sp,768 - 7e90: 0000 unimp - 7e92: 0764 addi s1,sp,908 - 7e94: 0000 unimp - 7e96: 0001 nop - 7e98: 6465 lui s0,0x19 - 7e9a: c4000007 0xc4000007 - 7e9e: 0300000b 0x300000b - 7ea2: 9100 0x9100 - 7ea4: 7f82 flw ft11,32(sp) - 7ea6: 0da8 addi a0,sp,728 - 7ea8: 0000 unimp - 7eaa: 0db4 addi a3,sp,728 - 7eac: 0000 unimp - 7eae: 82910003 lb zero,-2007(sp) - 7eb2: 007f 0x7f - 7eb4: 0000 unimp - 7eb6: 0000 unimp - 7eb8: 0000 unimp - 7eba: 5800 lw s0,48(s0) - 7ebc: 0006 c.slli zero,0x1 - 7ebe: 8000 0x8000 - 7ec0: 0006 c.slli zero,0x1 - 7ec2: 0100 addi s0,sp,128 - 7ec4: 5a00 lw s0,48(a2) - 7ec6: 0680 addi s0,sp,832 - 7ec8: 0000 unimp - 7eca: 068c addi a1,sp,832 - 7ecc: 0000 unimp - 7ece: 002d c.nop 11 - 7ed0: 0075 c.nop 29 - 7ed2: 4b40 lw s0,20(a4) - 7ed4: 2224 fld fs1,64(a2) - 7ed6: 008e slli ra,ra,0x3 - 7ed8: 007e c.slli zero,0x1f - 7eda: 891e mv s2,t2 - 7edc: 1a00 addi s0,sp,304 - 7ede: 0079 c.nop 30 - 7ee0: 007e c.slli zero,0x1f - 7ee2: 8f1e mv t5,t2 - 7ee4: 8e00 0x8e00 - 7ee6: 1e00 addi s0,sp,816 - 7ee8: 8e22 mv t3,s0 - 7eea: 7e00 flw fs0,56(a2) - 7eec: 1e00 addi s0,sp,816 - 7eee: 2540 fld fs0,136(a0) - 7ef0: 8922 mv s2,s0 - 7ef2: 1a00 addi s0,sp,304 - 7ef4: 2440 fld fs0,136(s0) - 7ef6: 4022 0x4022 - 7ef8: 2d22244b 0x2d22244b - 7efc: 009f 0000 0000 0x9f - 7f02: 0000 unimp - 7f04: 5800 lw s0,48(s0) - 7f06: 0006 c.slli zero,0x1 - 7f08: 8000 0x8000 - 7f0a: 0006 c.slli zero,0x1 - 7f0c: 1100 addi s0,sp,160 - 7f0e: 8400 0x8400 - 7f10: 4000 lw s0,0(s0) - 7f12: 7a22244b fnmsub.d fs0,ft4,ft2,fa5,rdn - 7f16: 4000 lw s0,0(s0) - 7f18: 2d22244b 0x2d22244b - 7f1c: ff08 fsw fa0,56(a4) - 7f1e: 9f1a add t5,t5,t1 - 7f20: 0680 addi s0,sp,832 - 7f22: 0000 unimp - 7f24: 068c addi a1,sp,832 - 7f26: 0000 unimp - 7f28: 0084003b 0x84003b - 7f2c: 4b40 lw s0,20(a4) - 7f2e: 2224 fld fs1,64(a2) - 7f30: 0075 c.nop 29 - 7f32: 4b40 lw s0,20(a4) - 7f34: 2224 fld fs1,64(a2) - 7f36: 008e slli ra,ra,0x3 - 7f38: 007e c.slli zero,0x1f - 7f3a: 891e mv s2,t2 - 7f3c: 1a00 addi s0,sp,304 - 7f3e: 0079 c.nop 30 - 7f40: 007e c.slli zero,0x1f - 7f42: 8f1e mv t5,t2 - 7f44: 8e00 0x8e00 - 7f46: 1e00 addi s0,sp,816 - 7f48: 8e22 mv t3,s0 - 7f4a: 7e00 flw fs0,56(a2) - 7f4c: 1e00 addi s0,sp,816 - 7f4e: 2540 fld fs0,136(a0) - 7f50: 8922 mv s2,s0 - 7f52: 1a00 addi s0,sp,304 - 7f54: 2440 fld fs0,136(s0) - 7f56: 4022 0x4022 - 7f58: 2d22244b 0x2d22244b - 7f5c: 4b40 lw s0,20(a4) - 7f5e: 2224 fld fs1,64(a2) - 7f60: 082d addi a6,a6,11 - 7f62: 1aff 0x1aff - 7f64: 009f 0000 0000 0x9f - 7f6a: 0000 unimp - 7f6c: 6800 flw fs0,16(s0) - 7f6e: 0006 c.slli zero,0x1 - 7f70: 7800 flw fs0,48(s0) - 7f72: 0006 c.slli zero,0x1 - 7f74: 0100 addi s0,sp,128 - 7f76: 6000 flw fs0,0(s0) - 7f78: 0678 addi a4,sp,780 - 7f7a: 0000 unimp - 7f7c: 0764 addi s1,sp,908 - 7f7e: 0000 unimp - 7f80: a491002f 0xa491002f - 7f84: 067f 0x67f - 7f86: 4b40 lw s0,20(a4) - 7f88: 2224 fld fs1,64(a2) - 7f8a: 008c addi a1,sp,64 - 7f8c: 891e007b 0x891e007b - 7f90: 1a00 addi s0,sp,304 - 7f92: 0085 addi ra,ra,1 - 7f94: 821e007b 0x821e007b - 7f98: 8c00 0x8c00 - 7f9a: 1e00 addi s0,sp,816 - 7f9c: 8c22 mv s8,s0 - 7f9e: 7b00 flw fs0,48(a4) - 7fa0: 1e00 addi s0,sp,816 - 7fa2: 2540 fld fs0,136(a0) - 7fa4: 8922 mv s2,s0 - 7fa6: 1a00 addi s0,sp,304 - 7fa8: 2440 fld fs0,136(s0) - 7faa: 4022 0x4022 - 7fac: 2d22244b 0x2d22244b - 7fb0: 649f 0007 6c00 0x6c000007649f - 7fb6: 33000007 vlseg2bff.v v0,(zero) - 7fba: 9100 0x9100 - 7fbc: 7fa4 flw fs1,120(a5) - 7fbe: 4006 0x4006 - 7fc0: 8c22244b 0x8c22244b - 7fc4: 7b00 flw fs0,48(a4) - 7fc6: 1e00 addi s0,sp,816 - 7fc8: 0089 addi ra,ra,2 - 7fca: 911a add sp,sp,t1 - 7fcc: 7f80 flw fs0,56(a5) - 7fce: 4006 0x4006 - 7fd0: 7b25 lui s6,0xfffe9 - 7fd2: 1e00 addi s0,sp,816 - 7fd4: 0082 c.slli64 ra - 7fd6: 008c addi a1,sp,64 - 7fd8: 221e fld ft4,448(sp) - 7fda: 008c addi a1,sp,64 - 7fdc: 401e007b 0x401e007b - 7fe0: 2225 jal 8108 <_start-0x7fff7ef8> - 7fe2: 0089 addi ra,ra,2 - 7fe4: 401a 0x401a - 7fe6: 2224 fld fs1,64(a2) - 7fe8: 4b40 lw s0,20(a4) - 7fea: 2224 fld fs1,64(a2) - 7fec: 9f2d 0x9f2d - 7fee: 076c addi a1,sp,908 - 7ff0: 0000 unimp - 7ff2: 0860 addi s0,sp,28 - 7ff4: 0000 unimp - 7ff6: 0042 c.slli zero,0x10 - 7ff8: a491 j 823c <_start-0x7fff7dc4> - 7ffa: 067f 0x67f - 7ffc: 4b40 lw s0,20(a4) - 7ffe: 2224 fld fs1,64(a2) - 8000: 8091 srli s1,s1,0x4 - 8002: 067f 0x67f - 8004: 0089 addi ra,ra,2 - 8006: 7b1a flw fs6,164(sp) - 8008: 1e00 addi s0,sp,816 - 800a: 0089 addi ra,ra,2 - 800c: 911a add sp,sp,t1 - 800e: 7f80 flw fs0,56(a5) - 8010: 4006 0x4006 - 8012: 7b25 lui s6,0xfffe9 - 8014: 1e00 addi s0,sp,816 - 8016: 8091 srli s1,s1,0x4 - 8018: 067f 0x67f - 801a: 0089 addi ra,ra,2 - 801c: 821a mv tp,t1 - 801e: 1e00 addi s0,sp,816 - 8020: 9122 add sp,sp,s0 - 8022: 7f80 flw fs0,56(a5) - 8024: 8906 mv s2,ra - 8026: 1a00 addi s0,sp,304 - 8028: 401e007b 0x401e007b - 802c: 2225 jal 8154 <_start-0x7fff7eac> - 802e: 0089 addi ra,ra,2 - 8030: 401a 0x401a - 8032: 2224 fld fs1,64(a2) - 8034: 4b40 lw s0,20(a4) - 8036: 2224 fld fs1,64(a2) - 8038: 9f2d 0x9f2d - 803a: 0860 addi s0,sp,28 - 803c: 0000 unimp - 803e: 0894 addi a3,sp,80 - 8040: 0000 unimp - 8042: 0042 c.slli zero,0x10 - 8044: a491 j 8288 <_start-0x7fff7d78> - 8046: 067f 0x67f - 8048: 4b40 lw s0,20(a4) - 804a: 2224 fld fs1,64(a2) - 804c: 8091 srli s1,s1,0x4 - 804e: 067f 0x67f - 8050: 008c addi a1,sp,64 - 8052: 7b1a flw fs6,164(sp) - 8054: 1e00 addi s0,sp,816 - 8056: 008c addi a1,sp,64 - 8058: 911a add sp,sp,t1 - 805a: 7f80 flw fs0,56(a5) - 805c: 4006 0x4006 - 805e: 7b25 lui s6,0xfffe9 - 8060: 1e00 addi s0,sp,816 - 8062: 8091 srli s1,s1,0x4 - 8064: 067f 0x67f - 8066: 008c addi a1,sp,64 - 8068: 821a mv tp,t1 - 806a: 1e00 addi s0,sp,816 - 806c: 9122 add sp,sp,s0 - 806e: 7f80 flw fs0,56(a5) - 8070: 8c06 mv s8,ra - 8072: 1a00 addi s0,sp,304 - 8074: 401e007b 0x401e007b - 8078: 2225 jal 81a0 <_start-0x7fff7e60> - 807a: 008c addi a1,sp,64 - 807c: 401a 0x401a - 807e: 2224 fld fs1,64(a2) - 8080: 4b40 lw s0,20(a4) - 8082: 2224 fld fs1,64(a2) - 8084: 9f2d 0x9f2d - 8086: 0894 addi a3,sp,80 - 8088: 0000 unimp - 808a: 08e0 addi s0,sp,92 - 808c: 0000 unimp - 808e: a4910047 0xa4910047 - 8092: 067f 0x67f - 8094: 4b40 lw s0,20(a4) - 8096: 2224 fld fs1,64(a2) - 8098: 8091 srli s1,s1,0x4 - 809a: 067f 0x67f - 809c: ff0a fsw ft2,188(sp) - 809e: 1aff 0x1aff - 80a0: 0a1e007b 0xa1e007b - 80a4: ffff 0xffff - 80a6: 911a add sp,sp,t1 - 80a8: 7f80 flw fs0,56(a5) - 80aa: 4006 0x4006 - 80ac: 7b25 lui s6,0xfffe9 - 80ae: 1e00 addi s0,sp,816 - 80b0: 8091 srli s1,s1,0x4 - 80b2: 067f 0x67f - 80b4: ff0a fsw ft2,188(sp) - 80b6: 1aff 0x1aff - 80b8: 0082 c.slli64 ra - 80ba: 221e fld ft4,448(sp) - 80bc: 8091 srli s1,s1,0x4 - 80be: 067f 0x67f - 80c0: ff0a fsw ft2,188(sp) - 80c2: 1aff 0x1aff - 80c4: 401e007b 0x401e007b - 80c8: 2225 jal 81f0 <_start-0x7fff7e10> - 80ca: ff0a fsw ft2,188(sp) - 80cc: 1aff 0x1aff - 80ce: 2440 fld fs0,136(s0) - 80d0: 4022 0x4022 - 80d2: 2d22244b 0x2d22244b - 80d6: e09f 0008 e400 0xe4000008e09f - 80dc: 0008 0x8 - 80de: 4200 lw s0,0(a2) - 80e0: 9100 0x9100 - 80e2: 7fa4 flw fs1,120(a5) - 80e4: 4006 0x4006 - 80e6: 7a22244b fnmsub.d fs0,ft4,ft2,fa5,rdn - 80ea: 917f 0x917f - 80ec: 7f80 flw fs0,56(a5) - 80ee: 1a06 slli s4,s4,0x21 - 80f0: 7a1e007b 0x7a1e007b - 80f4: 1a7f 0x1a7f - 80f6: 8091 srli s1,s1,0x4 - 80f8: 067f 0x67f - 80fa: 2540 fld fs0,136(a0) - 80fc: 7a1e007b 0x7a1e007b - 8100: 917f 0x917f - 8102: 7f80 flw fs0,56(a5) - 8104: 1a06 slli s4,s4,0x21 - 8106: 0082 c.slli64 ra - 8108: 221e fld ft4,448(sp) - 810a: 7f7a flw ft10,188(sp) - 810c: 8091 srli s1,s1,0x4 - 810e: 067f 0x67f - 8110: 7b1a flw fs6,164(sp) - 8112: 1e00 addi s0,sp,816 - 8114: 2540 fld fs0,136(a0) - 8116: 7a22 flw fs4,40(sp) - 8118: 1a7f 0x1a7f - 811a: 2440 fld fs0,136(s0) - 811c: 4022 0x4022 - 811e: 2d22244b 0x2d22244b - 8122: e49f 0008 e800 0xe8000008e49f - 8128: 0008 0x8 - 812a: 4700 lw s0,8(a4) - 812c: 9100 0x9100 - 812e: 7fa4 flw fs1,120(a5) - 8130: 4006 0x4006 - 8132: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - 8136: 7f80 flw fs0,56(a5) - 8138: 0a06 slli s4,s4,0x1 - 813a: ffff 0xffff - 813c: 7b1a flw fs6,164(sp) - 813e: 1e00 addi s0,sp,816 - 8140: ff0a fsw ft2,188(sp) - 8142: 1aff 0x1aff - 8144: 8091 srli s1,s1,0x4 - 8146: 067f 0x67f - 8148: 2540 fld fs0,136(a0) - 814a: 911e007b 0x911e007b - 814e: 7f80 flw fs0,56(a5) - 8150: 0a06 slli s4,s4,0x1 - 8152: ffff 0xffff - 8154: 821a mv tp,t1 - 8156: 1e00 addi s0,sp,816 - 8158: 9122 add sp,sp,s0 - 815a: 7f80 flw fs0,56(a5) - 815c: 0a06 slli s4,s4,0x1 - 815e: ffff 0xffff - 8160: 7b1a flw fs6,164(sp) - 8162: 1e00 addi s0,sp,816 - 8164: 2540 fld fs0,136(a0) - 8166: 0a22 slli s4,s4,0x8 - 8168: ffff 0xffff - 816a: 401a 0x401a - 816c: 2224 fld fs1,64(a2) - 816e: 4b40 lw s0,20(a4) - 8170: 2224 fld fs1,64(a2) - 8172: 9f2d 0x9f2d - 8174: 08e8 addi a0,sp,92 - 8176: 0000 unimp - 8178: 0910 addi a2,sp,144 - 817a: 0000 unimp - 817c: 0042 c.slli zero,0x10 - 817e: a491 j 83c2 <_start-0x7fff7c3e> - 8180: 067f 0x67f - 8182: 4b40 lw s0,20(a4) - 8184: 2224 fld fs1,64(a2) - 8186: 7f84 flw fs1,56(a5) - 8188: 8091 srli s1,s1,0x4 - 818a: 067f 0x67f - 818c: 7b1a flw fs6,164(sp) - 818e: 1e00 addi s0,sp,816 - 8190: 7f84 flw fs1,56(a5) - 8192: 911a add sp,sp,t1 - 8194: 7f80 flw fs0,56(a5) - 8196: 4006 0x4006 - 8198: 7b25 lui s6,0xfffe9 - 819a: 1e00 addi s0,sp,816 - 819c: 7f84 flw fs1,56(a5) - 819e: 8091 srli s1,s1,0x4 - 81a0: 067f 0x67f - 81a2: 821a mv tp,t1 - 81a4: 1e00 addi s0,sp,816 - 81a6: 8422 mv s0,s0 - 81a8: 917f 0x917f - 81aa: 7f80 flw fs0,56(a5) - 81ac: 1a06 slli s4,s4,0x21 - 81ae: 401e007b 0x401e007b - 81b2: 2225 jal 82da <_start-0x7fff7d26> - 81b4: 7f84 flw fs1,56(a5) - 81b6: 401a 0x401a - 81b8: 2224 fld fs1,64(a2) - 81ba: 4b40 lw s0,20(a4) - 81bc: 2224 fld fs1,64(a2) - 81be: 9f2d 0x9f2d - 81c0: 0910 addi a2,sp,144 - 81c2: 0000 unimp - 81c4: 0920 addi s0,sp,152 - 81c6: 0000 unimp - 81c8: 0051 c.nop 20 - 81ca: a491 j 840e <_start-0x7fff7bf2> - 81cc: 067f 0x67f - 81ce: 4b40 lw s0,20(a4) - 81d0: 2224 fld fs1,64(a2) - 81d2: 7f84 flw fs1,56(a5) - 81d4: 8091 srli s1,s1,0x4 - 81d6: 067f 0x67f - 81d8: 841a mv s0,t1 - 81da: 917f 0x917f - 81dc: 7ef4 flw fa3,124(a3) - 81de: 1a06 slli s4,s4,0x21 - 81e0: 841e mv s0,t2 - 81e2: 1a7f 0x1a7f - 81e4: 7f84 flw fs1,56(a5) - 81e6: f491 bnez s1,80f2 <_start-0x7fff7f0e> - 81e8: 067e slli a2,a2,0x1f - 81ea: 911a add sp,sp,t1 - 81ec: 7f80 flw fs0,56(a5) - 81ee: 4006 0x4006 - 81f0: 1e25 addi t3,t3,-23 - 81f2: 7f84 flw fs1,56(a5) - 81f4: 8091 srli s1,s1,0x4 - 81f6: 067f 0x67f - 81f8: 821a mv tp,t1 - 81fa: 1e00 addi s0,sp,816 - 81fc: 8422 mv s0,s0 - 81fe: 917f 0x917f - 8200: 7f80 flw fs0,56(a5) - 8202: 1a06 slli s4,s4,0x21 - 8204: 7f84 flw fs1,56(a5) - 8206: f491 bnez s1,8112 <_start-0x7fff7eee> - 8208: 067e slli a2,a2,0x1f - 820a: 1e1a slli t3,t3,0x26 - 820c: 2540 fld fs0,136(a0) - 820e: 8422 mv s0,s0 - 8210: 1a7f 0x1a7f - 8212: 2440 fld fs0,136(s0) - 8214: 4022 0x4022 - 8216: 2d22244b 0x2d22244b - 821a: 209f 0009 3400 0x34000009209f - 8220: 0009 c.nop 2 - 8222: 5500 lw s0,40(a0) - 8224: 9100 0x9100 - 8226: 7fa4 flw fs1,120(a5) - 8228: 4006 0x4006 - 822a: 8422244b 0x8422244b - 822e: 917f 0x917f - 8230: 7f80 flw fs0,56(a5) - 8232: 1a06 slli s4,s4,0x21 - 8234: 7f84 flw fs1,56(a5) - 8236: f491 bnez s1,8142 <_start-0x7fff7ebe> - 8238: 067e slli a2,a2,0x1f - 823a: 1e1a slli t3,t3,0x26 - 823c: 7f84 flw fs1,56(a5) - 823e: 841a mv s0,t1 - 8240: 917f 0x917f - 8242: 7ef4 flw fa3,124(a3) - 8244: 1a06 slli s4,s4,0x21 - 8246: 8091 srli s1,s1,0x4 - 8248: 067f 0x67f - 824a: 2540 fld fs0,136(a0) - 824c: 841e mv s0,t2 - 824e: 917f 0x917f - 8250: 7f80 flw fs0,56(a5) - 8252: 1a06 slli s4,s4,0x21 - 8254: f491 bnez s1,8160 <_start-0x7fff7ea0> - 8256: 067e slli a2,a2,0x1f - 8258: 2540 fld fs0,136(a0) - 825a: 221e fld ft4,448(sp) - 825c: 7f84 flw fs1,56(a5) - 825e: 8091 srli s1,s1,0x4 - 8260: 067f 0x67f - 8262: 841a mv s0,t1 - 8264: 917f 0x917f - 8266: 7ef4 flw fa3,124(a3) - 8268: 1a06 slli s4,s4,0x21 - 826a: 401e 0x401e - 826c: 2225 jal 8394 <_start-0x7fff7c6c> - 826e: 7f84 flw fs1,56(a5) - 8270: 401a 0x401a - 8272: 2224 fld fs1,64(a2) - 8274: 4b40 lw s0,20(a4) - 8276: 2224 fld fs1,64(a2) - 8278: 9f2d 0x9f2d - 827a: 0934 addi a3,sp,152 - 827c: 0000 unimp - 827e: 0958 addi a4,sp,148 - 8280: 0000 unimp - 8282: 0055 c.nop 21 - 8284: a491 j 84c8 <_start-0x7fff7b38> - 8286: 067f 0x67f - 8288: 4b40 lw s0,20(a4) - 828a: 2224 fld fs1,64(a2) - 828c: 8091 srli s1,s1,0x4 - 828e: 067f 0x67f - 8290: 0084 addi s1,sp,64 - 8292: 911a add sp,sp,t1 - 8294: 7ef4 flw fa3,124(a3) - 8296: 8406 mv s0,ra - 8298: 1a00 addi s0,sp,304 - 829a: 841e mv s0,t2 - 829c: 1a00 addi s0,sp,304 - 829e: f491 bnez s1,81aa <_start-0x7fff7e56> - 82a0: 067e slli a2,a2,0x1f - 82a2: 0084 addi s1,sp,64 - 82a4: 911a add sp,sp,t1 - 82a6: 7f80 flw fs0,56(a5) - 82a8: 4006 0x4006 - 82aa: 1e25 addi t3,t3,-23 - 82ac: 8091 srli s1,s1,0x4 - 82ae: 067f 0x67f - 82b0: 0084 addi s1,sp,64 - 82b2: 911a add sp,sp,t1 - 82b4: 7ef4 flw fa3,124(a3) - 82b6: 4006 0x4006 - 82b8: 1e25 addi t3,t3,-23 - 82ba: 9122 add sp,sp,s0 - 82bc: 7f80 flw fs0,56(a5) - 82be: 8406 mv s0,ra - 82c0: 1a00 addi s0,sp,304 - 82c2: f491 bnez s1,81ce <_start-0x7fff7e32> - 82c4: 067e slli a2,a2,0x1f - 82c6: 0084 addi s1,sp,64 - 82c8: 1e1a slli t3,t3,0x26 - 82ca: 2540 fld fs0,136(a0) - 82cc: 8422 mv s0,s0 - 82ce: 1a00 addi s0,sp,304 - 82d0: 2440 fld fs0,136(s0) - 82d2: 4022 0x4022 - 82d4: 2d22244b 0x2d22244b - 82d8: 589f 0009 e000 0xe0000009589f - 82de: 0009 c.nop 2 - 82e0: 5500 lw s0,40(a0) - 82e2: 9100 0x9100 - 82e4: 7fa4 flw fs1,120(a5) - 82e6: 4006 0x4006 - 82e8: 8522244b 0x8522244b - 82ec: 917f 0x917f - 82ee: 7f80 flw fs0,56(a5) - 82f0: 1a06 slli s4,s4,0x21 - 82f2: 7f85 lui t6,0xfffe1 - 82f4: f491 bnez s1,8200 <_start-0x7fff7e00> - 82f6: 067e slli a2,a2,0x1f - 82f8: 1e1a slli t3,t3,0x26 - 82fa: 7f85 lui t6,0xfffe1 - 82fc: 851a mv a0,t1 - 82fe: 917f 0x917f - 8300: 7ef4 flw fa3,124(a3) - 8302: 1a06 slli s4,s4,0x21 - 8304: 8091 srli s1,s1,0x4 - 8306: 067f 0x67f - 8308: 2540 fld fs0,136(a0) - 830a: 851e mv a0,t2 - 830c: 917f 0x917f - 830e: 7f80 flw fs0,56(a5) - 8310: 1a06 slli s4,s4,0x21 - 8312: f491 bnez s1,821e <_start-0x7fff7de2> - 8314: 067e slli a2,a2,0x1f - 8316: 2540 fld fs0,136(a0) - 8318: 221e fld ft4,448(sp) - 831a: 7f85 lui t6,0xfffe1 - 831c: 8091 srli s1,s1,0x4 - 831e: 067f 0x67f - 8320: 851a mv a0,t1 - 8322: 917f 0x917f - 8324: 7ef4 flw fa3,124(a3) - 8326: 1a06 slli s4,s4,0x21 - 8328: 401e 0x401e - 832a: 2225 jal 8452 <_start-0x7fff7bae> - 832c: 7f85 lui t6,0xfffe1 - 832e: 401a 0x401a - 8330: 2224 fld fs1,64(a2) - 8332: 4b40 lw s0,20(a4) - 8334: 2224 fld fs1,64(a2) - 8336: 9f2d 0x9f2d - 8338: 09e0 addi s0,sp,220 - 833a: 0000 unimp - 833c: 09ec addi a1,sp,220 - 833e: 0000 unimp - 8340: 0055 c.nop 21 - 8342: a491 j 8586 <_start-0x7fff7a7a> - 8344: 067f 0x67f - 8346: 4b40 lw s0,20(a4) - 8348: 2224 fld fs1,64(a2) - 834a: 8091 srli s1,s1,0x4 - 834c: 067f 0x67f - 834e: 0079 c.nop 30 - 8350: 911a add sp,sp,t1 - 8352: 7ef4 flw fa3,124(a3) - 8354: 7906 flw fs2,96(sp) - 8356: 1a00 addi s0,sp,304 - 8358: 791e flw fs2,228(sp) - 835a: 1a00 addi s0,sp,304 - 835c: f491 bnez s1,8268 <_start-0x7fff7d98> - 835e: 067e slli a2,a2,0x1f - 8360: 0079 c.nop 30 - 8362: 911a add sp,sp,t1 - 8364: 7f80 flw fs0,56(a5) - 8366: 4006 0x4006 - 8368: 1e25 addi t3,t3,-23 - 836a: 8091 srli s1,s1,0x4 - 836c: 067f 0x67f - 836e: 0079 c.nop 30 - 8370: 911a add sp,sp,t1 - 8372: 7ef4 flw fa3,124(a3) - 8374: 4006 0x4006 - 8376: 1e25 addi t3,t3,-23 - 8378: 9122 add sp,sp,s0 - 837a: 7f80 flw fs0,56(a5) - 837c: 7906 flw fs2,96(sp) - 837e: 1a00 addi s0,sp,304 - 8380: f491 bnez s1,828c <_start-0x7fff7d74> - 8382: 067e slli a2,a2,0x1f - 8384: 0079 c.nop 30 - 8386: 1e1a slli t3,t3,0x26 - 8388: 2540 fld fs0,136(a0) - 838a: 7922 flw fs2,40(sp) - 838c: 1a00 addi s0,sp,304 - 838e: 2440 fld fs0,136(s0) - 8390: 4022 0x4022 - 8392: 2d22244b 0x2d22244b - 8396: ec9f 0009 4800 0x48000009ec9f - 839c: 000a c.slli zero,0x2 - 839e: 5500 lw s0,40(a0) - 83a0: 9100 0x9100 - 83a2: 7fa4 flw fs1,120(a5) - 83a4: 4006 0x4006 - 83a6: 8422244b 0x8422244b - 83aa: 917f 0x917f - 83ac: 7f80 flw fs0,56(a5) - 83ae: 1a06 slli s4,s4,0x21 - 83b0: 7f84 flw fs1,56(a5) - 83b2: f491 bnez s1,82be <_start-0x7fff7d42> - 83b4: 067e slli a2,a2,0x1f - 83b6: 1e1a slli t3,t3,0x26 - 83b8: 7f84 flw fs1,56(a5) - 83ba: 841a mv s0,t1 - 83bc: 917f 0x917f - 83be: 7ef4 flw fa3,124(a3) - 83c0: 1a06 slli s4,s4,0x21 - 83c2: 8091 srli s1,s1,0x4 - 83c4: 067f 0x67f - 83c6: 2540 fld fs0,136(a0) - 83c8: 841e mv s0,t2 - 83ca: 917f 0x917f - 83cc: 7f80 flw fs0,56(a5) - 83ce: 1a06 slli s4,s4,0x21 - 83d0: f491 bnez s1,82dc <_start-0x7fff7d24> - 83d2: 067e slli a2,a2,0x1f - 83d4: 2540 fld fs0,136(a0) - 83d6: 221e fld ft4,448(sp) - 83d8: 7f84 flw fs1,56(a5) - 83da: 8091 srli s1,s1,0x4 - 83dc: 067f 0x67f - 83de: 841a mv s0,t1 - 83e0: 917f 0x917f - 83e2: 7ef4 flw fa3,124(a3) - 83e4: 1a06 slli s4,s4,0x21 - 83e6: 401e 0x401e - 83e8: 2225 jal 8510 <_start-0x7fff7af0> - 83ea: 7f84 flw fs1,56(a5) - 83ec: 401a 0x401a - 83ee: 2224 fld fs1,64(a2) - 83f0: 4b40 lw s0,20(a4) - 83f2: 2224 fld fs1,64(a2) - 83f4: 9f2d 0x9f2d - 83f6: 0a48 addi a0,sp,276 - 83f8: 0000 unimp - 83fa: 0ae0 addi s0,sp,348 - 83fc: 0000 unimp - 83fe: 0055 c.nop 21 - 8400: a491 j 8644 <_start-0x7fff79bc> - 8402: 067f 0x67f - 8404: 4b40 lw s0,20(a4) - 8406: 2224 fld fs1,64(a2) - 8408: 8091 srli s1,s1,0x4 - 840a: 067f 0x67f - 840c: 0079 c.nop 30 - 840e: 911a add sp,sp,t1 - 8410: 7ef4 flw fa3,124(a3) - 8412: 7906 flw fs2,96(sp) - 8414: 1a00 addi s0,sp,304 - 8416: 791e flw fs2,228(sp) - 8418: 1a00 addi s0,sp,304 - 841a: f491 bnez s1,8326 <_start-0x7fff7cda> - 841c: 067e slli a2,a2,0x1f - 841e: 0079 c.nop 30 - 8420: 911a add sp,sp,t1 - 8422: 7f80 flw fs0,56(a5) - 8424: 4006 0x4006 - 8426: 1e25 addi t3,t3,-23 - 8428: 8091 srli s1,s1,0x4 - 842a: 067f 0x67f - 842c: 0079 c.nop 30 - 842e: 911a add sp,sp,t1 - 8430: 7ef4 flw fa3,124(a3) - 8432: 4006 0x4006 - 8434: 1e25 addi t3,t3,-23 - 8436: 9122 add sp,sp,s0 - 8438: 7f80 flw fs0,56(a5) - 843a: 7906 flw fs2,96(sp) - 843c: 1a00 addi s0,sp,304 - 843e: f491 bnez s1,834a <_start-0x7fff7cb6> - 8440: 067e slli a2,a2,0x1f - 8442: 0079 c.nop 30 - 8444: 1e1a slli t3,t3,0x26 - 8446: 2540 fld fs0,136(a0) - 8448: 7922 flw fs2,40(sp) - 844a: 1a00 addi s0,sp,304 - 844c: 2440 fld fs0,136(s0) - 844e: 4022 0x4022 - 8450: 2d22244b 0x2d22244b - 8454: e09f 000a 2c00 0x2c00000ae09f - 845a: 5500000b 0x5500000b - 845e: 9100 0x9100 - 8460: 7fa4 flw fs1,120(a5) - 8462: 4006 0x4006 - 8464: 8922244b fnmsub.s fs0,ft4,fs2,fa7,rdn - 8468: 917f 0x917f - 846a: 7f80 flw fs0,56(a5) - 846c: 1a06 slli s4,s4,0x21 - 846e: 7f89 lui t6,0xfffe2 - 8470: f491 bnez s1,837c <_start-0x7fff7c84> - 8472: 067e slli a2,a2,0x1f - 8474: 1e1a slli t3,t3,0x26 - 8476: 7f89 lui t6,0xfffe2 - 8478: 891a mv s2,t1 - 847a: 917f 0x917f - 847c: 7ef4 flw fa3,124(a3) - 847e: 1a06 slli s4,s4,0x21 - 8480: 8091 srli s1,s1,0x4 - 8482: 067f 0x67f - 8484: 2540 fld fs0,136(a0) - 8486: 891e mv s2,t2 - 8488: 917f 0x917f - 848a: 7f80 flw fs0,56(a5) - 848c: 1a06 slli s4,s4,0x21 - 848e: f491 bnez s1,839a <_start-0x7fff7c66> - 8490: 067e slli a2,a2,0x1f - 8492: 2540 fld fs0,136(a0) - 8494: 221e fld ft4,448(sp) - 8496: 7f89 lui t6,0xfffe2 - 8498: 8091 srli s1,s1,0x4 - 849a: 067f 0x67f - 849c: 891a mv s2,t1 - 849e: 917f 0x917f - 84a0: 7ef4 flw fa3,124(a3) - 84a2: 1a06 slli s4,s4,0x21 - 84a4: 401e 0x401e - 84a6: 2225 jal 85ce <_start-0x7fff7a32> - 84a8: 7f89 lui t6,0xfffe2 - 84aa: 401a 0x401a - 84ac: 2224 fld fs1,64(a2) - 84ae: 4b40 lw s0,20(a4) - 84b0: 2224 fld fs1,64(a2) - 84b2: 9f2d 0x9f2d - 84b4: 0b2c addi a1,sp,408 - 84b6: 0000 unimp - 84b8: 0bc4 addi s1,sp,468 - 84ba: 0000 unimp - 84bc: 0055 c.nop 21 - 84be: d491 beqz s1,83ca <_start-0x7fff7c36> - 84c0: 067e slli a2,a2,0x1f - 84c2: 4b40 lw s0,20(a4) - 84c4: 2224 fld fs1,64(a2) - 84c6: 7f89 lui t6,0xfffe2 - 84c8: 8091 srli s1,s1,0x4 - 84ca: 067f 0x67f - 84cc: 891a mv s2,t1 - 84ce: 917f 0x917f - 84d0: 7ef4 flw fa3,124(a3) - 84d2: 1a06 slli s4,s4,0x21 - 84d4: 891e mv s2,t2 - 84d6: 1a7f 0x1a7f - 84d8: 7f89 lui t6,0xfffe2 - 84da: f491 bnez s1,83e6 <_start-0x7fff7c1a> - 84dc: 067e slli a2,a2,0x1f - 84de: 911a add sp,sp,t1 - 84e0: 7f80 flw fs0,56(a5) - 84e2: 4006 0x4006 - 84e4: 1e25 addi t3,t3,-23 - 84e6: 7f89 lui t6,0xfffe2 - 84e8: 8091 srli s1,s1,0x4 - 84ea: 067f 0x67f - 84ec: 911a add sp,sp,t1 - 84ee: 7ef4 flw fa3,124(a3) - 84f0: 4006 0x4006 - 84f2: 1e25 addi t3,t3,-23 - 84f4: 8922 mv s2,s0 - 84f6: 917f 0x917f - 84f8: 7f80 flw fs0,56(a5) - 84fa: 1a06 slli s4,s4,0x21 - 84fc: 7f89 lui t6,0xfffe2 - 84fe: f491 bnez s1,840a <_start-0x7fff7bf6> - 8500: 067e slli a2,a2,0x1f - 8502: 1e1a slli t3,t3,0x26 - 8504: 2540 fld fs0,136(a0) - 8506: 8922 mv s2,s0 - 8508: 1a7f 0x1a7f - 850a: 2440 fld fs0,136(s0) - 850c: 4022 0x4022 - 850e: 2d22244b 0x2d22244b - 8512: a89f 000d b400 0xb400000da89f - 8518: 000d c.nop 3 - 851a: 5500 lw s0,40(a0) - 851c: 9100 0x9100 - 851e: 7ed4 flw fa3,60(a3) - 8520: 4006 0x4006 - 8522: 8922244b fnmsub.s fs0,ft4,fs2,fa7,rdn - 8526: 917f 0x917f - 8528: 7f80 flw fs0,56(a5) - 852a: 1a06 slli s4,s4,0x21 - 852c: 7f89 lui t6,0xfffe2 - 852e: f491 bnez s1,843a <_start-0x7fff7bc6> - 8530: 067e slli a2,a2,0x1f - 8532: 1e1a slli t3,t3,0x26 - 8534: 7f89 lui t6,0xfffe2 - 8536: 891a mv s2,t1 - 8538: 917f 0x917f - 853a: 7ef4 flw fa3,124(a3) - 853c: 1a06 slli s4,s4,0x21 - 853e: 8091 srli s1,s1,0x4 - 8540: 067f 0x67f - 8542: 2540 fld fs0,136(a0) - 8544: 891e mv s2,t2 - 8546: 917f 0x917f - 8548: 7f80 flw fs0,56(a5) - 854a: 1a06 slli s4,s4,0x21 - 854c: f491 bnez s1,8458 <_start-0x7fff7ba8> - 854e: 067e slli a2,a2,0x1f - 8550: 2540 fld fs0,136(a0) - 8552: 221e fld ft4,448(sp) - 8554: 7f89 lui t6,0xfffe2 - 8556: 8091 srli s1,s1,0x4 - 8558: 067f 0x67f - 855a: 891a mv s2,t1 - 855c: 917f 0x917f - 855e: 7ef4 flw fa3,124(a3) - 8560: 1a06 slli s4,s4,0x21 - 8562: 401e 0x401e - 8564: 2225 jal 868c <_start-0x7fff7974> - 8566: 7f89 lui t6,0xfffe2 - 8568: 401a 0x401a - 856a: 2224 fld fs1,64(a2) - 856c: 4b40 lw s0,20(a4) - 856e: 2224 fld fs1,64(a2) - 8570: 9f2d 0x9f2d - ... - 857a: 066c addi a1,sp,780 - 857c: 0000 unimp - 857e: 0670 addi a2,sp,780 - 8580: 0000 unimp - 8582: 0011 c.nop 4 - 8584: 0076 c.slli zero,0x1d - 8586: 4b40 lw s0,20(a4) - 8588: 2224 fld fs1,64(a2) - 858a: 4b400083 lb ra,1204(zero) # 4b4 <_start-0x7ffffb4c> - 858e: 2224 fld fs1,64(a2) - 8590: 082d addi a6,a6,11 - 8592: 1aff 0x1aff - 8594: 709f 0006 7400 0x74000006709f - 859a: 0006 c.slli zero,0x1 - 859c: 1f00 addi s0,sp,944 - 859e: 7600 flw fs0,40(a2) - 85a0: 4000 lw s0,0(s0) - 85a2: 8322244b fnmsub.d fs0,ft4,fs2,fa6,rdn - 85a6: 4000 lw s0,0(s0) - 85a8: 2d22244b 0x2d22244b - 85ac: 0086 slli ra,ra,0x1 - 85ae: 4b40 lw s0,20(a4) - 85b0: 2224 fld fs1,64(a2) - 85b2: 0080 addi s0,sp,64 - 85b4: 4b40 lw s0,20(a4) - 85b6: 2224 fld fs1,64(a2) - 85b8: 212d jal 89e2 <_start-0x7fff761e> - 85ba: ff08 fsw fa0,56(a4) - 85bc: 9f1a add t5,t5,t1 - ... - 85c6: 0694 addi a3,sp,832 - 85c8: 0000 unimp - 85ca: 06ac addi a1,sp,840 - 85cc: 0000 unimp - 85ce: 0001 nop - 85d0: ac5d j 8886 <_start-0x7fff777a> - 85d2: 0006 c.slli zero,0x1 - 85d4: 5800 lw s0,48(s0) - 85d6: 4f000007 vlxseg3bu.v v0,(zero),v16 - 85da: 7b00 flw fs0,48(a4) - 85dc: 8e00 0x8e00 - 85de: 1e00 addi s0,sp,816 - 85e0: 0089 addi ra,ra,2 - 85e2: 791a flw fs2,164(sp) - 85e4: 7b00 flw fs0,48(a4) - 85e6: 1e00 addi s0,sp,816 - 85e8: 0082 c.slli64 ra - 85ea: 008e slli ra,ra,0x3 - 85ec: 221e fld ft4,448(sp) - 85ee: 008e007b 0x8e007b - 85f2: 401e 0x401e - 85f4: 2225 jal 871c <_start-0x7fff78e4> - 85f6: 0089 addi ra,ra,2 - 85f8: 401a 0x401a - 85fa: 2224 fld fs1,64(a2) - 85fc: 0086 slli ra,ra,0x1 - 85fe: 4022 0x4022 - 8600: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - 8604: 8e00 0x8e00 - 8606: 1e00 addi s0,sp,816 - 8608: 0089 addi ra,ra,2 - 860a: 791a flw fs2,164(sp) - 860c: 7b00 flw fs0,48(a4) - 860e: 1e00 addi s0,sp,816 - 8610: 0082 c.slli64 ra - 8612: 008e slli ra,ra,0x3 - 8614: 221e fld ft4,448(sp) - 8616: 008e007b 0x8e007b - 861a: 401e 0x401e - 861c: 2225 jal 8744 <_start-0x7fff78bc> - 861e: 0089 addi ra,ra,2 - 8620: 401a 0x401a - 8622: 2224 fld fs1,64(a2) - 8624: 4b40 lw s0,20(a4) - 8626: 2224 fld fs1,64(a2) - 8628: 9f2d 0x9f2d - ... - 8632: 0698 addi a4,sp,832 - 8634: 0000 unimp - 8636: 06a0 addi s0,sp,840 - 8638: 0000 unimp - 863a: 0011 c.nop 4 - 863c: 007a c.slli zero,0x1e - 863e: 4b40 lw s0,20(a4) - 8640: 2224 fld fs1,64(a2) - 8642: 0080 addi s0,sp,64 - 8644: 4b40 lw s0,20(a4) - 8646: 2224 fld fs1,64(a2) - 8648: 082d addi a6,a6,11 - 864a: 1aff 0x1aff - 864c: a09f 0006 a800 0xa8000006a09f - 8652: 0006 c.slli zero,0x1 - 8654: 1f00 addi s0,sp,944 - 8656: 7a00 flw fs0,48(a2) - 8658: 4000 lw s0,0(s0) - 865a: 8322244b fnmsub.d fs0,ft4,fs2,fa6,rdn - 865e: 4000 lw s0,0(s0) - 8660: 2d22244b 0x2d22244b - 8664: 0080 addi s0,sp,64 - 8666: 4b40 lw s0,20(a4) - 8668: 2224 fld fs1,64(a2) - 866a: 007d c.nop 31 - 866c: 4b40 lw s0,20(a4) - 866e: 2224 fld fs1,64(a2) - 8670: 212d jal 8a9a <_start-0x7fff7566> - 8672: ff08 fsw fa0,56(a4) - 8674: 9f1a add t5,t5,t1 - ... - 867e: 06b0 addi a2,sp,840 - 8680: 0000 unimp - 8682: 06cc addi a1,sp,836 - 8684: 0000 unimp - 8686: 0001 nop - 8688: cc5f 0006 0c00 0xc000006cc5f - 868e: 71000007 vlseg4bff.v v0,(zero),v0.t - 8692: 7b00 flw fs0,48(a4) - 8694: 8e00 0x8e00 - 8696: 1e00 addi s0,sp,816 - 8698: 0089 addi ra,ra,2 - 869a: 8d1a mv s10,t1 - 869c: 7e00 flw fs0,56(a2) - 869e: 1e00 addi s0,sp,816 - 86a0: 0089 addi ra,ra,2 - 86a2: 221a fld ft4,384(sp) - 86a4: 0078 addi a4,sp,12 - 86a6: 007e c.slli zero,0x1f - 86a8: 8f1e mv t5,t2 - 86aa: 8d00 0x8d00 - 86ac: 1e00 addi s0,sp,816 - 86ae: 8d22 mv s10,s0 - 86b0: 7e00 flw fs0,56(a2) - 86b2: 1e00 addi s0,sp,816 - 86b4: 2540 fld fs0,136(a0) - 86b6: 8922 mv s2,s0 - 86b8: 1a00 addi s0,sp,304 - 86ba: 2440 fld fs0,136(s0) - 86bc: 7922 flw fs2,40(sp) - 86be: 7b00 flw fs0,48(a4) - 86c0: 1e00 addi s0,sp,816 - 86c2: 0082 c.slli64 ra - 86c4: 008e slli ra,ra,0x3 - 86c6: 221e fld ft4,448(sp) - 86c8: 008e007b 0x8e007b - 86cc: 401e 0x401e - 86ce: 2225 jal 87f6 <_start-0x7fff780a> - 86d0: 0089 addi ra,ra,2 - 86d2: 401a 0x401a - 86d4: 2224 fld fs1,64(a2) - 86d6: 0086 slli ra,ra,0x1 - 86d8: 4022 0x4022 - 86da: 8d22244b 0x8d22244b - 86de: 7e00 flw fs0,56(a2) - 86e0: 1e00 addi s0,sp,816 - 86e2: 0089 addi ra,ra,2 - 86e4: 781a flw fa6,164(sp) - 86e6: 7e00 flw fs0,56(a2) - 86e8: 1e00 addi s0,sp,816 - 86ea: 008d008f 0x8d008f - 86ee: 221e fld ft4,448(sp) - 86f0: 008d addi ra,ra,3 - 86f2: 007e c.slli zero,0x1f - 86f4: 401e 0x401e - 86f6: 2225 jal 881e <_start-0x7fff77e2> - 86f8: 0089 addi ra,ra,2 - 86fa: 401a 0x401a - 86fc: 2224 fld fs1,64(a2) - 86fe: 4b40 lw s0,20(a4) - 8700: 2224 fld fs1,64(a2) - 8702: 9f2d 0x9f2d - 8704: 070c addi a1,sp,896 - 8706: 0000 unimp - 8708: 0720 addi s0,sp,904 - 870a: 0000 unimp - 870c: 007b008f 0x7b008f - 8710: 008e slli ra,ra,0x3 - 8712: 891e mv s2,t2 - 8714: 1a00 addi s0,sp,304 - 8716: f091 bnez s1,861a <_start-0x7fff79e6> - 8718: 067e slli a2,a2,0x1f - 871a: 0089 addi ra,ra,2 - 871c: 8d1a mv s10,t1 - 871e: 1e00 addi s0,sp,816 - 8720: 0089 addi ra,ra,2 - 8722: 221a fld ft4,384(sp) - 8724: f091 bnez s1,8628 <_start-0x7fff79d8> - 8726: 067e slli a2,a2,0x1f - 8728: 0089 addi ra,ra,2 - 872a: 781a flw fa6,164(sp) - 872c: 1e00 addi s0,sp,816 - 872e: 008d008f 0x8d008f - 8732: 221e fld ft4,448(sp) - 8734: f091 bnez s1,8638 <_start-0x7fff79c8> - 8736: 067e slli a2,a2,0x1f - 8738: 0089 addi ra,ra,2 - 873a: 8d1a mv s10,t1 - 873c: 1e00 addi s0,sp,816 - 873e: 2540 fld fs0,136(a0) - 8740: 8922 mv s2,s0 - 8742: 1a00 addi s0,sp,304 - 8744: 2440 fld fs0,136(s0) - 8746: 7922 flw fs2,40(sp) - 8748: 7b00 flw fs0,48(a4) - 874a: 1e00 addi s0,sp,816 - 874c: 0082 c.slli64 ra - 874e: 008e slli ra,ra,0x3 - 8750: 221e fld ft4,448(sp) - 8752: 008e007b 0x8e007b - 8756: 401e 0x401e - 8758: 2225 jal 8880 <_start-0x7fff7780> - 875a: 0089 addi ra,ra,2 - 875c: 401a 0x401a - 875e: 2224 fld fs1,64(a2) - 8760: 0086 slli ra,ra,0x1 - 8762: 4022 0x4022 - 8764: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - 8768: 7ef0 flw fa2,124(a3) - 876a: 8906 mv s2,ra - 876c: 1a00 addi s0,sp,304 - 876e: 008d addi ra,ra,3 - 8770: 891e mv s2,t2 - 8772: 1a00 addi s0,sp,304 - 8774: f091 bnez s1,8678 <_start-0x7fff7988> - 8776: 067e slli a2,a2,0x1f - 8778: 0089 addi ra,ra,2 - 877a: 781a flw fa6,164(sp) - 877c: 1e00 addi s0,sp,816 - 877e: 008d008f 0x8d008f - 8782: 221e fld ft4,448(sp) - 8784: f091 bnez s1,8688 <_start-0x7fff7978> - 8786: 067e slli a2,a2,0x1f - 8788: 0089 addi ra,ra,2 - 878a: 8d1a mv s10,t1 - 878c: 1e00 addi s0,sp,816 - 878e: 2540 fld fs0,136(a0) - 8790: 8922 mv s2,s0 - 8792: 1a00 addi s0,sp,304 - 8794: 2440 fld fs0,136(s0) - 8796: 4022 0x4022 - 8798: 2d22244b 0x2d22244b - 879c: 209f 0007 5800 0x58000007209f - 87a2: 97000007 0x97000007 - 87a6: 7b00 flw fs0,48(a4) - 87a8: 8e00 0x8e00 - 87aa: 1e00 addi s0,sp,816 - 87ac: 0089 addi ra,ra,2 - 87ae: 911a add sp,sp,t1 - 87b0: 7ef0 flw fa2,124(a3) - 87b2: 8906 mv s2,ra - 87b4: 1a00 addi s0,sp,304 - 87b6: 008d addi ra,ra,3 - 87b8: 891e mv s2,t2 - 87ba: 1a00 addi s0,sp,304 - 87bc: 9122 add sp,sp,s0 - 87be: 7ef0 flw fa2,124(a3) - 87c0: 8906 mv s2,ra - 87c2: 1a00 addi s0,sp,304 - 87c4: 0078 addi a4,sp,12 - 87c6: 911e add sp,sp,t2 - 87c8: 7ef0 flw fa2,124(a3) - 87ca: 4006 0x4006 - 87cc: 8d25 xor a0,a0,s1 - 87ce: 1e00 addi s0,sp,816 - 87d0: 9122 add sp,sp,s0 - 87d2: 7ef0 flw fa2,124(a3) - 87d4: 8906 mv s2,ra - 87d6: 1a00 addi s0,sp,304 - 87d8: 008d addi ra,ra,3 - 87da: 401e 0x401e - 87dc: 2225 jal 8904 <_start-0x7fff76fc> - 87de: 0089 addi ra,ra,2 - 87e0: 401a 0x401a - 87e2: 2224 fld fs1,64(a2) - 87e4: 0079 c.nop 30 - 87e6: 821e007b 0x821e007b - 87ea: 8e00 0x8e00 - 87ec: 1e00 addi s0,sp,816 - 87ee: 7b22 flw fs6,40(sp) - 87f0: 8e00 0x8e00 - 87f2: 1e00 addi s0,sp,816 - 87f4: 2540 fld fs0,136(a0) - 87f6: 8922 mv s2,s0 - 87f8: 1a00 addi s0,sp,304 - 87fa: 2440 fld fs0,136(s0) - 87fc: 8622 mv a2,s0 - 87fe: 2200 fld fs0,0(a2) - 8800: 4b40 lw s0,20(a4) - 8802: 2224 fld fs1,64(a2) - 8804: f091 bnez s1,8708 <_start-0x7fff78f8> - 8806: 067e slli a2,a2,0x1f - 8808: 0089 addi ra,ra,2 - 880a: 8d1a mv s10,t1 - 880c: 1e00 addi s0,sp,816 - 880e: 0089 addi ra,ra,2 - 8810: 911a add sp,sp,t1 - 8812: 7ef0 flw fa2,124(a3) - 8814: 8906 mv s2,ra - 8816: 1a00 addi s0,sp,304 - 8818: 0078 addi a4,sp,12 - 881a: 911e add sp,sp,t2 - 881c: 7ef0 flw fa2,124(a3) - 881e: 4006 0x4006 - 8820: 8d25 xor a0,a0,s1 - 8822: 1e00 addi s0,sp,816 - 8824: 9122 add sp,sp,s0 - 8826: 7ef0 flw fa2,124(a3) - 8828: 8906 mv s2,ra - 882a: 1a00 addi s0,sp,304 - 882c: 008d addi ra,ra,3 - 882e: 401e 0x401e - 8830: 2225 jal 8958 <_start-0x7fff76a8> - 8832: 0089 addi ra,ra,2 - 8834: 401a 0x401a - 8836: 2224 fld fs1,64(a2) - 8838: 4b40 lw s0,20(a4) - 883a: 2224 fld fs1,64(a2) - 883c: 9f2d 0x9f2d - ... - 8846: 06b4 addi a3,sp,840 - 8848: 0000 unimp - 884a: 06c0 addi s0,sp,836 - 884c: 0000 unimp - 884e: 0011 c.nop 4 - 8850: 4b40008b 0x4b40008b - 8854: 2224 fld fs1,64(a2) - 8856: 0076 c.slli zero,0x1d - 8858: 4b40 lw s0,20(a4) - 885a: 2224 fld fs1,64(a2) - 885c: 082d addi a6,a6,11 - 885e: 1aff 0x1aff - 8860: c09f 0006 cc00 0xcc000006c09f - 8866: 0006 c.slli zero,0x1 - 8868: 1f00 addi s0,sp,944 - 886a: 8b00 0x8b00 - 886c: 4000 lw s0,0(s0) - 886e: 7a22244b fnmsub.d fs0,ft4,ft2,fa5,rdn - 8872: 4000 lw s0,0(s0) - 8874: 2d22244b 0x2d22244b - 8878: 0076 c.slli zero,0x1d - 887a: 4b40 lw s0,20(a4) - 887c: 2224 fld fs1,64(a2) - 887e: 007f 0x7f - 8880: 4b40 lw s0,20(a4) - 8882: 2224 fld fs1,64(a2) - 8884: 212d jal 8cae <_start-0x7fff7352> - 8886: ff08 fsw fa0,56(a4) - 8888: 9f1a add t5,t5,t1 - 888a: 06cc addi a1,sp,836 - 888c: 0000 unimp - 888e: 06dc addi a5,sp,836 - 8890: 0000 unimp - 8892: 008d addi ra,ra,3 - 8894: 4b40008b 0x4b40008b - 8898: 2224 fld fs1,64(a2) - 889a: 007a c.slli zero,0x1e - 889c: 4b40 lw s0,20(a4) - 889e: 2224 fld fs1,64(a2) - 88a0: 762d lui a2,0xfffeb - 88a2: 4000 lw s0,0(s0) - 88a4: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - 88a8: 8e00 0x8e00 - 88aa: 1e00 addi s0,sp,816 - 88ac: 0089 addi ra,ra,2 - 88ae: 8d1a mv s10,t1 - 88b0: 7e00 flw fs0,56(a2) - 88b2: 1e00 addi s0,sp,816 - 88b4: 0089 addi ra,ra,2 - 88b6: 221a fld ft4,384(sp) - 88b8: 0078 addi a4,sp,12 - 88ba: 007e c.slli zero,0x1f - 88bc: 8f1e mv t5,t2 - 88be: 8d00 0x8d00 - 88c0: 1e00 addi s0,sp,816 - 88c2: 8d22 mv s10,s0 - 88c4: 7e00 flw fs0,56(a2) - 88c6: 1e00 addi s0,sp,816 - 88c8: 2540 fld fs0,136(a0) - 88ca: 8922 mv s2,s0 - 88cc: 1a00 addi s0,sp,304 - 88ce: 2440 fld fs0,136(s0) - 88d0: 7922 flw fs2,40(sp) - 88d2: 7b00 flw fs0,48(a4) - 88d4: 1e00 addi s0,sp,816 - 88d6: 0082 c.slli64 ra - 88d8: 008e slli ra,ra,0x3 - 88da: 221e fld ft4,448(sp) - 88dc: 008e007b 0x8e007b - 88e0: 401e 0x401e - 88e2: 2225 jal 8a0a <_start-0x7fff75f6> - 88e4: 0089 addi ra,ra,2 - 88e6: 401a 0x401a - 88e8: 2224 fld fs1,64(a2) - 88ea: 0086 slli ra,ra,0x1 - 88ec: 4022 0x4022 - 88ee: 8d22244b 0x8d22244b - 88f2: 7e00 flw fs0,56(a2) - 88f4: 1e00 addi s0,sp,816 - 88f6: 0089 addi ra,ra,2 - 88f8: 781a flw fa6,164(sp) - 88fa: 7e00 flw fs0,56(a2) - 88fc: 1e00 addi s0,sp,816 - 88fe: 008d008f 0x8d008f - 8902: 221e fld ft4,448(sp) - 8904: 008d addi ra,ra,3 - 8906: 007e c.slli zero,0x1f - 8908: 401e 0x401e - 890a: 2225 jal 8a32 <_start-0x7fff75ce> - 890c: 0089 addi ra,ra,2 - 890e: 401a 0x401a - 8910: 2224 fld fs1,64(a2) - 8912: 4b40 lw s0,20(a4) - 8914: 2224 fld fs1,64(a2) - 8916: 402d c.li zero,11 - 8918: 2d22244b 0x2d22244b - 891c: 0821 addi a6,a6,8 - 891e: 1aff 0x1aff - 8920: dc9f 0006 e400 0xe4000006dc9f - 8926: 0006 c.slli zero,0x1 - 8928: fe00 fsw fs0,56(a2) - 892a: 8b00 0x8b00 - 892c: 4000 lw s0,0(s0) - 892e: 7a22244b fnmsub.d fs0,ft4,ft2,fa5,rdn - 8932: 4000 lw s0,0(s0) - 8934: 2d22244b 0x2d22244b - 8938: 008e007b 0x8e007b - 893c: 891e mv s2,t2 - 893e: 1a00 addi s0,sp,304 - 8940: 008d addi ra,ra,3 - 8942: 007e c.slli zero,0x1f - 8944: 891e mv s2,t2 - 8946: 1a00 addi s0,sp,304 - 8948: 7822 flw fa6,40(sp) - 894a: 7e00 flw fs0,56(a2) - 894c: 1e00 addi s0,sp,816 - 894e: 008d008f 0x8d008f - 8952: 221e fld ft4,448(sp) - 8954: 008d addi ra,ra,3 - 8956: 007e c.slli zero,0x1f - 8958: 401e 0x401e - 895a: 2225 jal 8a82 <_start-0x7fff757e> - 895c: 0089 addi ra,ra,2 - 895e: 401a 0x401a - 8960: 2224 fld fs1,64(a2) - 8962: 0079 c.nop 30 - 8964: 821e007b 0x821e007b - 8968: 8e00 0x8e00 - 896a: 1e00 addi s0,sp,816 - 896c: 7b22 flw fs6,40(sp) - 896e: 8e00 0x8e00 - 8970: 1e00 addi s0,sp,816 - 8972: 2540 fld fs0,136(a0) - 8974: 8922 mv s2,s0 - 8976: 1a00 addi s0,sp,304 - 8978: 2440 fld fs0,136(s0) - 897a: 8622 mv a2,s0 - 897c: 2200 fld fs0,0(a2) - 897e: 4b40 lw s0,20(a4) - 8980: 2224 fld fs1,64(a2) - 8982: 008d addi ra,ra,3 - 8984: 007e c.slli zero,0x1f - 8986: 891e mv s2,t2 - 8988: 1a00 addi s0,sp,304 - 898a: 0078 addi a4,sp,12 - 898c: 007e c.slli zero,0x1f - 898e: 8f1e mv t5,t2 - 8990: 8d00 0x8d00 - 8992: 1e00 addi s0,sp,816 - 8994: 8d22 mv s10,s0 - 8996: 7e00 flw fs0,56(a2) - 8998: 1e00 addi s0,sp,816 - 899a: 2540 fld fs0,136(a0) - 899c: 8922 mv s2,s0 - 899e: 1a00 addi s0,sp,304 - 89a0: 2440 fld fs0,136(s0) - 89a2: 4022 0x4022 - 89a4: 2d22244b 0x2d22244b - 89a8: 4022008b 0x4022008b - 89ac: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - 89b0: 8e00 0x8e00 - 89b2: 1e00 addi s0,sp,816 - 89b4: 0089 addi ra,ra,2 - 89b6: 8d1a mv s10,t1 - 89b8: 7e00 flw fs0,56(a2) - 89ba: 1e00 addi s0,sp,816 - 89bc: 0089 addi ra,ra,2 - 89be: 221a fld ft4,384(sp) - 89c0: 0078 addi a4,sp,12 - 89c2: 007e c.slli zero,0x1f - 89c4: 8f1e mv t5,t2 - 89c6: 8d00 0x8d00 - 89c8: 1e00 addi s0,sp,816 - 89ca: 8d22 mv s10,s0 - 89cc: 7e00 flw fs0,56(a2) - 89ce: 1e00 addi s0,sp,816 - 89d0: 2540 fld fs0,136(a0) - 89d2: 8922 mv s2,s0 - 89d4: 1a00 addi s0,sp,304 - 89d6: 2440 fld fs0,136(s0) - 89d8: 7922 flw fs2,40(sp) - 89da: 7b00 flw fs0,48(a4) - 89dc: 1e00 addi s0,sp,816 - 89de: 0082 c.slli64 ra - 89e0: 008e slli ra,ra,0x3 - 89e2: 221e fld ft4,448(sp) - 89e4: 008e007b 0x8e007b - 89e8: 401e 0x401e - 89ea: 2225 jal 8b12 <_start-0x7fff74ee> - 89ec: 0089 addi ra,ra,2 - 89ee: 401a 0x401a - 89f0: 2224 fld fs1,64(a2) - 89f2: 0086 slli ra,ra,0x1 - 89f4: 4022 0x4022 - 89f6: 8d22244b 0x8d22244b - 89fa: 7e00 flw fs0,56(a2) - 89fc: 1e00 addi s0,sp,816 - 89fe: 0089 addi ra,ra,2 - 8a00: 781a flw fa6,164(sp) - 8a02: 7e00 flw fs0,56(a2) - 8a04: 1e00 addi s0,sp,816 - 8a06: 008d008f 0x8d008f - 8a0a: 221e fld ft4,448(sp) - 8a0c: 008d addi ra,ra,3 - 8a0e: 007e c.slli zero,0x1f - 8a10: 401e 0x401e - 8a12: 2225 jal 8b3a <_start-0x7fff74c6> - 8a14: 0089 addi ra,ra,2 - 8a16: 401a 0x401a - 8a18: 2224 fld fs1,64(a2) - 8a1a: 4b40 lw s0,20(a4) - 8a1c: 2224 fld fs1,64(a2) - 8a1e: 402d c.li zero,11 - 8a20: 2d22244b 0x2d22244b - 8a24: 0821 addi a6,a6,8 - 8a26: 1aff 0x1aff - 8a28: e49f 0006 0c00 0xc000006e49f - 8a2e: 04000007 0x4000007 - 8a32: 8001 c.srli64 s0 - 8a34: 7a00 flw fs0,48(a2) - 8a36: 2200 fld fs0,0(a2) - 8a38: 4b40 lw s0,20(a4) - 8a3a: 2224 fld fs1,64(a2) - 8a3c: 0080 addi s0,sp,64 - 8a3e: 4b40 lw s0,20(a4) - 8a40: 2224 fld fs1,64(a2) - 8a42: 7b2d lui s6,0xfffeb - 8a44: 8e00 0x8e00 - 8a46: 1e00 addi s0,sp,816 - 8a48: 0089 addi ra,ra,2 - 8a4a: 8d1a mv s10,t1 - 8a4c: 7e00 flw fs0,56(a2) - 8a4e: 1e00 addi s0,sp,816 - 8a50: 0089 addi ra,ra,2 - 8a52: 221a fld ft4,384(sp) - 8a54: 0078 addi a4,sp,12 - 8a56: 007e c.slli zero,0x1f - 8a58: 8f1e mv t5,t2 - 8a5a: 8d00 0x8d00 - 8a5c: 1e00 addi s0,sp,816 - 8a5e: 8d22 mv s10,s0 - 8a60: 7e00 flw fs0,56(a2) - 8a62: 1e00 addi s0,sp,816 - 8a64: 2540 fld fs0,136(a0) - 8a66: 8922 mv s2,s0 - 8a68: 1a00 addi s0,sp,304 - 8a6a: 2440 fld fs0,136(s0) - 8a6c: 7922 flw fs2,40(sp) - 8a6e: 7b00 flw fs0,48(a4) - 8a70: 1e00 addi s0,sp,816 - 8a72: 0082 c.slli64 ra - 8a74: 008e slli ra,ra,0x3 - 8a76: 221e fld ft4,448(sp) - 8a78: 008e007b 0x8e007b - 8a7c: 401e 0x401e - 8a7e: 2225 jal 8ba6 <_start-0x7fff745a> - 8a80: 0089 addi ra,ra,2 - 8a82: 401a 0x401a - 8a84: 2224 fld fs1,64(a2) - 8a86: 0086 slli ra,ra,0x1 - 8a88: 4022 0x4022 - 8a8a: 8d22244b 0x8d22244b - 8a8e: 7e00 flw fs0,56(a2) - 8a90: 1e00 addi s0,sp,816 - 8a92: 0089 addi ra,ra,2 - 8a94: 781a flw fa6,164(sp) - 8a96: 7e00 flw fs0,56(a2) - 8a98: 1e00 addi s0,sp,816 - 8a9a: 008d008f 0x8d008f - 8a9e: 221e fld ft4,448(sp) - 8aa0: 008d addi ra,ra,3 - 8aa2: 007e c.slli zero,0x1f - 8aa4: 401e 0x401e - 8aa6: 2225 jal 8bce <_start-0x7fff7432> - 8aa8: 0089 addi ra,ra,2 - 8aaa: 401a 0x401a - 8aac: 2224 fld fs1,64(a2) - 8aae: 4b40 lw s0,20(a4) - 8ab0: 2224 fld fs1,64(a2) - 8ab2: 7a2d lui s4,0xfffeb - 8ab4: 2200 fld fs0,0(a2) - 8ab6: 0080 addi s0,sp,64 - 8ab8: 4022 0x4022 - 8aba: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - 8abe: 8e00 0x8e00 - 8ac0: 1e00 addi s0,sp,816 - 8ac2: 0089 addi ra,ra,2 - 8ac4: 8d1a mv s10,t1 - 8ac6: 7e00 flw fs0,56(a2) - 8ac8: 1e00 addi s0,sp,816 - 8aca: 0089 addi ra,ra,2 - 8acc: 221a fld ft4,384(sp) - 8ace: 0078 addi a4,sp,12 - 8ad0: 007e c.slli zero,0x1f - 8ad2: 8f1e mv t5,t2 - 8ad4: 8d00 0x8d00 - 8ad6: 1e00 addi s0,sp,816 - 8ad8: 8d22 mv s10,s0 - 8ada: 7e00 flw fs0,56(a2) - 8adc: 1e00 addi s0,sp,816 - 8ade: 2540 fld fs0,136(a0) - 8ae0: 8922 mv s2,s0 - 8ae2: 1a00 addi s0,sp,304 - 8ae4: 2440 fld fs0,136(s0) - 8ae6: 7922 flw fs2,40(sp) - 8ae8: 7b00 flw fs0,48(a4) - 8aea: 1e00 addi s0,sp,816 - 8aec: 0082 c.slli64 ra - 8aee: 008e slli ra,ra,0x3 - 8af0: 221e fld ft4,448(sp) - 8af2: 008e007b 0x8e007b - 8af6: 401e 0x401e - 8af8: 2225 jal 8c20 <_start-0x7fff73e0> - 8afa: 0089 addi ra,ra,2 - 8afc: 401a 0x401a - 8afe: 2224 fld fs1,64(a2) - 8b00: 0086 slli ra,ra,0x1 - 8b02: 4022 0x4022 - 8b04: 8d22244b 0x8d22244b - 8b08: 7e00 flw fs0,56(a2) - 8b0a: 1e00 addi s0,sp,816 - 8b0c: 0089 addi ra,ra,2 - 8b0e: 781a flw fa6,164(sp) - 8b10: 7e00 flw fs0,56(a2) - 8b12: 1e00 addi s0,sp,816 - 8b14: 008d008f 0x8d008f - 8b18: 221e fld ft4,448(sp) - 8b1a: 008d addi ra,ra,3 - 8b1c: 007e c.slli zero,0x1f - 8b1e: 401e 0x401e - 8b20: 2225 jal 8c48 <_start-0x7fff73b8> - 8b22: 0089 addi ra,ra,2 - 8b24: 401a 0x401a - 8b26: 2224 fld fs1,64(a2) - 8b28: 4b40 lw s0,20(a4) - 8b2a: 2224 fld fs1,64(a2) - 8b2c: 402d c.li zero,11 - 8b2e: 2d22244b 0x2d22244b - 8b32: 0821 addi a6,a6,8 - 8b34: 1aff 0x1aff - 8b36: 0c9f 0007 2000 0x200000070c9f - 8b3c: 40000007 vlseg3bu.v v0,(zero),v0.t - 8b40: 8001 c.srli64 s0 - 8b42: 7a00 flw fs0,48(a2) - 8b44: 2200 fld fs0,0(a2) - 8b46: 4b40 lw s0,20(a4) - 8b48: 2224 fld fs1,64(a2) - 8b4a: 0080 addi s0,sp,64 - 8b4c: 4b40 lw s0,20(a4) - 8b4e: 2224 fld fs1,64(a2) - 8b50: 7b2d lui s6,0xfffeb - 8b52: 8e00 0x8e00 - 8b54: 1e00 addi s0,sp,816 - 8b56: 0089 addi ra,ra,2 - 8b58: 911a add sp,sp,t1 - 8b5a: 7ef0 flw fa2,124(a3) - 8b5c: 8906 mv s2,ra - 8b5e: 1a00 addi s0,sp,304 - 8b60: 008d addi ra,ra,3 - 8b62: 891e mv s2,t2 - 8b64: 1a00 addi s0,sp,304 - 8b66: 9122 add sp,sp,s0 - 8b68: 7ef0 flw fa2,124(a3) - 8b6a: 8906 mv s2,ra - 8b6c: 1a00 addi s0,sp,304 - 8b6e: 0078 addi a4,sp,12 - 8b70: 8f1e mv t5,t2 - 8b72: 8d00 0x8d00 - 8b74: 1e00 addi s0,sp,816 - 8b76: 9122 add sp,sp,s0 - 8b78: 7ef0 flw fa2,124(a3) - 8b7a: 8906 mv s2,ra - 8b7c: 1a00 addi s0,sp,304 - 8b7e: 008d addi ra,ra,3 - 8b80: 401e 0x401e - 8b82: 2225 jal 8caa <_start-0x7fff7356> - 8b84: 0089 addi ra,ra,2 - 8b86: 401a 0x401a - 8b88: 2224 fld fs1,64(a2) - 8b8a: 0079 c.nop 30 - 8b8c: 821e007b 0x821e007b - 8b90: 8e00 0x8e00 - 8b92: 1e00 addi s0,sp,816 - 8b94: 7b22 flw fs6,40(sp) - 8b96: 8e00 0x8e00 - 8b98: 1e00 addi s0,sp,816 - 8b9a: 2540 fld fs0,136(a0) - 8b9c: 8922 mv s2,s0 - 8b9e: 1a00 addi s0,sp,304 - 8ba0: 2440 fld fs0,136(s0) - 8ba2: 8622 mv a2,s0 - 8ba4: 2200 fld fs0,0(a2) - 8ba6: 4b40 lw s0,20(a4) - 8ba8: 2224 fld fs1,64(a2) - 8baa: f091 bnez s1,8aae <_start-0x7fff7552> - 8bac: 067e slli a2,a2,0x1f - 8bae: 0089 addi ra,ra,2 - 8bb0: 8d1a mv s10,t1 - 8bb2: 1e00 addi s0,sp,816 - 8bb4: 0089 addi ra,ra,2 - 8bb6: 911a add sp,sp,t1 - 8bb8: 7ef0 flw fa2,124(a3) - 8bba: 8906 mv s2,ra - 8bbc: 1a00 addi s0,sp,304 - 8bbe: 0078 addi a4,sp,12 - 8bc0: 8f1e mv t5,t2 - 8bc2: 8d00 0x8d00 - 8bc4: 1e00 addi s0,sp,816 - 8bc6: 9122 add sp,sp,s0 - 8bc8: 7ef0 flw fa2,124(a3) - 8bca: 8906 mv s2,ra - 8bcc: 1a00 addi s0,sp,304 - 8bce: 008d addi ra,ra,3 - 8bd0: 401e 0x401e - 8bd2: 2225 jal 8cfa <_start-0x7fff7306> - 8bd4: 0089 addi ra,ra,2 - 8bd6: 401a 0x401a - 8bd8: 2224 fld fs1,64(a2) - 8bda: 4b40 lw s0,20(a4) - 8bdc: 2224 fld fs1,64(a2) - 8bde: 7a2d lui s4,0xfffeb - 8be0: 2200 fld fs0,0(a2) - 8be2: 0080 addi s0,sp,64 - 8be4: 4022 0x4022 - 8be6: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - 8bea: 8e00 0x8e00 - 8bec: 1e00 addi s0,sp,816 - 8bee: 0089 addi ra,ra,2 - 8bf0: 911a add sp,sp,t1 - 8bf2: 7ef0 flw fa2,124(a3) - 8bf4: 8906 mv s2,ra - 8bf6: 1a00 addi s0,sp,304 - 8bf8: 008d addi ra,ra,3 - 8bfa: 891e mv s2,t2 - 8bfc: 1a00 addi s0,sp,304 - 8bfe: 9122 add sp,sp,s0 - 8c00: 7ef0 flw fa2,124(a3) - 8c02: 8906 mv s2,ra - 8c04: 1a00 addi s0,sp,304 - 8c06: 0078 addi a4,sp,12 - 8c08: 8f1e mv t5,t2 - 8c0a: 8d00 0x8d00 - 8c0c: 1e00 addi s0,sp,816 - 8c0e: 9122 add sp,sp,s0 - 8c10: 7ef0 flw fa2,124(a3) - 8c12: 8906 mv s2,ra - 8c14: 1a00 addi s0,sp,304 - 8c16: 008d addi ra,ra,3 - 8c18: 401e 0x401e - 8c1a: 2225 jal 8d42 <_start-0x7fff72be> - 8c1c: 0089 addi ra,ra,2 - 8c1e: 401a 0x401a - 8c20: 2224 fld fs1,64(a2) - 8c22: 0079 c.nop 30 - 8c24: 821e007b 0x821e007b - 8c28: 8e00 0x8e00 - 8c2a: 1e00 addi s0,sp,816 - 8c2c: 7b22 flw fs6,40(sp) - 8c2e: 8e00 0x8e00 - 8c30: 1e00 addi s0,sp,816 - 8c32: 2540 fld fs0,136(a0) - 8c34: 8922 mv s2,s0 - 8c36: 1a00 addi s0,sp,304 - 8c38: 2440 fld fs0,136(s0) - 8c3a: 8622 mv a2,s0 - 8c3c: 2200 fld fs0,0(a2) - 8c3e: 4b40 lw s0,20(a4) - 8c40: 2224 fld fs1,64(a2) - 8c42: f091 bnez s1,8b46 <_start-0x7fff74ba> - 8c44: 067e slli a2,a2,0x1f - 8c46: 0089 addi ra,ra,2 - 8c48: 8d1a mv s10,t1 - 8c4a: 1e00 addi s0,sp,816 - 8c4c: 0089 addi ra,ra,2 - 8c4e: 911a add sp,sp,t1 - 8c50: 7ef0 flw fa2,124(a3) - 8c52: 8906 mv s2,ra - 8c54: 1a00 addi s0,sp,304 - 8c56: 0078 addi a4,sp,12 - 8c58: 8f1e mv t5,t2 - 8c5a: 8d00 0x8d00 - 8c5c: 1e00 addi s0,sp,816 - 8c5e: 9122 add sp,sp,s0 - 8c60: 7ef0 flw fa2,124(a3) - 8c62: 8906 mv s2,ra - 8c64: 1a00 addi s0,sp,304 - 8c66: 008d addi ra,ra,3 - 8c68: 401e 0x401e - 8c6a: 2225 jal 8d92 <_start-0x7fff726e> - 8c6c: 0089 addi ra,ra,2 - 8c6e: 401a 0x401a - 8c70: 2224 fld fs1,64(a2) - 8c72: 4b40 lw s0,20(a4) - 8c74: 2224 fld fs1,64(a2) - 8c76: 402d c.li zero,11 - 8c78: 2d22244b 0x2d22244b - 8c7c: 0821 addi a6,a6,8 - 8c7e: 1aff 0x1aff - 8c80: 209f 0007 3400 0x34000007209f - 8c86: 50000007 vlseg3b.v v0,(zero),v0.t - 8c8a: 8001 c.srli64 s0 - 8c8c: 7a00 flw fs0,48(a2) - 8c8e: 2200 fld fs0,0(a2) - 8c90: 4b40 lw s0,20(a4) - 8c92: 2224 fld fs1,64(a2) - 8c94: 0080 addi s0,sp,64 - 8c96: 4b40 lw s0,20(a4) - 8c98: 2224 fld fs1,64(a2) - 8c9a: 7b2d lui s6,0xfffeb - 8c9c: 8e00 0x8e00 - 8c9e: 1e00 addi s0,sp,816 - 8ca0: 0089 addi ra,ra,2 - 8ca2: 911a add sp,sp,t1 - 8ca4: 7ef0 flw fa2,124(a3) - 8ca6: 8906 mv s2,ra - 8ca8: 1a00 addi s0,sp,304 - 8caa: 008d addi ra,ra,3 - 8cac: 891e mv s2,t2 - 8cae: 1a00 addi s0,sp,304 - 8cb0: 9122 add sp,sp,s0 - 8cb2: 7ef0 flw fa2,124(a3) - 8cb4: 8906 mv s2,ra - 8cb6: 1a00 addi s0,sp,304 - 8cb8: 0078 addi a4,sp,12 - 8cba: 911e add sp,sp,t2 - 8cbc: 7ef0 flw fa2,124(a3) - 8cbe: 4006 0x4006 - 8cc0: 8d25 xor a0,a0,s1 - 8cc2: 1e00 addi s0,sp,816 - 8cc4: 9122 add sp,sp,s0 - 8cc6: 7ef0 flw fa2,124(a3) - 8cc8: 8906 mv s2,ra - 8cca: 1a00 addi s0,sp,304 - 8ccc: 008d addi ra,ra,3 - 8cce: 401e 0x401e - 8cd0: 2225 jal 8df8 <_start-0x7fff7208> - 8cd2: 0089 addi ra,ra,2 - 8cd4: 401a 0x401a - 8cd6: 2224 fld fs1,64(a2) - 8cd8: 0079 c.nop 30 - 8cda: 821e007b 0x821e007b - 8cde: 8e00 0x8e00 - 8ce0: 1e00 addi s0,sp,816 - 8ce2: 7b22 flw fs6,40(sp) - 8ce4: 8e00 0x8e00 - 8ce6: 1e00 addi s0,sp,816 - 8ce8: 2540 fld fs0,136(a0) - 8cea: 8922 mv s2,s0 - 8cec: 1a00 addi s0,sp,304 - 8cee: 2440 fld fs0,136(s0) - 8cf0: 8622 mv a2,s0 - 8cf2: 2200 fld fs0,0(a2) - 8cf4: 4b40 lw s0,20(a4) - 8cf6: 2224 fld fs1,64(a2) - 8cf8: f091 bnez s1,8bfc <_start-0x7fff7404> - 8cfa: 067e slli a2,a2,0x1f - 8cfc: 0089 addi ra,ra,2 - 8cfe: 8d1a mv s10,t1 - 8d00: 1e00 addi s0,sp,816 - 8d02: 0089 addi ra,ra,2 - 8d04: 911a add sp,sp,t1 - 8d06: 7ef0 flw fa2,124(a3) - 8d08: 8906 mv s2,ra - 8d0a: 1a00 addi s0,sp,304 - 8d0c: 0078 addi a4,sp,12 - 8d0e: 911e add sp,sp,t2 - 8d10: 7ef0 flw fa2,124(a3) - 8d12: 4006 0x4006 - 8d14: 8d25 xor a0,a0,s1 - 8d16: 1e00 addi s0,sp,816 - 8d18: 9122 add sp,sp,s0 - 8d1a: 7ef0 flw fa2,124(a3) - 8d1c: 8906 mv s2,ra - 8d1e: 1a00 addi s0,sp,304 - 8d20: 008d addi ra,ra,3 - 8d22: 401e 0x401e - 8d24: 2225 jal 8e4c <_start-0x7fff71b4> - 8d26: 0089 addi ra,ra,2 - 8d28: 401a 0x401a - 8d2a: 2224 fld fs1,64(a2) - 8d2c: 4b40 lw s0,20(a4) - 8d2e: 2224 fld fs1,64(a2) - 8d30: 7a2d lui s4,0xfffeb - 8d32: 2200 fld fs0,0(a2) - 8d34: 0080 addi s0,sp,64 - 8d36: 4022 0x4022 - 8d38: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - 8d3c: 8e00 0x8e00 - 8d3e: 1e00 addi s0,sp,816 - 8d40: 0089 addi ra,ra,2 - 8d42: 911a add sp,sp,t1 - 8d44: 7ef0 flw fa2,124(a3) - 8d46: 8906 mv s2,ra - 8d48: 1a00 addi s0,sp,304 - 8d4a: 008d addi ra,ra,3 - 8d4c: 891e mv s2,t2 - 8d4e: 1a00 addi s0,sp,304 - 8d50: 9122 add sp,sp,s0 - 8d52: 7ef0 flw fa2,124(a3) - 8d54: 8906 mv s2,ra - 8d56: 1a00 addi s0,sp,304 - 8d58: 0078 addi a4,sp,12 - 8d5a: 911e add sp,sp,t2 - 8d5c: 7ef0 flw fa2,124(a3) - 8d5e: 4006 0x4006 - 8d60: 8d25 xor a0,a0,s1 - 8d62: 1e00 addi s0,sp,816 - 8d64: 9122 add sp,sp,s0 - 8d66: 7ef0 flw fa2,124(a3) - 8d68: 8906 mv s2,ra - 8d6a: 1a00 addi s0,sp,304 - 8d6c: 008d addi ra,ra,3 - 8d6e: 401e 0x401e - 8d70: 2225 jal 8e98 <_start-0x7fff7168> - 8d72: 0089 addi ra,ra,2 - 8d74: 401a 0x401a - 8d76: 2224 fld fs1,64(a2) - 8d78: 0079 c.nop 30 - 8d7a: 821e007b 0x821e007b - 8d7e: 8e00 0x8e00 - 8d80: 1e00 addi s0,sp,816 - 8d82: 7b22 flw fs6,40(sp) - 8d84: 8e00 0x8e00 - 8d86: 1e00 addi s0,sp,816 - 8d88: 2540 fld fs0,136(a0) - 8d8a: 8922 mv s2,s0 - 8d8c: 1a00 addi s0,sp,304 - 8d8e: 2440 fld fs0,136(s0) - 8d90: 8622 mv a2,s0 - 8d92: 2200 fld fs0,0(a2) - 8d94: 4b40 lw s0,20(a4) - 8d96: 2224 fld fs1,64(a2) - 8d98: f091 bnez s1,8c9c <_start-0x7fff7364> - 8d9a: 067e slli a2,a2,0x1f - 8d9c: 0089 addi ra,ra,2 - 8d9e: 8d1a mv s10,t1 - 8da0: 1e00 addi s0,sp,816 - 8da2: 0089 addi ra,ra,2 - 8da4: 911a add sp,sp,t1 - 8da6: 7ef0 flw fa2,124(a3) - 8da8: 8906 mv s2,ra - 8daa: 1a00 addi s0,sp,304 - 8dac: 0078 addi a4,sp,12 - 8dae: 911e add sp,sp,t2 - 8db0: 7ef0 flw fa2,124(a3) - 8db2: 4006 0x4006 - 8db4: 8d25 xor a0,a0,s1 - 8db6: 1e00 addi s0,sp,816 - 8db8: 9122 add sp,sp,s0 - 8dba: 7ef0 flw fa2,124(a3) - 8dbc: 8906 mv s2,ra - 8dbe: 1a00 addi s0,sp,304 - 8dc0: 008d addi ra,ra,3 - 8dc2: 401e 0x401e - 8dc4: 2225 jal 8eec <_start-0x7fff7114> - 8dc6: 0089 addi ra,ra,2 - 8dc8: 401a 0x401a - 8dca: 2224 fld fs1,64(a2) - 8dcc: 4b40 lw s0,20(a4) - 8dce: 2224 fld fs1,64(a2) - 8dd0: 402d c.li zero,11 - 8dd2: 2d22244b 0x2d22244b - 8dd6: 0821 addi a6,a6,8 - 8dd8: 1aff 0x1aff - 8dda: 349f 0007 5800 0x58000007349f - 8de0: 54000007 0x54000007 - 8de4: 8001 c.srli64 s0 - 8de6: 9100 0x9100 - 8de8: 7eec flw fa1,124(a3) - 8dea: 2206 fld ft4,64(sp) - 8dec: 4b40 lw s0,20(a4) - 8dee: 2224 fld fs1,64(a2) - 8df0: 0080 addi s0,sp,64 - 8df2: 4b40 lw s0,20(a4) - 8df4: 2224 fld fs1,64(a2) - 8df6: 7b2d lui s6,0xfffeb - 8df8: 8e00 0x8e00 - 8dfa: 1e00 addi s0,sp,816 - 8dfc: 0089 addi ra,ra,2 - 8dfe: 911a add sp,sp,t1 - 8e00: 7ef0 flw fa2,124(a3) - 8e02: 8906 mv s2,ra - 8e04: 1a00 addi s0,sp,304 - 8e06: 008d addi ra,ra,3 - 8e08: 891e mv s2,t2 - 8e0a: 1a00 addi s0,sp,304 - 8e0c: 9122 add sp,sp,s0 - 8e0e: 7ef0 flw fa2,124(a3) - 8e10: 8906 mv s2,ra - 8e12: 1a00 addi s0,sp,304 - 8e14: 0078 addi a4,sp,12 - 8e16: 911e add sp,sp,t2 - 8e18: 7ef0 flw fa2,124(a3) - 8e1a: 4006 0x4006 - 8e1c: 8d25 xor a0,a0,s1 - 8e1e: 1e00 addi s0,sp,816 - 8e20: 9122 add sp,sp,s0 - 8e22: 7ef0 flw fa2,124(a3) - 8e24: 8906 mv s2,ra - 8e26: 1a00 addi s0,sp,304 - 8e28: 008d addi ra,ra,3 - 8e2a: 401e 0x401e - 8e2c: 2225 jal 8f54 <_start-0x7fff70ac> - 8e2e: 0089 addi ra,ra,2 - 8e30: 401a 0x401a - 8e32: 2224 fld fs1,64(a2) - 8e34: 0079 c.nop 30 - 8e36: 821e007b 0x821e007b - 8e3a: 8e00 0x8e00 - 8e3c: 1e00 addi s0,sp,816 - 8e3e: 7b22 flw fs6,40(sp) - 8e40: 8e00 0x8e00 - 8e42: 1e00 addi s0,sp,816 - 8e44: 2540 fld fs0,136(a0) - 8e46: 8922 mv s2,s0 - 8e48: 1a00 addi s0,sp,304 - 8e4a: 2440 fld fs0,136(s0) - 8e4c: 8622 mv a2,s0 - 8e4e: 2200 fld fs0,0(a2) - 8e50: 4b40 lw s0,20(a4) - 8e52: 2224 fld fs1,64(a2) - 8e54: f091 bnez s1,8d58 <_start-0x7fff72a8> - 8e56: 067e slli a2,a2,0x1f - 8e58: 0089 addi ra,ra,2 - 8e5a: 8d1a mv s10,t1 - 8e5c: 1e00 addi s0,sp,816 - 8e5e: 0089 addi ra,ra,2 - 8e60: 911a add sp,sp,t1 - 8e62: 7ef0 flw fa2,124(a3) - 8e64: 8906 mv s2,ra - 8e66: 1a00 addi s0,sp,304 - 8e68: 0078 addi a4,sp,12 - 8e6a: 911e add sp,sp,t2 - 8e6c: 7ef0 flw fa2,124(a3) - 8e6e: 4006 0x4006 - 8e70: 8d25 xor a0,a0,s1 - 8e72: 1e00 addi s0,sp,816 - 8e74: 9122 add sp,sp,s0 - 8e76: 7ef0 flw fa2,124(a3) - 8e78: 8906 mv s2,ra - 8e7a: 1a00 addi s0,sp,304 - 8e7c: 008d addi ra,ra,3 - 8e7e: 401e 0x401e - 8e80: 2225 jal 8fa8 <_start-0x7fff7058> - 8e82: 0089 addi ra,ra,2 - 8e84: 401a 0x401a - 8e86: 2224 fld fs1,64(a2) - 8e88: 4b40 lw s0,20(a4) - 8e8a: 2224 fld fs1,64(a2) - 8e8c: 802d srli s0,s0,0xb - 8e8e: 2200 fld fs0,0(a2) - 8e90: ec91 bnez s1,8eac <_start-0x7fff7154> - 8e92: 067e slli a2,a2,0x1f - 8e94: 4022 0x4022 - 8e96: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - 8e9a: 8e00 0x8e00 - 8e9c: 1e00 addi s0,sp,816 - 8e9e: 0089 addi ra,ra,2 - 8ea0: 911a add sp,sp,t1 - 8ea2: 7ef0 flw fa2,124(a3) - 8ea4: 8906 mv s2,ra - 8ea6: 1a00 addi s0,sp,304 - 8ea8: 008d addi ra,ra,3 - 8eaa: 891e mv s2,t2 - 8eac: 1a00 addi s0,sp,304 - 8eae: 9122 add sp,sp,s0 - 8eb0: 7ef0 flw fa2,124(a3) - 8eb2: 8906 mv s2,ra - 8eb4: 1a00 addi s0,sp,304 - 8eb6: 0078 addi a4,sp,12 - 8eb8: 911e add sp,sp,t2 - 8eba: 7ef0 flw fa2,124(a3) - 8ebc: 4006 0x4006 - 8ebe: 8d25 xor a0,a0,s1 - 8ec0: 1e00 addi s0,sp,816 - 8ec2: 9122 add sp,sp,s0 - 8ec4: 7ef0 flw fa2,124(a3) - 8ec6: 8906 mv s2,ra - 8ec8: 1a00 addi s0,sp,304 - 8eca: 008d addi ra,ra,3 - 8ecc: 401e 0x401e - 8ece: 2225 jal 8ff6 <_start-0x7fff700a> - 8ed0: 0089 addi ra,ra,2 - 8ed2: 401a 0x401a - 8ed4: 2224 fld fs1,64(a2) - 8ed6: 0079 c.nop 30 - 8ed8: 821e007b 0x821e007b - 8edc: 8e00 0x8e00 - 8ede: 1e00 addi s0,sp,816 - 8ee0: 7b22 flw fs6,40(sp) - 8ee2: 8e00 0x8e00 - 8ee4: 1e00 addi s0,sp,816 - 8ee6: 2540 fld fs0,136(a0) - 8ee8: 8922 mv s2,s0 - 8eea: 1a00 addi s0,sp,304 - 8eec: 2440 fld fs0,136(s0) - 8eee: 8622 mv a2,s0 - 8ef0: 2200 fld fs0,0(a2) - 8ef2: 4b40 lw s0,20(a4) - 8ef4: 2224 fld fs1,64(a2) - 8ef6: f091 bnez s1,8dfa <_start-0x7fff7206> - 8ef8: 067e slli a2,a2,0x1f - 8efa: 0089 addi ra,ra,2 - 8efc: 8d1a mv s10,t1 - 8efe: 1e00 addi s0,sp,816 - 8f00: 0089 addi ra,ra,2 - 8f02: 911a add sp,sp,t1 - 8f04: 7ef0 flw fa2,124(a3) - 8f06: 8906 mv s2,ra - 8f08: 1a00 addi s0,sp,304 - 8f0a: 0078 addi a4,sp,12 - 8f0c: 911e add sp,sp,t2 - 8f0e: 7ef0 flw fa2,124(a3) - 8f10: 4006 0x4006 - 8f12: 8d25 xor a0,a0,s1 - 8f14: 1e00 addi s0,sp,816 - 8f16: 9122 add sp,sp,s0 - 8f18: 7ef0 flw fa2,124(a3) - 8f1a: 8906 mv s2,ra - 8f1c: 1a00 addi s0,sp,304 - 8f1e: 008d addi ra,ra,3 - 8f20: 401e 0x401e - 8f22: 2225 jal 904a <_start-0x7fff6fb6> - 8f24: 0089 addi ra,ra,2 - 8f26: 401a 0x401a - 8f28: 2224 fld fs1,64(a2) - 8f2a: 4b40 lw s0,20(a4) - 8f2c: 2224 fld fs1,64(a2) - 8f2e: 402d c.li zero,11 - 8f30: 2d22244b 0x2d22244b - 8f34: 0821 addi a6,a6,8 - 8f36: 1aff 0x1aff - 8f38: 009f 0000 0000 0x9f - 8f3e: 0000 unimp - 8f40: d400 sw s0,40(s0) - 8f42: 0006 c.slli zero,0x1 - 8f44: f000 fsw fs0,32(s0) - 8f46: 0006 c.slli zero,0x1 - 8f48: 0100 addi s0,sp,128 - 8f4a: 6100 flw fs0,0(a0) - 8f4c: 06f0 addi a2,sp,844 - 8f4e: 0000 unimp - 8f50: 0764 addi s1,sp,908 - 8f52: 0000 unimp - 8f54: a891002f 0xa891002f - 8f58: 067f 0x67f - 8f5a: 4b40 lw s0,20(a4) - 8f5c: 2224 fld fs1,64(a2) - 8f5e: 007c addi a5,sp,12 - 8f60: 008c addi a1,sp,64 - 8f62: 891e mv s2,t2 - 8f64: 1a00 addi s0,sp,304 - 8f66: 0085 addi ra,ra,1 - 8f68: 007c addi a5,sp,12 - 8f6a: 771e flw fa4,228(sp) - 8f6c: 8c00 0x8c00 - 8f6e: 1e00 addi s0,sp,816 - 8f70: 7c22 flw fs8,40(sp) - 8f72: 8c00 0x8c00 - 8f74: 1e00 addi s0,sp,816 - 8f76: 2540 fld fs0,136(a0) - 8f78: 8922 mv s2,s0 - 8f7a: 1a00 addi s0,sp,304 - 8f7c: 2440 fld fs0,136(s0) - 8f7e: 4022 0x4022 - 8f80: 2d22244b 0x2d22244b - 8f84: 649f 0007 6c00 0x6c000007649f - 8f8a: 33000007 vlseg2bff.v v0,(zero) - 8f8e: 9100 0x9100 - 8f90: 7fa8 flw fa0,120(a5) - 8f92: 4006 0x4006 - 8f94: 7c22244b 0x7c22244b - 8f98: 8c00 0x8c00 - 8f9a: 1e00 addi s0,sp,816 - 8f9c: 0089 addi ra,ra,2 - 8f9e: 911a add sp,sp,t1 - 8fa0: 7f80 flw fs0,56(a5) - 8fa2: 4006 0x4006 - 8fa4: 7c25 lui s8,0xfffe9 - 8fa6: 1e00 addi s0,sp,816 - 8fa8: 008c0077 0x8c0077 - 8fac: 221e fld ft4,448(sp) - 8fae: 007c addi a5,sp,12 - 8fb0: 008c addi a1,sp,64 - 8fb2: 401e 0x401e - 8fb4: 2225 jal 90dc <_start-0x7fff6f24> - 8fb6: 0089 addi ra,ra,2 - 8fb8: 401a 0x401a - 8fba: 2224 fld fs1,64(a2) - 8fbc: 4b40 lw s0,20(a4) - 8fbe: 2224 fld fs1,64(a2) - 8fc0: 9f2d 0x9f2d - 8fc2: 076c addi a1,sp,908 - 8fc4: 0000 unimp - 8fc6: 0860 addi s0,sp,28 - 8fc8: 0000 unimp - 8fca: 0042 c.slli zero,0x10 - 8fcc: a891 j 9020 <_start-0x7fff6fe0> - 8fce: 067f 0x67f - 8fd0: 4b40 lw s0,20(a4) - 8fd2: 2224 fld fs1,64(a2) - 8fd4: 8091 srli s1,s1,0x4 - 8fd6: 067f 0x67f - 8fd8: 0089 addi ra,ra,2 - 8fda: 7c1a flw fs8,164(sp) - 8fdc: 1e00 addi s0,sp,816 - 8fde: 0089 addi ra,ra,2 - 8fe0: 911a add sp,sp,t1 - 8fe2: 7f80 flw fs0,56(a5) - 8fe4: 4006 0x4006 - 8fe6: 7c25 lui s8,0xfffe9 - 8fe8: 1e00 addi s0,sp,816 - 8fea: 8091 srli s1,s1,0x4 - 8fec: 067f 0x67f - 8fee: 0089 addi ra,ra,2 - 8ff0: 771a flw fa4,164(sp) - 8ff2: 1e00 addi s0,sp,816 - 8ff4: 9122 add sp,sp,s0 - 8ff6: 7f80 flw fs0,56(a5) - 8ff8: 8906 mv s2,ra - 8ffa: 1a00 addi s0,sp,304 - 8ffc: 007c addi a5,sp,12 - 8ffe: 401e 0x401e - 9000: 2225 jal 9128 <_start-0x7fff6ed8> - 9002: 0089 addi ra,ra,2 - 9004: 401a 0x401a - 9006: 2224 fld fs1,64(a2) - 9008: 4b40 lw s0,20(a4) - 900a: 2224 fld fs1,64(a2) - 900c: 9f2d 0x9f2d - 900e: 0860 addi s0,sp,28 - 9010: 0000 unimp - 9012: 0894 addi a3,sp,80 - 9014: 0000 unimp - 9016: 0042 c.slli zero,0x10 - 9018: a891 j 906c <_start-0x7fff6f94> - 901a: 067f 0x67f - 901c: 4b40 lw s0,20(a4) - 901e: 2224 fld fs1,64(a2) - 9020: 8091 srli s1,s1,0x4 - 9022: 067f 0x67f - 9024: 008c addi a1,sp,64 - 9026: 7c1a flw fs8,164(sp) - 9028: 1e00 addi s0,sp,816 - 902a: 008c addi a1,sp,64 - 902c: 911a add sp,sp,t1 - 902e: 7f80 flw fs0,56(a5) - 9030: 4006 0x4006 - 9032: 7c25 lui s8,0xfffe9 - 9034: 1e00 addi s0,sp,816 - 9036: 8091 srli s1,s1,0x4 - 9038: 067f 0x67f - 903a: 008c addi a1,sp,64 - 903c: 771a flw fa4,164(sp) - 903e: 1e00 addi s0,sp,816 - 9040: 9122 add sp,sp,s0 - 9042: 7f80 flw fs0,56(a5) - 9044: 8c06 mv s8,ra - 9046: 1a00 addi s0,sp,304 - 9048: 007c addi a5,sp,12 - 904a: 401e 0x401e - 904c: 2225 jal 9174 <_start-0x7fff6e8c> - 904e: 008c addi a1,sp,64 - 9050: 401a 0x401a - 9052: 2224 fld fs1,64(a2) - 9054: 4b40 lw s0,20(a4) - 9056: 2224 fld fs1,64(a2) - 9058: 9f2d 0x9f2d - 905a: 0894 addi a3,sp,80 - 905c: 0000 unimp - 905e: 08e0 addi s0,sp,92 - 9060: 0000 unimp - 9062: a8910047 fmsub.s ft0,ft2,fs1,fs5,rne - 9066: 067f 0x67f - 9068: 4b40 lw s0,20(a4) - 906a: 2224 fld fs1,64(a2) - 906c: 8091 srli s1,s1,0x4 - 906e: 067f 0x67f - 9070: ff0a fsw ft2,188(sp) - 9072: 1aff 0x1aff - 9074: 007c addi a5,sp,12 - 9076: 0a1e slli s4,s4,0x7 - 9078: ffff 0xffff - 907a: 911a add sp,sp,t1 - 907c: 7f80 flw fs0,56(a5) - 907e: 4006 0x4006 - 9080: 7c25 lui s8,0xfffe9 - 9082: 1e00 addi s0,sp,816 - 9084: 8091 srli s1,s1,0x4 - 9086: 067f 0x67f - 9088: ff0a fsw ft2,188(sp) - 908a: 1aff 0x1aff - 908c: 221e0077 0x221e0077 - 9090: 8091 srli s1,s1,0x4 - 9092: 067f 0x67f - 9094: ff0a fsw ft2,188(sp) - 9096: 1aff 0x1aff - 9098: 007c addi a5,sp,12 - 909a: 401e 0x401e - 909c: 2225 jal 91c4 <_start-0x7fff6e3c> - 909e: ff0a fsw ft2,188(sp) - 90a0: 1aff 0x1aff - 90a2: 2440 fld fs0,136(s0) - 90a4: 4022 0x4022 - 90a6: 2d22244b 0x2d22244b - 90aa: e09f 0008 e400 0xe4000008e09f - 90b0: 0008 0x8 - 90b2: 4200 lw s0,0(a2) - 90b4: 9100 0x9100 - 90b6: 7fa8 flw fa0,120(a5) - 90b8: 4006 0x4006 - 90ba: 7a22244b fnmsub.d fs0,ft4,ft2,fa5,rdn - 90be: 917f 0x917f - 90c0: 7f80 flw fs0,56(a5) - 90c2: 1a06 slli s4,s4,0x21 - 90c4: 007c addi a5,sp,12 - 90c6: 7a1e flw fs4,228(sp) - 90c8: 1a7f 0x1a7f - 90ca: 8091 srli s1,s1,0x4 - 90cc: 067f 0x67f - 90ce: 2540 fld fs0,136(a0) - 90d0: 007c addi a5,sp,12 - 90d2: 7a1e flw fs4,228(sp) - 90d4: 917f 0x917f - 90d6: 7f80 flw fs0,56(a5) - 90d8: 1a06 slli s4,s4,0x21 - 90da: 221e0077 0x221e0077 - 90de: 7f7a flw ft10,188(sp) - 90e0: 8091 srli s1,s1,0x4 - 90e2: 067f 0x67f - 90e4: 7c1a flw fs8,164(sp) - 90e6: 1e00 addi s0,sp,816 - 90e8: 2540 fld fs0,136(a0) - 90ea: 7a22 flw fs4,40(sp) - 90ec: 1a7f 0x1a7f - 90ee: 2440 fld fs0,136(s0) - 90f0: 4022 0x4022 - 90f2: 2d22244b 0x2d22244b - 90f6: e49f 0008 e800 0xe8000008e49f - 90fc: 0008 0x8 - 90fe: 4700 lw s0,8(a4) - 9100: 9100 0x9100 - 9102: 7fa8 flw fa0,120(a5) - 9104: 4006 0x4006 - 9106: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - 910a: 7f80 flw fs0,56(a5) - 910c: 0a06 slli s4,s4,0x1 - 910e: ffff 0xffff - 9110: 7c1a flw fs8,164(sp) - 9112: 1e00 addi s0,sp,816 - 9114: ff0a fsw ft2,188(sp) - 9116: 1aff 0x1aff - 9118: 8091 srli s1,s1,0x4 - 911a: 067f 0x67f - 911c: 2540 fld fs0,136(a0) - 911e: 007c addi a5,sp,12 - 9120: 911e add sp,sp,t2 - 9122: 7f80 flw fs0,56(a5) - 9124: 0a06 slli s4,s4,0x1 - 9126: ffff 0xffff - 9128: 771a flw fa4,164(sp) - 912a: 1e00 addi s0,sp,816 - 912c: 9122 add sp,sp,s0 - 912e: 7f80 flw fs0,56(a5) - 9130: 0a06 slli s4,s4,0x1 - 9132: ffff 0xffff - 9134: 7c1a flw fs8,164(sp) - 9136: 1e00 addi s0,sp,816 - 9138: 2540 fld fs0,136(a0) - 913a: 0a22 slli s4,s4,0x8 - 913c: ffff 0xffff - 913e: 401a 0x401a - 9140: 2224 fld fs1,64(a2) - 9142: 4b40 lw s0,20(a4) - 9144: 2224 fld fs1,64(a2) - 9146: 9f2d 0x9f2d - 9148: 08e8 addi a0,sp,92 - 914a: 0000 unimp - 914c: 0934 addi a3,sp,152 - 914e: 0000 unimp - 9150: 0042 c.slli zero,0x10 - 9152: a891 j 91a6 <_start-0x7fff6e5a> - 9154: 067f 0x67f - 9156: 4b40 lw s0,20(a4) - 9158: 2224 fld fs1,64(a2) - 915a: 7f84 flw fs1,56(a5) - 915c: 8091 srli s1,s1,0x4 - 915e: 067f 0x67f - 9160: 7c1a flw fs8,164(sp) - 9162: 1e00 addi s0,sp,816 - 9164: 7f84 flw fs1,56(a5) - 9166: 911a add sp,sp,t1 - 9168: 7f80 flw fs0,56(a5) - 916a: 4006 0x4006 - 916c: 7c25 lui s8,0xfffe9 - 916e: 1e00 addi s0,sp,816 - 9170: 7f84 flw fs1,56(a5) - 9172: 8091 srli s1,s1,0x4 - 9174: 067f 0x67f - 9176: 771a flw fa4,164(sp) - 9178: 1e00 addi s0,sp,816 - 917a: 8422 mv s0,s0 - 917c: 917f 0x917f - 917e: 7f80 flw fs0,56(a5) - 9180: 1a06 slli s4,s4,0x21 - 9182: 007c addi a5,sp,12 - 9184: 401e 0x401e - 9186: 2225 jal 92ae <_start-0x7fff6d52> - 9188: 7f84 flw fs1,56(a5) - 918a: 401a 0x401a - 918c: 2224 fld fs1,64(a2) - 918e: 4b40 lw s0,20(a4) - 9190: 2224 fld fs1,64(a2) - 9192: 9f2d 0x9f2d - 9194: 0934 addi a3,sp,152 - 9196: 0000 unimp - 9198: 0958 addi a4,sp,148 - 919a: 0000 unimp - 919c: 0042 c.slli zero,0x10 - 919e: a891 j 91f2 <_start-0x7fff6e0e> - 91a0: 067f 0x67f - 91a2: 4b40 lw s0,20(a4) - 91a4: 2224 fld fs1,64(a2) - 91a6: 8091 srli s1,s1,0x4 - 91a8: 067f 0x67f - 91aa: 0084 addi s1,sp,64 - 91ac: 7c1a flw fs8,164(sp) - 91ae: 1e00 addi s0,sp,816 - 91b0: 0084 addi s1,sp,64 - 91b2: 911a add sp,sp,t1 - 91b4: 7f80 flw fs0,56(a5) - 91b6: 4006 0x4006 - 91b8: 7c25 lui s8,0xfffe9 - 91ba: 1e00 addi s0,sp,816 - 91bc: 8091 srli s1,s1,0x4 - 91be: 067f 0x67f - 91c0: 0084 addi s1,sp,64 - 91c2: 771a flw fa4,164(sp) - 91c4: 1e00 addi s0,sp,816 - 91c6: 9122 add sp,sp,s0 - 91c8: 7f80 flw fs0,56(a5) - 91ca: 8406 mv s0,ra - 91cc: 1a00 addi s0,sp,304 - 91ce: 007c addi a5,sp,12 - 91d0: 401e 0x401e - 91d2: 2225 jal 92fa <_start-0x7fff6d06> - 91d4: 0084 addi s1,sp,64 - 91d6: 401a 0x401a - 91d8: 2224 fld fs1,64(a2) - 91da: 4b40 lw s0,20(a4) - 91dc: 2224 fld fs1,64(a2) - 91de: 9f2d 0x9f2d - 91e0: 0958 addi a4,sp,148 - 91e2: 0000 unimp - 91e4: 0998 addi a4,sp,208 - 91e6: 0000 unimp - 91e8: 0042 c.slli zero,0x10 - 91ea: a891 j 923e <_start-0x7fff6dc2> - 91ec: 067f 0x67f - 91ee: 4b40 lw s0,20(a4) - 91f0: 2224 fld fs1,64(a2) - 91f2: 7f85 lui t6,0xfffe1 - 91f4: 8091 srli s1,s1,0x4 - 91f6: 067f 0x67f - 91f8: 7c1a flw fs8,164(sp) - 91fa: 1e00 addi s0,sp,816 - 91fc: 7f85 lui t6,0xfffe1 - 91fe: 911a add sp,sp,t1 - 9200: 7f80 flw fs0,56(a5) - 9202: 4006 0x4006 - 9204: 7c25 lui s8,0xfffe9 - 9206: 1e00 addi s0,sp,816 - 9208: 7f85 lui t6,0xfffe1 - 920a: 8091 srli s1,s1,0x4 - 920c: 067f 0x67f - 920e: 771a flw fa4,164(sp) - 9210: 1e00 addi s0,sp,816 - 9212: 8522 mv a0,s0 - 9214: 917f 0x917f - 9216: 7f80 flw fs0,56(a5) - 9218: 1a06 slli s4,s4,0x21 - 921a: 007c addi a5,sp,12 - 921c: 401e 0x401e - 921e: 2225 jal 9346 <_start-0x7fff6cba> - 9220: 7f85 lui t6,0xfffe1 - 9222: 401a 0x401a - 9224: 2224 fld fs1,64(a2) - 9226: 4b40 lw s0,20(a4) - 9228: 2224 fld fs1,64(a2) - 922a: 9f2d 0x9f2d - 922c: 0998 addi a4,sp,208 - 922e: 0000 unimp - 9230: 09a8 addi a0,sp,216 - 9232: 0000 unimp - 9234: 0051 c.nop 20 - 9236: a891 j 928a <_start-0x7fff6d76> - 9238: 067f 0x67f - 923a: 4b40 lw s0,20(a4) - 923c: 2224 fld fs1,64(a2) - 923e: 7f85 lui t6,0xfffe1 - 9240: f891 bnez s1,9154 <_start-0x7fff6eac> - 9242: 067e slli a2,a2,0x1f - 9244: 851a mv a0,t1 - 9246: 917f 0x917f - 9248: 7f80 flw fs0,56(a5) - 924a: 1a06 slli s4,s4,0x21 - 924c: 851e mv a0,t2 - 924e: 1a7f 0x1a7f - 9250: 7f85 lui t6,0xfffe1 - 9252: f891 bnez s1,9166 <_start-0x7fff6e9a> - 9254: 067e slli a2,a2,0x1f - 9256: 911a add sp,sp,t1 - 9258: 7f80 flw fs0,56(a5) - 925a: 4006 0x4006 - 925c: 1e25 addi t3,t3,-23 - 925e: 7f85 lui t6,0xfffe1 - 9260: 8091 srli s1,s1,0x4 - 9262: 067f 0x67f - 9264: 771a flw fa4,164(sp) - 9266: 1e00 addi s0,sp,816 - 9268: 8522 mv a0,s0 - 926a: 917f 0x917f - 926c: 7ef8 flw fa4,124(a3) - 926e: 1a06 slli s4,s4,0x21 - 9270: 7f85 lui t6,0xfffe1 - 9272: 8091 srli s1,s1,0x4 - 9274: 067f 0x67f - 9276: 1e1a slli t3,t3,0x26 - 9278: 2540 fld fs0,136(a0) - 927a: 8522 mv a0,s0 - 927c: 1a7f 0x1a7f - 927e: 2440 fld fs0,136(s0) - 9280: 4022 0x4022 - 9282: 2d22244b 0x2d22244b - 9286: a89f 0009 e000 0xe0000009a89f - 928c: 0009 c.nop 2 - 928e: 5500 lw s0,40(a0) - 9290: 9100 0x9100 - 9292: 7fa8 flw fa0,120(a5) - 9294: 4006 0x4006 - 9296: 8522244b 0x8522244b - 929a: 917f 0x917f - 929c: 7ef8 flw fa4,124(a3) - 929e: 1a06 slli s4,s4,0x21 - 92a0: 7f85 lui t6,0xfffe1 - 92a2: 8091 srli s1,s1,0x4 - 92a4: 067f 0x67f - 92a6: 1e1a slli t3,t3,0x26 - 92a8: 7f85 lui t6,0xfffe1 - 92aa: 851a mv a0,t1 - 92ac: 917f 0x917f - 92ae: 7ef8 flw fa4,124(a3) - 92b0: 1a06 slli s4,s4,0x21 - 92b2: 8091 srli s1,s1,0x4 - 92b4: 067f 0x67f - 92b6: 2540 fld fs0,136(a0) - 92b8: 851e mv a0,t2 - 92ba: 917f 0x917f - 92bc: 7f80 flw fs0,56(a5) - 92be: 1a06 slli s4,s4,0x21 - 92c0: f891 bnez s1,91d4 <_start-0x7fff6e2c> - 92c2: 067e slli a2,a2,0x1f - 92c4: 2540 fld fs0,136(a0) - 92c6: 221e fld ft4,448(sp) - 92c8: 7f85 lui t6,0xfffe1 - 92ca: f891 bnez s1,91de <_start-0x7fff6e22> - 92cc: 067e slli a2,a2,0x1f - 92ce: 851a mv a0,t1 - 92d0: 917f 0x917f - 92d2: 7f80 flw fs0,56(a5) - 92d4: 1a06 slli s4,s4,0x21 - 92d6: 401e 0x401e - 92d8: 2225 jal 9400 <_start-0x7fff6c00> - 92da: 7f85 lui t6,0xfffe1 - 92dc: 401a 0x401a - 92de: 2224 fld fs1,64(a2) - 92e0: 4b40 lw s0,20(a4) - 92e2: 2224 fld fs1,64(a2) - 92e4: 9f2d 0x9f2d - 92e6: 09e0 addi s0,sp,220 - 92e8: 0000 unimp - 92ea: 09ec addi a1,sp,220 - 92ec: 0000 unimp - 92ee: 0055 c.nop 21 - 92f0: a891 j 9344 <_start-0x7fff6cbc> - 92f2: 067f 0x67f - 92f4: 4b40 lw s0,20(a4) - 92f6: 2224 fld fs1,64(a2) - 92f8: f891 bnez s1,920c <_start-0x7fff6df4> - 92fa: 067e slli a2,a2,0x1f - 92fc: 0079 c.nop 30 - 92fe: 911a add sp,sp,t1 - 9300: 7f80 flw fs0,56(a5) - 9302: 7906 flw fs2,96(sp) - 9304: 1a00 addi s0,sp,304 - 9306: 791e flw fs2,228(sp) - 9308: 1a00 addi s0,sp,304 - 930a: f891 bnez s1,921e <_start-0x7fff6de2> - 930c: 067e slli a2,a2,0x1f - 930e: 0079 c.nop 30 - 9310: 911a add sp,sp,t1 - 9312: 7f80 flw fs0,56(a5) - 9314: 4006 0x4006 - 9316: 1e25 addi t3,t3,-23 - 9318: 8091 srli s1,s1,0x4 - 931a: 067f 0x67f - 931c: 0079 c.nop 30 - 931e: 911a add sp,sp,t1 - 9320: 7ef8 flw fa4,124(a3) - 9322: 4006 0x4006 - 9324: 1e25 addi t3,t3,-23 - 9326: 9122 add sp,sp,s0 - 9328: 7ef8 flw fa4,124(a3) - 932a: 7906 flw fs2,96(sp) - 932c: 1a00 addi s0,sp,304 - 932e: 8091 srli s1,s1,0x4 - 9330: 067f 0x67f - 9332: 0079 c.nop 30 - 9334: 1e1a slli t3,t3,0x26 - 9336: 2540 fld fs0,136(a0) - 9338: 7922 flw fs2,40(sp) - 933a: 1a00 addi s0,sp,304 - 933c: 2440 fld fs0,136(s0) - 933e: 4022 0x4022 - 9340: 2d22244b 0x2d22244b - 9344: ec9f 0009 4800 0x48000009ec9f - 934a: 000a c.slli zero,0x2 - 934c: 5500 lw s0,40(a0) - 934e: 9100 0x9100 - 9350: 7fa8 flw fa0,120(a5) - 9352: 4006 0x4006 - 9354: 8422244b 0x8422244b - 9358: 917f 0x917f - 935a: 7ef8 flw fa4,124(a3) - 935c: 1a06 slli s4,s4,0x21 - 935e: 7f84 flw fs1,56(a5) - 9360: 8091 srli s1,s1,0x4 - 9362: 067f 0x67f - 9364: 1e1a slli t3,t3,0x26 - 9366: 7f84 flw fs1,56(a5) - 9368: 841a mv s0,t1 - 936a: 917f 0x917f - 936c: 7ef8 flw fa4,124(a3) - 936e: 1a06 slli s4,s4,0x21 - 9370: 8091 srli s1,s1,0x4 - 9372: 067f 0x67f - 9374: 2540 fld fs0,136(a0) - 9376: 841e mv s0,t2 - 9378: 917f 0x917f - 937a: 7f80 flw fs0,56(a5) - 937c: 1a06 slli s4,s4,0x21 - 937e: f891 bnez s1,9292 <_start-0x7fff6d6e> - 9380: 067e slli a2,a2,0x1f - 9382: 2540 fld fs0,136(a0) - 9384: 221e fld ft4,448(sp) - 9386: 7f84 flw fs1,56(a5) - 9388: f891 bnez s1,929c <_start-0x7fff6d64> - 938a: 067e slli a2,a2,0x1f - 938c: 841a mv s0,t1 - 938e: 917f 0x917f - 9390: 7f80 flw fs0,56(a5) - 9392: 1a06 slli s4,s4,0x21 - 9394: 401e 0x401e - 9396: 2225 jal 94be <_start-0x7fff6b42> - 9398: 7f84 flw fs1,56(a5) - 939a: 401a 0x401a - 939c: 2224 fld fs1,64(a2) - 939e: 4b40 lw s0,20(a4) - 93a0: 2224 fld fs1,64(a2) - 93a2: 9f2d 0x9f2d - 93a4: 0a48 addi a0,sp,276 - 93a6: 0000 unimp - 93a8: 0ae0 addi s0,sp,348 - 93aa: 0000 unimp - 93ac: 0055 c.nop 21 - 93ae: a891 j 9402 <_start-0x7fff6bfe> - 93b0: 067f 0x67f - 93b2: 4b40 lw s0,20(a4) - 93b4: 2224 fld fs1,64(a2) - 93b6: f891 bnez s1,92ca <_start-0x7fff6d36> - 93b8: 067e slli a2,a2,0x1f - 93ba: 0079 c.nop 30 - 93bc: 911a add sp,sp,t1 - 93be: 7f80 flw fs0,56(a5) - 93c0: 7906 flw fs2,96(sp) - 93c2: 1a00 addi s0,sp,304 - 93c4: 791e flw fs2,228(sp) - 93c6: 1a00 addi s0,sp,304 - 93c8: f891 bnez s1,92dc <_start-0x7fff6d24> - 93ca: 067e slli a2,a2,0x1f - 93cc: 0079 c.nop 30 - 93ce: 911a add sp,sp,t1 - 93d0: 7f80 flw fs0,56(a5) - 93d2: 4006 0x4006 - 93d4: 1e25 addi t3,t3,-23 - 93d6: 8091 srli s1,s1,0x4 - 93d8: 067f 0x67f - 93da: 0079 c.nop 30 - 93dc: 911a add sp,sp,t1 - 93de: 7ef8 flw fa4,124(a3) - 93e0: 4006 0x4006 - 93e2: 1e25 addi t3,t3,-23 - 93e4: 9122 add sp,sp,s0 - 93e6: 7ef8 flw fa4,124(a3) - 93e8: 7906 flw fs2,96(sp) - 93ea: 1a00 addi s0,sp,304 - 93ec: 8091 srli s1,s1,0x4 - 93ee: 067f 0x67f - 93f0: 0079 c.nop 30 - 93f2: 1e1a slli t3,t3,0x26 - 93f4: 2540 fld fs0,136(a0) - 93f6: 7922 flw fs2,40(sp) - 93f8: 1a00 addi s0,sp,304 - 93fa: 2440 fld fs0,136(s0) - 93fc: 4022 0x4022 - 93fe: 2d22244b 0x2d22244b - 9402: e09f 000a 2c00 0x2c00000ae09f - 9408: 5500000b 0x5500000b - 940c: 9100 0x9100 - 940e: 7fa8 flw fa0,120(a5) - 9410: 4006 0x4006 - 9412: 8922244b fnmsub.s fs0,ft4,fs2,fa7,rdn - 9416: 917f 0x917f - 9418: 7ef8 flw fa4,124(a3) - 941a: 1a06 slli s4,s4,0x21 - 941c: 7f89 lui t6,0xfffe2 - 941e: 8091 srli s1,s1,0x4 - 9420: 067f 0x67f - 9422: 1e1a slli t3,t3,0x26 - 9424: 7f89 lui t6,0xfffe2 - 9426: 891a mv s2,t1 - 9428: 917f 0x917f - 942a: 7ef8 flw fa4,124(a3) - 942c: 1a06 slli s4,s4,0x21 - 942e: 8091 srli s1,s1,0x4 - 9430: 067f 0x67f - 9432: 2540 fld fs0,136(a0) - 9434: 891e mv s2,t2 - 9436: 917f 0x917f - 9438: 7f80 flw fs0,56(a5) - 943a: 1a06 slli s4,s4,0x21 - 943c: f891 bnez s1,9350 <_start-0x7fff6cb0> - 943e: 067e slli a2,a2,0x1f - 9440: 2540 fld fs0,136(a0) - 9442: 221e fld ft4,448(sp) - 9444: 7f89 lui t6,0xfffe2 - 9446: f891 bnez s1,935a <_start-0x7fff6ca6> - 9448: 067e slli a2,a2,0x1f - 944a: 891a mv s2,t1 - 944c: 917f 0x917f - 944e: 7f80 flw fs0,56(a5) - 9450: 1a06 slli s4,s4,0x21 - 9452: 401e 0x401e - 9454: 2225 jal 957c <_start-0x7fff6a84> - 9456: 7f89 lui t6,0xfffe2 - 9458: 401a 0x401a - 945a: 2224 fld fs1,64(a2) - 945c: 4b40 lw s0,20(a4) - 945e: 2224 fld fs1,64(a2) - 9460: 9f2d 0x9f2d - 9462: 0b2c addi a1,sp,408 - 9464: 0000 unimp - 9466: 0bc4 addi s1,sp,468 - 9468: 0000 unimp - 946a: 0055 c.nop 21 - 946c: d891 beqz s1,9380 <_start-0x7fff6c80> - 946e: 067e slli a2,a2,0x1f - 9470: 4b40 lw s0,20(a4) - 9472: 2224 fld fs1,64(a2) - 9474: 7f89 lui t6,0xfffe2 - 9476: f891 bnez s1,938a <_start-0x7fff6c76> - 9478: 067e slli a2,a2,0x1f - 947a: 891a mv s2,t1 - 947c: 917f 0x917f - 947e: 7f80 flw fs0,56(a5) - 9480: 1a06 slli s4,s4,0x21 - 9482: 891e mv s2,t2 - 9484: 1a7f 0x1a7f - 9486: 7f89 lui t6,0xfffe2 - 9488: f891 bnez s1,939c <_start-0x7fff6c64> - 948a: 067e slli a2,a2,0x1f - 948c: 911a add sp,sp,t1 - 948e: 7f80 flw fs0,56(a5) - 9490: 4006 0x4006 - 9492: 1e25 addi t3,t3,-23 - 9494: 7f89 lui t6,0xfffe2 - 9496: 8091 srli s1,s1,0x4 - 9498: 067f 0x67f - 949a: 911a add sp,sp,t1 - 949c: 7ef8 flw fa4,124(a3) - 949e: 4006 0x4006 - 94a0: 1e25 addi t3,t3,-23 - 94a2: 8922 mv s2,s0 - 94a4: 917f 0x917f - 94a6: 7ef8 flw fa4,124(a3) - 94a8: 1a06 slli s4,s4,0x21 - 94aa: 7f89 lui t6,0xfffe2 - 94ac: 8091 srli s1,s1,0x4 - 94ae: 067f 0x67f - 94b0: 1e1a slli t3,t3,0x26 - 94b2: 2540 fld fs0,136(a0) - 94b4: 8922 mv s2,s0 - 94b6: 1a7f 0x1a7f - 94b8: 2440 fld fs0,136(s0) - 94ba: 4022 0x4022 - 94bc: 2d22244b 0x2d22244b - 94c0: a89f 000d b400 0xb400000da89f - 94c6: 000d c.nop 3 - 94c8: 5500 lw s0,40(a0) - 94ca: 9100 0x9100 - 94cc: 7ed8 flw fa4,60(a3) - 94ce: 4006 0x4006 - 94d0: 8922244b fnmsub.s fs0,ft4,fs2,fa7,rdn - 94d4: 917f 0x917f - 94d6: 7ef8 flw fa4,124(a3) - 94d8: 1a06 slli s4,s4,0x21 - 94da: 7f89 lui t6,0xfffe2 - 94dc: 8091 srli s1,s1,0x4 - 94de: 067f 0x67f - 94e0: 1e1a slli t3,t3,0x26 - 94e2: 7f89 lui t6,0xfffe2 - 94e4: 891a mv s2,t1 - 94e6: 917f 0x917f - 94e8: 7ef8 flw fa4,124(a3) - 94ea: 1a06 slli s4,s4,0x21 - 94ec: 8091 srli s1,s1,0x4 - 94ee: 067f 0x67f - 94f0: 2540 fld fs0,136(a0) - 94f2: 891e mv s2,t2 - 94f4: 917f 0x917f - 94f6: 7f80 flw fs0,56(a5) - 94f8: 1a06 slli s4,s4,0x21 - 94fa: f891 bnez s1,940e <_start-0x7fff6bf2> - 94fc: 067e slli a2,a2,0x1f - 94fe: 2540 fld fs0,136(a0) - 9500: 221e fld ft4,448(sp) - 9502: 7f89 lui t6,0xfffe2 - 9504: f891 bnez s1,9418 <_start-0x7fff6be8> - 9506: 067e slli a2,a2,0x1f - 9508: 891a mv s2,t1 - 950a: 917f 0x917f - 950c: 7f80 flw fs0,56(a5) - 950e: 1a06 slli s4,s4,0x21 - 9510: 401e 0x401e - 9512: 2225 jal 963a <_start-0x7fff69c6> - 9514: 7f89 lui t6,0xfffe2 - 9516: 401a 0x401a - 9518: 2224 fld fs1,64(a2) - 951a: 4b40 lw s0,20(a4) - 951c: 2224 fld fs1,64(a2) - 951e: 9f2d 0x9f2d - ... - 9528: 06d8 addi a4,sp,836 - 952a: 0000 unimp - 952c: 06e0 addi s0,sp,844 - 952e: 0000 unimp - 9530: 0011 c.nop 4 - 9532: 0075 c.nop 29 - 9534: 4b40 lw s0,20(a4) - 9536: 2224 fld fs1,64(a2) - 9538: 4b400087 vlsseg3bu.v v1,(zero),s4 - 953c: 2224 fld fs1,64(a2) - 953e: 082d addi a6,a6,11 - 9540: 1aff 0x1aff - 9542: e09f 0006 ec00 0xec000006e09f - 9548: 0006 c.slli zero,0x1 - 954a: 1f00 addi s0,sp,944 - 954c: 7500 flw fs0,40(a0) - 954e: 4000 lw s0,0(s0) - 9550: 8722244b fnmsub.q fs0,ft4,fs2,fa6,rdn - 9554: 4000 lw s0,0(s0) - 9556: 2d22244b 0x2d22244b - 955a: 008a slli ra,ra,0x2 - 955c: 4b40 lw s0,20(a4) - 955e: 2224 fld fs1,64(a2) - 9560: 0081 addi ra,ra,0 - 9562: 4b40 lw s0,20(a4) - 9564: 2224 fld fs1,64(a2) - 9566: 212d jal 9990 <_start-0x7fff6670> - 9568: ff08 fsw fa0,56(a4) - 956a: 9f1a add t5,t5,t1 - ... - 9574: 0708 addi a0,sp,896 - 9576: 0000 unimp - 9578: 0744 addi s1,sp,900 - 957a: 0000 unimp - 957c: 0001 nop - 957e: 445f 0007 6000 0x60000007445f - 9584: 0008 0x8 - 9586: 0b00 addi s0,sp,400 - 9588: 9100 0x9100 - 958a: 7ef0 flw fa2,124(a3) - 958c: 8906 mv s2,ra - 958e: 1a00 addi s0,sp,304 - 9590: 0076 c.slli zero,0x1d - 9592: 9f1e add t5,t5,t2 - 9594: 0860 addi s0,sp,28 - 9596: 0000 unimp - 9598: 0894 addi a3,sp,80 - 959a: 0000 unimp - 959c: f091000b 0xf091000b - 95a0: 067e slli a2,a2,0x1f - 95a2: 008c addi a1,sp,64 - 95a4: 761a flw fa2,164(sp) - 95a6: 1e00 addi s0,sp,816 - 95a8: 949f 0008 e000 0xe0000008949f - 95ae: 0008 0x8 - 95b0: 0c00 addi s0,sp,528 - 95b2: 9100 0x9100 - 95b4: 7ef0 flw fa2,124(a3) - 95b6: 0a06 slli s4,s4,0x1 - 95b8: ffff 0xffff - 95ba: 761a flw fa2,164(sp) - 95bc: 1e00 addi s0,sp,816 - 95be: e09f 0008 e400 0xe4000008e09f - 95c4: 0008 0x8 - 95c6: 0b00 addi s0,sp,400 - 95c8: 7a00 flw fs0,48(a2) - 95ca: 917f 0x917f - 95cc: 7ef0 flw fa2,124(a3) - 95ce: 1a06 slli s4,s4,0x21 - 95d0: 0076 c.slli zero,0x1d - 95d2: 9f1e add t5,t5,t2 - 95d4: 08e4 addi s1,sp,92 - 95d6: 0000 unimp - 95d8: 08e8 addi a0,sp,92 - 95da: 0000 unimp - 95dc: 000c 0xc - 95de: f091 bnez s1,94e2 <_start-0x7fff6b1e> - 95e0: 067e slli a2,a2,0x1f - 95e2: ff0a fsw ft2,188(sp) - 95e4: 1aff 0x1aff - 95e6: 0076 c.slli zero,0x1d - 95e8: 9f1e add t5,t5,t2 - 95ea: 08e8 addi a0,sp,92 - 95ec: 0000 unimp - 95ee: 0934 addi a3,sp,152 - 95f0: 0000 unimp - 95f2: 7f84000b 0x7f84000b - 95f6: f091 bnez s1,94fa <_start-0x7fff6b06> - 95f8: 067e slli a2,a2,0x1f - 95fa: 761a flw fa2,164(sp) - 95fc: 1e00 addi s0,sp,816 - 95fe: 349f 0009 5800 0x58000009349f - 9604: 0009 c.nop 2 - 9606: 0b00 addi s0,sp,400 - 9608: 9100 0x9100 - 960a: 7ef0 flw fa2,124(a3) - 960c: 8406 mv s0,ra - 960e: 1a00 addi s0,sp,304 - 9610: 0076 c.slli zero,0x1d - 9612: 9f1e add t5,t5,t2 - 9614: 0958 addi a4,sp,148 - 9616: 0000 unimp - 9618: 09e0 addi s0,sp,220 - 961a: 0000 unimp - 961c: 7f85000b 0x7f85000b - 9620: f091 bnez s1,9524 <_start-0x7fff6adc> - 9622: 067e slli a2,a2,0x1f - 9624: 761a flw fa2,164(sp) - 9626: 1e00 addi s0,sp,816 - 9628: e09f 0009 ec00 0xec000009e09f - 962e: 0009 c.nop 2 - 9630: 0b00 addi s0,sp,400 - 9632: 9100 0x9100 - 9634: 7ef0 flw fa2,124(a3) - 9636: 7906 flw fs2,96(sp) - 9638: 1a00 addi s0,sp,304 - 963a: 0076 c.slli zero,0x1d - 963c: 9f1e add t5,t5,t2 - 963e: 09ec addi a1,sp,220 - 9640: 0000 unimp - 9642: 0a48 addi a0,sp,276 - 9644: 0000 unimp - 9646: 7f84000b 0x7f84000b - 964a: f091 bnez s1,954e <_start-0x7fff6ab2> - 964c: 067e slli a2,a2,0x1f - 964e: 761a flw fa2,164(sp) - 9650: 1e00 addi s0,sp,816 - 9652: 489f 000a b400 0xb400000a489f - 9658: 000a c.slli zero,0x2 - 965a: 0b00 addi s0,sp,400 - 965c: 9100 0x9100 - 965e: 7ef0 flw fa2,124(a3) - 9660: 7906 flw fs2,96(sp) - 9662: 1a00 addi s0,sp,304 - 9664: 0076 c.slli zero,0x1d - 9666: 9f1e add t5,t5,t2 - 9668: 0ab4 addi a3,sp,344 - 966a: 0000 unimp - 966c: 0ae0 addi s0,sp,348 - 966e: 0000 unimp - 9670: 0010 0x10 - 9672: 8c91 sub s1,s1,a2 - 9674: 067f 0x67f - 9676: 0079 c.nop 30 - 9678: 911a add sp,sp,t1 - 967a: 7ef0 flw fa2,124(a3) - 967c: 7906 flw fs2,96(sp) - 967e: 1a00 addi s0,sp,304 - 9680: 9f1e add t5,t5,t2 - 9682: 0ae0 addi s0,sp,348 - 9684: 0000 unimp - 9686: 0bc4 addi s1,sp,468 - 9688: 0000 unimp - 968a: 0010 0x10 - 968c: 7f89 lui t6,0xfffe2 - 968e: 8c91 sub s1,s1,a2 - 9690: 067f 0x67f - 9692: 891a mv s2,t1 - 9694: 917f 0x917f - 9696: 7ef0 flw fa2,124(a3) - 9698: 1a06 slli s4,s4,0x21 - 969a: 9f1e add t5,t5,t2 - 969c: 0da8 addi a0,sp,728 - 969e: 0000 unimp - 96a0: 0db4 addi a3,sp,728 - 96a2: 0000 unimp - 96a4: 0010 0x10 - 96a6: 7f89 lui t6,0xfffe2 - 96a8: 8c91 sub s1,s1,a2 - 96aa: 067f 0x67f - 96ac: 891a mv s2,t1 - 96ae: 917f 0x917f - 96b0: 7ef0 flw fa2,124(a3) - 96b2: 1a06 slli s4,s4,0x21 - 96b4: 9f1e add t5,t5,t2 - ... - 96be: 0708 addi a0,sp,896 - 96c0: 0000 unimp - 96c2: 070c addi a1,sp,896 - 96c4: 0000 unimp - 96c6: 0006 c.slli zero,0x1 - 96c8: 0075 c.nop 29 - 96ca: 007e c.slli zero,0x1f - 96cc: 9f1e add t5,t5,t2 - 96ce: 070c addi a1,sp,896 - 96d0: 0000 unimp - 96d2: 0718 addi a4,sp,896 - 96d4: 0000 unimp - 96d6: 0001 nop - 96d8: 185e slli a6,a6,0x37 - 96da: 20000007 vlseg2bu.v v0,(zero),v0.t - 96de: 0b000007 vlsbu.v v0,(zero),a6 - 96e2: 9100 0x9100 - 96e4: 7ef0 flw fa2,124(a3) - 96e6: 8906 mv s2,ra - 96e8: 1a00 addi s0,sp,304 - 96ea: 0075 c.nop 29 - 96ec: 9f1e add t5,t5,t2 - 96ee: 0720 addi s0,sp,904 - 96f0: 0000 unimp - 96f2: 073c addi a5,sp,904 - 96f4: 0000 unimp - 96f6: 0001 nop - 96f8: 3c61 jal 9190 <_start-0x7fff6e70> - 96fa: 44000007 0x44000007 - 96fe: 1a000007 vlsb.v v0,(zero),zero - 9702: 9100 0x9100 - 9704: 7ef0 flw fa2,124(a3) - 9706: 8906 mv s2,ra - 9708: 1a00 addi s0,sp,304 - 970a: 0075 c.nop 29 - 970c: 911e add sp,sp,t2 - 970e: 7ef0 flw fa2,124(a3) - 9710: 4006 0x4006 - 9712: 7625 lui a2,0xfffe9 - 9714: 1e00 addi s0,sp,816 - 9716: 7f22 flw ft10,40(sp) - 9718: 4000 lw s0,0(s0) - 971a: 2225 jal 9842 <_start-0x7fff67be> - 971c: 449f 0007 6000 0x60000007449f - 9722: 0008 0x8 - 9724: 2200 fld fs0,0(a2) - 9726: 9100 0x9100 - 9728: 7ef0 flw fa2,124(a3) - 972a: 8906 mv s2,ra - 972c: 1a00 addi s0,sp,304 - 972e: 0075 c.nop 29 - 9730: 911e add sp,sp,t2 - 9732: 7ef0 flw fa2,124(a3) - 9734: 4006 0x4006 - 9736: 7625 lui a2,0xfffe9 - 9738: 1e00 addi s0,sp,816 - 973a: 9122 add sp,sp,s0 - 973c: 7ef0 flw fa2,124(a3) - 973e: 8906 mv s2,ra - 9740: 1a00 addi s0,sp,304 - 9742: 0076 c.slli zero,0x1d - 9744: 401e 0x401e - 9746: 2225 jal 986e <_start-0x7fff6792> - 9748: 609f 0008 9400 0x94000008609f - 974e: 0008 0x8 - 9750: 2200 fld fs0,0(a2) - 9752: 9100 0x9100 - 9754: 7ef0 flw fa2,124(a3) - 9756: 8c06 mv s8,ra - 9758: 1a00 addi s0,sp,304 - 975a: 0075 c.nop 29 - 975c: 911e add sp,sp,t2 - 975e: 7ef0 flw fa2,124(a3) - 9760: 4006 0x4006 - 9762: 7625 lui a2,0xfffe9 - 9764: 1e00 addi s0,sp,816 - 9766: 9122 add sp,sp,s0 - 9768: 7ef0 flw fa2,124(a3) - 976a: 8c06 mv s8,ra - 976c: 1a00 addi s0,sp,304 - 976e: 0076 c.slli zero,0x1d - 9770: 401e 0x401e - 9772: 2225 jal 989a <_start-0x7fff6766> - 9774: 949f 0008 e000 0xe0000008949f - 977a: 0008 0x8 - 977c: 2400 fld fs0,8(s0) - 977e: 9100 0x9100 - 9780: 7ef0 flw fa2,124(a3) - 9782: 0a06 slli s4,s4,0x1 - 9784: ffff 0xffff - 9786: 751a flw fa0,164(sp) - 9788: 1e00 addi s0,sp,816 - 978a: f091 bnez s1,968e <_start-0x7fff6972> - 978c: 067e slli a2,a2,0x1f - 978e: 2540 fld fs0,136(a0) - 9790: 0076 c.slli zero,0x1d - 9792: 221e fld ft4,448(sp) - 9794: f091 bnez s1,9698 <_start-0x7fff6968> - 9796: 067e slli a2,a2,0x1f - 9798: ff0a fsw ft2,188(sp) - 979a: 1aff 0x1aff - 979c: 0076 c.slli zero,0x1d - 979e: 401e 0x401e - 97a0: 2225 jal 98c8 <_start-0x7fff6738> - 97a2: e09f 0008 e400 0xe4000008e09f - 97a8: 0008 0x8 - 97aa: 2200 fld fs0,0(a2) - 97ac: 7a00 flw fs0,48(a2) - 97ae: 917f 0x917f - 97b0: 7ef0 flw fa2,124(a3) - 97b2: 1a06 slli s4,s4,0x21 - 97b4: 0075 c.nop 29 - 97b6: 911e add sp,sp,t2 - 97b8: 7ef0 flw fa2,124(a3) - 97ba: 4006 0x4006 - 97bc: 7625 lui a2,0xfffe9 - 97be: 1e00 addi s0,sp,816 - 97c0: 7a22 flw fs4,40(sp) - 97c2: 917f 0x917f - 97c4: 7ef0 flw fa2,124(a3) - 97c6: 1a06 slli s4,s4,0x21 - 97c8: 0076 c.slli zero,0x1d - 97ca: 401e 0x401e - 97cc: 2225 jal 98f4 <_start-0x7fff670c> - 97ce: e49f 0008 e800 0xe8000008e49f - 97d4: 0008 0x8 - 97d6: 2400 fld fs0,8(s0) - 97d8: 9100 0x9100 - 97da: 7ef0 flw fa2,124(a3) - 97dc: 0a06 slli s4,s4,0x1 - 97de: ffff 0xffff - 97e0: 751a flw fa0,164(sp) - 97e2: 1e00 addi s0,sp,816 - 97e4: f091 bnez s1,96e8 <_start-0x7fff6918> - 97e6: 067e slli a2,a2,0x1f - 97e8: 2540 fld fs0,136(a0) - 97ea: 0076 c.slli zero,0x1d - 97ec: 221e fld ft4,448(sp) - 97ee: f091 bnez s1,96f2 <_start-0x7fff690e> - 97f0: 067e slli a2,a2,0x1f - 97f2: ff0a fsw ft2,188(sp) - 97f4: 1aff 0x1aff - 97f6: 0076 c.slli zero,0x1d - 97f8: 401e 0x401e - 97fa: 2225 jal 9922 <_start-0x7fff66de> - 97fc: e89f 0008 3400 0x34000008e89f - 9802: 0009 c.nop 2 - 9804: 2200 fld fs0,0(a2) - 9806: 8400 0x8400 - 9808: 917f 0x917f - 980a: 7ef0 flw fa2,124(a3) - 980c: 1a06 slli s4,s4,0x21 - 980e: 0075 c.nop 29 - 9810: 911e add sp,sp,t2 - 9812: 7ef0 flw fa2,124(a3) - 9814: 4006 0x4006 - 9816: 7625 lui a2,0xfffe9 - 9818: 1e00 addi s0,sp,816 - 981a: 8422 mv s0,s0 - 981c: 917f 0x917f - 981e: 7ef0 flw fa2,124(a3) - 9820: 1a06 slli s4,s4,0x21 - 9822: 0076 c.slli zero,0x1d - 9824: 401e 0x401e - 9826: 2225 jal 994e <_start-0x7fff66b2> - 9828: 349f 0009 5800 0x58000009349f - 982e: 0009 c.nop 2 - 9830: 2200 fld fs0,0(a2) - 9832: 9100 0x9100 - 9834: 7ef0 flw fa2,124(a3) - 9836: 8406 mv s0,ra - 9838: 1a00 addi s0,sp,304 - 983a: 0075 c.nop 29 - 983c: 911e add sp,sp,t2 - 983e: 7ef0 flw fa2,124(a3) - 9840: 4006 0x4006 - 9842: 7625 lui a2,0xfffe9 - 9844: 1e00 addi s0,sp,816 - 9846: 9122 add sp,sp,s0 - 9848: 7ef0 flw fa2,124(a3) - 984a: 8406 mv s0,ra - 984c: 1a00 addi s0,sp,304 - 984e: 0076 c.slli zero,0x1d - 9850: 401e 0x401e - 9852: 2225 jal 997a <_start-0x7fff6686> - 9854: 589f 0009 e000 0xe0000009589f - 985a: 0009 c.nop 2 - 985c: 2200 fld fs0,0(a2) - 985e: 8500 0x8500 - 9860: 917f 0x917f - 9862: 7ef0 flw fa2,124(a3) - 9864: 1a06 slli s4,s4,0x21 - 9866: 0075 c.nop 29 - 9868: 911e add sp,sp,t2 - 986a: 7ef0 flw fa2,124(a3) - 986c: 4006 0x4006 - 986e: 7625 lui a2,0xfffe9 - 9870: 1e00 addi s0,sp,816 - 9872: 8522 mv a0,s0 - 9874: 917f 0x917f - 9876: 7ef0 flw fa2,124(a3) - 9878: 1a06 slli s4,s4,0x21 - 987a: 0076 c.slli zero,0x1d - 987c: 401e 0x401e - 987e: 2225 jal 99a6 <_start-0x7fff665a> - 9880: e09f 0009 ec00 0xec000009e09f - 9886: 0009 c.nop 2 - 9888: 2200 fld fs0,0(a2) - 988a: 9100 0x9100 - 988c: 7ef0 flw fa2,124(a3) - 988e: 7906 flw fs2,96(sp) - 9890: 1a00 addi s0,sp,304 - 9892: 0075 c.nop 29 - 9894: 911e add sp,sp,t2 - 9896: 7ef0 flw fa2,124(a3) - 9898: 4006 0x4006 - 989a: 7625 lui a2,0xfffe9 - 989c: 1e00 addi s0,sp,816 - 989e: 9122 add sp,sp,s0 - 98a0: 7ef0 flw fa2,124(a3) - 98a2: 7906 flw fs2,96(sp) - 98a4: 1a00 addi s0,sp,304 - 98a6: 0076 c.slli zero,0x1d - 98a8: 401e 0x401e - 98aa: 2225 jal 99d2 <_start-0x7fff662e> - 98ac: ec9f 0009 4800 0x48000009ec9f - 98b2: 000a c.slli zero,0x2 - 98b4: 2200 fld fs0,0(a2) - 98b6: 8400 0x8400 - 98b8: 917f 0x917f - 98ba: 7ef0 flw fa2,124(a3) - 98bc: 1a06 slli s4,s4,0x21 - 98be: 0075 c.nop 29 - 98c0: 911e add sp,sp,t2 - 98c2: 7ef0 flw fa2,124(a3) - 98c4: 4006 0x4006 - 98c6: 7625 lui a2,0xfffe9 - 98c8: 1e00 addi s0,sp,816 - 98ca: 8422 mv s0,s0 - 98cc: 917f 0x917f - 98ce: 7ef0 flw fa2,124(a3) - 98d0: 1a06 slli s4,s4,0x21 - 98d2: 0076 c.slli zero,0x1d - 98d4: 401e 0x401e - 98d6: 2225 jal 99fe <_start-0x7fff6602> - 98d8: 489f 000a b400 0xb400000a489f - 98de: 000a c.slli zero,0x2 - 98e0: 2200 fld fs0,0(a2) - 98e2: 9100 0x9100 - 98e4: 7ef0 flw fa2,124(a3) - 98e6: 7906 flw fs2,96(sp) - 98e8: 1a00 addi s0,sp,304 - 98ea: 0075 c.nop 29 - 98ec: 911e add sp,sp,t2 - 98ee: 7ef0 flw fa2,124(a3) - 98f0: 4006 0x4006 - 98f2: 7625 lui a2,0xfffe9 - 98f4: 1e00 addi s0,sp,816 - 98f6: 9122 add sp,sp,s0 - 98f8: 7ef0 flw fa2,124(a3) - 98fa: 7906 flw fs2,96(sp) - 98fc: 1a00 addi s0,sp,304 - 98fe: 0076 c.slli zero,0x1d - 9900: 401e 0x401e - 9902: 2225 jal 9a2a <_start-0x7fff65d6> - 9904: b49f 000a cc00 0xcc00000ab49f - 990a: 000a c.slli zero,0x2 - 990c: 2c00 fld fs0,24(s0) - 990e: 9100 0x9100 - 9910: 7ef0 flw fa2,124(a3) - 9912: 7906 flw fs2,96(sp) - 9914: 1a00 addi s0,sp,304 - 9916: 0075 c.nop 29 - 9918: 911e add sp,sp,t2 - 991a: 7f8c flw fa1,56(a5) - 991c: 7906 flw fs2,96(sp) - 991e: 1a00 addi s0,sp,304 - 9920: f091 bnez s1,9824 <_start-0x7fff67dc> - 9922: 067e slli a2,a2,0x1f - 9924: 2540 fld fs0,136(a0) - 9926: 221e fld ft4,448(sp) - 9928: 8c91 sub s1,s1,a2 - 992a: 067f 0x67f - 992c: 0079 c.nop 30 - 992e: 911a add sp,sp,t1 - 9930: 7ef0 flw fa2,124(a3) - 9932: 7906 flw fs2,96(sp) - 9934: 1a00 addi s0,sp,304 - 9936: 401e 0x401e - 9938: 2225 jal 9a60 <_start-0x7fff65a0> - 993a: cc9f 000a e000 0xe000000acc9f - 9940: 000a c.slli zero,0x2 - 9942: 3000 fld fs0,32(s0) - 9944: 9100 0x9100 - 9946: 7ef0 flw fa2,124(a3) - 9948: 7906 flw fs2,96(sp) - 994a: 1a00 addi s0,sp,304 - 994c: 8c91 sub s1,s1,a2 - 994e: 067f 0x67f - 9950: 2540 fld fs0,136(a0) - 9952: 911e add sp,sp,t2 - 9954: 7f8c flw fa1,56(a5) - 9956: 7906 flw fs2,96(sp) - 9958: 1a00 addi s0,sp,304 - 995a: f091 bnez s1,985e <_start-0x7fff67a2> - 995c: 067e slli a2,a2,0x1f - 995e: 2540 fld fs0,136(a0) - 9960: 221e fld ft4,448(sp) - 9962: 8c91 sub s1,s1,a2 - 9964: 067f 0x67f - 9966: 0079 c.nop 30 - 9968: 911a add sp,sp,t1 - 996a: 7ef0 flw fa2,124(a3) - 996c: 7906 flw fs2,96(sp) - 996e: 1a00 addi s0,sp,304 - 9970: 401e 0x401e - 9972: 2225 jal 9a9a <_start-0x7fff6566> - 9974: e09f 000a c400 0xc400000ae09f - 997a: 3000000b 0x3000000b - 997e: 8900 0x8900 - 9980: 917f 0x917f - 9982: 7ef0 flw fa2,124(a3) - 9984: 1a06 slli s4,s4,0x21 - 9986: 8c91 sub s1,s1,a2 - 9988: 067f 0x67f - 998a: 2540 fld fs0,136(a0) - 998c: 891e mv s2,t2 - 998e: 917f 0x917f - 9990: 7f8c flw fa1,56(a5) - 9992: 1a06 slli s4,s4,0x21 - 9994: f091 bnez s1,9898 <_start-0x7fff6768> - 9996: 067e slli a2,a2,0x1f - 9998: 2540 fld fs0,136(a0) - 999a: 221e fld ft4,448(sp) - 999c: 7f89 lui t6,0xfffe2 - 999e: 8c91 sub s1,s1,a2 - 99a0: 067f 0x67f - 99a2: 891a mv s2,t1 - 99a4: 917f 0x917f - 99a6: 7ef0 flw fa2,124(a3) - 99a8: 1a06 slli s4,s4,0x21 - 99aa: 401e 0x401e - 99ac: 2225 jal 9ad4 <_start-0x7fff652c> - 99ae: a89f 000d b400 0xb400000da89f - 99b4: 000d c.nop 3 - 99b6: 3000 fld fs0,32(s0) - 99b8: 8900 0x8900 - 99ba: 917f 0x917f - 99bc: 7ef0 flw fa2,124(a3) - 99be: 1a06 slli s4,s4,0x21 - 99c0: 8c91 sub s1,s1,a2 - 99c2: 067f 0x67f - 99c4: 2540 fld fs0,136(a0) - 99c6: 891e mv s2,t2 - 99c8: 917f 0x917f - 99ca: 7f8c flw fa1,56(a5) - 99cc: 1a06 slli s4,s4,0x21 - 99ce: f091 bnez s1,98d2 <_start-0x7fff672e> - 99d0: 067e slli a2,a2,0x1f - 99d2: 2540 fld fs0,136(a0) - 99d4: 221e fld ft4,448(sp) - 99d6: 7f89 lui t6,0xfffe2 - 99d8: 8c91 sub s1,s1,a2 - 99da: 067f 0x67f - 99dc: 891a mv s2,t1 - 99de: 917f 0x917f - 99e0: 7ef0 flw fa2,124(a3) - 99e2: 1a06 slli s4,s4,0x21 - 99e4: 401e 0x401e - 99e6: 2225 jal 9b0e <_start-0x7fff64f2> - 99e8: 009f 0000 0000 0x9f - 99ee: 0000 unimp - 99f0: 1400 addi s0,sp,544 - 99f2: 30000007 vlseg2b.v v0,(zero),v0.t - 99f6: 01000007 vlbuff.v v0,(zero),v0.t - 99fa: 5d00 lw s0,56(a0) - 99fc: 0730 addi a2,sp,904 - 99fe: 0000 unimp - 9a00: 0ab4 addi a3,sp,344 - 9a02: 0000 unimp - 9a04: 000a c.slli zero,0x2 - 9a06: f091 bnez s1,990a <_start-0x7fff66f6> - 9a08: 067e slli a2,a2,0x1f - 9a0a: 2540 fld fs0,136(a0) - 9a0c: 0076 c.slli zero,0x1d - 9a0e: 9f1e add t5,t5,t2 - 9a10: 0ab4 addi a3,sp,344 - 9a12: 0000 unimp - 9a14: 0ae0 addi s0,sp,348 - 9a16: 0000 unimp - 9a18: 8c91000f 0x8c91000f - 9a1c: 067f 0x67f - 9a1e: 0079 c.nop 30 - 9a20: 911a add sp,sp,t1 - 9a22: 7ef0 flw fa2,124(a3) - 9a24: 4006 0x4006 - 9a26: 1e25 addi t3,t3,-23 - 9a28: e09f 000a c400 0xc400000ae09f - 9a2e: 0f00000b 0xf00000b - 9a32: 8900 0x8900 - 9a34: 917f 0x917f - 9a36: 7f8c flw fa1,56(a5) - 9a38: 1a06 slli s4,s4,0x21 - 9a3a: f091 bnez s1,993e <_start-0x7fff66c2> - 9a3c: 067e slli a2,a2,0x1f - 9a3e: 2540 fld fs0,136(a0) - 9a40: 9f1e add t5,t5,t2 - 9a42: 0da8 addi a0,sp,728 - 9a44: 0000 unimp - 9a46: 0db4 addi a3,sp,728 - 9a48: 0000 unimp - 9a4a: 7f89000f 0x7f89000f - 9a4e: 8c91 sub s1,s1,a2 - 9a50: 067f 0x67f - 9a52: 911a add sp,sp,t1 - 9a54: 7ef0 flw fa2,124(a3) - 9a56: 4006 0x4006 - 9a58: 1e25 addi t3,t3,-23 - 9a5a: 009f 0000 0000 0x9f - 9a60: 0000 unimp - 9a62: 2000 fld fs0,0(s0) - 9a64: 48000007 vlsseg3bu.v v0,(zero),zero,v0.t - 9a68: 01000007 vlbuff.v v0,(zero),v0.t - 9a6c: 6f00 flw fs0,24(a4) - ... - 9a76: 0708 addi a0,sp,896 - 9a78: 0000 unimp - 9a7a: 0bc4 addi s1,sp,468 - 9a7c: 0000 unimp - 9a7e: f0910003 lb zero,-247(sp) - 9a82: a87e fsd ft11,16(sp) - 9a84: 000d c.nop 3 - 9a86: b400 fsd fs0,40(s0) - 9a88: 000d c.nop 3 - 9a8a: 0300 addi s0,sp,384 - 9a8c: 9100 0x9100 - 9a8e: 7ef0 flw fa2,124(a3) - ... - 9a98: 0708 addi a0,sp,896 - 9a9a: 0000 unimp - 9a9c: 0720 addi s0,sp,904 - 9a9e: 0000 unimp - 9aa0: 0001 nop - 9aa2: 0007206f j 7baa2 <_start-0x7ff8455e> - 9aa6: c400 sw s0,8(s0) - 9aa8: 0300000b 0x300000b - 9aac: 9100 0x9100 - 9aae: 7ef2 flw ft9,60(sp) - 9ab0: 0da8 addi a0,sp,728 - 9ab2: 0000 unimp - 9ab4: 0db4 addi a3,sp,728 - 9ab6: 0000 unimp - 9ab8: f2910003 lb zero,-215(sp) - 9abc: 007e c.slli zero,0x1f - 9abe: 0000 unimp - 9ac0: 0000 unimp - 9ac2: 0000 unimp - 9ac4: 0800 addi s0,sp,16 - 9ac6: cc000007 vlxseg7bu.v v0,(zero),v0,v0.t - 9aca: 000a c.slli zero,0x2 - 9acc: 0100 addi s0,sp,128 - 9ace: 5500 lw s0,40(a0) - 9ad0: 0acc addi a1,sp,340 - 9ad2: 0000 unimp - 9ad4: 0bc4 addi s1,sp,468 - 9ad6: 0000 unimp - 9ad8: 8e910003 lb zero,-1815(sp) - 9adc: a87f 0xa87f - 9ade: 000d c.nop 3 - 9ae0: b400 fsd fs0,40(s0) - 9ae2: 000d c.nop 3 - 9ae4: 0300 addi s0,sp,384 - 9ae6: 9100 0x9100 - 9ae8: 7f8e flw ft11,224(sp) - ... - 9af2: 0760 addi s0,sp,908 - 9af4: 0000 unimp - 9af6: 0798 addi a4,sp,960 - 9af8: 0000 unimp - 9afa: 0001 nop - 9afc: 985f 0007 6000 0x60000007985f - 9b02: 0008 0x8 - 9b04: 0b00 addi s0,sp,400 - 9b06: 9100 0x9100 - 9b08: 7f80 flw fs0,56(a5) - 9b0a: 8906 mv s2,ra - 9b0c: 1a00 addi s0,sp,304 - 9b0e: 9f1e0083 lb ra,-1551(t3) - 9b12: 0860 addi s0,sp,28 - 9b14: 0000 unimp - 9b16: 0894 addi a3,sp,80 - 9b18: 0000 unimp - 9b1a: 8091000b 0x8091000b - 9b1e: 067f 0x67f - 9b20: 008c addi a1,sp,64 - 9b22: 831a mv t1,t1 - 9b24: 1e00 addi s0,sp,816 - 9b26: 949f 0008 e000 0xe0000008949f - 9b2c: 0008 0x8 - 9b2e: 0c00 addi s0,sp,528 - 9b30: 9100 0x9100 - 9b32: 7f80 flw fs0,56(a5) - 9b34: 0a06 slli s4,s4,0x1 - 9b36: ffff 0xffff - 9b38: 831a mv t1,t1 - 9b3a: 1e00 addi s0,sp,816 - 9b3c: e09f 0008 e400 0xe4000008e09f - 9b42: 0008 0x8 - 9b44: 0b00 addi s0,sp,400 - 9b46: 7a00 flw fs0,48(a2) - 9b48: 917f 0x917f - 9b4a: 7f80 flw fs0,56(a5) - 9b4c: 1a06 slli s4,s4,0x21 - 9b4e: 9f1e0083 lb ra,-1551(t3) - 9b52: 08e4 addi s1,sp,92 - 9b54: 0000 unimp - 9b56: 08e8 addi a0,sp,92 - 9b58: 0000 unimp - 9b5a: 000c 0xc - 9b5c: 8091 srli s1,s1,0x4 - 9b5e: 067f 0x67f - 9b60: ff0a fsw ft2,188(sp) - 9b62: 1aff 0x1aff - 9b64: 9f1e0083 lb ra,-1551(t3) - 9b68: 08e8 addi a0,sp,92 - 9b6a: 0000 unimp - 9b6c: 0934 addi a3,sp,152 - 9b6e: 0000 unimp - 9b70: 7f84000b 0x7f84000b - 9b74: 8091 srli s1,s1,0x4 - 9b76: 067f 0x67f - 9b78: 831a mv t1,t1 - 9b7a: 1e00 addi s0,sp,816 - 9b7c: 349f 0009 5800 0x58000009349f - 9b82: 0009 c.nop 2 - 9b84: 0b00 addi s0,sp,400 - 9b86: 9100 0x9100 - 9b88: 7f80 flw fs0,56(a5) - 9b8a: 8406 mv s0,ra - 9b8c: 1a00 addi s0,sp,304 - 9b8e: 9f1e0083 lb ra,-1551(t3) - 9b92: 0958 addi a4,sp,148 - 9b94: 0000 unimp - 9b96: 09e0 addi s0,sp,220 - 9b98: 0000 unimp - 9b9a: 7f85000b 0x7f85000b - 9b9e: 8091 srli s1,s1,0x4 - 9ba0: 067f 0x67f - 9ba2: 831a mv t1,t1 - 9ba4: 1e00 addi s0,sp,816 - 9ba6: e09f 0009 ec00 0xec000009e09f - 9bac: 0009 c.nop 2 - 9bae: 0b00 addi s0,sp,400 - 9bb0: 9100 0x9100 - 9bb2: 7f80 flw fs0,56(a5) - 9bb4: 7906 flw fs2,96(sp) - 9bb6: 1a00 addi s0,sp,304 - 9bb8: 9f1e0083 lb ra,-1551(t3) - 9bbc: 09ec addi a1,sp,220 - 9bbe: 0000 unimp - 9bc0: 0a48 addi a0,sp,276 - 9bc2: 0000 unimp - 9bc4: 7f84000b 0x7f84000b - 9bc8: 8091 srli s1,s1,0x4 - 9bca: 067f 0x67f - 9bcc: 831a mv t1,t1 - 9bce: 1e00 addi s0,sp,816 - 9bd0: 489f 000a c000 0xc000000a489f - 9bd6: 000a c.slli zero,0x2 - 9bd8: 0b00 addi s0,sp,400 - 9bda: 9100 0x9100 - 9bdc: 7f80 flw fs0,56(a5) - 9bde: 7906 flw fs2,96(sp) - 9be0: 1a00 addi s0,sp,304 - 9be2: 9f1e0083 lb ra,-1551(t3) - 9be6: 0ac0 addi s0,sp,340 - 9be8: 0000 unimp - 9bea: 0ae0 addi s0,sp,348 - 9bec: 0000 unimp - 9bee: 0010 0x10 - 9bf0: 8091 srli s1,s1,0x4 - 9bf2: 067f 0x67f - 9bf4: 0079 c.nop 30 - 9bf6: 911a add sp,sp,t1 - 9bf8: 7efc flw fa5,124(a3) - 9bfa: 7906 flw fs2,96(sp) - 9bfc: 1a00 addi s0,sp,304 - 9bfe: 9f1e add t5,t5,t2 - 9c00: 0ae0 addi s0,sp,348 - 9c02: 0000 unimp - 9c04: 0bc4 addi s1,sp,468 - 9c06: 0000 unimp - 9c08: 0010 0x10 - 9c0a: 7f89 lui t6,0xfffe2 - 9c0c: 8091 srli s1,s1,0x4 - 9c0e: 067f 0x67f - 9c10: 891a mv s2,t1 - 9c12: 917f 0x917f - 9c14: 7efc flw fa5,124(a3) - 9c16: 1a06 slli s4,s4,0x21 - 9c18: 9f1e add t5,t5,t2 - 9c1a: 0da8 addi a0,sp,728 - 9c1c: 0000 unimp - 9c1e: 0db4 addi a3,sp,728 - 9c20: 0000 unimp - 9c22: 0010 0x10 - 9c24: 7f89 lui t6,0xfffe2 - 9c26: 8091 srli s1,s1,0x4 - 9c28: 067f 0x67f - 9c2a: 891a mv s2,t1 - 9c2c: 917f 0x917f - 9c2e: 7efc flw fa5,124(a3) - 9c30: 1a06 slli s4,s4,0x21 - 9c32: 9f1e add t5,t5,t2 - ... - 9c3c: 0760 addi s0,sp,908 - 9c3e: 0000 unimp - 9c40: 0764 addi s1,sp,908 - 9c42: 0000 unimp - 9c44: 0006 c.slli zero,0x1 - 9c46: 0085 addi ra,ra,1 - 9c48: 9f1e0083 lb ra,-1551(t3) - 9c4c: 0764 addi s1,sp,908 - 9c4e: 0000 unimp - 9c50: 0770 addi a2,sp,908 - 9c52: 0000 unimp - 9c54: 0001 nop - 9c56: 7465 lui s0,0xffff9 - 9c58: 04000007 0x4000007 - 9c5c: 0008 0x8 - 9c5e: 0100 addi s0,sp,128 - 9c60: 6500 flw fs0,8(a0) - 9c62: 0804 addi s1,sp,16 - 9c64: 0000 unimp - 9c66: 0860 addi s0,sp,28 - 9c68: 0000 unimp - 9c6a: 0022 c.slli zero,0x8 - 9c6c: 8091 srli s1,s1,0x4 - 9c6e: 067f 0x67f - 9c70: 2540 fld fs0,136(a0) - 9c72: 911e0083 lb ra,-1775(t3) - 9c76: 7f80 flw fs0,56(a5) - 9c78: 8906 mv s2,ra - 9c7a: 1a00 addi s0,sp,304 - 9c7c: 221e008f 0x221e008f - 9c80: 8091 srli s1,s1,0x4 - 9c82: 067f 0x67f - 9c84: 0089 addi ra,ra,2 - 9c86: 831a mv t1,t1 - 9c88: 1e00 addi s0,sp,816 - 9c8a: 2540 fld fs0,136(a0) - 9c8c: 9f22 add t5,t5,s0 - 9c8e: 0860 addi s0,sp,28 - 9c90: 0000 unimp - 9c92: 0894 addi a3,sp,80 - 9c94: 0000 unimp - 9c96: 0022 c.slli zero,0x8 - 9c98: 8091 srli s1,s1,0x4 - 9c9a: 067f 0x67f - 9c9c: 2540 fld fs0,136(a0) - 9c9e: 911e0083 lb ra,-1775(t3) - 9ca2: 7f80 flw fs0,56(a5) - 9ca4: 8c06 mv s8,ra - 9ca6: 1a00 addi s0,sp,304 - 9ca8: 221e008f 0x221e008f - 9cac: 8091 srli s1,s1,0x4 - 9cae: 067f 0x67f - 9cb0: 008c addi a1,sp,64 - 9cb2: 831a mv t1,t1 - 9cb4: 1e00 addi s0,sp,816 - 9cb6: 2540 fld fs0,136(a0) - 9cb8: 9f22 add t5,t5,s0 - 9cba: 0894 addi a3,sp,80 - 9cbc: 0000 unimp - 9cbe: 08e0 addi s0,sp,92 - 9cc0: 0000 unimp - 9cc2: 0024 addi s1,sp,8 - 9cc4: 8091 srli s1,s1,0x4 - 9cc6: 067f 0x67f - 9cc8: 2540 fld fs0,136(a0) - 9cca: 911e0083 lb ra,-1775(t3) - 9cce: 7f80 flw fs0,56(a5) - 9cd0: 0a06 slli s4,s4,0x1 - 9cd2: ffff 0xffff - 9cd4: 8f1a mv t5,t1 - 9cd6: 1e00 addi s0,sp,816 - 9cd8: 9122 add sp,sp,s0 - 9cda: 7f80 flw fs0,56(a5) - 9cdc: 0a06 slli s4,s4,0x1 - 9cde: ffff 0xffff - 9ce0: 831a mv t1,t1 - 9ce2: 1e00 addi s0,sp,816 - 9ce4: 2540 fld fs0,136(a0) - 9ce6: 9f22 add t5,t5,s0 - 9ce8: 08e0 addi s0,sp,92 - 9cea: 0000 unimp - 9cec: 08e4 addi s1,sp,92 - 9cee: 0000 unimp - 9cf0: 0022 c.slli zero,0x8 - 9cf2: 8091 srli s1,s1,0x4 - 9cf4: 067f 0x67f - 9cf6: 2540 fld fs0,136(a0) - 9cf8: 7a1e0083 lb ra,1953(t3) - 9cfc: 917f 0x917f - 9cfe: 7f80 flw fs0,56(a5) - 9d00: 1a06 slli s4,s4,0x21 - 9d02: 221e008f 0x221e008f - 9d06: 7f7a flw ft10,188(sp) - 9d08: 8091 srli s1,s1,0x4 - 9d0a: 067f 0x67f - 9d0c: 831a mv t1,t1 - 9d0e: 1e00 addi s0,sp,816 - 9d10: 2540 fld fs0,136(a0) - 9d12: 9f22 add t5,t5,s0 - 9d14: 08e4 addi s1,sp,92 - 9d16: 0000 unimp - 9d18: 08e8 addi a0,sp,92 - 9d1a: 0000 unimp - 9d1c: 0024 addi s1,sp,8 - 9d1e: 8091 srli s1,s1,0x4 - 9d20: 067f 0x67f - 9d22: 2540 fld fs0,136(a0) - 9d24: 911e0083 lb ra,-1775(t3) - 9d28: 7f80 flw fs0,56(a5) - 9d2a: 0a06 slli s4,s4,0x1 - 9d2c: ffff 0xffff - 9d2e: 8f1a mv t5,t1 - 9d30: 1e00 addi s0,sp,816 - 9d32: 9122 add sp,sp,s0 - 9d34: 7f80 flw fs0,56(a5) - 9d36: 0a06 slli s4,s4,0x1 - 9d38: ffff 0xffff - 9d3a: 831a mv t1,t1 - 9d3c: 1e00 addi s0,sp,816 - 9d3e: 2540 fld fs0,136(a0) - 9d40: 9f22 add t5,t5,s0 - 9d42: 08e8 addi a0,sp,92 - 9d44: 0000 unimp - 9d46: 0934 addi a3,sp,152 - 9d48: 0000 unimp - 9d4a: 0022 c.slli zero,0x8 - 9d4c: 8091 srli s1,s1,0x4 - 9d4e: 067f 0x67f - 9d50: 2540 fld fs0,136(a0) - 9d52: 841e0083 lb ra,-1983(t3) - 9d56: 917f 0x917f - 9d58: 7f80 flw fs0,56(a5) - 9d5a: 1a06 slli s4,s4,0x21 - 9d5c: 221e008f 0x221e008f - 9d60: 7f84 flw fs1,56(a5) - 9d62: 8091 srli s1,s1,0x4 - 9d64: 067f 0x67f - 9d66: 831a mv t1,t1 - 9d68: 1e00 addi s0,sp,816 - 9d6a: 2540 fld fs0,136(a0) - 9d6c: 9f22 add t5,t5,s0 - 9d6e: 0934 addi a3,sp,152 - 9d70: 0000 unimp - 9d72: 0958 addi a4,sp,148 - 9d74: 0000 unimp - 9d76: 0022 c.slli zero,0x8 - 9d78: 8091 srli s1,s1,0x4 - 9d7a: 067f 0x67f - 9d7c: 2540 fld fs0,136(a0) - 9d7e: 911e0083 lb ra,-1775(t3) - 9d82: 7f80 flw fs0,56(a5) - 9d84: 8406 mv s0,ra - 9d86: 1a00 addi s0,sp,304 - 9d88: 221e008f 0x221e008f - 9d8c: 8091 srli s1,s1,0x4 - 9d8e: 067f 0x67f - 9d90: 0084 addi s1,sp,64 - 9d92: 831a mv t1,t1 - 9d94: 1e00 addi s0,sp,816 - 9d96: 2540 fld fs0,136(a0) - 9d98: 9f22 add t5,t5,s0 - 9d9a: 0958 addi a4,sp,148 - 9d9c: 0000 unimp - 9d9e: 09e0 addi s0,sp,220 - 9da0: 0000 unimp - 9da2: 0022 c.slli zero,0x8 - 9da4: 8091 srli s1,s1,0x4 - 9da6: 067f 0x67f - 9da8: 2540 fld fs0,136(a0) - 9daa: 851e0083 lb ra,-1967(t3) - 9dae: 917f 0x917f - 9db0: 7f80 flw fs0,56(a5) - 9db2: 1a06 slli s4,s4,0x21 - 9db4: 221e008f 0x221e008f - 9db8: 7f85 lui t6,0xfffe1 - 9dba: 8091 srli s1,s1,0x4 - 9dbc: 067f 0x67f - 9dbe: 831a mv t1,t1 - 9dc0: 1e00 addi s0,sp,816 - 9dc2: 2540 fld fs0,136(a0) - 9dc4: 9f22 add t5,t5,s0 - 9dc6: 09e0 addi s0,sp,220 - 9dc8: 0000 unimp - 9dca: 09ec addi a1,sp,220 - 9dcc: 0000 unimp - 9dce: 0022 c.slli zero,0x8 - 9dd0: 8091 srli s1,s1,0x4 - 9dd2: 067f 0x67f - 9dd4: 2540 fld fs0,136(a0) - 9dd6: 911e0083 lb ra,-1775(t3) - 9dda: 7f80 flw fs0,56(a5) - 9ddc: 7906 flw fs2,96(sp) - 9dde: 1a00 addi s0,sp,304 - 9de0: 221e008f 0x221e008f - 9de4: 8091 srli s1,s1,0x4 - 9de6: 067f 0x67f - 9de8: 0079 c.nop 30 - 9dea: 831a mv t1,t1 - 9dec: 1e00 addi s0,sp,816 - 9dee: 2540 fld fs0,136(a0) - 9df0: 9f22 add t5,t5,s0 - 9df2: 09ec addi a1,sp,220 - 9df4: 0000 unimp - 9df6: 0a48 addi a0,sp,276 - 9df8: 0000 unimp - 9dfa: 0022 c.slli zero,0x8 - 9dfc: 8091 srli s1,s1,0x4 - 9dfe: 067f 0x67f - 9e00: 2540 fld fs0,136(a0) - 9e02: 841e0083 lb ra,-1983(t3) - 9e06: 917f 0x917f - 9e08: 7f80 flw fs0,56(a5) - 9e0a: 1a06 slli s4,s4,0x21 - 9e0c: 221e008f 0x221e008f - 9e10: 7f84 flw fs1,56(a5) - 9e12: 8091 srli s1,s1,0x4 - 9e14: 067f 0x67f - 9e16: 831a mv t1,t1 - 9e18: 1e00 addi s0,sp,816 - 9e1a: 2540 fld fs0,136(a0) - 9e1c: 9f22 add t5,t5,s0 - 9e1e: 0a48 addi a0,sp,276 - 9e20: 0000 unimp - 9e22: 0ac0 addi s0,sp,340 - 9e24: 0000 unimp - 9e26: 0022 c.slli zero,0x8 - 9e28: 8091 srli s1,s1,0x4 - 9e2a: 067f 0x67f - 9e2c: 2540 fld fs0,136(a0) - 9e2e: 911e0083 lb ra,-1775(t3) - 9e32: 7f80 flw fs0,56(a5) - 9e34: 7906 flw fs2,96(sp) - 9e36: 1a00 addi s0,sp,304 - 9e38: 221e008f 0x221e008f - 9e3c: 8091 srli s1,s1,0x4 - 9e3e: 067f 0x67f - 9e40: 0079 c.nop 30 - 9e42: 831a mv t1,t1 - 9e44: 1e00 addi s0,sp,816 - 9e46: 2540 fld fs0,136(a0) - 9e48: 9f22 add t5,t5,s0 - 9e4a: 0ac0 addi s0,sp,340 - 9e4c: 0000 unimp - 9e4e: 0ac8 addi a0,sp,340 - 9e50: 0000 unimp - 9e52: 002c addi a1,sp,8 - 9e54: fc91 bnez s1,9d70 <_start-0x7fff6290> - 9e56: 067e slli a2,a2,0x1f - 9e58: 0079 c.nop 30 - 9e5a: 911a add sp,sp,t1 - 9e5c: 7f80 flw fs0,56(a5) - 9e5e: 4006 0x4006 - 9e60: 1e25 addi t3,t3,-23 - 9e62: 8091 srli s1,s1,0x4 - 9e64: 067f 0x67f - 9e66: 0079 c.nop 30 - 9e68: 8f1a mv t5,t1 - 9e6a: 1e00 addi s0,sp,816 - 9e6c: 9122 add sp,sp,s0 - 9e6e: 7f80 flw fs0,56(a5) - 9e70: 7906 flw fs2,96(sp) - 9e72: 1a00 addi s0,sp,304 - 9e74: fc91 bnez s1,9d90 <_start-0x7fff6270> - 9e76: 067e slli a2,a2,0x1f - 9e78: 0079 c.nop 30 - 9e7a: 1e1a slli t3,t3,0x26 - 9e7c: 2540 fld fs0,136(a0) - 9e7e: 9f22 add t5,t5,s0 - 9e80: 0ac8 addi a0,sp,340 - 9e82: 0000 unimp - 9e84: 0ae0 addi s0,sp,348 - 9e86: 0000 unimp - 9e88: 0030 addi a2,sp,8 - 9e8a: fc91 bnez s1,9da6 <_start-0x7fff625a> - 9e8c: 067e slli a2,a2,0x1f - 9e8e: 0079 c.nop 30 - 9e90: 911a add sp,sp,t1 - 9e92: 7f80 flw fs0,56(a5) - 9e94: 4006 0x4006 - 9e96: 1e25 addi t3,t3,-23 - 9e98: 8091 srli s1,s1,0x4 - 9e9a: 067f 0x67f - 9e9c: 0079 c.nop 30 - 9e9e: 911a add sp,sp,t1 - 9ea0: 7efc flw fa5,124(a3) - 9ea2: 4006 0x4006 - 9ea4: 1e25 addi t3,t3,-23 - 9ea6: 9122 add sp,sp,s0 - 9ea8: 7f80 flw fs0,56(a5) - 9eaa: 7906 flw fs2,96(sp) - 9eac: 1a00 addi s0,sp,304 - 9eae: fc91 bnez s1,9dca <_start-0x7fff6236> - 9eb0: 067e slli a2,a2,0x1f - 9eb2: 0079 c.nop 30 - 9eb4: 1e1a slli t3,t3,0x26 - 9eb6: 2540 fld fs0,136(a0) - 9eb8: 9f22 add t5,t5,s0 - 9eba: 0ae0 addi s0,sp,348 - 9ebc: 0000 unimp - 9ebe: 0bc4 addi s1,sp,468 - 9ec0: 0000 unimp - 9ec2: 0030 addi a2,sp,8 - 9ec4: 7f89 lui t6,0xfffe2 - 9ec6: fc91 bnez s1,9de2 <_start-0x7fff621e> - 9ec8: 067e slli a2,a2,0x1f - 9eca: 911a add sp,sp,t1 - 9ecc: 7f80 flw fs0,56(a5) - 9ece: 4006 0x4006 - 9ed0: 1e25 addi t3,t3,-23 - 9ed2: 7f89 lui t6,0xfffe2 - 9ed4: 8091 srli s1,s1,0x4 - 9ed6: 067f 0x67f - 9ed8: 911a add sp,sp,t1 - 9eda: 7efc flw fa5,124(a3) - 9edc: 4006 0x4006 - 9ede: 1e25 addi t3,t3,-23 - 9ee0: 8922 mv s2,s0 - 9ee2: 917f 0x917f - 9ee4: 7f80 flw fs0,56(a5) - 9ee6: 1a06 slli s4,s4,0x21 - 9ee8: 7f89 lui t6,0xfffe2 - 9eea: fc91 bnez s1,9e06 <_start-0x7fff61fa> - 9eec: 067e slli a2,a2,0x1f - 9eee: 1e1a slli t3,t3,0x26 - 9ef0: 2540 fld fs0,136(a0) - 9ef2: 9f22 add t5,t5,s0 - 9ef4: 0da8 addi a0,sp,728 - 9ef6: 0000 unimp - 9ef8: 0db4 addi a3,sp,728 - 9efa: 0000 unimp - 9efc: 0030 addi a2,sp,8 - 9efe: 7f89 lui t6,0xfffe2 - 9f00: fc91 bnez s1,9e1c <_start-0x7fff61e4> - 9f02: 067e slli a2,a2,0x1f - 9f04: 911a add sp,sp,t1 - 9f06: 7f80 flw fs0,56(a5) - 9f08: 4006 0x4006 - 9f0a: 1e25 addi t3,t3,-23 - 9f0c: 7f89 lui t6,0xfffe2 - 9f0e: 8091 srli s1,s1,0x4 - 9f10: 067f 0x67f - 9f12: 911a add sp,sp,t1 - 9f14: 7efc flw fa5,124(a3) - 9f16: 4006 0x4006 - 9f18: 1e25 addi t3,t3,-23 - 9f1a: 8922 mv s2,s0 - 9f1c: 917f 0x917f - 9f1e: 7f80 flw fs0,56(a5) - 9f20: 1a06 slli s4,s4,0x21 - 9f22: 7f89 lui t6,0xfffe2 - 9f24: fc91 bnez s1,9e40 <_start-0x7fff61c0> - 9f26: 067e slli a2,a2,0x1f - 9f28: 1e1a slli t3,t3,0x26 - 9f2a: 2540 fld fs0,136(a0) - 9f2c: 9f22 add t5,t5,s0 - ... - 9f36: 076c addi a1,sp,908 - 9f38: 0000 unimp - 9f3a: 07a8 addi a0,sp,968 - 9f3c: 0000 unimp - 9f3e: 0001 nop - 9f40: a86c fsd fa1,208(s0) - 9f42: 60000007 vlseg4bu.v v0,(zero),v0.t - 9f46: 0008 0x8 - 9f48: 0b00 addi s0,sp,400 - 9f4a: 9100 0x9100 - 9f4c: 7f80 flw fs0,56(a5) - 9f4e: 8906 mv s2,ra - 9f50: 1a00 addi s0,sp,304 - 9f52: 9f1e008f 0x9f1e008f - 9f56: 0860 addi s0,sp,28 - 9f58: 0000 unimp - 9f5a: 0894 addi a3,sp,80 - 9f5c: 0000 unimp - 9f5e: 8091000b 0x8091000b - 9f62: 067f 0x67f - 9f64: 008c addi a1,sp,64 - 9f66: 8f1a mv t5,t1 - 9f68: 1e00 addi s0,sp,816 - 9f6a: 949f 0008 e000 0xe0000008949f - 9f70: 0008 0x8 - 9f72: 0c00 addi s0,sp,528 - 9f74: 9100 0x9100 - 9f76: 7f80 flw fs0,56(a5) - 9f78: 0a06 slli s4,s4,0x1 - 9f7a: ffff 0xffff - 9f7c: 8f1a mv t5,t1 - 9f7e: 1e00 addi s0,sp,816 - 9f80: e09f 0008 e400 0xe4000008e09f - 9f86: 0008 0x8 - 9f88: 0b00 addi s0,sp,400 - 9f8a: 7a00 flw fs0,48(a2) - 9f8c: 917f 0x917f - 9f8e: 7f80 flw fs0,56(a5) - 9f90: 1a06 slli s4,s4,0x21 - 9f92: 9f1e008f 0x9f1e008f - 9f96: 08e4 addi s1,sp,92 - 9f98: 0000 unimp - 9f9a: 08e8 addi a0,sp,92 - 9f9c: 0000 unimp - 9f9e: 000c 0xc - 9fa0: 8091 srli s1,s1,0x4 - 9fa2: 067f 0x67f - 9fa4: ff0a fsw ft2,188(sp) - 9fa6: 1aff 0x1aff - 9fa8: 9f1e008f 0x9f1e008f - 9fac: 08e8 addi a0,sp,92 - 9fae: 0000 unimp - 9fb0: 0934 addi a3,sp,152 - 9fb2: 0000 unimp - 9fb4: 7f84000b 0x7f84000b - 9fb8: 8091 srli s1,s1,0x4 - 9fba: 067f 0x67f - 9fbc: 8f1a mv t5,t1 - 9fbe: 1e00 addi s0,sp,816 - 9fc0: 349f 0009 5800 0x58000009349f - 9fc6: 0009 c.nop 2 - 9fc8: 0b00 addi s0,sp,400 - 9fca: 9100 0x9100 - 9fcc: 7f80 flw fs0,56(a5) - 9fce: 8406 mv s0,ra - 9fd0: 1a00 addi s0,sp,304 - 9fd2: 9f1e008f 0x9f1e008f - 9fd6: 0958 addi a4,sp,148 - 9fd8: 0000 unimp - 9fda: 09e0 addi s0,sp,220 - 9fdc: 0000 unimp - 9fde: 7f85000b 0x7f85000b - 9fe2: 8091 srli s1,s1,0x4 - 9fe4: 067f 0x67f - 9fe6: 8f1a mv t5,t1 - 9fe8: 1e00 addi s0,sp,816 - 9fea: e09f 0009 ec00 0xec000009e09f - 9ff0: 0009 c.nop 2 - 9ff2: 0b00 addi s0,sp,400 - 9ff4: 9100 0x9100 - 9ff6: 7f80 flw fs0,56(a5) - 9ff8: 7906 flw fs2,96(sp) - 9ffa: 1a00 addi s0,sp,304 - 9ffc: 9f1e008f 0x9f1e008f - a000: 09ec addi a1,sp,220 - a002: 0000 unimp - a004: 0a48 addi a0,sp,276 - a006: 0000 unimp - a008: 7f84000b 0x7f84000b - a00c: 8091 srli s1,s1,0x4 - a00e: 067f 0x67f - a010: 8f1a mv t5,t1 - a012: 1e00 addi s0,sp,816 - a014: 489f 000a c800 0xc800000a489f - a01a: 000a c.slli zero,0x2 - a01c: 0b00 addi s0,sp,400 - a01e: 9100 0x9100 - a020: 7f80 flw fs0,56(a5) - a022: 7906 flw fs2,96(sp) - a024: 1a00 addi s0,sp,304 - a026: 9f1e008f 0x9f1e008f - a02a: 0ac8 addi a0,sp,340 - a02c: 0000 unimp - a02e: 0ae0 addi s0,sp,348 - a030: 0000 unimp - a032: 8091000f 0x8091000f - a036: 067f 0x67f - a038: 0079 c.nop 30 - a03a: 911a add sp,sp,t1 - a03c: 7efc flw fa5,124(a3) - a03e: 4006 0x4006 - a040: 1e25 addi t3,t3,-23 - a042: e09f 000a c400 0xc400000ae09f - a048: 0f00000b 0xf00000b - a04c: 8900 0x8900 - a04e: 917f 0x917f - a050: 7f80 flw fs0,56(a5) - a052: 1a06 slli s4,s4,0x21 - a054: fc91 bnez s1,9f70 <_start-0x7fff6090> - a056: 067e slli a2,a2,0x1f - a058: 2540 fld fs0,136(a0) - a05a: 9f1e add t5,t5,t2 - a05c: 0da8 addi a0,sp,728 - a05e: 0000 unimp - a060: 0db4 addi a3,sp,728 - a062: 0000 unimp - a064: 7f89000f 0x7f89000f - a068: 8091 srli s1,s1,0x4 - a06a: 067f 0x67f - a06c: 911a add sp,sp,t1 - a06e: 7efc flw fa5,124(a3) - a070: 4006 0x4006 - a072: 1e25 addi t3,t3,-23 - a074: 009f 0000 0000 0x9f - a07a: 0000 unimp - a07c: 6c00 flw fs0,24(s0) - a07e: 88000007 vlsseg5bu.v v0,(zero),zero,v0.t - a082: 01000007 vlbuff.v v0,(zero),v0.t - a086: 6600 flw fs0,8(a2) - ... - a090: 075c addi a5,sp,900 - a092: 0000 unimp - a094: 0bc4 addi s1,sp,468 - a096: 0000 unimp - a098: 80910003 lb zero,-2039(sp) - a09c: a87f 0xa87f - a09e: 000d c.nop 3 - a0a0: b400 fsd fs0,40(s0) - a0a2: 000d c.nop 3 - a0a4: 0300 addi s0,sp,384 - a0a6: 9100 0x9100 - a0a8: 7f80 flw fs0,56(a5) - ... - a0b2: 075c addi a5,sp,900 - a0b4: 0000 unimp - a0b6: 0ac8 addi a0,sp,340 - a0b8: 0000 unimp - a0ba: 0001 nop - a0bc: 000ac86f jal a6,b60bc <_start-0x7ff49f44> - a0c0: c400 sw s0,8(s0) - a0c2: 0300000b 0x300000b - a0c6: 9100 0x9100 - a0c8: 7efe flw ft9,252(sp) - a0ca: 0da8 addi a0,sp,728 - a0cc: 0000 unimp - a0ce: 0db4 addi a3,sp,728 - a0d0: 0000 unimp - a0d2: fe910003 lb zero,-23(sp) - a0d6: 007e c.slli zero,0x1f - a0d8: 0000 unimp - a0da: 0000 unimp - a0dc: 0000 unimp - a0de: 5c00 lw s0,56(s0) - a0e0: 64000007 0x64000007 - a0e4: 01000007 vlbuff.v v0,(zero),v0.t - a0e8: 6500 flw fs0,8(a0) - a0ea: 0764 addi s1,sp,908 - a0ec: 0000 unimp - a0ee: 0bc4 addi s1,sp,468 - a0f0: 0000 unimp - a0f2: 82910003 lb zero,-2007(sp) - a0f6: a87f 0xa87f - a0f8: 000d c.nop 3 - a0fa: b400 fsd fs0,40(s0) - a0fc: 000d c.nop 3 - a0fe: 0300 addi s0,sp,384 - a100: 9100 0x9100 - a102: 7f82 flw ft11,32(sp) - ... - a10c: 07a4 addi s1,sp,968 - a10e: 0000 unimp - a110: 07e0 addi s0,sp,972 - a112: 0000 unimp - a114: 0001 nop - a116: e05d bnez s0,a1bc <_start-0x7fff5e44> - a118: 10000007 vlb.v v0,(zero),v0.t - a11c: 0009 c.nop 2 - a11e: 0600 addi s0,sp,768 - a120: 8d00 0x8d00 - a122: 7b00 flw fs0,48(a4) - a124: 1e00 addi s0,sp,816 - a126: 109f 0009 3400 0x34000009109f - a12c: 0009 c.nop 2 - a12e: 0b00 addi s0,sp,400 - a130: 8400 0x8400 - a132: 917f 0x917f - a134: 7ef4 flw fa3,124(a3) - a136: 1a06 slli s4,s4,0x21 - a138: 008d addi ra,ra,3 - a13a: 9f1e add t5,t5,t2 - a13c: 0934 addi a3,sp,152 - a13e: 0000 unimp - a140: 0958 addi a4,sp,148 - a142: 0000 unimp - a144: f491000b 0xf491000b - a148: 067e slli a2,a2,0x1f - a14a: 0084 addi s1,sp,64 - a14c: 8d1a mv s10,t1 - a14e: 1e00 addi s0,sp,816 - a150: 589f 0009 dc00 0xdc000009589f - a156: 0009 c.nop 2 - a158: 0b00 addi s0,sp,400 - a15a: 8500 0x8500 - a15c: 917f 0x917f - a15e: 7ef4 flw fa3,124(a3) - a160: 1a06 slli s4,s4,0x21 - a162: 008d addi ra,ra,3 - a164: 9f1e add t5,t5,t2 - a166: 09dc addi a5,sp,212 - a168: 0000 unimp - a16a: 09e0 addi s0,sp,220 - a16c: 0000 unimp - a16e: 0010 0x10 - a170: 7f85 lui t6,0xfffe1 - a172: 8891 andi s1,s1,4 - a174: 067f 0x67f - a176: 851a mv a0,t1 - a178: 917f 0x917f - a17a: 7ef4 flw fa3,124(a3) - a17c: 1a06 slli s4,s4,0x21 - a17e: 9f1e add t5,t5,t2 - a180: 09e0 addi s0,sp,220 - a182: 0000 unimp - a184: 09ec addi a1,sp,220 - a186: 0000 unimp - a188: 0010 0x10 - a18a: 8891 andi s1,s1,4 - a18c: 067f 0x67f - a18e: 0079 c.nop 30 - a190: 911a add sp,sp,t1 - a192: 7ef4 flw fa3,124(a3) - a194: 7906 flw fs2,96(sp) - a196: 1a00 addi s0,sp,304 - a198: 9f1e add t5,t5,t2 - a19a: 09ec addi a1,sp,220 - a19c: 0000 unimp - a19e: 0a48 addi a0,sp,276 - a1a0: 0000 unimp - a1a2: 0010 0x10 - a1a4: 7f84 flw fs1,56(a5) - a1a6: 8891 andi s1,s1,4 - a1a8: 067f 0x67f - a1aa: 841a mv s0,t1 - a1ac: 917f 0x917f - a1ae: 7ef4 flw fa3,124(a3) - a1b0: 1a06 slli s4,s4,0x21 - a1b2: 9f1e add t5,t5,t2 - a1b4: 0a48 addi a0,sp,276 - a1b6: 0000 unimp - a1b8: 0ae0 addi s0,sp,348 - a1ba: 0000 unimp - a1bc: 0010 0x10 - a1be: 8891 andi s1,s1,4 - a1c0: 067f 0x67f - a1c2: 0079 c.nop 30 - a1c4: 911a add sp,sp,t1 - a1c6: 7ef4 flw fa3,124(a3) - a1c8: 7906 flw fs2,96(sp) - a1ca: 1a00 addi s0,sp,304 - a1cc: 9f1e add t5,t5,t2 - a1ce: 0ae0 addi s0,sp,348 - a1d0: 0000 unimp - a1d2: 0bc4 addi s1,sp,468 - a1d4: 0000 unimp - a1d6: 0010 0x10 - a1d8: 7f89 lui t6,0xfffe2 - a1da: 8891 andi s1,s1,4 - a1dc: 067f 0x67f - a1de: 891a mv s2,t1 - a1e0: 917f 0x917f - a1e2: 7ef4 flw fa3,124(a3) - a1e4: 1a06 slli s4,s4,0x21 - a1e6: 9f1e add t5,t5,t2 - a1e8: 0da8 addi a0,sp,728 - a1ea: 0000 unimp - a1ec: 0db4 addi a3,sp,728 - a1ee: 0000 unimp - a1f0: 0010 0x10 - a1f2: 7f89 lui t6,0xfffe2 - a1f4: 8891 andi s1,s1,4 - a1f6: 067f 0x67f - a1f8: 891a mv s2,t1 - a1fa: 917f 0x917f - a1fc: 7ef4 flw fa3,124(a3) - a1fe: 1a06 slli s4,s4,0x21 - a200: 9f1e add t5,t5,t2 - ... - a20a: 07a4 addi s1,sp,968 - a20c: 0000 unimp - a20e: 07b0 addi a2,sp,968 - a210: 0000 unimp - a212: 0006 c.slli zero,0x1 - a214: 0078 addi a4,sp,12 - a216: 9f1e007b 0x9f1e007b - a21a: 07b0 addi a2,sp,968 - a21c: 0000 unimp - a21e: 07b4 addi a3,sp,968 - a220: 0000 unimp - a222: 0001 nop - a224: b45f 0007 bc00 0xbc000007b45f - a22a: 06000007 0x6000007 - a22e: 7800 flw fs0,48(s0) - a230: 7b00 flw fs0,48(a4) - a232: 1e00 addi s0,sp,816 - a234: bc9f 0007 f400 0xf4000007bc9f - a23a: 01000007 vlbuff.v v0,(zero),v0.t - a23e: 5f00 lw s0,56(a4) - a240: 07f4 addi a3,sp,972 - a242: 0000 unimp - a244: 0910 addi a2,sp,144 - a246: 0000 unimp - a248: 0014 0x14 - a24a: 0078 addi a4,sp,12 - a24c: 821e007b 0x821e007b - a250: 8d00 0x8d00 - a252: 1e00 addi s0,sp,816 - a254: 8d22 mv s10,s0 - a256: 7b00 flw fs0,48(a4) - a258: 1e00 addi s0,sp,816 - a25a: 2540 fld fs0,136(a0) - a25c: 9f22 add t5,t5,s0 - a25e: 0910 addi a2,sp,144 - a260: 0000 unimp - a262: 0920 addi s0,sp,152 - a264: 0000 unimp - a266: 001e c.slli zero,0x7 - a268: 7f84 flw fs1,56(a5) - a26a: f491 bnez s1,a176 <_start-0x7fff5e8a> - a26c: 067e slli a2,a2,0x1f - a26e: 781a flw fa6,164(sp) - a270: 1e00 addi s0,sp,816 - a272: 0082 c.slli64 ra - a274: 008d addi ra,ra,3 - a276: 221e fld ft4,448(sp) - a278: 7f84 flw fs1,56(a5) - a27a: f491 bnez s1,a186 <_start-0x7fff5e7a> - a27c: 067e slli a2,a2,0x1f - a27e: 8d1a mv s10,t1 - a280: 1e00 addi s0,sp,816 - a282: 2540 fld fs0,136(a0) - a284: 9f22 add t5,t5,s0 - a286: 0920 addi s0,sp,152 - a288: 0000 unimp - a28a: 0934 addi a3,sp,152 - a28c: 0000 unimp - a28e: 0022 c.slli zero,0x8 - a290: 7f84 flw fs1,56(a5) - a292: f491 bnez s1,a19e <_start-0x7fff5e62> - a294: 067e slli a2,a2,0x1f - a296: 781a flw fa6,164(sp) - a298: 1e00 addi s0,sp,816 - a29a: f491 bnez s1,a1a6 <_start-0x7fff5e5a> - a29c: 067e slli a2,a2,0x1f - a29e: 2540 fld fs0,136(a0) - a2a0: 008d addi ra,ra,3 - a2a2: 221e fld ft4,448(sp) - a2a4: 7f84 flw fs1,56(a5) - a2a6: f491 bnez s1,a1b2 <_start-0x7fff5e4e> - a2a8: 067e slli a2,a2,0x1f - a2aa: 8d1a mv s10,t1 - a2ac: 1e00 addi s0,sp,816 - a2ae: 2540 fld fs0,136(a0) - a2b0: 9f22 add t5,t5,s0 - a2b2: 0934 addi a3,sp,152 - a2b4: 0000 unimp - a2b6: 0958 addi a4,sp,148 - a2b8: 0000 unimp - a2ba: 0022 c.slli zero,0x8 - a2bc: f491 bnez s1,a1c8 <_start-0x7fff5e38> - a2be: 067e slli a2,a2,0x1f - a2c0: 0084 addi s1,sp,64 - a2c2: 781a flw fa6,164(sp) - a2c4: 1e00 addi s0,sp,816 - a2c6: f491 bnez s1,a1d2 <_start-0x7fff5e2e> - a2c8: 067e slli a2,a2,0x1f - a2ca: 2540 fld fs0,136(a0) - a2cc: 008d addi ra,ra,3 - a2ce: 221e fld ft4,448(sp) - a2d0: f491 bnez s1,a1dc <_start-0x7fff5e24> - a2d2: 067e slli a2,a2,0x1f - a2d4: 0084 addi s1,sp,64 - a2d6: 8d1a mv s10,t1 - a2d8: 1e00 addi s0,sp,816 - a2da: 2540 fld fs0,136(a0) - a2dc: 9f22 add t5,t5,s0 - a2de: 0958 addi a4,sp,148 - a2e0: 0000 unimp - a2e2: 09dc addi a5,sp,212 - a2e4: 0000 unimp - a2e6: 0022 c.slli zero,0x8 - a2e8: 7f85 lui t6,0xfffe1 - a2ea: f491 bnez s1,a1f6 <_start-0x7fff5e0a> - a2ec: 067e slli a2,a2,0x1f - a2ee: 781a flw fa6,164(sp) - a2f0: 1e00 addi s0,sp,816 - a2f2: f491 bnez s1,a1fe <_start-0x7fff5e02> - a2f4: 067e slli a2,a2,0x1f - a2f6: 2540 fld fs0,136(a0) - a2f8: 008d addi ra,ra,3 - a2fa: 221e fld ft4,448(sp) - a2fc: 7f85 lui t6,0xfffe1 - a2fe: f491 bnez s1,a20a <_start-0x7fff5df6> - a300: 067e slli a2,a2,0x1f - a302: 8d1a mv s10,t1 - a304: 1e00 addi s0,sp,816 - a306: 2540 fld fs0,136(a0) - a308: 9f22 add t5,t5,s0 - a30a: 09dc addi a5,sp,212 - a30c: 0000 unimp - a30e: 09e0 addi s0,sp,220 - a310: 0000 unimp - a312: 002c addi a1,sp,8 - a314: 7f85 lui t6,0xfffe1 - a316: f491 bnez s1,a222 <_start-0x7fff5dde> - a318: 067e slli a2,a2,0x1f - a31a: 781a flw fa6,164(sp) - a31c: 1e00 addi s0,sp,816 - a31e: 7f85 lui t6,0xfffe1 - a320: 8891 andi s1,s1,4 - a322: 067f 0x67f - a324: 911a add sp,sp,t1 - a326: 7ef4 flw fa3,124(a3) - a328: 4006 0x4006 - a32a: 1e25 addi t3,t3,-23 - a32c: 8522 mv a0,s0 - a32e: 917f 0x917f - a330: 7f88 flw fa0,56(a5) - a332: 1a06 slli s4,s4,0x21 - a334: 7f85 lui t6,0xfffe1 - a336: f491 bnez s1,a242 <_start-0x7fff5dbe> - a338: 067e slli a2,a2,0x1f - a33a: 1e1a slli t3,t3,0x26 - a33c: 2540 fld fs0,136(a0) - a33e: 9f22 add t5,t5,s0 - a340: 09e0 addi s0,sp,220 - a342: 0000 unimp - a344: 09ec addi a1,sp,220 - a346: 0000 unimp - a348: 002c addi a1,sp,8 - a34a: f491 bnez s1,a256 <_start-0x7fff5daa> - a34c: 067e slli a2,a2,0x1f - a34e: 0079 c.nop 30 - a350: 781a flw fa6,164(sp) - a352: 1e00 addi s0,sp,816 - a354: 8891 andi s1,s1,4 - a356: 067f 0x67f - a358: 0079 c.nop 30 - a35a: 911a add sp,sp,t1 - a35c: 7ef4 flw fa3,124(a3) - a35e: 4006 0x4006 - a360: 1e25 addi t3,t3,-23 - a362: 9122 add sp,sp,s0 - a364: 7f88 flw fa0,56(a5) - a366: 7906 flw fs2,96(sp) - a368: 1a00 addi s0,sp,304 - a36a: f491 bnez s1,a276 <_start-0x7fff5d8a> - a36c: 067e slli a2,a2,0x1f - a36e: 0079 c.nop 30 - a370: 1e1a slli t3,t3,0x26 - a372: 2540 fld fs0,136(a0) - a374: 9f22 add t5,t5,s0 - a376: 09ec addi a1,sp,220 - a378: 0000 unimp - a37a: 0a48 addi a0,sp,276 - a37c: 0000 unimp - a37e: 002c addi a1,sp,8 - a380: 7f84 flw fs1,56(a5) - a382: f491 bnez s1,a28e <_start-0x7fff5d72> - a384: 067e slli a2,a2,0x1f - a386: 781a flw fa6,164(sp) - a388: 1e00 addi s0,sp,816 - a38a: 7f84 flw fs1,56(a5) - a38c: 8891 andi s1,s1,4 - a38e: 067f 0x67f - a390: 911a add sp,sp,t1 - a392: 7ef4 flw fa3,124(a3) - a394: 4006 0x4006 - a396: 1e25 addi t3,t3,-23 - a398: 8422 mv s0,s0 - a39a: 917f 0x917f - a39c: 7f88 flw fa0,56(a5) - a39e: 1a06 slli s4,s4,0x21 - a3a0: 7f84 flw fs1,56(a5) - a3a2: f491 bnez s1,a2ae <_start-0x7fff5d52> - a3a4: 067e slli a2,a2,0x1f - a3a6: 1e1a slli t3,t3,0x26 - a3a8: 2540 fld fs0,136(a0) - a3aa: 9f22 add t5,t5,s0 - a3ac: 0a48 addi a0,sp,276 - a3ae: 0000 unimp - a3b0: 0ae0 addi s0,sp,348 - a3b2: 0000 unimp - a3b4: 002c addi a1,sp,8 - a3b6: f491 bnez s1,a2c2 <_start-0x7fff5d3e> - a3b8: 067e slli a2,a2,0x1f - a3ba: 0079 c.nop 30 - a3bc: 781a flw fa6,164(sp) - a3be: 1e00 addi s0,sp,816 - a3c0: 8891 andi s1,s1,4 - a3c2: 067f 0x67f - a3c4: 0079 c.nop 30 - a3c6: 911a add sp,sp,t1 - a3c8: 7ef4 flw fa3,124(a3) - a3ca: 4006 0x4006 - a3cc: 1e25 addi t3,t3,-23 - a3ce: 9122 add sp,sp,s0 - a3d0: 7f88 flw fa0,56(a5) - a3d2: 7906 flw fs2,96(sp) - a3d4: 1a00 addi s0,sp,304 - a3d6: f491 bnez s1,a2e2 <_start-0x7fff5d1e> - a3d8: 067e slli a2,a2,0x1f - a3da: 0079 c.nop 30 - a3dc: 1e1a slli t3,t3,0x26 - a3de: 2540 fld fs0,136(a0) - a3e0: 9f22 add t5,t5,s0 - a3e2: 0ae0 addi s0,sp,348 - a3e4: 0000 unimp - a3e6: 0bc4 addi s1,sp,468 - a3e8: 0000 unimp - a3ea: 002c addi a1,sp,8 - a3ec: 7f89 lui t6,0xfffe2 - a3ee: f491 bnez s1,a2fa <_start-0x7fff5d06> - a3f0: 067e slli a2,a2,0x1f - a3f2: 781a flw fa6,164(sp) - a3f4: 1e00 addi s0,sp,816 - a3f6: 7f89 lui t6,0xfffe2 - a3f8: 8891 andi s1,s1,4 - a3fa: 067f 0x67f - a3fc: 911a add sp,sp,t1 - a3fe: 7ef4 flw fa3,124(a3) - a400: 4006 0x4006 - a402: 1e25 addi t3,t3,-23 - a404: 8922 mv s2,s0 - a406: 917f 0x917f - a408: 7f88 flw fa0,56(a5) - a40a: 1a06 slli s4,s4,0x21 - a40c: 7f89 lui t6,0xfffe2 - a40e: f491 bnez s1,a31a <_start-0x7fff5ce6> - a410: 067e slli a2,a2,0x1f - a412: 1e1a slli t3,t3,0x26 - a414: 2540 fld fs0,136(a0) - a416: 9f22 add t5,t5,s0 - a418: 0da8 addi a0,sp,728 - a41a: 0000 unimp - a41c: 0db4 addi a3,sp,728 - a41e: 0000 unimp - a420: 002c addi a1,sp,8 - a422: 7f89 lui t6,0xfffe2 - a424: f491 bnez s1,a330 <_start-0x7fff5cd0> - a426: 067e slli a2,a2,0x1f - a428: 781a flw fa6,164(sp) - a42a: 1e00 addi s0,sp,816 - a42c: 7f89 lui t6,0xfffe2 - a42e: 8891 andi s1,s1,4 - a430: 067f 0x67f - a432: 911a add sp,sp,t1 - a434: 7ef4 flw fa3,124(a3) - a436: 4006 0x4006 - a438: 1e25 addi t3,t3,-23 - a43a: 8922 mv s2,s0 - a43c: 917f 0x917f - a43e: 7f88 flw fa0,56(a5) - a440: 1a06 slli s4,s4,0x21 - a442: 7f89 lui t6,0xfffe2 - a444: f491 bnez s1,a350 <_start-0x7fff5cb0> - a446: 067e slli a2,a2,0x1f - a448: 1e1a slli t3,t3,0x26 - a44a: 2540 fld fs0,136(a0) - a44c: 9f22 add t5,t5,s0 - ... - a456: 07bc addi a5,sp,968 - a458: 0000 unimp - a45a: 07cc addi a1,sp,964 - a45c: 0000 unimp - a45e: 0001 nop - a460: 005e c.slli zero,0x17 - a462: 0000 unimp - a464: 0000 unimp - a466: 0000 unimp - a468: a000 fsd fs0,0(s0) - a46a: 20000007 vlseg2bu.v v0,(zero),v0.t - a46e: 0009 c.nop 2 - a470: 0100 addi s0,sp,128 - a472: 6200 flw fs0,0(a2) - a474: 0920 addi s0,sp,152 - a476: 0000 unimp - a478: 0bc4 addi s1,sp,468 - a47a: 0000 unimp - a47c: f6910003 lb zero,-151(sp) - a480: a87e fsd ft11,16(sp) - a482: 000d c.nop 3 - a484: b400 fsd fs0,40(s0) - a486: 000d c.nop 3 - a488: 0300 addi s0,sp,384 - a48a: 9100 0x9100 - a48c: 7ef6 flw ft9,124(sp) - ... - a496: 07a0 addi s0,sp,968 - a498: 0000 unimp - a49a: 0bc4 addi s1,sp,468 - a49c: 0000 unimp - a49e: 0001 nop - a4a0: a858 fsd fa4,144(s0) - a4a2: 000d c.nop 3 - a4a4: b400 fsd fs0,40(s0) - a4a6: 000d c.nop 3 - a4a8: 0100 addi s0,sp,128 - a4aa: 5800 lw s0,48(s0) - ... - a4b4: 07f0 addi a2,sp,972 - a4b6: 0000 unimp - a4b8: 0824 addi s1,sp,24 - a4ba: 0000 unimp - a4bc: 0001 nop - a4be: 245e fld fs0,464(sp) - a4c0: 0008 0x8 - a4c2: 5000 lw s0,32(s0) - a4c4: 0009 c.nop 2 - a4c6: 0600 addi s0,sp,768 - a4c8: 7c00 flw fs0,56(s0) - a4ca: 8e00 0x8e00 - a4cc: 1e00 addi s0,sp,816 - a4ce: 509f 0009 5800 0x58000009509f - a4d4: 0009 c.nop 2 - a4d6: 0b00 addi s0,sp,400 - a4d8: 9100 0x9100 - a4da: 7f84 flw fs1,56(a5) - a4dc: 8406 mv s0,ra - a4de: 1a00 addi s0,sp,304 - a4e0: 007c addi a5,sp,12 - a4e2: 9f1e add t5,t5,t2 - a4e4: 0958 addi a4,sp,148 - a4e6: 0000 unimp - a4e8: 0998 addi a4,sp,208 - a4ea: 0000 unimp - a4ec: 7f85000b 0x7f85000b - a4f0: 8491 srai s1,s1,0x4 - a4f2: 067f 0x67f - a4f4: 7c1a flw fs8,164(sp) - a4f6: 1e00 addi s0,sp,816 - a4f8: 989f 0009 e000 0xe0000009989f - a4fe: 0009 c.nop 2 - a500: 1000 addi s0,sp,32 - a502: 8500 0x8500 - a504: 917f 0x917f - a506: 7ef8 flw fa4,124(a3) - a508: 1a06 slli s4,s4,0x21 - a50a: 7f85 lui t6,0xfffe1 - a50c: 8491 srai s1,s1,0x4 - a50e: 067f 0x67f - a510: 1e1a slli t3,t3,0x26 - a512: e09f 0009 ec00 0xec000009e09f - a518: 0009 c.nop 2 - a51a: 1000 addi s0,sp,32 - a51c: 9100 0x9100 - a51e: 7ef8 flw fa4,124(a3) - a520: 7906 flw fs2,96(sp) - a522: 1a00 addi s0,sp,304 - a524: 8491 srai s1,s1,0x4 - a526: 067f 0x67f - a528: 0079 c.nop 30 - a52a: 1e1a slli t3,t3,0x26 - a52c: ec9f 0009 4800 0x48000009ec9f - a532: 000a c.slli zero,0x2 - a534: 1000 addi s0,sp,32 - a536: 8400 0x8400 - a538: 917f 0x917f - a53a: 7ef8 flw fa4,124(a3) - a53c: 1a06 slli s4,s4,0x21 - a53e: 7f84 flw fs1,56(a5) - a540: 8491 srai s1,s1,0x4 - a542: 067f 0x67f - a544: 1e1a slli t3,t3,0x26 - a546: 489f 000a e000 0xe000000a489f - a54c: 000a c.slli zero,0x2 - a54e: 1000 addi s0,sp,32 - a550: 9100 0x9100 - a552: 7ef8 flw fa4,124(a3) - a554: 7906 flw fs2,96(sp) - a556: 1a00 addi s0,sp,304 - a558: 8491 srai s1,s1,0x4 - a55a: 067f 0x67f - a55c: 0079 c.nop 30 - a55e: 1e1a slli t3,t3,0x26 - a560: e09f 000a c400 0xc400000ae09f - a566: 1000000b 0x1000000b - a56a: 8900 0x8900 - a56c: 917f 0x917f - a56e: 7ef8 flw fa4,124(a3) - a570: 1a06 slli s4,s4,0x21 - a572: 7f89 lui t6,0xfffe2 - a574: 8491 srai s1,s1,0x4 - a576: 067f 0x67f - a578: 1e1a slli t3,t3,0x26 - a57a: a89f 000d b400 0xb400000da89f - a580: 000d c.nop 3 - a582: 1000 addi s0,sp,32 - a584: 8900 0x8900 - a586: 917f 0x917f - a588: 7ef8 flw fa4,124(a3) - a58a: 1a06 slli s4,s4,0x21 - a58c: 7f89 lui t6,0xfffe2 - a58e: 8491 srai s1,s1,0x4 - a590: 067f 0x67f - a592: 1e1a slli t3,t3,0x26 - a594: 009f 0000 0000 0x9f - a59a: 0000 unimp - a59c: f000 fsw fs0,32(s0) - a59e: f4000007 0xf4000007 - a5a2: 06000007 0x6000007 - a5a6: 7900 flw fs0,48(a0) - a5a8: 7c00 flw fs0,56(s0) - a5aa: 1e00 addi s0,sp,816 - a5ac: f49f 0007 fc00 0xfc000007f49f - a5b2: 01000007 vlbuff.v v0,(zero),v0.t - a5b6: 5f00 lw s0,56(a4) - a5b8: 07fc addi a5,sp,972 - a5ba: 0000 unimp - a5bc: 0804 addi s1,sp,16 - a5be: 0000 unimp - a5c0: 0006 c.slli zero,0x1 - a5c2: 0079 c.nop 30 - a5c4: 007c addi a5,sp,12 - a5c6: 9f1e add t5,t5,t2 - a5c8: 0804 addi s1,sp,16 - a5ca: 0000 unimp - a5cc: 0820 addi s0,sp,24 - a5ce: 0000 unimp - a5d0: 0001 nop - a5d2: 205f 0008 2400 0x24000008205f - a5d8: 0008 0x8 - a5da: 1100 addi s0,sp,160 - a5dc: 7900 flw fs0,48(a0) - a5de: 7c00 flw fs0,56(s0) - a5e0: 1e00 addi s0,sp,816 - a5e2: 008e0077 0x8e0077 - a5e6: 221e fld ft4,448(sp) - a5e8: 007e c.slli zero,0x1f - a5ea: 2540 fld fs0,136(a0) - a5ec: 9f22 add t5,t5,s0 - a5ee: 0824 addi s1,sp,24 - a5f0: 0000 unimp - a5f2: 0950 addi a2,sp,148 - a5f4: 0000 unimp - a5f6: 0014 0x14 - a5f8: 0079 c.nop 30 - a5fa: 007c addi a5,sp,12 - a5fc: 771e flw fa4,228(sp) - a5fe: 8e00 0x8e00 - a600: 1e00 addi s0,sp,816 - a602: 7c22 flw fs8,40(sp) - a604: 8e00 0x8e00 - a606: 1e00 addi s0,sp,816 - a608: 2540 fld fs0,136(a0) - a60a: 9f22 add t5,t5,s0 - a60c: 0950 addi a2,sp,148 - a60e: 0000 unimp - a610: 0958 addi a4,sp,148 - a612: 0000 unimp - a614: 001e c.slli zero,0x7 - a616: 0079 c.nop 30 - a618: 007c addi a5,sp,12 - a61a: 911e add sp,sp,t2 - a61c: 7f84 flw fs1,56(a5) - a61e: 8406 mv s0,ra - a620: 1a00 addi s0,sp,304 - a622: 221e0077 0x221e0077 - a626: 8491 srai s1,s1,0x4 - a628: 067f 0x67f - a62a: 0084 addi s1,sp,64 - a62c: 7c1a flw fs8,164(sp) - a62e: 1e00 addi s0,sp,816 - a630: 2540 fld fs0,136(a0) - a632: 9f22 add t5,t5,s0 - a634: 0958 addi a4,sp,148 - a636: 0000 unimp - a638: 095c addi a5,sp,148 - a63a: 0000 unimp - a63c: 001e c.slli zero,0x7 - a63e: 0079 c.nop 30 - a640: 007c addi a5,sp,12 - a642: 851e mv a0,t2 - a644: 917f 0x917f - a646: 7f84 flw fs1,56(a5) - a648: 1a06 slli s4,s4,0x21 - a64a: 221e0077 0x221e0077 - a64e: 7f85 lui t6,0xfffe1 - a650: 8491 srai s1,s1,0x4 - a652: 067f 0x67f - a654: 7c1a flw fs8,164(sp) - a656: 1e00 addi s0,sp,816 - a658: 2540 fld fs0,136(a0) - a65a: 9f22 add t5,t5,s0 - a65c: 095c addi a5,sp,148 - a65e: 0000 unimp - a660: 0998 addi a4,sp,208 - a662: 0000 unimp - a664: 0022 c.slli zero,0x8 - a666: 8491 srai s1,s1,0x4 - a668: 067f 0x67f - a66a: 2540 fld fs0,136(a0) - a66c: 007c addi a5,sp,12 - a66e: 851e mv a0,t2 - a670: 917f 0x917f - a672: 7f84 flw fs1,56(a5) - a674: 1a06 slli s4,s4,0x21 - a676: 221e0077 0x221e0077 - a67a: 7f85 lui t6,0xfffe1 - a67c: 8491 srai s1,s1,0x4 - a67e: 067f 0x67f - a680: 7c1a flw fs8,164(sp) - a682: 1e00 addi s0,sp,816 - a684: 2540 fld fs0,136(a0) - a686: 9f22 add t5,t5,s0 - a688: 0998 addi a4,sp,208 - a68a: 0000 unimp - a68c: 09a8 addi a0,sp,216 - a68e: 0000 unimp - a690: 002c addi a1,sp,8 - a692: 7f85 lui t6,0xfffe1 - a694: f891 bnez s1,a5a8 <_start-0x7fff5a58> - a696: 067e slli a2,a2,0x1f - a698: 911a add sp,sp,t1 - a69a: 7f84 flw fs1,56(a5) - a69c: 4006 0x4006 - a69e: 1e25 addi t3,t3,-23 - a6a0: 7f85 lui t6,0xfffe1 - a6a2: 8491 srai s1,s1,0x4 - a6a4: 067f 0x67f - a6a6: 771a flw fa4,164(sp) - a6a8: 1e00 addi s0,sp,816 - a6aa: 8522 mv a0,s0 - a6ac: 917f 0x917f - a6ae: 7ef8 flw fa4,124(a3) - a6b0: 1a06 slli s4,s4,0x21 - a6b2: 7f85 lui t6,0xfffe1 - a6b4: 8491 srai s1,s1,0x4 - a6b6: 067f 0x67f - a6b8: 1e1a slli t3,t3,0x26 - a6ba: 2540 fld fs0,136(a0) - a6bc: 9f22 add t5,t5,s0 - a6be: 09a8 addi a0,sp,216 - a6c0: 0000 unimp - a6c2: 09e0 addi s0,sp,220 - a6c4: 0000 unimp - a6c6: 0030 addi a2,sp,8 - a6c8: 7f85 lui t6,0xfffe1 - a6ca: f891 bnez s1,a5de <_start-0x7fff5a22> - a6cc: 067e slli a2,a2,0x1f - a6ce: 911a add sp,sp,t1 - a6d0: 7f84 flw fs1,56(a5) - a6d2: 4006 0x4006 - a6d4: 1e25 addi t3,t3,-23 - a6d6: 7f85 lui t6,0xfffe1 - a6d8: 8491 srai s1,s1,0x4 - a6da: 067f 0x67f - a6dc: 911a add sp,sp,t1 - a6de: 7ef8 flw fa4,124(a3) - a6e0: 4006 0x4006 - a6e2: 1e25 addi t3,t3,-23 - a6e4: 8522 mv a0,s0 - a6e6: 917f 0x917f - a6e8: 7ef8 flw fa4,124(a3) - a6ea: 1a06 slli s4,s4,0x21 - a6ec: 7f85 lui t6,0xfffe1 - a6ee: 8491 srai s1,s1,0x4 - a6f0: 067f 0x67f - a6f2: 1e1a slli t3,t3,0x26 - a6f4: 2540 fld fs0,136(a0) - a6f6: 9f22 add t5,t5,s0 - a6f8: 09e0 addi s0,sp,220 - a6fa: 0000 unimp - a6fc: 09ec addi a1,sp,220 - a6fe: 0000 unimp - a700: 0030 addi a2,sp,8 - a702: f891 bnez s1,a616 <_start-0x7fff59ea> - a704: 067e slli a2,a2,0x1f - a706: 0079 c.nop 30 - a708: 911a add sp,sp,t1 - a70a: 7f84 flw fs1,56(a5) - a70c: 4006 0x4006 - a70e: 1e25 addi t3,t3,-23 - a710: 8491 srai s1,s1,0x4 - a712: 067f 0x67f - a714: 0079 c.nop 30 - a716: 911a add sp,sp,t1 - a718: 7ef8 flw fa4,124(a3) - a71a: 4006 0x4006 - a71c: 1e25 addi t3,t3,-23 - a71e: 9122 add sp,sp,s0 - a720: 7ef8 flw fa4,124(a3) - a722: 7906 flw fs2,96(sp) - a724: 1a00 addi s0,sp,304 - a726: 8491 srai s1,s1,0x4 - a728: 067f 0x67f - a72a: 0079 c.nop 30 - a72c: 1e1a slli t3,t3,0x26 - a72e: 2540 fld fs0,136(a0) - a730: 9f22 add t5,t5,s0 - a732: 09ec addi a1,sp,220 - a734: 0000 unimp - a736: 0a48 addi a0,sp,276 - a738: 0000 unimp - a73a: 0030 addi a2,sp,8 - a73c: 7f84 flw fs1,56(a5) - a73e: f891 bnez s1,a652 <_start-0x7fff59ae> - a740: 067e slli a2,a2,0x1f - a742: 911a add sp,sp,t1 - a744: 7f84 flw fs1,56(a5) - a746: 4006 0x4006 - a748: 1e25 addi t3,t3,-23 - a74a: 7f84 flw fs1,56(a5) - a74c: 8491 srai s1,s1,0x4 - a74e: 067f 0x67f - a750: 911a add sp,sp,t1 - a752: 7ef8 flw fa4,124(a3) - a754: 4006 0x4006 - a756: 1e25 addi t3,t3,-23 - a758: 8422 mv s0,s0 - a75a: 917f 0x917f - a75c: 7ef8 flw fa4,124(a3) - a75e: 1a06 slli s4,s4,0x21 - a760: 7f84 flw fs1,56(a5) - a762: 8491 srai s1,s1,0x4 - a764: 067f 0x67f - a766: 1e1a slli t3,t3,0x26 - a768: 2540 fld fs0,136(a0) - a76a: 9f22 add t5,t5,s0 - a76c: 0a48 addi a0,sp,276 - a76e: 0000 unimp - a770: 0ae0 addi s0,sp,348 - a772: 0000 unimp - a774: 0030 addi a2,sp,8 - a776: f891 bnez s1,a68a <_start-0x7fff5976> - a778: 067e slli a2,a2,0x1f - a77a: 0079 c.nop 30 - a77c: 911a add sp,sp,t1 - a77e: 7f84 flw fs1,56(a5) - a780: 4006 0x4006 - a782: 1e25 addi t3,t3,-23 - a784: 8491 srai s1,s1,0x4 - a786: 067f 0x67f - a788: 0079 c.nop 30 - a78a: 911a add sp,sp,t1 - a78c: 7ef8 flw fa4,124(a3) - a78e: 4006 0x4006 - a790: 1e25 addi t3,t3,-23 - a792: 9122 add sp,sp,s0 - a794: 7ef8 flw fa4,124(a3) - a796: 7906 flw fs2,96(sp) - a798: 1a00 addi s0,sp,304 - a79a: 8491 srai s1,s1,0x4 - a79c: 067f 0x67f - a79e: 0079 c.nop 30 - a7a0: 1e1a slli t3,t3,0x26 - a7a2: 2540 fld fs0,136(a0) - a7a4: 9f22 add t5,t5,s0 - a7a6: 0ae0 addi s0,sp,348 - a7a8: 0000 unimp - a7aa: 0bc4 addi s1,sp,468 - a7ac: 0000 unimp - a7ae: 0030 addi a2,sp,8 - a7b0: 7f89 lui t6,0xfffe2 - a7b2: f891 bnez s1,a6c6 <_start-0x7fff593a> - a7b4: 067e slli a2,a2,0x1f - a7b6: 911a add sp,sp,t1 - a7b8: 7f84 flw fs1,56(a5) - a7ba: 4006 0x4006 - a7bc: 1e25 addi t3,t3,-23 - a7be: 7f89 lui t6,0xfffe2 - a7c0: 8491 srai s1,s1,0x4 - a7c2: 067f 0x67f - a7c4: 911a add sp,sp,t1 - a7c6: 7ef8 flw fa4,124(a3) - a7c8: 4006 0x4006 - a7ca: 1e25 addi t3,t3,-23 - a7cc: 8922 mv s2,s0 - a7ce: 917f 0x917f - a7d0: 7ef8 flw fa4,124(a3) - a7d2: 1a06 slli s4,s4,0x21 - a7d4: 7f89 lui t6,0xfffe2 - a7d6: 8491 srai s1,s1,0x4 - a7d8: 067f 0x67f - a7da: 1e1a slli t3,t3,0x26 - a7dc: 2540 fld fs0,136(a0) - a7de: 9f22 add t5,t5,s0 - a7e0: 0da8 addi a0,sp,728 - a7e2: 0000 unimp - a7e4: 0db4 addi a3,sp,728 - a7e6: 0000 unimp - a7e8: 0030 addi a2,sp,8 - a7ea: 7f89 lui t6,0xfffe2 - a7ec: f891 bnez s1,a700 <_start-0x7fff5900> - a7ee: 067e slli a2,a2,0x1f - a7f0: 911a add sp,sp,t1 - a7f2: 7f84 flw fs1,56(a5) - a7f4: 4006 0x4006 - a7f6: 1e25 addi t3,t3,-23 - a7f8: 7f89 lui t6,0xfffe2 - a7fa: 8491 srai s1,s1,0x4 - a7fc: 067f 0x67f - a7fe: 911a add sp,sp,t1 - a800: 7ef8 flw fa4,124(a3) - a802: 4006 0x4006 - a804: 1e25 addi t3,t3,-23 - a806: 8922 mv s2,s0 - a808: 917f 0x917f - a80a: 7ef8 flw fa4,124(a3) - a80c: 1a06 slli s4,s4,0x21 - a80e: 7f89 lui t6,0xfffe2 - a810: 8491 srai s1,s1,0x4 - a812: 067f 0x67f - a814: 1e1a slli t3,t3,0x26 - a816: 2540 fld fs0,136(a0) - a818: 9f22 add t5,t5,s0 - ... - a822: 0804 addi s1,sp,16 - a824: 0000 unimp - a826: 0890 addi a2,sp,80 - a828: 0000 unimp - a82a: 0001 nop - a82c: 0065 c.nop 25 - a82e: 0000 unimp - a830: 0000 unimp - a832: 0000 unimp - a834: ec00 fsw fs0,24(s0) - a836: c4000007 0xc4000007 - a83a: 0300000b 0x300000b - a83e: 9100 0x9100 - a840: 7ef8 flw fa4,124(a3) - a842: 0da8 addi a0,sp,728 - a844: 0000 unimp - a846: 0db4 addi a3,sp,728 - a848: 0000 unimp - a84a: f8910003 lb zero,-119(sp) - a84e: 007e c.slli zero,0x1f - a850: 0000 unimp - a852: 0000 unimp - a854: 0000 unimp - a856: ec00 fsw fs0,24(s0) - a858: a8000007 vlsseg6bu.v v0,(zero),zero,v0.t - a85c: 0009 c.nop 2 - a85e: 0100 addi s0,sp,128 - a860: 5700 lw s0,40(a4) - a862: 09a8 addi a0,sp,216 - a864: 0000 unimp - a866: 0bc4 addi s1,sp,468 - a868: 0000 unimp - a86a: fa910003 lb zero,-87(sp) - a86e: a87e fsd ft11,16(sp) - a870: 000d c.nop 3 - a872: b400 fsd fs0,40(s0) - a874: 000d c.nop 3 - a876: 0300 addi s0,sp,384 - a878: 9100 0x9100 - a87a: 7efa flw ft9,188(sp) - ... - a884: 07ec addi a1,sp,972 - a886: 0000 unimp - a888: 095c addi a5,sp,148 - a88a: 0000 unimp - a88c: 0001 nop - a88e: 5c59 li s8,-10 - a890: 0009 c.nop 2 - a892: c400 sw s0,8(s0) - a894: 0300000b 0x300000b - a898: 9100 0x9100 - a89a: 7f86 flw ft11,96(sp) - a89c: 0da8 addi a0,sp,728 - a89e: 0000 unimp - a8a0: 0db4 addi a3,sp,728 - a8a2: 0000 unimp - a8a4: 86910003 lb zero,-1943(sp) - a8a8: 007f 0x7f - a8aa: 0000 unimp - a8ac: 0000 unimp - a8ae: 0000 unimp - a8b0: 8400 0x8400 - a8b2: 0008 0x8 - a8b4: 9c00 0x9c00 - a8b6: 0008 0x8 - a8b8: 0100 addi s0,sp,128 - a8ba: 5a00 lw s0,48(a2) - ... - a8c4: 0884 addi s1,sp,80 - a8c6: 0000 unimp - a8c8: 0898 addi a4,sp,80 - a8ca: 0000 unimp - a8cc: 001f 007e 4b40 0x4b40007e001f - a8d2: 2224 fld fs1,64(a2) - a8d4: 0080 addi s0,sp,64 - a8d6: 4b40 lw s0,20(a4) - a8d8: 2224 fld fs1,64(a2) - a8da: 882d andi s0,s0,11 - a8dc: 4000 lw s0,0(s0) - a8de: 7a22244b fnmsub.d fs0,ft4,ft2,fa5,rdn - a8e2: 4000 lw s0,0(s0) - a8e4: 2d22244b 0x2d22244b - a8e8: 0821 addi a6,a6,8 - a8ea: 1aff 0x1aff - a8ec: 989f 0008 9c00 0x9c000008989f - a8f2: 0008 0x8 - a8f4: 2200 fld fs0,0(a2) - a8f6: 8900 0x8900 - a8f8: 8000 0x8000 - a8fa: 2200 fld fs0,0(a2) - a8fc: 4b40 lw s0,20(a4) - a8fe: 2224 fld fs1,64(a2) - a900: 0089 addi ra,ra,2 - a902: 4b40 lw s0,20(a4) - a904: 2224 fld fs1,64(a2) - a906: 882d andi s0,s0,11 - a908: 4000 lw s0,0(s0) - a90a: 7a22244b fnmsub.d fs0,ft4,ft2,fa5,rdn - a90e: 4000 lw s0,0(s0) - a910: 2d22244b 0x2d22244b - a914: 0821 addi a6,a6,8 - a916: 1aff 0x1aff - a918: 009f 0000 0000 0x9f - a91e: 0000 unimp - a920: c000 sw s0,0(s0) - a922: 0008 0x8 - a924: fc00 fsw fs0,56(s0) - a926: 0008 0x8 - a928: 0100 addi s0,sp,128 - a92a: 6000 flw fs0,0(s0) - a92c: 08fc addi a5,sp,92 - a92e: 0000 unimp - a930: 0998 addi a4,sp,208 - a932: 0000 unimp - a934: 0006 c.slli zero,0x1 - a936: 008d addi ra,ra,3 - a938: 007c addi a5,sp,12 - a93a: 9f1e add t5,t5,t2 - a93c: 0998 addi a4,sp,208 - a93e: 0000 unimp - a940: 09dc addi a5,sp,212 - a942: 0000 unimp - a944: 7f85000b 0x7f85000b - a948: f891 bnez s1,a85c <_start-0x7fff57a4> - a94a: 067e slli a2,a2,0x1f - a94c: 8d1a mv s10,t1 - a94e: 1e00 addi s0,sp,816 - a950: dc9f 0009 e000 0xe0000009dc9f - a956: 0009 c.nop 2 - a958: 1000 addi s0,sp,32 - a95a: 8500 0x8500 - a95c: 917f 0x917f - a95e: 7f88 flw fa0,56(a5) - a960: 1a06 slli s4,s4,0x21 - a962: 7f85 lui t6,0xfffe1 - a964: f891 bnez s1,a878 <_start-0x7fff5788> - a966: 067e slli a2,a2,0x1f - a968: 1e1a slli t3,t3,0x26 - a96a: e09f 0009 ec00 0xec000009e09f - a970: 0009 c.nop 2 - a972: 1000 addi s0,sp,32 - a974: 9100 0x9100 - a976: 7f88 flw fa0,56(a5) - a978: 7906 flw fs2,96(sp) - a97a: 1a00 addi s0,sp,304 - a97c: f891 bnez s1,a890 <_start-0x7fff5770> - a97e: 067e slli a2,a2,0x1f - a980: 0079 c.nop 30 - a982: 1e1a slli t3,t3,0x26 - a984: ec9f 0009 4800 0x48000009ec9f - a98a: 000a c.slli zero,0x2 - a98c: 1000 addi s0,sp,32 - a98e: 8400 0x8400 - a990: 917f 0x917f - a992: 7f88 flw fa0,56(a5) - a994: 1a06 slli s4,s4,0x21 - a996: 7f84 flw fs1,56(a5) - a998: f891 bnez s1,a8ac <_start-0x7fff5754> - a99a: 067e slli a2,a2,0x1f - a99c: 1e1a slli t3,t3,0x26 - a99e: 489f 000a e000 0xe000000a489f - a9a4: 000a c.slli zero,0x2 - a9a6: 1000 addi s0,sp,32 - a9a8: 9100 0x9100 - a9aa: 7f88 flw fa0,56(a5) - a9ac: 7906 flw fs2,96(sp) - a9ae: 1a00 addi s0,sp,304 - a9b0: f891 bnez s1,a8c4 <_start-0x7fff573c> - a9b2: 067e slli a2,a2,0x1f - a9b4: 0079 c.nop 30 - a9b6: 1e1a slli t3,t3,0x26 - a9b8: e09f 000a c400 0xc400000ae09f - a9be: 1000000b 0x1000000b - a9c2: 8900 0x8900 - a9c4: 917f 0x917f - a9c6: 7f88 flw fa0,56(a5) - a9c8: 1a06 slli s4,s4,0x21 - a9ca: 7f89 lui t6,0xfffe2 - a9cc: f891 bnez s1,a8e0 <_start-0x7fff5720> - a9ce: 067e slli a2,a2,0x1f - a9d0: 1e1a slli t3,t3,0x26 - a9d2: a89f 000d b400 0xb400000da89f - a9d8: 000d c.nop 3 - a9da: 1000 addi s0,sp,32 - a9dc: 8900 0x8900 - a9de: 917f 0x917f - a9e0: 7f88 flw fa0,56(a5) - a9e2: 1a06 slli s4,s4,0x21 - a9e4: 7f89 lui t6,0xfffe2 - a9e6: f891 bnez s1,a8fa <_start-0x7fff5706> - a9e8: 067e slli a2,a2,0x1f - a9ea: 1e1a slli t3,t3,0x26 - a9ec: 009f 0000 0000 0x9f - a9f2: 0000 unimp - a9f4: c000 sw s0,0(s0) - a9f6: 0008 0x8 - a9f8: cc00 sw s0,24(s0) - a9fa: 0008 0x8 - a9fc: 0600 addi s0,sp,768 - a9fe: 7800 flw fs0,48(s0) - aa00: 7c00 flw fs0,56(s0) - aa02: 1e00 addi s0,sp,816 - aa04: cc9f 0008 d000 0xd0000008cc9f - aa0a: 0008 0x8 - aa0c: 0100 addi s0,sp,128 - aa0e: 5e00 lw s0,56(a2) - aa10: 08d0 addi a2,sp,84 - aa12: 0000 unimp - aa14: 08d8 addi a4,sp,84 - aa16: 0000 unimp - aa18: 0006 c.slli zero,0x1 - aa1a: 0078 addi a4,sp,12 - aa1c: 007c addi a5,sp,12 - aa1e: 9f1e add t5,t5,t2 - aa20: 08d8 addi a4,sp,84 - aa22: 0000 unimp - aa24: 0914 addi a3,sp,144 - aa26: 0000 unimp - aa28: 0001 nop - aa2a: 145e slli s0,s0,0x37 - aa2c: 0009 c.nop 2 - aa2e: 9800 0x9800 - aa30: 0009 c.nop 2 - aa32: 1400 addi s0,sp,544 - aa34: 7800 flw fs0,48(s0) - aa36: 7c00 flw fs0,56(s0) - aa38: 1e00 addi s0,sp,816 - aa3a: 008d0077 0x8d0077 - aa3e: 221e fld ft4,448(sp) - aa40: 008d addi ra,ra,3 - aa42: 007c addi a5,sp,12 - aa44: 401e 0x401e - aa46: 2225 jal ab6e <_start-0x7fff5492> - aa48: 989f 0009 a800 0xa8000009989f - aa4e: 0009 c.nop 2 - aa50: 1e00 addi s0,sp,816 - aa52: 8500 0x8500 - aa54: 917f 0x917f - aa56: 7ef8 flw fa4,124(a3) - aa58: 1a06 slli s4,s4,0x21 - aa5a: 0078 addi a4,sp,12 - aa5c: 771e flw fa4,228(sp) - aa5e: 8d00 0x8d00 - aa60: 1e00 addi s0,sp,816 - aa62: 8522 mv a0,s0 - aa64: 917f 0x917f - aa66: 7ef8 flw fa4,124(a3) - aa68: 1a06 slli s4,s4,0x21 - aa6a: 008d addi ra,ra,3 - aa6c: 401e 0x401e - aa6e: 2225 jal ab96 <_start-0x7fff546a> - aa70: a89f 0009 dc00 0xdc000009a89f - aa76: 0009 c.nop 2 - aa78: 2200 fld fs0,0(a2) - aa7a: 8500 0x8500 - aa7c: 917f 0x917f - aa7e: 7ef8 flw fa4,124(a3) - aa80: 1a06 slli s4,s4,0x21 - aa82: 0078 addi a4,sp,12 - aa84: 911e add sp,sp,t2 - aa86: 7ef8 flw fa4,124(a3) - aa88: 4006 0x4006 - aa8a: 8d25 xor a0,a0,s1 - aa8c: 1e00 addi s0,sp,816 - aa8e: 8522 mv a0,s0 - aa90: 917f 0x917f - aa92: 7ef8 flw fa4,124(a3) - aa94: 1a06 slli s4,s4,0x21 - aa96: 008d addi ra,ra,3 - aa98: 401e 0x401e - aa9a: 2225 jal abc2 <_start-0x7fff543e> - aa9c: dc9f 0009 e000 0xe0000009dc9f - aaa2: 0009 c.nop 2 - aaa4: 2c00 fld fs0,24(s0) - aaa6: 8500 0x8500 - aaa8: 917f 0x917f - aaaa: 7ef8 flw fa4,124(a3) - aaac: 1a06 slli s4,s4,0x21 - aaae: 0078 addi a4,sp,12 - aab0: 851e mv a0,t2 - aab2: 917f 0x917f - aab4: 7f88 flw fa0,56(a5) - aab6: 1a06 slli s4,s4,0x21 - aab8: f891 bnez s1,a9cc <_start-0x7fff5634> - aaba: 067e slli a2,a2,0x1f - aabc: 2540 fld fs0,136(a0) - aabe: 221e fld ft4,448(sp) - aac0: 7f85 lui t6,0xfffe1 - aac2: 8891 andi s1,s1,4 - aac4: 067f 0x67f - aac6: 851a mv a0,t1 - aac8: 917f 0x917f - aaca: 7ef8 flw fa4,124(a3) - aacc: 1a06 slli s4,s4,0x21 - aace: 401e 0x401e - aad0: 2225 jal abf8 <_start-0x7fff5408> - aad2: e09f 0009 ec00 0xec000009e09f - aad8: 0009 c.nop 2 - aada: 2c00 fld fs0,24(s0) - aadc: 9100 0x9100 - aade: 7ef8 flw fa4,124(a3) - aae0: 7906 flw fs2,96(sp) - aae2: 1a00 addi s0,sp,304 - aae4: 0078 addi a4,sp,12 - aae6: 911e add sp,sp,t2 - aae8: 7f88 flw fa0,56(a5) - aaea: 7906 flw fs2,96(sp) - aaec: 1a00 addi s0,sp,304 - aaee: f891 bnez s1,aa02 <_start-0x7fff55fe> - aaf0: 067e slli a2,a2,0x1f - aaf2: 2540 fld fs0,136(a0) - aaf4: 221e fld ft4,448(sp) - aaf6: 8891 andi s1,s1,4 - aaf8: 067f 0x67f - aafa: 0079 c.nop 30 - aafc: 911a add sp,sp,t1 - aafe: 7ef8 flw fa4,124(a3) - ab00: 7906 flw fs2,96(sp) - ab02: 1a00 addi s0,sp,304 - ab04: 401e 0x401e - ab06: 2225 jal ac2e <_start-0x7fff53d2> - ab08: ec9f 0009 4800 0x48000009ec9f - ab0e: 000a c.slli zero,0x2 - ab10: 2c00 fld fs0,24(s0) - ab12: 8400 0x8400 - ab14: 917f 0x917f - ab16: 7ef8 flw fa4,124(a3) - ab18: 1a06 slli s4,s4,0x21 - ab1a: 0078 addi a4,sp,12 - ab1c: 841e mv s0,t2 - ab1e: 917f 0x917f - ab20: 7f88 flw fa0,56(a5) - ab22: 1a06 slli s4,s4,0x21 - ab24: f891 bnez s1,aa38 <_start-0x7fff55c8> - ab26: 067e slli a2,a2,0x1f - ab28: 2540 fld fs0,136(a0) - ab2a: 221e fld ft4,448(sp) - ab2c: 7f84 flw fs1,56(a5) - ab2e: 8891 andi s1,s1,4 - ab30: 067f 0x67f - ab32: 841a mv s0,t1 - ab34: 917f 0x917f - ab36: 7ef8 flw fa4,124(a3) - ab38: 1a06 slli s4,s4,0x21 - ab3a: 401e 0x401e - ab3c: 2225 jal ac64 <_start-0x7fff539c> - ab3e: 489f 000a e000 0xe000000a489f - ab44: 000a c.slli zero,0x2 - ab46: 2c00 fld fs0,24(s0) - ab48: 9100 0x9100 - ab4a: 7ef8 flw fa4,124(a3) - ab4c: 7906 flw fs2,96(sp) - ab4e: 1a00 addi s0,sp,304 - ab50: 0078 addi a4,sp,12 - ab52: 911e add sp,sp,t2 - ab54: 7f88 flw fa0,56(a5) - ab56: 7906 flw fs2,96(sp) - ab58: 1a00 addi s0,sp,304 - ab5a: f891 bnez s1,aa6e <_start-0x7fff5592> - ab5c: 067e slli a2,a2,0x1f - ab5e: 2540 fld fs0,136(a0) - ab60: 221e fld ft4,448(sp) - ab62: 8891 andi s1,s1,4 - ab64: 067f 0x67f - ab66: 0079 c.nop 30 - ab68: 911a add sp,sp,t1 - ab6a: 7ef8 flw fa4,124(a3) - ab6c: 7906 flw fs2,96(sp) - ab6e: 1a00 addi s0,sp,304 - ab70: 401e 0x401e - ab72: 2225 jal ac9a <_start-0x7fff5366> - ab74: e09f 000a c400 0xc400000ae09f - ab7a: 2c00000b 0x2c00000b - ab7e: 8900 0x8900 - ab80: 917f 0x917f - ab82: 7ef8 flw fa4,124(a3) - ab84: 1a06 slli s4,s4,0x21 - ab86: 0078 addi a4,sp,12 - ab88: 891e mv s2,t2 - ab8a: 917f 0x917f - ab8c: 7f88 flw fa0,56(a5) - ab8e: 1a06 slli s4,s4,0x21 - ab90: f891 bnez s1,aaa4 <_start-0x7fff555c> - ab92: 067e slli a2,a2,0x1f - ab94: 2540 fld fs0,136(a0) - ab96: 221e fld ft4,448(sp) - ab98: 7f89 lui t6,0xfffe2 - ab9a: 8891 andi s1,s1,4 - ab9c: 067f 0x67f - ab9e: 891a mv s2,t1 - aba0: 917f 0x917f - aba2: 7ef8 flw fa4,124(a3) - aba4: 1a06 slli s4,s4,0x21 - aba6: 401e 0x401e - aba8: 2225 jal acd0 <_start-0x7fff5330> - abaa: a89f 000d b400 0xb400000da89f - abb0: 000d c.nop 3 - abb2: 2c00 fld fs0,24(s0) - abb4: 8900 0x8900 - abb6: 917f 0x917f - abb8: 7ef8 flw fa4,124(a3) - abba: 1a06 slli s4,s4,0x21 - abbc: 0078 addi a4,sp,12 - abbe: 891e mv s2,t2 - abc0: 917f 0x917f - abc2: 7f88 flw fa0,56(a5) - abc4: 1a06 slli s4,s4,0x21 - abc6: f891 bnez s1,aada <_start-0x7fff5526> - abc8: 067e slli a2,a2,0x1f - abca: 2540 fld fs0,136(a0) - abcc: 221e fld ft4,448(sp) - abce: 7f89 lui t6,0xfffe2 - abd0: 8891 andi s1,s1,4 - abd2: 067f 0x67f - abd4: 891a mv s2,t1 - abd6: 917f 0x917f - abd8: 7ef8 flw fa4,124(a3) - abda: 1a06 slli s4,s4,0x21 - abdc: 401e 0x401e - abde: 2225 jal ad06 <_start-0x7fff52fa> - abe0: 009f 0000 0000 0x9f - abe6: 0000 unimp - abe8: d800 sw s0,48(s0) - abea: 0008 0x8 - abec: f400 fsw fs0,40(s0) - abee: 0008 0x8 - abf0: 0100 addi s0,sp,128 - abf2: 6100 flw fs0,0(a0) - ... - abfc: 08c0 addi s0,sp,84 - abfe: 0000 unimp - ac00: 0bc4 addi s1,sp,468 - ac02: 0000 unimp - ac04: f8910003 lb zero,-119(sp) - ac08: a87e fsd ft11,16(sp) - ac0a: 000d c.nop 3 - ac0c: b400 fsd fs0,40(s0) - ac0e: 000d c.nop 3 - ac10: 0300 addi s0,sp,384 - ac12: 9100 0x9100 - ac14: 7ef8 flw fa4,124(a3) - ... - ac1e: 08c0 addi s0,sp,84 - ac20: 0000 unimp - ac22: 09a8 addi a0,sp,216 - ac24: 0000 unimp - ac26: 0001 nop - ac28: 0009a857 vredsum.vs v16,v0,v19,v0.t - ac2c: c400 sw s0,8(s0) - ac2e: 0300000b 0x300000b - ac32: 9100 0x9100 - ac34: 7efa flw ft9,188(sp) - ac36: 0da8 addi a0,sp,728 - ac38: 0000 unimp - ac3a: 0db4 addi a3,sp,728 - ac3c: 0000 unimp - ac3e: fa910003 lb zero,-87(sp) - ac42: 007e c.slli zero,0x1f - ac44: 0000 unimp - ac46: 0000 unimp - ac48: 0000 unimp - ac4a: c000 sw s0,0(s0) - ac4c: 0008 0x8 - ac4e: c400 sw s0,8(s0) - ac50: 0100000b 0x100000b - ac54: 5800 lw s0,48(s0) - ac56: 0da8 addi a0,sp,728 - ac58: 0000 unimp - ac5a: 0db4 addi a3,sp,728 - ac5c: 0000 unimp - ac5e: 0001 nop - ac60: 0058 addi a4,sp,4 - ac62: 0000 unimp - ac64: 0000 unimp - ac66: 0000 unimp - ac68: 0c00 addi s0,sp,528 - ac6a: 0009 c.nop 2 - ac6c: 3800 fld fs0,48(s0) - ac6e: 0009 c.nop 2 - ac70: 0100 addi s0,sp,128 - ac72: 6000 flw fs0,0(s0) - ac74: 0938 addi a4,sp,152 - ac76: 0000 unimp - ac78: 0958 addi a4,sp,148 - ac7a: 0000 unimp - ac7c: f491000b 0xf491000b - ac80: 067e slli a2,a2,0x1f - ac82: 0084 addi s1,sp,64 - ac84: 761a flw fa2,164(sp) - ac86: 1e00 addi s0,sp,816 - ac88: 589f 0009 e000 0xe0000009589f - ac8e: 0009 c.nop 2 - ac90: 0b00 addi s0,sp,400 - ac92: 8500 0x8500 - ac94: 917f 0x917f - ac96: 7ef4 flw fa3,124(a3) - ac98: 1a06 slli s4,s4,0x21 - ac9a: 0076 c.slli zero,0x1d - ac9c: 9f1e add t5,t5,t2 - ac9e: 09e0 addi s0,sp,220 - aca0: 0000 unimp - aca2: 09ec addi a1,sp,220 - aca4: 0000 unimp - aca6: f491000b 0xf491000b - acaa: 067e slli a2,a2,0x1f - acac: 0079 c.nop 30 - acae: 761a flw fa2,164(sp) - acb0: 1e00 addi s0,sp,816 - acb2: ec9f 0009 4800 0x48000009ec9f - acb8: 000a c.slli zero,0x2 - acba: 0b00 addi s0,sp,400 - acbc: 8400 0x8400 - acbe: 917f 0x917f - acc0: 7ef4 flw fa3,124(a3) - acc2: 1a06 slli s4,s4,0x21 - acc4: 0076 c.slli zero,0x1d - acc6: 9f1e add t5,t5,t2 - acc8: 0a48 addi a0,sp,276 - acca: 0000 unimp - accc: 0ab4 addi a3,sp,344 - acce: 0000 unimp - acd0: f491000b 0xf491000b - acd4: 067e slli a2,a2,0x1f - acd6: 0079 c.nop 30 - acd8: 761a flw fa2,164(sp) - acda: 1e00 addi s0,sp,816 - acdc: b49f 000a e000 0xe000000ab49f - ace2: 000a c.slli zero,0x2 - ace4: 1000 addi s0,sp,32 - ace6: 9100 0x9100 - ace8: 7f8c flw fa1,56(a5) - acea: 7906 flw fs2,96(sp) - acec: 1a00 addi s0,sp,304 - acee: f491 bnez s1,abfa <_start-0x7fff5406> - acf0: 067e slli a2,a2,0x1f - acf2: 0079 c.nop 30 - acf4: 1e1a slli t3,t3,0x26 - acf6: e09f 000a c400 0xc400000ae09f - acfc: 1000000b 0x1000000b - ad00: 8900 0x8900 - ad02: 917f 0x917f - ad04: 7f8c flw fa1,56(a5) - ad06: 1a06 slli s4,s4,0x21 - ad08: 7f89 lui t6,0xfffe2 - ad0a: f491 bnez s1,ac16 <_start-0x7fff53ea> - ad0c: 067e slli a2,a2,0x1f - ad0e: 1e1a slli t3,t3,0x26 - ad10: a89f 000d b400 0xb400000da89f - ad16: 000d c.nop 3 - ad18: 1000 addi s0,sp,32 - ad1a: 8900 0x8900 - ad1c: 917f 0x917f - ad1e: 7f8c flw fa1,56(a5) - ad20: 1a06 slli s4,s4,0x21 - ad22: 7f89 lui t6,0xfffe2 - ad24: f491 bnez s1,ac30 <_start-0x7fff53d0> - ad26: 067e slli a2,a2,0x1f - ad28: 1e1a slli t3,t3,0x26 - ad2a: 009f 0000 0000 0x9f - ad30: 0000 unimp - ad32: 0c00 addi s0,sp,528 - ad34: 0009 c.nop 2 - ad36: 1000 addi s0,sp,32 - ad38: 0009 c.nop 2 - ad3a: 0600 addi s0,sp,768 - ad3c: 7500 flw fs0,40(a0) - ad3e: 7b00 flw fs0,48(a4) - ad40: 1e00 addi s0,sp,816 - ad42: 109f 0009 1800 0x18000009109f - ad48: 0009 c.nop 2 - ad4a: 0100 addi s0,sp,128 - ad4c: 5b00 lw s0,48(a4) - ad4e: 0918 addi a4,sp,144 - ad50: 0000 unimp - ad52: 0920 addi s0,sp,152 - ad54: 0000 unimp - ad56: 7f84000b 0x7f84000b - ad5a: f491 bnez s1,ac66 <_start-0x7fff539a> - ad5c: 067e slli a2,a2,0x1f - ad5e: 751a flw fa0,164(sp) - ad60: 1e00 addi s0,sp,816 - ad62: 209f 0009 4800 0x48000009209f - ad68: 0009 c.nop 2 - ad6a: 0100 addi s0,sp,128 - ad6c: 5e00 lw s0,56(a2) - ad6e: 0948 addi a0,sp,148 - ad70: 0000 unimp - ad72: 0958 addi a4,sp,148 - ad74: 0000 unimp - ad76: 0022 c.slli zero,0x8 - ad78: f491 bnez s1,ac84 <_start-0x7fff537c> - ad7a: 067e slli a2,a2,0x1f - ad7c: 0084 addi s1,sp,64 - ad7e: 751a flw fa0,164(sp) - ad80: 1e00 addi s0,sp,816 - ad82: f491 bnez s1,ac8e <_start-0x7fff5372> - ad84: 067e slli a2,a2,0x1f - ad86: 2540 fld fs0,136(a0) - ad88: 0076 c.slli zero,0x1d - ad8a: 221e fld ft4,448(sp) - ad8c: f491 bnez s1,ac98 <_start-0x7fff5368> - ad8e: 067e slli a2,a2,0x1f - ad90: 0084 addi s1,sp,64 - ad92: 761a flw fa2,164(sp) - ad94: 1e00 addi s0,sp,816 - ad96: 2540 fld fs0,136(a0) - ad98: 9f22 add t5,t5,s0 - ad9a: 0958 addi a4,sp,148 - ad9c: 0000 unimp - ad9e: 09e0 addi s0,sp,220 - ada0: 0000 unimp - ada2: 0022 c.slli zero,0x8 - ada4: 7f85 lui t6,0xfffe1 - ada6: f491 bnez s1,acb2 <_start-0x7fff534e> - ada8: 067e slli a2,a2,0x1f - adaa: 751a flw fa0,164(sp) - adac: 1e00 addi s0,sp,816 - adae: f491 bnez s1,acba <_start-0x7fff5346> - adb0: 067e slli a2,a2,0x1f - adb2: 2540 fld fs0,136(a0) - adb4: 0076 c.slli zero,0x1d - adb6: 221e fld ft4,448(sp) - adb8: 7f85 lui t6,0xfffe1 - adba: f491 bnez s1,acc6 <_start-0x7fff533a> - adbc: 067e slli a2,a2,0x1f - adbe: 761a flw fa2,164(sp) - adc0: 1e00 addi s0,sp,816 - adc2: 2540 fld fs0,136(a0) - adc4: 9f22 add t5,t5,s0 - adc6: 09e0 addi s0,sp,220 - adc8: 0000 unimp - adca: 09ec addi a1,sp,220 - adcc: 0000 unimp - adce: 0022 c.slli zero,0x8 - add0: f491 bnez s1,acdc <_start-0x7fff5324> - add2: 067e slli a2,a2,0x1f - add4: 0079 c.nop 30 - add6: 751a flw fa0,164(sp) - add8: 1e00 addi s0,sp,816 - adda: f491 bnez s1,ace6 <_start-0x7fff531a> - addc: 067e slli a2,a2,0x1f - adde: 2540 fld fs0,136(a0) - ade0: 0076 c.slli zero,0x1d - ade2: 221e fld ft4,448(sp) - ade4: f491 bnez s1,acf0 <_start-0x7fff5310> - ade6: 067e slli a2,a2,0x1f - ade8: 0079 c.nop 30 - adea: 761a flw fa2,164(sp) - adec: 1e00 addi s0,sp,816 - adee: 2540 fld fs0,136(a0) - adf0: 9f22 add t5,t5,s0 - adf2: 09ec addi a1,sp,220 - adf4: 0000 unimp - adf6: 0a48 addi a0,sp,276 - adf8: 0000 unimp - adfa: 0022 c.slli zero,0x8 - adfc: 7f84 flw fs1,56(a5) - adfe: f491 bnez s1,ad0a <_start-0x7fff52f6> - ae00: 067e slli a2,a2,0x1f - ae02: 751a flw fa0,164(sp) - ae04: 1e00 addi s0,sp,816 - ae06: f491 bnez s1,ad12 <_start-0x7fff52ee> - ae08: 067e slli a2,a2,0x1f - ae0a: 2540 fld fs0,136(a0) - ae0c: 0076 c.slli zero,0x1d - ae0e: 221e fld ft4,448(sp) - ae10: 7f84 flw fs1,56(a5) - ae12: f491 bnez s1,ad1e <_start-0x7fff52e2> - ae14: 067e slli a2,a2,0x1f - ae16: 761a flw fa2,164(sp) - ae18: 1e00 addi s0,sp,816 - ae1a: 2540 fld fs0,136(a0) - ae1c: 9f22 add t5,t5,s0 - ae1e: 0a48 addi a0,sp,276 - ae20: 0000 unimp - ae22: 0ab4 addi a3,sp,344 - ae24: 0000 unimp - ae26: 0022 c.slli zero,0x8 - ae28: f491 bnez s1,ad34 <_start-0x7fff52cc> - ae2a: 067e slli a2,a2,0x1f - ae2c: 0079 c.nop 30 - ae2e: 751a flw fa0,164(sp) - ae30: 1e00 addi s0,sp,816 - ae32: f491 bnez s1,ad3e <_start-0x7fff52c2> - ae34: 067e slli a2,a2,0x1f - ae36: 2540 fld fs0,136(a0) - ae38: 0076 c.slli zero,0x1d - ae3a: 221e fld ft4,448(sp) - ae3c: f491 bnez s1,ad48 <_start-0x7fff52b8> - ae3e: 067e slli a2,a2,0x1f - ae40: 0079 c.nop 30 - ae42: 761a flw fa2,164(sp) - ae44: 1e00 addi s0,sp,816 - ae46: 2540 fld fs0,136(a0) - ae48: 9f22 add t5,t5,s0 - ae4a: 0ab4 addi a3,sp,344 - ae4c: 0000 unimp - ae4e: 0acc addi a1,sp,340 - ae50: 0000 unimp - ae52: 002c addi a1,sp,8 - ae54: f491 bnez s1,ad60 <_start-0x7fff52a0> - ae56: 067e slli a2,a2,0x1f - ae58: 0079 c.nop 30 - ae5a: 751a flw fa0,164(sp) - ae5c: 1e00 addi s0,sp,816 - ae5e: 8c91 sub s1,s1,a2 - ae60: 067f 0x67f - ae62: 0079 c.nop 30 - ae64: 911a add sp,sp,t1 - ae66: 7ef4 flw fa3,124(a3) - ae68: 4006 0x4006 - ae6a: 1e25 addi t3,t3,-23 - ae6c: 9122 add sp,sp,s0 - ae6e: 7f8c flw fa1,56(a5) - ae70: 7906 flw fs2,96(sp) - ae72: 1a00 addi s0,sp,304 - ae74: f491 bnez s1,ad80 <_start-0x7fff5280> - ae76: 067e slli a2,a2,0x1f - ae78: 0079 c.nop 30 - ae7a: 1e1a slli t3,t3,0x26 - ae7c: 2540 fld fs0,136(a0) - ae7e: 9f22 add t5,t5,s0 - ae80: 0acc addi a1,sp,340 - ae82: 0000 unimp - ae84: 0ae0 addi s0,sp,348 - ae86: 0000 unimp - ae88: 0030 addi a2,sp,8 - ae8a: f491 bnez s1,ad96 <_start-0x7fff526a> - ae8c: 067e slli a2,a2,0x1f - ae8e: 0079 c.nop 30 - ae90: 911a add sp,sp,t1 - ae92: 7f8c flw fa1,56(a5) - ae94: 4006 0x4006 - ae96: 1e25 addi t3,t3,-23 - ae98: 8c91 sub s1,s1,a2 - ae9a: 067f 0x67f - ae9c: 0079 c.nop 30 - ae9e: 911a add sp,sp,t1 - aea0: 7ef4 flw fa3,124(a3) - aea2: 4006 0x4006 - aea4: 1e25 addi t3,t3,-23 - aea6: 9122 add sp,sp,s0 - aea8: 7f8c flw fa1,56(a5) - aeaa: 7906 flw fs2,96(sp) - aeac: 1a00 addi s0,sp,304 - aeae: f491 bnez s1,adba <_start-0x7fff5246> - aeb0: 067e slli a2,a2,0x1f - aeb2: 0079 c.nop 30 - aeb4: 1e1a slli t3,t3,0x26 - aeb6: 2540 fld fs0,136(a0) - aeb8: 9f22 add t5,t5,s0 - aeba: 0ae0 addi s0,sp,348 - aebc: 0000 unimp - aebe: 0bc4 addi s1,sp,468 - aec0: 0000 unimp - aec2: 0030 addi a2,sp,8 - aec4: 7f89 lui t6,0xfffe2 - aec6: f491 bnez s1,add2 <_start-0x7fff522e> - aec8: 067e slli a2,a2,0x1f - aeca: 911a add sp,sp,t1 - aecc: 7f8c flw fa1,56(a5) - aece: 4006 0x4006 - aed0: 1e25 addi t3,t3,-23 - aed2: 7f89 lui t6,0xfffe2 - aed4: 8c91 sub s1,s1,a2 - aed6: 067f 0x67f - aed8: 911a add sp,sp,t1 - aeda: 7ef4 flw fa3,124(a3) - aedc: 4006 0x4006 - aede: 1e25 addi t3,t3,-23 - aee0: 8922 mv s2,s0 - aee2: 917f 0x917f - aee4: 7f8c flw fa1,56(a5) - aee6: 1a06 slli s4,s4,0x21 - aee8: 7f89 lui t6,0xfffe2 - aeea: f491 bnez s1,adf6 <_start-0x7fff520a> - aeec: 067e slli a2,a2,0x1f - aeee: 1e1a slli t3,t3,0x26 - aef0: 2540 fld fs0,136(a0) - aef2: 9f22 add t5,t5,s0 - aef4: 0da8 addi a0,sp,728 - aef6: 0000 unimp - aef8: 0db4 addi a3,sp,728 - aefa: 0000 unimp - aefc: 0030 addi a2,sp,8 - aefe: 7f89 lui t6,0xfffe2 - af00: f491 bnez s1,ae0c <_start-0x7fff51f4> - af02: 067e slli a2,a2,0x1f - af04: 911a add sp,sp,t1 - af06: 7f8c flw fa1,56(a5) - af08: 4006 0x4006 - af0a: 1e25 addi t3,t3,-23 - af0c: 7f89 lui t6,0xfffe2 - af0e: 8c91 sub s1,s1,a2 - af10: 067f 0x67f - af12: 911a add sp,sp,t1 - af14: 7ef4 flw fa3,124(a3) - af16: 4006 0x4006 - af18: 1e25 addi t3,t3,-23 - af1a: 8922 mv s2,s0 - af1c: 917f 0x917f - af1e: 7f8c flw fa1,56(a5) - af20: 1a06 slli s4,s4,0x21 - af22: 7f89 lui t6,0xfffe2 - af24: f491 bnez s1,ae30 <_start-0x7fff51d0> - af26: 067e slli a2,a2,0x1f - af28: 1e1a slli t3,t3,0x26 - af2a: 2540 fld fs0,136(a0) - af2c: 9f22 add t5,t5,s0 - ... - af36: 090c addi a1,sp,144 - af38: 0000 unimp - af3a: 092c addi a1,sp,152 - af3c: 0000 unimp - af3e: 0001 nop - af40: 2c65 jal b1f8 <_start-0x7fff4e08> - af42: 0009 c.nop 2 - af44: b400 fsd fs0,40(s0) - af46: 000a c.slli zero,0x2 - af48: 0a00 addi s0,sp,272 - af4a: 9100 0x9100 - af4c: 7ef4 flw fa3,124(a3) - af4e: 4006 0x4006 - af50: 7625 lui a2,0xfffe9 - af52: 1e00 addi s0,sp,816 - af54: b49f 000a e000 0xe000000ab49f - af5a: 000a c.slli zero,0x2 - af5c: 0f00 addi s0,sp,912 - af5e: 9100 0x9100 - af60: 7f8c flw fa1,56(a5) - af62: 7906 flw fs2,96(sp) - af64: 1a00 addi s0,sp,304 - af66: f491 bnez s1,ae72 <_start-0x7fff518e> - af68: 067e slli a2,a2,0x1f - af6a: 2540 fld fs0,136(a0) - af6c: 9f1e add t5,t5,t2 - af6e: 0ae0 addi s0,sp,348 - af70: 0000 unimp - af72: 0bc4 addi s1,sp,468 - af74: 0000 unimp - af76: 7f89000f 0x7f89000f - af7a: 8c91 sub s1,s1,a2 - af7c: 067f 0x67f - af7e: 911a add sp,sp,t1 - af80: 7ef4 flw fa3,124(a3) - af82: 4006 0x4006 - af84: 1e25 addi t3,t3,-23 - af86: a89f 000d b400 0xb400000da89f - af8c: 000d c.nop 3 - af8e: 0f00 addi s0,sp,912 - af90: 8900 0x8900 - af92: 917f 0x917f - af94: 7f8c flw fa1,56(a5) - af96: 1a06 slli s4,s4,0x21 - af98: f491 bnez s1,aea4 <_start-0x7fff515c> - af9a: 067e slli a2,a2,0x1f - af9c: 2540 fld fs0,136(a0) - af9e: 9f1e add t5,t5,t2 - ... - afa8: 0920 addi s0,sp,152 - afaa: 0000 unimp - afac: 093c addi a5,sp,152 - afae: 0000 unimp - afb0: 0001 nop - afb2: 0062 c.slli zero,0x18 - afb4: 0000 unimp - afb6: 0000 unimp - afb8: 0000 unimp - afba: 0800 addi s0,sp,16 - afbc: 0009 c.nop 2 - afbe: 2000 fld fs0,0(s0) - afc0: 0009 c.nop 2 - afc2: 0100 addi s0,sp,128 - afc4: 6200 flw fs0,0(a2) - afc6: 0920 addi s0,sp,152 - afc8: 0000 unimp - afca: 0bc4 addi s1,sp,468 - afcc: 0000 unimp - afce: f6910003 lb zero,-151(sp) - afd2: a87e fsd ft11,16(sp) - afd4: 000d c.nop 3 - afd6: b400 fsd fs0,40(s0) - afd8: 000d c.nop 3 - afda: 0300 addi s0,sp,384 - afdc: 9100 0x9100 - afde: 7ef6 flw ft9,124(sp) - ... - afe8: 0908 addi a0,sp,144 - afea: 0000 unimp - afec: 0acc addi a1,sp,340 - afee: 0000 unimp - aff0: 0001 nop - aff2: cc55 beqz s0,b0ae <_start-0x7fff4f52> - aff4: 000a c.slli zero,0x2 - aff6: c400 sw s0,8(s0) - aff8: 0300000b 0x300000b - affc: 9100 0x9100 - affe: 7f8e flw ft11,224(sp) - b000: 0da8 addi a0,sp,728 - b002: 0000 unimp - b004: 0db4 addi a3,sp,728 - b006: 0000 unimp - b008: 8e910003 lb zero,-1815(sp) - b00c: 007f 0x7f - b00e: 0000 unimp - b010: 0000 unimp - b012: 0000 unimp - b014: 4c00 lw s0,24(s0) - b016: 0009 c.nop 2 - b018: 8400 0x8400 - b01a: 0009 c.nop 2 - b01c: 0100 addi s0,sp,128 - b01e: 5e00 lw s0,56(a2) - b020: 0984 addi s1,sp,208 - b022: 0000 unimp - b024: 09e0 addi s0,sp,220 - b026: 0000 unimp - b028: 7f85000b 0x7f85000b - b02c: 8491 srai s1,s1,0x4 - b02e: 067f 0x67f - b030: 831a mv t1,t1 - b032: 1e00 addi s0,sp,816 - b034: e09f 0009 ec00 0xec000009e09f - b03a: 0009 c.nop 2 - b03c: 0b00 addi s0,sp,400 - b03e: 9100 0x9100 - b040: 7f84 flw fs1,56(a5) - b042: 7906 flw fs2,96(sp) - b044: 1a00 addi s0,sp,304 - b046: 9f1e0083 lb ra,-1551(t3) - b04a: 09ec addi a1,sp,220 - b04c: 0000 unimp - b04e: 0a48 addi a0,sp,276 - b050: 0000 unimp - b052: 7f84000b 0x7f84000b - b056: 8491 srai s1,s1,0x4 - b058: 067f 0x67f - b05a: 831a mv t1,t1 - b05c: 1e00 addi s0,sp,816 - b05e: 489f 000a c000 0xc000000a489f - b064: 000a c.slli zero,0x2 - b066: 0b00 addi s0,sp,400 - b068: 9100 0x9100 - b06a: 7f84 flw fs1,56(a5) - b06c: 7906 flw fs2,96(sp) - b06e: 1a00 addi s0,sp,304 - b070: 9f1e0083 lb ra,-1551(t3) - b074: 0ac0 addi s0,sp,340 - b076: 0000 unimp - b078: 0ae0 addi s0,sp,348 - b07a: 0000 unimp - b07c: 0010 0x10 - b07e: fc91 bnez s1,af9a <_start-0x7fff5066> - b080: 067e slli a2,a2,0x1f - b082: 0079 c.nop 30 - b084: 911a add sp,sp,t1 - b086: 7f84 flw fs1,56(a5) - b088: 7906 flw fs2,96(sp) - b08a: 1a00 addi s0,sp,304 - b08c: 9f1e add t5,t5,t2 - b08e: 0ae0 addi s0,sp,348 - b090: 0000 unimp - b092: 0bc4 addi s1,sp,468 - b094: 0000 unimp - b096: 0010 0x10 - b098: 7f89 lui t6,0xfffe2 - b09a: fc91 bnez s1,afb6 <_start-0x7fff504a> - b09c: 067e slli a2,a2,0x1f - b09e: 891a mv s2,t1 - b0a0: 917f 0x917f - b0a2: 7f84 flw fs1,56(a5) - b0a4: 1a06 slli s4,s4,0x21 - b0a6: 9f1e add t5,t5,t2 - b0a8: 0da8 addi a0,sp,728 - b0aa: 0000 unimp - b0ac: 0db4 addi a3,sp,728 - b0ae: 0000 unimp - b0b0: 0010 0x10 - b0b2: 7f89 lui t6,0xfffe2 - b0b4: fc91 bnez s1,afd0 <_start-0x7fff5030> - b0b6: 067e slli a2,a2,0x1f - b0b8: 891a mv s2,t1 - b0ba: 917f 0x917f - b0bc: 7f84 flw fs1,56(a5) - b0be: 1a06 slli s4,s4,0x21 - b0c0: 9f1e add t5,t5,t2 - ... - b0ca: 094c addi a1,sp,148 - b0cc: 0000 unimp - b0ce: 095c addi a5,sp,148 - b0d0: 0000 unimp - b0d2: 0006 c.slli zero,0x1 - b0d4: 0079 c.nop 30 - b0d6: 9f1e0083 lb ra,-1551(t3) - b0da: 095c addi a5,sp,148 - b0dc: 0000 unimp - b0de: 0960 addi s0,sp,156 - b0e0: 0000 unimp - b0e2: 0001 nop - b0e4: 6059 c.lui zero,0x16 - b0e6: 0009 c.nop 2 - b0e8: 6400 flw fs0,8(s0) - b0ea: 0009 c.nop 2 - b0ec: 0f00 addi s0,sp,912 - b0ee: 9100 0x9100 - b0f0: 7f84 flw fs1,56(a5) - b0f2: 4006 0x4006 - b0f4: 8325 srli a4,a4,0x9 - b0f6: 1e00 addi s0,sp,816 - b0f8: 007e c.slli zero,0x1f - b0fa: 2540 fld fs0,136(a0) - b0fc: 9f22 add t5,t5,s0 - b0fe: 0964 addi s1,sp,156 - b100: 0000 unimp - b102: 0988 addi a0,sp,208 - b104: 0000 unimp - b106: 0001 nop - b108: 8859 andi s0,s0,22 - b10a: 0009 c.nop 2 - b10c: e000 fsw fs0,0(s0) - b10e: 0009 c.nop 2 - b110: 2200 fld fs0,0(a2) - b112: 9100 0x9100 - b114: 7f84 flw fs1,56(a5) - b116: 4006 0x4006 - b118: 8325 srli a4,a4,0x9 - b11a: 1e00 addi s0,sp,816 - b11c: 7f85 lui t6,0xfffe1 - b11e: 8491 srai s1,s1,0x4 - b120: 067f 0x67f - b122: 8f1a mv t5,t1 - b124: 1e00 addi s0,sp,816 - b126: 8522 mv a0,s0 - b128: 917f 0x917f - b12a: 7f84 flw fs1,56(a5) - b12c: 1a06 slli s4,s4,0x21 - b12e: 401e0083 lb ra,1025(t3) - b132: 2225 jal b25a <_start-0x7fff4da6> - b134: e09f 0009 ec00 0xec000009e09f - b13a: 0009 c.nop 2 - b13c: 2200 fld fs0,0(a2) - b13e: 9100 0x9100 - b140: 7f84 flw fs1,56(a5) - b142: 4006 0x4006 - b144: 8325 srli a4,a4,0x9 - b146: 1e00 addi s0,sp,816 - b148: 8491 srai s1,s1,0x4 - b14a: 067f 0x67f - b14c: 0079 c.nop 30 - b14e: 8f1a mv t5,t1 - b150: 1e00 addi s0,sp,816 - b152: 9122 add sp,sp,s0 - b154: 7f84 flw fs1,56(a5) - b156: 7906 flw fs2,96(sp) - b158: 1a00 addi s0,sp,304 - b15a: 401e0083 lb ra,1025(t3) - b15e: 2225 jal b286 <_start-0x7fff4d7a> - b160: ec9f 0009 4800 0x48000009ec9f - b166: 000a c.slli zero,0x2 - b168: 2200 fld fs0,0(a2) - b16a: 9100 0x9100 - b16c: 7f84 flw fs1,56(a5) - b16e: 4006 0x4006 - b170: 8325 srli a4,a4,0x9 - b172: 1e00 addi s0,sp,816 - b174: 7f84 flw fs1,56(a5) - b176: 8491 srai s1,s1,0x4 - b178: 067f 0x67f - b17a: 8f1a mv t5,t1 - b17c: 1e00 addi s0,sp,816 - b17e: 8422 mv s0,s0 - b180: 917f 0x917f - b182: 7f84 flw fs1,56(a5) - b184: 1a06 slli s4,s4,0x21 - b186: 401e0083 lb ra,1025(t3) - b18a: 2225 jal b2b2 <_start-0x7fff4d4e> - b18c: 489f 000a c000 0xc000000a489f - b192: 000a c.slli zero,0x2 - b194: 2200 fld fs0,0(a2) - b196: 9100 0x9100 - b198: 7f84 flw fs1,56(a5) - b19a: 4006 0x4006 - b19c: 8325 srli a4,a4,0x9 - b19e: 1e00 addi s0,sp,816 - b1a0: 8491 srai s1,s1,0x4 - b1a2: 067f 0x67f - b1a4: 0079 c.nop 30 - b1a6: 8f1a mv t5,t1 - b1a8: 1e00 addi s0,sp,816 - b1aa: 9122 add sp,sp,s0 - b1ac: 7f84 flw fs1,56(a5) - b1ae: 7906 flw fs2,96(sp) - b1b0: 1a00 addi s0,sp,304 - b1b2: 401e0083 lb ra,1025(t3) - b1b6: 2225 jal b2de <_start-0x7fff4d22> - b1b8: c09f 000a c800 0xc800000ac09f - b1be: 000a c.slli zero,0x2 - b1c0: 2c00 fld fs0,24(s0) - b1c2: 9100 0x9100 - b1c4: 7efc flw fa5,124(a3) - b1c6: 7906 flw fs2,96(sp) - b1c8: 1a00 addi s0,sp,304 - b1ca: 8491 srai s1,s1,0x4 - b1cc: 067f 0x67f - b1ce: 2540 fld fs0,136(a0) - b1d0: 911e add sp,sp,t2 - b1d2: 7f84 flw fs1,56(a5) - b1d4: 7906 flw fs2,96(sp) - b1d6: 1a00 addi s0,sp,304 - b1d8: 221e008f 0x221e008f - b1dc: fc91 bnez s1,b0f8 <_start-0x7fff4f08> - b1de: 067e slli a2,a2,0x1f - b1e0: 0079 c.nop 30 - b1e2: 911a add sp,sp,t1 - b1e4: 7f84 flw fs1,56(a5) - b1e6: 7906 flw fs2,96(sp) - b1e8: 1a00 addi s0,sp,304 - b1ea: 401e 0x401e - b1ec: 2225 jal b314 <_start-0x7fff4cec> - b1ee: c89f 000a e000 0xe000000ac89f - b1f4: 000a c.slli zero,0x2 - b1f6: 3000 fld fs0,32(s0) - b1f8: 9100 0x9100 - b1fa: 7efc flw fa5,124(a3) - b1fc: 7906 flw fs2,96(sp) - b1fe: 1a00 addi s0,sp,304 - b200: 8491 srai s1,s1,0x4 - b202: 067f 0x67f - b204: 2540 fld fs0,136(a0) - b206: 911e add sp,sp,t2 - b208: 7f84 flw fs1,56(a5) - b20a: 7906 flw fs2,96(sp) - b20c: 1a00 addi s0,sp,304 - b20e: fc91 bnez s1,b12a <_start-0x7fff4ed6> - b210: 067e slli a2,a2,0x1f - b212: 2540 fld fs0,136(a0) - b214: 221e fld ft4,448(sp) - b216: fc91 bnez s1,b132 <_start-0x7fff4ece> - b218: 067e slli a2,a2,0x1f - b21a: 0079 c.nop 30 - b21c: 911a add sp,sp,t1 - b21e: 7f84 flw fs1,56(a5) - b220: 7906 flw fs2,96(sp) - b222: 1a00 addi s0,sp,304 - b224: 401e 0x401e - b226: 2225 jal b34e <_start-0x7fff4cb2> - b228: e09f 000a c400 0xc400000ae09f - b22e: 3000000b 0x3000000b - b232: 8900 0x8900 - b234: 917f 0x917f - b236: 7efc flw fa5,124(a3) - b238: 1a06 slli s4,s4,0x21 - b23a: 8491 srai s1,s1,0x4 - b23c: 067f 0x67f - b23e: 2540 fld fs0,136(a0) - b240: 891e mv s2,t2 - b242: 917f 0x917f - b244: 7f84 flw fs1,56(a5) - b246: 1a06 slli s4,s4,0x21 - b248: fc91 bnez s1,b164 <_start-0x7fff4e9c> - b24a: 067e slli a2,a2,0x1f - b24c: 2540 fld fs0,136(a0) - b24e: 221e fld ft4,448(sp) - b250: 7f89 lui t6,0xfffe2 - b252: fc91 bnez s1,b16e <_start-0x7fff4e92> - b254: 067e slli a2,a2,0x1f - b256: 891a mv s2,t1 - b258: 917f 0x917f - b25a: 7f84 flw fs1,56(a5) - b25c: 1a06 slli s4,s4,0x21 - b25e: 401e 0x401e - b260: 2225 jal b388 <_start-0x7fff4c78> - b262: a89f 000d b400 0xb400000da89f - b268: 000d c.nop 3 - b26a: 3000 fld fs0,32(s0) - b26c: 8900 0x8900 - b26e: 917f 0x917f - b270: 7efc flw fa5,124(a3) - b272: 1a06 slli s4,s4,0x21 - b274: 8491 srai s1,s1,0x4 - b276: 067f 0x67f - b278: 2540 fld fs0,136(a0) - b27a: 891e mv s2,t2 - b27c: 917f 0x917f - b27e: 7f84 flw fs1,56(a5) - b280: 1a06 slli s4,s4,0x21 - b282: fc91 bnez s1,b19e <_start-0x7fff4e62> - b284: 067e slli a2,a2,0x1f - b286: 2540 fld fs0,136(a0) - b288: 221e fld ft4,448(sp) - b28a: 7f89 lui t6,0xfffe2 - b28c: fc91 bnez s1,b1a8 <_start-0x7fff4e58> - b28e: 067e slli a2,a2,0x1f - b290: 891a mv s2,t1 - b292: 917f 0x917f - b294: 7f84 flw fs1,56(a5) - b296: 1a06 slli s4,s4,0x21 - b298: 401e 0x401e - b29a: 2225 jal b3c2 <_start-0x7fff4c3e> - b29c: 009f 0000 0000 0x9f - b2a2: 0000 unimp - b2a4: 5000 lw s0,32(s0) - b2a6: 0009 c.nop 2 - b2a8: 7c00 flw fs0,56(s0) - b2aa: 0009 c.nop 2 - b2ac: 0100 addi s0,sp,128 - b2ae: 6e00 flw fs0,24(a2) - b2b0: 097c addi a5,sp,156 - b2b2: 0000 unimp - b2b4: 09e0 addi s0,sp,220 - b2b6: 0000 unimp - b2b8: 7f85000b 0x7f85000b - b2bc: 8491 srai s1,s1,0x4 - b2be: 067f 0x67f - b2c0: 8f1a mv t5,t1 - b2c2: 1e00 addi s0,sp,816 - b2c4: e09f 0009 ec00 0xec000009e09f - b2ca: 0009 c.nop 2 - b2cc: 0b00 addi s0,sp,400 - b2ce: 9100 0x9100 - b2d0: 7f84 flw fs1,56(a5) - b2d2: 7906 flw fs2,96(sp) - b2d4: 1a00 addi s0,sp,304 - b2d6: 9f1e008f 0x9f1e008f - b2da: 09ec addi a1,sp,220 - b2dc: 0000 unimp - b2de: 0a48 addi a0,sp,276 - b2e0: 0000 unimp - b2e2: 7f84000b 0x7f84000b - b2e6: 8491 srai s1,s1,0x4 - b2e8: 067f 0x67f - b2ea: 8f1a mv t5,t1 - b2ec: 1e00 addi s0,sp,816 - b2ee: 489f 000a c800 0xc800000a489f - b2f4: 000a c.slli zero,0x2 - b2f6: 0b00 addi s0,sp,400 - b2f8: 9100 0x9100 - b2fa: 7f84 flw fs1,56(a5) - b2fc: 7906 flw fs2,96(sp) - b2fe: 1a00 addi s0,sp,304 - b300: 9f1e008f 0x9f1e008f - b304: 0ac8 addi a0,sp,340 - b306: 0000 unimp - b308: 0ae0 addi s0,sp,348 - b30a: 0000 unimp - b30c: 8491000f 0x8491000f - b310: 067f 0x67f - b312: 0079 c.nop 30 - b314: 911a add sp,sp,t1 - b316: 7efc flw fa5,124(a3) - b318: 4006 0x4006 - b31a: 1e25 addi t3,t3,-23 - b31c: e09f 000a c400 0xc400000ae09f - b322: 0f00000b 0xf00000b - b326: 8900 0x8900 - b328: 917f 0x917f - b32a: 7f84 flw fs1,56(a5) - b32c: 1a06 slli s4,s4,0x21 - b32e: fc91 bnez s1,b24a <_start-0x7fff4db6> - b330: 067e slli a2,a2,0x1f - b332: 2540 fld fs0,136(a0) - b334: 9f1e add t5,t5,t2 - b336: 0da8 addi a0,sp,728 - b338: 0000 unimp - b33a: 0db4 addi a3,sp,728 - b33c: 0000 unimp - b33e: 7f89000f 0x7f89000f - b342: 8491 srai s1,s1,0x4 - b344: 067f 0x67f - b346: 911a add sp,sp,t1 - b348: 7efc flw fa5,124(a3) - b34a: 4006 0x4006 - b34c: 1e25 addi t3,t3,-23 - b34e: 009f 0000 0000 0x9f - b354: 0000 unimp - b356: 5800 lw s0,48(s0) - b358: 0009 c.nop 2 - b35a: 7800 flw fs0,48(s0) - b35c: 0009 c.nop 2 - b35e: 0100 addi s0,sp,128 - b360: 6400 flw fs0,8(s0) - ... - b36a: 094c addi a1,sp,148 - b36c: 0000 unimp - b36e: 0ac8 addi a0,sp,340 - b370: 0000 unimp - b372: 0001 nop - b374: 000ac86f jal a6,b7374 <_start-0x7ff48c8c> - b378: c400 sw s0,8(s0) - b37a: 0300000b 0x300000b - b37e: 9100 0x9100 - b380: 7efe flw ft9,252(sp) - b382: 0da8 addi a0,sp,728 - b384: 0000 unimp - b386: 0db4 addi a3,sp,728 - b388: 0000 unimp - b38a: fe910003 lb zero,-23(sp) - b38e: 007e c.slli zero,0x1f - b390: 0000 unimp - b392: 0000 unimp - b394: 0000 unimp - b396: 4c00 lw s0,24(s0) - b398: 0009 c.nop 2 - b39a: 5c00 lw s0,56(s0) - b39c: 0009 c.nop 2 - b39e: 0100 addi s0,sp,128 - b3a0: 5900 lw s0,48(a0) - b3a2: 095c addi a5,sp,148 - b3a4: 0000 unimp - b3a6: 0bc4 addi s1,sp,468 - b3a8: 0000 unimp - b3aa: 86910003 lb zero,-1943(sp) - b3ae: a87f 0xa87f - b3b0: 000d c.nop 3 - b3b2: b400 fsd fs0,40(s0) - b3b4: 000d c.nop 3 - b3b6: 0300 addi s0,sp,384 - b3b8: 9100 0x9100 - b3ba: 7f86 flw ft11,96(sp) - ... - b3c4: 0994 addi a3,sp,208 - b3c6: 0000 unimp - b3c8: 09c8 addi a0,sp,212 - b3ca: 0000 unimp - b3cc: 0001 nop - b3ce: c86e sw s11,16(sp) - b3d0: 0009 c.nop 2 - b3d2: e000 fsw fs0,0(s0) - b3d4: 0009 c.nop 2 - b3d6: 0b00 addi s0,sp,400 - b3d8: 8500 0x8500 - b3da: 917f 0x917f - b3dc: 7ef8 flw fa4,124(a3) - b3de: 1a06 slli s4,s4,0x21 - b3e0: 0076 c.slli zero,0x1d - b3e2: 9f1e add t5,t5,t2 - b3e4: 09e0 addi s0,sp,220 - b3e6: 0000 unimp - b3e8: 09ec addi a1,sp,220 - b3ea: 0000 unimp - b3ec: f891000b 0xf891000b - b3f0: 067e slli a2,a2,0x1f - b3f2: 0079 c.nop 30 - b3f4: 761a flw fa2,164(sp) - b3f6: 1e00 addi s0,sp,816 - b3f8: ec9f 0009 4800 0x48000009ec9f - b3fe: 000a c.slli zero,0x2 - b400: 0b00 addi s0,sp,400 - b402: 8400 0x8400 - b404: 917f 0x917f - b406: 7ef8 flw fa4,124(a3) - b408: 1a06 slli s4,s4,0x21 - b40a: 0076 c.slli zero,0x1d - b40c: 9f1e add t5,t5,t2 - b40e: 0a48 addi a0,sp,276 - b410: 0000 unimp - b412: 0ab4 addi a3,sp,344 - b414: 0000 unimp - b416: f891000b 0xf891000b - b41a: 067e slli a2,a2,0x1f - b41c: 0079 c.nop 30 - b41e: 761a flw fa2,164(sp) - b420: 1e00 addi s0,sp,816 - b422: b49f 000a e000 0xe000000ab49f - b428: 000a c.slli zero,0x2 - b42a: 1000 addi s0,sp,32 - b42c: 9100 0x9100 - b42e: 7ef8 flw fa4,124(a3) - b430: 7906 flw fs2,96(sp) - b432: 1a00 addi s0,sp,304 - b434: 8c91 sub s1,s1,a2 - b436: 067f 0x67f - b438: 0079 c.nop 30 - b43a: 1e1a slli t3,t3,0x26 - b43c: e09f 000a c400 0xc400000ae09f - b442: 1000000b 0x1000000b - b446: 8900 0x8900 - b448: 917f 0x917f - b44a: 7ef8 flw fa4,124(a3) - b44c: 1a06 slli s4,s4,0x21 - b44e: 7f89 lui t6,0xfffe2 - b450: 8c91 sub s1,s1,a2 - b452: 067f 0x67f - b454: 1e1a slli t3,t3,0x26 - b456: a89f 000d b400 0xb400000da89f - b45c: 000d c.nop 3 - b45e: 1000 addi s0,sp,32 - b460: 8900 0x8900 - b462: 917f 0x917f - b464: 7ef8 flw fa4,124(a3) - b466: 1a06 slli s4,s4,0x21 - b468: 7f89 lui t6,0xfffe2 - b46a: 8c91 sub s1,s1,a2 - b46c: 067f 0x67f - b46e: 1e1a slli t3,t3,0x26 - b470: 009f 0000 0000 0x9f - b476: 0000 unimp - b478: 9400 0x9400 - b47a: 0009 c.nop 2 - b47c: 9800 0x9800 - b47e: 0009 c.nop 2 - b480: 0600 addi s0,sp,768 - b482: 7500 flw fs0,40(a0) - b484: 7c00 flw fs0,56(s0) - b486: 1e00 addi s0,sp,816 - b488: 989f 0009 a000 0xa0000009989f - b48e: 0009 c.nop 2 - b490: 0100 addi s0,sp,128 - b492: 5c00 lw s0,56(s0) - b494: 09a0 addi s0,sp,216 - b496: 0000 unimp - b498: 09a8 addi a0,sp,216 - b49a: 0000 unimp - b49c: 7f85000b 0x7f85000b - b4a0: f891 bnez s1,b3b4 <_start-0x7fff4c4c> - b4a2: 067e slli a2,a2,0x1f - b4a4: 751a flw fa0,164(sp) - b4a6: 1e00 addi s0,sp,816 - b4a8: a89f 0009 d400 0xd4000009a89f - b4ae: 0009 c.nop 2 - b4b0: 0100 addi s0,sp,128 - b4b2: 5c00 lw s0,56(s0) - b4b4: 09d4 addi a3,sp,212 - b4b6: 0000 unimp - b4b8: 09e0 addi s0,sp,220 - b4ba: 0000 unimp - b4bc: 0022 c.slli zero,0x8 - b4be: 7f85 lui t6,0xfffe1 - b4c0: f891 bnez s1,b3d4 <_start-0x7fff4c2c> - b4c2: 067e slli a2,a2,0x1f - b4c4: 751a flw fa0,164(sp) - b4c6: 1e00 addi s0,sp,816 - b4c8: f891 bnez s1,b3dc <_start-0x7fff4c24> - b4ca: 067e slli a2,a2,0x1f - b4cc: 2540 fld fs0,136(a0) - b4ce: 0076 c.slli zero,0x1d - b4d0: 221e fld ft4,448(sp) - b4d2: 7f85 lui t6,0xfffe1 - b4d4: f891 bnez s1,b3e8 <_start-0x7fff4c18> - b4d6: 067e slli a2,a2,0x1f - b4d8: 761a flw fa2,164(sp) - b4da: 1e00 addi s0,sp,816 - b4dc: 2540 fld fs0,136(a0) - b4de: 9f22 add t5,t5,s0 - b4e0: 09e0 addi s0,sp,220 - b4e2: 0000 unimp - b4e4: 09ec addi a1,sp,220 - b4e6: 0000 unimp - b4e8: 0022 c.slli zero,0x8 - b4ea: f891 bnez s1,b3fe <_start-0x7fff4c02> - b4ec: 067e slli a2,a2,0x1f - b4ee: 0079 c.nop 30 - b4f0: 751a flw fa0,164(sp) - b4f2: 1e00 addi s0,sp,816 - b4f4: f891 bnez s1,b408 <_start-0x7fff4bf8> - b4f6: 067e slli a2,a2,0x1f - b4f8: 2540 fld fs0,136(a0) - b4fa: 0076 c.slli zero,0x1d - b4fc: 221e fld ft4,448(sp) - b4fe: f891 bnez s1,b412 <_start-0x7fff4bee> - b500: 067e slli a2,a2,0x1f - b502: 0079 c.nop 30 - b504: 761a flw fa2,164(sp) - b506: 1e00 addi s0,sp,816 - b508: 2540 fld fs0,136(a0) - b50a: 9f22 add t5,t5,s0 - b50c: 09ec addi a1,sp,220 - b50e: 0000 unimp - b510: 0a48 addi a0,sp,276 - b512: 0000 unimp - b514: 0022 c.slli zero,0x8 - b516: 7f84 flw fs1,56(a5) - b518: f891 bnez s1,b42c <_start-0x7fff4bd4> - b51a: 067e slli a2,a2,0x1f - b51c: 751a flw fa0,164(sp) - b51e: 1e00 addi s0,sp,816 - b520: f891 bnez s1,b434 <_start-0x7fff4bcc> - b522: 067e slli a2,a2,0x1f - b524: 2540 fld fs0,136(a0) - b526: 0076 c.slli zero,0x1d - b528: 221e fld ft4,448(sp) - b52a: 7f84 flw fs1,56(a5) - b52c: f891 bnez s1,b440 <_start-0x7fff4bc0> - b52e: 067e slli a2,a2,0x1f - b530: 761a flw fa2,164(sp) - b532: 1e00 addi s0,sp,816 - b534: 2540 fld fs0,136(a0) - b536: 9f22 add t5,t5,s0 - b538: 0a48 addi a0,sp,276 - b53a: 0000 unimp - b53c: 0ab4 addi a3,sp,344 - b53e: 0000 unimp - b540: 0022 c.slli zero,0x8 - b542: f891 bnez s1,b456 <_start-0x7fff4baa> - b544: 067e slli a2,a2,0x1f - b546: 0079 c.nop 30 - b548: 751a flw fa0,164(sp) - b54a: 1e00 addi s0,sp,816 - b54c: f891 bnez s1,b460 <_start-0x7fff4ba0> - b54e: 067e slli a2,a2,0x1f - b550: 2540 fld fs0,136(a0) - b552: 0076 c.slli zero,0x1d - b554: 221e fld ft4,448(sp) - b556: f891 bnez s1,b46a <_start-0x7fff4b96> - b558: 067e slli a2,a2,0x1f - b55a: 0079 c.nop 30 - b55c: 761a flw fa2,164(sp) - b55e: 1e00 addi s0,sp,816 - b560: 2540 fld fs0,136(a0) - b562: 9f22 add t5,t5,s0 - b564: 0ab4 addi a3,sp,344 - b566: 0000 unimp - b568: 0acc addi a1,sp,340 - b56a: 0000 unimp - b56c: 002c addi a1,sp,8 - b56e: f891 bnez s1,b482 <_start-0x7fff4b7e> - b570: 067e slli a2,a2,0x1f - b572: 0079 c.nop 30 - b574: 751a flw fa0,164(sp) - b576: 1e00 addi s0,sp,816 - b578: 8c91 sub s1,s1,a2 - b57a: 067f 0x67f - b57c: 0079 c.nop 30 - b57e: 911a add sp,sp,t1 - b580: 7ef8 flw fa4,124(a3) - b582: 4006 0x4006 - b584: 1e25 addi t3,t3,-23 - b586: 9122 add sp,sp,s0 - b588: 7ef8 flw fa4,124(a3) - b58a: 7906 flw fs2,96(sp) - b58c: 1a00 addi s0,sp,304 - b58e: 8c91 sub s1,s1,a2 - b590: 067f 0x67f - b592: 0079 c.nop 30 - b594: 1e1a slli t3,t3,0x26 - b596: 2540 fld fs0,136(a0) - b598: 9f22 add t5,t5,s0 - b59a: 0acc addi a1,sp,340 - b59c: 0000 unimp - b59e: 0ae0 addi s0,sp,348 - b5a0: 0000 unimp - b5a2: 0030 addi a2,sp,8 - b5a4: f891 bnez s1,b4b8 <_start-0x7fff4b48> - b5a6: 067e slli a2,a2,0x1f - b5a8: 0079 c.nop 30 - b5aa: 911a add sp,sp,t1 - b5ac: 7f8c flw fa1,56(a5) - b5ae: 4006 0x4006 - b5b0: 1e25 addi t3,t3,-23 - b5b2: 8c91 sub s1,s1,a2 - b5b4: 067f 0x67f - b5b6: 0079 c.nop 30 - b5b8: 911a add sp,sp,t1 - b5ba: 7ef8 flw fa4,124(a3) - b5bc: 4006 0x4006 - b5be: 1e25 addi t3,t3,-23 - b5c0: 9122 add sp,sp,s0 - b5c2: 7ef8 flw fa4,124(a3) - b5c4: 7906 flw fs2,96(sp) - b5c6: 1a00 addi s0,sp,304 - b5c8: 8c91 sub s1,s1,a2 - b5ca: 067f 0x67f - b5cc: 0079 c.nop 30 - b5ce: 1e1a slli t3,t3,0x26 - b5d0: 2540 fld fs0,136(a0) - b5d2: 9f22 add t5,t5,s0 - b5d4: 0ae0 addi s0,sp,348 - b5d6: 0000 unimp - b5d8: 0bc4 addi s1,sp,468 - b5da: 0000 unimp - b5dc: 0030 addi a2,sp,8 - b5de: 7f89 lui t6,0xfffe2 - b5e0: f891 bnez s1,b4f4 <_start-0x7fff4b0c> - b5e2: 067e slli a2,a2,0x1f - b5e4: 911a add sp,sp,t1 - b5e6: 7f8c flw fa1,56(a5) - b5e8: 4006 0x4006 - b5ea: 1e25 addi t3,t3,-23 - b5ec: 7f89 lui t6,0xfffe2 - b5ee: 8c91 sub s1,s1,a2 - b5f0: 067f 0x67f - b5f2: 911a add sp,sp,t1 - b5f4: 7ef8 flw fa4,124(a3) - b5f6: 4006 0x4006 - b5f8: 1e25 addi t3,t3,-23 - b5fa: 8922 mv s2,s0 - b5fc: 917f 0x917f - b5fe: 7ef8 flw fa4,124(a3) - b600: 1a06 slli s4,s4,0x21 - b602: 7f89 lui t6,0xfffe2 - b604: 8c91 sub s1,s1,a2 - b606: 067f 0x67f - b608: 1e1a slli t3,t3,0x26 - b60a: 2540 fld fs0,136(a0) - b60c: 9f22 add t5,t5,s0 - b60e: 0da8 addi a0,sp,728 - b610: 0000 unimp - b612: 0db4 addi a3,sp,728 - b614: 0000 unimp - b616: 0030 addi a2,sp,8 - b618: 7f89 lui t6,0xfffe2 - b61a: f891 bnez s1,b52e <_start-0x7fff4ad2> - b61c: 067e slli a2,a2,0x1f - b61e: 911a add sp,sp,t1 - b620: 7f8c flw fa1,56(a5) - b622: 4006 0x4006 - b624: 1e25 addi t3,t3,-23 - b626: 7f89 lui t6,0xfffe2 - b628: 8c91 sub s1,s1,a2 - b62a: 067f 0x67f - b62c: 911a add sp,sp,t1 - b62e: 7ef8 flw fa4,124(a3) - b630: 4006 0x4006 - b632: 1e25 addi t3,t3,-23 - b634: 8922 mv s2,s0 - b636: 917f 0x917f - b638: 7ef8 flw fa4,124(a3) - b63a: 1a06 slli s4,s4,0x21 - b63c: 7f89 lui t6,0xfffe2 - b63e: 8c91 sub s1,s1,a2 - b640: 067f 0x67f - b642: 1e1a slli t3,t3,0x26 - b644: 2540 fld fs0,136(a0) - b646: 9f22 add t5,t5,s0 - ... - b650: 0994 addi a3,sp,208 - b652: 0000 unimp - b654: 09bc addi a5,sp,216 - b656: 0000 unimp - b658: 0001 nop - b65a: bc59 j b0f0 <_start-0x7fff4f10> - b65c: 0009 c.nop 2 - b65e: b400 fsd fs0,40(s0) - b660: 000a c.slli zero,0x2 - b662: 0a00 addi s0,sp,272 - b664: 9100 0x9100 - b666: 7ef8 flw fa4,124(a3) - b668: 4006 0x4006 - b66a: 7625 lui a2,0xfffe9 - b66c: 1e00 addi s0,sp,816 - b66e: b49f 000a e000 0xe000000ab49f - b674: 000a c.slli zero,0x2 - b676: 0f00 addi s0,sp,912 - b678: 9100 0x9100 - b67a: 7f8c flw fa1,56(a5) - b67c: 7906 flw fs2,96(sp) - b67e: 1a00 addi s0,sp,304 - b680: f891 bnez s1,b594 <_start-0x7fff4a6c> - b682: 067e slli a2,a2,0x1f - b684: 2540 fld fs0,136(a0) - b686: 9f1e add t5,t5,t2 - b688: 0ae0 addi s0,sp,348 - b68a: 0000 unimp - b68c: 0bc4 addi s1,sp,468 - b68e: 0000 unimp - b690: 7f89000f 0x7f89000f - b694: 8c91 sub s1,s1,a2 - b696: 067f 0x67f - b698: 911a add sp,sp,t1 - b69a: 7ef8 flw fa4,124(a3) - b69c: 4006 0x4006 - b69e: 1e25 addi t3,t3,-23 - b6a0: a89f 000d b400 0xb400000da89f - b6a6: 000d c.nop 3 - b6a8: 0f00 addi s0,sp,912 - b6aa: 8900 0x8900 - b6ac: 917f 0x917f - b6ae: 7f8c flw fa1,56(a5) - b6b0: 1a06 slli s4,s4,0x21 - b6b2: f891 bnez s1,b5c6 <_start-0x7fff4a3a> - b6b4: 067e slli a2,a2,0x1f - b6b6: 2540 fld fs0,136(a0) - b6b8: 9f1e add t5,t5,t2 - ... - b6c2: 09a8 addi a0,sp,216 - b6c4: 0000 unimp - b6c6: 09c0 addi s0,sp,212 - b6c8: 0000 unimp - b6ca: 0001 nop - b6cc: 00000057 vadd.vv v0,v0,v0,v0.t - b6d0: 0000 unimp - b6d2: 0000 unimp - b6d4: 9000 0x9000 - b6d6: 0009 c.nop 2 - b6d8: c400 sw s0,8(s0) - b6da: 0300000b 0x300000b - b6de: 9100 0x9100 - b6e0: 7ef8 flw fa4,124(a3) - b6e2: 0da8 addi a0,sp,728 - b6e4: 0000 unimp - b6e6: 0db4 addi a3,sp,728 - b6e8: 0000 unimp - b6ea: f8910003 lb zero,-119(sp) - b6ee: 007e c.slli zero,0x1f - b6f0: 0000 unimp - b6f2: 0000 unimp - b6f4: 0000 unimp - b6f6: 9000 0x9000 - b6f8: 0009 c.nop 2 - b6fa: a800 fsd fs0,16(s0) - b6fc: 0009 c.nop 2 - b6fe: 0100 addi s0,sp,128 - b700: 5700 lw s0,40(a4) - b702: 09a8 addi a0,sp,216 - b704: 0000 unimp - b706: 0bc4 addi s1,sp,468 - b708: 0000 unimp - b70a: fa910003 lb zero,-87(sp) - b70e: a87e fsd ft11,16(sp) - b710: 000d c.nop 3 - b712: b400 fsd fs0,40(s0) - b714: 000d c.nop 3 - b716: 0300 addi s0,sp,384 - b718: 9100 0x9100 - b71a: 7efa flw ft9,188(sp) - ... - b724: 0990 addi a2,sp,208 - b726: 0000 unimp - b728: 0acc addi a1,sp,340 - b72a: 0000 unimp - b72c: 0001 nop - b72e: cc55 beqz s0,b7ea <_start-0x7fff4816> - b730: 000a c.slli zero,0x2 - b732: c400 sw s0,8(s0) - b734: 0300000b 0x300000b - b738: 9100 0x9100 - b73a: 7f8e flw ft11,224(sp) - b73c: 0da8 addi a0,sp,728 - b73e: 0000 unimp - b740: 0db4 addi a3,sp,728 - b742: 0000 unimp - b744: 8e910003 lb zero,-1815(sp) - b748: 007f 0x7f - b74a: 0000 unimp - b74c: 0000 unimp - b74e: 0000 unimp - b750: d800 sw s0,48(s0) - b752: 0009 c.nop 2 - b754: 1c00 addi s0,sp,560 - b756: 000a c.slli zero,0x2 - b758: 0100 addi s0,sp,128 - b75a: 6e00 flw fs0,24(a2) - b75c: 0a1c addi a5,sp,272 - b75e: 0000 unimp - b760: 0a48 addi a0,sp,276 - b762: 0000 unimp - b764: 7f84000b 0x7f84000b - b768: 8891 andi s1,s1,4 - b76a: 067f 0x67f - b76c: 831a mv t1,t1 - b76e: 1e00 addi s0,sp,816 - b770: 489f 000a c000 0xc000000a489f - b776: 000a c.slli zero,0x2 - b778: 0b00 addi s0,sp,400 - b77a: 9100 0x9100 - b77c: 7f88 flw fa0,56(a5) - b77e: 7906 flw fs2,96(sp) - b780: 1a00 addi s0,sp,304 - b782: 9f1e0083 lb ra,-1551(t3) - b786: 0ac0 addi s0,sp,340 - b788: 0000 unimp - b78a: 0ae0 addi s0,sp,348 - b78c: 0000 unimp - b78e: 0010 0x10 - b790: 8891 andi s1,s1,4 - b792: 067f 0x67f - b794: 0079 c.nop 30 - b796: 911a add sp,sp,t1 - b798: 7efc flw fa5,124(a3) - b79a: 7906 flw fs2,96(sp) - b79c: 1a00 addi s0,sp,304 - b79e: 9f1e add t5,t5,t2 - b7a0: 0ae0 addi s0,sp,348 - b7a2: 0000 unimp - b7a4: 0bc4 addi s1,sp,468 - b7a6: 0000 unimp - b7a8: 0010 0x10 - b7aa: 7f89 lui t6,0xfffe2 - b7ac: 8891 andi s1,s1,4 - b7ae: 067f 0x67f - b7b0: 891a mv s2,t1 - b7b2: 917f 0x917f - b7b4: 7efc flw fa5,124(a3) - b7b6: 1a06 slli s4,s4,0x21 - b7b8: 9f1e add t5,t5,t2 - b7ba: 0da8 addi a0,sp,728 - b7bc: 0000 unimp - b7be: 0db4 addi a3,sp,728 - b7c0: 0000 unimp - b7c2: 0010 0x10 - b7c4: 7f89 lui t6,0xfffe2 - b7c6: 8891 andi s1,s1,4 - b7c8: 067f 0x67f - b7ca: 891a mv s2,t1 - b7cc: 917f 0x917f - b7ce: 7efc flw fa5,124(a3) - b7d0: 1a06 slli s4,s4,0x21 - b7d2: 9f1e add t5,t5,t2 - ... - b7dc: 09d8 addi a4,sp,212 - b7de: 0000 unimp - b7e0: 09e4 addi s1,sp,220 - b7e2: 0000 unimp - b7e4: 0001 nop - b7e6: e45c fsw fa5,12(s0) - b7e8: 0009 c.nop 2 - b7ea: ec00 fsw fs0,24(s0) - b7ec: 0009 c.nop 2 - b7ee: 0600 addi s0,sp,768 - b7f0: 7800 flw fs0,48(s0) - b7f2: 8300 0x8300 - b7f4: 1e00 addi s0,sp,816 - b7f6: ec9f 0009 1400 0x14000009ec9f - b7fc: 000a c.slli zero,0x2 - b7fe: 0100 addi s0,sp,128 - b800: 5c00 lw s0,56(s0) - b802: 0a14 addi a3,sp,272 - b804: 0000 unimp - b806: 0a3c addi a5,sp,280 - b808: 0000 unimp - b80a: 000c 0xc - b80c: 0078 addi a4,sp,12 - b80e: 851e0083 lb ra,-1967(t3) - b812: 2200 fld fs0,0(a2) - b814: 008d addi ra,ra,3 - b816: 9f22 add t5,t5,s0 - b818: 0a3c addi a5,sp,280 - b81a: 0000 unimp - b81c: 0a48 addi a0,sp,276 - b81e: 0000 unimp - b820: 0014 0x14 - b822: 0078 addi a4,sp,12 - b824: 841e0083 lb ra,-1983(t3) - b828: 917f 0x917f - b82a: 7f88 flw fa0,56(a5) - b82c: 1a06 slli s4,s4,0x21 - b82e: 221e008f 0x221e008f - b832: 0085 addi ra,ra,1 - b834: 9f22 add t5,t5,s0 - b836: 0a48 addi a0,sp,276 - b838: 0000 unimp - b83a: 0ac0 addi s0,sp,340 - b83c: 0000 unimp - b83e: 0014 0x14 - b840: 0078 addi a4,sp,12 - b842: 911e0083 lb ra,-1775(t3) - b846: 7f88 flw fa0,56(a5) - b848: 7906 flw fs2,96(sp) - b84a: 1a00 addi s0,sp,304 - b84c: 221e008f 0x221e008f - b850: 0085 addi ra,ra,1 - b852: 9f22 add t5,t5,s0 - b854: 0ac0 addi s0,sp,340 - b856: 0000 unimp - b858: 0ac8 addi a0,sp,340 - b85a: 0000 unimp - b85c: 0019 c.nop 6 - b85e: fc91 bnez s1,b77a <_start-0x7fff4886> - b860: 067e slli a2,a2,0x1f - b862: 0079 c.nop 30 - b864: 781a flw fa6,164(sp) - b866: 1e00 addi s0,sp,816 - b868: 8891 andi s1,s1,4 - b86a: 067f 0x67f - b86c: 0079 c.nop 30 - b86e: 8f1a mv t5,t1 - b870: 1e00 addi s0,sp,816 - b872: 8522 mv a0,s0 - b874: 2200 fld fs0,0(a2) - b876: c89f 000a e000 0xe000000ac89f - b87c: 000a c.slli zero,0x2 - b87e: 1d00 addi s0,sp,688 - b880: 9100 0x9100 - b882: 7efc flw fa5,124(a3) - b884: 7906 flw fs2,96(sp) - b886: 1a00 addi s0,sp,304 - b888: 0078 addi a4,sp,12 - b88a: 911e add sp,sp,t2 - b88c: 7f88 flw fa0,56(a5) - b88e: 7906 flw fs2,96(sp) - b890: 1a00 addi s0,sp,304 - b892: fc91 bnez s1,b7ae <_start-0x7fff4852> - b894: 067e slli a2,a2,0x1f - b896: 2540 fld fs0,136(a0) - b898: 221e fld ft4,448(sp) - b89a: 0085 addi ra,ra,1 - b89c: 9f22 add t5,t5,s0 - b89e: 0ae0 addi s0,sp,348 - b8a0: 0000 unimp - b8a2: 0bc4 addi s1,sp,468 - b8a4: 0000 unimp - b8a6: 001d c.nop 7 - b8a8: 7f89 lui t6,0xfffe2 - b8aa: fc91 bnez s1,b7c6 <_start-0x7fff483a> - b8ac: 067e slli a2,a2,0x1f - b8ae: 781a flw fa6,164(sp) - b8b0: 1e00 addi s0,sp,816 - b8b2: 7f89 lui t6,0xfffe2 - b8b4: 8891 andi s1,s1,4 - b8b6: 067f 0x67f - b8b8: 911a add sp,sp,t1 - b8ba: 7efc flw fa5,124(a3) - b8bc: 4006 0x4006 - b8be: 1e25 addi t3,t3,-23 - b8c0: 8522 mv a0,s0 - b8c2: 2200 fld fs0,0(a2) - b8c4: a89f 000d b400 0xb400000da89f - b8ca: 000d c.nop 3 - b8cc: 1d00 addi s0,sp,688 - b8ce: 8900 0x8900 - b8d0: 917f 0x917f - b8d2: 7efc flw fa5,124(a3) - b8d4: 1a06 slli s4,s4,0x21 - b8d6: 0078 addi a4,sp,12 - b8d8: 891e mv s2,t2 - b8da: 917f 0x917f - b8dc: 7f88 flw fa0,56(a5) - b8de: 1a06 slli s4,s4,0x21 - b8e0: fc91 bnez s1,b7fc <_start-0x7fff4804> - b8e2: 067e slli a2,a2,0x1f - b8e4: 2540 fld fs0,136(a0) - b8e6: 221e fld ft4,448(sp) - b8e8: 0085 addi ra,ra,1 - b8ea: 9f22 add t5,t5,s0 - ... - b8f4: 09dc addi a5,sp,212 - b8f6: 0000 unimp - b8f8: 0a3c addi a5,sp,280 - b8fa: 0000 unimp - b8fc: 0001 nop - b8fe: 3c6d jal b3b8 <_start-0x7fff4c48> - b900: 000a c.slli zero,0x2 - b902: 4800 lw s0,16(s0) - b904: 000a c.slli zero,0x2 - b906: 0b00 addi s0,sp,400 - b908: 8400 0x8400 - b90a: 917f 0x917f - b90c: 7f88 flw fa0,56(a5) - b90e: 1a06 slli s4,s4,0x21 - b910: 9f1e008f 0x9f1e008f - b914: 0a48 addi a0,sp,276 - b916: 0000 unimp - b918: 0ac8 addi a0,sp,340 - b91a: 0000 unimp - b91c: 8891000b 0x8891000b - b920: 067f 0x67f - b922: 0079 c.nop 30 - b924: 8f1a mv t5,t1 - b926: 1e00 addi s0,sp,816 - b928: c89f 000a e000 0xe000000ac89f - b92e: 000a c.slli zero,0x2 - b930: 0f00 addi s0,sp,912 - b932: 9100 0x9100 - b934: 7f88 flw fa0,56(a5) - b936: 7906 flw fs2,96(sp) - b938: 1a00 addi s0,sp,304 - b93a: fc91 bnez s1,b856 <_start-0x7fff47aa> - b93c: 067e slli a2,a2,0x1f - b93e: 2540 fld fs0,136(a0) - b940: 9f1e add t5,t5,t2 - b942: 0ae0 addi s0,sp,348 - b944: 0000 unimp - b946: 0bc4 addi s1,sp,468 - b948: 0000 unimp - b94a: 7f89000f 0x7f89000f - b94e: 8891 andi s1,s1,4 - b950: 067f 0x67f - b952: 911a add sp,sp,t1 - b954: 7efc flw fa5,124(a3) - b956: 4006 0x4006 - b958: 1e25 addi t3,t3,-23 - b95a: a89f 000d b400 0xb400000da89f - b960: 000d c.nop 3 - b962: 0f00 addi s0,sp,912 - b964: 8900 0x8900 - b966: 917f 0x917f - b968: 7f88 flw fa0,56(a5) - b96a: 1a06 slli s4,s4,0x21 - b96c: fc91 bnez s1,b888 <_start-0x7fff4778> - b96e: 067e slli a2,a2,0x1f - b970: 2540 fld fs0,136(a0) - b972: 9f1e add t5,t5,t2 - ... - b97c: 09ec addi a1,sp,220 - b97e: 0000 unimp - b980: 0a08 addi a0,sp,272 - b982: 0000 unimp - b984: 0001 nop - b986: 0059 c.nop 22 - b988: 0000 unimp - b98a: 0000 unimp - b98c: 0000 unimp - b98e: d000 sw s0,32(s0) - b990: 0009 c.nop 2 - b992: c800 sw s0,16(s0) - b994: 000a c.slli zero,0x2 - b996: 0100 addi s0,sp,128 - b998: 6f00 flw fs0,24(a4) - b99a: 0ac8 addi a0,sp,340 - b99c: 0000 unimp - b99e: 0bc4 addi s1,sp,468 - b9a0: 0000 unimp - b9a2: fe910003 lb zero,-23(sp) - b9a6: a87e fsd ft11,16(sp) - b9a8: 000d c.nop 3 - b9aa: b400 fsd fs0,40(s0) - b9ac: 000d c.nop 3 - b9ae: 0300 addi s0,sp,384 - b9b0: 9100 0x9100 - b9b2: 7efe flw ft9,252(sp) - ... - b9bc: 09d0 addi a2,sp,212 - b9be: 0000 unimp - b9c0: 0bc4 addi s1,sp,468 - b9c2: 0000 unimp - b9c4: 0001 nop - b9c6: a858 fsd fa4,144(s0) - b9c8: 000d c.nop 3 - b9ca: b400 fsd fs0,40(s0) - b9cc: 000d c.nop 3 - b9ce: 0100 addi s0,sp,128 - b9d0: 5800 lw s0,48(s0) - ... - b9da: 0a28 addi a0,sp,280 - b9dc: 0000 unimp - b9de: 0a54 addi a3,sp,276 - b9e0: 0000 unimp - b9e2: 0001 nop - b9e4: 005a c.slli zero,0x16 - b9e6: 0000 unimp - b9e8: 0000 unimp - b9ea: 0000 unimp - b9ec: 2800 fld fs0,16(s0) - b9ee: 000a c.slli zero,0x2 - b9f0: 4c00 lw s0,24(s0) - b9f2: 000a c.slli zero,0x2 - b9f4: 1f00 addi s0,sp,944 - b9f6: 7d00 flw fs0,56(a0) - b9f8: 4000 lw s0,0(s0) - b9fa: 8122244b fnmsub.s fs0,ft4,fs2,fa6,rdn - b9fe: 4000 lw s0,0(s0) - ba00: 2d22244b 0x2d22244b - ba04: 4b40008b 0x4b40008b - ba08: 2224 fld fs1,64(a2) - ba0a: 007a c.slli zero,0x1e - ba0c: 4b40 lw s0,20(a4) - ba0e: 2224 fld fs1,64(a2) - ba10: 212d jal be3a <_start-0x7fff41c6> - ba12: ff08 fsw fa0,56(a4) - ba14: 9f1a add t5,t5,t1 - ... - ba1e: 0a2c addi a1,sp,280 - ba20: 0000 unimp - ba22: 0a50 addi a2,sp,276 - ba24: 0000 unimp - ba26: 0001 nop - ba28: 0000005b 0x5b - ba2c: 0000 unimp - ba2e: 0000 unimp - ba30: 3000 fld fs0,32(s0) - ba32: 000a c.slli zero,0x2 - ba34: 3800 fld fs0,48(s0) - ba36: 000a c.slli zero,0x2 - ba38: 1100 addi s0,sp,160 - ba3a: 8e00 0x8e00 - ba3c: 4000 lw s0,0(s0) - ba3e: 8222244b fnmsub.d fs0,ft4,ft2,fa6,rdn - ba42: 4000 lw s0,0(s0) - ba44: 2d22244b 0x2d22244b - ba48: ff08 fsw fa0,56(a4) - ba4a: 9f1a add t5,t5,t1 - ba4c: 0a38 addi a4,sp,280 - ba4e: 0000 unimp - ba50: 0a50 addi a2,sp,276 - ba52: 0000 unimp - ba54: 001f 008e 4b40 0x4b40008e001f - ba5a: 2224 fld fs1,64(a2) - ba5c: 0082 c.slli64 ra - ba5e: 4b40 lw s0,20(a4) - ba60: 2224 fld fs1,64(a2) - ba62: 8a2d andi a2,a2,11 - ba64: 4000 lw s0,0(s0) - ba66: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - ba6a: 4000 lw s0,0(s0) - ba6c: 2d22244b 0x2d22244b - ba70: 0821 addi a6,a6,8 - ba72: 1aff 0x1aff - ba74: 009f 0000 0000 0x9f - ba7a: 0000 unimp - ba7c: 4400 lw s0,8(s0) - ba7e: 000a c.slli zero,0x2 - ba80: 6800 flw fs0,16(s0) - ba82: 000a c.slli zero,0x2 - ba84: 0100 addi s0,sp,128 - ba86: 6c00 flw fs0,24(s0) - ba88: 0a68 addi a0,sp,284 - ba8a: 0000 unimp - ba8c: 0a74 addi a3,sp,284 - ba8e: 0000 unimp - ba90: 0010 0x10 - ba92: b091 j b2d6 <_start-0x7fff4d2a> - ba94: 067f 0x67f - ba96: 4b40 lw s0,20(a4) - ba98: 2224 fld fs1,64(a2) - ba9a: 0080 addi s0,sp,64 - ba9c: 4b40 lw s0,20(a4) - ba9e: 2224 fld fs1,64(a2) - baa0: 9f2d 0x9f2d - baa2: 0a74 addi a3,sp,284 - baa4: 0000 unimp - baa6: 0ac0 addi s0,sp,340 - baa8: 0000 unimp - baaa: 0042 c.slli zero,0x10 - baac: b091 j b2f0 <_start-0x7fff4d10> - baae: 067f 0x67f - bab0: 4b40 lw s0,20(a4) - bab2: 2224 fld fs1,64(a2) - bab4: 8491 srai s1,s1,0x4 - bab6: 067f 0x67f - bab8: 0079 c.nop 30 - baba: 831a mv t1,t1 - babc: 1e00 addi s0,sp,816 - babe: 0079 c.nop 30 - bac0: 911a add sp,sp,t1 - bac2: 7f84 flw fs1,56(a5) - bac4: 4006 0x4006 - bac6: 8325 srli a4,a4,0x9 - bac8: 1e00 addi s0,sp,816 - baca: 8491 srai s1,s1,0x4 - bacc: 067f 0x67f - bace: 0079 c.nop 30 - bad0: 8f1a mv t5,t1 - bad2: 1e00 addi s0,sp,816 - bad4: 9122 add sp,sp,s0 - bad6: 7f84 flw fs1,56(a5) - bad8: 7906 flw fs2,96(sp) - bada: 1a00 addi s0,sp,304 - badc: 401e0083 lb ra,1025(t3) - bae0: 2225 jal bc08 <_start-0x7fff43f8> - bae2: 0079 c.nop 30 - bae4: 401a 0x401a - bae6: 2224 fld fs1,64(a2) - bae8: 4b40 lw s0,20(a4) - baea: 2224 fld fs1,64(a2) - baec: 9f2d 0x9f2d - baee: 0ac0 addi s0,sp,340 - baf0: 0000 unimp - baf2: 0ac8 addi a0,sp,340 - baf4: 0000 unimp - baf6: 0051 c.nop 20 - baf8: b091 j b33c <_start-0x7fff4cc4> - bafa: 067f 0x67f - bafc: 4b40 lw s0,20(a4) - bafe: 2224 fld fs1,64(a2) - bb00: fc91 bnez s1,ba1c <_start-0x7fff45e4> - bb02: 067e slli a2,a2,0x1f - bb04: 0079 c.nop 30 - bb06: 911a add sp,sp,t1 - bb08: 7f84 flw fs1,56(a5) - bb0a: 7906 flw fs2,96(sp) - bb0c: 1a00 addi s0,sp,304 - bb0e: 791e flw fs2,228(sp) - bb10: 1a00 addi s0,sp,304 - bb12: fc91 bnez s1,ba2e <_start-0x7fff45d2> - bb14: 067e slli a2,a2,0x1f - bb16: 0079 c.nop 30 - bb18: 911a add sp,sp,t1 - bb1a: 7f84 flw fs1,56(a5) - bb1c: 4006 0x4006 - bb1e: 1e25 addi t3,t3,-23 - bb20: 8491 srai s1,s1,0x4 - bb22: 067f 0x67f - bb24: 0079 c.nop 30 - bb26: 8f1a mv t5,t1 - bb28: 1e00 addi s0,sp,816 - bb2a: 9122 add sp,sp,s0 - bb2c: 7efc flw fa5,124(a3) - bb2e: 7906 flw fs2,96(sp) - bb30: 1a00 addi s0,sp,304 - bb32: 8491 srai s1,s1,0x4 - bb34: 067f 0x67f - bb36: 0079 c.nop 30 - bb38: 1e1a slli t3,t3,0x26 - bb3a: 2540 fld fs0,136(a0) - bb3c: 7922 flw fs2,40(sp) - bb3e: 1a00 addi s0,sp,304 - bb40: 2440 fld fs0,136(s0) - bb42: 4022 0x4022 - bb44: 2d22244b 0x2d22244b - bb48: c89f 000a e000 0xe000000ac89f - bb4e: 000a c.slli zero,0x2 - bb50: 5500 lw s0,40(a0) - bb52: 9100 0x9100 - bb54: 7fb0 flw fa2,120(a5) - bb56: 4006 0x4006 - bb58: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bb5c: 7efc flw fa5,124(a3) - bb5e: 7906 flw fs2,96(sp) - bb60: 1a00 addi s0,sp,304 - bb62: 8491 srai s1,s1,0x4 - bb64: 067f 0x67f - bb66: 0079 c.nop 30 - bb68: 1e1a slli t3,t3,0x26 - bb6a: 0079 c.nop 30 - bb6c: 911a add sp,sp,t1 - bb6e: 7efc flw fa5,124(a3) - bb70: 7906 flw fs2,96(sp) - bb72: 1a00 addi s0,sp,304 - bb74: 8491 srai s1,s1,0x4 - bb76: 067f 0x67f - bb78: 2540 fld fs0,136(a0) - bb7a: 911e add sp,sp,t2 - bb7c: 7f84 flw fs1,56(a5) - bb7e: 7906 flw fs2,96(sp) - bb80: 1a00 addi s0,sp,304 - bb82: fc91 bnez s1,ba9e <_start-0x7fff4562> - bb84: 067e slli a2,a2,0x1f - bb86: 2540 fld fs0,136(a0) - bb88: 221e fld ft4,448(sp) - bb8a: fc91 bnez s1,baa6 <_start-0x7fff455a> - bb8c: 067e slli a2,a2,0x1f - bb8e: 0079 c.nop 30 - bb90: 911a add sp,sp,t1 - bb92: 7f84 flw fs1,56(a5) - bb94: 7906 flw fs2,96(sp) - bb96: 1a00 addi s0,sp,304 - bb98: 401e 0x401e - bb9a: 2225 jal bcc2 <_start-0x7fff433e> - bb9c: 0079 c.nop 30 - bb9e: 401a 0x401a - bba0: 2224 fld fs1,64(a2) - bba2: 4b40 lw s0,20(a4) - bba4: 2224 fld fs1,64(a2) - bba6: 9f2d 0x9f2d - bba8: 0ae0 addi s0,sp,348 - bbaa: 0000 unimp - bbac: 0b2c addi a1,sp,408 - bbae: 0000 unimp - bbb0: 0055 c.nop 21 - bbb2: b091 j b3f6 <_start-0x7fff4c0a> - bbb4: 067f 0x67f - bbb6: 4b40 lw s0,20(a4) - bbb8: 2224 fld fs1,64(a2) - bbba: 7f89 lui t6,0xfffe2 - bbbc: fc91 bnez s1,bad8 <_start-0x7fff4528> - bbbe: 067e slli a2,a2,0x1f - bbc0: 891a mv s2,t1 - bbc2: 917f 0x917f - bbc4: 7f84 flw fs1,56(a5) - bbc6: 1a06 slli s4,s4,0x21 - bbc8: 891e mv s2,t2 - bbca: 1a7f 0x1a7f - bbcc: 7f89 lui t6,0xfffe2 - bbce: fc91 bnez s1,baea <_start-0x7fff4516> - bbd0: 067e slli a2,a2,0x1f - bbd2: 911a add sp,sp,t1 - bbd4: 7f84 flw fs1,56(a5) - bbd6: 4006 0x4006 - bbd8: 1e25 addi t3,t3,-23 - bbda: 7f89 lui t6,0xfffe2 - bbdc: 8491 srai s1,s1,0x4 - bbde: 067f 0x67f - bbe0: 911a add sp,sp,t1 - bbe2: 7efc flw fa5,124(a3) - bbe4: 4006 0x4006 - bbe6: 1e25 addi t3,t3,-23 - bbe8: 8922 mv s2,s0 - bbea: 917f 0x917f - bbec: 7efc flw fa5,124(a3) - bbee: 1a06 slli s4,s4,0x21 - bbf0: 7f89 lui t6,0xfffe2 - bbf2: 8491 srai s1,s1,0x4 - bbf4: 067f 0x67f - bbf6: 1e1a slli t3,t3,0x26 - bbf8: 2540 fld fs0,136(a0) - bbfa: 8922 mv s2,s0 - bbfc: 1a7f 0x1a7f - bbfe: 2440 fld fs0,136(s0) - bc00: 4022 0x4022 - bc02: 2d22244b 0x2d22244b - bc06: 009f 0000 0000 0x9f - bc0c: 0000 unimp - bc0e: 4400 lw s0,8(s0) - bc10: 000a c.slli zero,0x2 - bc12: 4800 lw s0,16(s0) - bc14: 000a c.slli zero,0x2 - bc16: 1100 addi s0,sp,160 - bc18: 8d00 0x8d00 - bc1a: 4000 lw s0,0(s0) - bc1c: 8622244b fnmsub.q fs0,ft4,ft2,fa6,rdn - bc20: 4000 lw s0,0(s0) - bc22: 2d22244b 0x2d22244b - bc26: ff08 fsw fa0,56(a4) - bc28: 9f1a add t5,t5,t1 - bc2a: 0a48 addi a0,sp,276 - bc2c: 0000 unimp - bc2e: 0a64 addi s1,sp,284 - bc30: 0000 unimp - bc32: 001f 008d 4b40 0x4b40008d001f - bc38: 2224 fld fs1,64(a2) - bc3a: 0086 slli ra,ra,0x1 - bc3c: 4b40 lw s0,20(a4) - bc3e: 2224 fld fs1,64(a2) - bc40: 842d srai s0,s0,0xb - bc42: 4000 lw s0,0(s0) - bc44: 8c22244b 0x8c22244b - bc48: 4000 lw s0,0(s0) - bc4a: 2d22244b 0x2d22244b - bc4e: 0821 addi a6,a6,8 - bc50: 1aff 0x1aff - bc52: 649f 000a 6800 0x6800000a649f - bc58: 000a c.slli zero,0x2 - bc5a: 2200 fld fs0,0(a2) - bc5c: 8a00 0x8a00 - bc5e: 8600 0x8600 - bc60: 2200 fld fs0,0(a2) - bc62: 4b40 lw s0,20(a4) - bc64: 2224 fld fs1,64(a2) - bc66: 008a slli ra,ra,0x2 - bc68: 4b40 lw s0,20(a4) - bc6a: 2224 fld fs1,64(a2) - bc6c: 842d srai s0,s0,0xb - bc6e: 4000 lw s0,0(s0) - bc70: 8c22244b 0x8c22244b - bc74: 4000 lw s0,0(s0) - bc76: 2d22244b 0x2d22244b - bc7a: 0821 addi a6,a6,8 - bc7c: 1aff 0x1aff - bc7e: 689f 000a 7400 0x7400000a689f - bc84: 000a c.slli zero,0x2 - bc86: 2f00 fld fs0,24(a4) - bc88: 8a00 0x8a00 - bc8a: 8600 0x8600 - bc8c: 2200 fld fs0,0(a2) - bc8e: 4b40 lw s0,20(a4) - bc90: 2224 fld fs1,64(a2) - bc92: 008a slli ra,ra,0x2 - bc94: 4b40 lw s0,20(a4) - bc96: 2224 fld fs1,64(a2) - bc98: 842d srai s0,s0,0xb - bc9a: 4000 lw s0,0(s0) - bc9c: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bca0: 7fb0 flw fa2,120(a5) - bca2: 4006 0x4006 - bca4: 8022244b fnmsub.s fs0,ft4,ft2,fa6,rdn - bca8: 4000 lw s0,0(s0) - bcaa: 2d22244b 0x2d22244b - bcae: 4b40 lw s0,20(a4) - bcb0: 2224 fld fs1,64(a2) - bcb2: 212d jal c0dc <_start-0x7fff3f24> - bcb4: ff08 fsw fa0,56(a4) - bcb6: 9f1a add t5,t5,t1 - bcb8: 0a74 addi a3,sp,284 - bcba: 0000 unimp - bcbc: 0ac0 addi s0,sp,340 - bcbe: 0000 unimp - bcc0: 0061 c.nop 24 - bcc2: 008a slli ra,ra,0x2 - bcc4: 0086 slli ra,ra,0x1 - bcc6: 4022 0x4022 - bcc8: 8a22244b fnmsub.d fs0,ft4,ft2,fa7,rdn - bccc: 4000 lw s0,0(s0) - bcce: 2d22244b 0x2d22244b - bcd2: 0084 addi s1,sp,64 - bcd4: 4b40 lw s0,20(a4) - bcd6: 2224 fld fs1,64(a2) - bcd8: b091 j b51c <_start-0x7fff4ae4> - bcda: 067f 0x67f - bcdc: 4b40 lw s0,20(a4) - bcde: 2224 fld fs1,64(a2) - bce0: 8491 srai s1,s1,0x4 - bce2: 067f 0x67f - bce4: 0079 c.nop 30 - bce6: 831a mv t1,t1 - bce8: 1e00 addi s0,sp,816 - bcea: 0079 c.nop 30 - bcec: 911a add sp,sp,t1 - bcee: 7f84 flw fs1,56(a5) - bcf0: 4006 0x4006 - bcf2: 8325 srli a4,a4,0x9 - bcf4: 1e00 addi s0,sp,816 - bcf6: 8491 srai s1,s1,0x4 - bcf8: 067f 0x67f - bcfa: 0079 c.nop 30 - bcfc: 8f1a mv t5,t1 - bcfe: 1e00 addi s0,sp,816 - bd00: 9122 add sp,sp,s0 - bd02: 7f84 flw fs1,56(a5) - bd04: 7906 flw fs2,96(sp) - bd06: 1a00 addi s0,sp,304 - bd08: 401e0083 lb ra,1025(t3) - bd0c: 2225 jal be34 <_start-0x7fff41cc> - bd0e: 0079 c.nop 30 - bd10: 401a 0x401a - bd12: 2224 fld fs1,64(a2) - bd14: 4b40 lw s0,20(a4) - bd16: 2224 fld fs1,64(a2) - bd18: 402d c.li zero,11 - bd1a: 2d22244b 0x2d22244b - bd1e: 0821 addi a6,a6,8 - bd20: 1aff 0x1aff - bd22: c09f 000a c800 0xc800000ac09f - bd28: 000a c.slli zero,0x2 - bd2a: 7000 flw fs0,32(s0) - bd2c: 8a00 0x8a00 - bd2e: 8600 0x8600 - bd30: 2200 fld fs0,0(a2) - bd32: 4b40 lw s0,20(a4) - bd34: 2224 fld fs1,64(a2) - bd36: 008a slli ra,ra,0x2 - bd38: 4b40 lw s0,20(a4) - bd3a: 2224 fld fs1,64(a2) - bd3c: 842d srai s0,s0,0xb - bd3e: 4000 lw s0,0(s0) - bd40: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bd44: 7fb0 flw fa2,120(a5) - bd46: 4006 0x4006 - bd48: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bd4c: 7efc flw fa5,124(a3) - bd4e: 7906 flw fs2,96(sp) - bd50: 1a00 addi s0,sp,304 - bd52: 8491 srai s1,s1,0x4 - bd54: 067f 0x67f - bd56: 0079 c.nop 30 - bd58: 1e1a slli t3,t3,0x26 - bd5a: 0079 c.nop 30 - bd5c: 911a add sp,sp,t1 - bd5e: 7efc flw fa5,124(a3) - bd60: 7906 flw fs2,96(sp) - bd62: 1a00 addi s0,sp,304 - bd64: 8491 srai s1,s1,0x4 - bd66: 067f 0x67f - bd68: 2540 fld fs0,136(a0) - bd6a: 911e add sp,sp,t2 - bd6c: 7f84 flw fs1,56(a5) - bd6e: 7906 flw fs2,96(sp) - bd70: 1a00 addi s0,sp,304 - bd72: 221e008f 0x221e008f - bd76: fc91 bnez s1,bc92 <_start-0x7fff436e> - bd78: 067e slli a2,a2,0x1f - bd7a: 0079 c.nop 30 - bd7c: 911a add sp,sp,t1 - bd7e: 7f84 flw fs1,56(a5) - bd80: 7906 flw fs2,96(sp) - bd82: 1a00 addi s0,sp,304 - bd84: 401e 0x401e - bd86: 2225 jal beae <_start-0x7fff4152> - bd88: 0079 c.nop 30 - bd8a: 401a 0x401a - bd8c: 2224 fld fs1,64(a2) - bd8e: 4b40 lw s0,20(a4) - bd90: 2224 fld fs1,64(a2) - bd92: 402d c.li zero,11 - bd94: 2d22244b 0x2d22244b - bd98: 0821 addi a6,a6,8 - bd9a: 1aff 0x1aff - bd9c: c89f 000a e000 0xe000000ac89f - bda2: 000a c.slli zero,0x2 - bda4: 7400 flw fs0,40(s0) - bda6: 8a00 0x8a00 - bda8: 8600 0x8600 - bdaa: 2200 fld fs0,0(a2) - bdac: 4b40 lw s0,20(a4) - bdae: 2224 fld fs1,64(a2) - bdb0: 008a slli ra,ra,0x2 - bdb2: 4b40 lw s0,20(a4) - bdb4: 2224 fld fs1,64(a2) - bdb6: 842d srai s0,s0,0xb - bdb8: 4000 lw s0,0(s0) - bdba: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bdbe: 7fb0 flw fa2,120(a5) - bdc0: 4006 0x4006 - bdc2: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bdc6: 7efc flw fa5,124(a3) - bdc8: 7906 flw fs2,96(sp) - bdca: 1a00 addi s0,sp,304 - bdcc: 8491 srai s1,s1,0x4 - bdce: 067f 0x67f - bdd0: 0079 c.nop 30 - bdd2: 1e1a slli t3,t3,0x26 - bdd4: 0079 c.nop 30 - bdd6: 911a add sp,sp,t1 - bdd8: 7efc flw fa5,124(a3) - bdda: 7906 flw fs2,96(sp) - bddc: 1a00 addi s0,sp,304 - bdde: 8491 srai s1,s1,0x4 - bde0: 067f 0x67f - bde2: 2540 fld fs0,136(a0) - bde4: 911e add sp,sp,t2 - bde6: 7f84 flw fs1,56(a5) - bde8: 7906 flw fs2,96(sp) - bdea: 1a00 addi s0,sp,304 - bdec: fc91 bnez s1,bd08 <_start-0x7fff42f8> - bdee: 067e slli a2,a2,0x1f - bdf0: 2540 fld fs0,136(a0) - bdf2: 221e fld ft4,448(sp) - bdf4: fc91 bnez s1,bd10 <_start-0x7fff42f0> - bdf6: 067e slli a2,a2,0x1f - bdf8: 0079 c.nop 30 - bdfa: 911a add sp,sp,t1 - bdfc: 7f84 flw fs1,56(a5) - bdfe: 7906 flw fs2,96(sp) - be00: 1a00 addi s0,sp,304 - be02: 401e 0x401e - be04: 2225 jal bf2c <_start-0x7fff40d4> - be06: 0079 c.nop 30 - be08: 401a 0x401a - be0a: 2224 fld fs1,64(a2) - be0c: 4b40 lw s0,20(a4) - be0e: 2224 fld fs1,64(a2) - be10: 402d c.li zero,11 - be12: 2d22244b 0x2d22244b - be16: 0821 addi a6,a6,8 - be18: 1aff 0x1aff - be1a: e09f 000a 2c00 0x2c00000ae09f - be20: 7400000b 0x7400000b - be24: 8a00 0x8a00 - be26: 8600 0x8600 - be28: 2200 fld fs0,0(a2) - be2a: 4b40 lw s0,20(a4) - be2c: 2224 fld fs1,64(a2) - be2e: 008a slli ra,ra,0x2 - be30: 4b40 lw s0,20(a4) - be32: 2224 fld fs1,64(a2) - be34: 842d srai s0,s0,0xb - be36: 4000 lw s0,0(s0) - be38: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - be3c: 7fb0 flw fa2,120(a5) - be3e: 4006 0x4006 - be40: 8922244b fnmsub.s fs0,ft4,fs2,fa7,rdn - be44: 917f 0x917f - be46: 7efc flw fa5,124(a3) - be48: 1a06 slli s4,s4,0x21 - be4a: 7f89 lui t6,0xfffe2 - be4c: 8491 srai s1,s1,0x4 - be4e: 067f 0x67f - be50: 1e1a slli t3,t3,0x26 - be52: 7f89 lui t6,0xfffe2 - be54: 891a mv s2,t1 - be56: 917f 0x917f - be58: 7efc flw fa5,124(a3) - be5a: 1a06 slli s4,s4,0x21 - be5c: 8491 srai s1,s1,0x4 - be5e: 067f 0x67f - be60: 2540 fld fs0,136(a0) - be62: 891e mv s2,t2 - be64: 917f 0x917f - be66: 7f84 flw fs1,56(a5) - be68: 1a06 slli s4,s4,0x21 - be6a: fc91 bnez s1,bd86 <_start-0x7fff427a> - be6c: 067e slli a2,a2,0x1f - be6e: 2540 fld fs0,136(a0) - be70: 221e fld ft4,448(sp) - be72: 7f89 lui t6,0xfffe2 - be74: fc91 bnez s1,bd90 <_start-0x7fff4270> - be76: 067e slli a2,a2,0x1f - be78: 891a mv s2,t1 - be7a: 917f 0x917f - be7c: 7f84 flw fs1,56(a5) - be7e: 1a06 slli s4,s4,0x21 - be80: 401e 0x401e - be82: 2225 jal bfaa <_start-0x7fff4056> - be84: 7f89 lui t6,0xfffe2 - be86: 401a 0x401a - be88: 2224 fld fs1,64(a2) - be8a: 4b40 lw s0,20(a4) - be8c: 2224 fld fs1,64(a2) - be8e: 402d c.li zero,11 - be90: 2d22244b 0x2d22244b - be94: 0821 addi a6,a6,8 - be96: 1aff 0x1aff - be98: 009f 0000 0000 0x9f - be9e: 0000 unimp - bea0: 7c00 flw fs0,56(s0) - bea2: 000a c.slli zero,0x2 - bea4: 9400 0x9400 - bea6: 000a c.slli zero,0x2 - bea8: 0100 addi s0,sp,128 - beaa: 5e00 lw s0,56(a2) - beac: 0a94 addi a3,sp,336 - beae: 0000 unimp - beb0: 0ab4 addi a3,sp,344 - beb2: 0000 unimp - beb4: 0075 c.nop 29 - beb6: f891 bnez s1,bdca <_start-0x7fff4236> - beb8: 067e slli a2,a2,0x1f - beba: 0079 c.nop 30 - bebc: 761a flw fa2,164(sp) - bebe: 1e00 addi s0,sp,816 - bec0: 0079 c.nop 30 - bec2: 911a add sp,sp,t1 - bec4: 7ef8 flw fa4,124(a3) - bec6: 7906 flw fs2,96(sp) - bec8: 1a00 addi s0,sp,304 - beca: 0075 c.nop 29 - becc: 911e add sp,sp,t2 - bece: 7ef8 flw fa4,124(a3) - bed0: 4006 0x4006 - bed2: 7625 lui a2,0xfffe9 - bed4: 1e00 addi s0,sp,816 - bed6: 9122 add sp,sp,s0 - bed8: 7ef8 flw fa4,124(a3) - beda: 7906 flw fs2,96(sp) - bedc: 1a00 addi s0,sp,304 - bede: 0076 c.slli zero,0x1d - bee0: 401e 0x401e - bee2: 2225 jal c00a <_start-0x7fff3ff6> - bee4: 0079 c.nop 30 - bee6: 401a 0x401a - bee8: 2224 fld fs1,64(a2) - beea: 0084 addi s1,sp,64 - beec: 4022 0x4022 - beee: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bef2: 7ef8 flw fa4,124(a3) - bef4: 7906 flw fs2,96(sp) - bef6: 1a00 addi s0,sp,304 - bef8: 0076 c.slli zero,0x1d - befa: 791e flw fs2,228(sp) - befc: 1a00 addi s0,sp,304 - befe: f891 bnez s1,be12 <_start-0x7fff41ee> - bf00: 067e slli a2,a2,0x1f - bf02: 0079 c.nop 30 - bf04: 751a flw fa0,164(sp) - bf06: 1e00 addi s0,sp,816 - bf08: f891 bnez s1,be1c <_start-0x7fff41e4> - bf0a: 067e slli a2,a2,0x1f - bf0c: 2540 fld fs0,136(a0) - bf0e: 0076 c.slli zero,0x1d - bf10: 221e fld ft4,448(sp) - bf12: f891 bnez s1,be26 <_start-0x7fff41da> - bf14: 067e slli a2,a2,0x1f - bf16: 0079 c.nop 30 - bf18: 761a flw fa2,164(sp) - bf1a: 1e00 addi s0,sp,816 - bf1c: 2540 fld fs0,136(a0) - bf1e: 7922 flw fs2,40(sp) - bf20: 1a00 addi s0,sp,304 - bf22: 2440 fld fs0,136(s0) - bf24: 4022 0x4022 - bf26: 2d22244b 0x2d22244b - bf2a: b49f 000a cc00 0xcc00000ab49f - bf30: 000a c.slli zero,0x2 - bf32: 9300 0x9300 - bf34: 9100 0x9100 - bf36: 7ef8 flw fa4,124(a3) - bf38: 7906 flw fs2,96(sp) - bf3a: 1a00 addi s0,sp,304 - bf3c: 8c91 sub s1,s1,a2 - bf3e: 067f 0x67f - bf40: 0079 c.nop 30 - bf42: 1e1a slli t3,t3,0x26 - bf44: 0079 c.nop 30 - bf46: 911a add sp,sp,t1 - bf48: 7ef8 flw fa4,124(a3) - bf4a: 7906 flw fs2,96(sp) - bf4c: 1a00 addi s0,sp,304 - bf4e: 0075 c.nop 29 - bf50: 911e add sp,sp,t2 - bf52: 7f8c flw fa1,56(a5) - bf54: 7906 flw fs2,96(sp) - bf56: 1a00 addi s0,sp,304 - bf58: f891 bnez s1,be6c <_start-0x7fff4194> - bf5a: 067e slli a2,a2,0x1f - bf5c: 2540 fld fs0,136(a0) - bf5e: 221e fld ft4,448(sp) - bf60: f891 bnez s1,be74 <_start-0x7fff418c> - bf62: 067e slli a2,a2,0x1f - bf64: 0079 c.nop 30 - bf66: 911a add sp,sp,t1 - bf68: 7f8c flw fa1,56(a5) - bf6a: 7906 flw fs2,96(sp) - bf6c: 1a00 addi s0,sp,304 - bf6e: 401e 0x401e - bf70: 2225 jal c098 <_start-0x7fff3f68> - bf72: 0079 c.nop 30 - bf74: 401a 0x401a - bf76: 2224 fld fs1,64(a2) - bf78: 0084 addi s1,sp,64 - bf7a: 4022 0x4022 - bf7c: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - bf80: 7ef8 flw fa4,124(a3) - bf82: 7906 flw fs2,96(sp) - bf84: 1a00 addi s0,sp,304 - bf86: 8c91 sub s1,s1,a2 - bf88: 067f 0x67f - bf8a: 0079 c.nop 30 - bf8c: 1e1a slli t3,t3,0x26 - bf8e: 0079 c.nop 30 - bf90: 911a add sp,sp,t1 - bf92: 7ef8 flw fa4,124(a3) - bf94: 7906 flw fs2,96(sp) - bf96: 1a00 addi s0,sp,304 - bf98: 0075 c.nop 29 - bf9a: 911e add sp,sp,t2 - bf9c: 7f8c flw fa1,56(a5) - bf9e: 7906 flw fs2,96(sp) - bfa0: 1a00 addi s0,sp,304 - bfa2: f891 bnez s1,beb6 <_start-0x7fff414a> - bfa4: 067e slli a2,a2,0x1f - bfa6: 2540 fld fs0,136(a0) - bfa8: 221e fld ft4,448(sp) - bfaa: f891 bnez s1,bebe <_start-0x7fff4142> - bfac: 067e slli a2,a2,0x1f - bfae: 0079 c.nop 30 - bfb0: 911a add sp,sp,t1 - bfb2: 7f8c flw fa1,56(a5) - bfb4: 7906 flw fs2,96(sp) - bfb6: 1a00 addi s0,sp,304 - bfb8: 401e 0x401e - bfba: 2225 jal c0e2 <_start-0x7fff3f1e> - bfbc: 0079 c.nop 30 - bfbe: 401a 0x401a - bfc0: 2224 fld fs1,64(a2) - bfc2: 4b40 lw s0,20(a4) - bfc4: 2224 fld fs1,64(a2) - bfc6: 9f2d 0x9f2d - bfc8: 0acc addi a1,sp,340 - bfca: 0000 unimp - bfcc: 0ae0 addi s0,sp,348 - bfce: 0000 unimp - bfd0: f891009b 0xf891009b - bfd4: 067e slli a2,a2,0x1f - bfd6: 0079 c.nop 30 - bfd8: 911a add sp,sp,t1 - bfda: 7f8c flw fa1,56(a5) - bfdc: 7906 flw fs2,96(sp) - bfde: 1a00 addi s0,sp,304 - bfe0: 791e flw fs2,228(sp) - bfe2: 1a00 addi s0,sp,304 - bfe4: f891 bnez s1,bef8 <_start-0x7fff4108> - bfe6: 067e slli a2,a2,0x1f - bfe8: 0079 c.nop 30 - bfea: 911a add sp,sp,t1 - bfec: 7f8c flw fa1,56(a5) - bfee: 4006 0x4006 - bff0: 1e25 addi t3,t3,-23 - bff2: 8c91 sub s1,s1,a2 - bff4: 067f 0x67f - bff6: 0079 c.nop 30 - bff8: 911a add sp,sp,t1 - bffa: 7ef8 flw fa4,124(a3) - bffc: 4006 0x4006 - bffe: 1e25 addi t3,t3,-23 - c000: 9122 add sp,sp,s0 - c002: 7ef8 flw fa4,124(a3) - c004: 7906 flw fs2,96(sp) - c006: 1a00 addi s0,sp,304 - c008: 8c91 sub s1,s1,a2 - c00a: 067f 0x67f - c00c: 0079 c.nop 30 - c00e: 1e1a slli t3,t3,0x26 - c010: 2540 fld fs0,136(a0) - c012: 7922 flw fs2,40(sp) - c014: 1a00 addi s0,sp,304 - c016: 2440 fld fs0,136(s0) - c018: 8422 mv s0,s0 - c01a: 2200 fld fs0,0(a2) - c01c: 4b40 lw s0,20(a4) - c01e: 2224 fld fs1,64(a2) - c020: f891 bnez s1,bf34 <_start-0x7fff40cc> - c022: 067e slli a2,a2,0x1f - c024: 0079 c.nop 30 - c026: 911a add sp,sp,t1 - c028: 7f8c flw fa1,56(a5) - c02a: 7906 flw fs2,96(sp) - c02c: 1a00 addi s0,sp,304 - c02e: 791e flw fs2,228(sp) - c030: 1a00 addi s0,sp,304 - c032: f891 bnez s1,bf46 <_start-0x7fff40ba> - c034: 067e slli a2,a2,0x1f - c036: 0079 c.nop 30 - c038: 911a add sp,sp,t1 - c03a: 7f8c flw fa1,56(a5) - c03c: 4006 0x4006 - c03e: 1e25 addi t3,t3,-23 - c040: 8c91 sub s1,s1,a2 - c042: 067f 0x67f - c044: 0079 c.nop 30 - c046: 911a add sp,sp,t1 - c048: 7ef8 flw fa4,124(a3) - c04a: 4006 0x4006 - c04c: 1e25 addi t3,t3,-23 - c04e: 9122 add sp,sp,s0 - c050: 7ef8 flw fa4,124(a3) - c052: 7906 flw fs2,96(sp) - c054: 1a00 addi s0,sp,304 - c056: 8c91 sub s1,s1,a2 - c058: 067f 0x67f - c05a: 0079 c.nop 30 - c05c: 1e1a slli t3,t3,0x26 - c05e: 2540 fld fs0,136(a0) - c060: 7922 flw fs2,40(sp) - c062: 1a00 addi s0,sp,304 - c064: 2440 fld fs0,136(s0) - c066: 4022 0x4022 - c068: 2d22244b 0x2d22244b - c06c: e09f 000a c400 0xc400000ae09f - c072: 9b00000b 0x9b00000b - c076: 8900 0x8900 - c078: 917f 0x917f - c07a: 7ef8 flw fa4,124(a3) - c07c: 1a06 slli s4,s4,0x21 - c07e: 7f89 lui t6,0xfffe2 - c080: 8c91 sub s1,s1,a2 - c082: 067f 0x67f - c084: 1e1a slli t3,t3,0x26 - c086: 7f89 lui t6,0xfffe2 - c088: 891a mv s2,t1 - c08a: 917f 0x917f - c08c: 7ef8 flw fa4,124(a3) - c08e: 1a06 slli s4,s4,0x21 - c090: 8c91 sub s1,s1,a2 - c092: 067f 0x67f - c094: 2540 fld fs0,136(a0) - c096: 891e mv s2,t2 - c098: 917f 0x917f - c09a: 7f8c flw fa1,56(a5) - c09c: 1a06 slli s4,s4,0x21 - c09e: f891 bnez s1,bfb2 <_start-0x7fff404e> - c0a0: 067e slli a2,a2,0x1f - c0a2: 2540 fld fs0,136(a0) - c0a4: 221e fld ft4,448(sp) - c0a6: 7f89 lui t6,0xfffe2 - c0a8: f891 bnez s1,bfbc <_start-0x7fff4044> - c0aa: 067e slli a2,a2,0x1f - c0ac: 891a mv s2,t1 - c0ae: 917f 0x917f - c0b0: 7f8c flw fa1,56(a5) - c0b2: 1a06 slli s4,s4,0x21 - c0b4: 401e 0x401e - c0b6: 2225 jal c1de <_start-0x7fff3e22> - c0b8: 7f89 lui t6,0xfffe2 - c0ba: 401a 0x401a - c0bc: 2224 fld fs1,64(a2) - c0be: 0084 addi s1,sp,64 - c0c0: 4022 0x4022 - c0c2: 8922244b fnmsub.s fs0,ft4,fs2,fa7,rdn - c0c6: 917f 0x917f - c0c8: 7ef8 flw fa4,124(a3) - c0ca: 1a06 slli s4,s4,0x21 - c0cc: 7f89 lui t6,0xfffe2 - c0ce: 8c91 sub s1,s1,a2 - c0d0: 067f 0x67f - c0d2: 1e1a slli t3,t3,0x26 - c0d4: 7f89 lui t6,0xfffe2 - c0d6: 891a mv s2,t1 - c0d8: 917f 0x917f - c0da: 7ef8 flw fa4,124(a3) - c0dc: 1a06 slli s4,s4,0x21 - c0de: 8c91 sub s1,s1,a2 - c0e0: 067f 0x67f - c0e2: 2540 fld fs0,136(a0) - c0e4: 891e mv s2,t2 - c0e6: 917f 0x917f - c0e8: 7f8c flw fa1,56(a5) - c0ea: 1a06 slli s4,s4,0x21 - c0ec: f891 bnez s1,c000 <_start-0x7fff4000> - c0ee: 067e slli a2,a2,0x1f - c0f0: 2540 fld fs0,136(a0) - c0f2: 221e fld ft4,448(sp) - c0f4: 7f89 lui t6,0xfffe2 - c0f6: f891 bnez s1,c00a <_start-0x7fff3ff6> - c0f8: 067e slli a2,a2,0x1f - c0fa: 891a mv s2,t1 - c0fc: 917f 0x917f - c0fe: 7f8c flw fa1,56(a5) - c100: 1a06 slli s4,s4,0x21 - c102: 401e 0x401e - c104: 2225 jal c22c <_start-0x7fff3dd4> - c106: 7f89 lui t6,0xfffe2 - c108: 401a 0x401a - c10a: 2224 fld fs1,64(a2) - c10c: 4b40 lw s0,20(a4) - c10e: 2224 fld fs1,64(a2) - c110: 9f2d 0x9f2d - c112: 0da8 addi a0,sp,728 - c114: 0000 unimp - c116: 0db4 addi a3,sp,728 - c118: 0000 unimp - c11a: 7f89009b 0x7f89009b - c11e: f891 bnez s1,c032 <_start-0x7fff3fce> - c120: 067e slli a2,a2,0x1f - c122: 891a mv s2,t1 - c124: 917f 0x917f - c126: 7f8c flw fa1,56(a5) - c128: 1a06 slli s4,s4,0x21 - c12a: 891e mv s2,t2 - c12c: 1a7f 0x1a7f - c12e: 7f89 lui t6,0xfffe2 - c130: f891 bnez s1,c044 <_start-0x7fff3fbc> - c132: 067e slli a2,a2,0x1f - c134: 911a add sp,sp,t1 - c136: 7f8c flw fa1,56(a5) - c138: 4006 0x4006 - c13a: 1e25 addi t3,t3,-23 - c13c: 7f89 lui t6,0xfffe2 - c13e: 8c91 sub s1,s1,a2 - c140: 067f 0x67f - c142: 911a add sp,sp,t1 - c144: 7ef8 flw fa4,124(a3) - c146: 4006 0x4006 - c148: 1e25 addi t3,t3,-23 - c14a: 8922 mv s2,s0 - c14c: 917f 0x917f - c14e: 7ef8 flw fa4,124(a3) - c150: 1a06 slli s4,s4,0x21 - c152: 7f89 lui t6,0xfffe2 - c154: 8c91 sub s1,s1,a2 - c156: 067f 0x67f - c158: 1e1a slli t3,t3,0x26 - c15a: 2540 fld fs0,136(a0) - c15c: 8922 mv s2,s0 - c15e: 1a7f 0x1a7f - c160: 2440 fld fs0,136(s0) - c162: 8422 mv s0,s0 - c164: 2200 fld fs0,0(a2) - c166: 4b40 lw s0,20(a4) - c168: 2224 fld fs1,64(a2) - c16a: 7f89 lui t6,0xfffe2 - c16c: f891 bnez s1,c080 <_start-0x7fff3f80> - c16e: 067e slli a2,a2,0x1f - c170: 891a mv s2,t1 - c172: 917f 0x917f - c174: 7f8c flw fa1,56(a5) - c176: 1a06 slli s4,s4,0x21 - c178: 891e mv s2,t2 - c17a: 1a7f 0x1a7f - c17c: 7f89 lui t6,0xfffe2 - c17e: f891 bnez s1,c092 <_start-0x7fff3f6e> - c180: 067e slli a2,a2,0x1f - c182: 911a add sp,sp,t1 - c184: 7f8c flw fa1,56(a5) - c186: 4006 0x4006 - c188: 1e25 addi t3,t3,-23 - c18a: 7f89 lui t6,0xfffe2 - c18c: 8c91 sub s1,s1,a2 - c18e: 067f 0x67f - c190: 911a add sp,sp,t1 - c192: 7ef8 flw fa4,124(a3) - c194: 4006 0x4006 - c196: 1e25 addi t3,t3,-23 - c198: 8922 mv s2,s0 - c19a: 917f 0x917f - c19c: 7ef8 flw fa4,124(a3) - c19e: 1a06 slli s4,s4,0x21 - c1a0: 7f89 lui t6,0xfffe2 - c1a2: 8c91 sub s1,s1,a2 - c1a4: 067f 0x67f - c1a6: 1e1a slli t3,t3,0x26 - c1a8: 2540 fld fs0,136(a0) - c1aa: 8922 mv s2,s0 - c1ac: 1a7f 0x1a7f - c1ae: 2440 fld fs0,136(s0) - c1b0: 4022 0x4022 - c1b2: 2d22244b 0x2d22244b - c1b6: 009f 0000 0000 0x9f - c1bc: 0000 unimp - c1be: 8000 0x8000 - c1c0: 000a c.slli zero,0x2 - c1c2: 8800 0x8800 - c1c4: 000a c.slli zero,0x2 - c1c6: 1100 addi s0,sp,160 - c1c8: 7a00 flw fs0,48(a2) - c1ca: 4000 lw s0,0(s0) - c1cc: 7722244b fnmsub.q fs0,ft4,fs2,fa4,rdn - c1d0: 4000 lw s0,0(s0) - c1d2: 2d22244b 0x2d22244b - c1d6: ff08 fsw fa0,56(a4) - c1d8: 9f1a add t5,t5,t1 - c1da: 0ab0 addi a2,sp,344 - c1dc: 0000 unimp - c1de: 0af8 addi a4,sp,348 - c1e0: 0000 unimp - c1e2: 0001 nop - c1e4: 005e c.slli zero,0x17 - c1e6: 0000 unimp - c1e8: 0000 unimp - c1ea: 0000 unimp - c1ec: bc00 fsd fs0,56(s0) - c1ee: 000a c.slli zero,0x2 - c1f0: 2c00 fld fs0,24(s0) - c1f2: 0100000b 0x100000b - c1f6: 5c00 lw s0,56(s0) - ... - c200: 0abc addi a5,sp,344 - c202: 0000 unimp - c204: 0bc4 addi s1,sp,468 - c206: 0000 unimp - c208: 0001 nop - c20a: a85a fsd fs6,16(sp) - c20c: 000d c.nop 3 - c20e: b400 fsd fs0,40(s0) - c210: 000d c.nop 3 - c212: 0100 addi s0,sp,128 - c214: 5a00 lw s0,48(a2) - ... - c21e: 0abc addi a5,sp,344 - c220: 0000 unimp - c222: 0ac0 addi s0,sp,340 - c224: 0000 unimp - c226: 0006 c.slli zero,0x1 - c228: 0075 c.nop 29 - c22a: 9f1e0083 lb ra,-1551(t3) - c22e: 0ac0 addi s0,sp,340 - c230: 0000 unimp - c232: 0ac4 addi s1,sp,340 - c234: 0000 unimp - c236: 0001 nop - c238: 000ac463 bltz s5,c240 <_start-0x7fff3dc0> - c23c: c800 sw s0,16(s0) - c23e: 000a c.slli zero,0x2 - c240: 0b00 addi s0,sp,400 - c242: 9100 0x9100 - c244: 7efc flw fa5,124(a3) - c246: 7906 flw fs2,96(sp) - c248: 1a00 addi s0,sp,304 - c24a: 0075 c.nop 29 - c24c: 9f1e add t5,t5,t2 - c24e: 0acc addi a1,sp,340 - c250: 0000 unimp - c252: 0ae8 addi a0,sp,348 - c254: 0000 unimp - c256: 0001 nop - c258: e855 bnez s0,c30c <_start-0x7fff3cf4> - c25a: 000a c.slli zero,0x2 - c25c: c400 sw s0,8(s0) - c25e: 0800000b 0x800000b - c262: 7a00 flw fs0,48(a2) - c264: 4000 lw s0,0(s0) - c266: 8325 srli a4,a4,0x9 - c268: 2200 fld fs0,0(a2) - c26a: a89f 000d b400 0xb400000da89f - c270: 000d c.nop 3 - c272: 0800 addi s0,sp,16 - c274: 7a00 flw fs0,48(a2) - c276: 4000 lw s0,0(s0) - c278: 8325 srli a4,a4,0x9 - c27a: 2200 fld fs0,0(a2) - c27c: 009f 0000 0000 0x9f - c282: 0000 unimp - c284: bc00 fsd fs0,56(s0) - c286: 000a c.slli zero,0x2 - c288: c400 sw s0,8(s0) - c28a: 0100000b 0x100000b - c28e: 5600 lw s0,40(a2) - c290: 0da8 addi a0,sp,728 - c292: 0000 unimp - c294: 0db4 addi a3,sp,728 - c296: 0000 unimp - c298: 0001 nop - c29a: 0056 c.slli zero,0x15 - c29c: 0000 unimp - c29e: 0000 unimp - c2a0: 0000 unimp - c2a2: c800 sw s0,16(s0) - c2a4: 000a c.slli zero,0x2 - c2a6: 0800 addi s0,sp,16 - c2a8: 0100000b 0x100000b - c2ac: 6f00 flw fs0,24(a4) - ... - c2b6: 0abc addi a5,sp,344 - c2b8: 0000 unimp - c2ba: 0ac8 addi a0,sp,340 - c2bc: 0000 unimp - c2be: 0001 nop - c2c0: 000ac86f jal a6,b82c0 <_start-0x7ff47d40> - c2c4: c400 sw s0,8(s0) - c2c6: 0300000b 0x300000b - c2ca: 9100 0x9100 - c2cc: 7efe flw ft9,252(sp) - c2ce: 0da8 addi a0,sp,728 - c2d0: 0000 unimp - c2d2: 0db4 addi a3,sp,728 - c2d4: 0000 unimp - c2d6: fe910003 lb zero,-23(sp) - c2da: 007e c.slli zero,0x1f - c2dc: 0000 unimp - c2de: 0000 unimp - c2e0: 0000 unimp - c2e2: bc00 fsd fs0,56(s0) - c2e4: 000a c.slli zero,0x2 - c2e6: cc00 sw s0,24(s0) - c2e8: 000a c.slli zero,0x2 - c2ea: 0100 addi s0,sp,128 - c2ec: 5500 lw s0,40(a0) - c2ee: 0acc addi a1,sp,340 - c2f0: 0000 unimp - c2f2: 0bc4 addi s1,sp,468 - c2f4: 0000 unimp - c2f6: 8e910003 lb zero,-1815(sp) - c2fa: a87f 0xa87f - c2fc: 000d c.nop 3 - c2fe: b400 fsd fs0,40(s0) - c300: 000d c.nop 3 - c302: 0300 addi s0,sp,384 - c304: 9100 0x9100 - c306: 7f8e flw ft11,224(sp) - ... - c310: 0aec addi a1,sp,348 - c312: 0000 unimp - c314: 0b2c addi a1,sp,408 - c316: 0000 unimp - c318: 0001 nop - c31a: 0000005b 0x5b - c31e: 0000 unimp - c320: 0000 unimp - c322: 2000 fld fs0,0(s0) - c324: c400000b 0xc400000b - c328: 0200000b 0x200000b - c32c: 3d00 fld fs0,56(a0) - c32e: a89f 000d b400 0xb400000da89f - c334: 000d c.nop 3 - c336: 0200 addi s0,sp,256 - c338: 3d00 fld fs0,56(a0) - c33a: 009f 0000 0000 0x9f - c340: 0000 unimp - c342: 2000 fld fs0,0(s0) - c344: c400000b 0xc400000b - c348: 0200000b 0x200000b - c34c: 4300 lw s0,0(a4) - c34e: a89f 000d b400 0xb400000da89f - c354: 000d c.nop 3 - c356: 0200 addi s0,sp,256 - c358: 4300 lw s0,0(a4) - c35a: 009f 0000 0000 0x9f - c360: 0000 unimp - c362: 2000 fld fs0,0(s0) - c364: c400000b 0xc400000b - c368: 0200000b 0x200000b - c36c: 3300 fld fs0,32(a4) - c36e: a89f 000d b400 0xb400000da89f - c374: 000d c.nop 3 - c376: 0200 addi s0,sp,256 - c378: 3300 fld fs0,32(a4) - c37a: 009f 0000 0000 0x9f - c380: 0000 unimp - c382: 2000 fld fs0,0(s0) - c384: 2400000b 0x2400000b - c388: 0200000b 0x200000b - c38c: 3300 fld fs0,32(a4) - c38e: 249f 000b 2c00 0x2c00000b249f - c394: 0200000b 0x200000b - c398: 3000 fld fs0,32(s0) - c39a: 4c9f 000b c400 0xc400000b4c9f - c3a0: 0200000b 0x200000b - c3a4: 3800 fld fs0,48(s0) - c3a6: a89f 000d b400 0xb400000da89f - c3ac: 000d c.nop 3 - c3ae: 0200 addi s0,sp,256 - c3b0: 3800 fld fs0,48(s0) - c3b2: 009f 0000 0000 0x9f - c3b8: 0000 unimp - c3ba: 2000 fld fs0,0(s0) - c3bc: 2400000b 0x2400000b - c3c0: 0100000b 0x100000b - c3c4: 5500 lw s0,40(a0) - c3c6: 0b24 addi s1,sp,408 - c3c8: 0000 unimp - c3ca: 0b58 addi a4,sp,404 - c3cc: 0000 unimp - c3ce: 0001 nop - c3d0: 005f 0000 0000 0x5f - c3d6: 0000 unimp - c3d8: 7c00 flw fs0,56(s0) - c3da: c400000b 0xc400000b - c3de: 0200000b 0x200000b - c3e2: 4f00 lw s0,24(a4) - c3e4: 009f 0000 0000 0x9f - c3ea: 0000 unimp - c3ec: 7c00 flw fs0,56(s0) - c3ee: c400000b 0xc400000b - c3f2: 0200000b 0x200000b - c3f6: 3100 fld fs0,32(a0) - c3f8: 009f 0000 0000 0x9f - c3fe: 0000 unimp - c400: 7c00 flw fs0,56(s0) - c402: c400000b 0xc400000b - c406: 0200000b 0x200000b - c40a: 3000 fld fs0,32(s0) - c40c: 009f 0000 0000 0x9f - c412: 0000 unimp - c414: 7c00 flw fs0,56(s0) - c416: 8800000b 0x8800000b - c41a: 0200000b 0x200000b - c41e: 3000 fld fs0,32(s0) - c420: a89f 000b c400 0xc400000ba89f - c426: 0200000b 0x200000b - c42a: 3400 fld fs0,40(s0) - c42c: 009f 0000 0000 0x9f - c432: 0000 unimp - c434: 7c00 flw fs0,56(s0) - c436: 8000000b 0x8000000b - c43a: 0200000b 0x200000b - c43e: 3000 fld fs0,32(s0) - c440: 809f 000b b000 0xb000000b809f - c446: 0100000b 0x100000b - c44a: 5f00 lw s0,56(a4) - ... - c454: 0c00 addi s0,sp,528 - c456: 0000 unimp - c458: 0c08 addi a0,sp,528 - c45a: 0000 unimp - c45c: 0001 nop - c45e: 085e slli a6,a6,0x17 - c460: 000c 0xc - c462: 0c00 addi s0,sp,528 - c464: 000c 0xc - c466: 0f00 addi s0,sp,912 - c468: 9100 0x9100 - c46a: 7f90 flw fa2,56(a5) - c46c: 4006 0x4006 - c46e: 0c22244b 0xc22244b - c472: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8a88> - c476: 9f2c 0x9f2c - c478: 0c0c addi a1,sp,528 - c47a: 0000 unimp - c47c: 0c1c addi a5,sp,528 - c47e: 0000 unimp - c480: 0001 nop - c482: 1c5e slli s8,s8,0x37 - c484: 000c 0xc - c486: 2400 fld fs0,8(s0) - c488: 000c 0xc - c48a: 0600 addi s0,sp,768 - c48c: 7d00 flw fs0,56(a0) - c48e: 0800 addi s0,sp,16 - c490: 1aff 0x1aff - c492: 249f 000c 2800 0x2800000c249f - c498: 000c 0xc - c49a: 2900 fld fs0,16(a0) - c49c: 9100 0x9100 - c49e: 7f98 flw fa4,56(a5) - c4a0: 4006 0x4006 - c4a2: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - c4a6: 7f94 flw fa3,56(a5) - c4a8: 4006 0x4006 - c4aa: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - c4ae: 7f90 flw fa2,56(a5) - c4b0: 4006 0x4006 - c4b2: 0c22244b 0xc22244b - c4b6: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8a88> - c4ba: 402c lw a1,64(s0) - c4bc: 2d22244b 0x2d22244b - c4c0: 4b40 lw s0,20(a4) - c4c2: 2224 fld fs1,64(a2) - c4c4: 9f2d 0x9f2d - ... - c4ce: 0c50 addi a2,sp,532 - c4d0: 0000 unimp - c4d2: 0c90 addi a2,sp,592 - c4d4: 0000 unimp - c4d6: 0002 c.slli64 zero - c4d8: 9f4d 0x9f4d - c4da: 0db4 addi a3,sp,728 - c4dc: 0000 unimp - c4de: 0dcc addi a1,sp,724 - c4e0: 0000 unimp - c4e2: 0002 c.slli64 zero - c4e4: 9f4d 0x9f4d - ... - c4ee: 0c50 addi a2,sp,532 - c4f0: 0000 unimp - c4f2: 0c90 addi a2,sp,592 - c4f4: 0000 unimp - c4f6: 0002 c.slli64 zero - c4f8: 0db49f33 0xdb49f33 - c4fc: 0000 unimp - c4fe: 0dcc addi a1,sp,724 - c500: 0000 unimp - c502: 0002 c.slli64 zero - c504: 00009f33 sll t5,ra,zero - c508: 0000 unimp - c50a: 0000 unimp - c50c: 0000 unimp - c50e: 0c50 addi a2,sp,532 - c510: 0000 unimp - c512: 0c90 addi a2,sp,592 - c514: 0000 unimp - c516: 0002 c.slli64 zero - c518: 9f30 0x9f30 - c51a: 0db4 addi a3,sp,728 - c51c: 0000 unimp - c51e: 0dcc addi a1,sp,724 - c520: 0000 unimp - c522: 0002 c.slli64 zero - c524: 9f30 0x9f30 - ... - c52e: 0c50 addi a2,sp,532 - c530: 0000 unimp - c532: 0c58 addi a4,sp,532 - c534: 0000 unimp - c536: 0002 c.slli64 zero - c538: 9f30 0x9f30 - c53a: 0c78 addi a4,sp,540 - c53c: 0000 unimp - c53e: 0c90 addi a2,sp,592 - c540: 0000 unimp - c542: 0002 c.slli64 zero - c544: 9f34 0x9f34 - c546: 0db4 addi a3,sp,728 - c548: 0000 unimp - c54a: 0dcc addi a1,sp,724 - c54c: 0000 unimp - c54e: 0002 c.slli64 zero - c550: 9f34 0x9f34 - ... - c55a: 0edc addi a5,sp,852 - c55c: 0000 unimp - c55e: 0ee4 addi s1,sp,860 - c560: 0000 unimp - c562: 0008 0x8 - c564: 007e c.slli zero,0x1f - c566: 2e30 fld fa2,88(a2) - c568: ff08 fsw fa0,56(a4) - c56a: 9f1a add t5,t5,t1 - ... - c574: 0de8 addi a0,sp,732 - c576: 0000 unimp - c578: 0e04 addi s1,sp,784 - c57a: 0000 unimp - c57c: 0006 c.slli zero,0x1 - c57e: 2008 fld fa0,0(s0) - c580: 007f 0x7f - c582: 9f1c 0x9f1c - c584: 0e04 addi s1,sp,784 - c586: 0000 unimp - c588: 0e24 addi s1,sp,792 - c58a: 0000 unimp - c58c: 000e c.slli zero,0x3 - c58e: 2008 fld fa0,0(s0) - c590: 91c0020b 0x91c0020b - c594: 7edc flw fa5,60(a3) - c596: 1c06 slli s8,s8,0x21 - c598: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - c59c: 0e24 addi s1,sp,792 - c59e: 0000 unimp - c5a0: 0e88 addi a0,sp,848 - c5a2: 0000 unimp - c5a4: 0006 c.slli zero,0x1 - c5a6: 2008 fld fa0,0(s0) - c5a8: 007f 0x7f - c5aa: 9f1c 0x9f1c - c5ac: 0e88 addi a0,sp,848 - c5ae: 0000 unimp - c5b0: 0e98 addi a4,sp,848 - c5b2: 0000 unimp - c5b4: 000e c.slli zero,0x3 - c5b6: 2008 fld fa0,0(s0) - c5b8: 91c0020b 0x91c0020b - c5bc: 7edc flw fa5,60(a3) - c5be: 1c06 slli s8,s8,0x21 - c5c0: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - c5c4: 0e98 addi a4,sp,848 - c5c6: 0000 unimp - c5c8: 0ec4 addi s1,sp,852 - c5ca: 0000 unimp - c5cc: 0006 c.slli zero,0x1 - c5ce: 2008 fld fa0,0(s0) - c5d0: 007f 0x7f - c5d2: 9f1c 0x9f1c - c5d4: 0ec4 addi s1,sp,852 - c5d6: 0000 unimp - c5d8: 0f54 addi a3,sp,916 - c5da: 0000 unimp - c5dc: 000e c.slli zero,0x3 - c5de: 2008 fld fa0,0(s0) - c5e0: 91c0020b 0x91c0020b - c5e4: 7edc flw fa5,60(a3) - c5e6: 1c06 slli s8,s8,0x21 - c5e8: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - c5ec: 0f54 addi a3,sp,916 - c5ee: 0000 unimp - c5f0: 0f58 addi a4,sp,916 - c5f2: 0000 unimp - c5f4: 0011 c.nop 4 - c5f6: 2008 fld fa0,0(s0) - c5f8: 007f 0x7f - c5fa: dc91 beqz s1,c516 <_start-0x7fff3aea> - c5fc: 067e slli a2,a2,0x1f - c5fe: 0a1c addi a5,sp,272 - c600: 3fff 0x3fff - c602: 4f1c lw a5,24(a4) - c604: 1c1a slli s8,s8,0x26 - c606: 589f 000f 8c00 0x8c00000f589f - c60c: 0e00000f fence ior,unknown - c610: 0800 addi s0,sp,16 - c612: 0b20 addi s0,sp,408 - c614: c002 sw zero,0(sp) - c616: dc91 beqz s1,c532 <_start-0x7fff3ace> - c618: 067e slli a2,a2,0x1f - c61a: 4f1c lw a5,24(a4) - c61c: 1c1a slli s8,s8,0x26 - c61e: 009f 0000 0000 0x9f - c624: 0000 unimp - c626: e800 fsw fs0,16(s0) - c628: 000d c.nop 3 - c62a: 0400 addi s0,sp,512 - c62c: 000e c.slli zero,0x3 - c62e: 0100 addi s0,sp,128 - c630: 5f00 lw s0,56(a4) - c632: 0e04 addi s1,sp,784 - c634: 0000 unimp - c636: 0e24 addi s1,sp,792 - c638: 0000 unimp - c63a: 020b000b 0x20b000b - c63e: 91c0 0x91c0 - c640: 7edc flw fa5,60(a3) - c642: 1c06 slli s8,s8,0x21 - c644: 249f1a4f 0x249f1a4f - c648: 000e c.slli zero,0x3 - c64a: 8800 0x8800 - c64c: 000e c.slli zero,0x3 - c64e: 0100 addi s0,sp,128 - c650: 5f00 lw s0,56(a4) - c652: 0e88 addi a0,sp,848 - c654: 0000 unimp - c656: 0e98 addi a4,sp,848 - c658: 0000 unimp - c65a: 020b000b 0x20b000b - c65e: 91c0 0x91c0 - c660: 7edc flw fa5,60(a3) - c662: 1c06 slli s8,s8,0x21 - c664: 989f1a4f fnmadd.s fs4,ft10,fs1,fs3,rtz - c668: 000e c.slli zero,0x3 - c66a: c400 sw s0,8(s0) - c66c: 000e c.slli zero,0x3 - c66e: 0100 addi s0,sp,128 - c670: 5f00 lw s0,56(a4) - c672: 0ec4 addi s1,sp,852 - c674: 0000 unimp - c676: 0f54 addi a3,sp,916 - c678: 0000 unimp - c67a: 020b000b 0x20b000b - c67e: 91c0 0x91c0 - c680: 7edc flw fa5,60(a3) - c682: 1c06 slli s8,s8,0x21 - c684: 549f1a4f 0x549f1a4f - c688: 5800000f 0x5800000f - c68c: 0e00000f fence ior,unknown - c690: 7f00 flw fs0,56(a4) - c692: 9100 0x9100 - c694: 7edc flw fa5,60(a3) - c696: 1c06 slli s8,s8,0x21 - c698: ff0a fsw ft2,188(sp) - c69a: 1a4f1c3f 000f589f 0xf589f1a4f1c3f - c6a2: 8c00 0x8c00 - c6a4: 0b00000f fence irw,unknown - c6a8: 0b00 addi s0,sp,400 - c6aa: c002 sw zero,0(sp) - c6ac: dc91 beqz s1,c5c8 <_start-0x7fff3a38> - c6ae: 067e slli a2,a2,0x1f - c6b0: 4f1c lw a5,24(a4) - c6b2: 9f1a add t5,t5,t1 - ... - c6bc: 0de0 addi s0,sp,732 - c6be: 0000 unimp - c6c0: 0f8c addi a1,sp,976 - c6c2: 0000 unimp - c6c4: 0001 nop - c6c6: 0061 c.nop 24 - c6c8: 0000 unimp - c6ca: 0000 unimp - c6cc: 0000 unimp - c6ce: e800 fsw fs0,16(s0) - c6d0: 000d c.nop 3 - c6d2: ec00 fsw fs0,24(s0) - c6d4: 000d c.nop 3 - c6d6: 0200 addi s0,sp,256 - c6d8: 3000 fld fs0,32(s0) - c6da: ec9f 000d 0400 0x400000dec9f - c6e0: 000e c.slli zero,0x3 - c6e2: 0100 addi s0,sp,128 - c6e4: 5d00 lw s0,56(a0) - c6e6: 0e04 addi s1,sp,784 - c6e8: 0000 unimp - c6ea: 0e1c addi a5,sp,784 - c6ec: 0000 unimp - c6ee: 0001 nop - c6f0: 245f 000e 3400 0x3400000e245f - c6f6: 000e c.slli zero,0x3 - c6f8: 0100 addi s0,sp,128 - c6fa: 5d00 lw s0,56(a0) - c6fc: 0e34 addi a3,sp,792 - c6fe: 0000 unimp - c700: 0e38 addi a4,sp,792 - c702: 0000 unimp - c704: 7f7d0003 lb zero,2039(s10) - c708: 389f 000e 4000 0x4000000e389f - c70e: 000e c.slli zero,0x3 - c710: 0100 addi s0,sp,128 - c712: 5d00 lw s0,56(a0) - c714: 0e58 addi a4,sp,788 - c716: 0000 unimp - c718: 0e6c addi a1,sp,796 - c71a: 0000 unimp - c71c: 0002 c.slli64 zero - c71e: 9f30 0x9f30 - c720: 0e6c addi a1,sp,796 - c722: 0000 unimp - c724: 0e74 addi a3,sp,796 - c726: 0000 unimp - c728: 0001 nop - c72a: 745a flw fs0,180(sp) - c72c: 000e c.slli zero,0x3 - c72e: 7c00 flw fs0,56(s0) - c730: 000e c.slli zero,0x3 - c732: 0300 addi s0,sp,384 - c734: 7d00 flw fs0,56(a0) - c736: 9f01 0x9f01 - c738: 0e7c addi a5,sp,796 - c73a: 0000 unimp - c73c: 0e98 addi a4,sp,848 - c73e: 0000 unimp - c740: 0005 c.nop 1 - c742: 8134 0x8134 - c744: 1c00 addi s0,sp,560 - c746: 989f 000e b000 0xb000000e989f - c74c: 000e c.slli zero,0x3 - c74e: 0100 addi s0,sp,128 - c750: 5a00 lw s0,48(a2) - c752: 0eb0 addi a2,sp,856 - c754: 0000 unimp - c756: 0ec0 addi s0,sp,852 - c758: 0000 unimp - c75a: 7f7a0003 lb zero,2039(s4) # fffeb7f7 <__BSS_END__+0x7ffd4a7f> - c75e: c09f 000e c400 0xc400000ec09f - c764: 000e c.slli zero,0x3 - c766: 0100 addi s0,sp,128 - c768: 5a00 lw s0,48(a2) - c76a: 0ec4 addi s1,sp,852 - c76c: 0000 unimp - c76e: 0f00 addi s0,sp,912 - c770: 0000 unimp - c772: 0001 nop - c774: 005f 0000 0000 0x5f - c77a: 0000 unimp - c77c: e800 fsw fs0,16(s0) - c77e: 000d c.nop 3 - c780: ec00 fsw fs0,24(s0) - c782: 000d c.nop 3 - c784: 0200 addi s0,sp,256 - c786: 3000 fld fs0,32(s0) - c788: ec9f 000d e400 0xe400000dec9f - c78e: 000e c.slli zero,0x3 - c790: 0100 addi s0,sp,128 - c792: 5e00 lw s0,56(a2) - ... - c79c: 0f0c addi a1,sp,912 - c79e: 0000 unimp - c7a0: 0f14 addi a3,sp,912 - c7a2: 0000 unimp - c7a4: 0001 nop - c7a6: 145e slli s0,s0,0x37 - c7a8: 1800000f 0x1800000f - c7ac: 0f00000f fence iorw,unknown - c7b0: 9100 0x9100 - c7b2: 7f90 flw fa2,56(a5) - c7b4: 4006 0x4006 - c7b6: 0c22244b 0xc22244b - c7ba: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8a88> - c7be: 9f2c 0x9f2c - c7c0: 0f18 addi a4,sp,912 - c7c2: 0000 unimp - c7c4: 0f28 addi a0,sp,920 - c7c6: 0000 unimp - c7c8: 0001 nop - c7ca: 285e fld fa6,464(sp) - c7cc: 3000000f 0x3000000f - c7d0: 0600000f fence or,unknown - c7d4: 7f00 flw fs0,56(a4) - c7d6: 0800 addi s0,sp,16 - c7d8: 1aff 0x1aff - c7da: 309f 000f 3400 0x3400000f309f - c7e0: 2900000f 0x2900000f - c7e4: 9100 0x9100 - c7e6: 7f98 flw fa4,56(a5) - c7e8: 4006 0x4006 - c7ea: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - c7ee: 7f94 flw fa3,56(a5) - c7f0: 4006 0x4006 - c7f2: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - c7f6: 7f90 flw fa2,56(a5) - c7f8: 4006 0x4006 - c7fa: 0c22244b 0xc22244b - c7fe: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8a88> - c802: 402c lw a1,64(s0) - c804: 2d22244b 0x2d22244b - c808: 4b40 lw s0,20(a4) - c80a: 2224 fld fs1,64(a2) - c80c: 9f2d 0x9f2d - ... - c816: 0f80 addi s0,sp,976 - c818: 0000 unimp - c81a: 0f8c addi a1,sp,976 - c81c: 0000 unimp - c81e: 0002 c.slli64 zero - c820: 9f34 0x9f34 - ... - c82e: 044c addi a1,sp,516 - c830: 0000 unimp - c832: 0002 c.slli64 zero - c834: 9f30 0x9f30 - c836: 044c addi a1,sp,516 - c838: 0000 unimp - c83a: 0450 addi a2,sp,516 - c83c: 0000 unimp - c83e: 0002 c.slli64 zero - c840: 9f35 0x9f35 - c842: 0450 addi a2,sp,516 - c844: 0000 unimp - c846: 0498 addi a4,sp,576 - c848: 0000 unimp - c84a: 0002 c.slli64 zero - c84c: 9f30 0x9f30 - c84e: 0604 addi s1,sp,768 - c850: 0000 unimp - c852: 094c addi a1,sp,148 - c854: 0000 unimp - c856: 0002 c.slli64 zero - c858: 9f30 0x9f30 - c85a: 09dc addi a5,sp,212 - c85c: 0000 unimp - c85e: 0a60 addi s0,sp,284 - c860: 0000 unimp - c862: 0002 c.slli64 zero - c864: 9f30 0x9f30 - c866: 0a60 addi s0,sp,284 - c868: 0000 unimp - c86a: 0a68 addi a0,sp,284 - c86c: 0000 unimp - c86e: 0002 c.slli64 zero - c870: 9f35 0x9f35 - c872: 0a68 addi a0,sp,284 - c874: 0000 unimp - c876: 1134 addi a3,sp,168 - c878: 0000 unimp - c87a: 0002 c.slli64 zero - c87c: 9f30 0x9f30 - c87e: 11e4 addi s1,sp,236 - c880: 0000 unimp - c882: 150c addi a1,sp,672 - c884: 0000 unimp - c886: 0002 c.slli64 zero - c888: 9f30 0x9f30 - ... - c892: 0078 addi a4,sp,12 - c894: 0000 unimp - c896: 023c addi a5,sp,264 - c898: 0000 unimp - c89a: 0001 nop - c89c: 4462 lw s0,24(sp) - c89e: 0002 c.slli64 zero - c8a0: 9800 0x9800 - c8a2: 0004 0x4 - c8a4: 0100 addi s0,sp,128 - c8a6: 6200 flw fs0,0(a2) - c8a8: 0604 addi s1,sp,768 - c8aa: 0000 unimp - c8ac: 09cc addi a1,sp,212 - c8ae: 0000 unimp - c8b0: 0001 nop - c8b2: dc62 sw s8,56(sp) - c8b4: 0009 c.nop 2 - c8b6: 1000 addi s0,sp,32 - c8b8: 0100000b 0x100000b - c8bc: 6200 flw fs0,0(a2) - c8be: 0b18 addi a4,sp,400 - c8c0: 0000 unimp - c8c2: 0ce0 addi s0,sp,604 - c8c4: 0000 unimp - c8c6: 0001 nop - c8c8: 0062 c.slli zero,0x18 - c8ca: 000d c.nop 3 - c8cc: 4c00 lw s0,24(s0) - c8ce: 000d c.nop 3 - c8d0: 0100 addi s0,sp,128 - c8d2: 6200 flw fs0,0(a2) - c8d4: 0d50 addi a2,sp,660 - c8d6: 0000 unimp - c8d8: 0db8 addi a4,sp,728 - c8da: 0000 unimp - c8dc: 0001 nop - c8de: c862 sw s8,16(sp) - c8e0: 000d c.nop 3 - c8e2: d800 sw s0,48(s0) - c8e4: 0100000f fence w,unknown - c8e8: 6200 flw fs0,0(a2) - c8ea: 0fdc addi a5,sp,980 - c8ec: 0000 unimp - c8ee: 103c addi a5,sp,40 - c8f0: 0000 unimp - c8f2: 0001 nop - c8f4: 4c62 lw s8,24(sp) - c8f6: 0010 0x10 - c8f8: 8c00 0x8c00 - c8fa: 0011 c.nop 4 - c8fc: 0100 addi s0,sp,128 - c8fe: 6200 flw fs0,0(a2) - c900: 1194 addi a3,sp,224 - c902: 0000 unimp - c904: 12a0 addi s0,sp,360 - c906: 0000 unimp - c908: 0001 nop - c90a: 0062 c.slli zero,0x18 - c90c: 14000013 li zero,320 - c910: 01000013 li zero,16 - c914: 6200 flw fs0,0(a2) - ... - c91e: 0074 addi a3,sp,12 - c920: 0000 unimp - c922: 01e8 addi a0,sp,204 - c924: 0000 unimp - c926: 0001 nop - c928: ec58 fsw fa4,28(s0) - c92a: 0001 nop - c92c: 3c00 fld fs0,56(s0) - c92e: 0002 c.slli64 zero - c930: 0100 addi s0,sp,128 - c932: 5800 lw s0,48(s0) - c934: 0244 addi s1,sp,260 - c936: 0000 unimp - c938: 03c4 addi s1,sp,452 - c93a: 0000 unimp - c93c: 0001 nop - c93e: 5058 lw a4,36(s0) - c940: 0004 0x4 - c942: 9800 0x9800 - c944: 0004 0x4 - c946: 0100 addi s0,sp,128 - c948: 5800 lw s0,48(s0) - c94a: 0604 addi s1,sp,768 - c94c: 0000 unimp - c94e: 06a8 addi a0,sp,840 - c950: 0000 unimp - c952: 0001 nop - c954: c058 sw a4,4(s0) - c956: 0006 c.slli zero,0x1 - c958: 1800 addi s0,sp,48 - c95a: 0008 0x8 - c95c: 0100 addi s0,sp,128 - c95e: 5800 lw s0,48(s0) - c960: 0860 addi s0,sp,28 - c962: 0000 unimp - c964: 0948 addi a0,sp,148 - c966: 0000 unimp - c968: 0001 nop - c96a: 4858 lw a4,20(s0) - c96c: 0009 c.nop 2 - c96e: 4c00 lw s0,24(s0) - c970: 0009 c.nop 2 - c972: 0300 addi s0,sp,384 - c974: 8e00 0x8e00 - c976: 9f7f 0x9f7f - c978: 094c addi a1,sp,148 - c97a: 0000 unimp - c97c: 0964 addi s1,sp,156 - c97e: 0000 unimp - c980: 0001 nop - c982: 6458 flw fa4,12(s0) - c984: 0009 c.nop 2 - c986: 6800 flw fs0,16(s0) - c988: 0009 c.nop 2 - c98a: 0300 addi s0,sp,384 - c98c: 8e00 0x8e00 - c98e: 9f7f 0x9f7f - c990: 0968 addi a0,sp,156 - c992: 0000 unimp - c994: 09c8 addi a0,sp,212 - c996: 0000 unimp - c998: 0001 nop - c99a: dc58 sw a4,60(s0) - c99c: 0009 c.nop 2 - c99e: 6400 flw fs0,8(s0) - c9a0: 000a c.slli zero,0x2 - c9a2: 0100 addi s0,sp,128 - c9a4: 5800 lw s0,48(s0) - c9a6: 0a64 addi s1,sp,284 - c9a8: 0000 unimp - c9aa: 0a68 addi a0,sp,284 - c9ac: 0000 unimp - c9ae: 7f8e0003 lb zero,2040(t3) - c9b2: 689f 000a 1400 0x1400000a689f - c9b8: 0100000b 0x100000b - c9bc: 5800 lw s0,48(s0) - c9be: 0b18 addi a4,sp,400 - c9c0: 0000 unimp - c9c2: 0ce0 addi s0,sp,604 - c9c4: 0000 unimp - c9c6: 0001 nop - c9c8: 0058 addi a4,sp,4 - c9ca: 000d c.nop 3 - c9cc: 3400 fld fs0,40(s0) - c9ce: 000d c.nop 3 - c9d0: 0100 addi s0,sp,128 - c9d2: 5800 lw s0,48(s0) - c9d4: 0d50 addi a2,sp,660 - c9d6: 0000 unimp - c9d8: 0e0c addi a1,sp,784 - c9da: 0000 unimp - c9dc: 0001 nop - c9de: 2458 fld fa4,136(s0) - c9e0: 000e c.slli zero,0x3 - c9e2: c800 sw s0,16(s0) - c9e4: 0100000f fence w,unknown - c9e8: 5800 lw s0,48(s0) - c9ea: 0fdc addi a5,sp,980 - c9ec: 0000 unimp - c9ee: 1044 addi s1,sp,36 - c9f0: 0000 unimp - c9f2: 0001 nop - c9f4: 4c58 lw a4,28(s0) - c9f6: 0010 0x10 - c9f8: 9000 0x9000 - c9fa: 0011 c.nop 4 - c9fc: 0100 addi s0,sp,128 - c9fe: 5800 lw s0,48(s0) - ca00: 1194 addi a3,sp,224 - ca02: 0000 unimp - ca04: 12a0 addi s0,sp,360 - ca06: 0000 unimp - ca08: 0001 nop - ca0a: 0058 addi a4,sp,4 - ca0c: 14000013 li zero,320 - ca10: 01000013 li zero,16 - ca14: 5800 lw s0,48(s0) - ... - ca1e: 00e0 addi s0,sp,76 - ca20: 0000 unimp - ca22: 0140 addi s0,sp,132 - ca24: 0000 unimp - ca26: 0006 c.slli zero,0x1 - ca28: 0080 addi s0,sp,64 - ca2a: ff08 fsw fa0,56(a4) - ca2c: 9f1a add t5,t5,t1 - ca2e: 0140 addi s0,sp,132 - ca30: 0000 unimp - ca32: 015c addi a5,sp,132 - ca34: 0000 unimp - ca36: 0001 nop - ca38: 1860 addi s0,sp,60 - ca3a: 0002 c.slli64 zero - ca3c: 3c00 fld fs0,56(s0) - ca3e: 0002 c.slli64 zero - ca40: 0100 addi s0,sp,128 - ca42: 6000 flw fs0,0(s0) - ca44: 0244 addi s1,sp,260 - ca46: 0000 unimp - ca48: 0260 addi s0,sp,268 - ca4a: 0000 unimp - ca4c: 0001 nop - ca4e: 5060 lw s0,100(s0) - ca50: 0004 0x4 - ca52: 6400 flw fs0,8(s0) - ca54: 0004 0x4 - ca56: 0100 addi s0,sp,128 - ca58: 6000 flw fs0,0(s0) - ca5a: 0690 addi a2,sp,832 - ca5c: 0000 unimp - ca5e: 06dc addi a5,sp,836 - ca60: 0000 unimp - ca62: 0001 nop - ca64: 6060 flw fs0,68(s0) - ca66: 0008 0x8 - ca68: 8c00 0x8c00 - ca6a: 0008 0x8 - ca6c: 0100 addi s0,sp,128 - ca6e: 6000 flw fs0,0(s0) - ca70: 0a7c addi a5,sp,284 - ca72: 0000 unimp - ca74: 0a88 addi a0,sp,336 - ca76: 0000 unimp - ca78: 0001 nop - ca7a: 4460 lw s0,76(s0) - ca7c: 6c00000b 0x6c00000b - ca80: 0100000b 0x100000b - ca84: 6000 flw fs0,0(s0) - ca86: 0d00 addi s0,sp,656 - ca88: 0000 unimp - ca8a: 12a0 addi s0,sp,360 - ca8c: 0000 unimp - ca8e: 0001 nop - ca90: 0060 addi s0,sp,12 - ca92: 14000013 li zero,320 - ca96: 01000013 li zero,16 - ca9a: 6000 flw fs0,0(s0) - ... - caa4: 00dc addi a5,sp,68 - caa6: 0000 unimp - caa8: 0158 addi a4,sp,132 - caaa: 0000 unimp - caac: 0001 nop - caae: 585c lw a5,52(s0) - cab0: 0001 nop - cab2: e400 fsw fs0,8(s0) - cab4: 0001 nop - cab6: 0800 addi s0,sp,16 - cab8: 9100 0x9100 - caba: 065c addi a5,sp,772 - cabc: 2431 jal ccc8 <_start-0x7fff3338> - cabe: 2541 jal d13e <_start-0x7fff2ec2> - cac0: ec9f 0001 1800 0x18000001ec9f - cac6: 0002 c.slli64 zero - cac8: 0800 addi s0,sp,16 - caca: 9100 0x9100 - cacc: 065c addi a5,sp,772 - cace: 2431 jal ccda <_start-0x7fff3326> - cad0: 2541 jal d150 <_start-0x7fff2eb0> - cad2: 189f 0002 3c00 0x3c000002189f - cad8: 0002 c.slli64 zero - cada: 0100 addi s0,sp,128 - cadc: 5c00 lw s0,56(s0) - cade: 0244 addi s1,sp,260 - cae0: 0000 unimp - cae2: 0260 addi s0,sp,268 - cae4: 0000 unimp - cae6: 0001 nop - cae8: 605c flw fa5,4(s0) - caea: 0002 c.slli64 zero - caec: c400 sw s0,8(s0) - caee: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - caf2: 9100 0x9100 - caf4: 065c addi a5,sp,772 - caf6: 2431 jal cd02 <_start-0x7fff32fe> - caf8: 2541 jal d178 <_start-0x7fff2e88> - cafa: 509f 0004 9000 0x90000004509f - cb00: 0004 0x4 - cb02: 0100 addi s0,sp,128 - cb04: 5c00 lw s0,56(s0) - cb06: 0490 addi a2,sp,576 - cb08: 0000 unimp - cb0a: 0494 addi a3,sp,576 - cb0c: 0000 unimp - cb0e: 0008 0x8 - cb10: 5c91 li s9,-28 - cb12: 3106 fld ft2,96(sp) - cb14: 4124 lw s1,64(a0) - cb16: 9f25 0x9f25 - cb18: 0604 addi s1,sp,768 - cb1a: 0000 unimp - cb1c: 061c addi a5,sp,768 - cb1e: 0000 unimp - cb20: 0001 nop - cb22: 1c5c addi a5,sp,564 - cb24: 0006 c.slli zero,0x1 - cb26: 6000 flw fs0,0(s0) - cb28: 0006 c.slli zero,0x1 - cb2a: 0800 addi s0,sp,16 - cb2c: 9100 0x9100 - cb2e: 065c addi a5,sp,772 - cb30: 2431 jal cd3c <_start-0x7fff32c4> - cb32: 2541 jal d1b2 <_start-0x7fff2e4e> - cb34: 649f 0006 6c00 0x6c000006649f - cb3a: 0008 0x8 - cb3c: 0100 addi s0,sp,128 - cb3e: 5c00 lw s0,56(s0) - cb40: 086c addi a1,sp,28 - cb42: 0000 unimp - cb44: 0890 addi a2,sp,80 - cb46: 0000 unimp - cb48: 0008 0x8 - cb4a: 5c91 li s9,-28 - cb4c: 3106 fld ft2,96(sp) - cb4e: 4124 lw s1,64(a0) - cb50: 9f25 0x9f25 - cb52: 0890 addi a2,sp,80 - cb54: 0000 unimp - cb56: 08b8 addi a4,sp,88 - cb58: 0000 unimp - cb5a: 0008 0x8 - cb5c: 008d addi ra,ra,3 - cb5e: 3106 fld ft2,96(sp) - cb60: 4124 lw s1,64(a0) - cb62: 9f25 0x9f25 - cb64: 08bc addi a5,sp,88 - cb66: 0000 unimp - cb68: 08dc addi a5,sp,84 - cb6a: 0000 unimp - cb6c: 0008 0x8 - cb6e: 008d addi ra,ra,3 - cb70: 3106 fld ft2,96(sp) - cb72: 4124 lw s1,64(a0) - cb74: 9f25 0x9f25 - cb76: 08e0 addi s0,sp,92 - cb78: 0000 unimp - cb7a: 0930 addi a2,sp,152 - cb7c: 0000 unimp - cb7e: 0008 0x8 - cb80: 008d addi ra,ra,3 - cb82: 3106 fld ft2,96(sp) - cb84: 4124 lw s1,64(a0) - cb86: 9f25 0x9f25 - cb88: 0934 addi a3,sp,152 - cb8a: 0000 unimp - cb8c: 0944 addi s1,sp,148 - cb8e: 0000 unimp - cb90: 0008 0x8 - cb92: 008d addi ra,ra,3 - cb94: 3106 fld ft2,96(sp) - cb96: 4124 lw s1,64(a0) - cb98: 9f25 0x9f25 - cb9a: 094c addi a1,sp,148 - cb9c: 0000 unimp - cb9e: 0960 addi s0,sp,156 - cba0: 0000 unimp - cba2: 0008 0x8 - cba4: 008d addi ra,ra,3 - cba6: 3106 fld ft2,96(sp) - cba8: 4124 lw s1,64(a0) - cbaa: 9f25 0x9f25 - cbac: 0968 addi a0,sp,156 - cbae: 0000 unimp - cbb0: 0988 addi a0,sp,208 - cbb2: 0000 unimp - cbb4: 0008 0x8 - cbb6: 008d addi ra,ra,3 - cbb8: 3106 fld ft2,96(sp) - cbba: 4124 lw s1,64(a0) - cbbc: 9f25 0x9f25 - cbbe: 098c addi a1,sp,208 - cbc0: 0000 unimp - cbc2: 0990 addi a2,sp,208 - cbc4: 0000 unimp - cbc6: 0008 0x8 - cbc8: 008d addi ra,ra,3 - cbca: 3106 fld ft2,96(sp) - cbcc: 4124 lw s1,64(a0) - cbce: 9f25 0x9f25 - cbd0: 09dc addi a5,sp,212 - cbd2: 0000 unimp - cbd4: 0a24 addi s1,sp,280 - cbd6: 0000 unimp - cbd8: 0008 0x8 - cbda: 008d addi ra,ra,3 - cbdc: 3106 fld ft2,96(sp) - cbde: 4124 lw s1,64(a0) - cbe0: 9f25 0x9f25 - cbe2: 0a7c addi a5,sp,284 - cbe4: 0000 unimp - cbe6: 0a8c addi a1,sp,336 - cbe8: 0000 unimp - cbea: 0001 nop - cbec: 8c5c 0x8c5c - cbee: 000a c.slli zero,0x2 - cbf0: 1000 addi s0,sp,32 - cbf2: 0800000b 0x800000b - cbf6: 9100 0x9100 - cbf8: 065c addi a5,sp,772 - cbfa: 2431 jal ce06 <_start-0x7fff31fa> - cbfc: 2541 jal d27c <_start-0x7fff2d84> - cbfe: 189f 000b 4400 0x4400000b189f - cc04: 0800000b 0x800000b - cc08: 9100 0x9100 - cc0a: 065c addi a5,sp,772 - cc0c: 2431 jal ce18 <_start-0x7fff31e8> - cc0e: 2541 jal d28e <_start-0x7fff2d72> - cc10: 449f 000b 6c00 0x6c00000b449f - cc16: 0100000b 0x100000b - cc1a: 5c00 lw s0,56(s0) - cc1c: 0b6c addi a1,sp,412 - cc1e: 0000 unimp - cc20: 0ce0 addi s0,sp,604 - cc22: 0000 unimp - cc24: 0008 0x8 - cc26: 5c91 li s9,-28 - cc28: 3106 fld ft2,96(sp) - cc2a: 4124 lw s1,64(a0) - cc2c: 9f25 0x9f25 - cc2e: 0d00 addi s0,sp,656 - cc30: 0000 unimp - cc32: 0d48 addi a0,sp,660 - cc34: 0000 unimp - cc36: 0001 nop - cc38: 505c lw a5,36(s0) - cc3a: 000d c.nop 3 - cc3c: 6800 flw fs0,16(s0) - cc3e: 000d c.nop 3 - cc40: 0100 addi s0,sp,128 - cc42: 5c00 lw s0,56(s0) - cc44: 0d68 addi a0,sp,668 - cc46: 0000 unimp - cc48: 0dc4 addi s1,sp,724 - cc4a: 0000 unimp - cc4c: 0008 0x8 - cc4e: 5c91 li s9,-28 - cc50: 3106 fld ft2,96(sp) - cc52: 4124 lw s1,64(a0) - cc54: 9f25 0x9f25 - cc56: 0dc8 addi a0,sp,724 - cc58: 0000 unimp - cc5a: 0ff0 addi a2,sp,988 - cc5c: 0000 unimp - cc5e: 0001 nop - cc60: f05c fsw fa5,36(s0) - cc62: 3800000f 0x3800000f - cc66: 0010 0x10 - cc68: 0800 addi s0,sp,16 - cc6a: 9100 0x9100 - cc6c: 065c addi a5,sp,772 - cc6e: 2431 jal ce7a <_start-0x7fff3186> - cc70: 2541 jal d2f0 <_start-0x7fff2d10> - cc72: 4c9f 0010 6000 0x600000104c9f - cc78: 0010 0x10 - cc7a: 0800 addi s0,sp,16 - cc7c: 9100 0x9100 - cc7e: 065c addi a5,sp,772 - cc80: 2431 jal ce8c <_start-0x7fff3174> - cc82: 2541 jal d302 <_start-0x7fff2cfe> - cc84: 649f 0010 c000 0xc0000010649f - cc8a: 0010 0x10 - cc8c: 0800 addi s0,sp,16 - cc8e: 9100 0x9100 - cc90: 065c addi a5,sp,772 - cc92: 2431 jal ce9e <_start-0x7fff3162> - cc94: 2541 jal d314 <_start-0x7fff2cec> - cc96: 349f 0011 4400 0x44000011349f - cc9c: 0011 c.nop 4 - cc9e: 0800 addi s0,sp,16 - cca0: 9100 0x9100 - cca2: 065c addi a5,sp,772 - cca4: 2431 jal ceb0 <_start-0x7fff3150> - cca6: 2541 jal d326 <_start-0x7fff2cda> - cca8: 789f 0011 8800 0x88000011789f - ccae: 0011 c.nop 4 - ccb0: 0800 addi s0,sp,16 - ccb2: 9100 0x9100 - ccb4: 065c addi a5,sp,772 - ccb6: 2431 jal cec2 <_start-0x7fff313e> - ccb8: 2541 jal d338 <_start-0x7fff2cc8> - ccba: 949f 0011 a800 0xa8000011949f - ccc0: 0011 c.nop 4 - ccc2: 0800 addi s0,sp,16 - ccc4: 9100 0x9100 - ccc6: 065c addi a5,sp,772 - ccc8: 2431 jal ced4 <_start-0x7fff312c> - ccca: 2541 jal d34a <_start-0x7fff2cb6> - cccc: ac9f 0011 b000 0xb0000011ac9f - ccd2: 0011 c.nop 4 - ccd4: 0800 addi s0,sp,16 - ccd6: 9100 0x9100 - ccd8: 065c addi a5,sp,772 - ccda: 2431 jal cee6 <_start-0x7fff311a> - ccdc: 2541 jal d35c <_start-0x7fff2ca4> - ccde: e49f 0011 4000 0x40000011e49f - cce4: 0012 c.slli zero,0x4 - cce6: 0800 addi s0,sp,16 - cce8: 9100 0x9100 - ccea: 065c addi a5,sp,772 - ccec: 2431 jal cef8 <_start-0x7fff3108> - ccee: 2541 jal d36e <_start-0x7fff2c92> - ccf0: 009f 0000 0000 0x9f - ccf6: 0000 unimp - ccf8: 9c00 0x9c00 - ccfa: 0009 c.nop 2 - ccfc: c000 sw s0,0(s0) - ccfe: 0009 c.nop 2 - cd00: 0200 addi s0,sp,256 - cd02: 3300 fld fs0,32(a4) - cd04: bc9f 0011 e400 0xe4000011bc9f - cd0a: 0011 c.nop 4 - cd0c: 0200 addi s0,sp,256 - cd0e: 3300 fld fs0,32(a4) - cd10: 009f 0000 0000 0x9f - cd16: 0000 unimp - cd18: 4800 lw s0,16(s0) - cd1a: 0001 nop - cd1c: 8400 0x8400 - cd1e: 0005 c.nop 1 - cd20: 0100 addi s0,sp,128 - cd22: 6200 flw fs0,0(a2) - cd24: 0584 addi s1,sp,704 - cd26: 0000 unimp - cd28: 0588 addi a0,sp,704 - cd2a: 0000 unimp - cd2c: 0002 c.slli64 zero - cd2e: 9f30 0x9f30 - cd30: 0588 addi a0,sp,704 - cd32: 0000 unimp - cd34: 05bc addi a5,sp,712 - cd36: 0000 unimp - cd38: 0001 nop - cd3a: 0462 slli s0,s0,0x18 - cd3c: 0006 c.slli zero,0x1 - cd3e: 8c00 0x8c00 - cd40: 0009 c.nop 2 - cd42: 0100 addi s0,sp,128 - cd44: 6200 flw fs0,0(a2) - cd46: 098c addi a1,sp,208 - cd48: 0000 unimp - cd4a: 09dc addi a5,sp,212 - cd4c: 0000 unimp - cd4e: 0002 c.slli64 zero - cd50: 9f30 0x9f30 - cd52: 09dc addi a5,sp,212 - cd54: 0000 unimp - cd56: 0a7c addi a5,sp,284 - cd58: 0000 unimp - cd5a: 0001 nop - cd5c: 8062 c.mv zero,s8 - cd5e: 000a c.slli zero,0x2 - cd60: 0000 unimp - cd62: 000d c.nop 3 - cd64: 0100 addi s0,sp,128 - cd66: 6200 flw fs0,0(a2) - cd68: 0d08 addi a0,sp,656 - cd6a: 0000 unimp - cd6c: 0fdc addi a5,sp,980 - cd6e: 0000 unimp - cd70: 0001 nop - cd72: 6060 flw fs0,68(s0) - cd74: 0010 0x10 - cd76: 6400 flw fs0,8(s0) - cd78: 0010 0x10 - cd7a: 0100 addi s0,sp,128 - cd7c: 6200 flw fs0,0(a2) - cd7e: 10c0 addi s0,sp,100 - cd80: 0000 unimp - cd82: 1134 addi a3,sp,168 - cd84: 0000 unimp - cd86: 0001 nop - cd88: 4062 0x4062 - cd8a: 0011 c.nop 4 - cd8c: 7800 flw fs0,48(s0) - cd8e: 0011 c.nop 4 - cd90: 0200 addi s0,sp,256 - cd92: 3000 fld fs0,32(s0) - cd94: 789f 0011 8c00 0x8c000011789f - cd9a: 0011 c.nop 4 - cd9c: 0100 addi s0,sp,128 - cd9e: 6000 flw fs0,0(s0) - cda0: 118c addi a1,sp,224 - cda2: 0000 unimp - cda4: 1194 addi a3,sp,224 - cda6: 0000 unimp - cda8: 0001 nop - cdaa: 9862 add a6,a6,s8 - cdac: 0011 c.nop 4 - cdae: ac00 fsd fs0,24(s0) - cdb0: 0011 c.nop 4 - cdb2: 0100 addi s0,sp,128 - cdb4: 6200 flw fs0,0(a2) - cdb6: 11ac addi a1,sp,232 - cdb8: 0000 unimp - cdba: 11e4 addi s1,sp,236 - cdbc: 0000 unimp - cdbe: 0002 c.slli64 zero - cdc0: 9f30 0x9f30 - cdc2: 1240 addi s0,sp,292 - cdc4: 0000 unimp - cdc6: 129c addi a5,sp,352 - cdc8: 0000 unimp - cdca: 0001 nop - cdcc: 9c62 add s8,s8,s8 - cdce: 0012 c.slli zero,0x4 - cdd0: a000 fsd fs0,0(s0) - cdd2: 0012 c.slli zero,0x4 - cdd4: 0100 addi s0,sp,128 - cdd6: 6000 flw fs0,0(s0) - cdd8: 12a0 addi s0,sp,360 - cdda: 0000 unimp - cddc: 1520 addi s0,sp,680 - cdde: 0000 unimp - cde0: 0001 nop - cde2: 0062 c.slli zero,0x18 - cde4: 0000 unimp - cde6: 0000 unimp - cde8: 0000 unimp - cdea: 4c00 lw s0,24(s0) - cdec: 0001 nop - cdee: e400 fsw fs0,8(s0) - cdf0: 0001 nop - cdf2: 0100 addi s0,sp,128 - cdf4: 5800 lw s0,48(s0) - cdf6: 01ec addi a1,sp,204 - cdf8: 0000 unimp - cdfa: 043c addi a5,sp,520 - cdfc: 0000 unimp - cdfe: 0001 nop - ce00: 3c58 fld fa4,184(s0) - ce02: 0004 0x4 - ce04: 5000 lw s0,32(s0) - ce06: 0004 0x4 - ce08: 0400 addi s0,sp,512 - ce0a: 0a00 addi s0,sp,272 - ce0c: 7fff 0x7fff - ce0e: 589f 0004 9000 0x90000004589f - ce14: 0004 0x4 - ce16: 0100 addi s0,sp,128 - ce18: 5c00 lw s0,56(s0) - ce1a: 0498 addi a4,sp,576 - ce1c: 0000 unimp - ce1e: 0590 addi a2,sp,704 - ce20: 0000 unimp - ce22: 0001 nop - ce24: 0458 addi a4,sp,516 - ce26: 0006 c.slli zero,0x1 - ce28: 1c00 addi s0,sp,560 - ce2a: 0006 c.slli zero,0x1 - ce2c: 0100 addi s0,sp,128 - ce2e: 5c00 lw s0,56(s0) - ce30: 061c addi a5,sp,768 - ce32: 0000 unimp - ce34: 0660 addi s0,sp,780 - ce36: 0000 unimp - ce38: 0008 0x8 - ce3a: 5c91 li s9,-28 - ce3c: 3106 fld ft2,96(sp) - ce3e: 4124 lw s1,64(a0) - ce40: 9f25 0x9f25 - ce42: 0664 addi s1,sp,780 - ce44: 0000 unimp - ce46: 0860 addi s0,sp,28 - ce48: 0000 unimp - ce4a: 0001 nop - ce4c: a45c fsd fa5,136(s0) - ce4e: 0008 0x8 - ce50: 4400 lw s0,8(s0) - ce52: 0009 c.nop 2 - ce54: 0200 addi s0,sp,256 - ce56: 3000 fld fs0,32(s0) - ce58: 449f 0009 4c00 0x4c000009449f - ce5e: 0009 c.nop 2 - ce60: 0200 addi s0,sp,256 - ce62: 3100 fld fs0,32(a0) - ce64: 4c9f 0009 dc00 0xdc0000094c9f - ce6a: 0009 c.nop 2 - ce6c: 0400 addi s0,sp,512 - ce6e: 0a00 addi s0,sp,272 - ce70: 7fff 0x7fff - ce72: 249f 000a 6000 0x6000000a249f - ce78: 000a c.slli zero,0x2 - ce7a: 0100 addi s0,sp,128 - ce7c: 6e00 flw fs0,24(a2) - ce7e: 0a60 addi s0,sp,284 - ce80: 0000 unimp - ce82: 0a7c addi a5,sp,284 - ce84: 0000 unimp - ce86: 0004 0x4 - ce88: ff0a fsw ft2,188(sp) - ce8a: 9f7f 0x9f7f - ce8c: 0a80 addi s0,sp,336 - ce8e: 0000 unimp - ce90: 0b10 addi a2,sp,400 - ce92: 0000 unimp - ce94: 0001 nop - ce96: 1858 addi a4,sp,52 - ce98: 0000000b 0xb - ce9c: 000d c.nop 3 - ce9e: 0100 addi s0,sp,128 - cea0: 5800 lw s0,48(s0) - cea2: 0d08 addi a0,sp,656 - cea4: 0000 unimp - cea6: 0d48 addi a0,sp,660 - cea8: 0000 unimp - ceaa: 0001 nop - ceac: 505c lw a5,36(s0) - ceae: 000d c.nop 3 - ceb0: 6800 flw fs0,16(s0) - ceb2: 000d c.nop 3 - ceb4: 0100 addi s0,sp,128 - ceb6: 5c00 lw s0,56(s0) - ceb8: 0d68 addi a0,sp,668 - ceba: 0000 unimp - cebc: 0dc4 addi s1,sp,724 - cebe: 0000 unimp - cec0: 0008 0x8 - cec2: 5c91 li s9,-28 - cec4: 3106 fld ft2,96(sp) - cec6: 4124 lw s1,64(a0) - cec8: 9f25 0x9f25 - ceca: 0dc8 addi a0,sp,724 - cecc: 0000 unimp - cece: 0fdc addi a5,sp,980 - ced0: 0000 unimp - ced2: 0001 nop - ced4: 245c fld fa5,136(s0) - ced6: 0010 0x10 - ced8: 4000 lw s0,0(s0) - ceda: 0010 0x10 - cedc: 0200 addi s0,sp,256 - cede: 3000 fld fs0,32(s0) - cee0: 4c9f 0010 3400 0x340000104c9f - cee6: 0011 c.nop 4 - cee8: 0200 addi s0,sp,256 - ceea: 3000 fld fs0,32(s0) - ceec: 349f 0011 e400 0xe4000011349f - cef2: 0011 c.nop 4 - cef4: 0400 addi s0,sp,512 - cef6: 0a00 addi s0,sp,272 - cef8: 7fff 0x7fff - cefa: e49f 0011 c000 0xc0000011e49f - cf00: 01000013 li zero,16 - cf04: 5800 lw s0,48(s0) - cf06: 14f0 addi a2,sp,620 - cf08: 0000 unimp - cf0a: 14f4 addi a3,sp,620 - cf0c: 0000 unimp - cf0e: 0002 c.slli64 zero - cf10: 9f30 0x9f30 - cf12: 14f4 addi a3,sp,620 - cf14: 0000 unimp - cf16: 150c addi a1,sp,672 - cf18: 0000 unimp - cf1a: 0001 nop - cf1c: 0c58 addi a4,sp,532 - cf1e: 0015 c.nop 5 - cf20: 2000 fld fs0,0(s0) - cf22: 0015 c.nop 5 - cf24: 0400 addi s0,sp,512 - cf26: 0a00 addi s0,sp,272 - cf28: 7fff 0x7fff - cf2a: 009f 0000 0000 0x9f - cf30: 0000 unimp - cf32: cc00 sw s0,24(s0) - cf34: 0005 c.nop 1 - cf36: d400 sw s0,40(s0) - cf38: 0005 c.nop 1 - cf3a: 0e00 addi s0,sp,784 - cf3c: 9100 0x9100 - cf3e: 9350 0x9350 - cf40: 5f04 lw s1,56(a4) - cf42: 58910493 addi s1,sp,1417 - cf46: 93580493 addi s1,a6,-1739 - cf4a: d404 sw s1,40(s0) - cf4c: 0005 c.nop 1 - cf4e: e000 fsw fs0,0(s0) - cf50: 0005 c.nop 1 - cf52: 0f00 addi s0,sp,912 - cf54: 9100 0x9100 - cf56: 9350 0x9350 - cf58: 9104 0x9104 - cf5a: 9354 0x9354 - cf5c: 9104 0x9104 - cf5e: 9358 0x9358 - cf60: 5804 lw s1,48(s0) - cf62: 05e00493 li s1,94 - cf66: 0000 unimp - cf68: 05f0 addi a2,sp,716 - cf6a: 0000 unimp - cf6c: 0010 0x10 - cf6e: 5091 li ra,-28 - cf70: 54910493 addi s1,sp,1353 - cf74: 58910493 addi s1,sp,1417 - cf78: 0c790493 addi s1,s2,199 - cf7c: 05f00493 li s1,95 - cf80: 0000 unimp - cf82: 0600 addi s0,sp,768 - cf84: 0000 unimp - cf86: 0010 0x10 - cf88: 5091 li ra,-28 - cf8a: 54910493 addi s1,sp,1353 - cf8e: 58910493 addi s1,sp,1417 - cf92: 0c7a0493 addi s1,s4,199 - cf96: 06000493 li s1,96 - cf9a: 0000 unimp - cf9c: 0604 addi s1,sp,768 - cf9e: 0000 unimp - cfa0: 5072000f 0x5072000f - cfa4: 54720493 addi s1,tp,1351 # 547 <_start-0x7ffffab9> - cfa8: 935f0493 addi s1,t5,-1739 - cfac: 7a04 flw fs1,48(a2) - cfae: 930c 0x930c - cfb0: 0004 0x4 - cfb2: 0000 unimp - cfb4: 0000 unimp - cfb6: 0000 unimp - cfb8: 7800 flw fs0,48(s0) - cfba: 0000 unimp - cfbc: 8000 0x8000 - cfbe: 0000 unimp - cfc0: 0200 addi s0,sp,256 - cfc2: 3300 fld fs0,32(a4) - cfc4: a09f 0000 2000 0x20000000a09f - cfca: 0015 c.nop 5 - cfcc: 0300 addi s0,sp,384 - cfce: 0900 addi s0,sp,144 - cfd0: 9fff 0x9fff - ... - cfda: 00e0 addi s0,sp,76 - cfdc: 0000 unimp - cfde: 00e8 addi a0,sp,76 - cfe0: 0000 unimp - cfe2: 0002 c.slli64 zero - cfe4: 01089f33 sll t5,a7,a6 - cfe8: 0000 unimp - cfea: 1520 addi s0,sp,680 - cfec: 0000 unimp - cfee: ff090003 lb zero,-16(s2) - cff2: 009f 0000 0000 0x9f - cff8: 0000 unimp - cffa: 4800 lw s0,16(s0) - cffc: 0001 nop - cffe: 6c00 flw fs0,24(s0) - d000: 0001 nop - d002: 0100 addi s0,sp,128 - d004: 5a00 lw s0,48(a2) - d006: 0188 addi a0,sp,192 - d008: 0000 unimp - d00a: 018c addi a1,sp,192 - d00c: 0000 unimp - d00e: 0001 nop - d010: 8c5a mv s8,s6 - d012: 0001 nop - d014: 9400 0x9400 - d016: 0001 nop - d018: 0100 addi s0,sp,128 - d01a: 5d00 lw s0,56(a0) - d01c: 0194 addi a3,sp,192 - d01e: 0000 unimp - d020: 01e4 addi s1,sp,204 - d022: 0000 unimp - d024: 7f7a0003 lb zero,2039(s4) - d028: ec9f 0001 0000 0x1ec9f - d02e: 0002 c.slli64 zero - d030: 0100 addi s0,sp,128 - d032: 5d00 lw s0,56(a0) - d034: 0218 addi a4,sp,256 - d036: 0000 unimp - d038: 0224 addi s1,sp,264 - d03a: 0000 unimp - d03c: 0001 nop - d03e: 445a lw s0,148(sp) - d040: 0002 c.slli64 zero - d042: 6000 flw fs0,0(s0) - d044: 0002 c.slli64 zero - d046: 0100 addi s0,sp,128 - d048: 5a00 lw s0,48(a2) - d04a: 0450 addi a2,sp,516 - d04c: 0000 unimp - d04e: 0458 addi a4,sp,516 - d050: 0000 unimp - d052: 0006 c.slli zero,0x1 - d054: 0078 addi a4,sp,12 - d056: 007c addi a5,sp,12 - d058: 9f1c 0x9f1c - d05a: 0458 addi a4,sp,516 - d05c: 0000 unimp - d05e: 0478 addi a4,sp,524 - d060: 0000 unimp - d062: 0001 nop - d064: 045a slli s0,s0,0x16 - d066: 0006 c.slli zero,0x1 - d068: 0800 addi s0,sp,16 - d06a: 0006 c.slli zero,0x1 - d06c: 0100 addi s0,sp,128 - d06e: 5a00 lw s0,48(a2) - d070: 0608 addi a0,sp,768 - d072: 0000 unimp - d074: 0610 addi a2,sp,768 - d076: 0000 unimp - d078: 0001 nop - d07a: 105d c.nop -9 - d07c: 0006 c.slli zero,0x1 - d07e: 6400 flw fs0,8(s0) - d080: 0006 c.slli zero,0x1 - d082: 0300 addi s0,sp,384 - d084: 7a00 flw fs0,48(a2) - d086: 9f7f 0x9f7f - d088: 0664 addi s1,sp,780 - d08a: 0000 unimp - d08c: 0678 addi a4,sp,780 - d08e: 0000 unimp - d090: 0001 nop - d092: 905d srli s0,s0,0x37 - d094: 0006 c.slli zero,0x1 - d096: dc00 sw s0,56(s0) - d098: 0006 c.slli zero,0x1 - d09a: 0100 addi s0,sp,128 - d09c: 5a00 lw s0,48(a2) - d09e: 06dc addi a5,sp,836 - d0a0: 0000 unimp - d0a2: 06f0 addi a2,sp,844 - d0a4: 0000 unimp - d0a6: 0001 nop - d0a8: 605d c.lui zero,0x17 - d0aa: 0008 0x8 - d0ac: 6c00 flw fs0,24(s0) - d0ae: 0008 0x8 - d0b0: 0600 addi s0,sp,768 - d0b2: 7800 flw fs0,48(s0) - d0b4: 7c00 flw fs0,56(s0) - d0b6: 1c00 addi s0,sp,560 - d0b8: 6c9f 0008 9000 0x900000086c9f - d0be: 0008 0x8 - d0c0: 0b00 addi s0,sp,400 - d0c2: 7800 flw fs0,48(s0) - d0c4: 9100 0x9100 - d0c6: 065c addi a5,sp,772 - d0c8: 2431 jal d2d4 <_start-0x7fff2d2c> - d0ca: 2541 jal d74a <_start-0x7fff28b6> - d0cc: 9f1c 0x9f1c - d0ce: 0890 addi a2,sp,80 - d0d0: 0000 unimp - d0d2: 08b8 addi a4,sp,88 - d0d4: 0000 unimp - d0d6: 0078000b 0x78000b - d0da: 008d addi ra,ra,3 - d0dc: 3106 fld ft2,96(sp) - d0de: 4124 lw s1,64(a0) - d0e0: 1c25 addi s8,s8,-23 - d0e2: bc9f 0008 dc00 0xdc000008bc9f - d0e8: 0008 0x8 - d0ea: 0b00 addi s0,sp,400 - d0ec: 7800 flw fs0,48(s0) - d0ee: 8d00 0x8d00 - d0f0: 0600 addi s0,sp,768 - d0f2: 2431 jal d2fe <_start-0x7fff2d02> - d0f4: 2541 jal d774 <_start-0x7fff288c> - d0f6: 9f1c 0x9f1c - d0f8: 08e0 addi s0,sp,92 - d0fa: 0000 unimp - d0fc: 0930 addi a2,sp,152 - d0fe: 0000 unimp - d100: 0078000b 0x78000b - d104: 008d addi ra,ra,3 - d106: 3106 fld ft2,96(sp) - d108: 4124 lw s1,64(a0) - d10a: 1c25 addi s8,s8,-23 - d10c: 349f 0009 4400 0x44000009349f - d112: 0009 c.nop 2 - d114: 0b00 addi s0,sp,400 - d116: 7800 flw fs0,48(s0) - d118: 8d00 0x8d00 - d11a: 0600 addi s0,sp,768 - d11c: 2431 jal d328 <_start-0x7fff2cd8> - d11e: 2541 jal d79e <_start-0x7fff2862> - d120: 9f1c 0x9f1c - d122: 094c addi a1,sp,148 - d124: 0000 unimp - d126: 0960 addi s0,sp,156 - d128: 0000 unimp - d12a: 0078000b 0x78000b - d12e: 008d addi ra,ra,3 - d130: 3106 fld ft2,96(sp) - d132: 4124 lw s1,64(a0) - d134: 1c25 addi s8,s8,-23 - d136: 689f 0009 8800 0x88000009689f - d13c: 0009 c.nop 2 - d13e: 0b00 addi s0,sp,400 - d140: 7800 flw fs0,48(s0) - d142: 8d00 0x8d00 - d144: 0600 addi s0,sp,768 - d146: 2431 jal d352 <_start-0x7fff2cae> - d148: 2541 jal d7c8 <_start-0x7fff2838> - d14a: 9f1c 0x9f1c - d14c: 098c addi a1,sp,208 - d14e: 0000 unimp - d150: 0990 addi a2,sp,208 - d152: 0000 unimp - d154: 0078000b 0x78000b - d158: 008d addi ra,ra,3 - d15a: 3106 fld ft2,96(sp) - d15c: 4124 lw s1,64(a0) - d15e: 1c25 addi s8,s8,-23 - d160: dc9f 0009 2400 0x24000009dc9f - d166: 000a c.slli zero,0x2 - d168: 0b00 addi s0,sp,400 - d16a: 7800 flw fs0,48(s0) - d16c: 8d00 0x8d00 - d16e: 0600 addi s0,sp,768 - d170: 2431 jal d37c <_start-0x7fff2c84> - d172: 2541 jal d7f2 <_start-0x7fff280e> - d174: 9f1c 0x9f1c - ... - d17e: 01a4 addi s1,sp,200 - d180: 0000 unimp - d182: 01ac addi a1,sp,200 - d184: 0000 unimp - d186: 0001 nop - d188: ac5e fsd fs7,24(sp) - d18a: 0001 nop - d18c: e400 fsw fs0,8(s0) - d18e: 0001 nop - d190: 1000 addi s0,sp,32 - d192: 8c00 0x8c00 - d194: 0600 addi s0,sp,768 - d196: 4b40 lw s0,20(a4) - d198: 2224 fld fs1,64(a2) - d19a: 5091 li ra,-28 - d19c: 4006 0x4006 - d19e: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d1a2: 009f 0000 0000 0x9f - d1a8: 0000 unimp - d1aa: a400 fsd fs0,8(s0) - d1ac: 0001 nop - d1ae: b800 fsd fs0,48(s0) - d1b0: 0001 nop - d1b2: 1100 addi s0,sp,160 - d1b4: 7d00 flw fs0,56(a0) - d1b6: 4000 lw s0,0(s0) - d1b8: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - d1bc: 4000 lw s0,0(s0) - d1be: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d1c2: ff08 fsw fa0,56(a4) - d1c4: 9f1a add t5,t5,t1 - d1c6: 01b8 addi a4,sp,200 - d1c8: 0000 unimp - d1ca: 01bc addi a5,sp,200 - d1cc: 0000 unimp - d1ce: b4910013 addi zero,sp,-1207 - d1d2: 067f 0x67f - d1d4: 4b40 lw s0,20(a4) - d1d6: 2224 fld fs1,64(a2) - d1d8: 4b40007b 0x4b40007b - d1dc: 2224 fld fs1,64(a2) - d1de: 1aff082b 0x1aff082b - d1e2: bc9f 0001 c800 0xc8000001bc9f - d1e8: 0001 nop - d1ea: 0100 addi s0,sp,128 - d1ec: 5e00 lw s0,56(a2) - d1ee: 01c8 addi a0,sp,196 - d1f0: 0000 unimp - d1f2: 01e4 addi s1,sp,204 - d1f4: 0000 unimp - d1f6: 002c addi a1,sp,8 - d1f8: b491 j cc3c <_start-0x7fff33c4> - d1fa: 067f 0x67f - d1fc: 4b40 lw s0,20(a4) - d1fe: 2224 fld fs1,64(a2) - d200: 4b40007b 0x4b40007b - d204: 2224 fld fs1,64(a2) - d206: 0654912b 0x654912b - d20a: 4b40 lw s0,20(a4) - d20c: 2224 fld fs1,64(a2) - d20e: 008c addi a1,sp,64 - d210: 4006 0x4006 - d212: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d216: 0650 addi a2,sp,772 - d218: 4b40 lw s0,20(a4) - d21a: 2224 fld fs1,64(a2) - d21c: 244b402b 0x244b402b - d220: 2d22 fld fs10,8(sp) - d222: 9f21 0x9f21 - ... - d22c: 01c0 addi s0,sp,196 - d22e: 0000 unimp - d230: 01cc addi a1,sp,196 - d232: 0000 unimp - d234: 0011 c.nop 4 - d236: 007f 0x7f - d238: 4b40 lw s0,20(a4) - d23a: 2224 fld fs1,64(a2) - d23c: 007d c.nop 31 - d23e: 4b40 lw s0,20(a4) - d240: 2224 fld fs1,64(a2) - d242: 1aff082b 0x1aff082b - d246: cc9f 0001 d800 0xd8000001cc9f - d24c: 0001 nop - d24e: 1300 addi s0,sp,416 - d250: 9100 0x9100 - d252: 7fb8 flw fa4,120(a5) - d254: 4006 0x4006 - d256: 7d22244b 0x7d22244b - d25a: 4000 lw s0,0(s0) - d25c: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d260: ff08 fsw fa0,56(a4) - d262: 9f1a add t5,t5,t1 - ... - d26c: 034c addi a1,sp,388 - d26e: 0000 unimp - d270: 0354 addi a3,sp,388 - d272: 0000 unimp - d274: 0008 0x8 - d276: 007c addi a5,sp,12 - d278: 2e30 fld fa2,88(a2) - d27a: ff08 fsw fa0,56(a4) - d27c: 9f1a add t5,t5,t1 - ... - d286: 0268 addi a0,sp,268 - d288: 0000 unimp - d28a: 0284 addi s1,sp,320 - d28c: 0000 unimp - d28e: 0006 c.slli zero,0x1 - d290: 2008 fld fa0,0(s0) - d292: 007f 0x7f - d294: 9f1c 0x9f1c - d296: 02a4 addi s1,sp,328 - d298: 0000 unimp - d29a: 0300 addi s0,sp,384 - d29c: 0000 unimp - d29e: 0006 c.slli zero,0x1 - d2a0: 2008 fld fa0,0(s0) - d2a2: 007f 0x7f - d2a4: 9f1c 0x9f1c - d2a6: 0310 addi a2,sp,384 - d2a8: 0000 unimp - d2aa: 0338 addi a4,sp,392 - d2ac: 0000 unimp - d2ae: 0006 c.slli zero,0x1 - d2b0: 2008 fld fa0,0(s0) - d2b2: 007f 0x7f - d2b4: 9f1c 0x9f1c - ... - d2be: 0268 addi a0,sp,268 - d2c0: 0000 unimp - d2c2: 0284 addi s1,sp,320 - d2c4: 0000 unimp - d2c6: 0001 nop - d2c8: a45f 0002 0000 0x2a45f - d2ce: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - d2d2: 5f00 lw s0,56(a4) - d2d4: 0310 addi a2,sp,384 - d2d6: 0000 unimp - d2d8: 0338 addi a4,sp,392 - d2da: 0000 unimp - d2dc: 0001 nop - d2de: 005f 0000 0000 0x5f - d2e4: 0000 unimp - d2e6: 6400 flw fs0,8(s0) - d2e8: 0002 c.slli64 zero - d2ea: 5c00 lw s0,56(s0) - d2ec: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - d2f0: 6c00 flw fs0,24(s0) - ... - d2fa: 0268 addi a0,sp,268 - d2fc: 0000 unimp - d2fe: 0270 addi a2,sp,268 - d300: 0000 unimp - d302: 0002 c.slli64 zero - d304: 9f30 0x9f30 - d306: 0270 addi a2,sp,268 - d308: 0000 unimp - d30a: 0284 addi s1,sp,320 - d30c: 0000 unimp - d30e: 0001 nop - d310: 845e mv s0,s7 - d312: 0002 c.slli64 zero - d314: 9c00 0x9c00 - d316: 0002 c.slli64 zero - d318: 0100 addi s0,sp,128 - d31a: 5f00 lw s0,56(a4) - d31c: 02a4 addi s1,sp,328 - d31e: 0000 unimp - d320: 02b0 addi a2,sp,328 - d322: 0000 unimp - d324: 0001 nop - d326: b05e fsd fs7,32(sp) - d328: 0002 c.slli64 zero - d32a: b400 fsd fs0,40(s0) - d32c: 0002 c.slli64 zero - d32e: 0300 addi s0,sp,384 - d330: 7e00 flw fs0,56(a2) - d332: 9f7f 0x9f7f - d334: 02b4 addi a3,sp,328 - d336: 0000 unimp - d338: 02bc addi a5,sp,328 - d33a: 0000 unimp - d33c: 0001 nop - d33e: d45e sw s7,40(sp) - d340: 0002 c.slli64 zero - d342: e400 fsw fs0,8(s0) - d344: 0002 c.slli64 zero - d346: 0200 addi s0,sp,256 - d348: 3000 fld fs0,32(s0) - d34a: e49f 0002 ec00 0xec000002e49f - d350: 0002 c.slli64 zero - d352: 0100 addi s0,sp,128 - d354: 5a00 lw s0,48(a2) - d356: 02ec addi a1,sp,332 - d358: 0000 unimp - d35a: 02f4 addi a3,sp,332 - d35c: 0000 unimp - d35e: 017e0003 lb zero,23(t3) - d362: f49f 0002 1000 0x10000002f49f - d368: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> - d36c: 3400 fld fs0,40(s0) - d36e: 008c addi a1,sp,64 - d370: 9f1c 0x9f1c - d372: 0310 addi a2,sp,384 - d374: 0000 unimp - d376: 0330 addi a2,sp,392 - d378: 0000 unimp - d37a: 0001 nop - d37c: 305a fld ft0,432(sp) - d37e: 34000003 lb zero,832(zero) # 340 <_start-0x7ffffcc0> - d382: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - d386: 7a00 flw fs0,48(a2) - d388: 9f01 0x9f01 - d38a: 0334 addi a3,sp,392 - d38c: 0000 unimp - d38e: 0338 addi a4,sp,392 - d390: 0000 unimp - d392: 0001 nop - d394: 385a fld fa6,432(sp) - d396: 50000003 lb zero,1280(zero) # 500 <_start-0x7ffffb00> - d39a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - d39e: 5f00 lw s0,56(a4) - ... - d3a8: 0268 addi a0,sp,268 - d3aa: 0000 unimp - d3ac: 0270 addi a2,sp,268 - d3ae: 0000 unimp - d3b0: 0002 c.slli64 zero - d3b2: 9f30 0x9f30 - d3b4: 0270 addi a2,sp,268 - d3b6: 0000 unimp - d3b8: 0354 addi a3,sp,388 - d3ba: 0000 unimp - d3bc: 0001 nop - d3be: 005c addi a5,sp,4 - d3c0: 0000 unimp - d3c2: 0000 unimp - d3c4: 0000 unimp - d3c6: 7800 flw fs0,48(s0) - d3c8: 9c000003 lb zero,-1600(zero) # fffff9c0 <__BSS_END__+0x7ffe8c48> - d3cc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - d3d0: 5d00 lw s0,56(a0) - d3d2: 039c addi a5,sp,448 - d3d4: 0000 unimp - d3d6: 03c4 addi s1,sp,452 - d3d8: 0000 unimp - d3da: 0011 c.nop 4 - d3dc: b091 j cc20 <_start-0x7fff33e0> - d3de: 067f 0x67f - d3e0: 4b40 lw s0,20(a4) - d3e2: 2224 fld fs1,64(a2) - d3e4: 5091 li ra,-28 - d3e6: 4006 0x4006 - d3e8: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d3ec: 009f 0000 0000 0x9f - d3f2: 0000 unimp - d3f4: 8400 0x8400 - d3f6: 8c000003 lb zero,-1856(zero) # fffff8c0 <__BSS_END__+0x7ffe8b48> - d3fa: 11000003 lb zero,272(zero) # 110 <_start-0x7ffffef0> - d3fe: 7e00 flw fs0,56(a2) - d400: 4000 lw s0,0(s0) - d402: 7f22244b fnmsub.q fs0,ft4,fs2,fa5,rdn - d406: 4000 lw s0,0(s0) - d408: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d40c: ff08 fsw fa0,56(a4) - d40e: 9f1a add t5,t5,t1 - d410: 038c addi a1,sp,448 - d412: 0000 unimp - d414: 0390 addi a2,sp,448 - d416: 0000 unimp - d418: b4910013 addi zero,sp,-1207 - d41c: 067f 0x67f - d41e: 4b40 lw s0,20(a4) - d420: 2224 fld fs1,64(a2) - d422: 007f 0x7f - d424: 4b40 lw s0,20(a4) - d426: 2224 fld fs1,64(a2) - d428: 1aff082b 0x1aff082b - d42c: 909f 0003 a000 0xa0000003909f - d432: 19000003 lb zero,400(zero) # 190 <_start-0x7ffffe70> - d436: 9100 0x9100 - d438: 7fb4 flw fa3,120(a5) - d43a: 4006 0x4006 - d43c: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d440: 7fb4 flw fa3,120(a5) - d442: 9106 add sp,sp,ra - d444: 0644 addi s1,sp,772 - d446: 4022 0x4022 - d448: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d44c: ff08 fsw fa0,56(a4) - d44e: 9f1a add t5,t5,t1 - d450: 03a0 addi s0,sp,456 - d452: 0000 unimp - d454: 03b0 addi a2,sp,456 - d456: 0000 unimp - d458: 0001 nop - d45a: b05f 0003 c400 0xc4000003b05f - d460: 33000003 lb zero,816(zero) # 330 <_start-0x7ffffcd0> - d464: 9100 0x9100 - d466: 7fb4 flw fa3,120(a5) - d468: 4006 0x4006 - d46a: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d46e: 7fb4 flw fa3,120(a5) - d470: 9106 add sp,sp,ra - d472: 0644 addi s1,sp,772 - d474: 4022 0x4022 - d476: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d47a: 5491 li s1,-28 - d47c: 4006 0x4006 - d47e: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d482: 7fb0 flw fa2,120(a5) - d484: 4006 0x4006 - d486: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d48a: 0650 addi a2,sp,772 - d48c: 4b40 lw s0,20(a4) - d48e: 2224 fld fs1,64(a2) - d490: 244b402b 0x244b402b - d494: 2d22 fld fs10,8(sp) - d496: 9f21 0x9f21 - ... - d4a0: 03a4 addi s1,sp,456 - d4a2: 0000 unimp - d4a4: 03ac addi a1,sp,456 - d4a6: 0000 unimp - d4a8: 0011 c.nop 4 - d4aa: 007e c.slli zero,0x1f - d4ac: 4b40 lw s0,20(a4) - d4ae: 2224 fld fs1,64(a2) - d4b0: 4b40007b 0x4b40007b - d4b4: 2224 fld fs1,64(a2) - d4b6: 1aff082b 0x1aff082b - d4ba: ac9f 0003 c000 0xc0000003ac9f - d4c0: 13000003 lb zero,304(zero) # 130 <_start-0x7ffffed0> - d4c4: 9100 0x9100 - d4c6: 7fb8 flw fa4,120(a5) - d4c8: 4006 0x4006 - d4ca: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - d4ce: 4000 lw s0,0(s0) - d4d0: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d4d4: ff08 fsw fa0,56(a4) - d4d6: 9f1a add t5,t5,t1 - ... - d4e0: 0620 addi s0,sp,776 - d4e2: 0000 unimp - d4e4: 0628 addi a0,sp,776 - d4e6: 0000 unimp - d4e8: 0001 nop - d4ea: 285f 0006 6400 0x64000006285f - d4f0: 0006 c.slli zero,0x1 - d4f2: 1000 addi s0,sp,32 - d4f4: 9100 0x9100 - d4f6: 0640 addi s0,sp,772 - d4f8: 4b40 lw s0,20(a4) - d4fa: 2224 fld fs1,64(a2) - d4fc: 5091 li ra,-28 - d4fe: 4006 0x4006 - d500: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d504: 009f 0000 0000 0x9f - d50a: 0000 unimp - d50c: 2000 fld fs0,0(s0) - d50e: 0006 c.slli zero,0x1 - d510: 3400 fld fs0,40(s0) - d512: 0006 c.slli zero,0x1 - d514: 1100 addi s0,sp,160 - d516: 7d00 flw fs0,56(a0) - d518: 4000 lw s0,0(s0) - d51a: 7c22244b 0x7c22244b - d51e: 4000 lw s0,0(s0) - d520: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d524: ff08 fsw fa0,56(a4) - d526: 9f1a add t5,t5,t1 - d528: 0634 addi a3,sp,776 - d52a: 0000 unimp - d52c: 0638 addi a4,sp,776 - d52e: 0000 unimp - d530: 0012 c.slli zero,0x4 - d532: 4491 li s1,4 - d534: 4006 0x4006 - d536: 7c22244b 0x7c22244b - d53a: 4000 lw s0,0(s0) - d53c: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d540: ff08 fsw fa0,56(a4) - d542: 9f1a add t5,t5,t1 - d544: 0638 addi a4,sp,776 - d546: 0000 unimp - d548: 0644 addi s1,sp,772 - d54a: 0000 unimp - d54c: 0001 nop - d54e: 445f 0006 6400 0x64000006445f - d554: 0006 c.slli zero,0x1 - d556: 2e00 fld fs0,24(a2) - d558: 8100 0x8100 - d55a: 9100 0x9100 - d55c: 0644 addi s1,sp,772 - d55e: 4022 0x4022 - d560: 8122244b fnmsub.s fs0,ft4,fs2,fa6,rdn - d564: 4000 lw s0,0(s0) - d566: 2d22244b 0x2d22244b - d56a: 5491 li s1,-28 - d56c: 4006 0x4006 - d56e: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d572: 0640 addi s0,sp,772 - d574: 4b40 lw s0,20(a4) - d576: 2224 fld fs1,64(a2) - d578: 5091 li ra,-28 - d57a: 4006 0x4006 - d57c: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d580: 4b40 lw s0,20(a4) - d582: 2224 fld fs1,64(a2) - d584: 212d jal d9ae <_start-0x7fff2652> - d586: 009f 0000 0000 0x9f - d58c: 0000 unimp - d58e: 3c00 fld fs0,56(s0) - d590: 0006 c.slli zero,0x1 - d592: 4800 lw s0,16(s0) - d594: 0006 c.slli zero,0x1 - d596: 1100 addi s0,sp,160 - d598: 7e00 flw fs0,56(a2) - d59a: 4000 lw s0,0(s0) - d59c: 7d22244b 0x7d22244b - d5a0: 4000 lw s0,0(s0) - d5a2: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d5a6: ff08 fsw fa0,56(a4) - d5a8: 9f1a add t5,t5,t1 - d5aa: 0648 addi a0,sp,772 - d5ac: 0000 unimp - d5ae: 0654 addi a3,sp,772 - d5b0: 0000 unimp - d5b2: 0012 c.slli zero,0x4 - d5b4: 4891 li a7,4 - d5b6: 4006 0x4006 - d5b8: 7d22244b 0x7d22244b - d5bc: 4000 lw s0,0(s0) - d5be: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d5c2: ff08 fsw fa0,56(a4) - d5c4: 9f1a add t5,t5,t1 - ... - d5ce: 07e0 addi s0,sp,972 - d5d0: 0000 unimp - d5d2: 07e8 addi a0,sp,972 - d5d4: 0000 unimp - d5d6: 0008 0x8 - d5d8: 007d c.nop 31 - d5da: 2e30 fld fa2,88(a2) - d5dc: ff08 fsw fa0,56(a4) - d5de: 9f1a add t5,t5,t1 - ... - d5e8: 06ec addi a1,sp,844 - d5ea: 0000 unimp - d5ec: 0710 addi a2,sp,896 - d5ee: 0000 unimp - d5f0: 0006 c.slli zero,0x1 - d5f2: 2008 fld fa0,0(s0) - d5f4: 007f 0x7f - d5f6: 9f1c 0x9f1c - d5f8: 0730 addi a2,sp,904 - d5fa: 0000 unimp - d5fc: 0794 addi a3,sp,960 - d5fe: 0000 unimp - d600: 0006 c.slli zero,0x1 - d602: 2008 fld fa0,0(s0) - d604: 007f 0x7f - d606: 9f1c 0x9f1c - d608: 07a4 addi s1,sp,968 - d60a: 0000 unimp - d60c: 07cc addi a1,sp,964 - d60e: 0000 unimp - d610: 0006 c.slli zero,0x1 - d612: 2008 fld fa0,0(s0) - d614: 007f 0x7f - d616: 9f1c 0x9f1c - ... - d620: 06ec addi a1,sp,844 - d622: 0000 unimp - d624: 0710 addi a2,sp,896 - d626: 0000 unimp - d628: 0001 nop - d62a: 305f 0007 9400 0x94000007305f - d630: 01000007 vlbuff.v v0,(zero),v0.t - d634: 5f00 lw s0,56(a4) - d636: 07a4 addi s1,sp,968 - d638: 0000 unimp - d63a: 07cc addi a1,sp,964 - d63c: 0000 unimp - d63e: 0001 nop - d640: 005f 0000 0000 0x5f - d646: 0000 unimp - d648: e400 fsw fs0,8(s0) - d64a: 0006 c.slli zero,0x1 - d64c: 1000 addi s0,sp,32 - d64e: 01000007 vlbuff.v v0,(zero),v0.t - d652: 5a00 lw s0,48(a2) - d654: 0730 addi a2,sp,904 - d656: 0000 unimp - d658: 07cc addi a1,sp,964 - d65a: 0000 unimp - d65c: 0001 nop - d65e: 005a c.slli zero,0x16 - d660: 0000 unimp - d662: 0000 unimp - d664: 0000 unimp - d666: ec00 fsw fs0,24(s0) - d668: 0006 c.slli zero,0x1 - d66a: f000 fsw fs0,32(s0) - d66c: 0006 c.slli zero,0x1 - d66e: 0200 addi s0,sp,256 - d670: 3000 fld fs0,32(s0) - d672: f09f 0006 0400 0x4000006f09f - d678: 01000007 vlbuff.v v0,(zero),v0.t - d67c: 5e00 lw s0,56(a2) - d67e: 0710 addi a2,sp,896 - d680: 0000 unimp - d682: 0728 addi a0,sp,904 - d684: 0000 unimp - d686: 0001 nop - d688: 305f 0007 4000 0x40000007305f - d68e: 01000007 vlbuff.v v0,(zero),v0.t - d692: 5e00 lw s0,56(a2) - d694: 0740 addi s0,sp,900 - d696: 0000 unimp - d698: 0744 addi s1,sp,900 - d69a: 0000 unimp - d69c: 7f7e0003 lb zero,2039(t3) - d6a0: 449f 0007 4800 0x48000007449f - d6a6: 01000007 vlbuff.v v0,(zero),v0.t - d6aa: 5e00 lw s0,56(a2) - d6ac: 0768 addi a0,sp,908 - d6ae: 0000 unimp - d6b0: 0778 addi a4,sp,908 - d6b2: 0000 unimp - d6b4: 0002 c.slli64 zero - d6b6: 9f30 0x9f30 - d6b8: 0778 addi a4,sp,908 - d6ba: 0000 unimp - d6bc: 0780 addi s0,sp,960 - d6be: 0000 unimp - d6c0: 0001 nop - d6c2: 8061 srli s0,s0,0x18 - d6c4: 88000007 vlsseg5bu.v v0,(zero),zero,v0.t - d6c8: 03000007 vlbuff.v v0,(zero) - d6cc: 7e00 flw fs0,56(a2) - d6ce: 9f01 0x9f01 - d6d0: 0788 addi a0,sp,960 - d6d2: 0000 unimp - d6d4: 07a4 addi s1,sp,968 - d6d6: 0000 unimp - d6d8: 0005 c.nop 1 - d6da: 7a34 flw fa3,112(a2) - d6dc: 1c00 addi s0,sp,560 - d6de: a49f 0007 c400 0xc4000007a49f - d6e4: 01000007 vlbuff.v v0,(zero),v0.t - d6e8: 6100 flw fs0,0(a0) - d6ea: 07c4 addi s1,sp,964 - d6ec: 0000 unimp - d6ee: 07c8 addi a0,sp,964 - d6f0: 0000 unimp - d6f2: 01810003 lb zero,24(sp) - d6f6: c89f 0007 cc00 0xcc000007c89f - d6fc: 01000007 vlbuff.v v0,(zero),v0.t - d700: 6100 flw fs0,0(a0) - d702: 07cc addi a1,sp,964 - d704: 0000 unimp - d706: 07e4 addi s1,sp,972 - d708: 0000 unimp - d70a: 0001 nop - d70c: 005f 0000 0000 0x5f - d712: 0000 unimp - d714: ec00 fsw fs0,24(s0) - d716: 0006 c.slli zero,0x1 - d718: f000 fsw fs0,32(s0) - d71a: 0006 c.slli zero,0x1 - d71c: 0200 addi s0,sp,256 - d71e: 3000 fld fs0,32(s0) - d720: f09f 0006 e800 0xe8000006f09f - d726: 01000007 vlbuff.v v0,(zero),v0.t - d72a: 5d00 lw s0,56(a0) - ... - d734: 080c addi a1,sp,16 - d736: 0000 unimp - d738: 0834 addi a3,sp,24 - d73a: 0000 unimp - d73c: 0001 nop - d73e: 345d jal d1e4 <_start-0x7fff2e1c> - d740: 0008 0x8 - d742: 6000 flw fs0,0(s0) - d744: 0008 0x8 - d746: 1000 addi s0,sp,32 - d748: 9100 0x9100 - d74a: 0640 addi s0,sp,772 - d74c: 4b40 lw s0,20(a4) - d74e: 2224 fld fs1,64(a2) - d750: 5091 li ra,-28 - d752: 4006 0x4006 - d754: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d758: 009f 0000 0000 0x9f - d75e: 0000 unimp - d760: 1c00 addi s0,sp,560 - d762: 0008 0x8 - d764: 2400 fld fs0,8(s0) - d766: 0008 0x8 - d768: 1100 addi s0,sp,160 - d76a: 7e00 flw fs0,56(a2) - d76c: 4000 lw s0,0(s0) - d76e: 7f22244b fnmsub.q fs0,ft4,fs2,fa5,rdn - d772: 4000 lw s0,0(s0) - d774: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d778: ff08 fsw fa0,56(a4) - d77a: 9f1a add t5,t5,t1 - d77c: 0824 addi s1,sp,24 - d77e: 0000 unimp - d780: 0828 addi a0,sp,24 - d782: 0000 unimp - d784: 0012 c.slli zero,0x4 - d786: 4491 li s1,4 - d788: 4006 0x4006 - d78a: 7f22244b fnmsub.q fs0,ft4,fs2,fa5,rdn - d78e: 4000 lw s0,0(s0) - d790: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d794: ff08 fsw fa0,56(a4) - d796: 9f1a add t5,t5,t1 - d798: 0828 addi a0,sp,24 - d79a: 0000 unimp - d79c: 0838 addi a4,sp,24 - d79e: 0000 unimp - d7a0: 0018 0x18 - d7a2: 4491 li s1,4 - d7a4: 4006 0x4006 - d7a6: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d7aa: 0644 addi s1,sp,772 - d7ac: b491 j d1f0 <_start-0x7fff2e10> - d7ae: 067f 0x67f - d7b0: 4022 0x4022 - d7b2: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d7b6: ff08 fsw fa0,56(a4) - d7b8: 9f1a add t5,t5,t1 - d7ba: 0838 addi a4,sp,24 - d7bc: 0000 unimp - d7be: 0848 addi a0,sp,20 - d7c0: 0000 unimp - d7c2: 0001 nop - d7c4: 485f 0008 6000 0x60000008485f - d7ca: 0008 0x8 - d7cc: 3100 fld fs0,32(a0) - d7ce: 9100 0x9100 - d7d0: 0644 addi s1,sp,772 - d7d2: 4b40 lw s0,20(a4) - d7d4: 2224 fld fs1,64(a2) - d7d6: 4491 li s1,4 - d7d8: 9106 add sp,sp,ra - d7da: 7fb4 flw fa3,120(a5) - d7dc: 2206 fld ft4,64(sp) - d7de: 4b40 lw s0,20(a4) - d7e0: 2224 fld fs1,64(a2) - d7e2: 0654912b 0x654912b - d7e6: 4b40 lw s0,20(a4) - d7e8: 2224 fld fs1,64(a2) - d7ea: 4091 li ra,4 - d7ec: 4006 0x4006 - d7ee: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d7f2: 0650 addi a2,sp,772 - d7f4: 4b40 lw s0,20(a4) - d7f6: 2224 fld fs1,64(a2) - d7f8: 244b402b 0x244b402b - d7fc: 2d22 fld fs10,8(sp) - d7fe: 9f21 0x9f21 - ... - d808: 083c addi a5,sp,24 - d80a: 0000 unimp - d80c: 0844 addi s1,sp,20 - d80e: 0000 unimp - d810: 0011 c.nop 4 - d812: 007e c.slli zero,0x1f - d814: 4b40 lw s0,20(a4) - d816: 2224 fld fs1,64(a2) - d818: 007a c.slli zero,0x1e - d81a: 4b40 lw s0,20(a4) - d81c: 2224 fld fs1,64(a2) - d81e: 1aff082b 0x1aff082b - d822: 449f 0008 5800 0x58000008449f - d828: 0008 0x8 - d82a: 1200 addi s0,sp,288 - d82c: 9100 0x9100 - d82e: 0648 addi a0,sp,772 - d830: 4b40 lw s0,20(a4) - d832: 2224 fld fs1,64(a2) - d834: 007a c.slli zero,0x1e - d836: 4b40 lw s0,20(a4) - d838: 2224 fld fs1,64(a2) - d83a: 1aff082b 0x1aff082b - d83e: 009f 0000 0000 0x9f - d844: 0000 unimp - d846: f000 fsw fs0,32(s0) - d848: 0008 0x8 - d84a: f800 fsw fs0,48(s0) - d84c: 0008 0x8 - d84e: 0100 addi s0,sp,128 - d850: 5e00 lw s0,56(a2) - d852: 08f8 addi a4,sp,92 - d854: 0000 unimp - d856: 094c addi a1,sp,148 - d858: 0000 unimp - d85a: 0011 c.nop 4 - d85c: b091 j d0a0 <_start-0x7fff2f60> - d85e: 067f 0x67f - d860: 4b40 lw s0,20(a4) - d862: 2224 fld fs1,64(a2) - d864: 0080 addi s0,sp,64 - d866: 4006 0x4006 - d868: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d86c: 009f 0000 0000 0x9f - d872: 0000 unimp - d874: f000 fsw fs0,32(s0) - d876: 0008 0x8 - d878: fc00 fsw fs0,56(s0) - d87a: 0008 0x8 - d87c: 1100 addi s0,sp,160 - d87e: 7d00 flw fs0,56(a0) - d880: 4000 lw s0,0(s0) - d882: 7622244b fnmsub.q fs0,ft4,ft2,fa4,rdn - d886: 4000 lw s0,0(s0) - d888: 2d22244b 0x2d22244b - d88c: ff08 fsw fa0,56(a4) - d88e: 9f1a add t5,t5,t1 - d890: 08fc addi a5,sp,92 - d892: 0000 unimp - d894: 0908 addi a0,sp,144 - d896: 0000 unimp - d898: 0016 c.slli zero,0x5 - d89a: 4491 li s1,4 - d89c: 7606 flw fa2,96(sp) - d89e: 2200 fld fs0,0(a2) - d8a0: 4b40 lw s0,20(a4) - d8a2: 2224 fld fs1,64(a2) - d8a4: 4491 li s1,4 - d8a6: 4006 0x4006 - d8a8: 2d22244b 0x2d22244b - d8ac: ff08 fsw fa0,56(a4) - d8ae: 9f1a add t5,t5,t1 - d8b0: 0908 addi a0,sp,144 - d8b2: 0000 unimp - d8b4: 0914 addi a3,sp,144 - d8b6: 0000 unimp - d8b8: 0001 nop - d8ba: 145e slli s0,s0,0x37 - d8bc: 0009 c.nop 2 - d8be: 4c00 lw s0,24(s0) - d8c0: 0009 c.nop 2 - d8c2: 2000 fld fs0,0(s0) - d8c4: 9100 0x9100 - d8c6: 0654 addi a3,sp,772 - d8c8: 4b40 lw s0,20(a4) - d8ca: 2224 fld fs1,64(a2) - d8cc: b091 j d110 <_start-0x7fff2ef0> - d8ce: 067f 0x67f - d8d0: 4b40 lw s0,20(a4) - d8d2: 2224 fld fs1,64(a2) - d8d4: 0080 addi s0,sp,64 - d8d6: 4006 0x4006 - d8d8: 2b22244b fnmsub.d fs0,ft4,fs2,ft5,rdn - d8dc: 4b40 lw s0,20(a4) - d8de: 2224 fld fs1,64(a2) - d8e0: 7d2d lui s10,0xfffeb - d8e2: 2100 fld fs0,0(a0) - d8e4: 009f 0000 0000 0x9f - d8ea: 0000 unimp - d8ec: 0800 addi s0,sp,16 - d8ee: 0009 c.nop 2 - d8f0: 2400 fld fs0,8(s0) - d8f2: 0009 c.nop 2 - d8f4: 1100 addi s0,sp,160 - d8f6: 7b00 flw fs0,48(a4) - d8f8: 4000 lw s0,0(s0) - d8fa: 8122244b fnmsub.s fs0,ft4,fs2,fa6,rdn - d8fe: 4000 lw s0,0(s0) - d900: 2d22244b 0x2d22244b - d904: ff08 fsw fa0,56(a4) - d906: 9f1a add t5,t5,t1 - ... - d910: 099c addi a5,sp,208 - d912: 0000 unimp - d914: 09c0 addi s0,sp,212 - d916: 0000 unimp - d918: 0002 c.slli64 zero - d91a: 00009f33 sll t5,ra,zero - d91e: 0000 unimp - d920: 0000 unimp - d922: 0000 unimp - d924: 099c addi a5,sp,208 - d926: 0000 unimp - d928: 09c0 addi s0,sp,212 - d92a: 0000 unimp - d92c: 0002 c.slli64 zero - d92e: 9f4d 0x9f4d - ... - d938: 099c addi a5,sp,208 - d93a: 0000 unimp - d93c: 09c0 addi s0,sp,212 - d93e: 0000 unimp - d940: 0002 c.slli64 zero - d942: 9f30 0x9f30 - ... - d94c: 099c addi a5,sp,208 - d94e: 0000 unimp - d950: 09a0 addi s0,sp,216 - d952: 0000 unimp - d954: 0002 c.slli64 zero - d956: 00009f33 sll t5,ra,zero - d95a: 0000 unimp - d95c: 0000 unimp - d95e: 0000 unimp - d960: 09ec addi a1,sp,220 - d962: 0000 unimp - d964: 09f4 addi a3,sp,220 - d966: 0000 unimp - d968: 0001 nop - d96a: f45e fsw fs7,40(sp) - d96c: 0009 c.nop 2 - d96e: 2800 fld fs0,16(s0) - d970: 000a c.slli zero,0x2 - d972: 1100 addi s0,sp,160 - d974: 9100 0x9100 - d976: 7fb0 flw fa2,120(a5) - d978: 4006 0x4006 - d97a: 8022244b fnmsub.s fs0,ft4,ft2,fa6,rdn - d97e: 0600 addi s0,sp,768 - d980: 4b40 lw s0,20(a4) - d982: 2224 fld fs1,64(a2) - d984: 0a289f2b 0xa289f2b - d988: 0000 unimp - d98a: 0a7c addi a5,sp,284 - d98c: 0000 unimp - d98e: 0016 c.slli zero,0x5 - d990: b091 j d1d4 <_start-0x7fff2e2c> - d992: 067f 0x67f - d994: 4b40 lw s0,20(a4) - d996: 2224 fld fs1,64(a2) - d998: b091 j d1dc <_start-0x7fff2e24> - d99a: 067f 0x67f - d99c: 4091 li ra,4 - d99e: 2206 fld ft4,64(sp) - d9a0: 4b40 lw s0,20(a4) - d9a2: 2224 fld fs1,64(a2) - d9a4: 00009f2b 0x9f2b - d9a8: 0000 unimp - d9aa: 0000 unimp - d9ac: 0000 unimp - d9ae: 09ec addi a1,sp,220 - d9b0: 0000 unimp - d9b2: 09f8 addi a4,sp,220 - d9b4: 0000 unimp - d9b6: 0011 c.nop 4 - d9b8: 007d c.nop 31 - d9ba: 4b40 lw s0,20(a4) - d9bc: 2224 fld fs1,64(a2) - d9be: 0076 c.slli zero,0x1d - d9c0: 4b40 lw s0,20(a4) - d9c2: 2224 fld fs1,64(a2) - d9c4: 082d addi a6,a6,11 - d9c6: 1aff 0x1aff - d9c8: f89f 0009 1c00 0x1c000009f89f - d9ce: 000a c.slli zero,0x2 - d9d0: 1600 addi s0,sp,800 - d9d2: 9100 0x9100 - d9d4: 0644 addi s1,sp,772 - d9d6: 0076 c.slli zero,0x1d - d9d8: 4022 0x4022 - d9da: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - d9de: 0644 addi s1,sp,772 - d9e0: 4b40 lw s0,20(a4) - d9e2: 2224 fld fs1,64(a2) - d9e4: 082d addi a6,a6,11 - d9e6: 1aff 0x1aff - d9e8: 009f 0000 0000 0x9f - d9ee: 0000 unimp - d9f0: 4800 lw s0,16(s0) - d9f2: 000a c.slli zero,0x2 - d9f4: 7c00 flw fs0,56(s0) - d9f6: 000a c.slli zero,0x2 - d9f8: 0200 addi s0,sp,256 - d9fa: 3000 fld fs0,32(s0) - d9fc: 009f 0000 0000 0x9f - da02: 0000 unimp - da04: 2400 fld fs0,8(s0) - da06: 000a c.slli zero,0x2 - da08: 7c00 flw fs0,56(s0) - da0a: 000a c.slli zero,0x2 - da0c: 0200 addi s0,sp,256 - da0e: 4f00 lw s0,24(a4) - da10: 009f 0000 0000 0x9f - da16: 0000 unimp - da18: 2400 fld fs0,8(s0) - da1a: 000a c.slli zero,0x2 - da1c: 7c00 flw fs0,56(s0) - da1e: 000a c.slli zero,0x2 - da20: 0200 addi s0,sp,256 - da22: 3100 fld fs0,32(a0) - da24: 009f 0000 0000 0x9f - da2a: 0000 unimp - da2c: 2400 fld fs0,8(s0) - da2e: 000a c.slli zero,0x2 - da30: 7c00 flw fs0,56(s0) - da32: 000a c.slli zero,0x2 - da34: 0200 addi s0,sp,256 - da36: 3000 fld fs0,32(s0) - da38: 009f 0000 0000 0x9f - da3e: 0000 unimp - da40: 2400 fld fs0,8(s0) - da42: 000a c.slli zero,0x2 - da44: 2800 fld fs0,16(s0) - da46: 000a c.slli zero,0x2 - da48: 0200 addi s0,sp,256 - da4a: 3000 fld fs0,32(s0) - da4c: 489f 000a 7c00 0x7c00000a489f - da52: 000a c.slli zero,0x2 - da54: 0200 addi s0,sp,256 - da56: 3400 fld fs0,40(s0) - da58: 009f 0000 0000 0x9f - da5e: 0000 unimp - da60: 2000 fld fs0,0(s0) - da62: 0004 0x4 - da64: 2800 fld fs0,16(s0) - da66: 0004 0x4 - da68: 0800 addi s0,sp,16 - da6a: 7e00 flw fs0,56(a2) - da6c: 3000 fld fs0,32(s0) - da6e: 082e slli a6,a6,0xb - da70: 1aff 0x1aff - da72: 009f 0000 0000 0x9f - da78: 0000 unimp - da7a: e800 fsw fs0,16(s0) - da7c: 50000003 lb zero,1280(zero) # 500 <_start-0x7ffffb00> - da80: 0004 0x4 - da82: 0200 addi s0,sp,256 - da84: 4f00 lw s0,24(a4) - da86: 009f 0000 0000 0x9f - da8c: 0000 unimp - da8e: e800 fsw fs0,16(s0) - da90: 50000003 lb zero,1280(zero) # 500 <_start-0x7ffffb00> - da94: 0004 0x4 - da96: 0200 addi s0,sp,256 - da98: 3100 fld fs0,32(a0) - da9a: 009f 0000 0000 0x9f - daa0: 0000 unimp - daa2: e800 fsw fs0,16(s0) - daa4: 50000003 lb zero,1280(zero) # 500 <_start-0x7ffffb00> - daa8: 0004 0x4 - daaa: 0200 addi s0,sp,256 - daac: 3000 fld fs0,32(s0) - daae: 009f 0000 0000 0x9f - dab4: 0000 unimp - dab6: e800 fsw fs0,16(s0) - dab8: f4000003 lb zero,-192(zero) # ffffff40 <__BSS_END__+0x7ffe91c8> - dabc: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - dac0: 3000 fld fs0,32(s0) - dac2: 149f 0004 5000 0x50000004149f - dac8: 0004 0x4 - daca: 0200 addi s0,sp,256 - dacc: 3400 fld fs0,40(s0) - dace: 009f 0000 0000 0x9f - dad4: 0000 unimp - dad6: e800 fsw fs0,16(s0) - dad8: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe9188> - dadc: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> - dae0: 3000 fld fs0,32(s0) - dae2: f09f 0003 2800 0x28000003f09f - dae8: 0004 0x4 - daea: 0100 addi s0,sp,128 - daec: 5e00 lw s0,56(a2) - ... - daf6: 0a7c addi a5,sp,284 - daf8: 0000 unimp - dafa: 0a8c addi a1,sp,336 - dafc: 0000 unimp - dafe: 0006 c.slli zero,0x1 - db00: 0078 addi a4,sp,12 - db02: 007c addi a5,sp,12 - db04: 9f1c 0x9f1c - db06: 0a8c addi a1,sp,336 - db08: 0000 unimp - db0a: 0aa4 addi s1,sp,344 - db0c: 0000 unimp - db0e: 0078000b 0x78000b - db12: 5c91 li s9,-28 - db14: 3106 fld ft2,96(sp) - db16: 4124 lw s1,64(a0) - db18: 1c25 addi s8,s8,-23 - db1a: a49f 000a fc00 0xfc00000aa49f - db20: 000a c.slli zero,0x2 - db22: 0100 addi s0,sp,128 - db24: 5d00 lw s0,56(a0) - db26: 0afc addi a5,sp,348 - db28: 0000 unimp - db2a: 0b10 addi a2,sp,400 - db2c: 0000 unimp - db2e: 000c 0xc - db30: 5c91 li s9,-28 - db32: 3106 fld ft2,96(sp) - db34: 4124 lw s1,64(a0) - db36: 2025 jal db5e <_start-0x7fff24a2> - db38: 0078 addi a4,sp,12 - db3a: 9f22 add t5,t5,s0 - db3c: 0b18 addi a4,sp,400 - db3e: 0000 unimp - db40: 0b2c addi a1,sp,408 - db42: 0000 unimp - db44: 0001 nop - db46: 445d li s0,23 - db48: 6c00000b 0x6c00000b - db4c: 0600000b 0x600000b - db50: 7800 flw fs0,48(s0) - db52: 7c00 flw fs0,56(s0) - db54: 1c00 addi s0,sp,560 - db56: 009f 000d 0800 0x800000d009f - db5c: 000d c.nop 3 - db5e: 0600 addi s0,sp,768 - db60: 7800 flw fs0,48(s0) - db62: 7c00 flw fs0,56(s0) - db64: 1c00 addi s0,sp,560 - db66: 089f 000d 2800 0x2800000d089f - db6c: 000d c.nop 3 - db6e: 0100 addi s0,sp,128 - db70: 5d00 lw s0,56(a0) - db72: 0d50 addi a2,sp,660 - db74: 0000 unimp - db76: 0d54 addi a3,sp,660 - db78: 0000 unimp - db7a: 0001 nop - db7c: 545d li s0,-9 - db7e: 000d c.nop 3 - db80: ac00 fsd fs0,24(s0) - db82: 000d c.nop 3 - db84: 0100 addi s0,sp,128 - db86: 5a00 lw s0,48(a2) - db88: 0dac addi a1,sp,728 - db8a: 0000 unimp - db8c: 0dc4 addi s1,sp,724 - db8e: 0000 unimp - db90: 000c 0xc - db92: 5c91 li s9,-28 - db94: 3106 fld ft2,96(sp) - db96: 4124 lw s1,64(a0) - db98: 7825 lui a6,0xfffe9 - db9a: 2000 fld fs0,0(s0) - db9c: 9f22 add t5,t5,s0 - db9e: 0dc8 addi a0,sp,724 - dba0: 0000 unimp - dba2: 0ddc addi a5,sp,724 - dba4: 0000 unimp - dba6: 0001 nop - dba8: f45a fsw fs6,40(sp) - dbaa: 000d c.nop 3 - dbac: 5000 lw s0,32(s0) - dbae: 000e c.slli zero,0x3 - dbb0: 0100 addi s0,sp,128 - dbb2: 5d00 lw s0,56(a0) - dbb4: 0e90 addi a2,sp,848 - dbb6: 0000 unimp - dbb8: 0e98 addi a4,sp,848 - dbba: 0000 unimp - dbbc: 0001 nop - dbbe: dc5a sw s6,56(sp) - dbc0: f000000f 0xf000000f - dbc4: 0600000f fence or,unknown - dbc8: 7800 flw fs0,48(s0) - dbca: 7c00 flw fs0,56(s0) - dbcc: 1c00 addi s0,sp,560 - dbce: f09f 000f 3800 0x3800000ff09f - dbd4: 0010 0x10 - dbd6: 0b00 addi s0,sp,400 - dbd8: 7800 flw fs0,48(s0) - dbda: 9100 0x9100 - dbdc: 065c addi a5,sp,772 - dbde: 2431 jal ddea <_start-0x7fff2216> - dbe0: 2541 jal e260 <_start-0x7fff1da0> - dbe2: 9f1c 0x9f1c - dbe4: 104c addi a1,sp,36 - dbe6: 0000 unimp - dbe8: 1060 addi s0,sp,44 - dbea: 0000 unimp - dbec: 0078000b 0x78000b - dbf0: 5c91 li s9,-28 - dbf2: 3106 fld ft2,96(sp) - dbf4: 4124 lw s1,64(a0) - dbf6: 1c25 addi s8,s8,-23 - dbf8: 649f 0010 c000 0xc0000010649f - dbfe: 0010 0x10 - dc00: 0b00 addi s0,sp,400 - dc02: 7800 flw fs0,48(s0) - dc04: 9100 0x9100 - dc06: 065c addi a5,sp,772 - dc08: 2431 jal de14 <_start-0x7fff21ec> - dc0a: 2541 jal e28a <_start-0x7fff1d76> - dc0c: 9f1c 0x9f1c - dc0e: 1134 addi a3,sp,168 - dc10: 0000 unimp - dc12: 1144 addi s1,sp,164 - dc14: 0000 unimp - dc16: 0078000b 0x78000b - dc1a: 5c91 li s9,-28 - dc1c: 3106 fld ft2,96(sp) - dc1e: 4124 lw s1,64(a0) - dc20: 1c25 addi s8,s8,-23 - dc22: 789f 0011 8800 0x88000011789f - dc28: 0011 c.nop 4 - dc2a: 0b00 addi s0,sp,400 - dc2c: 7800 flw fs0,48(s0) - dc2e: 9100 0x9100 - dc30: 065c addi a5,sp,772 - dc32: 2431 jal de3e <_start-0x7fff21c2> - dc34: 2541 jal e2b4 <_start-0x7fff1d4c> - dc36: 9f1c 0x9f1c - dc38: 1194 addi a3,sp,224 - dc3a: 0000 unimp - dc3c: 11a8 addi a0,sp,232 - dc3e: 0000 unimp - dc40: 0078000b 0x78000b - dc44: 5c91 li s9,-28 - dc46: 3106 fld ft2,96(sp) - dc48: 4124 lw s1,64(a0) - dc4a: 1c25 addi s8,s8,-23 - dc4c: ac9f 0011 b000 0xb0000011ac9f - dc52: 0011 c.nop 4 - dc54: 0b00 addi s0,sp,400 - dc56: 7800 flw fs0,48(s0) - dc58: 9100 0x9100 - dc5a: 065c addi a5,sp,772 - dc5c: 2431 jal de68 <_start-0x7fff2198> - dc5e: 2541 jal e2de <_start-0x7fff1d22> - dc60: 9f1c 0x9f1c - dc62: 11e4 addi s1,sp,236 - dc64: 0000 unimp - dc66: 1240 addi s0,sp,292 - dc68: 0000 unimp - dc6a: 0078000b 0x78000b - dc6e: 5c91 li s9,-28 - dc70: 3106 fld ft2,96(sp) - dc72: 4124 lw s1,64(a0) - dc74: 1c25 addi s8,s8,-23 - dc76: 009f 0000 0000 0x9f - dc7c: 0000 unimp - dc7e: c400 sw s0,8(s0) - dc80: 000a c.slli zero,0x2 - dc82: e800 fsw fs0,16(s0) - dc84: 000a c.slli zero,0x2 - dc86: 1100 addi s0,sp,160 - dc88: 7e00 flw fs0,56(a2) - dc8a: 4000 lw s0,0(s0) - dc8c: 7f22244b fnmsub.q fs0,ft4,fs2,fa5,rdn - dc90: 4000 lw s0,0(s0) - dc92: 2d22244b 0x2d22244b - dc96: ff08 fsw fa0,56(a4) - dc98: 9f1a add t5,t5,t1 - dc9a: 0ae8 addi a0,sp,348 - dc9c: 0000 unimp - dc9e: 0b00 addi s0,sp,400 - dca0: 0000 unimp - dca2: 0012 c.slli zero,0x4 - dca4: 007e c.slli zero,0x1f - dca6: 4b40 lw s0,20(a4) - dca8: 2224 fld fs1,64(a2) - dcaa: 5091 li ra,-28 - dcac: 4006 0x4006 - dcae: 2d22244b 0x2d22244b - dcb2: ff08 fsw fa0,56(a4) - dcb4: 9f1a add t5,t5,t1 - dcb6: 0b00 addi s0,sp,400 - dcb8: 0000 unimp - dcba: 0b10 addi a2,sp,400 - dcbc: 0000 unimp - dcbe: 0014 0x14 - dcc0: b091 j d504 <_start-0x7fff2afc> - dcc2: 067f 0x67f - dcc4: 4b40 lw s0,20(a4) - dcc6: 2224 fld fs1,64(a2) - dcc8: 5091 li ra,-28 - dcca: 4006 0x4006 - dccc: 2d22244b 0x2d22244b - dcd0: ff08 fsw fa0,56(a4) - dcd2: 9f1a add t5,t5,t1 - ... - dcdc: 0ac4 addi s1,sp,340 - dcde: 0000 unimp - dce0: 0ae0 addi s0,sp,348 - dce2: 0000 unimp - dce4: 0001 nop - dce6: e056 fsw fs5,0(sp) - dce8: 000a c.slli zero,0x2 - dcea: f400 fsw fs0,40(s0) - dcec: 000a c.slli zero,0x2 - dcee: 0100 addi s0,sp,128 - dcf0: 5b00 lw s0,48(a4) - dcf2: 0af4 addi a3,sp,348 - dcf4: 0000 unimp - dcf6: 0afc addi a5,sp,348 - dcf8: 0000 unimp - dcfa: 0002 c.slli64 zero - dcfc: 9f31 0x9f31 - ... - dd06: 0ae8 addi a0,sp,348 - dd08: 0000 unimp - dd0a: 0afc addi a5,sp,348 - dd0c: 0000 unimp - dd0e: 0001 nop - dd10: fc5f 000a 0400 0x400000afc5f - dd16: 0600000b 0x600000b - dd1a: 7d00 flw fs0,56(a0) - dd1c: 7f00 flw fs0,56(a4) - dd1e: 2100 fld fs0,0(a0) - dd20: 049f 000b 0c00 0xc00000b049f - dd26: 0100000b 0x100000b - dd2a: 5f00 lw s0,56(a4) - dd2c: 0b0c addi a1,sp,400 - dd2e: 0000 unimp - dd30: 0b10 addi a2,sp,400 - dd32: 0000 unimp - dd34: 0015 c.nop 5 - dd36: 0080 addi s0,sp,64 - dd38: 4b40 lw s0,20(a4) - dd3a: 2224 fld fs1,64(a2) - dd3c: 0080 addi s0,sp,64 - dd3e: 4891 li a7,4 - dd40: 1c06 slli s8,s8,0x21 - dd42: 4b40 lw s0,20(a4) - dd44: 2224 fld fs1,64(a2) - dd46: 7d2d lui s10,0xfffeb - dd48: 2100 fld fs0,0(a0) - dd4a: 009f 0000 0000 0x9f - dd50: 0000 unimp - dd52: 5800 lw s0,48(s0) - dd54: 000c 0xc - dd56: 6000 flw fs0,0(s0) - dd58: 000c 0xc - dd5a: 0800 addi s0,sp,16 - dd5c: 7c00 flw fs0,56(s0) - dd5e: 3000 fld fs0,32(s0) - dd60: 082e slli a6,a6,0xb - dd62: 1aff 0x1aff - dd64: 009f 0000 0000 0x9f - dd6a: 0000 unimp - dd6c: 7400 flw fs0,40(s0) - dd6e: 9000000b 0x9000000b - dd72: 0600000b 0x600000b - dd76: 0800 addi s0,sp,16 - dd78: 7f20 flw fs0,120(a4) - dd7a: 1c00 addi s0,sp,560 - dd7c: b09f 000b 0c00 0xc00000bb09f - dd82: 000c 0xc - dd84: 0600 addi s0,sp,768 - dd86: 0800 addi s0,sp,16 - dd88: 7f20 flw fs0,120(a4) - dd8a: 1c00 addi s0,sp,560 - dd8c: 1c9f 000c 4400 0x4400000c1c9f - dd92: 000c 0xc - dd94: 0600 addi s0,sp,768 - dd96: 0800 addi s0,sp,16 - dd98: 7f20 flw fs0,120(a4) - dd9a: 1c00 addi s0,sp,560 - dd9c: 009f 0000 0000 0x9f - dda2: 0000 unimp - dda4: 7400 flw fs0,40(s0) - dda6: 9000000b 0x9000000b - ddaa: 0100000b 0x100000b - ddae: 5f00 lw s0,56(a4) - ddb0: 0bb0 addi a2,sp,472 - ddb2: 0000 unimp - ddb4: 0c0c addi a1,sp,528 - ddb6: 0000 unimp - ddb8: 0001 nop - ddba: 1c5f 000c 4400 0x4400000c1c5f - ddc0: 000c 0xc - ddc2: 0100 addi s0,sp,128 - ddc4: 5f00 lw s0,56(a4) - ... - ddce: 0b70 addi a2,sp,412 - ddd0: 0000 unimp - ddd2: 0c68 addi a0,sp,540 - ddd4: 0000 unimp - ddd6: 0001 nop - ddd8: 006c addi a1,sp,12 - ddda: 0000 unimp - dddc: 0000 unimp - ddde: 0000 unimp - dde0: 7400 flw fs0,40(s0) - dde2: 7c00000b 0x7c00000b - dde6: 0200000b 0x200000b - ddea: 3000 fld fs0,32(s0) - ddec: 7c9f 000b 9000 0x9000000b7c9f - ddf2: 0100000b 0x100000b - ddf6: 5e00 lw s0,56(a2) - ddf8: 0b90 addi a2,sp,464 - ddfa: 0000 unimp - ddfc: 0ba8 addi a0,sp,472 - ddfe: 0000 unimp - de00: 0001 nop - de02: b05f 000b bc00 0xbc00000bb05f - de08: 0100000b 0x100000b - de0c: 5e00 lw s0,56(a2) - de0e: 0bbc addi a5,sp,472 - de10: 0000 unimp - de12: 0bc0 addi s0,sp,468 - de14: 0000 unimp - de16: 7f7e0003 lb zero,2039(t3) - de1a: c09f 000b c800 0xc800000bc09f - de20: 0100000b 0x100000b - de24: 5e00 lw s0,56(a2) - de26: 0be0 addi s0,sp,476 - de28: 0000 unimp - de2a: 0bf0 addi a2,sp,476 - de2c: 0000 unimp - de2e: 0002 c.slli64 zero - de30: 9f30 0x9f30 - de32: 0bf0 addi a2,sp,476 - de34: 0000 unimp - de36: 0bf8 addi a4,sp,476 - de38: 0000 unimp - de3a: 0001 nop - de3c: f85a fsw fs6,48(sp) - de3e: 0000000b 0xb - de42: 000c 0xc - de44: 0300 addi s0,sp,384 - de46: 7e00 flw fs0,56(a2) - de48: 9f01 0x9f01 - de4a: 0c00 addi s0,sp,528 - de4c: 0000 unimp - de4e: 0c1c addi a5,sp,528 - de50: 0000 unimp - de52: 0005 c.nop 1 - de54: 8c34 0x8c34 - de56: 1c00 addi s0,sp,560 - de58: 1c9f 000c 3c00 0x3c00000c1c9f - de5e: 000c 0xc - de60: 0100 addi s0,sp,128 - de62: 5a00 lw s0,48(a2) - de64: 0c3c addi a5,sp,536 - de66: 0000 unimp - de68: 0c40 addi s0,sp,532 - de6a: 0000 unimp - de6c: 017a0003 lb zero,23(s4) - de70: 409f 000c 4400 0x4400000c409f - de76: 000c 0xc - de78: 0100 addi s0,sp,128 - de7a: 5a00 lw s0,48(a2) - de7c: 0c44 addi s1,sp,532 - de7e: 0000 unimp - de80: 0c5c addi a5,sp,532 - de82: 0000 unimp - de84: 0001 nop - de86: 005f 0000 0000 0x5f - de8c: 0000 unimp - de8e: 7400 flw fs0,40(s0) - de90: 7c00000b 0x7c00000b - de94: 0200000b 0x200000b - de98: 3000 fld fs0,32(s0) - de9a: 7c9f 000b 6000 0x6000000b7c9f - dea0: 000c 0xc - dea2: 0100 addi s0,sp,128 - dea4: 5c00 lw s0,56(s0) - ... - deae: 0c94 addi a3,sp,592 - deb0: 0000 unimp - deb2: 0ca8 addi a0,sp,600 - deb4: 0000 unimp - deb6: 0011 c.nop 4 - deb8: 4b40007b 0x4b40007b - debc: 2224 fld fs1,64(a2) - debe: 007e c.slli zero,0x1f - dec0: 4b40 lw s0,20(a4) - dec2: 2224 fld fs1,64(a2) - dec4: 082d addi a6,a6,11 - dec6: 1aff 0x1aff - dec8: a89f 000c bc00 0xbc00000ca89f - dece: 000c 0xc - ded0: 1200 addi s0,sp,288 - ded2: 7b00 flw fs0,48(a4) - ded4: 4000 lw s0,0(s0) - ded6: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - deda: 0650 addi a2,sp,772 - dedc: 4b40 lw s0,20(a4) - dede: 2224 fld fs1,64(a2) - dee0: 082d addi a6,a6,11 - dee2: 1aff 0x1aff - dee4: bc9f 000c e000 0xe000000cbc9f - deea: 000c 0xc - deec: 1400 addi s0,sp,544 - deee: 9100 0x9100 - def0: 7fb0 flw fa2,120(a5) - def2: 4006 0x4006 - def4: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - def8: 0650 addi a2,sp,772 - defa: 4b40 lw s0,20(a4) - defc: 2224 fld fs1,64(a2) - defe: 082d addi a6,a6,11 - df00: 1aff 0x1aff - df02: 009f 0000 0000 0x9f - df08: 0000 unimp - df0a: 9400 0x9400 - df0c: 000c 0xc - df0e: a400 fsd fs0,8(s0) - df10: 000c 0xc - df12: 0100 addi s0,sp,128 - df14: 5c00 lw s0,56(s0) - df16: 0ca4 addi s1,sp,600 - df18: 0000 unimp - df1a: 0cc4 addi s1,sp,596 - df1c: 0000 unimp - df1e: 0001 nop - df20: c45d beqz s0,dfce <_start-0x7fff2032> - df22: 000c 0xc - df24: c800 sw s0,16(s0) - df26: 000c 0xc - df28: 0200 addi s0,sp,256 - df2a: 3100 fld fs0,32(a0) - df2c: 009f 0000 0000 0x9f - df32: 0000 unimp - df34: bc00 fsd fs0,56(s0) - df36: 000c 0xc - df38: c800 sw s0,16(s0) - df3a: 000c 0xc - df3c: 0100 addi s0,sp,128 - df3e: 5b00 lw s0,48(a4) - df40: 0cc8 addi a0,sp,596 - df42: 0000 unimp - df44: 0cd4 addi a3,sp,596 - df46: 0000 unimp - df48: 0006 c.slli zero,0x1 - df4a: 007c addi a5,sp,12 - df4c: 9f21007b 0x9f21007b - df50: 0cd4 addi a3,sp,596 - df52: 0000 unimp - df54: 0ce0 addi s0,sp,604 - df56: 0000 unimp - df58: 0001 nop - df5a: 005c addi a5,sp,4 - df5c: 0000 unimp - df5e: 0000 unimp - df60: 0000 unimp - df62: 7400 flw fs0,40(s0) - df64: 000d c.nop 3 - df66: 9000 0x9000 - df68: 000d c.nop 3 - df6a: 1100 addi s0,sp,160 - df6c: 7f00 flw fs0,56(a4) - df6e: 4000 lw s0,0(s0) - df70: 7e22244b fnmsub.q fs0,ft4,ft2,fa5,rdn - df74: 4000 lw s0,0(s0) - df76: 2d22244b 0x2d22244b - df7a: ff08 fsw fa0,56(a4) - df7c: 9f1a add t5,t5,t1 - df7e: 0d90 addi a2,sp,720 - df80: 0000 unimp - df82: 0db0 addi a2,sp,728 - df84: 0000 unimp - df86: 0012 c.slli zero,0x4 - df88: 007f 0x7f - df8a: 4b40 lw s0,20(a4) - df8c: 2224 fld fs1,64(a2) - df8e: 5091 li ra,-28 - df90: 4006 0x4006 - df92: 2d22244b 0x2d22244b - df96: ff08 fsw fa0,56(a4) - df98: 9f1a add t5,t5,t1 - df9a: 0db0 addi a2,sp,728 - df9c: 0000 unimp - df9e: 0dc8 addi a0,sp,724 - dfa0: 0000 unimp - dfa2: 40910013 addi zero,sp,1033 - dfa6: 4006 0x4006 - dfa8: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - dfac: 0650 addi a2,sp,772 - dfae: 4b40 lw s0,20(a4) - dfb0: 2224 fld fs1,64(a2) - dfb2: 082d addi a6,a6,11 - dfb4: 1aff 0x1aff - dfb6: 009f 0000 0000 0x9f - dfbc: 0000 unimp - dfbe: 7400 flw fs0,40(s0) - dfc0: 000d c.nop 3 - dfc2: 9000 0x9000 - dfc4: 000d c.nop 3 - dfc6: 0100 addi s0,sp,128 - dfc8: 6c00 flw fs0,24(s0) - dfca: 0d90 addi a2,sp,720 - dfcc: 0000 unimp - dfce: 0da4 addi s1,sp,728 - dfd0: 0000 unimp - dfd2: 0001 nop - dfd4: a45e fsd fs7,8(sp) - dfd6: 000d c.nop 3 - dfd8: ac00 fsd fs0,24(s0) - dfda: 000d c.nop 3 - dfdc: 0200 addi s0,sp,256 - dfde: 3100 fld fs0,32(a0) - dfe0: 009f 0000 0000 0x9f - dfe6: 0000 unimp - dfe8: 9800 0x9800 - dfea: 000d c.nop 3 - dfec: ac00 fsd fs0,24(s0) - dfee: 000d c.nop 3 - dff0: 0100 addi s0,sp,128 - dff2: 5c00 lw s0,56(s0) - dff4: 0dac addi a1,sp,728 - dff6: 0000 unimp - dff8: 0db4 addi a3,sp,728 - dffa: 0000 unimp - dffc: 0006 c.slli zero,0x1 - dffe: 007a c.slli zero,0x1e - e000: 007c addi a5,sp,12 - e002: 9f21 0x9f21 - e004: 0db4 addi a3,sp,728 - e006: 0000 unimp - e008: 0dc0 addi s0,sp,724 - e00a: 0000 unimp - e00c: 0001 nop - e00e: 005a c.slli zero,0x16 - e010: 0000 unimp - e012: 0000 unimp - e014: 0000 unimp - e016: 4800 lw s0,16(s0) - e018: 5000000f 0x5000000f - e01c: 0800000f fence i,unknown - e020: 7d00 flw fs0,56(a0) - e022: 3000 fld fs0,32(s0) - e024: 082e slli a6,a6,0xb - e026: 1aff 0x1aff - e028: 009f 0000 0000 0x9f - e02e: 0000 unimp - e030: 4c00 lw s0,24(s0) - e032: 000e c.slli zero,0x3 - e034: 7000 flw fs0,32(s0) - e036: 000e c.slli zero,0x3 - e038: 0600 addi s0,sp,768 - e03a: 0800 addi s0,sp,16 - e03c: 7f20 flw fs0,120(a4) - e03e: 1c00 addi s0,sp,560 - e040: 989f 000e fc00 0xfc00000e989f - e046: 000e c.slli zero,0x3 - e048: 0600 addi s0,sp,768 - e04a: 0800 addi s0,sp,16 - e04c: 7f20 flw fs0,120(a4) - e04e: 1c00 addi s0,sp,560 - e050: 0c9f 000f 3400 0x3400000f0c9f - e056: 0600000f fence or,unknown - e05a: 0800 addi s0,sp,16 - e05c: 7f20 flw fs0,120(a4) - e05e: 1c00 addi s0,sp,560 - e060: 009f 0000 0000 0x9f - e066: 0000 unimp - e068: 4c00 lw s0,24(s0) - e06a: 000e c.slli zero,0x3 - e06c: 7000 flw fs0,32(s0) - e06e: 000e c.slli zero,0x3 - e070: 0100 addi s0,sp,128 - e072: 5f00 lw s0,56(a4) - e074: 0e98 addi a4,sp,848 - e076: 0000 unimp - e078: 0efc addi a5,sp,860 - e07a: 0000 unimp - e07c: 0001 nop - e07e: 0c5f 000f 3400 0x3400000f0c5f - e084: 0100000f fence w,unknown - e088: 5f00 lw s0,56(a4) - ... - e092: 0e44 addi s1,sp,788 - e094: 0000 unimp - e096: 0e70 addi a2,sp,796 - e098: 0000 unimp - e09a: 0001 nop - e09c: 985a add a6,a6,s6 - e09e: 000e c.slli zero,0x3 - e0a0: 3400 fld fs0,40(s0) - e0a2: 0100000f fence w,unknown - e0a6: 5a00 lw s0,48(a2) - ... - e0b0: 0e4c addi a1,sp,788 - e0b2: 0000 unimp - e0b4: 0e50 addi a2,sp,788 - e0b6: 0000 unimp - e0b8: 0002 c.slli64 zero - e0ba: 9f30 0x9f30 - e0bc: 0e50 addi a2,sp,788 - e0be: 0000 unimp - e0c0: 0e64 addi s1,sp,796 - e0c2: 0000 unimp - e0c4: 0001 nop - e0c6: 705e flw ft0,244(sp) - e0c8: 000e c.slli zero,0x3 - e0ca: 8800 0x8800 - e0cc: 000e c.slli zero,0x3 - e0ce: 0100 addi s0,sp,128 - e0d0: 5f00 lw s0,56(a4) - e0d2: 0e98 addi a4,sp,848 - e0d4: 0000 unimp - e0d6: 0ea8 addi a0,sp,856 - e0d8: 0000 unimp - e0da: 0001 nop - e0dc: a85e fsd fs7,16(sp) - e0de: 000e c.slli zero,0x3 - e0e0: ac00 fsd fs0,24(s0) - e0e2: 000e c.slli zero,0x3 - e0e4: 0300 addi s0,sp,384 - e0e6: 7e00 flw fs0,56(a2) - e0e8: 9f7f 0x9f7f - e0ea: 0eac addi a1,sp,856 - e0ec: 0000 unimp - e0ee: 0eb0 addi a2,sp,856 - e0f0: 0000 unimp - e0f2: 0001 nop - e0f4: d05e sw s7,32(sp) - e0f6: 000e c.slli zero,0x3 - e0f8: e000 fsw fs0,0(s0) - e0fa: 000e c.slli zero,0x3 - e0fc: 0200 addi s0,sp,256 - e0fe: 3000 fld fs0,32(s0) - e100: e09f 000e e800 0xe800000ee09f - e106: 000e c.slli zero,0x3 - e108: 0100 addi s0,sp,128 - e10a: 5600 lw s0,40(a2) - e10c: 0ee8 addi a0,sp,860 - e10e: 0000 unimp - e110: 0ef0 addi a2,sp,860 - e112: 0000 unimp - e114: 017e0003 lb zero,23(t3) - e118: f09f 000e 0c00 0xc00000ef09f - e11e: 0500000f fence ow,unknown - e122: 3400 fld fs0,40(s0) - e124: 007a c.slli zero,0x1e - e126: 9f1c 0x9f1c - e128: 0f0c addi a1,sp,912 - e12a: 0000 unimp - e12c: 0f2c addi a1,sp,920 - e12e: 0000 unimp - e130: 0001 nop - e132: 2c56 fld fs8,336(sp) - e134: 3000000f 0x3000000f - e138: 0300000f fence rw,unknown - e13c: 7600 flw fs0,40(a2) - e13e: 9f01 0x9f01 - e140: 0f30 addi a2,sp,920 - e142: 0000 unimp - e144: 0f34 addi a3,sp,920 - e146: 0000 unimp - e148: 0001 nop - e14a: 3456 fld fs0,368(sp) - e14c: 4c00000f 0x4c00000f - e150: 0100000f fence w,unknown - e154: 5f00 lw s0,56(a4) - ... - e15e: 0e4c addi a1,sp,788 - e160: 0000 unimp - e162: 0e50 addi a2,sp,788 - e164: 0000 unimp - e166: 0002 c.slli64 zero - e168: 9f30 0x9f30 - e16a: 0e50 addi a2,sp,788 - e16c: 0000 unimp - e16e: 0e90 addi a2,sp,848 - e170: 0000 unimp - e172: 0001 nop - e174: 985d andi s0,s0,-9 - e176: 000e c.slli zero,0x3 - e178: 5000 lw s0,32(s0) - e17a: 0100000f fence w,unknown - e17e: 5d00 lw s0,56(a0) - ... - e188: 0f84 addi s1,sp,976 - e18a: 0000 unimp - e18c: 0f98 addi a4,sp,976 - e18e: 0000 unimp - e190: 0011 c.nop 4 - e192: 007a c.slli zero,0x1e - e194: 4b40 lw s0,20(a4) - e196: 2224 fld fs1,64(a2) - e198: 007e c.slli zero,0x1f - e19a: 4b40 lw s0,20(a4) - e19c: 2224 fld fs1,64(a2) - e19e: 082d addi a6,a6,11 - e1a0: 1aff 0x1aff - e1a2: 989f 000f ac00 0xac00000f989f - e1a8: 1200000f 0x1200000f - e1ac: 7a00 flw fs0,48(a2) - e1ae: 4000 lw s0,0(s0) - e1b0: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - e1b4: 0650 addi a2,sp,772 - e1b6: 4b40 lw s0,20(a4) - e1b8: 2224 fld fs1,64(a2) - e1ba: 082d addi a6,a6,11 - e1bc: 1aff 0x1aff - e1be: ac9f 000f dc00 0xdc00000fac9f - e1c4: 1300000f 0x1300000f - e1c8: 9100 0x9100 - e1ca: 0640 addi s0,sp,772 - e1cc: 4b40 lw s0,20(a4) - e1ce: 2224 fld fs1,64(a2) - e1d0: 5091 li ra,-28 - e1d2: 4006 0x4006 - e1d4: 2d22244b 0x2d22244b - e1d8: ff08 fsw fa0,56(a4) - e1da: 9f1a add t5,t5,t1 - ... - e1e4: 0f84 addi s1,sp,976 - e1e6: 0000 unimp - e1e8: 0f94 addi a3,sp,976 - e1ea: 0000 unimp - e1ec: 0001 nop - e1ee: 000f945b 0xf945b - e1f2: b400 fsd fs0,40(s0) - e1f4: 0100000f fence w,unknown - e1f8: 5d00 lw s0,56(a0) - e1fa: 0fb4 addi a3,sp,984 - e1fc: 0000 unimp - e1fe: 0fb8 addi a4,sp,984 - e200: 0000 unimp - e202: 0002 c.slli64 zero - e204: 9f31 0x9f31 - ... - e20e: 0fac addi a1,sp,984 - e210: 0000 unimp - e212: 0fb8 addi a4,sp,984 - e214: 0000 unimp - e216: 0001 nop - e218: b85a fsd fs6,48(sp) - e21a: c400000f 0xc400000f - e21e: 0600000f fence or,unknown - e222: 7b00 flw fs0,48(a4) - e224: 7a00 flw fs0,48(a2) - e226: 2100 fld fs0,0(a0) - e228: c49f 000f dc00 0xdc00000fc49f - e22e: 0100000f fence w,unknown - e232: 5b00 lw s0,48(a4) - ... - e23c: 107c addi a5,sp,44 - e23e: 0000 unimp - e240: 10cc addi a1,sp,100 - e242: 0000 unimp - e244: 0011 c.nop 4 - e246: 007e c.slli zero,0x1f - e248: 4b40 lw s0,20(a4) - e24a: 2224 fld fs1,64(a2) - e24c: 4b40007b 0x4b40007b - e250: 2224 fld fs1,64(a2) - e252: 082d addi a6,a6,11 - e254: 1aff 0x1aff - e256: cc9f 0010 d400 0xd4000010cc9f - e25c: 0010 0x10 - e25e: 1300 addi s0,sp,416 - e260: 9100 0x9100 - e262: 7fb0 flw fa2,120(a5) - e264: 4006 0x4006 - e266: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - e26a: 4000 lw s0,0(s0) - e26c: 2d22244b 0x2d22244b - e270: ff08 fsw fa0,56(a4) - e272: 9f1a add t5,t5,t1 - e274: 10d4 addi a3,sp,100 - e276: 0000 unimp - e278: 10e0 addi s0,sp,108 - e27a: 0000 unimp - e27c: 0014 0x14 - e27e: b091 j dac2 <_start-0x7fff253e> - e280: 067f 0x67f - e282: 4b40 lw s0,20(a4) - e284: 2224 fld fs1,64(a2) - e286: 5091 li ra,-28 - e288: 4006 0x4006 - e28a: 2d22244b 0x2d22244b - e28e: ff08 fsw fa0,56(a4) - e290: 9f1a add t5,t5,t1 - e292: 10e0 addi s0,sp,108 - e294: 0000 unimp - e296: 1124 addi s1,sp,168 - e298: 0000 unimp - e29a: 0018 0x18 - e29c: b091 j dae0 <_start-0x7fff2520> - e29e: 067f 0x67f - e2a0: 4b40 lw s0,20(a4) - e2a2: 2224 fld fs1,64(a2) - e2a4: b091 j dae8 <_start-0x7fff2518> - e2a6: 067f 0x67f - e2a8: 007f 0x7f - e2aa: 401c lw a5,0(s0) - e2ac: 2d22244b 0x2d22244b - e2b0: ff08 fsw fa0,56(a4) - e2b2: 9f1a add t5,t5,t1 - e2b4: 1124 addi s1,sp,168 - e2b6: 0000 unimp - e2b8: 1128 addi a0,sp,168 - e2ba: 0000 unimp - e2bc: 0011 c.nop 4 - e2be: 007e c.slli zero,0x1f - e2c0: 4b40 lw s0,20(a4) - e2c2: 2224 fld fs1,64(a2) - e2c4: 4b40007b 0x4b40007b - e2c8: 2224 fld fs1,64(a2) - e2ca: 082d addi a6,a6,11 - e2cc: 1aff 0x1aff - e2ce: 289f 0011 3400 0x34000011289f - e2d4: 0011 c.nop 4 - e2d6: 1200 addi s0,sp,288 - e2d8: 7e00 flw fs0,56(a2) - e2da: 4000 lw s0,0(s0) - e2dc: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - e2e0: 0650 addi a2,sp,772 - e2e2: 4b40 lw s0,20(a4) - e2e4: 2224 fld fs1,64(a2) - e2e6: 082d addi a6,a6,11 - e2e8: 1aff 0x1aff - e2ea: 009f 0000 0000 0x9f - e2f0: 0000 unimp - e2f2: 7c00 flw fs0,56(s0) - e2f4: 0010 0x10 - e2f6: 9800 0x9800 - e2f8: 0010 0x10 - e2fa: 0100 addi s0,sp,128 - e2fc: 5a00 lw s0,48(a2) - e2fe: 1098 addi a4,sp,96 - e300: 0000 unimp - e302: 10ac addi a1,sp,104 - e304: 0000 unimp - e306: 0001 nop - e308: ac6e fsd fs11,24(sp) - e30a: 0010 0x10 - e30c: b000 fsd fs0,32(s0) - e30e: 0010 0x10 - e310: 0200 addi s0,sp,256 - e312: 3100 fld fs0,32(a0) - e314: 009f 0000 0000 0x9f - e31a: 0000 unimp - e31c: a400 fsd fs0,8(s0) - e31e: 0010 0x10 - e320: b000 fsd fs0,32(s0) - e322: 0010 0x10 - e324: 0100 addi s0,sp,128 - e326: 6400 flw fs0,8(s0) - e328: 10b0 addi a2,sp,104 - e32a: 0000 unimp - e32c: 10b8 addi a4,sp,104 - e32e: 0000 unimp - e330: 0006 c.slli zero,0x1 - e332: 00840077 0x840077 - e336: 9f21 0x9f21 - e338: 10b8 addi a4,sp,104 - e33a: 0000 unimp - e33c: 1134 addi a3,sp,168 - e33e: 0000 unimp - e340: 0001 nop - e342: 00000057 vadd.vv v0,v0,v0,v0.t - e346: 0000 unimp - e348: 0000 unimp - e34a: e000 fsw fs0,0(s0) - e34c: 0010 0x10 - e34e: f800 fsw fs0,48(s0) - e350: 0010 0x10 - e352: 1100 addi s0,sp,160 - e354: 7f00 flw fs0,56(a4) - e356: 4000 lw s0,0(s0) - e358: 7e22244b fnmsub.q fs0,ft4,ft2,fa5,rdn - e35c: 4000 lw s0,0(s0) - e35e: 2d22244b 0x2d22244b - e362: ff08 fsw fa0,56(a4) - e364: 9f1a add t5,t5,t1 - e366: 10f8 addi a4,sp,108 - e368: 0000 unimp - e36a: 1124 addi s1,sp,168 - e36c: 0000 unimp - e36e: 0012 c.slli zero,0x4 - e370: 007f 0x7f - e372: 4b40 lw s0,20(a4) - e374: 2224 fld fs1,64(a2) - e376: 5091 li ra,-28 - e378: 4006 0x4006 - e37a: 2d22244b 0x2d22244b - e37e: ff08 fsw fa0,56(a4) - e380: 9f1a add t5,t5,t1 - ... - e38a: 10e4 addi s1,sp,108 - e38c: 0000 unimp - e38e: 110c addi a1,sp,160 - e390: 0000 unimp - e392: 0001 nop - e394: 0c5c addi a5,sp,532 - e396: 0011 c.nop 4 - e398: 1000 addi s0,sp,32 - e39a: 0011 c.nop 4 - e39c: 0200 addi s0,sp,256 - e39e: 3100 fld fs0,32(a0) - e3a0: 009f 0000 0000 0x9f - e3a6: 0000 unimp - e3a8: fc00 fsw fs0,56(s0) - e3aa: 0010 0x10 - e3ac: 1000 addi s0,sp,32 - e3ae: 0011 c.nop 4 - e3b0: 0100 addi s0,sp,128 - e3b2: 5d00 lw s0,56(a0) - e3b4: 1110 addi a2,sp,160 - e3b6: 0000 unimp - e3b8: 1118 addi a4,sp,160 - e3ba: 0000 unimp - e3bc: 0006 c.slli zero,0x1 - e3be: 007d007b 0x7d007b - e3c2: 9f21 0x9f21 - e3c4: 1118 addi a4,sp,160 - e3c6: 0000 unimp - e3c8: 111c addi a5,sp,160 - e3ca: 0000 unimp - e3cc: 0001 nop - e3ce: 0000005b 0x5b - e3d2: 0000 unimp - e3d4: 0000 unimp - e3d6: 5000 lw s0,32(s0) - e3d8: 0011 c.nop 4 - e3da: 7800 flw fs0,48(s0) - e3dc: 0011 c.nop 4 - e3de: 0200 addi s0,sp,256 - e3e0: 3300 fld fs0,32(a4) - e3e2: 009f 0000 0000 0x9f - e3e8: 0000 unimp - e3ea: 5000 lw s0,32(s0) - e3ec: 0011 c.nop 4 - e3ee: 7800 flw fs0,48(s0) - e3f0: 0011 c.nop 4 - e3f2: 0200 addi s0,sp,256 - e3f4: 4d00 lw s0,24(a0) - e3f6: 009f 0000 0000 0x9f - e3fc: 0000 unimp - e3fe: 5000 lw s0,32(s0) - e400: 0011 c.nop 4 - e402: 7800 flw fs0,48(s0) - e404: 0011 c.nop 4 - e406: 0200 addi s0,sp,256 - e408: 3000 fld fs0,32(s0) - e40a: 009f 0000 0000 0x9f - e410: 0000 unimp - e412: 5000 lw s0,32(s0) - e414: 0011 c.nop 4 - e416: 5400 lw s0,40(s0) - e418: 0011 c.nop 4 - e41a: 0200 addi s0,sp,256 - e41c: 3300 fld fs0,32(a4) - e41e: 009f 0000 0000 0x9f - e424: 0000 unimp - e426: bc00 fsd fs0,56(s0) - e428: 0011 c.nop 4 - e42a: e400 fsw fs0,8(s0) - e42c: 0011 c.nop 4 - e42e: 0200 addi s0,sp,256 - e430: 3300 fld fs0,32(a4) - e432: 009f 0000 0000 0x9f - e438: 0000 unimp - e43a: bc00 fsd fs0,56(s0) - e43c: 0011 c.nop 4 - e43e: e400 fsw fs0,8(s0) - e440: 0011 c.nop 4 - e442: 0200 addi s0,sp,256 - e444: 4d00 lw s0,24(a0) - e446: 009f 0000 0000 0x9f - e44c: 0000 unimp - e44e: bc00 fsd fs0,56(s0) - e450: 0011 c.nop 4 - e452: e400 fsw fs0,8(s0) - e454: 0011 c.nop 4 - e456: 0200 addi s0,sp,256 - e458: 3000 fld fs0,32(s0) - e45a: 009f 0000 0000 0x9f - e460: 0000 unimp - e462: c000 sw s0,0(s0) - e464: 0009 c.nop 2 - e466: dc00 sw s0,56(s0) - e468: 0009 c.nop 2 - e46a: 0300 addi s0,sp,384 - e46c: 0900 addi s0,sp,144 - e46e: 9fff 0x9fff - e470: 11bc addi a5,sp,232 - e472: 0000 unimp - e474: 11c0 addi s0,sp,228 - e476: 0000 unimp - e478: 0002 c.slli64 zero - e47a: 00009f33 sll t5,ra,zero - e47e: 0000 unimp - e480: 0000 unimp - e482: 0000 unimp - e484: 11fc addi a5,sp,236 - e486: 0000 unimp - e488: 124c addi a1,sp,292 - e48a: 0000 unimp - e48c: 0011 c.nop 4 - e48e: 007e c.slli zero,0x1f - e490: 4b40 lw s0,20(a4) - e492: 2224 fld fs1,64(a2) - e494: 4b40007b 0x4b40007b - e498: 2224 fld fs1,64(a2) - e49a: 082d addi a6,a6,11 - e49c: 1aff 0x1aff - e49e: 4c9f 0012 5400 0x540000124c9f - e4a4: 0012 c.slli zero,0x4 - e4a6: 1300 addi s0,sp,416 - e4a8: 9100 0x9100 - e4aa: 7fb0 flw fa2,120(a5) - e4ac: 4006 0x4006 - e4ae: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - e4b2: 4000 lw s0,0(s0) - e4b4: 2d22244b 0x2d22244b - e4b8: ff08 fsw fa0,56(a4) - e4ba: 9f1a add t5,t5,t1 - e4bc: 1254 addi a3,sp,292 - e4be: 0000 unimp - e4c0: 1260 addi s0,sp,300 - e4c2: 0000 unimp - e4c4: 0014 0x14 - e4c6: b091 j dd0a <_start-0x7fff22f6> - e4c8: 067f 0x67f - e4ca: 4b40 lw s0,20(a4) - e4cc: 2224 fld fs1,64(a2) - e4ce: 5091 li ra,-28 - e4d0: 4006 0x4006 - e4d2: 2d22244b 0x2d22244b - e4d6: ff08 fsw fa0,56(a4) - e4d8: 9f1a add t5,t5,t1 - e4da: 1260 addi s0,sp,300 - e4dc: 0000 unimp - e4de: 1294 addi a3,sp,352 - e4e0: 0000 unimp - e4e2: 0018 0x18 - e4e4: b091 j dd28 <_start-0x7fff22d8> - e4e6: 067f 0x67f - e4e8: 4b40 lw s0,20(a4) - e4ea: 2224 fld fs1,64(a2) - e4ec: b091 j dd30 <_start-0x7fff22d0> - e4ee: 067f 0x67f - e4f0: 007f 0x7f - e4f2: 401c lw a5,0(s0) - e4f4: 2d22244b 0x2d22244b - e4f8: ff08 fsw fa0,56(a4) - e4fa: 9f1a add t5,t5,t1 - e4fc: 1294 addi a3,sp,352 - e4fe: 0000 unimp - e500: 12a0 addi s0,sp,360 - e502: 0000 unimp - e504: 0019 c.nop 6 - e506: b091 j dd4a <_start-0x7fff22b6> - e508: 067f 0x67f - e50a: 4b40 lw s0,20(a4) - e50c: 2224 fld fs1,64(a2) - e50e: b091 j dd52 <_start-0x7fff22ae> - e510: 067f 0x67f - e512: 4091 li ra,4 - e514: 1c06 slli s8,s8,0x21 - e516: 4b40 lw s0,20(a4) - e518: 2224 fld fs1,64(a2) - e51a: 082d addi a6,a6,11 - e51c: 1aff 0x1aff - e51e: 009f 0013 0400 0x4000013009f - e524: 11000013 li zero,272 - e528: 7e00 flw fs0,56(a2) - e52a: 4000 lw s0,0(s0) - e52c: 7b22244b fnmsub.d fs0,ft4,fs2,fa5,rdn - e530: 4000 lw s0,0(s0) - e532: 2d22244b 0x2d22244b - e536: ff08 fsw fa0,56(a4) - e538: 9f1a add t5,t5,t1 - e53a: 1304 addi s1,sp,416 - e53c: 0000 unimp - e53e: 1314 addi a3,sp,416 - e540: 0000 unimp - e542: 0012 c.slli zero,0x4 - e544: 007e c.slli zero,0x1f - e546: 4b40 lw s0,20(a4) - e548: 2224 fld fs1,64(a2) - e54a: 5091 li ra,-28 - e54c: 4006 0x4006 - e54e: 2d22244b 0x2d22244b - e552: ff08 fsw fa0,56(a4) - e554: 9f1a add t5,t5,t1 - ... - e55e: 11fc addi a5,sp,236 - e560: 0000 unimp - e562: 1218 addi a4,sp,288 - e564: 0000 unimp - e566: 0001 nop - e568: 186e slli a6,a6,0x3b - e56a: 0012 c.slli zero,0x4 - e56c: 2c00 fld fs0,24(s0) - e56e: 0012 c.slli zero,0x4 - e570: 0100 addi s0,sp,128 - e572: 6f00 flw fs0,24(a4) - e574: 122c addi a1,sp,296 - e576: 0000 unimp - e578: 1230 addi a2,sp,296 - e57a: 0000 unimp - e57c: 0002 c.slli64 zero - e57e: 9f31 0x9f31 - ... - e588: 1224 addi s1,sp,296 - e58a: 0000 unimp - e58c: 1230 addi a2,sp,296 - e58e: 0000 unimp - e590: 0001 nop - e592: 3065 jal de3a <_start-0x7fff21c6> - e594: 0012 c.slli zero,0x4 - e596: 3800 fld fs0,48(s0) - e598: 0012 c.slli zero,0x4 - e59a: 0600 addi s0,sp,768 - e59c: 8300 0x8300 - e59e: 8500 0x8500 - e5a0: 2100 fld fs0,0(a0) - e5a2: 389f 0012 a000 0xa0000012389f - e5a8: 0012 c.slli zero,0x4 - e5aa: 0100 addi s0,sp,128 - e5ac: 6300 flw fs0,0(a4) - e5ae: 1300 addi s0,sp,416 - e5b0: 0000 unimp - e5b2: 1314 addi a3,sp,416 - e5b4: 0000 unimp - e5b6: 0001 nop - e5b8: 00000063 beqz zero,e5b8 <_start-0x7fff1a48> - e5bc: 0000 unimp - e5be: 0000 unimp - e5c0: 6000 flw fs0,0(s0) - e5c2: 0012 c.slli zero,0x4 - e5c4: 7400 flw fs0,40(s0) - e5c6: 0012 c.slli zero,0x4 - e5c8: 1100 addi s0,sp,160 - e5ca: 7f00 flw fs0,56(a4) - e5cc: 4000 lw s0,0(s0) - e5ce: 7e22244b fnmsub.q fs0,ft4,ft2,fa5,rdn - e5d2: 4000 lw s0,0(s0) - e5d4: 2d22244b 0x2d22244b - e5d8: ff08 fsw fa0,56(a4) - e5da: 9f1a add t5,t5,t1 - e5dc: 1274 addi a3,sp,300 - e5de: 0000 unimp - e5e0: 1294 addi a3,sp,352 - e5e2: 0000 unimp - e5e4: 0012 c.slli zero,0x4 - e5e6: 007f 0x7f - e5e8: 4b40 lw s0,20(a4) - e5ea: 2224 fld fs1,64(a2) - e5ec: 5091 li ra,-28 - e5ee: 4006 0x4006 - e5f0: 2d22244b 0x2d22244b - e5f4: ff08 fsw fa0,56(a4) - e5f6: 9f1a add t5,t5,t1 - e5f8: 1294 addi a3,sp,352 - e5fa: 0000 unimp - e5fc: 12a0 addi s0,sp,360 - e5fe: 0000 unimp - e600: 40910013 addi zero,sp,1033 - e604: 4006 0x4006 - e606: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - e60a: 0650 addi a2,sp,772 - e60c: 4b40 lw s0,20(a4) - e60e: 2224 fld fs1,64(a2) - e610: 082d addi a6,a6,11 - e612: 1aff 0x1aff - e614: 009f 0000 0000 0x9f - e61a: 0000 unimp - e61c: 6400 flw fs0,8(s0) - e61e: 0012 c.slli zero,0x4 - e620: 8800 0x8800 - e622: 0012 c.slli zero,0x4 - e624: 0100 addi s0,sp,128 - e626: 5c00 lw s0,56(s0) - e628: 1288 addi a0,sp,352 - e62a: 0000 unimp - e62c: 128c addi a1,sp,352 - e62e: 0000 unimp - e630: 0002 c.slli64 zero - e632: 9f31 0x9f31 - ... - e63c: 127c addi a5,sp,300 - e63e: 0000 unimp - e640: 128c addi a1,sp,352 - e642: 0000 unimp - e644: 0001 nop - e646: 8c5d or s0,s0,a5 - e648: 0012 c.slli zero,0x4 - e64a: 9400 0x9400 - e64c: 0012 c.slli zero,0x4 - e64e: 0600 addi s0,sp,768 - e650: 7a00 flw fs0,48(a2) - e652: 7d00 flw fs0,56(a0) - e654: 2100 fld fs0,0(a0) - e656: 949f 0012 9800 0x98000012949f - e65c: 0012 c.slli zero,0x4 - e65e: 0100 addi s0,sp,128 - e660: 5f00 lw s0,56(a4) - e662: 1298 addi a4,sp,352 - e664: 0000 unimp - e666: 12a0 addi s0,sp,360 - e668: 0000 unimp - e66a: 0006 c.slli zero,0x1 - e66c: 007a c.slli zero,0x1e - e66e: 007d c.nop 31 - e670: 9f21 0x9f21 - ... - e67a: 12ac addi a1,sp,360 - e67c: 0000 unimp - e67e: 1300 addi s0,sp,416 - e680: 0000 unimp - e682: 0001 nop - e684: 205a fld ft0,400(sp) - e686: 28000013 li zero,640 - e68a: 01000013 li zero,16 - e68e: 5a00 lw s0,48(a2) - e690: 1334 addi a3,sp,424 - e692: 0000 unimp - e694: 133c addi a5,sp,424 - e696: 0000 unimp - e698: 0001 nop - e69a: 445a lw s0,148(sp) - e69c: c4000013 li zero,-960 - e6a0: 01000013 li zero,16 - e6a4: 5a00 lw s0,48(a2) - e6a6: 13c4 addi s1,sp,484 - e6a8: 0000 unimp - e6aa: 13d8 addi a4,sp,484 - e6ac: 0000 unimp - e6ae: 0001 nop - e6b0: f458 fsw fa4,44(s0) - e6b2: 0014 0x14 - e6b4: 0c00 addi s0,sp,528 - e6b6: 0015 c.nop 5 - e6b8: 0100 addi s0,sp,128 - e6ba: 5a00 lw s0,48(a2) - ... - e6c4: 12bc addi a5,sp,360 - e6c6: 0000 unimp - e6c8: 12f4 addi a3,sp,364 - e6ca: 0000 unimp - e6cc: 0001 nop - e6ce: f460 fsw fs0,108(s0) - e6d0: 0012 c.slli zero,0x4 - e6d2: 0000 unimp - e6d4: 0a000013 li zero,160 - e6d8: 7a00 flw fs0,48(a2) - e6da: 0800 addi s0,sp,16 - e6dc: 1420 addi s0,sp,552 - e6de: 1b14 addi a3,sp,432 - e6e0: 1c1e slli s8,s8,0x27 - e6e2: 4c9f 0013 a000 0xa00000134c9f - e6e8: 01000013 li zero,16 - e6ec: 6000 flw fs0,0(s0) - e6ee: 13a0 addi s0,sp,488 - e6f0: 0000 unimp - e6f2: 13c8 addi a0,sp,484 - e6f4: 0000 unimp - e6f6: 000a c.slli zero,0x2 - e6f8: 007a c.slli zero,0x1e - e6fa: 2008 fld fa0,0(s0) - e6fc: 1414 addi a3,sp,544 - e6fe: 9f1c1e1b 0x9f1c1e1b - e702: 13c8 addi a0,sp,484 - e704: 0000 unimp - e706: 13d0 addi a2,sp,484 - e708: 0000 unimp - e70a: 000a c.slli zero,0x2 - e70c: 007a c.slli zero,0x1e - e70e: 007f 0x7f - e710: 1414 addi a3,sp,544 - e712: 9f1c1e1b 0x9f1c1e1b - e716: 14f4 addi a3,sp,620 - e718: 0000 unimp - e71a: 150c addi a1,sp,672 - e71c: 0000 unimp - e71e: 000a c.slli zero,0x2 - e720: 007a c.slli zero,0x1e - e722: 2008 fld fa0,0(s0) - e724: 1414 addi a3,sp,544 - e726: 9f1c1e1b 0x9f1c1e1b - ... - e732: 12bc addi a5,sp,360 - e734: 0000 unimp - e736: 12d0 addi a2,sp,356 - e738: 0000 unimp - e73a: 0006 c.slli zero,0x1 - e73c: 2008 fld fa0,0(s0) - e73e: 0080 addi s0,sp,64 - e740: 9f1c 0x9f1c - e742: 12d0 addi a2,sp,356 - e744: 0000 unimp - e746: 12f8 addi a4,sp,364 - e748: 0000 unimp - e74a: 0001 nop - e74c: f85d bnez s0,e702 <_start-0x7fff18fe> - e74e: 0012 c.slli zero,0x4 - e750: 0000 unimp - e752: 0d000013 li zero,208 - e756: 0800 addi s0,sp,16 - e758: 7a20 flw fs0,112(a2) - e75a: 0800 addi s0,sp,16 - e75c: 1420 addi s0,sp,552 - e75e: 1b14 addi a3,sp,432 - e760: 1c1e slli s8,s8,0x27 - e762: 9f1c 0x9f1c - e764: 134c addi a1,sp,420 - e766: 0000 unimp - e768: 137c addi a5,sp,428 - e76a: 0000 unimp - e76c: 0006 c.slli zero,0x1 - e76e: 2008 fld fa0,0(s0) - e770: 0080 addi s0,sp,64 - e772: 9f1c 0x9f1c - e774: 137c addi a5,sp,428 - e776: 0000 unimp - e778: 13a0 addi s0,sp,488 - e77a: 0000 unimp - e77c: 0001 nop - e77e: a05d j e824 <_start-0x7fff17dc> - e780: c8000013 li zero,-896 - e784: 0d000013 li zero,208 - e788: 0800 addi s0,sp,16 - e78a: 7a20 flw fs0,112(a2) - e78c: 0800 addi s0,sp,16 - e78e: 1420 addi s0,sp,552 - e790: 1b14 addi a3,sp,432 - e792: 1c1e slli s8,s8,0x27 - e794: 9f1c 0x9f1c - e796: 13c8 addi a0,sp,484 - e798: 0000 unimp - e79a: 13d0 addi a2,sp,484 - e79c: 0000 unimp - e79e: 000d c.nop 3 - e7a0: 2008 fld fa0,0(s0) - e7a2: 007a c.slli zero,0x1e - e7a4: 007f 0x7f - e7a6: 1414 addi a3,sp,544 - e7a8: 1c1c1e1b 0x1c1c1e1b - e7ac: f49f 0014 0c00 0xc000014f49f - e7b2: 0015 c.nop 5 - e7b4: 0d00 addi s0,sp,656 - e7b6: 0800 addi s0,sp,16 - e7b8: 7a20 flw fs0,112(a2) - e7ba: 0800 addi s0,sp,16 - e7bc: 1420 addi s0,sp,552 - e7be: 1b14 addi a3,sp,432 - e7c0: 1c1e slli s8,s8,0x27 - e7c2: 9f1c 0x9f1c - ... - e7cc: 12bc addi a5,sp,360 - e7ce: 0000 unimp - e7d0: 12f0 addi a2,sp,364 - e7d2: 0000 unimp - e7d4: 0001 nop - e7d6: f05f 0012 f800 0xf8000012f05f - e7dc: 0012 c.slli zero,0x4 - e7de: 0300 addi s0,sp,384 - e7e0: 7f00 flw fs0,56(a4) - e7e2: 9f01 0x9f01 - e7e4: 12f8 addi a4,sp,364 - e7e6: 0000 unimp - e7e8: 1300 addi s0,sp,416 - e7ea: 0000 unimp - e7ec: 0006 c.slli zero,0x1 - e7ee: 007a c.slli zero,0x1e - e7f0: 2008 fld fa0,0(s0) - e7f2: 134c9f1b 0x134c9f1b - e7f6: 0000 unimp - e7f8: 1378 addi a4,sp,428 - e7fa: 0000 unimp - e7fc: 0001 nop - e7fe: 785f 0013 7c00 0x7c000013785f - e804: 03000013 li zero,48 - e808: 7f00 flw fs0,56(a4) - e80a: 9f01 0x9f01 - e80c: 137c addi a5,sp,428 - e80e: 0000 unimp - e810: 13a0 addi s0,sp,488 - e812: 0000 unimp - e814: 0001 nop - e816: a05f 0013 c800 0xc8000013a05f - e81c: 06000013 li zero,96 - e820: 7a00 flw fs0,48(a2) - e822: 0800 addi s0,sp,16 - e824: 1b20 addi s0,sp,440 - e826: c89f 0013 d000 0xd0000013c89f - e82c: 06000013 li zero,96 - e830: 7a00 flw fs0,48(a2) - e832: 7f00 flw fs0,56(a4) - e834: 1b00 addi s0,sp,432 - e836: f49f 0014 0c00 0xc000014f49f - e83c: 0015 c.nop 5 - e83e: 0600 addi s0,sp,768 - e840: 7a00 flw fs0,48(a2) - e842: 0800 addi s0,sp,16 - e844: 1b20 addi s0,sp,440 - e846: 009f 0000 0000 0x9f - e84c: 0000 unimp - e84e: f000 fsw fs0,32(s0) - e850: 0012 c.slli zero,0x4 - e852: f800 fsw fs0,48(s0) - e854: 0012 c.slli zero,0x4 - e856: 0100 addi s0,sp,128 - e858: 5f00 lw s0,56(a4) - e85a: 135c addi a5,sp,420 - e85c: 0000 unimp - e85e: 137c addi a5,sp,428 - e860: 0000 unimp - e862: 0001 nop - e864: a05d j e90a <_start-0x7fff16f6> - e866: c8000013 li zero,-896 - e86a: 01000013 li zero,16 - e86e: 5f00 lw s0,56(a4) - e870: 14f4 addi a3,sp,620 - e872: 0000 unimp - e874: 14f8 addi a4,sp,620 - e876: 0000 unimp - e878: 0001 nop - e87a: 005f 0000 0000 0x5f - e880: 0000 unimp - e882: dc00 sw s0,56(s0) - e884: 0014 0x14 - e886: f400 fsw fs0,40(s0) - e888: 0014 0x14 - e88a: 0800 addi s0,sp,16 - e88c: 7a00 flw fs0,48(a2) - e88e: 3000 fld fs0,32(s0) - e890: 082e slli a6,a6,0xb - e892: 1aff 0x1aff - e894: 009f 0000 0000 0x9f - e89a: 0000 unimp - e89c: d800 sw s0,48(s0) - e89e: fc000013 li zero,-64 - e8a2: 06000013 li zero,96 - e8a6: 0800 addi s0,sp,16 - e8a8: 7820 flw fs0,112(s0) - e8aa: 1c00 addi s0,sp,560 - e8ac: 1c9f 0014 8800 0x880000141c9f - e8b2: 0014 0x14 - e8b4: 0600 addi s0,sp,768 - e8b6: 0800 addi s0,sp,16 - e8b8: 7820 flw fs0,112(s0) - e8ba: 1c00 addi s0,sp,560 - e8bc: 989f 0014 c400 0xc4000014989f - e8c2: 0014 0x14 - e8c4: 0600 addi s0,sp,768 - e8c6: 0800 addi s0,sp,16 - e8c8: 7820 flw fs0,112(s0) - e8ca: 1c00 addi s0,sp,560 - e8cc: 009f 0000 0000 0x9f - e8d2: 0000 unimp - e8d4: d800 sw s0,48(s0) - e8d6: fc000013 li zero,-64 - e8da: 01000013 li zero,16 - e8de: 5800 lw s0,48(s0) - e8e0: 141c addi a5,sp,544 - e8e2: 0000 unimp - e8e4: 1488 addi a0,sp,608 - e8e6: 0000 unimp - e8e8: 0001 nop - e8ea: 9858 0x9858 - e8ec: 0014 0x14 - e8ee: c400 sw s0,8(s0) - e8f0: 0014 0x14 - e8f2: 0100 addi s0,sp,128 - e8f4: 5800 lw s0,48(s0) - ... - e8fe: 13cc addi a1,sp,484 - e900: 0000 unimp - e902: 13e4 addi s1,sp,492 - e904: 0000 unimp - e906: 0001 nop - e908: e460 fsw fs0,76(s0) - e90a: e8000013 li zero,-384 - e90e: 01000013 li zero,16 - e912: 5d00 lw s0,56(a0) - e914: 13e8 addi a0,sp,492 - e916: 0000 unimp - e918: 13fc addi a5,sp,492 - e91a: 0000 unimp - e91c: 0001 nop - e91e: 1c60 addi s0,sp,572 - e920: 0014 0x14 - e922: c400 sw s0,8(s0) - e924: 0014 0x14 - e926: 0100 addi s0,sp,128 - e928: 6000 flw fs0,0(s0) - ... - e932: 13d8 addi a4,sp,484 - e934: 0000 unimp - e936: 13ec addi a1,sp,492 - e938: 0000 unimp - e93a: 0001 nop - e93c: fc5e fsw fs7,56(sp) - e93e: 14000013 li zero,320 - e942: 0014 0x14 - e944: 0100 addi s0,sp,128 - e946: 5800 lw s0,48(s0) - e948: 141c addi a5,sp,544 - e94a: 0000 unimp - e94c: 1430 addi a2,sp,552 - e94e: 0000 unimp - e950: 0001 nop - e952: 305e fld ft0,496(sp) - e954: 0014 0x14 - e956: 3400 fld fs0,40(s0) - e958: 0014 0x14 - e95a: 0300 addi s0,sp,384 - e95c: 7e00 flw fs0,56(a2) - e95e: 9f7f 0x9f7f - e960: 1434 addi a3,sp,552 - e962: 0000 unimp - e964: 1438 addi a4,sp,552 - e966: 0000 unimp - e968: 0001 nop - e96a: 585e lw a6,244(sp) - e96c: 0014 0x14 - e96e: 6c00 flw fs0,24(s0) - e970: 0014 0x14 - e972: 0200 addi s0,sp,256 - e974: 3000 fld fs0,32(s0) - e976: 6c9f 0014 7400 0x740000146c9f - e97c: 0014 0x14 - e97e: 0100 addi s0,sp,128 - e980: 5c00 lw s0,56(s0) - e982: 1474 addi a3,sp,556 - e984: 0000 unimp - e986: 147c addi a5,sp,556 - e988: 0000 unimp - e98a: 017f0003 lb zero,23(t5) - e98e: 7c9f 0014 9800 0x980000147c9f - e994: 0014 0x14 - e996: 0500 addi s0,sp,640 - e998: 3400 fld fs0,40(s0) - e99a: 0080 addi s0,sp,64 - e99c: 9f1c 0x9f1c - e99e: 1498 addi a4,sp,608 - e9a0: 0000 unimp - e9a2: 14b0 addi a2,sp,616 - e9a4: 0000 unimp - e9a6: 0001 nop - e9a8: b05c fsd fa5,160(s0) - e9aa: 0014 0x14 - e9ac: c000 sw s0,0(s0) - e9ae: 0014 0x14 - e9b0: 0300 addi s0,sp,384 - e9b2: 7c00 flw fs0,56(s0) - e9b4: 9f7f 0x9f7f - e9b6: 14c0 addi s0,sp,612 - e9b8: 0000 unimp - e9ba: 14c4 addi s1,sp,612 - e9bc: 0000 unimp - e9be: 0001 nop - e9c0: c45c sw a5,12(s0) - e9c2: 0014 0x14 - e9c4: e800 fsw fs0,16(s0) - e9c6: 0014 0x14 - e9c8: 0100 addi s0,sp,128 - e9ca: 5800 lw s0,48(s0) - ... - e9d4: 13d8 addi a4,sp,484 - e9d6: 0000 unimp - e9d8: 14f4 addi a3,sp,620 - e9da: 0000 unimp - e9dc: 0001 nop - e9de: 005a c.slli zero,0x16 - e9e0: 0000 unimp - e9e2: 0000 unimp - e9e4: 0000 unimp - e9e6: 9800 0x9800 - e9e8: 0004 0x4 - e9ea: 0400 addi s0,sp,512 - e9ec: 0006 c.slli zero,0x1 - e9ee: 0200 addi s0,sp,256 - e9f0: 3000 fld fs0,32(s0) - e9f2: 0c9f 0015 2000 0x200000150c9f - e9f8: 0015 c.nop 5 - e9fa: 0200 addi s0,sp,256 - e9fc: 3000 fld fs0,32(s0) - e9fe: 009f 0000 0000 0x9f - ea04: 0000 unimp - ea06: c000 sw s0,0(s0) - ea08: 0004 0x4 - ea0a: c800 sw s0,16(s0) - ea0c: 0004 0x4 - ea0e: 0100 addi s0,sp,128 - ea10: 5f00 lw s0,56(a4) - ea12: 04c8 addi a0,sp,580 - ea14: 0000 unimp - ea16: 04cc addi a1,sp,580 - ea18: 0000 unimp - ea1a: 000e c.slli zero,0x3 - ea1c: 5091 li ra,-28 - ea1e: 4006 0x4006 - ea20: 0c22244b 0xc22244b - ea24: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8a88> - ea28: 9f2c 0x9f2c - ea2a: 04cc addi a1,sp,580 - ea2c: 0000 unimp - ea2e: 04dc addi a5,sp,580 - ea30: 0000 unimp - ea32: 0001 nop - ea34: dc5f 0004 e400 0xe4000004dc5f - ea3a: 0004 0x4 - ea3c: 0600 addi s0,sp,768 - ea3e: 7e00 flw fs0,56(a2) - ea40: 0800 addi s0,sp,16 - ea42: 1aff 0x1aff - ea44: e49f 0004 e800 0xe8000004e49f - ea4a: 0004 0x4 - ea4c: 2600 fld fs0,8(a2) - ea4e: 9100 0x9100 - ea50: 0658 addi a4,sp,772 - ea52: 4b40 lw s0,20(a4) - ea54: 2224 fld fs1,64(a2) - ea56: 5491 li s1,-28 - ea58: 4006 0x4006 - ea5a: 9122244b fnmsub.s fs0,ft4,fs2,fs2,rdn - ea5e: 0650 addi a2,sp,772 - ea60: 4b40 lw s0,20(a4) - ea62: 2224 fld fs1,64(a2) - ea64: 030c addi a1,sp,384 - ea66: 0000 unimp - ea68: 2c80 fld fs0,24(s1) - ea6a: 4b40 lw s0,20(a4) - ea6c: 2224 fld fs1,64(a2) - ea6e: 402d c.li zero,11 - ea70: 2d22244b 0x2d22244b - ea74: 009f 0000 0000 0x9f - ea7a: 0000 unimp - ea7c: 1800 addi s0,sp,48 - ea7e: 0005 c.nop 1 - ea80: 0400 addi s0,sp,512 - ea82: 0006 c.slli zero,0x1 - ea84: 0200 addi s0,sp,256 - ea86: 4d00 lw s0,24(a0) - ea88: 009f 0000 0000 0x9f - ea8e: 0000 unimp - ea90: 1800 addi s0,sp,48 - ea92: 0005 c.nop 1 - ea94: 0400 addi s0,sp,512 - ea96: 0006 c.slli zero,0x1 - ea98: 0200 addi s0,sp,256 - ea9a: 3300 fld fs0,32(a4) - ea9c: 009f 0000 0000 0x9f - eaa2: 0000 unimp - eaa4: 1800 addi s0,sp,48 - eaa6: 0005 c.nop 1 - eaa8: 0400 addi s0,sp,512 - eaaa: 0006 c.slli zero,0x1 - eaac: 0200 addi s0,sp,256 - eaae: 3000 fld fs0,32(s0) - eab0: 009f 0000 0000 0x9f - eab6: 0000 unimp - eab8: 1800 addi s0,sp,48 - eaba: 0005 c.nop 1 - eabc: 2000 fld fs0,0(s0) - eabe: 0005 c.nop 1 - eac0: 0200 addi s0,sp,256 - eac2: 3000 fld fs0,32(s0) - eac4: 409f 0005 0400 0x4000005409f - eaca: 0006 c.slli zero,0x1 - eacc: 0200 addi s0,sp,256 - eace: 3400 fld fs0,40(s0) - ead0: 009f 0000 0000 0x9f - ead6: 0000 unimp - ead8: 4400 lw s0,8(s0) - eada: 0000 unimp - eadc: 6400 flw fs0,8(s0) - eade: 0000 unimp - eae0: 0100 addi s0,sp,128 - eae2: 5d00 lw s0,56(a0) - eae4: 0064 addi s1,sp,12 - eae6: 0000 unimp - eae8: 0068 addi a0,sp,12 - eaea: 0000 unimp - eaec: 0008 0x8 - eaee: 6c91 lui s9,0x4 - eaf0: 3106 fld ft2,96(sp) - eaf2: 4124 lw s1,64(a0) - eaf4: 9f25 0x9f25 - eaf6: 0068 addi a0,sp,12 - eaf8: 0000 unimp - eafa: 006c addi a1,sp,12 - eafc: 0000 unimp - eafe: 0008 0x8 - eb00: 6c72 flw fs8,28(sp) - eb02: 3106 fld ft2,96(sp) - eb04: 4124 lw s1,64(a0) - eb06: 9f25 0x9f25 - eb08: 006c addi a1,sp,12 - eb0a: 0000 unimp - eb0c: 0098 addi a4,sp,64 - eb0e: 0000 unimp - eb10: 0001 nop - eb12: 985d andi s0,s0,-9 - eb14: 0000 unimp - eb16: b400 fsd fs0,40(s0) - eb18: 0000 unimp - eb1a: 0800 addi s0,sp,16 - eb1c: 7d00 flw fs0,56(a0) - eb1e: 066c addi a1,sp,780 - eb20: 2431 jal ed2c <_start-0x7fff12d4> - eb22: 2541 jal f1a2 <_start-0x7fff0e5e> - eb24: b49f 0000 0800 0x8000000b49f - eb2a: 0001 nop - eb2c: 0800 addi s0,sp,16 - eb2e: 9100 0x9100 - eb30: 066c addi a1,sp,780 - eb32: 2431 jal ed3e <_start-0x7fff12c2> - eb34: 2541 jal f1b4 <_start-0x7fff0e4c> - eb36: 089f 0001 1c00 0x1c000001089f - eb3c: 0001 nop - eb3e: 0800 addi s0,sp,16 - eb40: 7e00 flw fs0,56(a2) - eb42: 066c addi a1,sp,780 - eb44: 2431 jal ed50 <_start-0x7fff12b0> - eb46: 2541 jal f1c6 <_start-0x7fff0e3a> - eb48: 1c9f 0001 4400 0x440000011c9f - eb4e: 0001 nop - eb50: 0100 addi s0,sp,128 - eb52: 5d00 lw s0,56(a0) - eb54: 0144 addi s1,sp,132 - eb56: 0000 unimp - eb58: 0150 addi a2,sp,132 - eb5a: 0000 unimp - eb5c: 0008 0x8 - eb5e: 6c76 flw fs8,92(sp) - eb60: 3106 fld ft2,96(sp) - eb62: 4124 lw s1,64(a0) - eb64: 9f25 0x9f25 - ... - eb6e: 0058 addi a4,sp,4 - eb70: 0000 unimp - eb72: 0064 addi s1,sp,12 - eb74: 0000 unimp - eb76: 0005 c.nop 1 - eb78: 4b40 lw s0,20(a4) - eb7a: 1f24 addi s1,sp,952 - eb7c: 649f 0000 6c00 0x6c000000649f - eb82: 0000 unimp - eb84: 0100 addi s0,sp,128 - eb86: 5a00 lw s0,48(a2) - eb88: 00d4 addi a3,sp,68 - eb8a: 0000 unimp - eb8c: 00e0 addi s0,sp,76 - eb8e: 0000 unimp - eb90: 0001 nop - eb92: 005a c.slli zero,0x16 - eb94: 0000 unimp - eb96: 0000 unimp - eb98: 0000 unimp - eb9a: 7400 flw fs0,40(s0) - eb9c: 0000 unimp - eb9e: d000 sw s0,32(s0) - eba0: 0000 unimp - eba2: 0200 addi s0,sp,256 - eba4: 3000 fld fs0,32(s0) - eba6: e09f 0000 5000 0x50000000e09f - ebac: 0001 nop - ebae: 0200 addi s0,sp,256 - ebb0: 3000 fld fs0,32(s0) - ebb2: 009f 0000 0000 0x9f - ebb8: 0000 unimp - ebba: 8c00 0x8c00 - ebbc: 0000 unimp - ebbe: 9400 0x9400 - ebc0: 0000 unimp - ebc2: 0600 addi s0,sp,768 - ebc4: 0800 addi s0,sp,16 - ebc6: 7f20 flw fs0,120(a4) - ebc8: 1c00 addi s0,sp,560 - ebca: 949f 0000 9800 0x98000000949f - ebd0: 0000 unimp - ebd2: 0c00 addi s0,sp,528 - ebd4: 0800 addi s0,sp,16 - ebd6: 0a20 addi s0,sp,280 - ebd8: 007d406f j e33de <_start-0x7ff1cc22> - ebdc: 4f1c lw a5,24(a4) - ebde: 1c1a slli s8,s8,0x26 - ebe0: 989f 0000 b400 0xb4000000989f - ebe6: 0000 unimp - ebe8: 1100 addi s0,sp,160 - ebea: 0800 addi s0,sp,16 - ebec: 0a20 addi s0,sp,280 - ebee: 6c7d406f j e3ab4 <_start-0x7ff1c54c> - ebf2: 3106 fld ft2,96(sp) - ebf4: 4124 lw s1,64(a0) - ebf6: 1c25 addi s8,s8,-23 - ebf8: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - ebfc: 00b4 addi a3,sp,72 - ebfe: 0000 unimp - ec00: 00e0 addi s0,sp,76 - ec02: 0000 unimp - ec04: 0011 c.nop 4 - ec06: 2008 fld fa0,0(s0) - ec08: 6f0a flw ft10,128(sp) - ec0a: 9140 0x9140 - ec0c: 066c addi a1,sp,780 - ec0e: 2431 jal ee1a <_start-0x7fff11e6> - ec10: 2541 jal f290 <_start-0x7fff0d70> - ec12: 4f1c lw a5,24(a4) - ec14: 1c1a slli s8,s8,0x26 - ec16: e09f 0000 1400 0x14000000e09f - ec1c: 0001 nop - ec1e: 0600 addi s0,sp,768 - ec20: 0800 addi s0,sp,16 - ec22: 7f20 flw fs0,120(a4) - ec24: 1c00 addi s0,sp,560 - ec26: 149f 0001 1c00 0x1c000001149f - ec2c: 0001 nop - ec2e: 1100 addi s0,sp,160 - ec30: 0800 addi s0,sp,16 - ec32: 0a20 addi s0,sp,280 - ec34: 6c7e406f j f3afa <_start-0x7ff0c506> - ec38: 3106 fld ft2,96(sp) - ec3a: 4124 lw s1,64(a0) - ec3c: 1c25 addi s8,s8,-23 - ec3e: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - ec42: 011c addi a5,sp,128 - ec44: 0000 unimp - ec46: 0150 addi a2,sp,132 - ec48: 0000 unimp - ec4a: 0006 c.slli zero,0x1 - ec4c: 2008 fld fa0,0(s0) - ec4e: 007f 0x7f - ec50: 9f1c 0x9f1c - ... - ec5a: 008c addi a1,sp,64 - ec5c: 0000 unimp - ec5e: 0094 addi a3,sp,64 - ec60: 0000 unimp - ec62: 0001 nop - ec64: 945f 0000 9800 0x98000000945f - ec6a: 0000 unimp - ec6c: 0900 addi s0,sp,144 - ec6e: 0a00 addi s0,sp,272 - ec70: 007d406f j e3476 <_start-0x7ff1cb8a> - ec74: 4f1c lw a5,24(a4) - ec76: 9f1a add t5,t5,t1 - ec78: 0098 addi a4,sp,64 - ec7a: 0000 unimp - ec7c: 00b4 addi a3,sp,72 - ec7e: 0000 unimp - ec80: 000e c.slli zero,0x3 - ec82: 6f0a flw ft10,128(sp) - ec84: 7d40 flw fs0,60(a0) - ec86: 066c addi a1,sp,780 - ec88: 2431 jal ee94 <_start-0x7fff116c> - ec8a: 2541 jal f30a <_start-0x7fff0cf6> - ec8c: 4f1c lw a5,24(a4) - ec8e: 9f1a add t5,t5,t1 - ec90: 00b4 addi a3,sp,72 - ec92: 0000 unimp - ec94: 00e0 addi s0,sp,76 - ec96: 0000 unimp - ec98: 000e c.slli zero,0x3 - ec9a: 6f0a flw ft10,128(sp) - ec9c: 9140 0x9140 - ec9e: 066c addi a1,sp,780 - eca0: 2431 jal eeac <_start-0x7fff1154> - eca2: 2541 jal f322 <_start-0x7fff0cde> - eca4: 4f1c lw a5,24(a4) - eca6: 9f1a add t5,t5,t1 - eca8: 00e0 addi s0,sp,76 - ecaa: 0000 unimp - ecac: 0114 addi a3,sp,128 - ecae: 0000 unimp - ecb0: 0001 nop - ecb2: 145f 0001 1c00 0x1c000001145f - ecb8: 0001 nop - ecba: 0e00 addi s0,sp,784 - ecbc: 0a00 addi s0,sp,272 - ecbe: 6c7e406f j f3b84 <_start-0x7ff0c47c> - ecc2: 3106 fld ft2,96(sp) - ecc4: 4124 lw s1,64(a0) - ecc6: 1c25 addi s8,s8,-23 - ecc8: 1c9f1a4f 0x1c9f1a4f - eccc: 0001 nop - ecce: 5000 lw s0,32(s0) - ecd0: 0001 nop - ecd2: 0100 addi s0,sp,128 - ecd4: 5f00 lw s0,56(a4) - ... - ecde: 0088 addi a0,sp,64 - ece0: 0000 unimp - ece2: 00b4 addi a3,sp,72 - ece4: 0000 unimp - ece6: 0001 nop - ece8: b45e fsd fs7,40(sp) - ecea: 0000 unimp - ecec: 0800 addi s0,sp,16 - ecee: 0001 nop - ecf0: 0e00 addi s0,sp,784 - ecf2: 0a00 addi s0,sp,272 - ecf4: 6c91406f j 23bbc <_start-0x7ffdc444> - ecf8: 3106 fld ft2,96(sp) - ecfa: 4124 lw s1,64(a0) - ecfc: 1c25 addi s8,s8,-23 - ecfe: 2635 jal f02a <_start-0x7fff0fd6> - ed00: 089f 0001 1c00 0x1c000001089f - ed06: 0001 nop - ed08: 0e00 addi s0,sp,784 - ed0a: 0a00 addi s0,sp,272 - ed0c: 6c7e406f j f3bd2 <_start-0x7ff0c42e> - ed10: 3106 fld ft2,96(sp) - ed12: 4124 lw s1,64(a0) - ed14: 1c25 addi s8,s8,-23 - ed16: 2635 jal f042 <_start-0x7fff0fbe> - ed18: 1c9f 0001 3800 0x380000011c9f - ed1e: 0001 nop - ed20: 0100 addi s0,sp,128 - ed22: 5e00 lw s0,56(a2) - ed24: 0138 addi a4,sp,136 - ed26: 0000 unimp - ed28: 0144 addi s1,sp,132 - ed2a: 0000 unimp - ed2c: 0009 c.nop 2 - ed2e: 6f0a flw ft10,128(sp) - ed30: 7d40 flw fs0,60(a0) - ed32: 1c00 addi s0,sp,560 - ed34: 2635 jal f060 <_start-0x7fff0fa0> - ed36: 449f 0001 5000 0x50000001449f - ed3c: 0001 nop - ed3e: 0e00 addi s0,sp,784 - ed40: 0a00 addi s0,sp,272 - ed42: 6c76406f j 73c08 <_start-0x7ff8c3f8> - ed46: 3106 fld ft2,96(sp) - ed48: 4124 lw s1,64(a0) - ed4a: 1c25 addi s8,s8,-23 - ed4c: 2635 jal f078 <_start-0x7fff0f88> - ed4e: 009f 0000 0000 0x9f - ed54: 0000 unimp - ed56: 8c00 0x8c00 - ed58: 0000 unimp - ed5a: a800 fsd fs0,16(s0) - ed5c: 0000 unimp - ed5e: 0200 addi s0,sp,256 - ed60: 3000 fld fs0,32(s0) - ed62: a89f 0000 b400 0xb4000000a89f - ed68: 0000 unimp - ed6a: 0200 addi s0,sp,256 - ed6c: 3100 fld fs0,32(a0) - ed6e: b89f 0000 e000 0xe0000000b89f - ed74: 0000 unimp - ed76: 0100 addi s0,sp,128 - ed78: 5c00 lw s0,56(s0) - ed7a: 00e0 addi s0,sp,76 - ed7c: 0000 unimp - ed7e: 00e4 addi s1,sp,76 - ed80: 0000 unimp - ed82: 0001 nop - ed84: f85d bnez s0,ed3a <_start-0x7fff12c6> - ed86: 0000 unimp - ed88: fc00 fsw fs0,56(s0) - ed8a: 0000 unimp - ed8c: 0200 addi s0,sp,256 - ed8e: 3100 fld fs0,32(a0) - ed90: fc9f 0000 0400 0x4000000fc9f - ed96: 0001 nop - ed98: 0100 addi s0,sp,128 - ed9a: 5d00 lw s0,56(a0) - ed9c: 0104 addi s1,sp,128 - ed9e: 0000 unimp - eda0: 011c addi a5,sp,128 - eda2: 0000 unimp - eda4: 0001 nop - eda6: 1c5c addi a5,sp,564 - eda8: 0001 nop - edaa: 5000 lw s0,32(s0) - edac: 0001 nop - edae: 0200 addi s0,sp,256 - edb0: 3000 fld fs0,32(s0) - edb2: 009f 0000 0000 0x9f - edb8: 0000 unimp - edba: 8c00 0x8c00 - edbc: 0000 unimp - edbe: b800 fsd fs0,48(s0) - edc0: 0000 unimp - edc2: 0200 addi s0,sp,256 - edc4: 3000 fld fs0,32(s0) - edc6: e09f 0000 5000 0x50000000e09f - edcc: 0001 nop - edce: 0200 addi s0,sp,256 - edd0: 3000 fld fs0,32(s0) - edd2: 009f 0000 0000 0x9f - edd8: 0000 unimp - edda: 0000 unimp - eddc: 0000 unimp - edde: 3300 fld fs0,32(a4) - ede0: 0000 unimp - ede2: 0100 addi s0,sp,128 - ede4: 5b00 lw s0,48(a4) - ede6: 00000033 add zero,zero,zero - edea: 0170 addi a2,sp,140 - edec: 0000 unimp - edee: 0004 0x4 - edf0: 9f5b01f3 0x9f5b01f3 - edf4: 0170 addi a2,sp,140 - edf6: 0000 unimp - edf8: 0188 addi a0,sp,192 - edfa: 0000 unimp - edfc: 0001 nop - edfe: 0000005b 0x5b - ee02: 0000 unimp - ee04: 0000 unimp - ee06: 3000 fld fs0,32(s0) - ee08: 0000 unimp - ee0a: 3400 fld fs0,40(s0) - ee0c: 0001 nop - ee0e: 0100 addi s0,sp,128 - ee10: 6200 flw fs0,0(a2) - ee12: 0170 addi a2,sp,140 - ee14: 0000 unimp - ee16: 0188 addi a0,sp,192 - ee18: 0000 unimp - ee1a: 0002 c.slli64 zero - ee1c: 9f30 0x9f30 - ... - ee26: 0040 addi s0,sp,4 - ee28: 0000 unimp - ee2a: 0108 addi a0,sp,128 - ee2c: 0000 unimp - ee2e: 0001 nop - ee30: 0001705b 0x1705b - ee34: 8800 0x8800 - ee36: 0001 nop - ee38: 0200 addi s0,sp,256 - ee3a: 3000 fld fs0,32(s0) - ee3c: 009f 0000 0000 0x9f - ee42: 0000 unimp - ee44: 5400 lw s0,40(s0) - ee46: 0001 nop - ee48: 6c00 flw fs0,24(s0) - ee4a: 0001 nop - ee4c: 0e00 addi s0,sp,784 - ee4e: 9100 0x9100 - ee50: 9360 0x9360 - ee52: 9104 0x9104 - ee54: 9364 0x9364 - ee56: 5f04 lw s1,56(a4) - ee58: 935b0493 addi s1,s6,-1739 # fffea935 <__BSS_END__+0x7ffd3bbd> - ee5c: 6c04 flw fs1,24(s0) - ee5e: 0001 nop - ee60: 7000 flw fs0,32(s0) - ee62: 0001 nop - ee64: 0e00 addi s0,sp,784 - ee66: 7200 flw fs0,32(a2) - ee68: 9360 0x9360 - ee6a: 7204 flw fs1,32(a2) - ee6c: 9364 0x9364 - ee6e: 5f04 lw s1,56(a4) - ee70: 935b0493 addi s1,s6,-1739 - ee74: 0004 0x4 - ee76: 0000 unimp - ee78: 0000 unimp - ee7a: 0000 unimp - ee7c: 1c00 addi s0,sp,560 - ee7e: 0000 unimp - ee80: 3000 fld fs0,32(s0) - ee82: 0000 unimp - ee84: 0100 addi s0,sp,128 - ee86: 5b00 lw s0,48(a4) - ee88: 0030 addi a2,sp,8 - ee8a: 0000 unimp - ee8c: 0090 addi a2,sp,64 - ee8e: 0000 unimp - ee90: 0001 nop - ee92: 9058 0x9058 - ee94: 0000 unimp - ee96: 9400 0x9400 - ee98: 0000 unimp - ee9a: 0200 addi s0,sp,256 - ee9c: 9100 0x9100 - ee9e: 9460 0x9460 - eea0: 0000 unimp - eea2: 9800 0x9800 - eea4: 0000 unimp - eea6: 1000 addi s0,sp,32 - eea8: f300 fsw fs0,32(a4) - eeaa: 5b01 li s6,-32 - eeac: 01f3264f fnmadd.s fa2,ft6,ft11,ft0,rdn - eeb0: 01f3275b 0x1f3275b - eeb4: 1c264f5b 0x1c264f5b - eeb8: 989f 0000 e400 0xe4000000989f - eebe: 0000 unimp - eec0: 0100 addi s0,sp,128 - eec2: 5800 lw s0,48(s0) - eec4: 00e4 addi s1,sp,76 - eec6: 0000 unimp - eec8: 0100 addi s0,sp,128 - eeca: 0000 unimp - eecc: 0010 0x10 - eece: 4f5b01f3 0x4f5b01f3 - eed2: f326 fsw fs1,164(sp) - eed4: 5b01 li s6,-32 - eed6: 5b01f327 0x5b01f327 - eeda: 9f1c264f fnmadd.q fa2,fs8,fa7,fs3,rdn - ... - eee6: 0034 addi a3,sp,8 - eee8: 0000 unimp - eeea: 0044 addi s1,sp,4 - eeec: 0000 unimp - eeee: 0001 nop - eef0: 445a lw s0,148(sp) - eef2: 0000 unimp - eef4: 0000 unimp - eef6: 0001 nop - eef8: 0400 addi s0,sp,512 - eefa: 7a00 flw fs0,48(a2) - eefc: 009f7faf vamoadde.v zero,v9,(t5),v31,v0.t - ef00: 0000 unimp - ef02: 0000 unimp - ef04: 0000 unimp - ef06: 5800 lw s0,48(s0) - ef08: 0000 unimp - ef0a: 9c00 0x9c00 - ef0c: 0000 unimp - ef0e: 0100 addi s0,sp,128 - ef10: 5d00 lw s0,56(a0) - ef12: 009c addi a5,sp,64 - ef14: 0000 unimp - ef16: 0100 addi s0,sp,128 - ef18: 0000 unimp - ef1a: 0005 c.nop 1 - ef1c: 007a c.slli zero,0x1e - ef1e: 009f1a4f fnmadd.s fs4,ft10,fs1,ft0,rtz - ef22: 0000 unimp - ef24: 0000 unimp - ef26: 0000 unimp - ef28: 5800 lw s0,48(s0) - ef2a: 0000 unimp - ef2c: 7000 flw fs0,32(s0) - ef2e: 0000 unimp - ef30: 0600 addi s0,sp,768 - ef32: 0800 addi s0,sp,16 - ef34: 7d20 flw fs0,120(a0) - ef36: 1c00 addi s0,sp,560 - ef38: 709f 0000 7400 0x74000000709f - ef3e: 0000 unimp - ef40: 0100 addi s0,sp,128 - ef42: 5f00 lw s0,56(a4) - ef44: 0074 addi a3,sp,12 - ef46: 0000 unimp - ef48: 009c addi a5,sp,64 - ef4a: 0000 unimp - ef4c: 0006 c.slli zero,0x1 - ef4e: 2008 fld fa0,0(s0) - ef50: 007d c.nop 31 - ef52: 9f1c 0x9f1c - ef54: 009c addi a5,sp,64 - ef56: 0000 unimp - ef58: 0100 addi s0,sp,128 - ef5a: 0000 unimp - ef5c: 0008 0x8 - ef5e: 2008 fld fa0,0(s0) - ef60: 007a c.slli zero,0x1e - ef62: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - ... - ef6e: 0054 addi a3,sp,4 - ef70: 0000 unimp - ef72: 0100 addi s0,sp,128 - ef74: 0000 unimp - ef76: 0005 c.nop 1 - ef78: 007a c.slli zero,0x1e - ef7a: 2635 jal f2a6 <_start-0x7fff0d5a> - ef7c: 009f 0000 0000 0x9f - ef82: 0000 unimp - ef84: 5c00 lw s0,56(s0) - ef86: 0000 unimp - ef88: 7800 flw fs0,48(s0) - ef8a: 0000 unimp - ef8c: 0200 addi s0,sp,256 - ef8e: 3300 fld fs0,32(a4) - ef90: 789f 0000 7c00 0x7c000000789f - ef96: 0000 unimp - ef98: 0200 addi s0,sp,256 - ef9a: 3200 fld fs0,32(a2) - ef9c: 809f 0000 9800 0x98000000809f - efa2: 0000 unimp - efa4: 0100 addi s0,sp,128 - efa6: 5e00 lw s0,56(a2) - efa8: 009c addi a5,sp,64 - efaa: 0000 unimp - efac: 00bc addi a5,sp,72 - efae: 0000 unimp - efb0: 0002 c.slli64 zero - efb2: 00bc9f33 sll t5,s9,a1 - efb6: 0000 unimp - efb8: 00e4 addi s1,sp,76 - efba: 0000 unimp - efbc: 0002 c.slli64 zero - efbe: 9f32 add t5,t5,a2 - efc0: 00e8 addi a0,sp,76 - efc2: 0000 unimp - efc4: 0100 addi s0,sp,128 - efc6: 0000 unimp - efc8: 0001 nop - efca: 005e c.slli zero,0x17 - ... - efd4: 0000 unimp - efd6: 6400 flw fs0,8(s0) - efd8: 0000 unimp - efda: 0600 addi s0,sp,768 - efdc: 5b00 lw s0,48(a4) - efde: 935c0493 addi s1,s8,-1739 # fffe8935 <__BSS_END__+0x7ffd1bbd> - efe2: 6404 flw fs1,8(s0) - efe4: 0000 unimp - efe6: e000 fsw fs0,0(s0) - efe8: 0000 unimp - efea: 0600 addi s0,sp,768 - efec: f300 fsw fs0,32(a4) - efee: 250bf503 0x250bf503 - eff2: e09f 0000 f700 0xf7000000e09f - eff8: 0000 unimp - effa: 0600 addi s0,sp,768 - effc: 5b00 lw s0,48(a4) - effe: 935c0493 addi s1,s8,-1739 - f002: f704 fsw fs1,40(a4) - f004: 0000 unimp - f006: 4800 lw s0,16(s0) - f008: 0001 nop - f00a: 0600 addi s0,sp,768 - f00c: f300 fsw fs0,32(a4) - f00e: 250bf503 0x250bf503 - f012: 489f 0001 4b00 0x4b000001489f - f018: 0001 nop - f01a: 0600 addi s0,sp,768 - f01c: 5b00 lw s0,48(a4) - f01e: 935c0493 addi s1,s8,-1739 - f022: 4b04 lw s1,16(a4) - f024: 0001 nop - f026: d000 sw s0,32(s0) - f028: 0001 nop - f02a: 0600 addi s0,sp,768 - f02c: f300 fsw fs0,32(a4) - f02e: 250bf503 0x250bf503 - f032: d09f 0001 f400 0xf4000001d09f - f038: 0001 nop - f03a: 0600 addi s0,sp,768 - f03c: 5b00 lw s0,48(a4) - f03e: 935c0493 addi s1,s8,-1739 - f042: f404 fsw fs1,40(s0) - f044: 0001 nop - f046: 0c00 addi s0,sp,528 - f048: 0002 c.slli64 zero - f04a: 0600 addi s0,sp,768 - f04c: f300 fsw fs0,32(a4) - f04e: 250bf503 0x250bf503 - f052: 009f 0000 0000 0x9f - f058: 0000 unimp - f05a: 4000 lw s0,0(s0) - f05c: 0000 unimp - f05e: a800 fsd fs0,16(s0) - f060: 0000 unimp - f062: 0600 addi s0,sp,768 - f064: 7800 flw fs0,48(s0) - f066: 0800 addi s0,sp,16 - f068: 1aff 0x1aff - f06a: e09f 0000 0c00 0xc000000e09f - f070: 0002 c.slli64 zero - f072: 0600 addi s0,sp,768 - f074: 7800 flw fs0,48(s0) - f076: 0800 addi s0,sp,16 - f078: 1aff 0x1aff - f07a: 009f 0000 0000 0x9f - f080: 0000 unimp - f082: 1400 addi s0,sp,544 - f084: 0000 unimp - f086: 5400 lw s0,40(s0) - f088: 0000 unimp - f08a: 0100 addi s0,sp,128 - f08c: 5f00 lw s0,56(a4) - f08e: 0054 addi a3,sp,4 - f090: 0000 unimp - f092: 0074 addi a3,sp,12 - f094: 0000 unimp - f096: 0005 c.nop 1 - f098: 807f 0x807f - f09a: 7f88 flw fa0,56(a5) - f09c: e09f 0000 f700 0xf7000000e09f - f0a2: 0000 unimp - f0a4: 0100 addi s0,sp,128 - f0a6: 5f00 lw s0,56(a4) - f0a8: 0148 addi a0,sp,132 - f0aa: 0000 unimp - f0ac: 0000014b fnmsub.s ft2,ft0,ft0,ft0,rne - f0b0: 0001 nop - f0b2: d05f 0001 d400 0xd4000001d05f - f0b8: 0001 nop - f0ba: 0100 addi s0,sp,128 - f0bc: 5f00 lw s0,56(a4) - f0be: 01d4 addi a3,sp,196 - f0c0: 0000 unimp - f0c2: 020c addi a1,sp,256 - f0c4: 0000 unimp - f0c6: 0009 c.nop 2 - f0c8: 007c addi a5,sp,12 - f0ca: 2544 fld fs1,136(a0) - f0cc: ff0a fsw ft2,188(sp) - f0ce: 009f1a07 0x9f1a07 - ... - f0da: 0000 unimp - f0dc: 6400 flw fs0,8(s0) - f0de: 0000 unimp - f0e0: 0100 addi s0,sp,128 - f0e2: 5b00 lw s0,48(a4) - f0e4: 0064 addi s1,sp,12 - f0e6: 0000 unimp - f0e8: 0074 addi a3,sp,12 - f0ea: 0000 unimp - f0ec: 0002 c.slli64 zero - f0ee: 6091 lui ra,0x4 - f0f0: 00e0 addi s0,sp,76 - f0f2: 0000 unimp - f0f4: 000000f7 0xf7 - f0f8: 0001 nop - f0fa: 0001485b 0x1485b - f0fe: 4b00 lw s0,16(a4) - f100: 0001 nop - f102: 0100 addi s0,sp,128 - f104: 5b00 lw s0,48(a4) - f106: 01d0 addi a2,sp,196 - f108: 0000 unimp - f10a: 01f4 addi a3,sp,204 - f10c: 0000 unimp - f10e: 0001 nop - f110: 0001f45b 0x1f45b - f114: 0000 unimp - f116: 0002 c.slli64 zero - f118: 0200 addi s0,sp,256 - f11a: 9100 0x9100 - f11c: 0060 addi s0,sp,12 - f11e: 0000 unimp - f120: 0000 unimp - f122: 0000 unimp - f124: 1400 addi s0,sp,544 - f126: 0000 unimp - f128: 5c00 lw s0,56(s0) - f12a: 0000 unimp - f12c: 0100 addi s0,sp,128 - f12e: 5e00 lw s0,56(a2) - f130: 005c addi a5,sp,4 - f132: 0000 unimp - f134: 0070 addi a2,sp,12 - f136: 0000 unimp - f138: 0002 c.slli64 zero - f13a: 6491 lui s1,0x4 - f13c: 0070 addi a2,sp,12 - f13e: 0000 unimp - f140: 0074 addi a3,sp,12 - f142: 0000 unimp - f144: 007c0007 0x7c0007 - f148: 243c fld fa5,72(s0) - f14a: 253c fld fa5,72(a0) - f14c: e09f 0000 f700 0xf7000000e09f - f152: 0000 unimp - f154: 0100 addi s0,sp,128 - f156: 5e00 lw s0,56(a2) - f158: 0148 addi a0,sp,132 - f15a: 0000 unimp - f15c: 0000014b fnmsub.s ft2,ft0,ft0,ft0,rne - f160: 0001 nop - f162: d05e sw s7,32(sp) - f164: 0001 nop - f166: ec00 fsw fs0,24(s0) - f168: 0001 nop - f16a: 0100 addi s0,sp,128 - f16c: 5e00 lw s0,56(a2) - f16e: 01ec addi a1,sp,204 - f170: 0000 unimp - f172: 01fc addi a5,sp,204 - f174: 0000 unimp - f176: 0002 c.slli64 zero - f178: 6491 lui s1,0x4 - f17a: 01fc addi a5,sp,204 - f17c: 0000 unimp - f17e: 020c addi a1,sp,256 - f180: 0000 unimp - f182: 007c0007 0x7c0007 - f186: 243c fld fa5,72(s0) - f188: 253c fld fa5,72(a0) - f18a: 009f 0000 0000 0x9f - f190: 0000 unimp - f192: 5400 lw s0,40(s0) - f194: 0000 unimp - f196: 7c00 flw fs0,56(s0) - f198: 0000 unimp - f19a: 0100 addi s0,sp,128 - f19c: 5f00 lw s0,56(a4) - f19e: 01a8 addi a0,sp,200 - f1a0: 0000 unimp - f1a2: 01ac addi a1,sp,200 - f1a4: 0000 unimp - f1a6: 0001 nop - f1a8: d05f 0001 0c00 0xc000001d05f - f1ae: 0002 c.slli64 zero - f1b0: 0400 addi s0,sp,512 - f1b2: 0a00 addi s0,sp,272 - f1b4: 7fff 0x7fff - f1b6: 009f 0000 0000 0x9f - f1bc: 0000 unimp - f1be: b800 fsd fs0,48(s0) - f1c0: 0000 unimp - f1c2: c000 sw s0,0(s0) - f1c4: 0000 unimp - f1c6: 0e00 addi s0,sp,784 - f1c8: 9100 0x9100 - f1ca: 9360 0x9360 - f1cc: 5e04 lw s1,56(a2) - f1ce: 68910493 addi s1,sp,1673 - f1d2: 935f0493 addi s1,t5,-1739 - f1d6: c004 sw s1,0(s0) - f1d8: 0000 unimp - f1da: dc00 sw s0,56(s0) - f1dc: 0000 unimp - f1de: 0f00 addi s0,sp,912 - f1e0: 9100 0x9100 - f1e2: 9360 0x9360 - f1e4: 9104 0x9104 - f1e6: 9364 0x9364 - f1e8: 9104 0x9104 - f1ea: 9368 0x9368 - f1ec: 5f04 lw s1,56(a4) - f1ee: 00dc0493 addi s1,s8,13 - f1f2: 0000 unimp - f1f4: 00e0 addi s0,sp,76 - f1f6: 0000 unimp - f1f8: 000e c.slli zero,0x3 - f1fa: 6072 flw ft0,28(sp) - f1fc: 64720493 addi s1,tp,1607 # 647 <_start-0x7ffff9b9> - f200: 935e0493 addi s1,t3,-1739 - f204: 5f04 lw s1,56(a4) - f206: 00000493 li s1,0 - f20a: 0000 unimp - f20c: 0000 unimp - f20e: 0000 unimp - f210: 0054 addi a3,sp,4 - f212: 0000 unimp - f214: 0074 addi a3,sp,12 - f216: 0000 unimp - f218: 0002 c.slli64 zero - f21a: 9f4c 0x9f4c - ... - f224: 0054 addi a3,sp,4 - f226: 0000 unimp - f228: 0074 addi a3,sp,12 - f22a: 0000 unimp - f22c: 0002 c.slli64 zero - f22e: 9f34 0x9f34 - ... - f238: 0054 addi a3,sp,4 - f23a: 0000 unimp - f23c: 0074 addi a3,sp,12 - f23e: 0000 unimp - f240: 0002 c.slli64 zero - f242: 9f31 0x9f31 - ... - f24c: 0054 addi a3,sp,4 - f24e: 0000 unimp - f250: 0068 addi a0,sp,12 - f252: 0000 unimp - f254: 0002 c.slli64 zero - f256: 00689f33 sll t5,a7,t1 - f25a: 0000 unimp - f25c: 006c addi a1,sp,12 - f25e: 0000 unimp - f260: 0002 c.slli64 zero - f262: 9f32 add t5,t5,a2 - f264: 006c addi a1,sp,12 - f266: 0000 unimp - f268: 0074 addi a3,sp,12 - f26a: 0000 unimp - f26c: 0002 c.slli64 zero - f26e: 9f30 0x9f30 - ... - f278: 00f8 addi a4,sp,76 - f27a: 0000 unimp - f27c: 0148 addi a0,sp,132 - f27e: 0000 unimp - f280: 0001 nop - f282: 4c5a lw s8,148(sp) - f284: 0001 nop - f286: d000 sw s0,32(s0) - f288: 0001 nop - f28a: 0100 addi s0,sp,128 - f28c: 5a00 lw s0,48(a2) - ... - f296: 0104 addi s1,sp,128 - f298: 0000 unimp - f29a: 0140 addi s0,sp,132 - f29c: 0000 unimp - f29e: 0001 nop - f2a0: 405c lw a5,4(s0) - f2a2: 0001 nop - f2a4: 4800 lw s0,16(s0) - f2a6: 0001 nop - f2a8: 0500 addi s0,sp,640 - f2aa: 7a00 flw fs0,48(a2) - f2ac: 4f31 li t5,12 - f2ae: 9f1a add t5,t5,t1 - f2b0: 0154 addi a3,sp,132 - f2b2: 0000 unimp - f2b4: 0158 addi a4,sp,132 - f2b6: 0000 unimp - f2b8: 0001 nop - f2ba: 585c lw a5,52(s0) - f2bc: 0001 nop - f2be: ac00 fsd fs0,24(s0) - f2c0: 0001 nop - f2c2: 0500 addi s0,sp,640 - f2c4: 7a00 flw fs0,48(a2) - f2c6: 4f31 li t5,12 - f2c8: 9f1a add t5,t5,t1 - f2ca: 01ac addi a1,sp,200 - f2cc: 0000 unimp - f2ce: 01d0 addi a2,sp,196 - f2d0: 0000 unimp - f2d2: 0001 nop - f2d4: 005c addi a5,sp,4 - f2d6: 0000 unimp - f2d8: 0000 unimp - f2da: 0000 unimp - f2dc: 0400 addi s0,sp,512 - f2de: 0001 nop - f2e0: 2000 fld fs0,0(s0) - f2e2: 0001 nop - f2e4: 0600 addi s0,sp,768 - f2e6: 0800 addi s0,sp,16 - f2e8: 7c20 flw fs0,120(s0) - f2ea: 1c00 addi s0,sp,560 - f2ec: 209f 0001 3000 0x30000001209f - f2f2: 0001 nop - f2f4: 0100 addi s0,sp,128 - f2f6: 5f00 lw s0,56(a4) - f2f8: 0130 addi a2,sp,136 - f2fa: 0000 unimp - f2fc: 0140 addi s0,sp,132 - f2fe: 0000 unimp - f300: 0006 c.slli zero,0x1 - f302: 2008 fld fa0,0(s0) - f304: 007c addi a5,sp,12 - f306: 9f1c 0x9f1c - f308: 0140 addi s0,sp,132 - f30a: 0000 unimp - f30c: 0148 addi a0,sp,132 - f30e: 0000 unimp - f310: 0008 0x8 - f312: 2008 fld fa0,0(s0) - f314: 317a fld ft2,440(sp) - f316: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - f31a: 0154 addi a3,sp,132 - f31c: 0000 unimp - f31e: 0158 addi a4,sp,132 - f320: 0000 unimp - f322: 0006 c.slli zero,0x1 - f324: 2008 fld fa0,0(s0) - f326: 007c addi a5,sp,12 - f328: 9f1c 0x9f1c - f32a: 0158 addi a4,sp,132 - f32c: 0000 unimp - f32e: 01ac addi a1,sp,200 - f330: 0000 unimp - f332: 0008 0x8 - f334: 2008 fld fa0,0(s0) - f336: 317a fld ft2,440(sp) - f338: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - f33c: 01ac addi a1,sp,200 - f33e: 0000 unimp - f340: 01d0 addi a2,sp,196 - f342: 0000 unimp - f344: 0001 nop - f346: 005f 0000 0000 0x5f - f34c: 0000 unimp - f34e: 0000 unimp - f350: 0001 nop - f352: 3c00 fld fs0,56(s0) - f354: 0001 nop - f356: 0100 addi s0,sp,128 - f358: 5e00 lw s0,56(a2) - f35a: 013c addi a5,sp,136 - f35c: 0000 unimp - f35e: 0148 addi a0,sp,132 - f360: 0000 unimp - f362: 017e0003 lb zero,23(t3) - f366: 549f 0001 8000 0x80000001549f - f36c: 0001 nop - f36e: 0100 addi s0,sp,128 - f370: 5e00 lw s0,56(a2) - f372: 0180 addi s0,sp,192 - f374: 0000 unimp - f376: 01ac addi a1,sp,200 - f378: 0000 unimp - f37a: 0005 c.nop 1 - f37c: 317a fld ft2,440(sp) - f37e: 2635 jal f6aa <_start-0x7fff0956> - f380: ac9f 0001 d000 0xd0000001ac9f - f386: 0001 nop - f388: 0100 addi s0,sp,128 - f38a: 5e00 lw s0,56(a2) - ... - f394: 013c addi a5,sp,136 - f396: 0000 unimp - f398: 0148 addi a0,sp,132 - f39a: 0000 unimp - f39c: 0001 nop - f39e: 645e flw fs0,212(sp) - f3a0: 0001 nop - f3a2: 8000 0x8000 - f3a4: 0001 nop - f3a6: 0100 addi s0,sp,128 - f3a8: 5f00 lw s0,56(a4) - f3aa: 0184 addi s1,sp,192 - f3ac: 0000 unimp - f3ae: 01ac addi a1,sp,200 - f3b0: 0000 unimp - f3b2: 0001 nop - f3b4: 005e c.slli zero,0x17 - f3b6: 0000 unimp - f3b8: 0000 unimp - f3ba: 0000 unimp - f3bc: d800 sw s0,48(s0) - f3be: 0001 nop - f3c0: e800 fsw fs0,16(s0) - f3c2: 0001 nop - f3c4: 0200 addi s0,sp,256 - f3c6: 3200 fld fs0,32(a2) - f3c8: e89f 0001 0000 0x1e89f - f3ce: 0002 c.slli64 zero - f3d0: 0200 addi s0,sp,256 - f3d2: 3000 fld fs0,32(s0) - f3d4: 009f 0002 0400 0x4000002009f - f3da: 0002 c.slli64 zero - f3dc: 0300 addi s0,sp,384 - f3de: 0900 addi s0,sp,144 - f3e0: 9fff 0x9fff - ... - f3ee: 00ec addi a1,sp,76 - f3f0: 0000 unimp - f3f2: 0002 c.slli64 zero - f3f4: 9f30 0x9f30 - f3f6: 0114 addi a3,sp,128 - f3f8: 0000 unimp - f3fa: 02a4 addi s1,sp,328 - f3fc: 0000 unimp - f3fe: 0002 c.slli64 zero - f400: 9f30 0x9f30 - f402: 0320 addi s0,sp,392 - f404: 0000 unimp - f406: 0328 addi a0,sp,392 - f408: 0000 unimp - f40a: 0002 c.slli64 zero - f40c: 9f30 0x9f30 - ... - f416: 0048 addi a0,sp,4 - f418: 0000 unimp - f41a: 02f4 addi a3,sp,332 - f41c: 0000 unimp - f41e: 0001 nop - f420: 0002f45b 0x2f45b - f424: 1c00 addi s0,sp,560 - f426: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - f42a: 9100 0x9100 - f42c: 066c addi a1,sp,780 - f42e: 1c9f254f 0x1c9f254f - f432: 20000003 lb zero,512(zero) # 200 <_start-0x7ffffe00> - f436: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> - f43a: 7200 flw fs0,32(a2) - f43c: 066c addi a1,sp,780 - f43e: 209f254f fnmadd.s fa0,ft10,fs1,ft4,rdn - f442: 34000003 lb zero,832(zero) # 340 <_start-0x7ffffcc0> - f446: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - f44a: 5b00 lw s0,48(a4) - ... - f454: 0044 addi s1,sp,4 - f456: 0000 unimp - f458: 009c addi a5,sp,64 - f45a: 0000 unimp - f45c: 0001 nop - f45e: 9c5e add s8,s8,s7 - f460: 0000 unimp - f462: e400 fsw fs0,8(s0) - f464: 0000 unimp - f466: 0500 addi s0,sp,640 - f468: 7e00 flw fs0,56(a2) - f46a: f880 fsw fs0,48(s1) - f46c: 9f00 0x9f00 - f46e: 00e4 addi s1,sp,76 - f470: 0000 unimp - f472: 01c4 addi s1,sp,196 - f474: 0000 unimp - f476: 0008 0x8 - f478: 6c91 lui s9,0x4 - f47a: 3106 fld ft2,96(sp) - f47c: 4124 lw s1,64(a0) - f47e: 9f25 0x9f25 - f480: 01c4 addi s1,sp,196 - f482: 0000 unimp - f484: 01c8 addi a0,sp,196 - f486: 0000 unimp - f488: 0008 0x8 - f48a: 6c7f 0x6c7f - f48c: 3106 fld ft2,96(sp) - f48e: 4124 lw s1,64(a0) - f490: 9f25 0x9f25 - f492: 01c8 addi a0,sp,196 - f494: 0000 unimp - f496: 01f8 addi a4,sp,204 - f498: 0000 unimp - f49a: 0008 0x8 - f49c: 6c91 lui s9,0x4 - f49e: 3106 fld ft2,96(sp) - f4a0: 4124 lw s1,64(a0) - f4a2: 9f25 0x9f25 - f4a4: 01f8 addi a4,sp,204 - f4a6: 0000 unimp - f4a8: 0204 addi s1,sp,256 - f4aa: 0000 unimp - f4ac: 0008 0x8 - f4ae: 6c7d lui s8,0x1f - f4b0: 3106 fld ft2,96(sp) - f4b2: 4124 lw s1,64(a0) - f4b4: 9f25 0x9f25 - f4b6: 0204 addi s1,sp,256 - f4b8: 0000 unimp - f4ba: 0240 addi s0,sp,260 - f4bc: 0000 unimp - f4be: 0008 0x8 - f4c0: 6c91 lui s9,0x4 - f4c2: 3106 fld ft2,96(sp) - f4c4: 4124 lw s1,64(a0) - f4c6: 9f25 0x9f25 - f4c8: 0240 addi s0,sp,260 - f4ca: 0000 unimp - f4cc: 0280 addi s0,sp,320 - f4ce: 0000 unimp - f4d0: 0001 nop - f4d2: 805e c.mv zero,s7 - f4d4: 0002 c.slli64 zero - f4d6: 1c00 addi s0,sp,560 - f4d8: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - f4dc: 9100 0x9100 - f4de: 066c addi a1,sp,780 - f4e0: 2431 jal f6ec <_start-0x7fff0914> - f4e2: 2541 jal fb62 <_start-0x7fff049e> - f4e4: 1c9f 0003 2000 0x200000031c9f - f4ea: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> - f4ee: 7200 flw fs0,32(a2) - f4f0: 066c addi a1,sp,780 - f4f2: 2431 jal f6fe <_start-0x7fff0902> - f4f4: 2541 jal fb74 <_start-0x7fff048c> - f4f6: 209f 0003 2800 0x28000003209f - f4fc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - f500: 5e00 lw s0,56(a2) - f502: 0328 addi a0,sp,392 - f504: 0000 unimp - f506: 0334 addi a3,sp,392 - f508: 0000 unimp - f50a: 0008 0x8 - f50c: 6c91 lui s9,0x4 - f50e: 3106 fld ft2,96(sp) - f510: 4124 lw s1,64(a0) - f512: 9f25 0x9f25 - ... - f51c: 0088 addi a0,sp,64 - f51e: 0000 unimp - f520: 0308 addi a0,sp,384 - f522: 0000 unimp - f524: 0001 nop - f526: 0003205b 0x3205b - f52a: 3400 fld fs0,40(s0) - f52c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - f530: 5b00 lw s0,48(a4) - ... - f53a: 009c addi a5,sp,64 - f53c: 0000 unimp - f53e: 0124 addi s1,sp,136 - f540: 0000 unimp - f542: 0001 nop - f544: 245e fld fs0,464(sp) - f546: 0001 nop - f548: 3000 fld fs0,32(s0) - f54a: 0001 nop - f54c: 0c00 addi s0,sp,528 - f54e: 9100 0x9100 - f550: 066c addi a1,sp,780 - f552: 2431 jal f75e <_start-0x7fff08a2> - f554: 2541 jal fbd4 <_start-0x7fff042c> - f556: 000a c.slli zero,0x2 - f558: 1c3c addi a5,sp,568 - f55a: 309f 0001 4c00 0x4c000001309f - f560: 0001 nop - f562: 0100 addi s0,sp,128 - f564: 5e00 lw s0,56(a2) - f566: 014c addi a1,sp,132 - f568: 0000 unimp - f56a: 01c4 addi s1,sp,196 - f56c: 0000 unimp - f56e: 000c 0xc - f570: 6c91 lui s9,0x4 - f572: 3106 fld ft2,96(sp) - f574: 4124 lw s1,64(a0) - f576: 0a25 addi s4,s4,9 - f578: 3c00 fld fs0,56(s0) - f57a: 9f1c 0x9f1c - f57c: 01c4 addi s1,sp,196 - f57e: 0000 unimp - f580: 01c8 addi a0,sp,196 - f582: 0000 unimp - f584: 000c 0xc - f586: 6c7f 0x6c7f - f588: 3106 fld ft2,96(sp) - f58a: 4124 lw s1,64(a0) - f58c: 0a25 addi s4,s4,9 - f58e: 3c00 fld fs0,56(s0) - f590: 9f1c 0x9f1c - f592: 01c8 addi a0,sp,196 - f594: 0000 unimp - f596: 01f8 addi a4,sp,204 - f598: 0000 unimp - f59a: 000c 0xc - f59c: 6c91 lui s9,0x4 - f59e: 3106 fld ft2,96(sp) - f5a0: 4124 lw s1,64(a0) - f5a2: 0a25 addi s4,s4,9 - f5a4: 3c00 fld fs0,56(s0) - f5a6: 9f1c 0x9f1c - f5a8: 01f8 addi a4,sp,204 - f5aa: 0000 unimp - f5ac: 0204 addi s1,sp,256 - f5ae: 0000 unimp - f5b0: 000c 0xc - f5b2: 6c7d lui s8,0x1f - f5b4: 3106 fld ft2,96(sp) - f5b6: 4124 lw s1,64(a0) - f5b8: 0a25 addi s4,s4,9 - f5ba: 3c00 fld fs0,56(s0) - f5bc: 9f1c 0x9f1c - f5be: 0204 addi s1,sp,256 - f5c0: 0000 unimp - f5c2: 0240 addi s0,sp,260 - f5c4: 0000 unimp - f5c6: 000c 0xc - f5c8: 6c91 lui s9,0x4 - f5ca: 3106 fld ft2,96(sp) - f5cc: 4124 lw s1,64(a0) - f5ce: 0a25 addi s4,s4,9 - f5d0: 3c00 fld fs0,56(s0) - f5d2: 9f1c 0x9f1c - f5d4: 025c addi a5,sp,260 - f5d6: 0000 unimp - f5d8: 0268 addi a0,sp,268 - f5da: 0000 unimp - f5dc: 0002 c.slli64 zero - f5de: 9f30 0x9f30 - f5e0: 0268 addi a0,sp,268 - f5e2: 0000 unimp - f5e4: 0298 addi a4,sp,320 - f5e6: 0000 unimp - f5e8: 0004 0x4 - f5ea: ff0a fsw ft2,188(sp) - f5ec: 02989f07 0x2989f07 - f5f0: 0000 unimp - f5f2: 02a0 addi s0,sp,328 - f5f4: 0000 unimp - f5f6: 0001 nop - f5f8: b05e fsd fs7,32(sp) - f5fa: 0002 c.slli64 zero - f5fc: dc00 sw s0,56(s0) - f5fe: 0002 c.slli64 zero - f600: 0100 addi s0,sp,128 - f602: 5e00 lw s0,56(a2) - f604: 02dc addi a5,sp,324 - f606: 0000 unimp - f608: 02f4 addi a3,sp,332 - f60a: 0000 unimp - f60c: 0004 0x4 - f60e: ff0a fsw ft2,188(sp) - f610: 03209f07 0x3209f07 - f614: 0000 unimp - f616: 0328 addi a0,sp,392 - f618: 0000 unimp - f61a: 0004 0x4 - f61c: ff0a fsw ft2,188(sp) - f61e: 03289f07 0x3289f07 - f622: 0000 unimp - f624: 0334 addi a3,sp,392 - f626: 0000 unimp - f628: 0001 nop - f62a: 005e c.slli zero,0x17 - f62c: 0000 unimp - f62e: 0000 unimp - f630: 0000 unimp - f632: e800 fsw fs0,16(s0) - f634: 0000 unimp - f636: 0800 addi s0,sp,16 - f638: 0001 nop - f63a: 0100 addi s0,sp,128 - f63c: 5d00 lw s0,56(a0) - f63e: 0108 addi a0,sp,128 - f640: 0000 unimp - f642: 010c addi a1,sp,128 - f644: 0000 unimp - f646: 7c7c0003 lb zero,1991(s8) # 1f7c7 <_start-0x7ffe0839> - f64a: 0c9f 0001 1400 0x140000010c9f - f650: 0001 nop - f652: 0100 addi s0,sp,128 - f654: 5c00 lw s0,56(s0) - f656: 026c addi a1,sp,268 - f658: 0000 unimp - f65a: 0278 addi a4,sp,268 - f65c: 0000 unimp - f65e: 000a c.slli zero,0x2 - f660: 007c addi a5,sp,12 - f662: 254c fld fa1,136(a0) - f664: 007f 0x7f - f666: 2434 fld fa3,72(s0) - f668: 9f21 0x9f21 - f66a: 0278 addi a4,sp,268 - f66c: 0000 unimp - f66e: 027c addi a5,sp,268 - f670: 0000 unimp - f672: 7491000b 0x7491000b - f676: 4c06 lw s8,64(sp) - f678: 7f25 lui t5,0xfffe9 - f67a: 3400 fld fs0,40(s0) - f67c: 2124 fld fs1,64(a0) - f67e: 7c9f 0002 8400 0x840000027c9f - f684: 0002 c.slli64 zero - f686: 0c00 addi s0,sp,528 - f688: 9100 0x9100 - f68a: 0674 addi a3,sp,780 - f68c: 254c fld fa1,136(a0) - f68e: 7891 lui a7,0xfffe4 - f690: 3406 fld fs0,96(sp) - f692: 2124 fld fs1,64(a0) - f694: 849f 0002 9800 0x98000002849f - f69a: 0002 c.slli64 zero - f69c: 0100 addi s0,sp,128 - f69e: 5d00 lw s0,56(a0) - f6a0: 02a4 addi s1,sp,328 - f6a2: 0000 unimp - f6a4: 02cc addi a1,sp,324 - f6a6: 0000 unimp - f6a8: 0001 nop - f6aa: d05d beqz s0,f650 <_start-0x7fff09b0> - f6ac: 0002 c.slli64 zero - f6ae: e000 fsw fs0,0(s0) - f6b0: 0002 c.slli64 zero - f6b2: 0100 addi s0,sp,128 - f6b4: 5d00 lw s0,56(a0) - f6b6: 02f4 addi a3,sp,332 - f6b8: 0000 unimp - f6ba: 0320 addi s0,sp,392 - f6bc: 0000 unimp - f6be: 0001 nop - f6c0: 285d jal f776 <_start-0x7fff088a> - f6c2: 30000003 lb zero,768(zero) # 300 <_start-0x7ffffd00> - f6c6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - f6ca: 5d00 lw s0,56(a0) - ... - f6d4: 00ec addi a1,sp,76 - f6d6: 0000 unimp - f6d8: 0114 addi a3,sp,128 - f6da: 0000 unimp - f6dc: 0001 nop - f6de: 6c5f 0002 7400 0x740000026c5f - f6e4: 0002 c.slli64 zero - f6e6: 0a00 addi s0,sp,272 - f6e8: 7f00 flw fs0,56(a4) - f6ea: 4c00 lw s0,24(s0) - f6ec: 8025 srli s0,s0,0x9 - f6ee: 3400 fld fs0,40(s0) - f6f0: 2124 fld fs1,64(a0) - f6f2: 749f 0002 7c00 0x7c000002749f - f6f8: 0002 c.slli64 zero - f6fa: 0b00 addi s0,sp,400 - f6fc: 7f00 flw fs0,56(a4) - f6fe: 4c00 lw s0,24(s0) - f700: 9125 srli a0,a0,0x29 - f702: 067c addi a5,sp,780 - f704: 2434 fld fa3,72(s0) - f706: 9f21 0x9f21 - f708: 027c addi a5,sp,268 - f70a: 0000 unimp - f70c: 0288 addi a0,sp,320 - f70e: 0000 unimp - f710: 000c 0xc - f712: 7891 lui a7,0xfffe4 - f714: 4c06 lw s8,64(sp) - f716: 9125 srli a0,a0,0x29 - f718: 067c addi a5,sp,780 - f71a: 2434 fld fa3,72(s0) - f71c: 9f21 0x9f21 - f71e: 0288 addi a0,sp,320 - f720: 0000 unimp - f722: 028c addi a1,sp,320 - f724: 0000 unimp - f726: 0001 nop - f728: 8c5f 0002 9000 0x900000028c5f - f72e: 0002 c.slli64 zero - f730: 0c00 addi s0,sp,528 - f732: 9100 0x9100 - f734: 0678 addi a4,sp,780 - f736: 254c fld fa1,136(a0) - f738: 7c91 lui s9,0xfffe4 - f73a: 3406 fld fs0,96(sp) - f73c: 2124 fld fs1,64(a0) - f73e: 909f 0002 9800 0x98000002909f - f744: 0002 c.slli64 zero - f746: 0100 addi s0,sp,128 - f748: 5f00 lw s0,56(a4) - f74a: 02a4 addi s1,sp,328 - f74c: 0000 unimp - f74e: 02ac addi a1,sp,328 - f750: 0000 unimp - f752: 0001 nop - f754: ac5f 0002 c400 0xc4000002ac5f - f75a: 0002 c.slli64 zero - f75c: 0900 addi s0,sp,144 - f75e: 7f00 flw fs0,56(a4) - f760: 1100 addi s0,sp,160 - f762: ffff 0xffff - f764: 7bff 0x7bff - f766: 9f1a add t5,t5,t1 - f768: 02c4 addi s1,sp,324 - f76a: 0000 unimp - f76c: 02e4 addi s1,sp,332 - f76e: 0000 unimp - f770: 0001 nop - f772: f45f 0002 f800 0xf8000002f45f - f778: 0002 c.slli64 zero - f77a: 0100 addi s0,sp,128 - f77c: 5f00 lw s0,56(a4) - f77e: 0328 addi a0,sp,392 - f780: 0000 unimp - f782: 032c addi a1,sp,392 - f784: 0000 unimp - f786: 0009 c.nop 2 - f788: 007f 0x7f - f78a: ff11 bnez a4,f6a6 <_start-0x7fff095a> - f78c: ffff 0xffff - f78e: 009f1a7b 0x9f1a7b - f792: 0000 unimp - f794: 0000 unimp - f796: 0000 unimp - f798: 4800 lw s0,16(s0) - f79a: 0000 unimp - f79c: 5000 lw s0,32(s0) - f79e: 0000 unimp - f7a0: 0200 addi s0,sp,256 - f7a2: 3300 fld fs0,32(a4) - f7a4: 709f 0000 3400 0x34000000709f - f7aa: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - f7ae: 0900 addi s0,sp,144 - f7b0: 9fff 0x9fff - ... - f7ba: 01b0 addi a2,sp,200 - f7bc: 0000 unimp - f7be: 01c0 addi s0,sp,196 - f7c0: 0000 unimp - f7c2: 0008 0x8 - f7c4: 008c addi a1,sp,64 - f7c6: 2e30 fld fa2,88(a2) - f7c8: ff08 fsw fa0,56(a4) - f7ca: 9f1a add t5,t5,t1 - ... - f7d4: 0158 addi a4,sp,132 - f7d6: 0000 unimp - f7d8: 0180 addi s0,sp,192 - f7da: 0000 unimp - f7dc: 0006 c.slli zero,0x1 - f7de: 2008 fld fa0,0(s0) - f7e0: 007e c.slli zero,0x1f - f7e2: 9f1c 0x9f1c - f7e4: 0180 addi s0,sp,192 - f7e6: 0000 unimp - f7e8: 01c0 addi s0,sp,196 - f7ea: 0000 unimp - f7ec: 0011 c.nop 4 - f7ee: 2008 fld fa0,0(s0) - f7f0: 3d0a fld fs10,160(sp) - f7f2: 913c 0x913c - f7f4: 066c addi a1,sp,780 - f7f6: 2431 jal fa02 <_start-0x7fff05fe> - f7f8: 2541 jal fe78 <_start-0x7fff0188> - f7fa: 4f1c lw a5,24(a4) - f7fc: 1c1a slli s8,s8,0x26 - f7fe: c09f 0001 0800 0x8000001c09f - f804: 0002 c.slli64 zero - f806: 0600 addi s0,sp,768 - f808: 0800 addi s0,sp,16 - f80a: 7e20 flw fs0,120(a2) - f80c: 1c00 addi s0,sp,560 - f80e: 089f 0002 1800 0x18000002089f - f814: 0002 c.slli64 zero - f816: 1100 addi s0,sp,160 - f818: 0800 addi s0,sp,16 - f81a: 0a20 addi s0,sp,280 - f81c: 3c3d jal f25a <_start-0x7fff0da6> - f81e: 6c91 lui s9,0x4 - f820: 3106 fld ft2,96(sp) - f822: 4124 lw s1,64(a0) - f824: 1c25 addi s8,s8,-23 - f826: 9f1c1a4f fnmadd.q fs4,fs8,fa7,fs3,rtz - f82a: 0218 addi a4,sp,256 - f82c: 0000 unimp - f82e: 0240 addi s0,sp,260 - f830: 0000 unimp - f832: 0006 c.slli zero,0x1 - f834: 2008 fld fa0,0(s0) - f836: 007e c.slli zero,0x1f - f838: 9f1c 0x9f1c - ... - f842: 0158 addi a4,sp,132 - f844: 0000 unimp - f846: 0180 addi s0,sp,192 - f848: 0000 unimp - f84a: 0001 nop - f84c: 805e c.mv zero,s7 - f84e: 0001 nop - f850: c000 sw s0,0(s0) - f852: 0001 nop - f854: 0e00 addi s0,sp,784 - f856: 0a00 addi s0,sp,272 - f858: 3c3d jal f296 <_start-0x7fff0d6a> - f85a: 6c91 lui s9,0x4 - f85c: 3106 fld ft2,96(sp) - f85e: 4124 lw s1,64(a0) - f860: 1c25 addi s8,s8,-23 - f862: c09f1a4f fnmadd.s fs4,ft10,fs1,fs8,rtz - f866: 0001 nop - f868: 0800 addi s0,sp,16 - f86a: 0002 c.slli64 zero - f86c: 0100 addi s0,sp,128 - f86e: 5e00 lw s0,56(a2) - f870: 0208 addi a0,sp,256 - f872: 0000 unimp - f874: 0218 addi a4,sp,256 - f876: 0000 unimp - f878: 000e c.slli zero,0x3 - f87a: 3d0a fld fs10,160(sp) - f87c: 913c 0x913c - f87e: 066c addi a1,sp,780 - f880: 2431 jal fa8c <_start-0x7fff0574> - f882: 2541 jal ff02 <_start-0x7fff00fe> - f884: 4f1c lw a5,24(a4) - f886: 9f1a add t5,t5,t1 - f888: 0218 addi a4,sp,256 - f88a: 0000 unimp - f88c: 0240 addi s0,sp,260 - f88e: 0000 unimp - f890: 0001 nop - f892: 005e c.slli zero,0x17 - f894: 0000 unimp - f896: 0000 unimp - f898: 0000 unimp - f89a: 5000 lw s0,32(s0) - f89c: 0001 nop - f89e: 8000 0x8000 - f8a0: 0001 nop - f8a2: 0100 addi s0,sp,128 - f8a4: 5a00 lw s0,48(a2) - f8a6: 0180 addi s0,sp,192 - f8a8: 0000 unimp - f8aa: 01c0 addi s0,sp,196 - f8ac: 0000 unimp - f8ae: 000e c.slli zero,0x3 - f8b0: 3d0a fld fs10,160(sp) - f8b2: 913c 0x913c - f8b4: 066c addi a1,sp,780 - f8b6: 2431 jal fac2 <_start-0x7fff053e> - f8b8: 2541 jal ff38 <_start-0x7fff00c8> - f8ba: 351c fld fa5,40(a0) - f8bc: 9f26 add t5,t5,s1 - f8be: 01c0 addi s0,sp,196 - f8c0: 0000 unimp - f8c2: 0240 addi s0,sp,260 - f8c4: 0000 unimp - f8c6: 0001 nop - f8c8: 005a c.slli zero,0x16 - f8ca: 0000 unimp - f8cc: 0000 unimp - f8ce: 0000 unimp - f8d0: 5800 lw s0,48(s0) - f8d2: 0001 nop - f8d4: 5c00 lw s0,56(s0) - f8d6: 0001 nop - f8d8: 0200 addi s0,sp,256 - f8da: 3000 fld fs0,32(s0) - f8dc: 5c9f 0001 6400 0x640000015c9f - f8e2: 0001 nop - f8e4: 0100 addi s0,sp,128 - f8e6: 5f00 lw s0,56(a4) - f8e8: 0164 addi s1,sp,140 - f8ea: 0000 unimp - f8ec: 016c addi a1,sp,140 - f8ee: 0000 unimp - f8f0: 7f7f0003 lb zero,2039(t5) # fffe97f7 <__BSS_END__+0x7ffd2a7f> - f8f4: 6c9f 0001 7c00 0x7c0000016c9f - f8fa: 0001 nop - f8fc: 0100 addi s0,sp,128 - f8fe: 5f00 lw s0,56(a4) - f900: 0180 addi s0,sp,192 - f902: 0000 unimp - f904: 01b4 addi a3,sp,200 - f906: 0000 unimp - f908: 0001 nop - f90a: c05e sw s7,0(sp) - f90c: 0001 nop - f90e: c400 sw s0,8(s0) - f910: 0001 nop - f912: 0100 addi s0,sp,128 - f914: 5f00 lw s0,56(a4) - f916: 01dc addi a5,sp,196 - f918: 0000 unimp - f91a: 01ec addi a1,sp,204 - f91c: 0000 unimp - f91e: 0002 c.slli64 zero - f920: 9f30 0x9f30 - f922: 01ec addi a1,sp,204 - f924: 0000 unimp - f926: 01f4 addi a3,sp,204 - f928: 0000 unimp - f92a: 0001 nop - f92c: f460 fsw fs0,108(s0) - f92e: 0001 nop - f930: fc00 fsw fs0,56(s0) - f932: 0001 nop - f934: 0300 addi s0,sp,384 - f936: 7f00 flw fs0,56(a4) - f938: 9f01 0x9f01 - f93a: 01fc addi a5,sp,204 - f93c: 0000 unimp - f93e: 0218 addi a4,sp,256 - f940: 0000 unimp - f942: 0005 c.nop 1 - f944: 7a34 flw fa3,112(a2) - f946: 1c00 addi s0,sp,560 - f948: 189f 0002 3800 0x38000002189f - f94e: 0002 c.slli64 zero - f950: 0100 addi s0,sp,128 - f952: 6000 flw fs0,0(s0) - f954: 0238 addi a4,sp,264 - f956: 0000 unimp - f958: 023c addi a5,sp,264 - f95a: 0000 unimp - f95c: 01800003 lb zero,24(zero) # 18 <_start-0x7fffffe8> - f960: 3c9f 0002 4000 0x400000023c9f - f966: 0002 c.slli64 zero - f968: 0100 addi s0,sp,128 - f96a: 6000 flw fs0,0(s0) - ... - f974: 0158 addi a4,sp,132 - f976: 0000 unimp - f978: 015c addi a5,sp,132 - f97a: 0000 unimp - f97c: 0002 c.slli64 zero - f97e: 9f30 0x9f30 - f980: 015c addi a5,sp,132 - f982: 0000 unimp - f984: 0240 addi s0,sp,260 - f986: 0000 unimp - f988: 0001 nop - f98a: 006c addi a1,sp,12 - f98c: 0000 unimp - f98e: 0000 unimp - f990: 0000 unimp - f992: a800 fsd fs0,16(s0) - f994: 0000 unimp - f996: e000 fsw fs0,0(s0) - f998: 0000 unimp - f99a: 0200 addi s0,sp,256 - f99c: 3100 fld fs0,32(a0) - f99e: e09f 0000 e400 0xe4000000e09f - f9a4: 0000 unimp - f9a6: 0200 addi s0,sp,256 - f9a8: 3300 fld fs0,32(a4) - f9aa: 009f 0000 0000 0x9f - f9b0: 0000 unimp - f9b2: a800 fsd fs0,16(s0) - f9b4: 0000 unimp - f9b6: b400 fsd fs0,40(s0) - f9b8: 0000 unimp - f9ba: 0100 addi s0,sp,128 - f9bc: 5a00 lw s0,48(a2) - f9be: 00b4 addi a3,sp,72 - f9c0: 0000 unimp - f9c2: 00c8 addi a0,sp,68 - f9c4: 0000 unimp - f9c6: 0008 0x8 - f9c8: 007f 0x7f - f9ca: 2434 fld fa3,72(s0) - f9cc: 007a c.slli zero,0x1e - f9ce: 9f21 0x9f21 - f9d0: 00c8 addi a0,sp,68 - f9d2: 0000 unimp - f9d4: 00d4 addi a3,sp,68 - f9d6: 0000 unimp - f9d8: 0001 nop - f9da: d45d beqz s0,f988 <_start-0x7fff0678> - f9dc: 0000 unimp - f9de: e000 fsw fs0,0(s0) - f9e0: 0000 unimp - f9e2: 0900 addi s0,sp,144 - f9e4: 9100 0x9100 - f9e6: 0674 addi a3,sp,780 - f9e8: 2434 fld fa3,72(s0) - f9ea: 007a c.slli zero,0x1e - f9ec: 9f21 0x9f21 - ... - f9f6: 026c addi a1,sp,268 - f9f8: 0000 unimp - f9fa: 0298 addi a4,sp,320 - f9fc: 0000 unimp - f9fe: 0002 c.slli64 zero - fa00: 00009f33 sll t5,ra,zero - fa04: 0000 unimp - fa06: 0000 unimp - fa08: 0000 unimp - fa0a: 00ec addi a1,sp,76 - fa0c: 0000 unimp - fa0e: 0114 addi a3,sp,128 - fa10: 0000 unimp - fa12: 0002 c.slli64 zero - fa14: 9f30 0x9f30 - ... - fa1e: 0104 addi s1,sp,128 - fa20: 0000 unimp - fa22: 0114 addi a3,sp,128 - fa24: 0000 unimp - fa26: 0001 nop - fa28: 005c addi a5,sp,4 - ... - fa32: 0000 unimp - fa34: 2400 fld fs0,8(s0) - fa36: 0000 unimp - fa38: 0100 addi s0,sp,128 - fa3a: 5a00 lw s0,48(a2) - fa3c: 0024 addi s1,sp,8 - fa3e: 0000 unimp - fa40: 0038 addi a4,sp,8 - fa42: 0000 unimp - fa44: 0004 0x4 - fa46: 9f5a01f3 0x9f5a01f3 - fa4a: 0038 addi a4,sp,8 - fa4c: 0000 unimp - fa4e: 004c addi a1,sp,4 - fa50: 0000 unimp - fa52: 0001 nop - fa54: 005a c.slli zero,0x16 - ... - fa5e: 0000 unimp - fa60: 2400 fld fs0,8(s0) - fa62: 0000 unimp - fa64: 0100 addi s0,sp,128 - fa66: 5a00 lw s0,48(a2) - fa68: 0024 addi s1,sp,8 - fa6a: 0000 unimp - fa6c: 0038 addi a4,sp,8 - fa6e: 0000 unimp - fa70: 0004 0x4 - fa72: 9f5a01f3 0x9f5a01f3 - fa76: 0038 addi a4,sp,8 - fa78: 0000 unimp - fa7a: 004c addi a1,sp,4 - fa7c: 0000 unimp - fa7e: 0001 nop - fa80: 005a c.slli zero,0x16 - fa82: 0000 unimp - fa84: 0000 unimp - fa86: 0000 unimp - fa88: 1400 addi s0,sp,544 - fa8a: 0000 unimp - fa8c: 2000 fld fs0,0(s0) - fa8e: 0000 unimp - fa90: 0100 addi s0,sp,128 - fa92: 5f00 lw s0,56(a4) - ... - -Disassembly of section .debug_ranges: - -00000000 <.debug_ranges>: - ... - 8: 0004 0x4 - a: 0000 unimp - c: 01d4 addi a3,sp,196 - e: 0000 unimp - 10: 01dc addi a5,sp,196 - 12: 0000 unimp - 14: 0424 addi s1,sp,520 - 16: 0000 unimp - 18: 0428 addi a0,sp,520 - 1a: 0000 unimp - 1c: 0434 addi a3,sp,520 - ... - 26: 0000 unimp - 28: 0020 addi s0,sp,8 - 2a: 0000 unimp - 2c: 004c addi a1,sp,4 - 2e: 0000 unimp - 30: 00f4 addi a3,sp,76 - 32: 0000 unimp - 34: 0108 addi a0,sp,128 - ... - 3e: 0000 unimp - 40: 00ec addi a1,sp,76 - 42: 0000 unimp - 44: 00f4 addi a3,sp,76 - 46: 0000 unimp - 48: 0300 addi s0,sp,384 - 4a: 0000 unimp - 4c: 0424 addi s1,sp,520 - ... - 56: 0000 unimp - 58: 030c addi a1,sp,384 - 5a: 0000 unimp - 5c: 0310 addi a2,sp,384 - 5e: 0000 unimp - 60: 0314 addi a3,sp,384 - 62: 0000 unimp - 64: 0318 addi a4,sp,384 - 66: 0000 unimp - 68: 0324 addi s1,sp,392 - 6a: 0000 unimp - 6c: 0330 addi a2,sp,392 - 6e: 0000 unimp - 70: 0334 addi a3,sp,392 - 72: 0000 unimp - 74: 03ac addi a1,sp,456 - 76: 0000 unimp - 78: 03b0 addi a2,sp,456 - 7a: 0000 unimp - 7c: 03b4 addi a3,sp,456 - ... - 86: 0000 unimp - 88: 03ac addi a1,sp,456 - 8a: 0000 unimp - 8c: 03b0 addi a2,sp,456 - 8e: 0000 unimp - 90: 03b4 addi a3,sp,456 - 92: 0000 unimp - 94: 03f4 addi a3,sp,460 - 96: 0000 unimp - 98: 03fc addi a5,sp,460 - 9a: 0000 unimp - 9c: 0410 addi a2,sp,512 - 9e: 0000 unimp - a0: 0414 addi a3,sp,512 - a2: 0000 unimp - a4: 0418 addi a4,sp,512 - ... - ae: 0000 unimp - b0: 0114 addi a3,sp,128 - b2: 0000 unimp - b4: 0140 addi s0,sp,132 - b6: 0000 unimp - b8: 01dc addi a5,sp,196 - ba: 0000 unimp - bc: 01f0 addi a2,sp,204 - ... - c6: 0000 unimp - c8: 0200 addi s0,sp,256 - ca: 0000 unimp - cc: 0204 addi s1,sp,256 - ce: 0000 unimp - d0: 0208 addi a0,sp,256 - d2: 0000 unimp - d4: 020c addi a1,sp,256 - d6: 0000 unimp - d8: 0210 addi a2,sp,256 - da: 0000 unimp - dc: 029c addi a5,sp,320 - ... - e6: 0000 unimp - e8: 02a0 addi s0,sp,328 - ea: 0000 unimp - ec: 02d4 addi a3,sp,324 - ee: 0000 unimp - f0: 02ec addi a1,sp,332 - f2: 0000 unimp - f4: 0300 addi s0,sp,384 - ... - 102: 0000 unimp - 104: 00dc addi a5,sp,68 - 106: 0000 unimp - 108: 00e0 addi s0,sp,76 - 10a: 0000 unimp - 10c: 040c addi a1,sp,512 - ... - 116: 0000 unimp - 118: 0020 addi s0,sp,8 - 11a: 0000 unimp - 11c: 004c addi a1,sp,4 - 11e: 0000 unimp - 120: 00e0 addi s0,sp,76 - 122: 0000 unimp - 124: 00f4 addi a3,sp,76 - ... - 12e: 0000 unimp - 130: 0100 addi s0,sp,128 - 132: 0000 unimp - 134: 012c addi a1,sp,136 - 136: 0000 unimp - 138: 01a8 addi a0,sp,200 - 13a: 0000 unimp - 13c: 01bc addi a5,sp,200 - ... - 146: 0000 unimp - 148: 01cc addi a1,sp,196 - 14a: 0000 unimp - 14c: 01d4 addi a3,sp,196 - 14e: 0000 unimp - 150: 01dc addi a5,sp,196 - 152: 0000 unimp - 154: 0248 addi a0,sp,260 - ... - 15e: 0000 unimp - 160: 024c addi a1,sp,260 - 162: 0000 unimp - 164: 0280 addi s0,sp,320 - 166: 0000 unimp - 168: 02a8 addi a0,sp,328 - 16a: 0000 unimp - 16c: 02bc addi a5,sp,328 - ... - 176: 0000 unimp - 178: 02c8 addi a0,sp,324 - 17a: 0000 unimp - 17c: 02cc addi a1,sp,324 - 17e: 0000 unimp - 180: 02d0 addi a2,sp,324 - 182: 0000 unimp - 184: 02d4 addi a3,sp,324 - 186: 0000 unimp - 188: 02e0 addi s0,sp,332 - 18a: 0000 unimp - 18c: 02ec addi a1,sp,332 - 18e: 0000 unimp - 190: 02f4 addi a3,sp,332 - 192: 0000 unimp - 194: 0368 addi a0,sp,396 - 196: 0000 unimp - 198: 036c addi a1,sp,396 - 19a: 0000 unimp - 19c: 0370 addi a2,sp,396 - 19e: 0000 unimp - 1a0: 0378 addi a4,sp,396 - 1a2: 0000 unimp - 1a4: 037c addi a5,sp,396 - ... - 1ae: 0000 unimp - 1b0: 0368 addi a0,sp,396 - 1b2: 0000 unimp - 1b4: 036c addi a1,sp,396 - 1b6: 0000 unimp - 1b8: 0370 addi a2,sp,396 - 1ba: 0000 unimp - 1bc: 0378 addi a4,sp,396 - 1be: 0000 unimp - 1c0: 037c addi a5,sp,396 - 1c2: 0000 unimp - 1c4: 03cc addi a1,sp,452 - ... - 1d6: 0000 unimp - 1d8: 0004 0x4 - 1da: 0000 unimp - 1dc: 0008 0x8 - 1de: 0000 unimp - 1e0: 001c 0x1c - 1e2: 0000 unimp - 1e4: 0020 addi s0,sp,8 - 1e6: 0000 unimp - 1e8: 0030 addi a2,sp,8 - 1ea: 0000 unimp - 1ec: 0034 addi a3,sp,8 - 1ee: 0000 unimp - 1f0: 0040 addi s0,sp,4 - 1f2: 0000 unimp - 1f4: 0048 addi a0,sp,4 - 1f6: 0000 unimp - 1f8: 0158 addi a4,sp,132 - 1fa: 0000 unimp - 1fc: 015c addi a5,sp,132 - 1fe: 0000 unimp - 200: 0588 addi a0,sp,704 - 202: 0000 unimp - 204: 058c addi a1,sp,704 - ... - 20e: 0000 unimp - 210: 0070 addi a2,sp,12 - 212: 0000 unimp - 214: 0074 addi a3,sp,12 - 216: 0000 unimp - 218: 00f0 addi a2,sp,76 - 21a: 0000 unimp - 21c: 014c addi a1,sp,132 - ... - 226: 0000 unimp - 228: 0074 addi a3,sp,12 - 22a: 0000 unimp - 22c: 0088 addi a0,sp,64 - 22e: 0000 unimp - 230: 05bc addi a5,sp,712 - 232: 0000 unimp - 234: 05c0 addi s0,sp,708 - ... - 23e: 0000 unimp - 240: 00b0 addi a2,sp,72 - 242: 0000 unimp - 244: 00b4 addi a3,sp,72 - 246: 0000 unimp - 248: 0190 addi a2,sp,192 - 24a: 0000 unimp - 24c: 01f0 addi a2,sp,204 - ... - 256: 0000 unimp - 258: 0228 addi a0,sp,264 - 25a: 0000 unimp - 25c: 04d0 addi a2,sp,580 - 25e: 0000 unimp - 260: 057c addi a5,sp,652 - 262: 0000 unimp - 264: 0588 addi a0,sp,704 - 266: 0000 unimp - 268: 06bc addi a5,sp,840 - 26a: 0000 unimp - 26c: 06c8 addi a0,sp,836 - ... - 276: 0000 unimp - 278: 0254 addi a3,sp,260 - 27a: 0000 unimp - 27c: 0268 addi a0,sp,268 - 27e: 0000 unimp - 280: 026c addi a1,sp,268 - 282: 0000 unimp - 284: 02ec addi a1,sp,332 - 286: 0000 unimp - 288: 0348 addi a0,sp,388 - 28a: 0000 unimp - 28c: 034c addi a1,sp,388 - ... - 296: 0000 unimp - 298: 0354 addi a3,sp,388 - 29a: 0000 unimp - 29c: 0364 addi s1,sp,396 - 29e: 0000 unimp - 2a0: 0368 addi a0,sp,396 - 2a2: 0000 unimp - 2a4: 0368 addi a0,sp,396 - ... - 2ae: 0000 unimp - 2b0: 0380 addi s0,sp,448 - 2b2: 0000 unimp - 2b4: 038c addi a1,sp,448 - 2b6: 0000 unimp - 2b8: 0390 addi a2,sp,448 - 2ba: 0000 unimp - 2bc: 0394 addi a3,sp,448 - ... - 2c6: 0000 unimp - 2c8: 03ac addi a1,sp,456 - 2ca: 0000 unimp - 2cc: 0438 addi a4,sp,520 - 2ce: 0000 unimp - 2d0: 048c addi a1,sp,576 - 2d2: 0000 unimp - 2d4: 0490 addi a2,sp,576 - ... - 2de: 0000 unimp - 2e0: 0494 addi a3,sp,576 - 2e2: 0000 unimp - 2e4: 0498 addi a4,sp,576 - 2e6: 0000 unimp - 2e8: 049c addi a5,sp,576 - 2ea: 0000 unimp - 2ec: 049c addi a5,sp,576 - ... - 2f6: 0000 unimp - 2f8: 04ac addi a1,sp,584 - 2fa: 0000 unimp - 2fc: 04b8 addi a4,sp,584 - 2fe: 0000 unimp - 300: 04bc addi a5,sp,584 - 302: 0000 unimp - 304: 04c4 addi s1,sp,580 - 306: 0000 unimp - 308: 06c0 addi s0,sp,836 - 30a: 0000 unimp - 30c: 06c8 addi a0,sp,836 - ... - 316: 0000 unimp - 318: 052c addi a1,sp,648 - 31a: 0000 unimp - 31c: 0538 addi a4,sp,648 - 31e: 0000 unimp - 320: 0540 addi s0,sp,644 - 322: 0000 unimp - 324: 0550 addi a2,sp,644 - ... - 32e: 0000 unimp - 330: 05d8 addi a4,sp,708 - 332: 0000 unimp - 334: 064c addi a1,sp,772 - 336: 0000 unimp - 338: 0654 addi a3,sp,772 - 33a: 0000 unimp - 33c: 0688 addi a0,sp,832 - 33e: 0000 unimp - 340: 06ac addi a1,sp,840 - 342: 0000 unimp - 344: 06bc addi a5,sp,840 - ... - 356: 0000 unimp - 358: 0008 0x8 - 35a: 0000 unimp - 35c: 000c 0xc - 35e: 0000 unimp - 360: 0020 addi s0,sp,8 - 362: 0000 unimp - 364: 0024 addi s1,sp,8 - 366: 0000 unimp - 368: 0030 addi a2,sp,8 - 36a: 0000 unimp - 36c: 0034 addi a3,sp,8 - 36e: 0000 unimp - 370: 0040 addi s0,sp,4 - 372: 0000 unimp - 374: 0048 addi a0,sp,4 - 376: 0000 unimp - 378: 0490 addi a2,sp,576 - 37a: 0000 unimp - 37c: 0494 addi a3,sp,576 - ... - 386: 0000 unimp - 388: 0070 addi a2,sp,12 - 38a: 0000 unimp - 38c: 0074 addi a3,sp,12 - 38e: 0000 unimp - 390: 00f4 addi a3,sp,76 - 392: 0000 unimp - 394: 0150 addi a2,sp,132 - ... - 39e: 0000 unimp - 3a0: 0074 addi a3,sp,12 - 3a2: 0000 unimp - 3a4: 0088 addi a0,sp,64 - 3a6: 0000 unimp - 3a8: 04c4 addi s1,sp,580 - 3aa: 0000 unimp - 3ac: 04c8 addi a0,sp,580 - ... - 3b6: 0000 unimp - 3b8: 00b0 addi a2,sp,72 - 3ba: 0000 unimp - 3bc: 00b4 addi a3,sp,72 - 3be: 0000 unimp - 3c0: 0190 addi a2,sp,192 - 3c2: 0000 unimp - 3c4: 01f0 addi a2,sp,204 - ... - 3ce: 0000 unimp - 3d0: 0228 addi a0,sp,264 - 3d2: 0000 unimp - 3d4: 0374 addi a3,sp,396 - 3d6: 0000 unimp - 3d8: 0374 addi a3,sp,396 - 3da: 0000 unimp - 3dc: 039c addi a5,sp,448 - ... - 3e6: 0000 unimp - 3e8: 0228 addi a0,sp,264 - 3ea: 0000 unimp - 3ec: 0270 addi a2,sp,268 - 3ee: 0000 unimp - 3f0: 0278 addi a4,sp,268 - 3f2: 0000 unimp - 3f4: 0280 addi s0,sp,320 - ... - 3fe: 0000 unimp - 400: 0270 addi a2,sp,268 - 402: 0000 unimp - 404: 0278 addi a4,sp,268 - 406: 0000 unimp - 408: 0280 addi s0,sp,320 - 40a: 0000 unimp - 40c: 02c0 addi s0,sp,324 - 40e: 0000 unimp - 410: 02c4 addi s1,sp,324 - 412: 0000 unimp - 414: 02d0 addi a2,sp,324 - ... - 41e: 0000 unimp - 420: 02c0 addi s0,sp,324 - 422: 0000 unimp - 424: 02c4 addi s1,sp,324 - 426: 0000 unimp - 428: 02d0 addi a2,sp,324 - 42a: 0000 unimp - 42c: 02d8 addi a4,sp,324 - 42e: 0000 unimp - 430: 02d8 addi a4,sp,324 - 432: 0000 unimp - 434: 0310 addi a2,sp,384 - 436: 0000 unimp - 438: 0314 addi a3,sp,384 - 43a: 0000 unimp - 43c: 031c addi a5,sp,384 - ... - 446: 0000 unimp - 448: 0310 addi a2,sp,384 - 44a: 0000 unimp - 44c: 0314 addi a3,sp,384 - 44e: 0000 unimp - 450: 031c addi a5,sp,384 - 452: 0000 unimp - 454: 033c addi a5,sp,392 - 456: 0000 unimp - 458: 033c addi a5,sp,392 - 45a: 0000 unimp - 45c: 0350 addi a2,sp,388 - 45e: 0000 unimp - 460: 0354 addi a3,sp,388 - 462: 0000 unimp - 464: 0358 addi a4,sp,388 - 466: 0000 unimp - 468: 0380 addi s0,sp,448 - 46a: 0000 unimp - 46c: 0384 addi s1,sp,448 - ... - 476: 0000 unimp - 478: 033c addi a5,sp,392 - 47a: 0000 unimp - 47c: 033c addi a5,sp,392 - 47e: 0000 unimp - 480: 0350 addi a2,sp,388 - 482: 0000 unimp - 484: 0354 addi a3,sp,388 - 486: 0000 unimp - 488: 0358 addi a4,sp,388 - 48a: 0000 unimp - 48c: 0364 addi s1,sp,396 - 48e: 0000 unimp - 490: 0374 addi a3,sp,396 - 492: 0000 unimp - 494: 0380 addi s0,sp,448 - ... - 49e: 0000 unimp - 4a0: 0364 addi s1,sp,396 - 4a2: 0000 unimp - 4a4: 0374 addi a3,sp,396 - 4a6: 0000 unimp - 4a8: 0384 addi s1,sp,448 - 4aa: 0000 unimp - 4ac: 039c addi a5,sp,448 - ... - 4b6: 0000 unimp - 4b8: 0374 addi a3,sp,396 - 4ba: 0000 unimp - 4bc: 0374 addi a3,sp,396 - 4be: 0000 unimp - 4c0: 039c addi a5,sp,448 - 4c2: 0000 unimp - 4c4: 03c4 addi s1,sp,452 - ... - 4ce: 0000 unimp - 4d0: 0374 addi a3,sp,396 - 4d2: 0000 unimp - 4d4: 0374 addi a3,sp,396 - 4d6: 0000 unimp - 4d8: 039c addi a5,sp,448 - 4da: 0000 unimp - 4dc: 03a8 addi a0,sp,456 - 4de: 0000 unimp - 4e0: 03a8 addi a0,sp,456 - 4e2: 0000 unimp - 4e4: 03bc addi a5,sp,456 - ... - 4ee: 0000 unimp - 4f0: 04b8 addi a4,sp,584 - 4f2: 0000 unimp - 4f4: 04c4 addi s1,sp,580 - 4f6: 0000 unimp - 4f8: 04d4 addi a3,sp,580 - 4fa: 0000 unimp - 4fc: 0584 addi s1,sp,704 - 4fe: 0000 unimp - 500: 05a8 addi a0,sp,712 - 502: 0000 unimp - 504: 05b8 addi a4,sp,712 - ... - 516: 0000 unimp - 518: 0014 0x14 - 51a: 0000 unimp - 51c: 0024 addi s1,sp,8 - 51e: 0000 unimp - 520: 0028 addi a0,sp,8 - 522: 0000 unimp - 524: 0030 addi a2,sp,8 - 526: 0000 unimp - 528: 003c addi a5,sp,8 - 52a: 0000 unimp - 52c: 003c addi a5,sp,8 - 52e: 0000 unimp - 530: 0040 addi s0,sp,4 - 532: 0000 unimp - 534: 0040 addi s0,sp,4 - 536: 0000 unimp - 538: 0044 addi s1,sp,4 - 53a: 0000 unimp - 53c: 0048 addi a0,sp,4 - ... - 546: 0000 unimp - 548: 0024 addi s1,sp,8 - 54a: 0000 unimp - 54c: 0028 addi a0,sp,8 - 54e: 0000 unimp - 550: 0030 addi a2,sp,8 - 552: 0000 unimp - 554: 0034 addi a3,sp,8 - 556: 0000 unimp - 558: 0048 addi a0,sp,4 - 55a: 0000 unimp - 55c: 0054 addi a3,sp,4 - ... - 56e: 0000 unimp - 570: 0004 0x4 - 572: 0000 unimp - 574: 0004 0x4 - 576: 0000 unimp - 578: 0008 0x8 - 57a: 0000 unimp - 57c: 0008 0x8 - 57e: 0000 unimp - 580: 000c 0xc - 582: 0000 unimp - 584: 000c 0xc - 586: 0000 unimp - 588: 0014 0x14 - 58a: 0000 unimp - 58c: 0020 addi s0,sp,8 - 58e: 0000 unimp - 590: 0034 addi a3,sp,8 - 592: 0000 unimp - 594: 003c addi a5,sp,8 - 596: 0000 unimp - 598: 0040 addi s0,sp,4 - 59a: 0000 unimp - 59c: 0048 addi a0,sp,4 - ... - 5a6: 0000 unimp - 5a8: 0020 addi s0,sp,8 - 5aa: 0000 unimp - 5ac: 0028 addi a0,sp,8 - 5ae: 0000 unimp - 5b0: 0048 addi a0,sp,4 - 5b2: 0000 unimp - 5b4: 0054 addi a3,sp,4 - ... - 5be: 0000 unimp - 5c0: 0084 addi s1,sp,64 - 5c2: 0000 unimp - 5c4: 00cc addi a1,sp,68 - 5c6: 0000 unimp - 5c8: 00d4 addi a3,sp,68 - 5ca: 0000 unimp - 5cc: 0134 addi a3,sp,136 - 5ce: 0000 unimp - 5d0: 0138 addi a4,sp,136 - 5d2: 0000 unimp - 5d4: 0144 addi s1,sp,132 - ... - 5e6: 0000 unimp - 5e8: 0004 0x4 - 5ea: 0000 unimp - 5ec: 0004 0x4 - 5ee: 0000 unimp - 5f0: 0008 0x8 - 5f2: 0000 unimp - 5f4: 0008 0x8 - 5f6: 0000 unimp - 5f8: 000c 0xc - 5fa: 0000 unimp - 5fc: 000c 0xc - 5fe: 0000 unimp - 600: 0014 0x14 - 602: 0000 unimp - 604: 0020 addi s0,sp,8 - 606: 0000 unimp - 608: 0034 addi a3,sp,8 - 60a: 0000 unimp - 60c: 003c addi a5,sp,8 - 60e: 0000 unimp - 610: 0040 addi s0,sp,4 - 612: 0000 unimp - 614: 0048 addi a0,sp,4 - ... - 61e: 0000 unimp - 620: 0020 addi s0,sp,8 - 622: 0000 unimp - 624: 0028 addi a0,sp,8 - 626: 0000 unimp - 628: 0048 addi a0,sp,4 - 62a: 0000 unimp - 62c: 0054 addi a3,sp,4 - ... - 636: 0000 unimp - 638: 0084 addi s1,sp,64 - 63a: 0000 unimp - 63c: 00cc addi a1,sp,68 - 63e: 0000 unimp - 640: 00d4 addi a3,sp,68 - 642: 0000 unimp - 644: 0134 addi a3,sp,136 - 646: 0000 unimp - 648: 0138 addi a4,sp,136 - 64a: 0000 unimp - 64c: 0144 addi s1,sp,132 - ... - 65e: 0000 unimp - 660: 0040 addi s0,sp,4 - 662: 0000 unimp - 664: 0044 addi s1,sp,4 - 666: 0000 unimp - 668: 004c addi a1,sp,4 - 66a: 0000 unimp - 66c: 0058 addi a4,sp,4 - 66e: 0000 unimp - 670: 0074 addi a3,sp,12 - 672: 0000 unimp - 674: 0098 addi a4,sp,64 - 676: 0000 unimp - 678: 0d2c addi a1,sp,664 - 67a: 0000 unimp - 67c: 0d30 addi a2,sp,664 - ... - 686: 0000 unimp - 688: 00ac addi a1,sp,72 - 68a: 0000 unimp - 68c: 00d8 addi a4,sp,68 - 68e: 0000 unimp - 690: 00e0 addi s0,sp,76 - 692: 0000 unimp - 694: 00e8 addi a0,sp,76 - ... - 69e: 0000 unimp - 6a0: 00ec addi a1,sp,76 - 6a2: 0000 unimp - 6a4: 00f0 addi a2,sp,76 - 6a6: 0000 unimp - 6a8: 01d8 addi a4,sp,196 - 6aa: 0000 unimp - 6ac: 02e8 addi a0,sp,332 - ... - 6b6: 0000 unimp - 6b8: 01e4 addi s1,sp,204 - 6ba: 0000 unimp - 6bc: 0238 addi a4,sp,264 - 6be: 0000 unimp - 6c0: 0278 addi a4,sp,268 - 6c2: 0000 unimp - 6c4: 02d8 addi a4,sp,324 - ... - 6ce: 0000 unimp - 6d0: 00f0 addi a2,sp,76 - 6d2: 0000 unimp - 6d4: 012c addi a1,sp,136 - 6d6: 0000 unimp - 6d8: 0d7c addi a5,sp,668 - 6da: 0000 unimp - 6dc: 0d80 addi s0,sp,720 - ... - 6e6: 0000 unimp - 6e8: 0140 addi s0,sp,132 - 6ea: 0000 unimp - 6ec: 016c addi a1,sp,140 - 6ee: 0000 unimp - 6f0: 0174 addi a3,sp,140 - 6f2: 0000 unimp - 6f4: 017c addi a5,sp,140 - ... - 6fe: 0000 unimp - 700: 0180 addi s0,sp,192 - 702: 0000 unimp - 704: 0184 addi s1,sp,192 - 706: 0000 unimp - 708: 0320 addi s0,sp,392 - 70a: 0000 unimp - 70c: 0430 addi a2,sp,520 - ... - 716: 0000 unimp - 718: 0328 addi a0,sp,392 - 71a: 0000 unimp - 71c: 037c addi a5,sp,396 - 71e: 0000 unimp - 720: 03c0 addi s0,sp,452 - 722: 0000 unimp - 724: 0420 addi s0,sp,520 - ... - 72e: 0000 unimp - 730: 0458 addi a4,sp,516 - 732: 0000 unimp - 734: 0b6c addi a1,sp,412 - 736: 0000 unimp - 738: 0b6c addi a1,sp,412 - 73a: 0000 unimp - 73c: 0b74 addi a3,sp,412 - ... - 746: 0000 unimp - 748: 0458 addi a4,sp,516 - 74a: 0000 unimp - 74c: 0af0 addi a2,sp,348 - 74e: 0000 unimp - 750: 0af8 addi a4,sp,348 - 752: 0000 unimp - 754: 0b08 addi a0,sp,400 - 756: 0000 unimp - 758: 0b14 addi a3,sp,400 - 75a: 0000 unimp - 75c: 0b18 addi a4,sp,400 - 75e: 0000 unimp - 760: 0b1c addi a5,sp,400 - 762: 0000 unimp - 764: 0b20 addi s0,sp,408 - ... - 76e: 0000 unimp - 770: 0458 addi a4,sp,516 - 772: 0000 unimp - 774: 049c addi a5,sp,576 - 776: 0000 unimp - 778: 04a0 addi s0,sp,584 - 77a: 0000 unimp - 77c: 04b4 addi a3,sp,584 - 77e: 0000 unimp - 780: 04bc addi a5,sp,584 - 782: 0000 unimp - 784: 04c4 addi s1,sp,580 - ... - 78e: 0000 unimp - 790: 049c addi a5,sp,576 - 792: 0000 unimp - 794: 04a0 addi s0,sp,584 - 796: 0000 unimp - 798: 04b4 addi a3,sp,584 - 79a: 0000 unimp - 79c: 04bc addi a5,sp,584 - 79e: 0000 unimp - 7a0: 04c4 addi s1,sp,580 - 7a2: 0000 unimp - 7a4: 04fc addi a5,sp,588 - 7a6: 0000 unimp - 7a8: 0500 addi s0,sp,640 - 7aa: 0000 unimp - 7ac: 0508 addi a0,sp,640 - 7ae: 0000 unimp - 7b0: 0510 addi a2,sp,640 - 7b2: 0000 unimp - 7b4: 0514 addi a3,sp,640 - ... - 7be: 0000 unimp - 7c0: 04fc addi a5,sp,588 - 7c2: 0000 unimp - 7c4: 0500 addi s0,sp,640 - 7c6: 0000 unimp - 7c8: 0508 addi a0,sp,640 - 7ca: 0000 unimp - 7cc: 0510 addi a2,sp,640 - 7ce: 0000 unimp - 7d0: 0514 addi a3,sp,640 - 7d2: 0000 unimp - 7d4: 051c addi a5,sp,640 - 7d6: 0000 unimp - 7d8: 051c addi a5,sp,640 - 7da: 0000 unimp - 7dc: 055c addi a5,sp,644 - ... - 7e6: 0000 unimp - 7e8: 055c addi a5,sp,644 - 7ea: 0000 unimp - 7ec: 0584 addi s1,sp,704 - 7ee: 0000 unimp - 7f0: 0588 addi a0,sp,704 - 7f2: 0000 unimp - 7f4: 0598 addi a4,sp,704 - 7f6: 0000 unimp - 7f8: 05a4 addi s1,sp,712 - 7fa: 0000 unimp - 7fc: 05b4 addi a3,sp,712 - ... - 806: 0000 unimp - 808: 0584 addi s1,sp,704 - 80a: 0000 unimp - 80c: 0588 addi a0,sp,704 - 80e: 0000 unimp - 810: 0598 addi a4,sp,704 - 812: 0000 unimp - 814: 05a4 addi s1,sp,712 - 816: 0000 unimp - 818: 05b4 addi a3,sp,712 - 81a: 0000 unimp - 81c: 05ec addi a1,sp,716 - 81e: 0000 unimp - 820: 05f0 addi a2,sp,716 - 822: 0000 unimp - 824: 05f8 addi a4,sp,716 - 826: 0000 unimp - 828: 0600 addi s0,sp,768 - 82a: 0000 unimp - 82c: 0604 addi s1,sp,768 - ... - 836: 0000 unimp - 838: 05ec addi a1,sp,716 - 83a: 0000 unimp - 83c: 05f0 addi a2,sp,716 - 83e: 0000 unimp - 840: 05f8 addi a4,sp,716 - 842: 0000 unimp - 844: 0600 addi s0,sp,768 - 846: 0000 unimp - 848: 0604 addi s1,sp,768 - 84a: 0000 unimp - 84c: 0634 addi a3,sp,776 - 84e: 0000 unimp - 850: 0638 addi a4,sp,776 - 852: 0000 unimp - 854: 063c addi a5,sp,776 - 856: 0000 unimp - 858: 0640 addi s0,sp,772 - 85a: 0000 unimp - 85c: 0644 addi s1,sp,772 - 85e: 0000 unimp - 860: 0648 addi a0,sp,772 - 862: 0000 unimp - 864: 0650 addi a2,sp,772 - 866: 0000 unimp - 868: 0654 addi a3,sp,772 - 86a: 0000 unimp - 86c: 0658 addi a4,sp,772 - ... - 876: 0000 unimp - 878: 0634 addi a3,sp,776 - 87a: 0000 unimp - 87c: 0638 addi a4,sp,776 - 87e: 0000 unimp - 880: 063c addi a5,sp,776 - 882: 0000 unimp - 884: 0640 addi s0,sp,772 - 886: 0000 unimp - 888: 0644 addi s1,sp,772 - 88a: 0000 unimp - 88c: 0648 addi a0,sp,772 - 88e: 0000 unimp - 890: 0650 addi a2,sp,772 - 892: 0000 unimp - 894: 0654 addi a3,sp,772 - 896: 0000 unimp - 898: 0658 addi a4,sp,772 - 89a: 0000 unimp - 89c: 0658 addi a4,sp,772 - 89e: 0000 unimp - 8a0: 067c addi a5,sp,780 - 8a2: 0000 unimp - 8a4: 0680 addi s0,sp,832 - ... - 8ae: 0000 unimp - 8b0: 0658 addi a4,sp,772 - 8b2: 0000 unimp - 8b4: 0670 addi a2,sp,780 - 8b6: 0000 unimp - 8b8: 0670 addi a2,sp,780 - 8ba: 0000 unimp - 8bc: 067c addi a5,sp,780 - 8be: 0000 unimp - 8c0: 0680 addi s0,sp,832 - 8c2: 0000 unimp - 8c4: 0684 addi s1,sp,832 - ... - 8ce: 0000 unimp - 8d0: 0670 addi a2,sp,780 - 8d2: 0000 unimp - 8d4: 0670 addi a2,sp,780 - 8d6: 0000 unimp - 8d8: 0684 addi s1,sp,832 - 8da: 0000 unimp - 8dc: 0698 addi a4,sp,832 - 8de: 0000 unimp - 8e0: 069c addi a5,sp,832 - 8e2: 0000 unimp - 8e4: 06a0 addi s0,sp,840 - 8e6: 0000 unimp - 8e8: 06a4 addi s1,sp,840 - 8ea: 0000 unimp - 8ec: 06ac addi a1,sp,840 - 8ee: 0000 unimp - 8f0: 06b4 addi a3,sp,840 - 8f2: 0000 unimp - 8f4: 06b8 addi a4,sp,840 - ... - 8fe: 0000 unimp - 900: 0698 addi a4,sp,832 - 902: 0000 unimp - 904: 069c addi a5,sp,832 - 906: 0000 unimp - 908: 06a0 addi s0,sp,840 - 90a: 0000 unimp - 90c: 06a4 addi s1,sp,840 - 90e: 0000 unimp - 910: 06ac addi a1,sp,840 - 912: 0000 unimp - 914: 06b4 addi a3,sp,840 - 916: 0000 unimp - 918: 06b8 addi a4,sp,840 - 91a: 0000 unimp - 91c: 06c0 addi s0,sp,836 - 91e: 0000 unimp - 920: 06c8 addi a0,sp,836 - 922: 0000 unimp - 924: 06cc addi a1,sp,836 - 926: 0000 unimp - 928: 06e0 addi s0,sp,844 - 92a: 0000 unimp - 92c: 06e8 addi a0,sp,844 - 92e: 0000 unimp - 930: 06f0 addi a2,sp,844 - 932: 0000 unimp - 934: 06f4 addi a3,sp,844 - ... - 93e: 0000 unimp - 940: 06c0 addi s0,sp,836 - 942: 0000 unimp - 944: 06c8 addi a0,sp,836 - 946: 0000 unimp - 948: 06cc addi a1,sp,836 - 94a: 0000 unimp - 94c: 06d8 addi a4,sp,836 - 94e: 0000 unimp - 950: 06dc addi a5,sp,836 - 952: 0000 unimp - 954: 06e0 addi s0,sp,844 - 956: 0000 unimp - 958: 06e8 addi a0,sp,844 - 95a: 0000 unimp - 95c: 06f0 addi a2,sp,844 - 95e: 0000 unimp - 960: 06f8 addi a4,sp,844 - 962: 0000 unimp - 964: 0700 addi s0,sp,896 - 966: 0000 unimp - 968: 0704 addi s1,sp,896 - 96a: 0000 unimp - 96c: 0708 addi a0,sp,896 - ... - 976: 0000 unimp - 978: 06d8 addi a4,sp,836 - 97a: 0000 unimp - 97c: 06dc addi a5,sp,836 - 97e: 0000 unimp - 980: 06f4 addi a3,sp,844 - 982: 0000 unimp - 984: 06f8 addi a4,sp,844 - 986: 0000 unimp - 988: 0700 addi s0,sp,896 - 98a: 0000 unimp - 98c: 0704 addi s1,sp,896 - 98e: 0000 unimp - 990: 0708 addi a0,sp,896 - 992: 0000 unimp - 994: 0728 addi a0,sp,904 - 996: 0000 unimp - 998: 072c addi a1,sp,904 - 99a: 0000 unimp - 99c: 0744 addi s1,sp,900 - 99e: 0000 unimp - 9a0: 0748 addi a0,sp,900 - 9a2: 0000 unimp - 9a4: 0754 addi a3,sp,900 - 9a6: 0000 unimp - 9a8: 0758 addi a4,sp,900 - 9aa: 0000 unimp - 9ac: 075c addi a5,sp,900 - ... - 9b6: 0000 unimp - 9b8: 0728 addi a0,sp,904 - 9ba: 0000 unimp - 9bc: 072c addi a1,sp,904 - 9be: 0000 unimp - 9c0: 0744 addi s1,sp,900 - 9c2: 0000 unimp - 9c4: 0748 addi a0,sp,900 - 9c6: 0000 unimp - 9c8: 0754 addi a3,sp,900 - 9ca: 0000 unimp - 9cc: 0758 addi a4,sp,900 - 9ce: 0000 unimp - 9d0: 075c addi a5,sp,900 - 9d2: 0000 unimp - 9d4: 07a0 addi s0,sp,968 - ... - 9de: 0000 unimp - 9e0: 07a0 addi s0,sp,968 - 9e2: 0000 unimp - 9e4: 07e0 addi s0,sp,972 - 9e6: 0000 unimp - 9e8: 07e4 addi s1,sp,972 - 9ea: 0000 unimp - 9ec: 07ec addi a1,sp,972 - ... - 9f6: 0000 unimp - 9f8: 07e0 addi s0,sp,972 - 9fa: 0000 unimp - 9fc: 07e4 addi s1,sp,972 - 9fe: 0000 unimp - a00: 07ec addi a1,sp,972 - a02: 0000 unimp - a04: 081c addi a5,sp,16 - a06: 0000 unimp - a08: 0820 addi s0,sp,24 - a0a: 0000 unimp - a0c: 0824 addi s1,sp,24 - a0e: 0000 unimp - a10: 082c addi a1,sp,24 - a12: 0000 unimp - a14: 0834 addi a3,sp,24 - a16: 0000 unimp - a18: 0880 addi s0,sp,80 - a1a: 0000 unimp - a1c: 0884 addi s1,sp,80 - ... - a26: 0000 unimp - a28: 081c addi a5,sp,16 - a2a: 0000 unimp - a2c: 0820 addi s0,sp,24 - a2e: 0000 unimp - a30: 0824 addi s1,sp,24 - a32: 0000 unimp - a34: 082c addi a1,sp,24 - a36: 0000 unimp - a38: 0834 addi a3,sp,24 - a3a: 0000 unimp - a3c: 0838 addi a4,sp,24 - a3e: 0000 unimp - a40: 083c addi a5,sp,24 - a42: 0000 unimp - a44: 0844 addi s1,sp,20 - a46: 0000 unimp - a48: 0848 addi a0,sp,20 - a4a: 0000 unimp - a4c: 084c addi a1,sp,20 - a4e: 0000 unimp - a50: 0884 addi s1,sp,80 - a52: 0000 unimp - a54: 0884 addi s1,sp,80 - ... - a5e: 0000 unimp - a60: 0838 addi a4,sp,24 - a62: 0000 unimp - a64: 083c addi a5,sp,24 - a66: 0000 unimp - a68: 0844 addi s1,sp,20 - a6a: 0000 unimp - a6c: 0848 addi a0,sp,20 - a6e: 0000 unimp - a70: 084c addi a1,sp,20 - a72: 0000 unimp - a74: 0858 addi a4,sp,20 - a76: 0000 unimp - a78: 085c addi a5,sp,20 - a7a: 0000 unimp - a7c: 0860 addi s0,sp,28 - a7e: 0000 unimp - a80: 0864 addi s1,sp,28 - a82: 0000 unimp - a84: 086c addi a1,sp,28 - a86: 0000 unimp - a88: 0874 addi a3,sp,28 - a8a: 0000 unimp - a8c: 0878 addi a4,sp,28 - a8e: 0000 unimp - a90: 0884 addi s1,sp,80 - a92: 0000 unimp - a94: 0884 addi s1,sp,80 - a96: 0000 unimp - a98: 08a4 addi s1,sp,88 - a9a: 0000 unimp - a9c: 08a8 addi a0,sp,88 - ... - aa6: 0000 unimp - aa8: 0858 addi a4,sp,20 - aaa: 0000 unimp - aac: 085c addi a5,sp,20 - aae: 0000 unimp - ab0: 0860 addi s0,sp,28 - ab2: 0000 unimp - ab4: 0864 addi s1,sp,28 - ab6: 0000 unimp - ab8: 086c addi a1,sp,28 - aba: 0000 unimp - abc: 0874 addi a3,sp,28 - abe: 0000 unimp - ac0: 0878 addi a4,sp,28 - ac2: 0000 unimp - ac4: 0880 addi s0,sp,80 - ac6: 0000 unimp - ac8: 0884 addi s1,sp,80 - aca: 0000 unimp - acc: 0884 addi s1,sp,80 - ace: 0000 unimp - ad0: 0894 addi a3,sp,80 - ad2: 0000 unimp - ad4: 08a0 addi s0,sp,88 - ad6: 0000 unimp - ad8: 08ac addi a1,sp,88 - ada: 0000 unimp - adc: 08b0 addi a2,sp,88 - ... - ae6: 0000 unimp - ae8: 0884 addi s1,sp,80 - aea: 0000 unimp - aec: 0894 addi a3,sp,80 - aee: 0000 unimp - af0: 08a0 addi s0,sp,88 - af2: 0000 unimp - af4: 08a4 addi s1,sp,88 - af6: 0000 unimp - af8: 08a8 addi a0,sp,88 - afa: 0000 unimp - afc: 08ac addi a1,sp,88 - afe: 0000 unimp - b00: 08b0 addi a2,sp,88 - b02: 0000 unimp - b04: 08b8 addi a4,sp,88 - b06: 0000 unimp - b08: 08bc addi a5,sp,88 - b0a: 0000 unimp - b0c: 08c0 addi s0,sp,84 - ... - b16: 0000 unimp - b18: 08b8 addi a4,sp,88 - b1a: 0000 unimp - b1c: 08bc addi a5,sp,88 - b1e: 0000 unimp - b20: 08c0 addi s0,sp,84 - b22: 0000 unimp - b24: 0900 addi s0,sp,144 - b26: 0000 unimp - b28: 0904 addi s1,sp,144 - b2a: 0000 unimp - b2c: 0908 addi a0,sp,144 - ... - b36: 0000 unimp - b38: 0900 addi s0,sp,144 - b3a: 0000 unimp - b3c: 0904 addi s1,sp,144 - b3e: 0000 unimp - b40: 0908 addi a0,sp,144 - b42: 0000 unimp - b44: 0944 addi s1,sp,148 - b46: 0000 unimp - b48: 0948 addi a0,sp,148 - b4a: 0000 unimp - b4c: 094c addi a1,sp,148 - ... - b56: 0000 unimp - b58: 0944 addi s1,sp,148 - b5a: 0000 unimp - b5c: 0948 addi a0,sp,148 - b5e: 0000 unimp - b60: 094c addi a1,sp,148 - b62: 0000 unimp - b64: 0984 addi s1,sp,208 - b66: 0000 unimp - b68: 0988 addi a0,sp,208 - b6a: 0000 unimp - b6c: 0990 addi a2,sp,208 - ... - b76: 0000 unimp - b78: 0984 addi s1,sp,208 - b7a: 0000 unimp - b7c: 0988 addi a0,sp,208 - b7e: 0000 unimp - b80: 0990 addi a2,sp,208 - b82: 0000 unimp - b84: 09d0 addi a2,sp,212 - ... - b8e: 0000 unimp - b90: 09d0 addi a2,sp,212 - b92: 0000 unimp - b94: 0a00 addi s0,sp,272 - b96: 0000 unimp - b98: 0a04 addi s1,sp,272 - b9a: 0000 unimp - b9c: 0a08 addi a0,sp,272 - b9e: 0000 unimp - ba0: 0a10 addi a2,sp,272 - ba2: 0000 unimp - ba4: 0a14 addi a3,sp,272 - ba6: 0000 unimp - ba8: 0a18 addi a4,sp,272 - baa: 0000 unimp - bac: 0a1c addi a5,sp,272 - bae: 0000 unimp - bb0: 0a20 addi s0,sp,280 - bb2: 0000 unimp - bb4: 0a28 addi a0,sp,280 - ... - bbe: 0000 unimp - bc0: 0a00 addi s0,sp,272 - bc2: 0000 unimp - bc4: 0a04 addi s1,sp,272 - bc6: 0000 unimp - bc8: 0a08 addi a0,sp,272 - bca: 0000 unimp - bcc: 0a10 addi a2,sp,272 - bce: 0000 unimp - bd0: 0a14 addi a3,sp,272 - bd2: 0000 unimp - bd4: 0a18 addi a4,sp,272 - bd6: 0000 unimp - bd8: 0a28 addi a0,sp,280 - bda: 0000 unimp - bdc: 0a28 addi a0,sp,280 - bde: 0000 unimp - be0: 0a48 addi a0,sp,276 - be2: 0000 unimp - be4: 0a4c addi a1,sp,276 - be6: 0000 unimp - be8: 0a50 addi a2,sp,276 - bea: 0000 unimp - bec: 0a54 addi a3,sp,276 - bee: 0000 unimp - bf0: 0a58 addi a4,sp,276 - bf2: 0000 unimp - bf4: 0a5c addi a5,sp,276 - ... - bfe: 0000 unimp - c00: 0a1c addi a5,sp,272 - c02: 0000 unimp - c04: 0a20 addi s0,sp,280 - c06: 0000 unimp - c08: 0a28 addi a0,sp,280 - c0a: 0000 unimp - c0c: 0a30 addi a2,sp,280 - c0e: 0000 unimp - c10: 0a34 addi a3,sp,280 - c12: 0000 unimp - c14: 0a38 addi a4,sp,280 - c16: 0000 unimp - c18: 0a4c addi a1,sp,276 - c1a: 0000 unimp - c1c: 0a50 addi a2,sp,276 - c1e: 0000 unimp - c20: 0a54 addi a3,sp,276 - c22: 0000 unimp - c24: 0a58 addi a4,sp,276 - c26: 0000 unimp - c28: 0a5c addi a5,sp,276 - c2a: 0000 unimp - c2c: 0a60 addi s0,sp,284 - c2e: 0000 unimp - c30: 0a68 addi a0,sp,284 - c32: 0000 unimp - c34: 0a6c addi a1,sp,284 - ... - c3e: 0000 unimp - c40: 0a30 addi a2,sp,280 - c42: 0000 unimp - c44: 0a34 addi a3,sp,280 - c46: 0000 unimp - c48: 0a38 addi a4,sp,280 - c4a: 0000 unimp - c4c: 0a48 addi a0,sp,276 - c4e: 0000 unimp - c50: 0a60 addi s0,sp,284 - c52: 0000 unimp - c54: 0a68 addi a0,sp,284 - c56: 0000 unimp - c58: 0a6c addi a1,sp,284 - c5a: 0000 unimp - c5c: 0a70 addi a2,sp,284 - c5e: 0000 unimp - c60: 0a74 addi a3,sp,284 - c62: 0000 unimp - c64: 0a78 addi a4,sp,284 - ... - c6e: 0000 unimp - c70: 0a48 addi a0,sp,276 - c72: 0000 unimp - c74: 0a48 addi a0,sp,276 - c76: 0000 unimp - c78: 0a70 addi a2,sp,284 - c7a: 0000 unimp - c7c: 0a74 addi a3,sp,284 - c7e: 0000 unimp - c80: 0a78 addi a4,sp,284 - c82: 0000 unimp - c84: 0a88 addi a0,sp,336 - c86: 0000 unimp - c88: 0a90 addi a2,sp,336 - c8a: 0000 unimp - c8c: 0a94 addi a3,sp,336 - c8e: 0000 unimp - c90: 0aac addi a1,sp,344 - c92: 0000 unimp - c94: 0ab0 addi a2,sp,344 - ... - c9e: 0000 unimp - ca0: 0a88 addi a0,sp,336 - ca2: 0000 unimp - ca4: 0a8c addi a1,sp,336 - ca6: 0000 unimp - ca8: 0ab0 addi a2,sp,344 - caa: 0000 unimp - cac: 0ab8 addi a4,sp,344 - cae: 0000 unimp - cb0: 0abc addi a5,sp,344 - cb2: 0000 unimp - cb4: 0ae4 addi s1,sp,348 - cb6: 0000 unimp - cb8: 0ae4 addi s1,sp,348 - cba: 0000 unimp - cbc: 0ae8 addi a0,sp,348 - ... - cc6: 0000 unimp - cc8: 0a8c addi a1,sp,336 - cca: 0000 unimp - ccc: 0a90 addi a2,sp,336 - cce: 0000 unimp - cd0: 0a94 addi a3,sp,336 - cd2: 0000 unimp - cd4: 0aac addi a1,sp,344 - cd6: 0000 unimp - cd8: 0ab0 addi a2,sp,344 - cda: 0000 unimp - cdc: 0ab0 addi a2,sp,344 - cde: 0000 unimp - ce0: 0ab8 addi a4,sp,344 - ce2: 0000 unimp - ce4: 0abc addi a5,sp,344 - ... - cee: 0000 unimp - cf0: 0ae4 addi s1,sp,348 - cf2: 0000 unimp - cf4: 0ae4 addi s1,sp,348 - cf6: 0000 unimp - cf8: 0ae8 addi a0,sp,348 - cfa: 0000 unimp - cfc: 0af0 addi a2,sp,348 - cfe: 0000 unimp - d00: 0af8 addi a4,sp,348 - d02: 0000 unimp - d04: 0b08 addi a0,sp,400 - d06: 0000 unimp - d08: 0b14 addi a3,sp,400 - d0a: 0000 unimp - d0c: 0b18 addi a4,sp,400 - d0e: 0000 unimp - d10: 0b1c addi a5,sp,400 - d12: 0000 unimp - d14: 0b20 addi s0,sp,408 - ... - d1e: 0000 unimp - d20: 0af0 addi a2,sp,348 - d22: 0000 unimp - d24: 0af8 addi a4,sp,348 - d26: 0000 unimp - d28: 0b08 addi a0,sp,400 - d2a: 0000 unimp - d2c: 0b14 addi a3,sp,400 - d2e: 0000 unimp - d30: 0b18 addi a4,sp,400 - d32: 0000 unimp - d34: 0b1c addi a5,sp,400 - d36: 0000 unimp - d38: 0b20 addi s0,sp,408 - d3a: 0000 unimp - d3c: 0b50 addi a2,sp,404 - d3e: 0000 unimp - d40: 0b54 addi a3,sp,404 - d42: 0000 unimp - d44: 0b5c addi a5,sp,404 - ... - d4e: 0000 unimp - d50: 0c50 addi a2,sp,532 - d52: 0000 unimp - d54: 0c78 addi a4,sp,540 - d56: 0000 unimp - d58: 0c84 addi s1,sp,592 - d5a: 0000 unimp - d5c: 0c90 addi a2,sp,592 - ... - d66: 0000 unimp - d68: 0c90 addi a2,sp,592 - d6a: 0000 unimp - d6c: 0cc8 addi a0,sp,596 - d6e: 0000 unimp - d70: 0ccc addi a1,sp,596 - d72: 0000 unimp - d74: 0cd0 addi a2,sp,596 - ... - d7e: 0000 unimp - d80: 0dcc addi a1,sp,724 - d82: 0000 unimp - d84: 0f8c addi a1,sp,976 - d86: 0000 unimp - d88: 0f94 addi a3,sp,976 - d8a: 0000 unimp - d8c: 0fc4 addi s1,sp,980 - d8e: 0000 unimp - d90: 0fc4 addi s1,sp,980 - d92: 0000 unimp - d94: 0fcc addi a1,sp,980 - ... - d9e: 0000 unimp - da0: 0ddc addi a5,sp,724 - da2: 0000 unimp - da4: 0edc addi a5,sp,852 - da6: 0000 unimp - da8: 0ee0 addi s0,sp,860 - daa: 0000 unimp - dac: 0ee4 addi s1,sp,860 - ... - dbe: 0000 unimp - dc0: 0020 addi s0,sp,8 - dc2: 0000 unimp - dc4: 0028 addi a0,sp,8 - dc6: 0000 unimp - dc8: 002c addi a1,sp,8 - dca: 0000 unimp - dcc: 0030 addi a2,sp,8 - dce: 0000 unimp - dd0: 0040 addi s0,sp,4 - dd2: 0000 unimp - dd4: 004c addi a1,sp,4 - dd6: 0000 unimp - dd8: 005c addi a5,sp,4 - dda: 0000 unimp - ddc: 0078 addi a4,sp,12 - ... - de6: 0000 unimp - de8: 0078 addi a4,sp,12 - dea: 0000 unimp - dec: 00a4 addi s1,sp,72 - dee: 0000 unimp - df0: 00ac addi a1,sp,72 - df2: 0000 unimp - df4: 00b0 addi a2,sp,72 - df6: 0000 unimp - df8: 00c8 addi a0,sp,68 - dfa: 0000 unimp - dfc: 00cc addi a1,sp,68 - ... - e06: 0000 unimp - e08: 00a4 addi s1,sp,72 - e0a: 0000 unimp - e0c: 00ac addi a1,sp,72 - e0e: 0000 unimp - e10: 00b0 addi a2,sp,72 - e12: 0000 unimp - e14: 00c8 addi a0,sp,68 - e16: 0000 unimp - e18: 00cc addi a1,sp,68 - e1a: 0000 unimp - e1c: 00e0 addi s0,sp,76 - e1e: 0000 unimp - e20: 01e4 addi s1,sp,204 - e22: 0000 unimp - e24: 01e8 addi a0,sp,204 - e26: 0000 unimp - e28: 0814 addi a3,sp,16 - e2a: 0000 unimp - e2c: 0818 addi a4,sp,16 - e2e: 0000 unimp - e30: 0b10 addi a2,sp,400 - e32: 0000 unimp - e34: 0b14 addi a3,sp,400 - e36: 0000 unimp - e38: 0fc4 addi s1,sp,980 - e3a: 0000 unimp - e3c: 0fc8 addi a0,sp,980 - ... - e46: 0000 unimp - e48: 00e0 addi s0,sp,76 - e4a: 0000 unimp - e4c: 010c addi a1,sp,128 - e4e: 0000 unimp - e50: 0114 addi a3,sp,128 - e52: 0000 unimp - e54: 011c addi a5,sp,128 - ... - e5e: 0000 unimp - e60: 0148 addi a0,sp,132 - e62: 0000 unimp - e64: 016c addi a1,sp,140 - e66: 0000 unimp - e68: 0188 addi a0,sp,192 - e6a: 0000 unimp - e6c: 01e4 addi s1,sp,204 - e6e: 0000 unimp - e70: 01e8 addi a0,sp,204 - e72: 0000 unimp - e74: 0224 addi s1,sp,264 - e76: 0000 unimp - e78: 0244 addi s1,sp,260 - e7a: 0000 unimp - e7c: 0498 addi a4,sp,576 - e7e: 0000 unimp - e80: 0604 addi s1,sp,768 - e82: 0000 unimp - e84: 0814 addi a3,sp,16 - e86: 0000 unimp - e88: 0818 addi a4,sp,16 - e8a: 0000 unimp - e8c: 098c addi a1,sp,208 - e8e: 0000 unimp - e90: 098c addi a1,sp,208 - e92: 0000 unimp - e94: 09c0 addi s0,sp,212 - e96: 0000 unimp - e98: 09dc addi a5,sp,212 - e9a: 0000 unimp - e9c: 0a7c addi a5,sp,284 - ... - ea6: 0000 unimp - ea8: 0260 addi s0,sp,268 - eaa: 0000 unimp - eac: 034c addi a1,sp,388 - eae: 0000 unimp - eb0: 0350 addi a2,sp,388 - eb2: 0000 unimp - eb4: 0354 addi a3,sp,388 - ... - ebe: 0000 unimp - ec0: 03e0 addi s0,sp,460 - ec2: 0000 unimp - ec4: 03e4 addi s1,sp,460 - ec6: 0000 unimp - ec8: 03e8 addi a0,sp,460 - eca: 0000 unimp - ecc: 0430 addi a2,sp,520 - ... - ed6: 0000 unimp - ed8: 03e0 addi s0,sp,460 - eda: 0000 unimp - edc: 03e4 addi s1,sp,460 - ede: 0000 unimp - ee0: 03e8 addi a0,sp,460 - ee2: 0000 unimp - ee4: 0420 addi s0,sp,520 - ee6: 0000 unimp - ee8: 0420 addi s0,sp,520 - eea: 0000 unimp - eec: 0424 addi s1,sp,520 - ... - ef6: 0000 unimp - ef8: 06dc addi a5,sp,836 - efa: 0000 unimp - efc: 07e0 addi s0,sp,972 - efe: 0000 unimp - f00: 07e4 addi s1,sp,972 - f02: 0000 unimp - f04: 07e8 addi a0,sp,972 - ... - f0e: 0000 unimp - f10: 07f0 addi a2,sp,972 - f12: 0000 unimp - f14: 0814 addi a3,sp,16 - f16: 0000 unimp - f18: 0818 addi a4,sp,16 - f1a: 0000 unimp - f1c: 085c addi a5,sp,20 - ... - f26: 0000 unimp - f28: 08e0 addi s0,sp,92 - f2a: 0000 unimp - f2c: 0924 addi s1,sp,152 - f2e: 0000 unimp - f30: 092c addi a1,sp,152 - f32: 0000 unimp - f34: 0934 addi a3,sp,152 - ... - f3e: 0000 unimp - f40: 0a24 addi s1,sp,280 - f42: 0000 unimp - f44: 0a48 addi a0,sp,276 - f46: 0000 unimp - f48: 0a54 addi a3,sp,276 - f4a: 0000 unimp - f4c: 0a60 addi s0,sp,284 - ... - f56: 0000 unimp - f58: 016c addi a1,sp,140 - f5a: 0000 unimp - f5c: 0188 addi a0,sp,192 - f5e: 0000 unimp - f60: 0224 addi s1,sp,264 - f62: 0000 unimp - f64: 0244 addi s1,sp,260 - f66: 0000 unimp - f68: 0498 addi a4,sp,576 - f6a: 0000 unimp - f6c: 0498 addi a4,sp,576 - f6e: 0000 unimp - f70: 09c0 addi s0,sp,212 - f72: 0000 unimp - f74: 09dc addi a5,sp,212 - f76: 0000 unimp - f78: 0a7c addi a5,sp,284 - f7a: 0000 unimp - f7c: 0b10 addi a2,sp,400 - f7e: 0000 unimp - f80: 0b14 addi a3,sp,400 - f82: 0000 unimp - f84: 0fc4 addi s1,sp,980 - f86: 0000 unimp - f88: 0fc8 addi a0,sp,980 - f8a: 0000 unimp - f8c: 11ac addi a1,sp,232 - f8e: 0000 unimp - f90: 11ac addi a1,sp,232 - f92: 0000 unimp - f94: 150c addi a1,sp,672 - ... - f9e: 0000 unimp - fa0: 023c addi a5,sp,264 - fa2: 0000 unimp - fa4: 0244 addi s1,sp,260 - fa6: 0000 unimp - fa8: 0cec addi a1,sp,604 - faa: 0000 unimp - fac: 0d00 addi s0,sp,656 - fae: 0000 unimp - fb0: 12a0 addi s0,sp,360 - fb2: 0000 unimp - fb4: 1300 addi s0,sp,416 - fb6: 0000 unimp - fb8: 1314 addi a3,sp,416 - fba: 0000 unimp - fbc: 150c addi a1,sp,672 - ... - fc6: 0000 unimp - fc8: 12b0 addi a2,sp,360 - fca: 0000 unimp - fcc: 1300 addi s0,sp,416 - fce: 0000 unimp - fd0: 1358 addi a4,sp,420 - fd2: 0000 unimp - fd4: 13b8 addi a4,sp,488 - ... - fde: 0000 unimp - fe0: 13c4 addi s1,sp,484 - fe2: 0000 unimp - fe4: 14e4 addi s1,sp,620 - fe6: 0000 unimp - fe8: 14e8 addi a0,sp,620 - fea: 0000 unimp - fec: 14f0 addi a2,sp,620 - ... - ff6: 0000 unimp - ff8: 13c4 addi s1,sp,484 - ffa: 0000 unimp - ffc: 14dc addi a5,sp,612 - ffe: 0000 unimp - 1000: 14e0 addi s0,sp,620 - 1002: 0000 unimp - 1004: 14e4 addi s1,sp,620 - ... - 100e: 0000 unimp - 1010: 09c0 addi s0,sp,212 - 1012: 0000 unimp - 1014: 09c4 addi s1,sp,212 - 1016: 0000 unimp - 1018: 09cc addi a1,sp,212 - 101a: 0000 unimp - 101c: 09d4 addi a3,sp,212 - 101e: 0000 unimp - 1020: 09d8 addi a4,sp,212 - 1022: 0000 unimp - 1024: 09dc addi a5,sp,212 - 1026: 0000 unimp - 1028: 11bc addi a5,sp,232 - 102a: 0000 unimp - 102c: 11e4 addi s1,sp,236 - ... - 1036: 0000 unimp - 1038: 0b6c addi a1,sp,412 - 103a: 0000 unimp - 103c: 0c58 addi a4,sp,532 - 103e: 0000 unimp - 1040: 0c5c addi a5,sp,532 - 1042: 0000 unimp - 1044: 0c60 addi s0,sp,540 - ... - 104e: 0000 unimp - 1050: 0d58 addi a4,sp,660 - 1052: 0000 unimp - 1054: 0db4 addi a3,sp,728 - 1056: 0000 unimp - 1058: 0db8 addi a4,sp,728 - 105a: 0000 unimp - 105c: 0dc4 addi s1,sp,724 - ... - 1066: 0000 unimp - 1068: 0e3c addi a5,sp,792 - 106a: 0000 unimp - 106c: 0e90 addi a2,sp,848 - 106e: 0000 unimp - 1070: 0e98 addi a4,sp,848 - 1072: 0000 unimp - 1074: 0f58 addi a4,sp,916 - ... - 107e: 0000 unimp - 1080: 0e3c addi a5,sp,792 - 1082: 0000 unimp - 1084: 0e90 addi a2,sp,848 - 1086: 0000 unimp - 1088: 0e98 addi a4,sp,848 - 108a: 0000 unimp - 108c: 0f48 addi a0,sp,916 - 108e: 0000 unimp - 1090: 0f4c addi a1,sp,916 - 1092: 0000 unimp - 1094: 0f50 addi a2,sp,916 - ... - 109e: 0000 unimp - 10a0: 0f58 addi a4,sp,916 - 10a2: 0000 unimp - 10a4: 0fc4 addi s1,sp,980 - 10a6: 0000 unimp - 10a8: 0fc8 addi a0,sp,980 - 10aa: 0000 unimp - 10ac: 0fd4 addi a3,sp,980 - ... - 10b6: 0000 unimp - 10b8: 0498 addi a4,sp,576 - 10ba: 0000 unimp - 10bc: 0588 addi a0,sp,704 - 10be: 0000 unimp - 10c0: 150c addi a1,sp,672 - 10c2: 0000 unimp - 10c4: 1520 addi s0,sp,680 - ... - 10ce: 0000 unimp - 10d0: 0518 addi a4,sp,640 - 10d2: 0000 unimp - 10d4: 0544 addi s1,sp,644 - 10d6: 0000 unimp - 10d8: 0548 addi a0,sp,644 - 10da: 0000 unimp - 10dc: 0550 addi a2,sp,644 - ... - 10e6: 0000 unimp - 10e8: 0588 addi a0,sp,704 - 10ea: 0000 unimp - 10ec: 05b0 addi a2,sp,712 - 10ee: 0000 unimp - 10f0: 05b4 addi a3,sp,712 - 10f2: 0000 unimp - 10f4: 05bc addi a5,sp,712 - 10f6: 0000 unimp - 10f8: 05c4 addi s1,sp,708 - 10fa: 0000 unimp - 10fc: 05cc addi a1,sp,708 - ... - 110e: 0000 unimp - 1110: 0014 0x14 - 1112: 0000 unimp - 1114: 002c addi a1,sp,8 - 1116: 0000 unimp - 1118: 0030 addi a2,sp,8 - 111a: 0000 unimp - 111c: 0044 addi s1,sp,4 - ... - 1126: 0000 unimp - 1128: 0078 addi a4,sp,12 - 112a: 0000 unimp - 112c: 0084 addi s1,sp,64 - 112e: 0000 unimp - 1130: 0088 addi a0,sp,64 - 1132: 0000 unimp - 1134: 00d0 addi a2,sp,68 - 1136: 0000 unimp - 1138: 00e0 addi s0,sp,76 - 113a: 0000 unimp - 113c: 0150 addi a2,sp,132 - ... - 114e: 0000 unimp - 1150: 0018 0x18 - 1152: 0000 unimp - 1154: 0100 addi s0,sp,128 - 1156: 0000 unimp - 1158: 0170 addi a2,sp,140 - 115a: 0000 unimp - 115c: 0188 addi a0,sp,192 - ... - 1166: 0000 unimp - 1168: 0028 addi a0,sp,8 - 116a: 0000 unimp - 116c: 002c addi a1,sp,8 - 116e: 0000 unimp - 1170: 0030 addi a2,sp,8 - 1172: 0000 unimp - 1174: 0040 addi s0,sp,4 - ... - 117e: 0000 unimp - 1180: 0100 addi s0,sp,128 - 1182: 0000 unimp - 1184: 0128 addi a0,sp,136 - 1186: 0000 unimp - 1188: 012c addi a1,sp,136 - 118a: 0000 unimp - 118c: 0134 addi a3,sp,136 - 118e: 0000 unimp - 1190: 014c addi a1,sp,132 - 1192: 0000 unimp - 1194: 0154 addi a3,sp,132 - ... - 11a2: 0000 unimp - 11a4: 000c 0xc - 11a6: 0000 unimp - 11a8: 0010 0x10 - 11aa: 0000 unimp - 11ac: 0014 0x14 - 11ae: 0000 unimp - 11b0: 003c addi a5,sp,8 - 11b2: 0000 unimp - 11b4: 0040 addi s0,sp,4 - ... - 11be: 0000 unimp - 11c0: 004c addi a1,sp,4 - 11c2: 0000 unimp - 11c4: 0050 addi a2,sp,4 - 11c6: 0000 unimp - 11c8: 0054 addi a3,sp,4 - 11ca: 0000 unimp - 11cc: 0074 addi a3,sp,12 - ... - 11d6: 0000 unimp - 11d8: 0074 addi a3,sp,12 - 11da: 0000 unimp - 11dc: 009c addi a5,sp,64 - 11de: 0000 unimp - 11e0: 00a0 addi s0,sp,72 - 11e2: 0000 unimp - 11e4: 00a8 addi a0,sp,72 - 11e6: 0000 unimp - 11e8: 00b0 addi a2,sp,72 - 11ea: 0000 unimp - 11ec: 00b8 addi a4,sp,72 - ... - 11f6: 0000 unimp - 11f8: 00f8 addi a4,sp,76 - 11fa: 0000 unimp - 11fc: 0148 addi a0,sp,132 - 11fe: 0000 unimp - 1200: 0160 addi s0,sp,140 - 1202: 0000 unimp - 1204: 019c addi a5,sp,192 - 1206: 0000 unimp - 1208: 01ac addi a1,sp,200 - 120a: 0000 unimp - 120c: 01d0 addi a2,sp,196 - ... - 1216: 0000 unimp - 1218: 01d8 addi a4,sp,196 - 121a: 0000 unimp - 121c: 01ec addi a1,sp,204 - 121e: 0000 unimp - 1220: 01f0 addi a2,sp,204 - 1222: 0000 unimp - 1224: 01f4 addi a3,sp,204 - 1226: 0000 unimp - 1228: 01f8 addi a4,sp,204 - 122a: 0000 unimp - 122c: 0200 addi s0,sp,256 - ... - 123e: 0000 unimp - 1240: 0014 0x14 - 1242: 0000 unimp - 1244: 0048 addi a0,sp,4 - ... - 124e: 0000 unimp - 1250: 0048 addi a0,sp,4 - 1252: 0000 unimp - 1254: 0074 addi a3,sp,12 - 1256: 0000 unimp - 1258: 0078 addi a4,sp,12 - 125a: 0000 unimp - 125c: 007c addi a5,sp,12 - 125e: 0000 unimp - 1260: 0084 addi s1,sp,64 - 1262: 0000 unimp - 1264: 0088 addi a0,sp,64 - ... - 126e: 0000 unimp - 1270: 00a8 addi a0,sp,72 - 1272: 0000 unimp - 1274: 00d8 addi a4,sp,68 - 1276: 0000 unimp - 1278: 00dc addi a5,sp,68 - 127a: 0000 unimp - 127c: 00e0 addi s0,sp,76 - ... - 1286: 0000 unimp - 1288: 00ec addi a1,sp,76 - 128a: 0000 unimp - 128c: 0114 addi a3,sp,128 - 128e: 0000 unimp - 1290: 02a4 addi s1,sp,328 - 1292: 0000 unimp - 1294: 02f4 addi a3,sp,332 - 1296: 0000 unimp - 1298: 0328 addi a0,sp,392 - 129a: 0000 unimp - 129c: 0334 addi a3,sp,392 - ... - 12a6: 0000 unimp - 12a8: 0124 addi s1,sp,136 - 12aa: 0000 unimp - 12ac: 0128 addi a0,sp,136 - 12ae: 0000 unimp - 12b0: 0138 addi a4,sp,136 - 12b2: 0000 unimp - 12b4: 013c addi a5,sp,136 - 12b6: 0000 unimp - 12b8: 0144 addi s1,sp,132 - 12ba: 0000 unimp - 12bc: 0240 addi s0,sp,260 - ... - 12c6: 0000 unimp - 12c8: 0138 addi a4,sp,136 - 12ca: 0000 unimp - 12cc: 013c addi a5,sp,136 - 12ce: 0000 unimp - 12d0: 0144 addi s1,sp,132 - 12d2: 0000 unimp - 12d4: 01b0 addi a2,sp,200 - 12d6: 0000 unimp - 12d8: 01b4 addi a3,sp,200 - 12da: 0000 unimp - 12dc: 01b8 addi a4,sp,200 - 12de: 0000 unimp - 12e0: 01c0 addi s0,sp,196 - 12e2: 0000 unimp - 12e4: 0240 addi s0,sp,260 - ... - 12ee: 0000 unimp - 12f0: 026c addi a1,sp,268 - 12f2: 0000 unimp - 12f4: 026c addi a1,sp,268 - 12f6: 0000 unimp - 12f8: 026c addi a1,sp,268 - 12fa: 0000 unimp - 12fc: 027c addi a5,sp,268 - 12fe: 0000 unimp - 1300: 0280 addi s0,sp,320 - 1302: 0000 unimp - 1304: 0288 addi a0,sp,320 - ... - 1312: 0000 unimp - 1314: 0014 0x14 - 1316: 0000 unimp - 1318: 0014 0x14 - 131a: 0000 unimp - 131c: 0030 addi a2,sp,8 - 131e: 0000 unimp - 1320: 0038 addi a4,sp,8 - 1322: 0000 unimp - 1324: 004c addi a1,sp,4 - ... diff --git a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.elf b/miscs/rvvector/benchmark_temp/vx_vec_benchmark.elf deleted file mode 100755 index a57a47db..00000000 Binary files a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.elf and /dev/null differ diff --git a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.h b/miscs/rvvector/benchmark_temp/vx_vec_benchmark.h deleted file mode 100644 index cd5a1c3f..00000000 --- a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.h +++ /dev/null @@ -1,16 +0,0 @@ -#pragma once - - -#ifdef __cplusplus -extern "C" { -#endif - -//void vx_vec_vvaddint32(int n, int* a, int* b, int *c); -//void vx_vec_vsadd(int n, int* a, int scalar); -//void vx_vec_memcpy(int* a, int* b, int n); -void vx_vec_saxpy(int n, int scalar, int* a, int* b); -//void vx_vec_sgemm_nn(int n, int m, int k, int* a1, int lda, int* b1, int ldb, int* c1, int ldc); - -#ifdef __cplusplus -} -#endif diff --git a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.hex b/miscs/rvvector/benchmark_temp/vx_vec_benchmark.hex deleted file mode 100644 index d1750791..00000000 --- a/miscs/rvvector/benchmark_temp/vx_vec_benchmark.hex +++ /dev/null @@ -1,5595 +0,0 @@ -:0200000480007A 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-:106D2800000000100000002068630180FFFFFFFFE3 -:046D38000000020055 -:040000058000000077 -:00000001FF diff --git a/miscs/rvvector/benchmark_temp/vx_vec_memcpy.s b/miscs/rvvector/benchmark_temp/vx_vec_memcpy.s deleted file mode 100644 index 8edbe844..00000000 --- a/miscs/rvvector/benchmark_temp/vx_vec_memcpy.s +++ /dev/null @@ -1,17 +0,0 @@ -.type vx_vec_memcpy, @function -.global vx_vec_memcpy -# void *memcpy(void* dest, const void* src, size_t n) -# a0=dest, a1=src, a2=n -# -vx_vec_memcpy: -# memcpy - mv a3, a0 # Copy destination - vsetvli t0, a2, e8,m8 # Vectors of 8b -loop: - vlb.v v0, (a1) # Load bytes - add a1, a1, t0 # Bump pointer - sub a2, a2, t0 # Decrement count - vsb.v v0, (a3) # Store bytes - add a3, a3, t0 # Bump pointer - bnez a2, loop # Any more? - ret # Return \ No newline at end of file diff --git a/miscs/rvvector/benchmark_temp/vx_vec_saxpy.s b/miscs/rvvector/benchmark_temp/vx_vec_saxpy.s deleted file mode 100644 index be0f280b..00000000 --- a/miscs/rvvector/benchmark_temp/vx_vec_saxpy.s +++ /dev/null @@ -1,62 +0,0 @@ -.type vx_vec_saxpy, @function -.global vx_vec_saxpy -# void -# saxpy(size_t n, const float a, const float *x, float *y) -# { -# size_t i; -# for (i=0; i $(PROJECT).dump - -$(PROJECT).hex: $(PROJECT).elf - $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex - -$(PROJECT).elf: $(SRCS) - $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf - -.depend: $(SRCS) - $(CC) $(CFLAGS) -MM $^ > .depend; - -clean: - rm -rf *.elf *.hex *.dump .depend diff --git a/miscs/rvvector/vector_test/vx_vec.h b/miscs/rvvector/vector_test/vx_vec.h deleted file mode 100644 index b9a32ace..00000000 --- a/miscs/rvvector/vector_test/vx_vec.h +++ /dev/null @@ -1,13 +0,0 @@ -#pragma once - - -#ifdef __cplusplus -extern "C" { -#endif - -void vx_vec_test(int n, int* a, int* b, int* c); //vvaddint32 -//void vx_vec_test(int*); - -#ifdef __cplusplus -} -#endif \ No newline at end of file diff --git a/miscs/rvvector/vector_test/vx_vec.s b/miscs/rvvector/vector_test/vx_vec.s deleted file mode 100644 index d06a70da..00000000 --- a/miscs/rvvector/vector_test/vx_vec.s +++ /dev/null @@ -1,23 +0,0 @@ -.type vx_vec_test, @function -.global vx_vec_test -vx_vec_test: -# vector-vector add routine of 32-bit integers -# void vvaddint32(size_t n, const int*x, const int*y, int*z) -# { for (size_t i=0; i -#include "vx_vec.h" - -int main() { - vx_tmc(1); - - int n = 32; - int *a = (int*)malloc(sizeof(int) * n); //{1, 1, 1, 1, 1}; - int *b = (int*)malloc(sizeof(int) * n); //{1, 1, 1, 1, 1}; - int *c = (int*)malloc(sizeof(int) * n); //{1, 1, 1, 1, 1}; - - for(int i = 0; i < n; ++i) { - a[i] = 1; - b[i] = 1; - c[i] = 1; - } - - vx_vec_test(n, a, b, c); - for (int i = 0; i < n; ++i) { - vx_printf("%d", c[i]); - } - - vx_tmc(0); -} diff --git a/perf/.gitignore b/perf/.gitignore new file mode 100644 index 00000000..a9884992 --- /dev/null +++ b/perf/.gitignore @@ -0,0 +1 @@ +**/*.log diff --git a/perf/cache/cache_perf.log b/perf/cache/cache_perf.log new file mode 100644 index 00000000..21a446d2 --- /dev/null +++ b/perf/cache/cache_perf.log @@ -0,0 +1,3 @@ +CONFIGS=-DNUM_CLUSTERS=1 -DNUM_CORES=1 -DNUM_WARPS=2 -DNUM_THREADS=2 -DPERF_ENABLE -DICACHE_NUM_WAYS=1 +running: CONFIGS=-DNUM_CLUSTERS=1 -DNUM_CORES=1 -DNUM_WARPS=2 -DNUM_THREADS=2 -DPERF_ENABLE -DICACHE_NUM_WAYS=1 make -C ./ci/../driver/rtlsim +verilator --build --exe --cc Vortex --top-module Vortex --language 1800-2009 --assert -Wall -Wpedantic -Wno-DECLFILENAME -Wno-REDEFMACRO --x-initial unique --x-assign unique verilator.vlt -I../../hw/rtl -I../../hw/dpi -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache -I../../hw/rtl/simulate -I../../hw/rtl/fp_cores -I../../third_party/fpnew/src/common_cells/include -I../../third_party/fpnew/src/common_cells/src -I../../third_party/fpnew/src/fpu_div_sqrt_mvp/hdl -I../../third_party/fpnew/src -I../../hw/rtl/tex_unit -I../../hw/rtl/raster_unit -I../../hw/rtl/rop_unit -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DNUM_WARPS=2 -DNUM_THREADS=2 -DPERF_ENABLE -DICACHE_NUM_WAYS=1 -j 64 -DNDEBUG -DIMUL_DPI -DIDIV_DPI -DFPU_DPI ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp ../../hw/dpi/util_dpi.cpp ../../hw/dpi/float_dpi.cpp processor.cpp -CFLAGS '-std=c++11 -Wall -Wextra -Wfatal-errors -Wno-array-bounds -fPIC -Wno-maybe-uninitialized -I../../../hw -I../../common -I../../../third_party/softfloat/source/include -I../../../third_party -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DNUM_WARPS=2 -DNUM_THREADS=2 -DPERF_ENABLE -DICACHE_NUM_WAYS=1 -O2 -DNDEBUG' -LDFLAGS '-shared ../../../third_party/softfloat/build/Linux-x86_64-GCC/softfloat.a -L../../../third_party/ramulator -lramulator' -o ../../../driver/rtlsim/librtlsim.so diff --git a/perf/cache/run.sh b/perf/cache/run.sh new file mode 100755 index 00000000..ffb86e34 --- /dev/null +++ b/perf/cache/run.sh @@ -0,0 +1,41 @@ +#!/bin/bash + +# exit when any command fails +set -e + +# ensure build +make -s + +sgemm() +{ +echo "begin cache tests" + +CONFIGS="-DICACHE_NUM_WAYS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemm --args="-n64" --perf=1 | grep 'PERF' > ./perf/cache/cache_perf.log +echo -e "\n**************************************\n" >> ./perf/cache/cache_perf.log +CONFIGS="-DDCACHE_NUM_WAYS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemm --args="-n64" --perf=1 | grep 'PERF' >> ./perf/cache/cache_perf.log +echo -e "\n**************************************\n" >> ./perf/cache/cache_perf.log +CONFIGS="-DICACHE_NUM_WAYS=4" ./ci/blackbox.sh --driver=rtlsim --app=sgemm --args="-n64" --perf=1 | grep 'PERF' >> ./perf/cache/cache_perf.log +echo -e "\n**************************************\n" >> ./perf/cache/cache_perf.log +CONFIGS="-DDCACHE_NUM_WAYS=4" ./ci/blackbox.sh --driver=rtlsim --app=sgemm --args="-n64" --perf=1 | grep 'PERF' >> ./perf/cache/cache_perf.log +echo -e "\n**************************************\n" >> ./perf/cache/cache_perf.log +CONFIGS="-DICACHE_NUM_WAYS=8" ./ci/blackbox.sh --driver=rtlsim --app=sgemm --args="-n64" --perf=1 | grep 'PERF' >> ./perf/cache/cache_perf.log +echo -e "\n**************************************\n" >> ./perf/cache/cache_perf.log +CONFIGS="-DDCACHE_NUM_WAYS=8" ./ci/blackbox.sh --driver=rtlsim --app=sgemm --args="-n64" --perf=1 | grep 'PERF' >> ./perf/cache/cache_perf.log + +echo "cache tests done!" +} + +usage() +{ + echo "usage: [-s] [-h|--help]" +} + +case $1 in + -s ) sgemm + ;; + -h | --help ) usage + ;; + * ) sgemm + ;; +esac +shift \ No newline at end of file diff --git a/runtime/Makefile b/runtime/Makefile index 4c0241aa..19037d09 100644 --- a/runtime/Makefile +++ b/runtime/Makefile @@ -1,49 +1,25 @@ -XLEN ?= 32 +all: stub rtlsim simx opae -ifeq ($(XLEN),32) -RISCV_TOOLCHAIN_PATH = /opt/riscv-gnu-toolchain -else -RISCV_TOOLCHAIN_PATH = /opt/riscv64-gnu-toolchain -endif +stub: + $(MAKE) -C stub -RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- +simx: + $(MAKE) -C simx -CC = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)gcc -AR = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)gcc-ar -DP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)objdump -CP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)objcopy +rtlsim: + $(MAKE) -C rtlsim -ifeq ($(XLEN),32) -CFLAGS += -march=rv32imf -mabi=ilp32f -else -CFLAGS += -march=rv64imfd -mabi=lp64d -endif +opae: + $(MAKE) -C opae -CFLAGS += -O3 -mcmodel=medany -Wstack-usage=1024 -fno-exceptions -fdata-sections -ffunction-sections -CFLAGS += -I./include -I../hw - -PROJECT = libvortexrt - -SRCS = ./src/vx_start.S ./src/vx_syscalls.c ./src/vx_print.S ./src/tinyprintf.c ./src/vx_print.c ./src/vx_spawn.c ./src/vx_spawn.S ./src/vx_perf.c - -OBJS := $(addsuffix .o, $(notdir $(SRCS))) - -all: $(PROJECT).a $(PROJECT).dump - -$(PROJECT).dump: $(PROJECT).a - $(DP) -D $(PROJECT).a > $(PROJECT).dump - -%.S.o: src/%.S - $(CC) $(CFLAGS) -c $< -o $@ - -%.c.o: src/%.c - $(CC) $(CFLAGS) -c $< -o $@ - -$(PROJECT).a: $(OBJS) - $(AR) rcs $@ $^ - -.depend: $(SRCS) - $(CC) $(CFLAGS) -MM $^ > .depend; +xrt: + $(MAKE) -C xrt clean: - rm -rf *.a *.o *.dump .depend \ No newline at end of file + $(MAKE) clean -C stub + $(MAKE) clean -C simx + $(MAKE) clean -C rtlsim + $(MAKE) clean -C opae + $(MAKE) clean -C xrt + +.PHONY: all stub simx rtlsim opae xrt clean \ No newline at end of file diff --git a/driver/common/vx_malloc.h b/runtime/common/malloc.h similarity index 79% rename from driver/common/vx_malloc.h rename to runtime/common/malloc.h index 650a2f80..52357568 100644 --- a/driver/common/vx_malloc.h +++ b/runtime/common/malloc.h @@ -1,22 +1,38 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #pragma once #include #include +#include namespace vortex { class MemoryAllocator { public: MemoryAllocator( - uint64_t minAddress, - uint64_t maxAddress, + uint64_t baseAddress, + uint64_t capacity, uint32_t pageAlign, uint32_t blockAlign) - : nextAddress_(minAddress) - , maxAddress_(maxAddress) + : baseAddress_(baseAddress) + , capacity_(capacity) , pageAlign_(pageAlign) , blockAlign_(blockAlign) , pages_(nullptr) + , nextAddress_(0) + , allocated_(0) {} ~MemoryAllocator() { @@ -28,10 +44,28 @@ public: currPage = nextPage; } } + + uint32_t baseAddress() const { + return baseAddress_; + } + + uint32_t capacity() const { + return capacity_; + } + + uint64_t free() const { + return (capacity_ - allocated_); + } + + uint64_t allocated() const { + return allocated_; + } int allocate(uint64_t size, uint64_t* addr) { - if (size == 0 || addr == nullptr) + if (size == 0 || addr == nullptr) { + printf("error: invalid argurments\n"); return -1; + } // Align allocation size size = AlignSize(size, blockAlign_); @@ -61,15 +95,17 @@ public: if (nullptr == freeBlock) { // Allocate a new page for this request currPage = this->NewPage(size); - if (nullptr == currPage) + if (nullptr == currPage) { + printf("error: out of memory\n"); return -1; + } freeBlock = currPage->freeSList; } // Remove the block from the free lists assert(freeBlock->size >= size); - currPage->RemoveFreeMBlock(freeBlock); - currPage->RemoveFreeSBlock(freeBlock); + currPage->RemoveFreeMList(freeBlock); + currPage->RemoveFreeSList(freeBlock); // If the free block we have found is larger than what we are looking for, // we may be able to split our free block in two. @@ -83,29 +119,33 @@ public: auto newBlock = new block_t(nextAddr, extraBytes); // Add the new block to the free lists - currPage->InsertFreeMBlock(newBlock); - currPage->InsertFreeSBlock(newBlock); + currPage->InsertFreeMList(newBlock); + currPage->InsertFreeSList(newBlock); } // Insert the free block into the used list - currPage->InsertUsedBlock(freeBlock); + currPage->InsertUsedList(freeBlock); // Return the free block address - *addr = freeBlock->addr; + *addr = baseAddress_ + freeBlock->addr; + + // Update allocated size + allocated_ += size; return 0; } int release(uint64_t addr) { // Walk all pages to find the pointer + uint64_t local_addr = addr - baseAddress_; block_t* usedBlock = nullptr; auto currPage = pages_; while (currPage) { - if (addr >= currPage->addr - && addr < (currPage->addr + currPage->size)) { + if (local_addr >= currPage->addr + && local_addr < (currPage->addr + currPage->size)) { auto currBlock = currPage->usedList; while (currBlock) { - if (currBlock->addr == addr) { + if (currBlock->addr == local_addr) { usedBlock = currBlock; break; } @@ -117,14 +157,18 @@ public: } // found the corresponding block? - if (nullptr == usedBlock) + if (nullptr == usedBlock) { + printf("error: invalid address to release: 0x%lx\n", addr); return -1; + } + + auto size = usedBlock->size; // Remove the block from the used list - currPage->RemoveUsedBlock(usedBlock); + currPage->RemoveUsedList(usedBlock); // Insert the block into the free M-list. - currPage->InsertFreeMBlock(usedBlock); + currPage->InsertFreeMList(usedBlock); // Check if we can merge adjacent free blocks from the left. if (usedBlock->prevFreeM) { @@ -141,7 +185,7 @@ public: } // Detach previous block from the free S-list since size increased - currPage->RemoveFreeSBlock(prevBlock); + currPage->RemoveFreeSList(prevBlock); // reset usedBlock delete usedBlock; @@ -164,23 +208,26 @@ public: } // Delete next block - currPage->RemoveFreeSBlock(nextBlock); + currPage->RemoveFreeSList(nextBlock); delete nextBlock; } } // Insert the block into the free S-list. - currPage->InsertFreeSBlock(usedBlock); + currPage->InsertFreeSList(usedBlock); // Check if we can free empty pages if (nullptr == currPage->usedList) { // Try to delete the page while (currPage && this->DeletePage(currPage)) { - currPage = this->NextEmptyPage(); + currPage = this->FindNextEmptyPage(); } } + // update allocated size + allocated_ -= size; + return 0; } @@ -236,7 +283,7 @@ private: freeSList = freeMList = new block_t(addr, size); } - void InsertUsedBlock(block_t* block) { + void InsertUsedList(block_t* block) { block->nextUsed = usedList; if (usedList) { usedList->prevUsed = block; @@ -244,7 +291,7 @@ private: usedList = block; } - void RemoveUsedBlock(block_t* block) { + void RemoveUsedList(block_t* block) { if (block->prevUsed) { block->prevUsed->nextUsed = block->nextUsed; } else { @@ -257,7 +304,7 @@ private: block->prevUsed = nullptr; } - void InsertFreeMBlock(block_t* block) { + void InsertFreeMList(block_t* block) { block_t* currBlock = freeMList; block_t* prevBlock = nullptr; while (currBlock && (currBlock->addr < block->addr)) { @@ -276,7 +323,7 @@ private: } } - void RemoveFreeMBlock(block_t* block) { + void RemoveFreeMList(block_t* block) { if (block->prevFreeM) { block->prevFreeM->nextFreeM = block->nextFreeM; } else { @@ -289,7 +336,7 @@ private: block->prevFreeM = nullptr; } - void InsertFreeSBlock(block_t* block) { + void InsertFreeSList(block_t* block) { block_t* currBlock = this->freeSList; block_t* prevBlock = nullptr; while (currBlock && (currBlock->size > block->size)) { @@ -308,7 +355,7 @@ private: } } - void RemoveFreeSBlock(block_t* block) { + void RemoveFreeSList(block_t* block) { if (block->prevFreeS) { block->prevFreeS->nextFreeS = block->nextFreeS; } else { @@ -324,7 +371,7 @@ private: page_t* NewPage(uint64_t size) { // Increase buffer size to include the page and first block size - // also add padding to ensure page aligment + // also add padding to ensure page alignment size = AlignSize(size, pageAlign_); // Allocate page memory @@ -332,7 +379,7 @@ private: nextAddress_ += size; // Overflow check - if (nextAddress_ > maxAddress_) + if (nextAddress_ > capacity_) return nullptr; // Allocate object @@ -381,7 +428,7 @@ private: return true; } - page_t* NextEmptyPage() { + page_t* FindNextEmptyPage() { auto currPage = pages_; while (currPage) { if (nullptr == currPage->usedList) @@ -396,11 +443,13 @@ private: return (size + alignment - 1) & ~(alignment - 1); } - uint64_t nextAddress_; - uint64_t maxAddress_; + uint64_t baseAddress_; + uint64_t capacity_; uint32_t pageAlign_; - uint32_t blockAlign_; - page_t* pages_; + uint32_t blockAlign_; + page_t* pages_; + uint16_t nextAddress_; + uint64_t allocated_; }; } // namespace vortex \ No newline at end of file diff --git a/runtime/common/nlohmann_json.hpp b/runtime/common/nlohmann_json.hpp new file mode 100644 index 00000000..5df7f56d --- /dev/null +++ b/runtime/common/nlohmann_json.hpp @@ -0,0 +1,24674 @@ +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + +/****************************************************************************\ + * Note on documentation: The source files contain links to the online * + * documentation of the public API at https://json.nlohmann.me. This URL * + * contains the most recent documentation and should also be applicable to * + * previous versions; documentation for deprecated functions is not * + * removed, but marked deprecated. See "Generate documentation" section in * + * file docs/README.md. * +\****************************************************************************/ + +#ifndef INCLUDE_NLOHMANN_JSON_HPP_ +#define INCLUDE_NLOHMANN_JSON_HPP_ + +#include // all_of, find, for_each +#include // nullptr_t, ptrdiff_t, size_t +#include // hash, less +#include // initializer_list +#ifndef JSON_NO_IO + #include // istream, ostream +#endif // JSON_NO_IO +#include // random_access_iterator_tag +#include // unique_ptr +#include // string, stoi, to_string +#include // declval, forward, move, pair, swap +#include // vector + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// This file contains all macro definitions affecting or depending on the ABI + +#ifndef JSON_SKIP_LIBRARY_VERSION_CHECK + #if defined(NLOHMANN_JSON_VERSION_MAJOR) && defined(NLOHMANN_JSON_VERSION_MINOR) && defined(NLOHMANN_JSON_VERSION_PATCH) + #if NLOHMANN_JSON_VERSION_MAJOR != 3 || NLOHMANN_JSON_VERSION_MINOR != 11 || NLOHMANN_JSON_VERSION_PATCH != 2 + #warning "Already included a different version of the library!" + #endif + #endif +#endif + +#define NLOHMANN_JSON_VERSION_MAJOR 3 // NOLINT(modernize-macro-to-enum) +#define NLOHMANN_JSON_VERSION_MINOR 11 // NOLINT(modernize-macro-to-enum) +#define NLOHMANN_JSON_VERSION_PATCH 2 // NOLINT(modernize-macro-to-enum) + +#ifndef JSON_DIAGNOSTICS + #define JSON_DIAGNOSTICS 0 +#endif + +#ifndef JSON_USE_LEGACY_DISCARDED_VALUE_COMPARISON + #define JSON_USE_LEGACY_DISCARDED_VALUE_COMPARISON 0 +#endif + +#if JSON_DIAGNOSTICS + #define NLOHMANN_JSON_ABI_TAG_DIAGNOSTICS _diag +#else + #define NLOHMANN_JSON_ABI_TAG_DIAGNOSTICS +#endif + +#if JSON_USE_LEGACY_DISCARDED_VALUE_COMPARISON + #define NLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON _ldvcmp +#else + #define NLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON +#endif + +#ifndef NLOHMANN_JSON_NAMESPACE_NO_VERSION + #define NLOHMANN_JSON_NAMESPACE_NO_VERSION 0 +#endif + +// Construct the namespace ABI tags component +#define NLOHMANN_JSON_ABI_TAGS_CONCAT_EX(a, b) json_abi ## a ## b +#define NLOHMANN_JSON_ABI_TAGS_CONCAT(a, b) \ + NLOHMANN_JSON_ABI_TAGS_CONCAT_EX(a, b) + +#define NLOHMANN_JSON_ABI_TAGS \ + NLOHMANN_JSON_ABI_TAGS_CONCAT( \ + NLOHMANN_JSON_ABI_TAG_DIAGNOSTICS, \ + NLOHMANN_JSON_ABI_TAG_LEGACY_DISCARDED_VALUE_COMPARISON) + +// Construct the namespace version component +#define NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT_EX(major, minor, patch) \ + _v ## major ## _ ## minor ## _ ## patch +#define NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT(major, minor, patch) \ + NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT_EX(major, minor, patch) + +#if NLOHMANN_JSON_NAMESPACE_NO_VERSION +#define NLOHMANN_JSON_NAMESPACE_VERSION +#else +#define NLOHMANN_JSON_NAMESPACE_VERSION \ + NLOHMANN_JSON_NAMESPACE_VERSION_CONCAT(NLOHMANN_JSON_VERSION_MAJOR, \ + NLOHMANN_JSON_VERSION_MINOR, \ + NLOHMANN_JSON_VERSION_PATCH) +#endif + +// Combine namespace components +#define NLOHMANN_JSON_NAMESPACE_CONCAT_EX(a, b) a ## b +#define NLOHMANN_JSON_NAMESPACE_CONCAT(a, b) \ + NLOHMANN_JSON_NAMESPACE_CONCAT_EX(a, b) + +#ifndef NLOHMANN_JSON_NAMESPACE +#define NLOHMANN_JSON_NAMESPACE \ + nlohmann::NLOHMANN_JSON_NAMESPACE_CONCAT( \ + NLOHMANN_JSON_ABI_TAGS, \ + NLOHMANN_JSON_NAMESPACE_VERSION) +#endif + +#ifndef NLOHMANN_JSON_NAMESPACE_BEGIN +#define NLOHMANN_JSON_NAMESPACE_BEGIN \ + namespace nlohmann \ + { \ + inline namespace NLOHMANN_JSON_NAMESPACE_CONCAT( \ + NLOHMANN_JSON_ABI_TAGS, \ + NLOHMANN_JSON_NAMESPACE_VERSION) \ + { +#endif + +#ifndef NLOHMANN_JSON_NAMESPACE_END +#define NLOHMANN_JSON_NAMESPACE_END \ + } /* namespace (inline namespace) NOLINT(readability/namespace) */ \ + } // namespace nlohmann +#endif + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // transform +#include // array +#include // forward_list +#include // inserter, front_inserter, end +#include // map +#include // string +#include // tuple, make_tuple +#include // is_arithmetic, is_same, is_enum, underlying_type, is_convertible +#include // unordered_map +#include // pair, declval +#include // valarray + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // nullptr_t +#include // exception +#if JSON_DIAGNOSTICS + #include // accumulate +#endif +#include // runtime_error +#include // to_string +#include // vector + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // array +#include // size_t +#include // uint8_t +#include // string + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // declval, pair +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +template struct make_void +{ + using type = void; +}; +template using void_t = typename make_void::type; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +// https://en.cppreference.com/w/cpp/experimental/is_detected +struct nonesuch +{ + nonesuch() = delete; + ~nonesuch() = delete; + nonesuch(nonesuch const&) = delete; + nonesuch(nonesuch const&&) = delete; + void operator=(nonesuch const&) = delete; + void operator=(nonesuch&&) = delete; +}; + +template class Op, + class... Args> +struct detector +{ + using value_t = std::false_type; + using type = Default; +}; + +template class Op, class... Args> +struct detector>, Op, Args...> +{ + using value_t = std::true_type; + using type = Op; +}; + +template class Op, class... Args> +using is_detected = typename detector::value_t; + +template class Op, class... Args> +struct is_detected_lazy : is_detected { }; + +template class Op, class... Args> +using detected_t = typename detector::type; + +template class Op, class... Args> +using detected_or = detector; + +template class Op, class... Args> +using detected_or_t = typename detected_or::type; + +template class Op, class... Args> +using is_detected_exact = std::is_same>; + +template class Op, class... Args> +using is_detected_convertible = + std::is_convertible, To>; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include + + +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-FileCopyrightText: 2016-2021 Evan Nemerson +// SPDX-License-Identifier: MIT + +/* Hedley - https://nemequ.github.io/hedley + * Created by Evan Nemerson + */ + +#if !defined(JSON_HEDLEY_VERSION) || (JSON_HEDLEY_VERSION < 15) +#if defined(JSON_HEDLEY_VERSION) + #undef JSON_HEDLEY_VERSION +#endif +#define JSON_HEDLEY_VERSION 15 + +#if defined(JSON_HEDLEY_STRINGIFY_EX) + #undef JSON_HEDLEY_STRINGIFY_EX +#endif +#define JSON_HEDLEY_STRINGIFY_EX(x) #x + +#if defined(JSON_HEDLEY_STRINGIFY) + #undef JSON_HEDLEY_STRINGIFY +#endif +#define JSON_HEDLEY_STRINGIFY(x) JSON_HEDLEY_STRINGIFY_EX(x) + +#if defined(JSON_HEDLEY_CONCAT_EX) + #undef JSON_HEDLEY_CONCAT_EX +#endif +#define JSON_HEDLEY_CONCAT_EX(a,b) a##b + +#if defined(JSON_HEDLEY_CONCAT) + #undef JSON_HEDLEY_CONCAT +#endif +#define JSON_HEDLEY_CONCAT(a,b) JSON_HEDLEY_CONCAT_EX(a,b) + +#if defined(JSON_HEDLEY_CONCAT3_EX) + #undef JSON_HEDLEY_CONCAT3_EX +#endif +#define JSON_HEDLEY_CONCAT3_EX(a,b,c) a##b##c + +#if defined(JSON_HEDLEY_CONCAT3) + #undef JSON_HEDLEY_CONCAT3 +#endif +#define JSON_HEDLEY_CONCAT3(a,b,c) JSON_HEDLEY_CONCAT3_EX(a,b,c) + +#if defined(JSON_HEDLEY_VERSION_ENCODE) + #undef JSON_HEDLEY_VERSION_ENCODE +#endif +#define JSON_HEDLEY_VERSION_ENCODE(major,minor,revision) (((major) * 1000000) + ((minor) * 1000) + (revision)) + +#if defined(JSON_HEDLEY_VERSION_DECODE_MAJOR) + #undef JSON_HEDLEY_VERSION_DECODE_MAJOR +#endif +#define JSON_HEDLEY_VERSION_DECODE_MAJOR(version) ((version) / 1000000) + +#if defined(JSON_HEDLEY_VERSION_DECODE_MINOR) + #undef JSON_HEDLEY_VERSION_DECODE_MINOR +#endif +#define JSON_HEDLEY_VERSION_DECODE_MINOR(version) (((version) % 1000000) / 1000) + +#if defined(JSON_HEDLEY_VERSION_DECODE_REVISION) + #undef JSON_HEDLEY_VERSION_DECODE_REVISION +#endif +#define JSON_HEDLEY_VERSION_DECODE_REVISION(version) ((version) % 1000) + +#if defined(JSON_HEDLEY_GNUC_VERSION) + #undef JSON_HEDLEY_GNUC_VERSION +#endif +#if defined(__GNUC__) && defined(__GNUC_PATCHLEVEL__) + #define JSON_HEDLEY_GNUC_VERSION JSON_HEDLEY_VERSION_ENCODE(__GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__) +#elif defined(__GNUC__) + #define JSON_HEDLEY_GNUC_VERSION JSON_HEDLEY_VERSION_ENCODE(__GNUC__, __GNUC_MINOR__, 0) +#endif + +#if defined(JSON_HEDLEY_GNUC_VERSION_CHECK) + #undef JSON_HEDLEY_GNUC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_GNUC_VERSION) + #define JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_GNUC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_MSVC_VERSION) + #undef JSON_HEDLEY_MSVC_VERSION +#endif +#if defined(_MSC_FULL_VER) && (_MSC_FULL_VER >= 140000000) && !defined(__ICL) + #define JSON_HEDLEY_MSVC_VERSION JSON_HEDLEY_VERSION_ENCODE(_MSC_FULL_VER / 10000000, (_MSC_FULL_VER % 10000000) / 100000, (_MSC_FULL_VER % 100000) / 100) +#elif defined(_MSC_FULL_VER) && !defined(__ICL) + #define JSON_HEDLEY_MSVC_VERSION JSON_HEDLEY_VERSION_ENCODE(_MSC_FULL_VER / 1000000, (_MSC_FULL_VER % 1000000) / 10000, (_MSC_FULL_VER % 10000) / 10) +#elif defined(_MSC_VER) && !defined(__ICL) + #define JSON_HEDLEY_MSVC_VERSION JSON_HEDLEY_VERSION_ENCODE(_MSC_VER / 100, _MSC_VER % 100, 0) +#endif + +#if defined(JSON_HEDLEY_MSVC_VERSION_CHECK) + #undef JSON_HEDLEY_MSVC_VERSION_CHECK +#endif +#if !defined(JSON_HEDLEY_MSVC_VERSION) + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (0) +#elif defined(_MSC_VER) && (_MSC_VER >= 1400) + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_FULL_VER >= ((major * 10000000) + (minor * 100000) + (patch))) +#elif defined(_MSC_VER) && (_MSC_VER >= 1200) + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_FULL_VER >= ((major * 1000000) + (minor * 10000) + (patch))) +#else + #define JSON_HEDLEY_MSVC_VERSION_CHECK(major,minor,patch) (_MSC_VER >= ((major * 100) + (minor))) +#endif + +#if defined(JSON_HEDLEY_INTEL_VERSION) + #undef JSON_HEDLEY_INTEL_VERSION +#endif +#if defined(__INTEL_COMPILER) && defined(__INTEL_COMPILER_UPDATE) && !defined(__ICL) + #define JSON_HEDLEY_INTEL_VERSION JSON_HEDLEY_VERSION_ENCODE(__INTEL_COMPILER / 100, __INTEL_COMPILER % 100, __INTEL_COMPILER_UPDATE) +#elif defined(__INTEL_COMPILER) && !defined(__ICL) + #define JSON_HEDLEY_INTEL_VERSION JSON_HEDLEY_VERSION_ENCODE(__INTEL_COMPILER / 100, __INTEL_COMPILER % 100, 0) +#endif + +#if defined(JSON_HEDLEY_INTEL_VERSION_CHECK) + #undef JSON_HEDLEY_INTEL_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_INTEL_VERSION) + #define JSON_HEDLEY_INTEL_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_INTEL_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_INTEL_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_INTEL_CL_VERSION) + #undef JSON_HEDLEY_INTEL_CL_VERSION +#endif +#if defined(__INTEL_COMPILER) && defined(__INTEL_COMPILER_UPDATE) && defined(__ICL) + #define JSON_HEDLEY_INTEL_CL_VERSION JSON_HEDLEY_VERSION_ENCODE(__INTEL_COMPILER, __INTEL_COMPILER_UPDATE, 0) +#endif + +#if defined(JSON_HEDLEY_INTEL_CL_VERSION_CHECK) + #undef JSON_HEDLEY_INTEL_CL_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_INTEL_CL_VERSION) + #define JSON_HEDLEY_INTEL_CL_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_INTEL_CL_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_INTEL_CL_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_PGI_VERSION) + #undef JSON_HEDLEY_PGI_VERSION +#endif +#if defined(__PGI) && defined(__PGIC__) && defined(__PGIC_MINOR__) && defined(__PGIC_PATCHLEVEL__) + #define JSON_HEDLEY_PGI_VERSION JSON_HEDLEY_VERSION_ENCODE(__PGIC__, __PGIC_MINOR__, __PGIC_PATCHLEVEL__) +#endif + +#if defined(JSON_HEDLEY_PGI_VERSION_CHECK) + #undef JSON_HEDLEY_PGI_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_PGI_VERSION) + #define JSON_HEDLEY_PGI_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_PGI_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_PGI_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_SUNPRO_VERSION) + #undef JSON_HEDLEY_SUNPRO_VERSION +#endif +#if defined(__SUNPRO_C) && (__SUNPRO_C > 0x1000) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((((__SUNPRO_C >> 16) & 0xf) * 10) + ((__SUNPRO_C >> 12) & 0xf), (((__SUNPRO_C >> 8) & 0xf) * 10) + ((__SUNPRO_C >> 4) & 0xf), (__SUNPRO_C & 0xf) * 10) +#elif defined(__SUNPRO_C) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((__SUNPRO_C >> 8) & 0xf, (__SUNPRO_C >> 4) & 0xf, (__SUNPRO_C) & 0xf) +#elif defined(__SUNPRO_CC) && (__SUNPRO_CC > 0x1000) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((((__SUNPRO_CC >> 16) & 0xf) * 10) + ((__SUNPRO_CC >> 12) & 0xf), (((__SUNPRO_CC >> 8) & 0xf) * 10) + ((__SUNPRO_CC >> 4) & 0xf), (__SUNPRO_CC & 0xf) * 10) +#elif defined(__SUNPRO_CC) + #define JSON_HEDLEY_SUNPRO_VERSION JSON_HEDLEY_VERSION_ENCODE((__SUNPRO_CC >> 8) & 0xf, (__SUNPRO_CC >> 4) & 0xf, (__SUNPRO_CC) & 0xf) +#endif + +#if defined(JSON_HEDLEY_SUNPRO_VERSION_CHECK) + #undef JSON_HEDLEY_SUNPRO_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_SUNPRO_VERSION) + #define JSON_HEDLEY_SUNPRO_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_SUNPRO_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_SUNPRO_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_EMSCRIPTEN_VERSION) + #undef JSON_HEDLEY_EMSCRIPTEN_VERSION +#endif +#if defined(__EMSCRIPTEN__) + #define JSON_HEDLEY_EMSCRIPTEN_VERSION JSON_HEDLEY_VERSION_ENCODE(__EMSCRIPTEN_major__, __EMSCRIPTEN_minor__, __EMSCRIPTEN_tiny__) +#endif + +#if defined(JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK) + #undef JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_EMSCRIPTEN_VERSION) + #define JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_EMSCRIPTEN_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_EMSCRIPTEN_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_ARM_VERSION) + #undef JSON_HEDLEY_ARM_VERSION +#endif +#if defined(__CC_ARM) && defined(__ARMCOMPILER_VERSION) + #define JSON_HEDLEY_ARM_VERSION JSON_HEDLEY_VERSION_ENCODE(__ARMCOMPILER_VERSION / 1000000, (__ARMCOMPILER_VERSION % 1000000) / 10000, (__ARMCOMPILER_VERSION % 10000) / 100) +#elif defined(__CC_ARM) && defined(__ARMCC_VERSION) + #define JSON_HEDLEY_ARM_VERSION JSON_HEDLEY_VERSION_ENCODE(__ARMCC_VERSION / 1000000, (__ARMCC_VERSION % 1000000) / 10000, (__ARMCC_VERSION % 10000) / 100) +#endif + +#if defined(JSON_HEDLEY_ARM_VERSION_CHECK) + #undef JSON_HEDLEY_ARM_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_ARM_VERSION) + #define JSON_HEDLEY_ARM_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_ARM_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_ARM_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_IBM_VERSION) + #undef JSON_HEDLEY_IBM_VERSION +#endif +#if defined(__ibmxl__) + #define JSON_HEDLEY_IBM_VERSION JSON_HEDLEY_VERSION_ENCODE(__ibmxl_version__, __ibmxl_release__, __ibmxl_modification__) +#elif defined(__xlC__) && defined(__xlC_ver__) + #define JSON_HEDLEY_IBM_VERSION JSON_HEDLEY_VERSION_ENCODE(__xlC__ >> 8, __xlC__ & 0xff, (__xlC_ver__ >> 8) & 0xff) +#elif defined(__xlC__) + #define JSON_HEDLEY_IBM_VERSION JSON_HEDLEY_VERSION_ENCODE(__xlC__ >> 8, __xlC__ & 0xff, 0) +#endif + +#if defined(JSON_HEDLEY_IBM_VERSION_CHECK) + #undef JSON_HEDLEY_IBM_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_IBM_VERSION) + #define JSON_HEDLEY_IBM_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_IBM_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_IBM_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_VERSION) + #undef JSON_HEDLEY_TI_VERSION +#endif +#if \ + defined(__TI_COMPILER_VERSION__) && \ + ( \ + defined(__TMS470__) || defined(__TI_ARM__) || \ + defined(__MSP430__) || \ + defined(__TMS320C2000__) \ + ) +#if (__TI_COMPILER_VERSION__ >= 16000000) + #define JSON_HEDLEY_TI_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif +#endif + +#if defined(JSON_HEDLEY_TI_VERSION_CHECK) + #undef JSON_HEDLEY_TI_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_VERSION) + #define JSON_HEDLEY_TI_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL2000_VERSION) + #undef JSON_HEDLEY_TI_CL2000_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__TMS320C2000__) + #define JSON_HEDLEY_TI_CL2000_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL2000_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL2000_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL2000_VERSION) + #define JSON_HEDLEY_TI_CL2000_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL2000_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL2000_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL430_VERSION) + #undef JSON_HEDLEY_TI_CL430_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__MSP430__) + #define JSON_HEDLEY_TI_CL430_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL430_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL430_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL430_VERSION) + #define JSON_HEDLEY_TI_CL430_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL430_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL430_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_ARMCL_VERSION) + #undef JSON_HEDLEY_TI_ARMCL_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && (defined(__TMS470__) || defined(__TI_ARM__)) + #define JSON_HEDLEY_TI_ARMCL_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_ARMCL_VERSION_CHECK) + #undef JSON_HEDLEY_TI_ARMCL_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_ARMCL_VERSION) + #define JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_ARMCL_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL6X_VERSION) + #undef JSON_HEDLEY_TI_CL6X_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__TMS320C6X__) + #define JSON_HEDLEY_TI_CL6X_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL6X_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL6X_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL6X_VERSION) + #define JSON_HEDLEY_TI_CL6X_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL6X_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL6X_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CL7X_VERSION) + #undef JSON_HEDLEY_TI_CL7X_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__C7000__) + #define JSON_HEDLEY_TI_CL7X_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CL7X_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CL7X_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CL7X_VERSION) + #define JSON_HEDLEY_TI_CL7X_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CL7X_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CL7X_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TI_CLPRU_VERSION) + #undef JSON_HEDLEY_TI_CLPRU_VERSION +#endif +#if defined(__TI_COMPILER_VERSION__) && defined(__PRU__) + #define JSON_HEDLEY_TI_CLPRU_VERSION JSON_HEDLEY_VERSION_ENCODE(__TI_COMPILER_VERSION__ / 1000000, (__TI_COMPILER_VERSION__ % 1000000) / 1000, (__TI_COMPILER_VERSION__ % 1000)) +#endif + +#if defined(JSON_HEDLEY_TI_CLPRU_VERSION_CHECK) + #undef JSON_HEDLEY_TI_CLPRU_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TI_CLPRU_VERSION) + #define JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TI_CLPRU_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_CRAY_VERSION) + #undef JSON_HEDLEY_CRAY_VERSION +#endif +#if defined(_CRAYC) + #if defined(_RELEASE_PATCHLEVEL) + #define JSON_HEDLEY_CRAY_VERSION JSON_HEDLEY_VERSION_ENCODE(_RELEASE_MAJOR, _RELEASE_MINOR, _RELEASE_PATCHLEVEL) + #else + #define JSON_HEDLEY_CRAY_VERSION JSON_HEDLEY_VERSION_ENCODE(_RELEASE_MAJOR, _RELEASE_MINOR, 0) + #endif +#endif + +#if defined(JSON_HEDLEY_CRAY_VERSION_CHECK) + #undef JSON_HEDLEY_CRAY_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_CRAY_VERSION) + #define JSON_HEDLEY_CRAY_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_CRAY_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_CRAY_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_IAR_VERSION) + #undef JSON_HEDLEY_IAR_VERSION +#endif +#if defined(__IAR_SYSTEMS_ICC__) + #if __VER__ > 1000 + #define JSON_HEDLEY_IAR_VERSION JSON_HEDLEY_VERSION_ENCODE((__VER__ / 1000000), ((__VER__ / 1000) % 1000), (__VER__ % 1000)) + #else + #define JSON_HEDLEY_IAR_VERSION JSON_HEDLEY_VERSION_ENCODE(__VER__ / 100, __VER__ % 100, 0) + #endif +#endif + +#if defined(JSON_HEDLEY_IAR_VERSION_CHECK) + #undef JSON_HEDLEY_IAR_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_IAR_VERSION) + #define JSON_HEDLEY_IAR_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_IAR_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_IAR_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_TINYC_VERSION) + #undef JSON_HEDLEY_TINYC_VERSION +#endif +#if defined(__TINYC__) + #define JSON_HEDLEY_TINYC_VERSION JSON_HEDLEY_VERSION_ENCODE(__TINYC__ / 1000, (__TINYC__ / 100) % 10, __TINYC__ % 100) +#endif + +#if defined(JSON_HEDLEY_TINYC_VERSION_CHECK) + #undef JSON_HEDLEY_TINYC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_TINYC_VERSION) + #define JSON_HEDLEY_TINYC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_TINYC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_TINYC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_DMC_VERSION) + #undef JSON_HEDLEY_DMC_VERSION +#endif +#if defined(__DMC__) + #define JSON_HEDLEY_DMC_VERSION JSON_HEDLEY_VERSION_ENCODE(__DMC__ >> 8, (__DMC__ >> 4) & 0xf, __DMC__ & 0xf) +#endif + +#if defined(JSON_HEDLEY_DMC_VERSION_CHECK) + #undef JSON_HEDLEY_DMC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_DMC_VERSION) + #define JSON_HEDLEY_DMC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_DMC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_DMC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_COMPCERT_VERSION) + #undef JSON_HEDLEY_COMPCERT_VERSION +#endif +#if defined(__COMPCERT_VERSION__) + #define JSON_HEDLEY_COMPCERT_VERSION JSON_HEDLEY_VERSION_ENCODE(__COMPCERT_VERSION__ / 10000, (__COMPCERT_VERSION__ / 100) % 100, __COMPCERT_VERSION__ % 100) +#endif + +#if defined(JSON_HEDLEY_COMPCERT_VERSION_CHECK) + #undef JSON_HEDLEY_COMPCERT_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_COMPCERT_VERSION) + #define JSON_HEDLEY_COMPCERT_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_COMPCERT_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_COMPCERT_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_PELLES_VERSION) + #undef JSON_HEDLEY_PELLES_VERSION +#endif +#if defined(__POCC__) + #define JSON_HEDLEY_PELLES_VERSION JSON_HEDLEY_VERSION_ENCODE(__POCC__ / 100, __POCC__ % 100, 0) +#endif + +#if defined(JSON_HEDLEY_PELLES_VERSION_CHECK) + #undef JSON_HEDLEY_PELLES_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_PELLES_VERSION) + #define JSON_HEDLEY_PELLES_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_PELLES_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_PELLES_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_MCST_LCC_VERSION) + #undef JSON_HEDLEY_MCST_LCC_VERSION +#endif +#if defined(__LCC__) && defined(__LCC_MINOR__) + #define JSON_HEDLEY_MCST_LCC_VERSION JSON_HEDLEY_VERSION_ENCODE(__LCC__ / 100, __LCC__ % 100, __LCC_MINOR__) +#endif + +#if defined(JSON_HEDLEY_MCST_LCC_VERSION_CHECK) + #undef JSON_HEDLEY_MCST_LCC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_MCST_LCC_VERSION) + #define JSON_HEDLEY_MCST_LCC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_MCST_LCC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_MCST_LCC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_GCC_VERSION) + #undef JSON_HEDLEY_GCC_VERSION +#endif +#if \ + defined(JSON_HEDLEY_GNUC_VERSION) && \ + !defined(__clang__) && \ + !defined(JSON_HEDLEY_INTEL_VERSION) && \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_ARM_VERSION) && \ + !defined(JSON_HEDLEY_CRAY_VERSION) && \ + !defined(JSON_HEDLEY_TI_VERSION) && \ + !defined(JSON_HEDLEY_TI_ARMCL_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL430_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL2000_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL6X_VERSION) && \ + !defined(JSON_HEDLEY_TI_CL7X_VERSION) && \ + !defined(JSON_HEDLEY_TI_CLPRU_VERSION) && \ + !defined(__COMPCERT__) && \ + !defined(JSON_HEDLEY_MCST_LCC_VERSION) + #define JSON_HEDLEY_GCC_VERSION JSON_HEDLEY_GNUC_VERSION +#endif + +#if defined(JSON_HEDLEY_GCC_VERSION_CHECK) + #undef JSON_HEDLEY_GCC_VERSION_CHECK +#endif +#if defined(JSON_HEDLEY_GCC_VERSION) + #define JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) (JSON_HEDLEY_GCC_VERSION >= JSON_HEDLEY_VERSION_ENCODE(major, minor, patch)) +#else + #define JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) (0) +#endif + +#if defined(JSON_HEDLEY_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_HAS_ATTRIBUTE +#endif +#if \ + defined(__has_attribute) && \ + ( \ + (!defined(JSON_HEDLEY_IAR_VERSION) || JSON_HEDLEY_IAR_VERSION_CHECK(8,5,9)) \ + ) +# define JSON_HEDLEY_HAS_ATTRIBUTE(attribute) __has_attribute(attribute) +#else +# define JSON_HEDLEY_HAS_ATTRIBUTE(attribute) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_GNUC_HAS_ATTRIBUTE +#endif +#if defined(__has_attribute) + #define JSON_HEDLEY_GNUC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_HAS_ATTRIBUTE(attribute) +#else + #define JSON_HEDLEY_GNUC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_GCC_HAS_ATTRIBUTE +#endif +#if defined(__has_attribute) + #define JSON_HEDLEY_GCC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_HAS_ATTRIBUTE(attribute) +#else + #define JSON_HEDLEY_GCC_HAS_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_HAS_CPP_ATTRIBUTE +#endif +#if \ + defined(__has_cpp_attribute) && \ + defined(__cplusplus) && \ + (!defined(JSON_HEDLEY_SUNPRO_VERSION) || JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0)) + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE(attribute) __has_cpp_attribute(attribute) +#else + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE(attribute) (0) +#endif + +#if defined(JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS) + #undef JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS +#endif +#if !defined(__cplusplus) || !defined(__has_cpp_attribute) + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) (0) +#elif \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_IAR_VERSION) && \ + (!defined(JSON_HEDLEY_SUNPRO_VERSION) || JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0)) && \ + (!defined(JSON_HEDLEY_MSVC_VERSION) || JSON_HEDLEY_MSVC_VERSION_CHECK(19,20,0)) + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) JSON_HEDLEY_HAS_CPP_ATTRIBUTE(ns::attribute) +#else + #define JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(ns,attribute) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE +#endif +#if defined(__has_cpp_attribute) && defined(__cplusplus) + #define JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) __has_cpp_attribute(attribute) +#else + #define JSON_HEDLEY_GNUC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE +#endif +#if defined(__has_cpp_attribute) && defined(__cplusplus) + #define JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) __has_cpp_attribute(attribute) +#else + #define JSON_HEDLEY_GCC_HAS_CPP_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_BUILTIN) + #undef JSON_HEDLEY_HAS_BUILTIN +#endif +#if defined(__has_builtin) + #define JSON_HEDLEY_HAS_BUILTIN(builtin) __has_builtin(builtin) +#else + #define JSON_HEDLEY_HAS_BUILTIN(builtin) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_BUILTIN) + #undef JSON_HEDLEY_GNUC_HAS_BUILTIN +#endif +#if defined(__has_builtin) + #define JSON_HEDLEY_GNUC_HAS_BUILTIN(builtin,major,minor,patch) __has_builtin(builtin) +#else + #define JSON_HEDLEY_GNUC_HAS_BUILTIN(builtin,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_BUILTIN) + #undef JSON_HEDLEY_GCC_HAS_BUILTIN +#endif +#if defined(__has_builtin) + #define JSON_HEDLEY_GCC_HAS_BUILTIN(builtin,major,minor,patch) __has_builtin(builtin) +#else + #define JSON_HEDLEY_GCC_HAS_BUILTIN(builtin,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_FEATURE) + #undef JSON_HEDLEY_HAS_FEATURE +#endif +#if defined(__has_feature) + #define JSON_HEDLEY_HAS_FEATURE(feature) __has_feature(feature) +#else + #define JSON_HEDLEY_HAS_FEATURE(feature) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_FEATURE) + #undef JSON_HEDLEY_GNUC_HAS_FEATURE +#endif +#if defined(__has_feature) + #define JSON_HEDLEY_GNUC_HAS_FEATURE(feature,major,minor,patch) __has_feature(feature) +#else + #define JSON_HEDLEY_GNUC_HAS_FEATURE(feature,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_FEATURE) + #undef JSON_HEDLEY_GCC_HAS_FEATURE +#endif +#if defined(__has_feature) + #define JSON_HEDLEY_GCC_HAS_FEATURE(feature,major,minor,patch) __has_feature(feature) +#else + #define JSON_HEDLEY_GCC_HAS_FEATURE(feature,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_EXTENSION) + #undef JSON_HEDLEY_HAS_EXTENSION +#endif +#if defined(__has_extension) + #define JSON_HEDLEY_HAS_EXTENSION(extension) __has_extension(extension) +#else + #define JSON_HEDLEY_HAS_EXTENSION(extension) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_EXTENSION) + #undef JSON_HEDLEY_GNUC_HAS_EXTENSION +#endif +#if defined(__has_extension) + #define JSON_HEDLEY_GNUC_HAS_EXTENSION(extension,major,minor,patch) __has_extension(extension) +#else + #define JSON_HEDLEY_GNUC_HAS_EXTENSION(extension,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_EXTENSION) + #undef JSON_HEDLEY_GCC_HAS_EXTENSION +#endif +#if defined(__has_extension) + #define JSON_HEDLEY_GCC_HAS_EXTENSION(extension,major,minor,patch) __has_extension(extension) +#else + #define JSON_HEDLEY_GCC_HAS_EXTENSION(extension,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE +#endif +#if defined(__has_declspec_attribute) + #define JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) __has_declspec_attribute(attribute) +#else + #define JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE +#endif +#if defined(__has_declspec_attribute) + #define JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) __has_declspec_attribute(attribute) +#else + #define JSON_HEDLEY_GNUC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE +#endif +#if defined(__has_declspec_attribute) + #define JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) __has_declspec_attribute(attribute) +#else + #define JSON_HEDLEY_GCC_HAS_DECLSPEC_ATTRIBUTE(attribute,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_HAS_WARNING) + #undef JSON_HEDLEY_HAS_WARNING +#endif +#if defined(__has_warning) + #define JSON_HEDLEY_HAS_WARNING(warning) __has_warning(warning) +#else + #define JSON_HEDLEY_HAS_WARNING(warning) (0) +#endif + +#if defined(JSON_HEDLEY_GNUC_HAS_WARNING) + #undef JSON_HEDLEY_GNUC_HAS_WARNING +#endif +#if defined(__has_warning) + #define JSON_HEDLEY_GNUC_HAS_WARNING(warning,major,minor,patch) __has_warning(warning) +#else + #define JSON_HEDLEY_GNUC_HAS_WARNING(warning,major,minor,patch) JSON_HEDLEY_GNUC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_GCC_HAS_WARNING) + #undef JSON_HEDLEY_GCC_HAS_WARNING +#endif +#if defined(__has_warning) + #define JSON_HEDLEY_GCC_HAS_WARNING(warning,major,minor,patch) __has_warning(warning) +#else + #define JSON_HEDLEY_GCC_HAS_WARNING(warning,major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if \ + (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) || \ + defined(__clang__) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(18,4,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,7,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(2,0,1) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(5,0,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,17) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(8,0,0) || \ + (JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) && defined(__C99_PRAGMA_OPERATOR)) + #define JSON_HEDLEY_PRAGMA(value) _Pragma(#value) +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) + #define JSON_HEDLEY_PRAGMA(value) __pragma(value) +#else + #define JSON_HEDLEY_PRAGMA(value) +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_PUSH) + #undef JSON_HEDLEY_DIAGNOSTIC_PUSH +#endif +#if defined(JSON_HEDLEY_DIAGNOSTIC_POP) + #undef JSON_HEDLEY_DIAGNOSTIC_POP +#endif +#if defined(__clang__) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("clang diagnostic push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("clang diagnostic pop") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("warning(push)") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("warning(pop)") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,6,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("GCC diagnostic push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("GCC diagnostic pop") +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH __pragma(warning(push)) + #define JSON_HEDLEY_DIAGNOSTIC_POP __pragma(warning(pop)) +#elif JSON_HEDLEY_ARM_VERSION_CHECK(5,6,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("pop") +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,4,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("diag_push") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("diag_pop") +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(2,90,0) + #define JSON_HEDLEY_DIAGNOSTIC_PUSH _Pragma("warning(push)") + #define JSON_HEDLEY_DIAGNOSTIC_POP _Pragma("warning(pop)") +#else + #define JSON_HEDLEY_DIAGNOSTIC_PUSH + #define JSON_HEDLEY_DIAGNOSTIC_POP +#endif + +/* JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_ is for + HEDLEY INTERNAL USE ONLY. API subject to change without notice. */ +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_ +#endif +#if defined(__cplusplus) +# if JSON_HEDLEY_HAS_WARNING("-Wc++98-compat") +# if JSON_HEDLEY_HAS_WARNING("-Wc++17-extensions") +# if JSON_HEDLEY_HAS_WARNING("-Wc++1z-extensions") +# define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \ + _Pragma("clang diagnostic ignored \"-Wc++17-extensions\"") \ + _Pragma("clang diagnostic ignored \"-Wc++1z-extensions\"") \ + xpr \ + JSON_HEDLEY_DIAGNOSTIC_POP +# else +# define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \ + _Pragma("clang diagnostic ignored \"-Wc++17-extensions\"") \ + xpr \ + JSON_HEDLEY_DIAGNOSTIC_POP +# endif +# else +# define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(xpr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wc++98-compat\"") \ + xpr \ + JSON_HEDLEY_DIAGNOSTIC_POP +# endif +# endif +#endif +#if !defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(x) x +#endif + +#if defined(JSON_HEDLEY_CONST_CAST) + #undef JSON_HEDLEY_CONST_CAST +#endif +#if defined(__cplusplus) +# define JSON_HEDLEY_CONST_CAST(T, expr) (const_cast(expr)) +#elif \ + JSON_HEDLEY_HAS_WARNING("-Wcast-qual") || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,6,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) +# define JSON_HEDLEY_CONST_CAST(T, expr) (__extension__ ({ \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL \ + ((T) (expr)); \ + JSON_HEDLEY_DIAGNOSTIC_POP \ + })) +#else +# define JSON_HEDLEY_CONST_CAST(T, expr) ((T) (expr)) +#endif + +#if defined(JSON_HEDLEY_REINTERPRET_CAST) + #undef JSON_HEDLEY_REINTERPRET_CAST +#endif +#if defined(__cplusplus) + #define JSON_HEDLEY_REINTERPRET_CAST(T, expr) (reinterpret_cast(expr)) +#else + #define JSON_HEDLEY_REINTERPRET_CAST(T, expr) ((T) (expr)) +#endif + +#if defined(JSON_HEDLEY_STATIC_CAST) + #undef JSON_HEDLEY_STATIC_CAST +#endif +#if defined(__cplusplus) + #define JSON_HEDLEY_STATIC_CAST(T, expr) (static_cast(expr)) +#else + #define JSON_HEDLEY_STATIC_CAST(T, expr) ((T) (expr)) +#endif + +#if defined(JSON_HEDLEY_CPP_CAST) + #undef JSON_HEDLEY_CPP_CAST +#endif +#if defined(__cplusplus) +# if JSON_HEDLEY_HAS_WARNING("-Wold-style-cast") +# define JSON_HEDLEY_CPP_CAST(T, expr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wold-style-cast\"") \ + ((T) (expr)) \ + JSON_HEDLEY_DIAGNOSTIC_POP +# elif JSON_HEDLEY_IAR_VERSION_CHECK(8,3,0) +# define JSON_HEDLEY_CPP_CAST(T, expr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("diag_suppress=Pe137") \ + JSON_HEDLEY_DIAGNOSTIC_POP +# else +# define JSON_HEDLEY_CPP_CAST(T, expr) ((T) (expr)) +# endif +#else +# define JSON_HEDLEY_CPP_CAST(T, expr) (expr) +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wdeprecated-declarations") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("clang diagnostic ignored \"-Wdeprecated-declarations\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("warning(disable:1478 1786)") +#elif JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED __pragma(warning(disable:1478 1786)) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(20,7,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1216,1444,1445") +#elif JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1444") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,3,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"") +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED __pragma(warning(disable:4996)) +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1215,1444") +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress 1291,1718") +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) && !defined(__cplusplus) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("error_messages(off,E_DEPRECATED_ATT,E_DEPRECATED_ATT_MESS)") +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) && defined(__cplusplus) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("error_messages(off,symdeprecated,symdeprecated2)") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("diag_suppress=Pe1444,Pe1215") +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(2,90,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED _Pragma("warn(disable:2241)") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_DEPRECATED +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-pragmas") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("clang diagnostic ignored \"-Wunknown-pragmas\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("warning(disable:161)") +#elif JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS __pragma(warning(disable:161)) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 1675") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,3,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("GCC diagnostic ignored \"-Wunknown-pragmas\"") +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS __pragma(warning(disable:4068)) +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(16,9,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,3,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 163") +#elif JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 163") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress=Pe161") +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS _Pragma("diag_suppress 161") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-attributes") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("clang diagnostic ignored \"-Wunknown-attributes\"") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(4,6,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(17,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("warning(disable:1292)") +#elif JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES __pragma(warning(disable:1292)) +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(19,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES __pragma(warning(disable:5030)) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(20,7,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097,1098") +#elif JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097") +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,14,0) && defined(__cplusplus) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("error_messages(off,attrskipunsup)") +#elif \ + JSON_HEDLEY_TI_VERSION_CHECK(18,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,3,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1173") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress=Pe1097") +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES _Pragma("diag_suppress 1097") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_CPP_ATTRIBUTES +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wcast-qual") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("clang diagnostic ignored \"-Wcast-qual\"") +#elif JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("warning(disable:2203 2331)") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(3,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL _Pragma("GCC diagnostic ignored \"-Wcast-qual\"") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_CAST_QUAL +#endif + +#if defined(JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION) + #undef JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunused-function") + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("clang diagnostic ignored \"-Wunused-function\"") +#elif JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("GCC diagnostic ignored \"-Wunused-function\"") +#elif JSON_HEDLEY_MSVC_VERSION_CHECK(1,0,0) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION __pragma(warning(disable:4505)) +#elif JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION _Pragma("diag_suppress 3142") +#else + #define JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNUSED_FUNCTION +#endif + +#if defined(JSON_HEDLEY_DEPRECATED) + #undef JSON_HEDLEY_DEPRECATED +#endif +#if defined(JSON_HEDLEY_DEPRECATED_FOR) + #undef JSON_HEDLEY_DEPRECATED_FOR +#endif +#if \ + JSON_HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DEPRECATED(since) __declspec(deprecated("Since " # since)) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __declspec(deprecated("Since " #since "; use " #replacement)) +#elif \ + (JSON_HEDLEY_HAS_EXTENSION(attribute_deprecated_with_message) && !defined(JSON_HEDLEY_IAR_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,5,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,6,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(18,1,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(18,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,3,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,3,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_DEPRECATED(since) __attribute__((__deprecated__("Since " #since))) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __attribute__((__deprecated__("Since " #since "; use " #replacement))) +#elif defined(__cplusplus) && (__cplusplus >= 201402L) + #define JSON_HEDLEY_DEPRECATED(since) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[deprecated("Since " #since)]]) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[deprecated("Since " #since "; use " #replacement)]]) +#elif \ + JSON_HEDLEY_HAS_ATTRIBUTE(deprecated) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) + #define JSON_HEDLEY_DEPRECATED(since) __attribute__((__deprecated__)) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __attribute__((__deprecated__)) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_PELLES_VERSION_CHECK(6,50,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_DEPRECATED(since) __declspec(deprecated) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) __declspec(deprecated) +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_DEPRECATED(since) _Pragma("deprecated") + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) _Pragma("deprecated") +#else + #define JSON_HEDLEY_DEPRECATED(since) + #define JSON_HEDLEY_DEPRECATED_FOR(since, replacement) +#endif + +#if defined(JSON_HEDLEY_UNAVAILABLE) + #undef JSON_HEDLEY_UNAVAILABLE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(warning) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,3,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_UNAVAILABLE(available_since) __attribute__((__warning__("Not available until " #available_since))) +#else + #define JSON_HEDLEY_UNAVAILABLE(available_since) +#endif + +#if defined(JSON_HEDLEY_WARN_UNUSED_RESULT) + #undef JSON_HEDLEY_WARN_UNUSED_RESULT +#endif +#if defined(JSON_HEDLEY_WARN_UNUSED_RESULT_MSG) + #undef JSON_HEDLEY_WARN_UNUSED_RESULT_MSG +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(warn_unused_result) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0) && defined(__cplusplus)) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_WARN_UNUSED_RESULT __attribute__((__warn_unused_result__)) + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) __attribute__((__warn_unused_result__)) +#elif (JSON_HEDLEY_HAS_CPP_ATTRIBUTE(nodiscard) >= 201907L) + #define JSON_HEDLEY_WARN_UNUSED_RESULT JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]]) + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard(msg)]]) +#elif JSON_HEDLEY_HAS_CPP_ATTRIBUTE(nodiscard) + #define JSON_HEDLEY_WARN_UNUSED_RESULT JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]]) + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[nodiscard]]) +#elif defined(_Check_return_) /* SAL */ + #define JSON_HEDLEY_WARN_UNUSED_RESULT _Check_return_ + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) _Check_return_ +#else + #define JSON_HEDLEY_WARN_UNUSED_RESULT + #define JSON_HEDLEY_WARN_UNUSED_RESULT_MSG(msg) +#endif + +#if defined(JSON_HEDLEY_SENTINEL) + #undef JSON_HEDLEY_SENTINEL +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(sentinel) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,4,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_SENTINEL(position) __attribute__((__sentinel__(position))) +#else + #define JSON_HEDLEY_SENTINEL(position) +#endif + +#if defined(JSON_HEDLEY_NO_RETURN) + #undef JSON_HEDLEY_NO_RETURN +#endif +#if JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_NO_RETURN __noreturn +#elif \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_NO_RETURN __attribute__((__noreturn__)) +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define JSON_HEDLEY_NO_RETURN _Noreturn +#elif defined(__cplusplus) && (__cplusplus >= 201103L) + #define JSON_HEDLEY_NO_RETURN JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[noreturn]]) +#elif \ + JSON_HEDLEY_HAS_ATTRIBUTE(noreturn) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,2,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) + #define JSON_HEDLEY_NO_RETURN __attribute__((__noreturn__)) +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) + #define JSON_HEDLEY_NO_RETURN _Pragma("does_not_return") +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_NO_RETURN __declspec(noreturn) +#elif JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,0,0) && defined(__cplusplus) + #define JSON_HEDLEY_NO_RETURN _Pragma("FUNC_NEVER_RETURNS;") +#elif JSON_HEDLEY_COMPCERT_VERSION_CHECK(3,2,0) + #define JSON_HEDLEY_NO_RETURN __attribute((noreturn)) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(9,0,0) + #define JSON_HEDLEY_NO_RETURN __declspec(noreturn) +#else + #define JSON_HEDLEY_NO_RETURN +#endif + +#if defined(JSON_HEDLEY_NO_ESCAPE) + #undef JSON_HEDLEY_NO_ESCAPE +#endif +#if JSON_HEDLEY_HAS_ATTRIBUTE(noescape) + #define JSON_HEDLEY_NO_ESCAPE __attribute__((__noescape__)) +#else + #define JSON_HEDLEY_NO_ESCAPE +#endif + +#if defined(JSON_HEDLEY_UNREACHABLE) + #undef JSON_HEDLEY_UNREACHABLE +#endif +#if defined(JSON_HEDLEY_UNREACHABLE_RETURN) + #undef JSON_HEDLEY_UNREACHABLE_RETURN +#endif +#if defined(JSON_HEDLEY_ASSUME) + #undef JSON_HEDLEY_ASSUME +#endif +#if \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_ASSUME(expr) __assume(expr) +#elif JSON_HEDLEY_HAS_BUILTIN(__builtin_assume) + #define JSON_HEDLEY_ASSUME(expr) __builtin_assume(expr) +#elif \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0) + #if defined(__cplusplus) + #define JSON_HEDLEY_ASSUME(expr) std::_nassert(expr) + #else + #define JSON_HEDLEY_ASSUME(expr) _nassert(expr) + #endif +#endif +#if \ + (JSON_HEDLEY_HAS_BUILTIN(__builtin_unreachable) && (!defined(JSON_HEDLEY_ARM_VERSION))) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,5,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(18,10,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,5) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(10,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_UNREACHABLE() __builtin_unreachable() +#elif defined(JSON_HEDLEY_ASSUME) + #define JSON_HEDLEY_UNREACHABLE() JSON_HEDLEY_ASSUME(0) +#endif +#if !defined(JSON_HEDLEY_ASSUME) + #if defined(JSON_HEDLEY_UNREACHABLE) + #define JSON_HEDLEY_ASSUME(expr) JSON_HEDLEY_STATIC_CAST(void, ((expr) ? 1 : (JSON_HEDLEY_UNREACHABLE(), 1))) + #else + #define JSON_HEDLEY_ASSUME(expr) JSON_HEDLEY_STATIC_CAST(void, expr) + #endif +#endif +#if defined(JSON_HEDLEY_UNREACHABLE) + #if \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0) + #define JSON_HEDLEY_UNREACHABLE_RETURN(value) return (JSON_HEDLEY_STATIC_CAST(void, JSON_HEDLEY_ASSUME(0)), (value)) + #else + #define JSON_HEDLEY_UNREACHABLE_RETURN(value) JSON_HEDLEY_UNREACHABLE() + #endif +#else + #define JSON_HEDLEY_UNREACHABLE_RETURN(value) return (value) +#endif +#if !defined(JSON_HEDLEY_UNREACHABLE) + #define JSON_HEDLEY_UNREACHABLE() JSON_HEDLEY_ASSUME(0) +#endif + +JSON_HEDLEY_DIAGNOSTIC_PUSH +#if JSON_HEDLEY_HAS_WARNING("-Wpedantic") + #pragma clang diagnostic ignored "-Wpedantic" +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wc++98-compat-pedantic") && defined(__cplusplus) + #pragma clang diagnostic ignored "-Wc++98-compat-pedantic" +#endif +#if JSON_HEDLEY_GCC_HAS_WARNING("-Wvariadic-macros",4,0,0) + #if defined(__clang__) + #pragma clang diagnostic ignored "-Wvariadic-macros" + #elif defined(JSON_HEDLEY_GCC_VERSION) + #pragma GCC diagnostic ignored "-Wvariadic-macros" + #endif +#endif +#if defined(JSON_HEDLEY_NON_NULL) + #undef JSON_HEDLEY_NON_NULL +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(nonnull) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,3,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) + #define JSON_HEDLEY_NON_NULL(...) __attribute__((__nonnull__(__VA_ARGS__))) +#else + #define JSON_HEDLEY_NON_NULL(...) +#endif +JSON_HEDLEY_DIAGNOSTIC_POP + +#if defined(JSON_HEDLEY_PRINTF_FORMAT) + #undef JSON_HEDLEY_PRINTF_FORMAT +#endif +#if defined(__MINGW32__) && JSON_HEDLEY_GCC_HAS_ATTRIBUTE(format,4,4,0) && !defined(__USE_MINGW_ANSI_STDIO) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(ms_printf, string_idx, first_to_check))) +#elif defined(__MINGW32__) && JSON_HEDLEY_GCC_HAS_ATTRIBUTE(format,4,4,0) && defined(__USE_MINGW_ANSI_STDIO) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(gnu_printf, string_idx, first_to_check))) +#elif \ + JSON_HEDLEY_HAS_ATTRIBUTE(format) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,6,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __attribute__((__format__(__printf__, string_idx, first_to_check))) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(6,0,0) + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) __declspec(vaformat(printf,string_idx,first_to_check)) +#else + #define JSON_HEDLEY_PRINTF_FORMAT(string_idx,first_to_check) +#endif + +#if defined(JSON_HEDLEY_CONSTEXPR) + #undef JSON_HEDLEY_CONSTEXPR +#endif +#if defined(__cplusplus) + #if __cplusplus >= 201103L + #define JSON_HEDLEY_CONSTEXPR JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(constexpr) + #endif +#endif +#if !defined(JSON_HEDLEY_CONSTEXPR) + #define JSON_HEDLEY_CONSTEXPR +#endif + +#if defined(JSON_HEDLEY_PREDICT) + #undef JSON_HEDLEY_PREDICT +#endif +#if defined(JSON_HEDLEY_LIKELY) + #undef JSON_HEDLEY_LIKELY +#endif +#if defined(JSON_HEDLEY_UNLIKELY) + #undef JSON_HEDLEY_UNLIKELY +#endif +#if defined(JSON_HEDLEY_UNPREDICTABLE) + #undef JSON_HEDLEY_UNPREDICTABLE +#endif +#if JSON_HEDLEY_HAS_BUILTIN(__builtin_unpredictable) + #define JSON_HEDLEY_UNPREDICTABLE(expr) __builtin_unpredictable((expr)) +#endif +#if \ + (JSON_HEDLEY_HAS_BUILTIN(__builtin_expect_with_probability) && !defined(JSON_HEDLEY_PGI_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(9,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PREDICT(expr, value, probability) __builtin_expect_with_probability( (expr), (value), (probability)) +# define JSON_HEDLEY_PREDICT_TRUE(expr, probability) __builtin_expect_with_probability(!!(expr), 1 , (probability)) +# define JSON_HEDLEY_PREDICT_FALSE(expr, probability) __builtin_expect_with_probability(!!(expr), 0 , (probability)) +# define JSON_HEDLEY_LIKELY(expr) __builtin_expect (!!(expr), 1 ) +# define JSON_HEDLEY_UNLIKELY(expr) __builtin_expect (!!(expr), 0 ) +#elif \ + (JSON_HEDLEY_HAS_BUILTIN(__builtin_expect) && !defined(JSON_HEDLEY_INTEL_CL_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,15,0) && defined(__cplusplus)) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,7,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,27) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PREDICT(expr, expected, probability) \ + (((probability) >= 0.9) ? __builtin_expect((expr), (expected)) : (JSON_HEDLEY_STATIC_CAST(void, expected), (expr))) +# define JSON_HEDLEY_PREDICT_TRUE(expr, probability) \ + (__extension__ ({ \ + double hedley_probability_ = (probability); \ + ((hedley_probability_ >= 0.9) ? __builtin_expect(!!(expr), 1) : ((hedley_probability_ <= 0.1) ? __builtin_expect(!!(expr), 0) : !!(expr))); \ + })) +# define JSON_HEDLEY_PREDICT_FALSE(expr, probability) \ + (__extension__ ({ \ + double hedley_probability_ = (probability); \ + ((hedley_probability_ >= 0.9) ? __builtin_expect(!!(expr), 0) : ((hedley_probability_ <= 0.1) ? __builtin_expect(!!(expr), 1) : !!(expr))); \ + })) +# define JSON_HEDLEY_LIKELY(expr) __builtin_expect(!!(expr), 1) +# define JSON_HEDLEY_UNLIKELY(expr) __builtin_expect(!!(expr), 0) +#else +# define JSON_HEDLEY_PREDICT(expr, expected, probability) (JSON_HEDLEY_STATIC_CAST(void, expected), (expr)) +# define JSON_HEDLEY_PREDICT_TRUE(expr, probability) (!!(expr)) +# define JSON_HEDLEY_PREDICT_FALSE(expr, probability) (!!(expr)) +# define JSON_HEDLEY_LIKELY(expr) (!!(expr)) +# define JSON_HEDLEY_UNLIKELY(expr) (!!(expr)) +#endif +#if !defined(JSON_HEDLEY_UNPREDICTABLE) + #define JSON_HEDLEY_UNPREDICTABLE(expr) JSON_HEDLEY_PREDICT(expr, 1, 0.5) +#endif + +#if defined(JSON_HEDLEY_MALLOC) + #undef JSON_HEDLEY_MALLOC +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(malloc) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(12,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_MALLOC __attribute__((__malloc__)) +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) + #define JSON_HEDLEY_MALLOC _Pragma("returns_new_memory") +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_MALLOC __declspec(restrict) +#else + #define JSON_HEDLEY_MALLOC +#endif + +#if defined(JSON_HEDLEY_PURE) + #undef JSON_HEDLEY_PURE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(pure) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(2,96,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PURE __attribute__((__pure__)) +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) +# define JSON_HEDLEY_PURE _Pragma("does_not_write_global_data") +#elif defined(__cplusplus) && \ + ( \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(2,0,1) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) \ + ) +# define JSON_HEDLEY_PURE _Pragma("FUNC_IS_PURE;") +#else +# define JSON_HEDLEY_PURE +#endif + +#if defined(JSON_HEDLEY_CONST) + #undef JSON_HEDLEY_CONST +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(const) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(2,5,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_CONST __attribute__((__const__)) +#elif \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) + #define JSON_HEDLEY_CONST _Pragma("no_side_effect") +#else + #define JSON_HEDLEY_CONST JSON_HEDLEY_PURE +#endif + +#if defined(JSON_HEDLEY_RESTRICT) + #undef JSON_HEDLEY_RESTRICT +#endif +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) && !defined(__cplusplus) + #define JSON_HEDLEY_RESTRICT restrict +#elif \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_MSVC_VERSION_CHECK(14,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(17,10,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,4) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,14,0) && defined(__cplusplus)) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) || \ + defined(__clang__) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_RESTRICT __restrict +#elif JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,3,0) && !defined(__cplusplus) + #define JSON_HEDLEY_RESTRICT _Restrict +#else + #define JSON_HEDLEY_RESTRICT +#endif + +#if defined(JSON_HEDLEY_INLINE) + #undef JSON_HEDLEY_INLINE +#endif +#if \ + (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) || \ + (defined(__cplusplus) && (__cplusplus >= 199711L)) + #define JSON_HEDLEY_INLINE inline +#elif \ + defined(JSON_HEDLEY_GCC_VERSION) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(6,2,0) + #define JSON_HEDLEY_INLINE __inline__ +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(12,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,1,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(3,1,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,2,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(8,0,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_INLINE __inline +#else + #define JSON_HEDLEY_INLINE +#endif + +#if defined(JSON_HEDLEY_ALWAYS_INLINE) + #undef JSON_HEDLEY_ALWAYS_INLINE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(always_inline) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) +# define JSON_HEDLEY_ALWAYS_INLINE __attribute__((__always_inline__)) JSON_HEDLEY_INLINE +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(12,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) +# define JSON_HEDLEY_ALWAYS_INLINE __forceinline +#elif defined(__cplusplus) && \ + ( \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) \ + ) +# define JSON_HEDLEY_ALWAYS_INLINE _Pragma("FUNC_ALWAYS_INLINE;") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) +# define JSON_HEDLEY_ALWAYS_INLINE _Pragma("inline=forced") +#else +# define JSON_HEDLEY_ALWAYS_INLINE JSON_HEDLEY_INLINE +#endif + +#if defined(JSON_HEDLEY_NEVER_INLINE) + #undef JSON_HEDLEY_NEVER_INLINE +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(noinline) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(10,1,0) || \ + JSON_HEDLEY_TI_VERSION_CHECK(15,12,0) || \ + (JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(4,8,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_ARMCL_VERSION_CHECK(5,2,0) || \ + (JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL2000_VERSION_CHECK(6,4,0) || \ + (JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,0,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(4,3,0) || \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) || \ + JSON_HEDLEY_TI_CL7X_VERSION_CHECK(1,2,0) || \ + JSON_HEDLEY_TI_CLPRU_VERSION_CHECK(2,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ + JSON_HEDLEY_IAR_VERSION_CHECK(8,10,0) + #define JSON_HEDLEY_NEVER_INLINE __attribute__((__noinline__)) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,10,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_NEVER_INLINE __declspec(noinline) +#elif JSON_HEDLEY_PGI_VERSION_CHECK(10,2,0) + #define JSON_HEDLEY_NEVER_INLINE _Pragma("noinline") +#elif JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,0,0) && defined(__cplusplus) + #define JSON_HEDLEY_NEVER_INLINE _Pragma("FUNC_CANNOT_INLINE;") +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) + #define JSON_HEDLEY_NEVER_INLINE _Pragma("inline=never") +#elif JSON_HEDLEY_COMPCERT_VERSION_CHECK(3,2,0) + #define JSON_HEDLEY_NEVER_INLINE __attribute((noinline)) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(9,0,0) + #define JSON_HEDLEY_NEVER_INLINE __declspec(noinline) +#else + #define JSON_HEDLEY_NEVER_INLINE +#endif + +#if defined(JSON_HEDLEY_PRIVATE) + #undef JSON_HEDLEY_PRIVATE +#endif +#if defined(JSON_HEDLEY_PUBLIC) + #undef JSON_HEDLEY_PUBLIC +#endif +#if defined(JSON_HEDLEY_IMPORT) + #undef JSON_HEDLEY_IMPORT +#endif +#if defined(_WIN32) || defined(__CYGWIN__) +# define JSON_HEDLEY_PRIVATE +# define JSON_HEDLEY_PUBLIC __declspec(dllexport) +# define JSON_HEDLEY_IMPORT __declspec(dllimport) +#else +# if \ + JSON_HEDLEY_HAS_ATTRIBUTE(visibility) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,3,0) || \ + JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,11,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,0) || \ + ( \ + defined(__TI_EABI__) && \ + ( \ + (JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,2,0) && defined(__TI_GNU_ATTRIBUTE_SUPPORT__)) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(7,5,0) \ + ) \ + ) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) +# define JSON_HEDLEY_PRIVATE __attribute__((__visibility__("hidden"))) +# define JSON_HEDLEY_PUBLIC __attribute__((__visibility__("default"))) +# else +# define JSON_HEDLEY_PRIVATE +# define JSON_HEDLEY_PUBLIC +# endif +# define JSON_HEDLEY_IMPORT extern +#endif + +#if defined(JSON_HEDLEY_NO_THROW) + #undef JSON_HEDLEY_NO_THROW +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(nothrow) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,3,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_NO_THROW __attribute__((__nothrow__)) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(13,1,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) + #define JSON_HEDLEY_NO_THROW __declspec(nothrow) +#else + #define JSON_HEDLEY_NO_THROW +#endif + +#if defined(JSON_HEDLEY_FALL_THROUGH) + #undef JSON_HEDLEY_FALL_THROUGH +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(fallthrough) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(7,0,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_FALL_THROUGH __attribute__((__fallthrough__)) +#elif JSON_HEDLEY_HAS_CPP_ATTRIBUTE_NS(clang,fallthrough) + #define JSON_HEDLEY_FALL_THROUGH JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[clang::fallthrough]]) +#elif JSON_HEDLEY_HAS_CPP_ATTRIBUTE(fallthrough) + #define JSON_HEDLEY_FALL_THROUGH JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_([[fallthrough]]) +#elif defined(__fallthrough) /* SAL */ + #define JSON_HEDLEY_FALL_THROUGH __fallthrough +#else + #define JSON_HEDLEY_FALL_THROUGH +#endif + +#if defined(JSON_HEDLEY_RETURNS_NON_NULL) + #undef JSON_HEDLEY_RETURNS_NON_NULL +#endif +#if \ + JSON_HEDLEY_HAS_ATTRIBUTE(returns_nonnull) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,9,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_RETURNS_NON_NULL __attribute__((__returns_nonnull__)) +#elif defined(_Ret_notnull_) /* SAL */ + #define JSON_HEDLEY_RETURNS_NON_NULL _Ret_notnull_ +#else + #define JSON_HEDLEY_RETURNS_NON_NULL +#endif + +#if defined(JSON_HEDLEY_ARRAY_PARAM) + #undef JSON_HEDLEY_ARRAY_PARAM +#endif +#if \ + defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) && \ + !defined(__STDC_NO_VLA__) && \ + !defined(__cplusplus) && \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_TINYC_VERSION) + #define JSON_HEDLEY_ARRAY_PARAM(name) (name) +#else + #define JSON_HEDLEY_ARRAY_PARAM(name) +#endif + +#if defined(JSON_HEDLEY_IS_CONSTANT) + #undef JSON_HEDLEY_IS_CONSTANT +#endif +#if defined(JSON_HEDLEY_REQUIRE_CONSTEXPR) + #undef JSON_HEDLEY_REQUIRE_CONSTEXPR +#endif +/* JSON_HEDLEY_IS_CONSTEXPR_ is for + HEDLEY INTERNAL USE ONLY. API subject to change without notice. */ +#if defined(JSON_HEDLEY_IS_CONSTEXPR_) + #undef JSON_HEDLEY_IS_CONSTEXPR_ +#endif +#if \ + JSON_HEDLEY_HAS_BUILTIN(__builtin_constant_p) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,19) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,0) || \ + JSON_HEDLEY_TI_CL6X_VERSION_CHECK(6,1,0) || \ + (JSON_HEDLEY_SUNPRO_VERSION_CHECK(5,10,0) && !defined(__cplusplus)) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) + #define JSON_HEDLEY_IS_CONSTANT(expr) __builtin_constant_p(expr) +#endif +#if !defined(__cplusplus) +# if \ + JSON_HEDLEY_HAS_BUILTIN(__builtin_types_compatible_p) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(3,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(13,1,0) || \ + JSON_HEDLEY_CRAY_VERSION_CHECK(8,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,4,0) || \ + JSON_HEDLEY_TINYC_VERSION_CHECK(0,9,24) +#if defined(__INTPTR_TYPE__) + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) __builtin_types_compatible_p(__typeof__((1 ? (void*) ((__INTPTR_TYPE__) ((expr) * 0)) : (int*) 0)), int*) +#else + #include + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) __builtin_types_compatible_p(__typeof__((1 ? (void*) ((intptr_t) ((expr) * 0)) : (int*) 0)), int*) +#endif +# elif \ + ( \ + defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) && \ + !defined(JSON_HEDLEY_SUNPRO_VERSION) && \ + !defined(JSON_HEDLEY_PGI_VERSION) && \ + !defined(JSON_HEDLEY_IAR_VERSION)) || \ + (JSON_HEDLEY_HAS_EXTENSION(c_generic_selections) && !defined(JSON_HEDLEY_IAR_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,9,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(17,0,0) || \ + JSON_HEDLEY_IBM_VERSION_CHECK(12,1,0) || \ + JSON_HEDLEY_ARM_VERSION_CHECK(5,3,0) +#if defined(__INTPTR_TYPE__) + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) _Generic((1 ? (void*) ((__INTPTR_TYPE__) ((expr) * 0)) : (int*) 0), int*: 1, void*: 0) +#else + #include + #define JSON_HEDLEY_IS_CONSTEXPR_(expr) _Generic((1 ? (void*) ((intptr_t) * 0) : (int*) 0), int*: 1, void*: 0) +#endif +# elif \ + defined(JSON_HEDLEY_GCC_VERSION) || \ + defined(JSON_HEDLEY_INTEL_VERSION) || \ + defined(JSON_HEDLEY_TINYC_VERSION) || \ + defined(JSON_HEDLEY_TI_ARMCL_VERSION) || \ + JSON_HEDLEY_TI_CL430_VERSION_CHECK(18,12,0) || \ + defined(JSON_HEDLEY_TI_CL2000_VERSION) || \ + defined(JSON_HEDLEY_TI_CL6X_VERSION) || \ + defined(JSON_HEDLEY_TI_CL7X_VERSION) || \ + defined(JSON_HEDLEY_TI_CLPRU_VERSION) || \ + defined(__clang__) +# define JSON_HEDLEY_IS_CONSTEXPR_(expr) ( \ + sizeof(void) != \ + sizeof(*( \ + 1 ? \ + ((void*) ((expr) * 0L) ) : \ +((struct { char v[sizeof(void) * 2]; } *) 1) \ + ) \ + ) \ + ) +# endif +#endif +#if defined(JSON_HEDLEY_IS_CONSTEXPR_) + #if !defined(JSON_HEDLEY_IS_CONSTANT) + #define JSON_HEDLEY_IS_CONSTANT(expr) JSON_HEDLEY_IS_CONSTEXPR_(expr) + #endif + #define JSON_HEDLEY_REQUIRE_CONSTEXPR(expr) (JSON_HEDLEY_IS_CONSTEXPR_(expr) ? (expr) : (-1)) +#else + #if !defined(JSON_HEDLEY_IS_CONSTANT) + #define JSON_HEDLEY_IS_CONSTANT(expr) (0) + #endif + #define JSON_HEDLEY_REQUIRE_CONSTEXPR(expr) (expr) +#endif + +#if defined(JSON_HEDLEY_BEGIN_C_DECLS) + #undef JSON_HEDLEY_BEGIN_C_DECLS +#endif +#if defined(JSON_HEDLEY_END_C_DECLS) + #undef JSON_HEDLEY_END_C_DECLS +#endif +#if defined(JSON_HEDLEY_C_DECL) + #undef JSON_HEDLEY_C_DECL +#endif +#if defined(__cplusplus) + #define JSON_HEDLEY_BEGIN_C_DECLS extern "C" { + #define JSON_HEDLEY_END_C_DECLS } + #define JSON_HEDLEY_C_DECL extern "C" +#else + #define JSON_HEDLEY_BEGIN_C_DECLS + #define JSON_HEDLEY_END_C_DECLS + #define JSON_HEDLEY_C_DECL +#endif + +#if defined(JSON_HEDLEY_STATIC_ASSERT) + #undef JSON_HEDLEY_STATIC_ASSERT +#endif +#if \ + !defined(__cplusplus) && ( \ + (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)) || \ + (JSON_HEDLEY_HAS_FEATURE(c_static_assert) && !defined(JSON_HEDLEY_INTEL_CL_VERSION)) || \ + JSON_HEDLEY_GCC_VERSION_CHECK(6,0,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ + defined(_Static_assert) \ + ) +# define JSON_HEDLEY_STATIC_ASSERT(expr, message) _Static_assert(expr, message) +#elif \ + (defined(__cplusplus) && (__cplusplus >= 201103L)) || \ + JSON_HEDLEY_MSVC_VERSION_CHECK(16,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) +# define JSON_HEDLEY_STATIC_ASSERT(expr, message) JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(static_assert(expr, message)) +#else +# define JSON_HEDLEY_STATIC_ASSERT(expr, message) +#endif + +#if defined(JSON_HEDLEY_NULL) + #undef JSON_HEDLEY_NULL +#endif +#if defined(__cplusplus) + #if __cplusplus >= 201103L + #define JSON_HEDLEY_NULL JSON_HEDLEY_DIAGNOSTIC_DISABLE_CPP98_COMPAT_WRAP_(nullptr) + #elif defined(NULL) + #define JSON_HEDLEY_NULL NULL + #else + #define JSON_HEDLEY_NULL JSON_HEDLEY_STATIC_CAST(void*, 0) + #endif +#elif defined(NULL) + #define JSON_HEDLEY_NULL NULL +#else + #define JSON_HEDLEY_NULL ((void*) 0) +#endif + +#if defined(JSON_HEDLEY_MESSAGE) + #undef JSON_HEDLEY_MESSAGE +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-pragmas") +# define JSON_HEDLEY_MESSAGE(msg) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS \ + JSON_HEDLEY_PRAGMA(message msg) \ + JSON_HEDLEY_DIAGNOSTIC_POP +#elif \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(message msg) +#elif JSON_HEDLEY_CRAY_VERSION_CHECK(5,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(_CRI message msg) +#elif JSON_HEDLEY_IAR_VERSION_CHECK(8,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(message(msg)) +#elif JSON_HEDLEY_PELLES_VERSION_CHECK(2,0,0) +# define JSON_HEDLEY_MESSAGE(msg) JSON_HEDLEY_PRAGMA(message(msg)) +#else +# define JSON_HEDLEY_MESSAGE(msg) +#endif + +#if defined(JSON_HEDLEY_WARNING) + #undef JSON_HEDLEY_WARNING +#endif +#if JSON_HEDLEY_HAS_WARNING("-Wunknown-pragmas") +# define JSON_HEDLEY_WARNING(msg) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + JSON_HEDLEY_DIAGNOSTIC_DISABLE_UNKNOWN_PRAGMAS \ + JSON_HEDLEY_PRAGMA(clang warning msg) \ + JSON_HEDLEY_DIAGNOSTIC_POP +#elif \ + JSON_HEDLEY_GCC_VERSION_CHECK(4,8,0) || \ + JSON_HEDLEY_PGI_VERSION_CHECK(18,4,0) || \ + JSON_HEDLEY_INTEL_VERSION_CHECK(13,0,0) +# define JSON_HEDLEY_WARNING(msg) JSON_HEDLEY_PRAGMA(GCC warning msg) +#elif \ + JSON_HEDLEY_MSVC_VERSION_CHECK(15,0,0) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) +# define JSON_HEDLEY_WARNING(msg) JSON_HEDLEY_PRAGMA(message(msg)) +#else +# define JSON_HEDLEY_WARNING(msg) JSON_HEDLEY_MESSAGE(msg) +#endif + +#if defined(JSON_HEDLEY_REQUIRE) + #undef JSON_HEDLEY_REQUIRE +#endif +#if defined(JSON_HEDLEY_REQUIRE_MSG) + #undef JSON_HEDLEY_REQUIRE_MSG +#endif +#if JSON_HEDLEY_HAS_ATTRIBUTE(diagnose_if) +# if JSON_HEDLEY_HAS_WARNING("-Wgcc-compat") +# define JSON_HEDLEY_REQUIRE(expr) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wgcc-compat\"") \ + __attribute__((diagnose_if(!(expr), #expr, "error"))) \ + JSON_HEDLEY_DIAGNOSTIC_POP +# define JSON_HEDLEY_REQUIRE_MSG(expr,msg) \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("clang diagnostic ignored \"-Wgcc-compat\"") \ + __attribute__((diagnose_if(!(expr), msg, "error"))) \ + JSON_HEDLEY_DIAGNOSTIC_POP +# else +# define JSON_HEDLEY_REQUIRE(expr) __attribute__((diagnose_if(!(expr), #expr, "error"))) +# define JSON_HEDLEY_REQUIRE_MSG(expr,msg) __attribute__((diagnose_if(!(expr), msg, "error"))) +# endif +#else +# define JSON_HEDLEY_REQUIRE(expr) +# define JSON_HEDLEY_REQUIRE_MSG(expr,msg) +#endif + +#if defined(JSON_HEDLEY_FLAGS) + #undef JSON_HEDLEY_FLAGS +#endif +#if JSON_HEDLEY_HAS_ATTRIBUTE(flag_enum) && (!defined(__cplusplus) || JSON_HEDLEY_HAS_WARNING("-Wbitfield-enum-conversion")) + #define JSON_HEDLEY_FLAGS __attribute__((__flag_enum__)) +#else + #define JSON_HEDLEY_FLAGS +#endif + +#if defined(JSON_HEDLEY_FLAGS_CAST) + #undef JSON_HEDLEY_FLAGS_CAST +#endif +#if JSON_HEDLEY_INTEL_VERSION_CHECK(19,0,0) +# define JSON_HEDLEY_FLAGS_CAST(T, expr) (__extension__ ({ \ + JSON_HEDLEY_DIAGNOSTIC_PUSH \ + _Pragma("warning(disable:188)") \ + ((T) (expr)); \ + JSON_HEDLEY_DIAGNOSTIC_POP \ + })) +#else +# define JSON_HEDLEY_FLAGS_CAST(T, expr) JSON_HEDLEY_STATIC_CAST(T, expr) +#endif + +#if defined(JSON_HEDLEY_EMPTY_BASES) + #undef JSON_HEDLEY_EMPTY_BASES +#endif +#if \ + (JSON_HEDLEY_MSVC_VERSION_CHECK(19,0,23918) && !JSON_HEDLEY_MSVC_VERSION_CHECK(20,0,0)) || \ + JSON_HEDLEY_INTEL_CL_VERSION_CHECK(2021,1,0) + #define JSON_HEDLEY_EMPTY_BASES __declspec(empty_bases) +#else + #define JSON_HEDLEY_EMPTY_BASES +#endif + +/* Remaining macros are deprecated. */ + +#if defined(JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK) + #undef JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK +#endif +#if defined(__clang__) + #define JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK(major,minor,patch) (0) +#else + #define JSON_HEDLEY_GCC_NOT_CLANG_VERSION_CHECK(major,minor,patch) JSON_HEDLEY_GCC_VERSION_CHECK(major,minor,patch) +#endif + +#if defined(JSON_HEDLEY_CLANG_HAS_ATTRIBUTE) + #undef JSON_HEDLEY_CLANG_HAS_ATTRIBUTE +#endif +#define JSON_HEDLEY_CLANG_HAS_ATTRIBUTE(attribute) JSON_HEDLEY_HAS_ATTRIBUTE(attribute) + +#if defined(JSON_HEDLEY_CLANG_HAS_CPP_ATTRIBUTE) + #undef JSON_HEDLEY_CLANG_HAS_CPP_ATTRIBUTE +#endif +#define JSON_HEDLEY_CLANG_HAS_CPP_ATTRIBUTE(attribute) JSON_HEDLEY_HAS_CPP_ATTRIBUTE(attribute) + +#if defined(JSON_HEDLEY_CLANG_HAS_BUILTIN) + #undef JSON_HEDLEY_CLANG_HAS_BUILTIN +#endif +#define JSON_HEDLEY_CLANG_HAS_BUILTIN(builtin) JSON_HEDLEY_HAS_BUILTIN(builtin) + +#if defined(JSON_HEDLEY_CLANG_HAS_FEATURE) + #undef JSON_HEDLEY_CLANG_HAS_FEATURE +#endif +#define JSON_HEDLEY_CLANG_HAS_FEATURE(feature) JSON_HEDLEY_HAS_FEATURE(feature) + +#if defined(JSON_HEDLEY_CLANG_HAS_EXTENSION) + #undef JSON_HEDLEY_CLANG_HAS_EXTENSION +#endif +#define JSON_HEDLEY_CLANG_HAS_EXTENSION(extension) JSON_HEDLEY_HAS_EXTENSION(extension) + +#if defined(JSON_HEDLEY_CLANG_HAS_DECLSPEC_DECLSPEC_ATTRIBUTE) + #undef JSON_HEDLEY_CLANG_HAS_DECLSPEC_DECLSPEC_ATTRIBUTE +#endif +#define JSON_HEDLEY_CLANG_HAS_DECLSPEC_ATTRIBUTE(attribute) JSON_HEDLEY_HAS_DECLSPEC_ATTRIBUTE(attribute) + +#if defined(JSON_HEDLEY_CLANG_HAS_WARNING) + #undef JSON_HEDLEY_CLANG_HAS_WARNING +#endif +#define JSON_HEDLEY_CLANG_HAS_WARNING(warning) JSON_HEDLEY_HAS_WARNING(warning) + +#endif /* !defined(JSON_HEDLEY_VERSION) || (JSON_HEDLEY_VERSION < X) */ + + +// This file contains all internal macro definitions (except those affecting ABI) +// You MUST include macro_unscope.hpp at the end of json.hpp to undef all of them + +// #include + + +// exclude unsupported compilers +#if !defined(JSON_SKIP_UNSUPPORTED_COMPILER_CHECK) + #if defined(__clang__) + #if (__clang_major__ * 10000 + __clang_minor__ * 100 + __clang_patchlevel__) < 30400 + #error "unsupported Clang version - see https://github.com/nlohmann/json#supported-compilers" + #endif + #elif defined(__GNUC__) && !(defined(__ICC) || defined(__INTEL_COMPILER)) + #if (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) < 40800 + #error "unsupported GCC version - see https://github.com/nlohmann/json#supported-compilers" + #endif + #endif +#endif + +// C++ language standard detection +// if the user manually specified the used c++ version this is skipped +#if !defined(JSON_HAS_CPP_20) && !defined(JSON_HAS_CPP_17) && !defined(JSON_HAS_CPP_14) && !defined(JSON_HAS_CPP_11) + #if (defined(__cplusplus) && __cplusplus >= 202002L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 202002L) + #define JSON_HAS_CPP_20 + #define JSON_HAS_CPP_17 + #define JSON_HAS_CPP_14 + #elif (defined(__cplusplus) && __cplusplus >= 201703L) || (defined(_HAS_CXX17) && _HAS_CXX17 == 1) // fix for issue #464 + #define JSON_HAS_CPP_17 + #define JSON_HAS_CPP_14 + #elif (defined(__cplusplus) && __cplusplus >= 201402L) || (defined(_HAS_CXX14) && _HAS_CXX14 == 1) + #define JSON_HAS_CPP_14 + #endif + // the cpp 11 flag is always specified because it is the minimal required version + #define JSON_HAS_CPP_11 +#endif + +#ifdef __has_include + #if __has_include() + #include + #endif +#endif + +#if !defined(JSON_HAS_FILESYSTEM) && !defined(JSON_HAS_EXPERIMENTAL_FILESYSTEM) + #ifdef JSON_HAS_CPP_17 + #if defined(__cpp_lib_filesystem) + #define JSON_HAS_FILESYSTEM 1 + #elif defined(__cpp_lib_experimental_filesystem) + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 1 + #elif !defined(__has_include) + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 1 + #elif __has_include() + #define JSON_HAS_FILESYSTEM 1 + #elif __has_include() + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 1 + #endif + + // std::filesystem does not work on MinGW GCC 8: https://sourceforge.net/p/mingw-w64/bugs/737/ + #if defined(__MINGW32__) && defined(__GNUC__) && __GNUC__ == 8 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before GCC 8: https://en.cppreference.com/w/cpp/compiler_support + #if defined(__GNUC__) && !defined(__clang__) && __GNUC__ < 8 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before Clang 7: https://en.cppreference.com/w/cpp/compiler_support + #if defined(__clang_major__) && __clang_major__ < 7 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before MSVC 19.14: https://en.cppreference.com/w/cpp/compiler_support + #if defined(_MSC_VER) && _MSC_VER < 1914 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before iOS 13 + #if defined(__IPHONE_OS_VERSION_MIN_REQUIRED) && __IPHONE_OS_VERSION_MIN_REQUIRED < 130000 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + + // no filesystem support before macOS Catalina + #if defined(__MAC_OS_X_VERSION_MIN_REQUIRED) && __MAC_OS_X_VERSION_MIN_REQUIRED < 101500 + #undef JSON_HAS_FILESYSTEM + #undef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #endif + #endif +#endif + +#ifndef JSON_HAS_EXPERIMENTAL_FILESYSTEM + #define JSON_HAS_EXPERIMENTAL_FILESYSTEM 0 +#endif + +#ifndef JSON_HAS_FILESYSTEM + #define JSON_HAS_FILESYSTEM 0 +#endif + +#ifndef JSON_HAS_THREE_WAY_COMPARISON + #if defined(__cpp_impl_three_way_comparison) && __cpp_impl_three_way_comparison >= 201907L \ + && defined(__cpp_lib_three_way_comparison) && __cpp_lib_three_way_comparison >= 201907L + #define JSON_HAS_THREE_WAY_COMPARISON 1 + #else + #define JSON_HAS_THREE_WAY_COMPARISON 0 + #endif +#endif + +#ifndef JSON_HAS_RANGES + // ranges header shipping in GCC 11.1.0 (released 2021-04-27) has syntax error + #if defined(__GLIBCXX__) && __GLIBCXX__ == 20210427 + #define JSON_HAS_RANGES 0 + #elif defined(__cpp_lib_ranges) + #define JSON_HAS_RANGES 1 + #else + #define JSON_HAS_RANGES 0 + #endif +#endif + +#ifdef JSON_HAS_CPP_17 + #define JSON_INLINE_VARIABLE inline +#else + #define JSON_INLINE_VARIABLE +#endif + +#if JSON_HEDLEY_HAS_ATTRIBUTE(no_unique_address) + #define JSON_NO_UNIQUE_ADDRESS [[no_unique_address]] +#else + #define JSON_NO_UNIQUE_ADDRESS +#endif + +// disable documentation warnings on clang +#if defined(__clang__) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wdocumentation" + #pragma clang diagnostic ignored "-Wdocumentation-unknown-command" +#endif + +// allow disabling exceptions +#if (defined(__cpp_exceptions) || defined(__EXCEPTIONS) || defined(_CPPUNWIND)) && !defined(JSON_NOEXCEPTION) + #define JSON_THROW(exception) throw exception + #define JSON_TRY try + #define JSON_CATCH(exception) catch(exception) + #define JSON_INTERNAL_CATCH(exception) catch(exception) +#else + #include + #define JSON_THROW(exception) std::abort() + #define JSON_TRY if(true) + #define JSON_CATCH(exception) if(false) + #define JSON_INTERNAL_CATCH(exception) if(false) +#endif + +// override exception macros +#if defined(JSON_THROW_USER) + #undef JSON_THROW + #define JSON_THROW JSON_THROW_USER +#endif +#if defined(JSON_TRY_USER) + #undef JSON_TRY + #define JSON_TRY JSON_TRY_USER +#endif +#if defined(JSON_CATCH_USER) + #undef JSON_CATCH + #define JSON_CATCH JSON_CATCH_USER + #undef JSON_INTERNAL_CATCH + #define JSON_INTERNAL_CATCH JSON_CATCH_USER +#endif +#if defined(JSON_INTERNAL_CATCH_USER) + #undef JSON_INTERNAL_CATCH + #define JSON_INTERNAL_CATCH JSON_INTERNAL_CATCH_USER +#endif + +// allow overriding assert +#if !defined(JSON_ASSERT) + #include // assert + #define JSON_ASSERT(x) assert(x) +#endif + +// allow to access some private functions (needed by the test suite) +#if defined(JSON_TESTS_PRIVATE) + #define JSON_PRIVATE_UNLESS_TESTED public +#else + #define JSON_PRIVATE_UNLESS_TESTED private +#endif + +/*! +@brief macro to briefly define a mapping between an enum and JSON +@def NLOHMANN_JSON_SERIALIZE_ENUM +@since version 3.4.0 +*/ +#define NLOHMANN_JSON_SERIALIZE_ENUM(ENUM_TYPE, ...) \ + template \ + inline void to_json(BasicJsonType& j, const ENUM_TYPE& e) \ + { \ + static_assert(std::is_enum::value, #ENUM_TYPE " must be an enum!"); \ + static const std::pair m[] = __VA_ARGS__; \ + auto it = std::find_if(std::begin(m), std::end(m), \ + [e](const std::pair& ej_pair) -> bool \ + { \ + return ej_pair.first == e; \ + }); \ + j = ((it != std::end(m)) ? it : std::begin(m))->second; \ + } \ + template \ + inline void from_json(const BasicJsonType& j, ENUM_TYPE& e) \ + { \ + static_assert(std::is_enum::value, #ENUM_TYPE " must be an enum!"); \ + static const std::pair m[] = __VA_ARGS__; \ + auto it = std::find_if(std::begin(m), std::end(m), \ + [&j](const std::pair& ej_pair) -> bool \ + { \ + return ej_pair.second == j; \ + }); \ + e = ((it != std::end(m)) ? it : std::begin(m))->first; \ + } + +// Ugly macros to avoid uglier copy-paste when specializing basic_json. They +// may be removed in the future once the class is split. + +#define NLOHMANN_BASIC_JSON_TPL_DECLARATION \ + template class ObjectType, \ + template class ArrayType, \ + class StringType, class BooleanType, class NumberIntegerType, \ + class NumberUnsignedType, class NumberFloatType, \ + template class AllocatorType, \ + template class JSONSerializer, \ + class BinaryType, \ + class CustomBaseClass> + +#define NLOHMANN_BASIC_JSON_TPL \ + basic_json + +// Macros to simplify conversion from/to types + +#define NLOHMANN_JSON_EXPAND( x ) x +#define NLOHMANN_JSON_GET_MACRO(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, _61, _62, _63, _64, NAME,...) NAME +#define NLOHMANN_JSON_PASTE(...) NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_GET_MACRO(__VA_ARGS__, \ + NLOHMANN_JSON_PASTE64, \ + NLOHMANN_JSON_PASTE63, \ + NLOHMANN_JSON_PASTE62, \ + NLOHMANN_JSON_PASTE61, \ + NLOHMANN_JSON_PASTE60, \ + NLOHMANN_JSON_PASTE59, \ + NLOHMANN_JSON_PASTE58, \ + NLOHMANN_JSON_PASTE57, \ + NLOHMANN_JSON_PASTE56, \ + NLOHMANN_JSON_PASTE55, \ + NLOHMANN_JSON_PASTE54, \ + NLOHMANN_JSON_PASTE53, \ + NLOHMANN_JSON_PASTE52, \ + NLOHMANN_JSON_PASTE51, \ + NLOHMANN_JSON_PASTE50, \ + NLOHMANN_JSON_PASTE49, \ + NLOHMANN_JSON_PASTE48, \ + NLOHMANN_JSON_PASTE47, \ + NLOHMANN_JSON_PASTE46, \ + NLOHMANN_JSON_PASTE45, \ + NLOHMANN_JSON_PASTE44, \ + NLOHMANN_JSON_PASTE43, \ + NLOHMANN_JSON_PASTE42, \ + NLOHMANN_JSON_PASTE41, \ + NLOHMANN_JSON_PASTE40, \ + NLOHMANN_JSON_PASTE39, \ + NLOHMANN_JSON_PASTE38, \ + NLOHMANN_JSON_PASTE37, \ + NLOHMANN_JSON_PASTE36, \ + NLOHMANN_JSON_PASTE35, \ + NLOHMANN_JSON_PASTE34, \ + NLOHMANN_JSON_PASTE33, \ + NLOHMANN_JSON_PASTE32, \ + NLOHMANN_JSON_PASTE31, \ + NLOHMANN_JSON_PASTE30, \ + NLOHMANN_JSON_PASTE29, \ + NLOHMANN_JSON_PASTE28, \ + NLOHMANN_JSON_PASTE27, \ + NLOHMANN_JSON_PASTE26, \ + NLOHMANN_JSON_PASTE25, \ + NLOHMANN_JSON_PASTE24, \ + NLOHMANN_JSON_PASTE23, \ + NLOHMANN_JSON_PASTE22, \ + NLOHMANN_JSON_PASTE21, \ + NLOHMANN_JSON_PASTE20, \ + NLOHMANN_JSON_PASTE19, \ + NLOHMANN_JSON_PASTE18, \ + NLOHMANN_JSON_PASTE17, \ + NLOHMANN_JSON_PASTE16, \ + NLOHMANN_JSON_PASTE15, \ + NLOHMANN_JSON_PASTE14, \ + NLOHMANN_JSON_PASTE13, \ + NLOHMANN_JSON_PASTE12, \ + NLOHMANN_JSON_PASTE11, \ + NLOHMANN_JSON_PASTE10, \ + NLOHMANN_JSON_PASTE9, \ + NLOHMANN_JSON_PASTE8, \ + NLOHMANN_JSON_PASTE7, \ + NLOHMANN_JSON_PASTE6, \ + NLOHMANN_JSON_PASTE5, \ + NLOHMANN_JSON_PASTE4, \ + NLOHMANN_JSON_PASTE3, \ + NLOHMANN_JSON_PASTE2, \ + NLOHMANN_JSON_PASTE1)(__VA_ARGS__)) +#define NLOHMANN_JSON_PASTE2(func, v1) func(v1) +#define NLOHMANN_JSON_PASTE3(func, v1, v2) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE2(func, v2) +#define NLOHMANN_JSON_PASTE4(func, v1, v2, v3) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE3(func, v2, v3) +#define NLOHMANN_JSON_PASTE5(func, v1, v2, v3, v4) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE4(func, v2, v3, v4) +#define NLOHMANN_JSON_PASTE6(func, v1, v2, v3, v4, v5) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE5(func, v2, v3, v4, v5) +#define NLOHMANN_JSON_PASTE7(func, v1, v2, v3, v4, v5, v6) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE6(func, v2, v3, v4, v5, v6) +#define NLOHMANN_JSON_PASTE8(func, v1, v2, v3, v4, v5, v6, v7) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE7(func, v2, v3, v4, v5, v6, v7) +#define NLOHMANN_JSON_PASTE9(func, v1, v2, v3, v4, v5, v6, v7, v8) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE8(func, v2, v3, v4, v5, v6, v7, v8) +#define NLOHMANN_JSON_PASTE10(func, v1, v2, v3, v4, v5, v6, v7, v8, v9) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE9(func, v2, v3, v4, v5, v6, v7, v8, v9) +#define NLOHMANN_JSON_PASTE11(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE10(func, v2, v3, v4, v5, v6, v7, v8, v9, v10) +#define NLOHMANN_JSON_PASTE12(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE11(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11) +#define NLOHMANN_JSON_PASTE13(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE12(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12) +#define NLOHMANN_JSON_PASTE14(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE13(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13) +#define NLOHMANN_JSON_PASTE15(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE14(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14) +#define NLOHMANN_JSON_PASTE16(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE15(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15) +#define NLOHMANN_JSON_PASTE17(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE16(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16) +#define NLOHMANN_JSON_PASTE18(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE17(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17) +#define NLOHMANN_JSON_PASTE19(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE18(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18) +#define NLOHMANN_JSON_PASTE20(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE19(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19) +#define NLOHMANN_JSON_PASTE21(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE20(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20) +#define NLOHMANN_JSON_PASTE22(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE21(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21) +#define NLOHMANN_JSON_PASTE23(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE22(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22) +#define NLOHMANN_JSON_PASTE24(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE23(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23) +#define NLOHMANN_JSON_PASTE25(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE24(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24) +#define NLOHMANN_JSON_PASTE26(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE25(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25) +#define NLOHMANN_JSON_PASTE27(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE26(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26) +#define NLOHMANN_JSON_PASTE28(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE27(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27) +#define NLOHMANN_JSON_PASTE29(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE28(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28) +#define NLOHMANN_JSON_PASTE30(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE29(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29) +#define NLOHMANN_JSON_PASTE31(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE30(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30) +#define NLOHMANN_JSON_PASTE32(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE31(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31) +#define NLOHMANN_JSON_PASTE33(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE32(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32) +#define NLOHMANN_JSON_PASTE34(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE33(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33) +#define NLOHMANN_JSON_PASTE35(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE34(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34) +#define NLOHMANN_JSON_PASTE36(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE35(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35) +#define NLOHMANN_JSON_PASTE37(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE36(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36) +#define NLOHMANN_JSON_PASTE38(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE37(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37) +#define NLOHMANN_JSON_PASTE39(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE38(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38) +#define NLOHMANN_JSON_PASTE40(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE39(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39) +#define NLOHMANN_JSON_PASTE41(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE40(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40) +#define NLOHMANN_JSON_PASTE42(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE41(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41) +#define NLOHMANN_JSON_PASTE43(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE42(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42) +#define NLOHMANN_JSON_PASTE44(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE43(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43) +#define NLOHMANN_JSON_PASTE45(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE44(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44) +#define NLOHMANN_JSON_PASTE46(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE45(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45) +#define NLOHMANN_JSON_PASTE47(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE46(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46) +#define NLOHMANN_JSON_PASTE48(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE47(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47) +#define NLOHMANN_JSON_PASTE49(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE48(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48) +#define NLOHMANN_JSON_PASTE50(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE49(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49) +#define NLOHMANN_JSON_PASTE51(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE50(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50) +#define NLOHMANN_JSON_PASTE52(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE51(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51) +#define NLOHMANN_JSON_PASTE53(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE52(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52) +#define NLOHMANN_JSON_PASTE54(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE53(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53) +#define NLOHMANN_JSON_PASTE55(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE54(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54) +#define NLOHMANN_JSON_PASTE56(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE55(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55) +#define NLOHMANN_JSON_PASTE57(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE56(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56) +#define NLOHMANN_JSON_PASTE58(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE57(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57) +#define NLOHMANN_JSON_PASTE59(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE58(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58) +#define NLOHMANN_JSON_PASTE60(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE59(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59) +#define NLOHMANN_JSON_PASTE61(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE60(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60) +#define NLOHMANN_JSON_PASTE62(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE61(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61) +#define NLOHMANN_JSON_PASTE63(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE62(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62) +#define NLOHMANN_JSON_PASTE64(func, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63) NLOHMANN_JSON_PASTE2(func, v1) NLOHMANN_JSON_PASTE63(func, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63) + +#define NLOHMANN_JSON_TO(v1) nlohmann_json_j[#v1] = nlohmann_json_t.v1; +#define NLOHMANN_JSON_FROM(v1) nlohmann_json_j.at(#v1).get_to(nlohmann_json_t.v1); +#define NLOHMANN_JSON_FROM_WITH_DEFAULT(v1) nlohmann_json_t.v1 = nlohmann_json_j.value(#v1, nlohmann_json_default_obj.v1); + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_INTRUSIVE +@since version 3.9.0 +*/ +#define NLOHMANN_DEFINE_TYPE_INTRUSIVE(Type, ...) \ + friend void to_json(nlohmann::json& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + friend void from_json(const nlohmann::json& nlohmann_json_j, Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM, __VA_ARGS__)) } + +#define NLOHMANN_DEFINE_TYPE_INTRUSIVE_WITH_DEFAULT(Type, ...) \ + friend void to_json(nlohmann::json& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + friend void from_json(const nlohmann::json& nlohmann_json_j, Type& nlohmann_json_t) { const Type nlohmann_json_default_obj{}; NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM_WITH_DEFAULT, __VA_ARGS__)) } + +/*! +@brief macro +@def NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE +@since version 3.9.0 +*/ +#define NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE(Type, ...) \ + inline void to_json(nlohmann::json& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + inline void from_json(const nlohmann::json& nlohmann_json_j, Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM, __VA_ARGS__)) } + +#define NLOHMANN_DEFINE_TYPE_NON_INTRUSIVE_WITH_DEFAULT(Type, ...) \ + inline void to_json(nlohmann::json& nlohmann_json_j, const Type& nlohmann_json_t) { NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_TO, __VA_ARGS__)) } \ + inline void from_json(const nlohmann::json& nlohmann_json_j, Type& nlohmann_json_t) { const Type nlohmann_json_default_obj{}; NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(NLOHMANN_JSON_FROM_WITH_DEFAULT, __VA_ARGS__)) } + + +// inspired from https://stackoverflow.com/a/26745591 +// allows to call any std function as if (e.g. with begin): +// using std::begin; begin(x); +// +// it allows using the detected idiom to retrieve the return type +// of such an expression +#define NLOHMANN_CAN_CALL_STD_FUNC_IMPL(std_name) \ + namespace detail { \ + using std::std_name; \ + \ + template \ + using result_of_##std_name = decltype(std_name(std::declval()...)); \ + } \ + \ + namespace detail2 { \ + struct std_name##_tag \ + { \ + }; \ + \ + template \ + std_name##_tag std_name(T&&...); \ + \ + template \ + using result_of_##std_name = decltype(std_name(std::declval()...)); \ + \ + template \ + struct would_call_std_##std_name \ + { \ + static constexpr auto const value = ::nlohmann::detail:: \ + is_detected_exact::value; \ + }; \ + } /* namespace detail2 */ \ + \ + template \ + struct would_call_std_##std_name : detail2::would_call_std_##std_name \ + { \ + } + +#ifndef JSON_USE_IMPLICIT_CONVERSIONS + #define JSON_USE_IMPLICIT_CONVERSIONS 1 +#endif + +#if JSON_USE_IMPLICIT_CONVERSIONS + #define JSON_EXPLICIT +#else + #define JSON_EXPLICIT explicit +#endif + +#ifndef JSON_DISABLE_ENUM_SERIALIZATION + #define JSON_DISABLE_ENUM_SERIALIZATION 0 +#endif + +#ifndef JSON_USE_GLOBAL_UDLS + #define JSON_USE_GLOBAL_UDLS 1 +#endif + +#if JSON_HAS_THREE_WAY_COMPARISON + #include // partial_ordering +#endif + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +/////////////////////////// +// JSON type enumeration // +/////////////////////////// + +/*! +@brief the JSON type enumeration + +This enumeration collects the different JSON types. It is internally used to +distinguish the stored values, and the functions @ref basic_json::is_null(), +@ref basic_json::is_object(), @ref basic_json::is_array(), +@ref basic_json::is_string(), @ref basic_json::is_boolean(), +@ref basic_json::is_number() (with @ref basic_json::is_number_integer(), +@ref basic_json::is_number_unsigned(), and @ref basic_json::is_number_float()), +@ref basic_json::is_discarded(), @ref basic_json::is_primitive(), and +@ref basic_json::is_structured() rely on it. + +@note There are three enumeration entries (number_integer, number_unsigned, and +number_float), because the library distinguishes these three types for numbers: +@ref basic_json::number_unsigned_t is used for unsigned integers, +@ref basic_json::number_integer_t is used for signed integers, and +@ref basic_json::number_float_t is used for floating-point numbers or to +approximate integers which do not fit in the limits of their respective type. + +@sa see @ref basic_json::basic_json(const value_t value_type) -- create a JSON +value with the default value for a given type + +@since version 1.0.0 +*/ +enum class value_t : std::uint8_t +{ + null, ///< null value + object, ///< object (unordered set of name/value pairs) + array, ///< array (ordered collection of values) + string, ///< string value + boolean, ///< boolean value + number_integer, ///< number value (signed integer) + number_unsigned, ///< number value (unsigned integer) + number_float, ///< number value (floating-point) + binary, ///< binary array (ordered collection of bytes) + discarded ///< discarded by the parser callback function +}; + +/*! +@brief comparison operator for JSON types + +Returns an ordering that is similar to Python: +- order: null < boolean < number < object < array < string < binary +- furthermore, each type is not smaller than itself +- discarded values are not comparable +- binary is represented as a b"" string in python and directly comparable to a + string; however, making a binary array directly comparable with a string would + be surprising behavior in a JSON file. + +@since version 1.0.0 +*/ +#if JSON_HAS_THREE_WAY_COMPARISON + inline std::partial_ordering operator<=>(const value_t lhs, const value_t rhs) noexcept // *NOPAD* +#else + inline bool operator<(const value_t lhs, const value_t rhs) noexcept +#endif +{ + static constexpr std::array order = {{ + 0 /* null */, 3 /* object */, 4 /* array */, 5 /* string */, + 1 /* boolean */, 2 /* integer */, 2 /* unsigned */, 2 /* float */, + 6 /* binary */ + } + }; + + const auto l_index = static_cast(lhs); + const auto r_index = static_cast(rhs); +#if JSON_HAS_THREE_WAY_COMPARISON + if (l_index < order.size() && r_index < order.size()) + { + return order[l_index] <=> order[r_index]; // *NOPAD* + } + return std::partial_ordering::unordered; +#else + return l_index < order.size() && r_index < order.size() && order[l_index] < order[r_index]; +#endif +} + +// GCC selects the built-in operator< over an operator rewritten from +// a user-defined spaceship operator +// Clang, MSVC, and ICC select the rewritten candidate +// (see GCC bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105200) +#if JSON_HAS_THREE_WAY_COMPARISON && defined(__GNUC__) +inline bool operator<(const value_t lhs, const value_t rhs) noexcept +{ + return std::is_lt(lhs <=> rhs); // *NOPAD* +} +#endif + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +/*! +@brief replace all occurrences of a substring by another string + +@param[in,out] s the string to manipulate; changed so that all + occurrences of @a f are replaced with @a t +@param[in] f the substring to replace with @a t +@param[in] t the string to replace @a f + +@pre The search string @a f must not be empty. **This precondition is +enforced with an assertion.** + +@since version 2.0.0 +*/ +template +inline void replace_substring(StringType& s, const StringType& f, + const StringType& t) +{ + JSON_ASSERT(!f.empty()); + for (auto pos = s.find(f); // find first occurrence of f + pos != StringType::npos; // make sure f was found + s.replace(pos, f.size(), t), // replace with t, and + pos = s.find(f, pos + t.size())) // find next occurrence of f + {} +} + +/*! + * @brief string escaping as described in RFC 6901 (Sect. 4) + * @param[in] s string to escape + * @return escaped string + * + * Note the order of escaping "~" to "~0" and "/" to "~1" is important. + */ +template +inline StringType escape(StringType s) +{ + replace_substring(s, StringType{"~"}, StringType{"~0"}); + replace_substring(s, StringType{"/"}, StringType{"~1"}); + return s; +} + +/*! + * @brief string unescaping as described in RFC 6901 (Sect. 4) + * @param[in] s string to unescape + * @return unescaped string + * + * Note the order of escaping "~1" to "/" and "~0" to "~" is important. + */ +template +static void unescape(StringType& s) +{ + replace_substring(s, StringType{"~1"}, StringType{"/"}); + replace_substring(s, StringType{"~0"}, StringType{"~"}); +} + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // size_t + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +/// struct to capture the start position of the current token +struct position_t +{ + /// the total number of characters read + std::size_t chars_read_total = 0; + /// the number of characters read in the current line + std::size_t chars_read_current_line = 0; + /// the number of lines read + std::size_t lines_read = 0; + + /// conversion to size_t to preserve SAX interface + constexpr operator size_t() const + { + return chars_read_total; + } +}; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-FileCopyrightText: 2018 The Abseil Authors +// SPDX-License-Identifier: MIT + + + +#include // array +#include // size_t +#include // conditional, enable_if, false_type, integral_constant, is_constructible, is_integral, is_same, remove_cv, remove_reference, true_type +#include // index_sequence, make_index_sequence, index_sequence_for + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +template +using uncvref_t = typename std::remove_cv::type>::type; + +#ifdef JSON_HAS_CPP_14 + +// the following utilities are natively available in C++14 +using std::enable_if_t; +using std::index_sequence; +using std::make_index_sequence; +using std::index_sequence_for; + +#else + +// alias templates to reduce boilerplate +template +using enable_if_t = typename std::enable_if::type; + +// The following code is taken from https://github.com/abseil/abseil-cpp/blob/10cb35e459f5ecca5b2ff107635da0bfa41011b4/absl/utility/utility.h +// which is part of Google Abseil (https://github.com/abseil/abseil-cpp), licensed under the Apache License 2.0. + +//// START OF CODE FROM GOOGLE ABSEIL + +// integer_sequence +// +// Class template representing a compile-time integer sequence. An instantiation +// of `integer_sequence` has a sequence of integers encoded in its +// type through its template arguments (which is a common need when +// working with C++11 variadic templates). `absl::integer_sequence` is designed +// to be a drop-in replacement for C++14's `std::integer_sequence`. +// +// Example: +// +// template< class T, T... Ints > +// void user_function(integer_sequence); +// +// int main() +// { +// // user_function's `T` will be deduced to `int` and `Ints...` +// // will be deduced to `0, 1, 2, 3, 4`. +// user_function(make_integer_sequence()); +// } +template +struct integer_sequence +{ + using value_type = T; + static constexpr std::size_t size() noexcept + { + return sizeof...(Ints); + } +}; + +// index_sequence +// +// A helper template for an `integer_sequence` of `size_t`, +// `absl::index_sequence` is designed to be a drop-in replacement for C++14's +// `std::index_sequence`. +template +using index_sequence = integer_sequence; + +namespace utility_internal +{ + +template +struct Extend; + +// Note that SeqSize == sizeof...(Ints). It's passed explicitly for efficiency. +template +struct Extend, SeqSize, 0> +{ + using type = integer_sequence < T, Ints..., (Ints + SeqSize)... >; +}; + +template +struct Extend, SeqSize, 1> +{ + using type = integer_sequence < T, Ints..., (Ints + SeqSize)..., 2 * SeqSize >; +}; + +// Recursion helper for 'make_integer_sequence'. +// 'Gen::type' is an alias for 'integer_sequence'. +template +struct Gen +{ + using type = + typename Extend < typename Gen < T, N / 2 >::type, N / 2, N % 2 >::type; +}; + +template +struct Gen +{ + using type = integer_sequence; +}; + +} // namespace utility_internal + +// Compile-time sequences of integers + +// make_integer_sequence +// +// This template alias is equivalent to +// `integer_sequence`, and is designed to be a drop-in +// replacement for C++14's `std::make_integer_sequence`. +template +using make_integer_sequence = typename utility_internal::Gen::type; + +// make_index_sequence +// +// This template alias is equivalent to `index_sequence<0, 1, ..., N-1>`, +// and is designed to be a drop-in replacement for C++14's +// `std::make_index_sequence`. +template +using make_index_sequence = make_integer_sequence; + +// index_sequence_for +// +// Converts a typename pack into an index sequence of the same length, and +// is designed to be a drop-in replacement for C++14's +// `std::index_sequence_for()` +template +using index_sequence_for = make_index_sequence; + +//// END OF CODE FROM GOOGLE ABSEIL + +#endif + +// dispatch utility (taken from ranges-v3) +template struct priority_tag : priority_tag < N - 1 > {}; +template<> struct priority_tag<0> {}; + +// taken from ranges-v3 +template +struct static_const +{ + static JSON_INLINE_VARIABLE constexpr T value{}; +}; + +#ifndef JSON_HAS_CPP_17 + template + constexpr T static_const::value; +#endif + +template +inline constexpr std::array make_array(Args&& ... args) +{ + return std::array {{static_cast(std::forward(args))...}}; +} + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // numeric_limits +#include // false_type, is_constructible, is_integral, is_same, true_type +#include // declval +#include // tuple + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +#include // random_access_iterator_tag + +// #include + +// #include + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN +namespace detail +{ + +template +struct iterator_types {}; + +template +struct iterator_types < + It, + void_t> +{ + using difference_type = typename It::difference_type; + using value_type = typename It::value_type; + using pointer = typename It::pointer; + using reference = typename It::reference; + using iterator_category = typename It::iterator_category; +}; + +// This is required as some compilers implement std::iterator_traits in a way that +// doesn't work with SFINAE. See https://github.com/nlohmann/json/issues/1341. +template +struct iterator_traits +{ +}; + +template +struct iterator_traits < T, enable_if_t < !std::is_pointer::value >> + : iterator_types +{ +}; + +template +struct iterator_traits::value>> +{ + using iterator_category = std::random_access_iterator_tag; + using value_type = T; + using difference_type = ptrdiff_t; + using pointer = T*; + using reference = T&; +}; + +} // namespace detail +NLOHMANN_JSON_NAMESPACE_END + +// #include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN + +NLOHMANN_CAN_CALL_STD_FUNC_IMPL(begin); + +NLOHMANN_JSON_NAMESPACE_END + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + + + +// #include + + +NLOHMANN_JSON_NAMESPACE_BEGIN + +NLOHMANN_CAN_CALL_STD_FUNC_IMPL(end); + +NLOHMANN_JSON_NAMESPACE_END + +// #include + +// #include + +// #include +// __ _____ _____ _____ +// __| | __| | | | JSON for Modern C++ +// | | |__ | | | | | | version 3.11.2 +// |_____|_____|_____|_|___| https://github.com/nlohmann/json +// +// SPDX-FileCopyrightText: 2013-2022 Niels Lohmann +// SPDX-License-Identifier: MIT + +#ifndef INCLUDE_NLOHMANN_JSON_FWD_HPP_ + #define INCLUDE_NLOHMANN_JSON_FWD_HPP_ + + #include // int64_t, uint64_t + #include // map + #include // allocator + #include // string + #include // vector + + // #include + + + /*! + @brief namespace for Niels Lohmann + @see https://github.com/nlohmann + @since version 1.0.0 + */ + NLOHMANN_JSON_NAMESPACE_BEGIN + + /*! + @brief default JSONSerializer template argument + + This serializer ignores the template arguments and uses ADL + ([argument-dependent lookup](https://en.cppreference.com/w/cpp/language/adl)) + for serialization. + */ + template + struct adl_serializer; + + /// a class to store JSON values + /// @sa https://json.nlohmann.me/api/basic_json/ + template class ObjectType = + std::map, + template class ArrayType = std::vector, + class StringType = std::string, class BooleanType = bool, + class NumberIntegerType = std::int64_t, + class NumberUnsignedType = std::uint64_t, + class NumberFloatType = double, + template class AllocatorType = std::allocator, + template class JSONSerializer = + adl_serializer, + class BinaryType = std::vector, // cppcheck-suppress syntaxError + class CustomBaseClass = void> + class basic_json; + + /// @brief JSON Pointer defines a string syntax for identifying a specific value within a JSON document + /// @sa https://json.nlohmann.me/api/json_pointer/ + template + class json_pointer; + + /*! + @brief default specialization + @sa https://json.nlohmann.me/api/json/ + */ + using json = basic_json<>; + + /// @brief a minimal map-like container that preserves insertion order + /// @sa https://json.nlohmann.me/api/ordered_map/ + template + struct ordered_map; + + /// @brief specialization that maintains the insertion order of object keys + /// @sa https://json.nlohmann.me/api/ordered_json/ + using ordered_json = basic_json; + + NLOHMANN_JSON_NAMESPACE_END + +#endif // INCLUDE_NLOHMANN_JSON_FWD_HPP_ + + +NLOHMANN_JSON_NAMESPACE_BEGIN +/*! +@brief detail namespace with internal helper functions + +This namespace collects functions that should not be exposed, +implementations of some @ref basic_json methods, and meta-programming helpers. + +@since version 2.1.0 +*/ +namespace detail +{ + +///////////// +// helpers // +///////////// + +// Note to maintainers: +// +// Every trait in this file expects a non CV-qualified type. +// The only exceptions are in the 'aliases for detected' section +// (i.e. those of the form: decltype(T::member_function(std::declval()))) +// +// In this case, T has to be properly CV-qualified to constraint the function arguments +// (e.g. to_json(BasicJsonType&, const T&)) + +template struct is_basic_json : std::false_type {}; + +NLOHMANN_BASIC_JSON_TPL_DECLARATION +struct is_basic_json : std::true_type {}; + +// used by exceptions create() member functions +// true_type for pointer to possibly cv-qualified basic_json or std::nullptr_t +// false_type otherwise +template +struct is_basic_json_context : + std::integral_constant < bool, + is_basic_json::type>::type>::value + || std::is_same::value > +{}; + +////////////////////// +// json_ref helpers // +////////////////////// + +template +class json_ref; + +template +struct is_json_ref : std::false_type {}; + +template +struct is_json_ref> : std::true_type {}; + +////////////////////////// +// aliases for detected // +////////////////////////// + +template +using mapped_type_t = typename T::mapped_type; + +template +using key_type_t = typename T::key_type; + +template +using value_type_t = typename T::value_type; + +template +using difference_type_t = typename T::difference_type; + +template +using pointer_t = typename T::pointer; + +template +using reference_t = typename T::reference; + +template +using iterator_category_t = typename T::iterator_category; + +template +using to_json_function = decltype(T::to_json(std::declval()...)); + +template +using from_json_function = decltype(T::from_json(std::declval()...)); + +template +using get_template_function = decltype(std::declval().template get()); + +// trait checking if JSONSerializer::from_json(json const&, udt&) exists +template +struct has_from_json : std::false_type {}; + +// trait checking if j.get is valid +// use this trait instead of std::is_constructible or std::is_convertible, +// both rely on, or make use of implicit conversions, and thus fail when T +// has several constructors/operator= (see https://github.com/nlohmann/json/issues/958) +template +struct is_getable +{ + static constexpr bool value = is_detected::value; +}; + +template +struct has_from_json < BasicJsonType, T, enable_if_t < !is_basic_json::value >> +{ + using serializer = typename BasicJsonType::template json_serializer; + + static constexpr bool value = + is_detected_exact::value; +}; + +// This trait checks if JSONSerializer::from_json(json const&) exists +// this overload is used for non-default-constructible user-defined-types +template +struct has_non_default_from_json : std::false_type {}; + +template +struct has_non_default_from_json < BasicJsonType, T, enable_if_t < !is_basic_json::value >> +{ + using serializer = typename BasicJsonType::template json_serializer; + + static constexpr bool value = + is_detected_exact::value; +}; + +// This trait checks if BasicJsonType::json_serializer::to_json exists +// Do not evaluate the trait when T is a basic_json type, to avoid template instantiation infinite recursion. +template +struct has_to_json : std::false_type {}; + +template +struct has_to_json < BasicJsonType, T, enable_if_t < !is_basic_json::value >> +{ + using serializer = typename BasicJsonType::template json_serializer; + + static constexpr bool value = + is_detected_exact::value; +}; + +template +using detect_key_compare = typename T::key_compare; + +template +struct has_key_compare : std::integral_constant::value> {}; + +// obtains the actual object key comparator +template +struct actual_object_comparator +{ + using object_t = typename BasicJsonType::object_t; + using object_comparator_t = typename BasicJsonType::default_object_comparator_t; + using type = typename std::conditional < has_key_compare::value, + typename object_t::key_compare, object_comparator_t>::type; +}; + +template +using actual_object_comparator_t = typename actual_object_comparator::type; + +/////////////////// +// is_ functions // +/////////////////// + +// https://en.cppreference.com/w/cpp/types/conjunction +template struct conjunction : std::true_type { }; +template struct conjunction : B { }; +template +struct conjunction +: std::conditional(B::value), conjunction, B>::type {}; + +// https://en.cppreference.com/w/cpp/types/negation +template struct negation : std::integral_constant < bool, !B::value > { }; + +// Reimplementation of is_constructible and is_default_constructible, due to them being broken for +// std::pair and std::tuple until LWG 2367 fix (see https://cplusplus.github.io/LWG/lwg-defects.html#2367). +// This causes compile errors in e.g. clang 3.5 or gcc 4.9. +template +struct is_default_constructible : std::is_default_constructible {}; + +template +struct is_default_constructible> + : conjunction, is_default_constructible> {}; + +template +struct is_default_constructible> + : conjunction, is_default_constructible> {}; + +template +struct is_default_constructible> + : conjunction...> {}; + +template +struct is_default_constructible> + : conjunction...> {}; + + +template +struct is_constructible : std::is_constructible {}; + +template +struct is_constructible> : is_default_constructible> {}; + +template +struct is_constructible> : is_default_constructible> {}; + +template +struct is_constructible> : is_default_constructible> {}; + +template +struct is_constructible> : is_default_constructible> {}; + + +template +struct is_iterator_traits : std::false_type {}; + +template +struct is_iterator_traits> +{ + private: + using traits = iterator_traits; + + public: + static constexpr auto value = + is_detected::value && + is_detected::value && + is_detected::value && + is_detected::value && + is_detected::value; +}; + +template +struct is_range +{ + private: + using t_ref = typename std::add_lvalue_reference::type; + + using iterator = detected_t; + using sentinel = detected_t; + + // to be 100% correct, it should use https://en.cppreference.com/w/cpp/iterator/input_or_output_iterator + // and https://en.cppreference.com/w/cpp/iterator/sentinel_for + // but reimplementing these would be too much work, as a lot of other concepts are used underneath + static constexpr auto is_iterator_begin = + is_iterator_traits>::value; + + public: + static constexpr bool value = !std::is_same::value && !std::is_same::value && is_iterator_begin; +}; + +template +using iterator_t = enable_if_t::value, result_of_begin())>>; + +template +using range_value_t = value_type_t>>; + +// The following implementation of is_complete_type is taken from +// https://blogs.msdn.microsoft.com/vcblog/2015/12/02/partial-support-for-expression-sfinae-in-vs-2015-update-1/ +// and is written by Xiang Fan who agreed to using it in this library. + +template +struct is_complete_type : std::false_type {}; + +template +struct is_complete_type : std::true_type {}; + +template +struct is_compatible_object_type_impl : std::false_type {}; + +template +struct is_compatible_object_type_impl < + BasicJsonType, CompatibleObjectType, + enable_if_t < is_detected::value&& + is_detected::value >> +{ + using object_t = typename BasicJsonType::object_t; + + // macOS's is_constructible does not play well with nonesuch... + static constexpr bool value = + is_constructible::value && + is_constructible::value; +}; + +template +struct is_compatible_object_type + : is_compatible_object_type_impl {}; + +template +struct is_constructible_object_type_impl : std::false_type {}; + +template +struct is_constructible_object_type_impl < + BasicJsonType, ConstructibleObjectType, + enable_if_t < is_detected::value&& + is_detected::value >> +{ + using object_t = typename BasicJsonType::object_t; + + static constexpr bool value = + (is_default_constructible::value && + (std::is_move_assignable::value || + std::is_copy_assignable::value) && + (is_constructible::value && + std::is_same < + typename object_t::mapped_type, + typename ConstructibleObjectType::mapped_type >::value)) || + (has_from_json::value || + has_non_default_from_json < + BasicJsonType, + typename ConstructibleObjectType::mapped_type >::value); +}; + +template +struct is_constructible_object_type + : is_constructible_object_type_impl {}; + +template +struct is_compatible_string_type +{ + static constexpr auto value = + is_constructible::value; +}; + +template +struct is_constructible_string_type +{ + // launder type through decltype() to fix compilation failure on ICPC +#ifdef __INTEL_COMPILER + using laundered_type = decltype(std::declval()); +#else + using laundered_type = ConstructibleStringType; +#endif + + static constexpr auto value = + conjunction < + is_constructible, + is_detected_exact>::value; +}; + +template +struct is_compatible_array_type_impl : std::false_type {}; + +template +struct is_compatible_array_type_impl < + BasicJsonType, CompatibleArrayType, + enable_if_t < + is_detected::value&& + is_iterator_traits>>::value&& +// special case for types like std::filesystem::path whose iterator's value_type are themselves +// c.f. https://github.com/nlohmann/json/pull/3073 + !std::is_same>::value >> +{ + static constexpr bool value = + is_constructible>::value; +}; + +template +struct is_compatible_array_type + : is_compatible_array_type_impl {}; + +template +struct is_constructible_array_type_impl : std::false_type {}; + +template +struct is_constructible_array_type_impl < + BasicJsonType, ConstructibleArrayType, + enable_if_t::value >> + : std::true_type {}; + +template +struct is_constructible_array_type_impl < + BasicJsonType, ConstructibleArrayType, + enable_if_t < !std::is_same::value&& + !is_compatible_string_type::value&& + is_default_constructible::value&& +(std::is_move_assignable::value || + std::is_copy_assignable::value)&& +is_detected::value&& +is_iterator_traits>>::value&& +is_detected::value&& +// special case for types like std::filesystem::path whose iterator's value_type are themselves +// c.f. https://github.com/nlohmann/json/pull/3073 +!std::is_same>::value&& + is_complete_type < + detected_t>::value >> +{ + using value_type = range_value_t; + + static constexpr bool value = + std::is_same::value || + has_from_json::value || + has_non_default_from_json < + BasicJsonType, + value_type >::value; +}; + +template +struct is_constructible_array_type + : is_constructible_array_type_impl {}; + +template +struct is_compatible_integer_type_impl : std::false_type {}; + +template +struct is_compatible_integer_type_impl < + RealIntegerType, CompatibleNumberIntegerType, + enable_if_t < std::is_integral::value&& + std::is_integral::value&& + !std::is_same::value >> +{ + // is there an assert somewhere on overflows? + using RealLimits = std::numeric_limits; + using CompatibleLimits = std::numeric_limits; + + static constexpr auto value = + is_constructible::value && + CompatibleLimits::is_integer && + RealLimits::is_signed == CompatibleLimits::is_signed; +}; + +template +struct is_compatible_integer_type + : is_compatible_integer_type_impl {}; + +template +struct is_compatible_type_impl: std::false_type {}; + +template +struct is_compatible_type_impl < + BasicJsonType, CompatibleType, + enable_if_t::value >> +{ + static constexpr bool value = + has_to_json::value; +}; + +template +struct is_compatible_type + : is_compatible_type_impl {}; + +template +struct is_constructible_tuple : std::false_type {}; + +template +struct is_constructible_tuple> : conjunction...> {}; + +template +struct is_json_iterator_of : std::false_type {}; + +template +struct is_json_iterator_of : std::true_type {}; + +template +struct is_json_iterator_of : std::true_type +{}; + +// checks if a given type T is a template specialization of Primary +template