diff --git a/hw/opae/sources_16c.txt b/hw/opae/sources_16c.txt index 987404f0..f82b85dc 100644 --- a/hw/opae/sources_16c.txt +++ b/hw/opae/sources_16c.txt @@ -1,5 +1,6 @@ +define+NUM_CORES=4 +define+NUM_CLUSTERS=4 ++define+L3_ENABLE=1 +define+SYNTHESIS +define+QUARTUS diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 83583707..fc0fdfcc 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -264,7 +264,7 @@ // Size of cache in bytes `ifndef ICACHE_SIZE -`define ICACHE_SIZE 8192 +`define ICACHE_SIZE 16384 `endif // Core Request Queue Size @@ -296,7 +296,7 @@ // Size of cache in bytes `ifndef DCACHE_SIZE -`define DCACHE_SIZE 8192 +`define DCACHE_SIZE 16384 `endif // Number of banks @@ -360,7 +360,7 @@ // Size of cache in bytes `ifndef L2CACHE_SIZE -`define L2CACHE_SIZE 131072 +`define L2CACHE_SIZE 262144 `endif // Number of banks @@ -380,7 +380,7 @@ // Miss Handling Register Size `ifndef L2MSHR_SIZE -`define L2MSHR_SIZE 8 +`define L2MSHR_SIZE 16 `endif // DRAM Request Queue Size @@ -397,7 +397,7 @@ // Size of cache in bytes `ifndef L3CACHE_SIZE -`define L3CACHE_SIZE 262144 +`define L3CACHE_SIZE 1048576 `endif // Number of banks @@ -417,7 +417,7 @@ // Miss Handling Register Size `ifndef L3MSHR_SIZE -`define L3MSHR_SIZE 8 +`define L3MSHR_SIZE 16 `endif // DRAM Request Queue Size diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index bef90dd9..cfd78acc 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -30,9 +30,6 @@ module VX_bank #( // Enable cache writeable parameter WRITE_ENABLE = 1, - // Enable write-through - parameter WRITE_THROUGH = 1, - // core request tag size parameter CORE_TAG_WIDTH = 1, @@ -195,12 +192,9 @@ module VX_bank #( wire valid_st0, valid_st1; wire is_fill_st0, is_fill_st1; wire is_mshr_st0, is_mshr_st1; - wire [`CACHE_LINE_WIDTH-1:0] readdata_st0, readdata_st1; - wire [`TAG_SELECT_BITS-1:0] readtag_st0, readtag_st1; + wire [`CACHE_LINE_WIDTH-1:0] readdata_st1; wire miss_st0, miss_st1; wire force_miss_st0, force_miss_st1; - wire dirty_st0; - wire [CACHE_LINE_SIZE-1:0] dirtyb_st0, dirtyb_st1; wire do_writeback_st0, do_writeback_st1; wire writeen_unqual_st0, writeen_unqual_st1; wire mshr_push_unqual_st0, mshr_push_unqual_st1; @@ -258,14 +252,13 @@ module VX_bank #( `endif VX_tag_access #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CORE_TAG_ID_BITS(CORE_TAG_ID_BITS), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .WRITE_ENABLE (WRITE_ENABLE), + .BANK_ID (BANK_ID), + .CACHE_ID (CACHE_ID), + .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), + .CACHE_SIZE (CACHE_SIZE), + .CACHE_LINE_SIZE (CACHE_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE), .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET) ) tag_access ( .clk (clk), @@ -280,15 +273,9 @@ module VX_bank #( // read/Fill .lookup_in (creq_pop || mshr_pop), - .raddr_in (addr_st0), + .addr_in (addr_st0), .do_fill_in (drsq_pop), - .miss_out (miss_st0), - .readtag_out (readtag_st0), - .dirty_out (dirty_st0), - - // write - .waddr_in (addr_st1), - .writeen_in (valid_st1 && writeen_st1) + .miss_out (miss_st0) ); // redundant fills @@ -296,33 +283,31 @@ module VX_bank #( // we have a miss in mshr or going to it for the current address wire mshr_pending_st0 = mshr_pending_unqual_st0 - || (valid_st1 && (miss_st1 || force_miss_st1) && (addr_st0 == addr_st1)); + || (valid_st1 && (miss_st1 || force_miss_st1) && (addr_st0 == addr_st1)); // force miss to ensure commit order when a new request has pending previous requests to same block assign force_miss_st0 = !is_mshr_st0 && !is_fill_st0 && mshr_pending_st0; assign writeen_unqual_st0 = (!is_fill_st0 && !miss_st0 && mem_rw_st0) - || (is_fill_st0 && !is_redundant_fill); + || (is_fill_st0 && !is_redundant_fill); - wire send_fill_req_st0 = !is_fill_st0 && miss_st0 - && !(WRITE_THROUGH && mem_rw_st0); + wire send_fill_req_st0 = !is_fill_st0 && miss_st0 && !mem_rw_st0; - assign do_writeback_st0 = (WRITE_THROUGH && !is_fill_st0 && mem_rw_st0) - || (!WRITE_THROUGH && is_fill_st0 && dirty_st0 && !is_redundant_fill); + assign do_writeback_st0 = !is_fill_st0 && mem_rw_st0; assign dreq_push_unqual_st0 = send_fill_req_st0 || do_writeback_st0; - assign mshr_push_unqual_st0 = !is_fill_st0 && !(WRITE_THROUGH && mem_rw_st0); + assign mshr_push_unqual_st0 = !is_fill_st0 && !mem_rw_st0; VX_pipe_register #( - .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH + `WORD_WIDTH + `TAG_SELECT_BITS + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), + .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + `WORD_WIDTH + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), .RESETW (1) ) pipe_reg1 ( .clk (clk), .reset (reset), .enable (!pipeline_stall), - .data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, mshr_push_unqual_st0, dreq_push_unqual_st0, do_writeback_st0, miss_st0, force_miss_st0, addr_st0, wsel_st0, dirtyb_st0, readdata_st0, writeword_st0, readtag_st0, filldata_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}), - .data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, mshr_push_unqual_st1, dreq_push_unqual_st1, do_writeback_st1, miss_st1, force_miss_st1, addr_st1, wsel_st1, dirtyb_st1, readdata_st1, writeword_st1, readtag_st1, filldata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}) + .data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, mshr_push_unqual_st0, dreq_push_unqual_st0, do_writeback_st0, miss_st0, force_miss_st0, addr_st0, wsel_st0, writeword_st0, filldata_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}), + .data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, mshr_push_unqual_st1, dreq_push_unqual_st1, do_writeback_st1, miss_st1, force_miss_st1, addr_st1, wsel_st1, writeword_st1, filldata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}) ); assign core_req_hit_st1 = !is_fill_st1 && !miss_st1 && !force_miss_st1; @@ -336,36 +321,32 @@ module VX_bank #( wire crsq_push_st1 = core_req_hit_st1 && !mem_rw_st1; VX_data_access #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CORE_TAG_ID_BITS(CORE_TAG_ID_BITS), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .WRITE_ENABLE (WRITE_ENABLE), - .WRITE_THROUGH (WRITE_THROUGH) + .BANK_ID (BANK_ID), + .CACHE_ID (CACHE_ID), + .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), + .CACHE_SIZE (CACHE_SIZE), + .CACHE_LINE_SIZE (CACHE_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE), + .WRITE_ENABLE (WRITE_ENABLE) ) data_access ( .clk (clk), .reset (reset), `ifdef DBG_CACHE_REQ_INFO - .rdebug_pc (debug_pc_st0), - .rdebug_wid (debug_wid_st0), - .wdebug_pc (debug_pc_st1), - .wdebug_wid (debug_wid_st1), + .debug_pc (debug_pc_st1), + .debug_wid (debug_wid_st1), `endif .stall (pipeline_stall), + .addr_in (addr_st1), + // reading - .readen_in (valid_st0 && !mem_rw_st0 && !is_fill_st0), - .raddr_in (addr_st0), - .readdata_out (readdata_st0), - .dirtyb_out (dirtyb_st0), + .readen_in (valid_st1 && !mem_rw_st1 && !is_fill_st1), + .readdata_out (readdata_st1), // writing .writeen_in (valid_st1 && writeen_st1), - .waddr_in (addr_st1), .wfill_in (is_fill_st1), .wwsel_in (wsel_st1), .wbyteen_in (byteen_st1), @@ -508,26 +489,19 @@ module VX_bank #( wire writeback = WRITE_ENABLE && do_writeback_st1; - wire [`LINE_ADDR_WIDTH-1:0] dreq_addr = (WRITE_THROUGH || !writeback) ? addr_st1 : - {readtag_st1, addr_st1[`LINE_SELECT_BITS-1:0]}; + wire [`LINE_ADDR_WIDTH-1:0] dreq_addr = addr_st1; wire [`CACHE_LINE_WIDTH-1:0] dreq_data; wire [CACHE_LINE_SIZE-1:0] dreq_byteen, dreq_byteen_unqual; - if (WRITE_THROUGH) begin - `UNUSED_VAR (dirtyb_st1) - if (`WORD_SELECT_BITS != 0) begin - for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin - assign dreq_byteen_unqual[i * WORD_SIZE +: WORD_SIZE] = (wsel_st1 == `WORD_SELECT_BITS'(i)) ? byteen_st1 : {WORD_SIZE{1'b0}}; - assign dreq_data[i * `WORD_WIDTH +: `WORD_WIDTH] = writeword_st1; - end - end else begin - assign dreq_byteen_unqual = byteen_st1; - assign dreq_data = writeword_st1; + if (`WORD_SELECT_BITS != 0) begin + for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin + assign dreq_byteen_unqual[i * WORD_SIZE +: WORD_SIZE] = (wsel_st1 == `WORD_SELECT_BITS'(i)) ? byteen_st1 : {WORD_SIZE{1'b0}}; + assign dreq_data[i * `WORD_WIDTH +: `WORD_WIDTH] = writeword_st1; end end else begin - assign dreq_byteen_unqual = dirtyb_st1; - assign dreq_data = readdata_st1; + assign dreq_byteen_unqual = byteen_st1; + assign dreq_data = writeword_st1; end assign dreq_byteen = writeback ? dreq_byteen_unqual : {CACHE_LINE_SIZE{1'b1}}; @@ -562,7 +536,6 @@ module VX_bank #( `SCOPE_ASSIGN (is_fill_st0, is_fill_st0); `SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0); `SCOPE_ASSIGN (miss_st0, miss_st0); - `SCOPE_ASSIGN (dirty_st0, dirty_st0); `SCOPE_ASSIGN (force_miss_st0, force_miss_st0); `SCOPE_ASSIGN (mshr_push, mshr_push); `SCOPE_ASSIGN (pipeline_stall, pipeline_stall); diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 70981983..79320430 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -29,9 +29,6 @@ module VX_cache #( // Enable cache writeable parameter WRITE_ENABLE = 1, - // Enable write-through - parameter WRITE_THROUGH = 1, - // core request tag size parameter CORE_TAG_WIDTH = $clog2(MSHR_SIZE), @@ -242,7 +239,6 @@ module VX_cache #( .CRSQ_SIZE (CRSQ_SIZE), .DREQ_SIZE (DREQ_SIZE), .WRITE_ENABLE (WRITE_ENABLE), - .WRITE_THROUGH (WRITE_THROUGH), .CORE_TAG_WIDTH (CORE_TAG_WIDTH), .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET) diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index 0ac55f7c..cb3ba418 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -23,122 +23,86 @@ module VX_data_access #( `ifdef DBG_CACHE_REQ_INFO `IGNORE_WARNINGS_BEGIN - input wire[31:0] rdebug_pc, - input wire[`NW_BITS-1:0] rdebug_wid, - input wire[31:0] wdebug_pc, - input wire[`NW_BITS-1:0] wdebug_wid, + input wire[31:0] debug_pc, + input wire[`NW_BITS-1:0] debug_wid, `IGNORE_WARNINGS_END `endif input wire stall, +`IGNORE_WARNINGS_BEGIN + input wire[`LINE_ADDR_WIDTH-1:0] addr_in, +`IGNORE_WARNINGS_END + // reading input wire readen_in, -`IGNORE_WARNINGS_BEGIN - input wire[`LINE_ADDR_WIDTH-1:0] raddr_in, -`IGNORE_WARNINGS_END output wire [`CACHE_LINE_WIDTH-1:0] readdata_out, - output wire [CACHE_LINE_SIZE-1:0] dirtyb_out, // writing input wire writeen_in, -`IGNORE_WARNINGS_BEGIN - input wire[`LINE_ADDR_WIDTH-1:0] waddr_in, -`IGNORE_WARNINGS_END input wire [`UP(`WORD_SELECT_BITS)-1:0] wwsel_in, input wire [WORD_SIZE-1:0] wbyteen_in, input wire wfill_in, input wire [`WORD_WIDTH-1:0] writeword_in, input wire [`CACHE_LINE_WIDTH-1:0] filldata_in ); + `UNUSED_VAR (reset) - wire [CACHE_LINE_SIZE-1:0] read_dirtyb; wire [`CACHE_LINE_WIDTH-1:0] read_data; - wire [CACHE_LINE_SIZE-1:0] byte_enable; wire [`CACHE_LINE_WIDTH-1:0] write_data; wire write_enable; - wire [`LINE_SELECT_BITS-1:0] raddr = raddr_in[`LINE_SELECT_BITS-1:0]; - wire [`LINE_SELECT_BITS-1:0] waddr = waddr_in[`LINE_SELECT_BITS-1:0]; + wire [`LINE_SELECT_BITS-1:0] line_addr = addr_in[`LINE_SELECT_BITS-1:0]; - `UNUSED_VAR (readen_in) - - VX_data_store #( - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .WRITE_ENABLE (WRITE_ENABLE), - .WRITE_THROUGH (WRITE_THROUGH) + VX_sp_ram #( + .DATAW(CACHE_LINE_SIZE * 8), + .SIZE(`LINES_PER_BANK), + .BYTEENW(CACHE_LINE_SIZE), + .RWCHECK(1) ) data_store ( - .clk (clk), - .reset (reset), - - .read_addr (raddr), - .read_data (read_data), - .read_dirtyb (read_dirtyb), - - .write_enable(write_enable), - .write_fill (wfill_in), - .write_addr (waddr), - .byte_enable (byte_enable), - .write_data (write_data) + .clk(clk), + .addr(line_addr), + .wren(write_enable), + .byteen(byte_enable), + .rden(1'b1), + .din(write_data), + .dout(read_data) ); - wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wbyteen_qual; - wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] writedata_qual; + wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wbyteen_qual; + wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] writedata_qual; if (`WORD_SELECT_BITS != 0) begin for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin assign wbyteen_qual[i] = (wwsel_in == `WORD_SELECT_BITS'(i)) ? wbyteen_in : {WORD_SIZE{1'b0}}; - assign writedata_qual[i] = writeword_in; + assign writedata_qual[i] = writeword_in; end end else begin `UNUSED_VAR (wwsel_in) assign wbyteen_qual = wbyteen_in; assign writedata_qual = writeword_in; - end - - assign write_enable = writeen_in && !stall; - assign byte_enable = wfill_in ? {CACHE_LINE_SIZE{1'b1}} : wbyteen_qual; - assign write_data = wfill_in ? filldata_in : writedata_qual; - - wire rw_hazard = (raddr == waddr) && writeen_in; - - if (`WORD_SELECT_BITS != 0) begin - for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin - wire [`WORD_WIDTH-1:0] readdata_sel = read_data[i * `WORD_WIDTH +: `WORD_WIDTH]; - wire [`WORD_WIDTH-1:0] writeword_qual; - for (genvar j = 0; j < WORD_SIZE; j++) begin - assign writeword_qual[j * 8 +: 8] = wbyteen_in[j] ? writeword_in[j * 8 +: 8] : readdata_sel[j * 8 +: 8]; - end - wire wenable = (wwsel_in == `WORD_SELECT_BITS'(i)); - assign dirtyb_out[i * WORD_SIZE +: WORD_SIZE] = read_dirtyb[i * WORD_SIZE +: WORD_SIZE] | ({WORD_SIZE{rw_hazard && wenable}} & wbyteen_in); - assign readdata_out[i * `WORD_WIDTH +: `WORD_WIDTH] = (rw_hazard && wfill_in) ? filldata_in[i * `WORD_WIDTH +: `WORD_WIDTH] : - (rw_hazard && wenable) ? writeword_qual : readdata_sel; - end - end else begin - wire [`WORD_WIDTH-1:0] writeword_qual; - for (genvar i = 0; i < WORD_SIZE; i++) begin - assign writeword_qual[i * 8 +: 8] = wbyteen_in[i] ? writeword_in[i * 8 +: 8] : read_data[i * 8 +: 8]; - end - assign dirtyb_out = read_dirtyb | ({WORD_SIZE{rw_hazard}} & wbyteen_in); - assign readdata_out = rw_hazard ? (wfill_in ? filldata_in : writeword_qual) : read_data; end + + assign write_enable = writeen_in && !stall; + assign byte_enable = wfill_in ? {CACHE_LINE_SIZE{1'b1}} : wbyteen_qual; + assign write_data = wfill_in ? filldata_in : writedata_qual; + assign readdata_out = read_data; + + `UNUSED_VAR (readen_in) `ifdef DBG_PRINT_CACHE_DATA always @(posedge clk) begin if (!stall) begin if (writeen_in) begin if (wfill_in) begin - $display("%t: cache%0d:%0d data-fill: addr=%0h, dirty=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(waddr_in, BANK_ID), dirtyb_out, waddr, write_data); + $display("%t: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), line_addr, write_data); end else begin - $display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, dirty=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(waddr_in, BANK_ID), rdebug_wid, rdebug_pc, byte_enable, dirtyb_out, waddr, wwsel_in, writeword_in); + $display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wwsel_in, writeword_in); end end if (readen_in) begin - $display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(raddr_in, BANK_ID), rdebug_wid, rdebug_pc, dirtyb_out, raddr, read_data); + $display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), debug_wid, debug_pc, line_addr, read_data); end end end diff --git a/hw/rtl/cache/VX_data_store.v b/hw/rtl/cache/VX_data_store.v deleted file mode 100644 index fee94756..00000000 --- a/hw/rtl/cache/VX_data_store.v +++ /dev/null @@ -1,64 +0,0 @@ -`include "VX_cache_config.vh" - -module VX_data_store #( - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - - // Enable cache writeable - parameter WRITE_ENABLE = 1, - - // Enable write-through - parameter WRITE_THROUGH = 1 -) ( - input wire clk, - input wire reset, - - input wire write_enable, - input wire write_fill, - input wire[CACHE_LINE_SIZE-1:0] byte_enable, - input wire[`LINE_SELECT_BITS-1:0] write_addr, - input wire[`CACHE_LINE_WIDTH-1:0] write_data, - - input wire[`LINE_SELECT_BITS-1:0] read_addr, - output wire[`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] read_dirtyb, - output wire[`CACHE_LINE_WIDTH-1:0] read_data -); - `UNUSED_VAR (reset) - - if (WRITE_ENABLE && !WRITE_THROUGH) begin - reg [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] dirtyb[`LINES_PER_BANK-1:0]; - always @(posedge clk) begin - if (write_enable) begin - dirtyb[write_addr] <= write_fill ? 0 : (dirtyb[write_addr] | byte_enable); - end - end - assign read_dirtyb = dirtyb [read_addr]; - end else begin - `UNUSED_VAR (write_fill) - `UNUSED_VAR (byte_enable) - assign read_dirtyb = 0; - end - - VX_dp_ram #( - .DATAW(CACHE_LINE_SIZE * 8), - .SIZE(`LINES_PER_BANK), - .BYTEENW(CACHE_LINE_SIZE), - .RWCHECK(1) - ) data ( - .clk(clk), - .waddr(write_addr), - .raddr(read_addr), - .wren(write_enable), - .byteen(byte_enable), - .rden(1'b1), - .din(write_data), - .dout(read_data) - ); - -endmodule diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index 9c25ae09..b32fbf01 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -11,8 +11,6 @@ module VX_tag_access #( parameter NUM_BANKS = 1, // Size of a word in bytes parameter WORD_SIZE = 1, - // Enable cache writeable - parameter WRITE_ENABLE = 0, // size of tag id in core request tag parameter CORE_TAG_ID_BITS = 0, // bank offset from beginning of index range @@ -32,82 +30,55 @@ module VX_tag_access #( // read/fill input wire lookup_in, - input wire[`LINE_ADDR_WIDTH-1:0] raddr_in, + input wire[`LINE_ADDR_WIDTH-1:0] addr_in, input wire do_fill_in, - output wire miss_out, - output wire[`TAG_SELECT_BITS-1:0] readtag_out, - output wire dirty_out, - - // write -`IGNORE_WARNINGS_BEGIN - input wire[`LINE_ADDR_WIDTH-1:0] waddr_in, -`IGNORE_WARNINGS_END - input wire writeen_in + output wire miss_out ); + `UNUSED_VAR (reset) wire read_valid; - wire read_dirty; wire [`TAG_SELECT_BITS-1:0] read_tag; - wire do_fill; - wire do_write; - wire [`TAG_SELECT_BITS-1:0] raddr_tag = `LINE_TAG_ADDR(raddr_in); - wire [`LINE_SELECT_BITS-1:0] raddr = raddr_in [`LINE_SELECT_BITS-1:0]; - wire [`LINE_SELECT_BITS-1:0] waddr = waddr_in [`LINE_SELECT_BITS-1:0]; + wire [`TAG_SELECT_BITS-1:0] line_tag = `LINE_TAG_ADDR(addr_in); + wire [`LINE_SELECT_BITS-1:0] line_addr = addr_in [`LINE_SELECT_BITS-1:0]; - VX_tag_store #( - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET) + VX_sp_ram #( + .DATAW(`TAG_SELECT_BITS + 1), + .SIZE(`LINES_PER_BANK), + .INITZERO(1), + .RWCHECK(1) ) tag_store ( - .clk (clk), - .reset (reset), - - .raddr (raddr), - .read_valid (read_valid), - .read_dirty (read_dirty), - .read_tag (read_tag), - .do_fill (do_fill), - .fill_tag (raddr_tag), - - .waddr (waddr), - .do_write (do_write) + .clk(clk), + .addr(line_addr), + .wren(do_fill), + .byteen(1'b1), + .rden(1'b1), + .din({1'b1, line_tag}), + .dout({read_valid, read_tag}) ); - // read/fill stage - - wire tags_match = read_valid && (raddr_tag == read_tag); + wire tags_match = read_valid && (line_tag == read_tag); assign do_fill = do_fill_in && !stall; - assign readtag_out = read_tag; - assign miss_out = !tags_match; - assign dirty_out = read_dirty || ((raddr == waddr) && writeen_in); - - // write stage - - assign do_write = WRITE_ENABLE && writeen_in && !stall; - wire do_lookup = lookup_in && !stall; `UNUSED_VAR (do_lookup) `ifdef DBG_PRINT_CACHE_TAG always @(posedge clk) begin if (do_fill) begin - $display("%t: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(raddr_in, BANK_ID), raddr, raddr_tag, read_tag); + $display("%t: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), line_addr, line_tag, read_tag); if (tags_match) begin - $display("%t: warning: redundant fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(raddr_in, BANK_ID)); + $display("%t: warning: redundant fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID)); end end else if (do_lookup) begin if (tags_match) begin - $display("%t: cache%0d:%0d tag-hit: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(raddr_in, BANK_ID), debug_wid, debug_pc, read_dirty, raddr, raddr_tag); + $display("%t: cache%0d:%0d tag-hit: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), debug_wid, debug_pc, line_addr, line_tag); end else begin - $display("%t: cache%0d:%0d tag-miss: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(raddr_in, BANK_ID), debug_wid, debug_pc, read_dirty, raddr, raddr_tag, read_tag); + $display("%t: cache%0d:%0d tag-miss: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), debug_wid, debug_pc, line_addr, line_tag, read_tag); end end end diff --git a/hw/rtl/cache/VX_tag_store.v b/hw/rtl/cache/VX_tag_store.v deleted file mode 100644 index 8d4bcc39..00000000 --- a/hw/rtl/cache/VX_tag_store.v +++ /dev/null @@ -1,65 +0,0 @@ -`include "VX_cache_config.vh" - -module VX_tag_store #( - // Size of cache in bytes - parameter CACHE_SIZE = 1, - // Size of line inside a bank in bytes - parameter CACHE_LINE_SIZE = 1, - // Number of banks - parameter NUM_BANKS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1, - // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0 -) ( - input wire clk, - input wire reset, - - input wire[`LINE_SELECT_BITS-1:0] raddr, - input wire do_fill, - input wire[`TAG_SELECT_BITS-1:0] fill_tag, - - input wire[`LINE_SELECT_BITS-1:0] waddr, - input wire do_write, - - output wire[`TAG_SELECT_BITS-1:0] read_tag, - output wire read_valid, - output wire read_dirty -); - reg [`LINES_PER_BANK-1:0] dirty; - reg [`LINES_PER_BANK-1:0] valid; - - always @(posedge clk) begin - if (reset) begin - for (integer i = 0; i < `LINES_PER_BANK; i++) begin - valid[i] <= 0; - dirty[i] <= 0; - end - end else begin - if (do_fill) begin - valid[raddr] <= 1; - dirty[raddr] <= 0; - end else if (do_write) begin - dirty[waddr] <= 1; - end - end - end - - VX_sp_ram #( - .DATAW(`TAG_SELECT_BITS), - .SIZE(`LINES_PER_BANK), - .RWCHECK(1) - ) tags ( - .clk(clk), - .addr(raddr), - .wren(do_fill), - .byteen(1'b1), - .rden(1'b1), - .din(fill_tag), - .dout(read_tag) - ); - - assign read_valid = valid[raddr]; - assign read_dirty = dirty[raddr]; - -endmodule diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index ef7f018e..ed151ba0 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -9,7 +9,8 @@ module VX_dp_ram #( parameter RWCHECK = 1, parameter ADDRW = $clog2(SIZE), parameter SIZEW = $clog2(SIZE+1), - parameter FASTRAM = 0 + parameter FASTRAM = 0, + parameter INITZERO = 0 ) ( input wire clk, input wire [ADDRW-1:0] waddr, @@ -30,6 +31,10 @@ module VX_dp_ram #( if (BYTEENW > 1) begin `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -43,6 +48,10 @@ module VX_dp_ram #( end else begin `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[waddr] <= din; @@ -57,6 +66,10 @@ module VX_dp_ram #( if (BYTEENW > 1) begin `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -69,6 +82,10 @@ module VX_dp_ram #( end else begin `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[waddr] <= din; @@ -83,6 +100,10 @@ module VX_dp_ram #( if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -96,6 +117,10 @@ module VX_dp_ram #( end else begin reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[waddr] <= din; @@ -111,6 +136,10 @@ module VX_dp_ram #( if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -123,6 +152,10 @@ module VX_dp_ram #( end else begin reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[waddr] <= din; @@ -133,6 +166,10 @@ module VX_dp_ram #( if (BYTEENW > 1) begin `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -143,7 +180,11 @@ module VX_dp_ram #( end assign dout = mem[raddr]; end else begin - `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; + `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; + + if (INITZERO) begin + initial mem = '{default: 0}; + end always @(posedge clk) begin if (wren && byteen) diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v index 14d0c5da..7cbf7048 100644 --- a/hw/rtl/libs/VX_sp_ram.v +++ b/hw/rtl/libs/VX_sp_ram.v @@ -9,7 +9,8 @@ module VX_sp_ram #( parameter RWCHECK = 1, parameter ADDRW = $clog2(SIZE), parameter SIZEW = $clog2(SIZE+1), - parameter FASTRAM = 0 + parameter FASTRAM = 0, + parameter INITZERO = 0 ) ( input wire clk, input wire [ADDRW-1:0] addr, @@ -29,6 +30,10 @@ module VX_sp_ram #( if (BYTEENW > 1) begin `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -42,6 +47,10 @@ module VX_sp_ram #( end else begin `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[addr] <= din; @@ -55,6 +64,10 @@ module VX_sp_ram #( if (BYTEENW > 1) begin `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -67,6 +80,10 @@ module VX_sp_ram #( end else begin `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[addr] <= din; @@ -81,6 +98,10 @@ module VX_sp_ram #( if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -94,6 +115,10 @@ module VX_sp_ram #( end else begin reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[addr] <= din; @@ -108,6 +133,10 @@ module VX_sp_ram #( if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -120,6 +149,10 @@ module VX_sp_ram #( end else begin reg [DATAW-1:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren && byteen) mem[addr] <= din; @@ -130,6 +163,10 @@ module VX_sp_ram #( if (BYTEENW > 1) begin `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0]; + if (INITZERO) begin + initial mem = '{default: 0}; + end + always @(posedge clk) begin if (wren) begin for (integer i = 0; i < BYTEENW; i++) begin @@ -140,7 +177,11 @@ module VX_sp_ram #( end assign dout = mem[addr]; end else begin - `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; + `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; + + if (INITZERO) begin + initial mem = '{default: 0}; + end always @(posedge clk) begin if (wren && byteen) diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index 86659ba4..2bf19ce1 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -210,8 +210,7 @@ "is_fill_st0": 1, "is_mshr_st0": 1, "miss_st0": 1, - "force_miss_st0": 1, - "dirty_st0": 1, + "force_miss_st0": 1, "mshr_push": 1, "?pipeline_stall": 1 } diff --git a/hw/syn/quartus/top16/Makefile b/hw/syn/quartus/top16/Makefile index 3583a832..1f4fb40b 100644 --- a/hw/syn/quartus/top16/Makefile +++ b/hw/syn/quartus/top16/Makefile @@ -55,7 +55,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=4" -set "L3_ENABLE=1" syn.chg: $(STAMP) syn.chg