remove tab spaces
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@@ -3,48 +3,51 @@
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module byte_enabled_simple_dual_port_ram
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(
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input we, clk,
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input wire reset,
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input wire[4:0] waddr, raddr1, raddr2,
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input wire[`NUM_THREADS-1:0] be,
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input wire[`NUM_THREADS-1:0][31:0] wdata,
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output reg[`NUM_THREADS-1:0][31:0] q1, q2
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input clk;
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input wire reset;
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input wire we;
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input wire[4:0] waddr,
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input wire[4:0] raddr1,
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input wire[4:0] raddr2,
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input wire[`NUM_THREADS-1:0] be,
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input wire[`NUM_THREADS-1:0][31:0] wdata,
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output reg[`NUM_THREADS-1:0][31:0] q1
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output reg[`NUM_THREADS-1:0][31:0] q2
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);
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// integer regi;
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// integer threadi;
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// integer threadi;
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// Thread Byte Bit
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logic [`NUM_THREADS-1:0][3:0][7:0] GPR[31:0];
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// Thread Byte Bit
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logic [`NUM_THREADS-1:0][3:0][7:0] GPR[31:0];
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always @(posedge clk) begin
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if (reset) begin
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//--
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end else begin
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if (we) begin
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integer thread_ind;
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for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
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if (be[thread_ind]) begin
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GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
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GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
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GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
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GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
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end
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end
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end
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// $display("^^^^^^^^^^^^^^^^^^^^^^^");
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// for (regi = 0; regi <= 31; regi = regi + 1) begin
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// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
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// if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]);
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// end
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// end
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end
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end
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assign q1 = GPR[raddr1];
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assign q2 = GPR[raddr2];
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always @(posedge clk) begin
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if (reset) begin
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//--
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end else begin
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if (we) begin
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integer thread_ind;
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for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
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if (be[thread_ind]) begin
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GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
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GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
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GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
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GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
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end
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end
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end
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// $display("^^^^^^^^^^^^^^^^^^^^^^^");
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// for (regi = 0; regi <= 31; regi = regi + 1) begin
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// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
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// if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]);
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// end
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// end
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end
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end
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assign q1 = GPR[raddr1];
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assign q2 = GPR[raddr2];
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// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
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// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
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// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
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// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
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endmodule
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