remove tab spaces

hw/rtl/VX_csr_wrapper.v

@@ -6,7 +6,6 @@ module VX_csr_wrapper (
     VX_csr_wb_if  csr_wb_if
 );
 
-
     wire[`NUM_THREADS-1:0][31:0] thread_ids;
     wire[`NUM_THREADS-1:0][31:0] warp_ids;
 

hw/rtl/VX_lsu.v

@@ -74,7 +74,9 @@ module VX_lsu (
     wire found;
 `DEBUG_END
 
-	VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc(
+    VX_generic_priority_encoder #(
+        .N(`NUM_THREADS)
+    ) pick_first_pc (
         .valids(dcache_rsp_if.core_rsp_valid),
         .index (use_pc_index),
         .found (found)

hw/rtl/byte_enabled_simple_dual_port_ram.v

@@ -3,14 +3,17 @@
 
 module byte_enabled_simple_dual_port_ram
 (
-	input we, clk,
-	input wire reset,
-	input wire[4:0] waddr, raddr1, raddr2,
+    input clk;
+    input wire reset;
+	input wire we;
+    input wire[4:0] waddr,
+	input wire[4:0] raddr1,
+	input wire[4:0] raddr2,
     input wire[`NUM_THREADS-1:0] be,
     input wire[`NUM_THREADS-1:0][31:0] wdata,
-	output reg[`NUM_THREADS-1:0][31:0] q1, q2
+    output reg[`NUM_THREADS-1:0][31:0] q1
+	output reg[`NUM_THREADS-1:0][31:0] q2
 );
-
     // integer regi;
     // integer threadi;
 

hw/rtl/libs/VX_mult.v

@@ -9,7 +9,9 @@ module VX_mult #(
     parameter PIPELINE=0,
     parameter FORCE_LE="NO"
 ) (
-    input clock, aclr, clken,
+    input               clock;
+    input               aclr;
+    input               clken;
 
     input [WIDTHA-1:0]  dataa,
     input [WIDTHB-1:0]  datab,

hw/syn/yosys/diagram.ys

@@ -1,5 +1,5 @@
 # load design
-read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs  ../../rtl/Vortex.v
+read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache  ../../rtl/Vortex.v
 
 # dump diagram
 show