pipeline refactoring
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@@ -89,7 +89,7 @@ module VX_alu_unit #(
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VX_generic_register #(
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.N(1 + `NW_BITS + 1 + 32)
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) rsp_reg (
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) branch_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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