From ddafe96ca6bd098743ac4e59e6174fde4f86d3c6 Mon Sep 17 00:00:00 2001
From: Blaise Tine <btine3@flubber.crnch.gatech.edu>
Date: Sat, 7 Mar 2020 06:56:11 -0500
Subject: [PATCH] fixed write logic in generic_queue_ll

---
 rtl/Makefile                             |  3 ++
 rtl/VX_generic_queue_ll.v                | 16 ++++---
 rtl/unit_tests/generic_queue/testbench.v | 55 ++++++++----------------
 3 files changed, 32 insertions(+), 42 deletions(-)

diff --git a/rtl/Makefile b/rtl/Makefile
index c9b2a3fb..5fb2eb5b 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -46,5 +46,8 @@ debug: compdebug
 w: VERILATORnoWarnings
 	$(MAKECPP)
 
+run: w
+	(cd obj_dir && ./VVortex)
+
 clean:
 	rm obj_dir/*
diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v
index d92ff164..233355e5 100644
--- a/rtl/VX_generic_queue_ll.v
+++ b/rtl/VX_generic_queue_ll.v
@@ -75,6 +75,12 @@ module VX_generic_queue_ll
                 end
             end
         end    
+
+		always @(posedge clk) begin
+			if (writing) begin 
+				data[wr_ctr_r] <= in_data;
+			end
+		end
    
         always @(posedge clk) begin
             if (reset) begin
@@ -92,15 +98,13 @@ module VX_generic_queue_ll
                     end
                 end
 
-                if (!(!reading && bypass_r)) begin
-                    bypass_r <= writing && (empty_r || (1 == size_r && reading));
-                    curr_r <= in_data;
-                end
+                bypass_r <= writing && (empty_r || (1 == size_r) && reading);
+                curr_r <= in_data;
                 head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
             end
         end
-        
-        assign out_data = bypass_r ? curr_r : head_r;
+
+		assign out_data = bypass_r ? curr_r : head_r;
         assign empty = empty_r;
         assign full = full_r;
     end
diff --git a/rtl/unit_tests/generic_queue/testbench.v b/rtl/unit_tests/generic_queue/testbench.v
index a406abd5..b2dc8720 100644
--- a/rtl/unit_tests/generic_queue/testbench.v
+++ b/rtl/unit_tests/generic_queue/testbench.v
@@ -10,14 +10,9 @@ module testbench();
   reg[3:0] in_data;
   reg push;
   reg pop;
-  wire io_enq_ready;
   wire[3:0] out_data;
-  wire io_deq_valid;
-
-  wire full, empty;
-
-  assign io_enq_ready = !full;
-  assign io_deq_valid = !empty;
+  wire full;
+  wire empty;
 
   VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut (
                                 .clk(clk), 
@@ -34,40 +29,28 @@ module testbench();
   end
 
   initial begin
-    $monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h", $time, clk, reset, push, pop, in_data, empty, full, out_data);
-    #0 clk=0; reset=1; in_data=4'hd; push=1; pop=1;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0);
-    #0 reset=0; in_data=4'ha; pop=0;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
+    $monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h", 
+              $time, clk, reset, push, pop, in_data, empty, full, out_data);
+    #0 clk=0; reset=1; pop=0; push=0;   
+    #2 reset=0; in_data=4'ha; pop=0; push=1;
+    #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0);
     #0 in_data=4'hb;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
+    #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0);
     #0 in_data=4'hc;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
+    #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0);
     #0 in_data=4'hd;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1);
+    #2 `check(full, 1); `check(out_data, 4'ha); `check(empty, 0);
     #0 push=0; pop=1;
-    #1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0);
-    #0 in_data=4'ha; push=1; pop=0;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
-    #0 in_data=4'hb; pop=1;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
+    #2 `check(full, 0); `check(out_data, 4'hb); `check(empty, 0);
+    #2 `check(full, 0); `check(out_data, 4'hc); `check(empty, 0);
+    #2 `check(full, 0); `check(out_data, 4'hd); `check(empty, 0);
+    #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 1);
+    #0 in_data=4'he; push=1; pop=0;
+    #2 `check(full, 0); `check(out_data, 4'he); `check(empty, 0);
+    #0 in_data=4'hf; pop=1;
+    #2 `check(full, 0); `check(out_data, 4'hf); `check(empty, 0);
     #0 push=0;
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
-    #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 0);
+    #2 `check(full, 0); `check(out_data, 4'hc); `check(empty, 1);
     #1 $finish;
   end