From df7d91d690774cdf412e6726d4e62def88488bb4 Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Wed, 26 May 2021 15:29:39 -0700
Subject: [PATCH] more testing

---
 ci/regression.sh               | 11 +++++++++--
 driver/opae/vlsim/opae_sim.cpp | 15 ++++++++++++++-
 hw/simulate/simulator.cpp      | 15 ++++++++++++++-
 3 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/ci/regression.sh b/ci/regression.sh
index 2a411bba..0e0fb248 100755
--- a/ci/regression.sh
+++ b/ci/regression.sh
@@ -51,7 +51,14 @@ CONFIGS=-DMEM_BLOCK_SIZE=16 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
 CONFIGS="-DMEM_BLOCK_SIZE=16 -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28 -DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
 
 # test 27-bit DRAM address
-CONFIGS=-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
+CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
 
 # test 128-bit DRAM block
-CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1 -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
\ No newline at end of file
+CONFIGS="-DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=1 -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=128 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=28" ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
+
+# test verilator reset values
+CONFIGS="-DVERILATOR_RESET_VALUE=0" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm
+CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm
+
+# test vlsim memory stress
+CONFIGS="-DMEM_LATENCY=100 -DMEM_RQ_SIZE=4 -DMEM_STALLS_MODULO=4" ./ci/blackbox.sh --driver=vlsim --cores=4 --app=sgemm
diff --git a/driver/opae/vlsim/opae_sim.cpp b/driver/opae/vlsim/opae_sim.cpp
index 98a52ce6..9f8df01d 100644
--- a/driver/opae/vlsim/opae_sim.cpp
+++ b/driver/opae/vlsim/opae_sim.cpp
@@ -11,9 +11,22 @@
 #define RESET_DELAY 4
 
 #define ENABLE_MEM_STALLS
+
+#ifndef MEM_LATENCY
 #define MEM_LATENCY 24
+#endif
+
+#ifndef MEM_RQ_SIZE
 #define MEM_RQ_SIZE 16
+#endif
+
+#ifndef MEM_STALLS_MODULO
 #define MEM_STALLS_MODULO 16
+#endif
+
+#ifndef VERILATOR_RESET_VALUE
+#define VERILATOR_RESET_VALUE 2
+#endif
 
 uint64_t timestamp = 0;
 
@@ -23,7 +36,7 @@ double sc_time_stamp() {
 
 opae_sim::opae_sim() {  
   // force random values for unitialized signals  
-  Verilated::randReset(2);
+  Verilated::randReset(VERILATOR_RESET_VALUE);
   Verilated::randSeed(50);
 
   // Turn off assertion before reset
diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp
index 86156b94..25ed1992 100644
--- a/hw/simulate/simulator.cpp
+++ b/hw/simulate/simulator.cpp
@@ -6,9 +6,22 @@
 #define RESET_DELAY 4
 
 #define ENABLE_MEM_STALLS
+
+#ifndef MEM_LATENCY
 #define MEM_LATENCY 24
+#endif
+
+#ifndef MEM_RQ_SIZE
 #define MEM_RQ_SIZE 16
+#endif
+
+#ifndef MEM_STALLS_MODULO
 #define MEM_STALLS_MODULO 16
+#endif
+
+#ifndef VERILATOR_RESET_VALUE
+#define VERILATOR_RESET_VALUE 2
+#endif
 
 #define VL_WDATA_GETW(lwp, i, n, w) \
   VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w)
@@ -21,7 +34,7 @@ double sc_time_stamp() {
 
 Simulator::Simulator() {  
   // force random values for unitialized signals  
-  Verilated::randReset(2);
+  Verilated::randReset(VERILATOR_RESET_VALUE);
   Verilated::randSeed(50);
 
   // Turn off assertion before reset