Provisioned SM

rtl/VX_memory.v

@@ -3,6 +3,7 @@
 
 
 module VX_memory (
+		input wire        clk,
 		input wire[31:0]  in_alu_result[`NT_M1:0],
 		input wire[2:0]   in_mem_read, 
 		input wire[2:0]   in_mem_write,
@@ -42,6 +43,16 @@ module VX_memory (
 		// 	end
 		// end
 
+		wire[15:0] addr_0 = in_alu_result[0][31:16];
+
+		wire sm_valid[`NT_M1:0];
+
+		assign sm_valid = (addr_0 != 16'hFFFF) ? in_valid : in_valid;
+
+
+		 // wire z_valid[`NT_M1:0];
+		 // assign z_valid = 0;
+
 		assign out_delay = 1'b0;
 
 		assign out_cache_driver_in_address   = in_alu_result;
@@ -50,7 +61,23 @@ module VX_memory (
 		assign out_cache_driver_in_data      = in_rd2;
 		assign out_cache_driver_in_valid     = in_valid;
 
-		assign out_mem_result = in_cache_driver_out_data;
+
+
+		wire[31:0] sm_out_data[`NT_M1:0];
+
+
+		VX_shared_memory vx_shared_memory(
+			.clk         (clk),
+			.in_address  (in_alu_result),
+			.in_mem_read (in_mem_read),
+			.in_mem_write(in_mem_write),
+			.in_valid    (sm_valid),
+			.in_data     (in_rd2),
+			.out_data    (sm_out_data)
+			);
+
+
+		assign out_mem_result = sm_valid ? sm_out_data : in_cache_driver_out_data;
 		assign out_alu_result = in_alu_result;
 		assign out_rd         = in_rd;
 		assign out_wb         = in_wb;