From f7583757675ddf81fb15173fc9f04f627b8263a6 Mon Sep 17 00:00:00 2001 From: chad Date: Sun, 24 Jul 2011 10:07:09 +0000 Subject: [PATCH] Replaced instruction information arrays with a table. git-svn-id: http://www.cdkersey.com/harp/harptool@12 0246edb2-e076-4747-b392-db732a341fa2 --- src/enc.cpp | 4 +- src/include/instruction.h | 12 ++-- src/instruction.cpp | 130 +++++++++++++++++++------------------- src/obj.cpp | 7 +- 4 files changed, 79 insertions(+), 74 deletions(-) diff --git a/src/enc.cpp b/src/enc.cpp index 95da161f..4b44fc32 100644 --- a/src/enc.cpp +++ b/src/enc.cpp @@ -109,7 +109,7 @@ Instruction *ByteDecoder::decode(const vector &v, Size &n) { bool usedImm = false; - switch (Instruction::argClasses[op]) { + switch (Instruction::instTable[op].argClass) { case Instruction::AC_NONE: break; case Instruction::AC_2REG: @@ -276,7 +276,7 @@ Instruction *WordDecoder::decode(const std::vector &v, Size &idx) { inst.setOpcode(op); bool usedImm(false); - switch(Instruction::argClasses[op]) { + switch(Instruction::instTable[op].argClass) { case Instruction::AC_NONE: break; case Instruction::AC_1IMM: diff --git a/src/include/instruction.h b/src/include/instruction.h index b99f3861..08a1df5b 100644 --- a/src/include/instruction.h +++ b/src/include/instruction.h @@ -35,9 +35,13 @@ namespace Harp { AC_NONE, AC_2REG, AC_2IMM, AC_3REG, AC_3PREG, AC_3IMM, AC_3REGSRC, AC_1IMM, AC_1REG, AC_3IMMSRC, AC_PREG_REG, AC_2PREG }; - static const char *opStrings[]; - static const bool allSrcArgs[], privileged[], relAddress[], isControlFlow[]; - static const ArgClass argClasses[]; + + // We build a table of instruction information out of this. + static struct InstTableEntry { + const char *opString; + bool controlFlow, relAddress, allSrcArgs, privileged; + ArgClass argClass; + } instTable[]; Instruction() : predicated(false), nRsrc(0), nPsrc(0), immsrcPresent(false), @@ -75,7 +79,7 @@ namespace Harp { Ref *getRefLiteral() const { return refLiteral; } /* Getters used as table lookup. */ - bool hasRelImm() const { return relAddress[op]; } + bool hasRelImm() const { return instTable[op].relAddress; } private: bool predicated; diff --git a/src/instruction.cpp b/src/instruction.cpp index 20b8109a..a9f17a51 100644 --- a/src/instruction.cpp +++ b/src/instruction.cpp @@ -14,68 +14,68 @@ using namespace std; /* It is important that this stays consistent with the Harp::Instruction::Opcode enum. */ -const char *Instruction::opStrings[] = { - "nop", "di", "ei", "tlbadd", "tlbflush", "neg", "not", "and", "or", "xor", - "add", "sub", "mul", "div", "mod", "shl", "shr","andi", - "ori", "xori", "addi", "subi", "muli", "divi", "modi", "shli", "shri", - "jali", "jalr", "jmpi", "jmpr", "clone", "jalis", "jalrs", - "jmprt", "ld", "st", "ldi", "rtop", "andp", "orp", "xorp", "notp", - "isneg", "iszero", "halt", "trap", "jmpru", "skep", "reti", "tlbrm", - "itof", "ftoi", "fadd", "fsub", "fmul", "fdiv", "fneg", 0 -}; -const bool Instruction::isControlFlow[] = { - false, false, false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, false, - true, true, true, true, true, true, true, - true, false, false, false, false, false, false, false, false, - false, false, false, false, true, false, true, false, - false, false, false, false, false, false, false -}; - -const bool Instruction::relAddress[] = { - false, false, false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, false, - true, false, true, false, false, true, false, - false, false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false -}; - -const bool Instruction::allSrcArgs[] = { - false, false, false, true, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, false, - false, false, true, true, false, false, false, - true, false, true, false, false, false, false, false, false, - false, false, false, false, true, true, false, false, - false, false, false, false, false, false, false -}; - -const bool Instruction::privileged[] = { - false, true, true, true, true, false, false, false, false, false, - false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, false, - false, false, true, false, true, true, true, true, - false, false, false, false, false, false, false -}; - -const Instruction::ArgClass Instruction::argClasses[] = { - AC_NONE, AC_NONE, AC_NONE, AC_3REGSRC, AC_NONE, AC_2REG, AC_2REG, AC_3REG, - AC_3REG, AC_3REG, - AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3IMM, - AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, - AC_3IMM, - AC_2IMM, AC_2REG, AC_1IMM, AC_1REG, AC_1REG, AC_3IMM, AC_3REG, - AC_1REG, AC_3IMM, AC_3IMMSRC, AC_2IMM, AC_PREG_REG, AC_3PREG, AC_3PREG, - AC_3PREG, AC_2PREG, - AC_PREG_REG, AC_PREG_REG, AC_NONE, AC_NONE, AC_1REG, AC_1REG, AC_NONE, - AC_1REG, - AC_2REG, AC_2REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_2REG +Instruction::InstTableEntry Instruction::instTable[] = { + //str cflow relad allsrc priv argcl + {"nop", false, false, false, false, AC_NONE }, + {"di", false, false, false, true, AC_NONE }, + {"ei", false, false, false, true, AC_NONE }, + {"tlbadd", false, false, true, true, AC_3REGSRC }, + {"tlbflush", false, false, false, true, AC_NONE }, + {"neg", false, false, false, false, AC_2REG }, + {"not", false, false, false, false, AC_2REG }, + {"and", false, false, false, false, AC_3REG }, + {"or", false, false, false, false, AC_3REG }, + {"xor", false, false, false, false, AC_3REG }, + {"add", false, false, false, false, AC_3REG }, + {"sub", false, false, false, false, AC_3REG }, + {"mul", false, false, false, false, AC_3REG }, + {"div", false, false, false, false, AC_3REG }, + {"mod", false, false, false, false, AC_3REG }, + {"shl", false, false, false, false, AC_3REG }, + {"shr", false, false, false, false, AC_3REG }, + {"andi", false, false, false, false, AC_3IMM }, + {"ori", false, false, false, false, AC_3IMM }, + {"xori", false, false, false, false, AC_3IMM }, + {"addi", false, false, false, false, AC_3IMM }, + {"subi", false, false, false, false, AC_3IMM }, + {"muli", false, false, false, false, AC_3IMM }, + {"divi", false, false, false, false, AC_3IMM }, + {"modi", false, false, false, false, AC_3IMM }, + {"shli", false, false, false, false, AC_3IMM }, + {"shri", false, false, false, false, AC_3IMM }, + {"jali", true, true, false, false, AC_2IMM }, + {"jalr", true, false, false, false, AC_2REG }, + {"jmpi", true, true, true, false, AC_1IMM }, + {"jmpr", true, false, true, false, AC_1REG }, + {"clone", true, false, false, false, AC_1REG }, + {"jalis", true, true, false, false, AC_3IMM }, + {"jalrs", true, false, false, false, AC_3REG }, + {"jmprt", true, false, true, false, AC_1REG }, + {"ld", false, false, false, false, AC_3IMM }, + {"st", false, false, true, false, AC_3IMMSRC }, + {"ldi", false, false, false, false, AC_2IMM }, + {"rtop", false, false, false, false, AC_PREG_REG}, + {"andp", false, false, false, false, AC_3PREG }, + {"orp", false, false, false, false, AC_3PREG }, + {"xorp", false, false, false, false, AC_3PREG }, + {"notp", false, false, false, false, AC_3PREG }, + {"isneg", false, false, false, false, AC_PREG_REG}, + {"iszero", false, false, false, false, AC_PREG_REG}, + {"halt", false, false, false, true, AC_NONE }, + {"trap", true, false, false, false, AC_NONE }, + {"jmpru", false, false, false, true, AC_1REG }, + {"skep", false, false, false, true, AC_1REG }, + {"reti", true, false, false, true, AC_NONE }, + {"tlbrm", false, false, false, true, AC_1REG }, + {"itof", false, false, false, false, AC_2REG }, + {"ftoi", false, false, false, false, AC_2REG }, + {"fadd", false, false, false, false, AC_3REG }, + {"fsub", false, false, false, false, AC_3REG }, + {"fmul", false, false, false, false, AC_3REG }, + {"fdiv", false, false, false, false, AC_3REG }, + {"fneg", false, false, false, false, AC_2REG }, + {NULL,false,false,false,false,AC_NONE}/////////////// End of table. }; ostream &Harp::operator<<(ostream& os, Instruction &inst) { @@ -83,7 +83,7 @@ ostream &Harp::operator<<(ostream& os, Instruction &inst) { os << "@p" << inst.pred << " ? "; } - os << Instruction::opStrings[inst.op] << ' '; + os << Instruction::instTable[inst.op].opString << ' '; if (inst.rdestPresent) os << "%r" << inst.rdest << ' '; if (inst.pdestPresent) os << "@p" << inst.pdest << ' '; for (int i = 0; i < inst.nRsrc; i++) { @@ -104,12 +104,12 @@ ostream &Harp::operator<<(ostream& os, Instruction &inst) { void Instruction::executeOn(Core &c) { /* If I try to execute a privileged instruction in user mode, throw an exception 3. */ - if (privileged[op] && !c.supervisorMode) { + if (instTable[op].privileged && !c.supervisorMode) { c.interrupt(3); return; } - if (predicated && isControlFlow[op]) { + if (predicated && instTable[op].controlFlow) { bool p0 = c.pred[0][pred]; for (Size t = 1; t < c.activeThreads; t++) { if (c.pred[t][pred] != p0) throw DivergentBranchException(); @@ -244,7 +244,7 @@ void Instruction::executeOn(Core &c) { exit(1); } - if (isControlFlow[op]) break; + if (instTable[op].controlFlow) break; } c.activeThreads = nextActiveThreads; diff --git a/src/obj.cpp b/src/obj.cpp index 47775b64..14c77fbf 100644 --- a/src/obj.cpp +++ b/src/obj.cpp @@ -104,8 +104,9 @@ Obj *AsmReader::read(std::istream &input) { map opMap; // Build opMap - for (size_t i = 0; Instruction::opStrings[i]; i++) - opMap[std::string(Instruction::opStrings[i])] = Instruction::Opcode(i); + for (size_t i = 0; Instruction::instTable[i].opString; i++) + opMap[std::string(Instruction::instTable[i].opString)] + = Instruction::Opcode(i); enum { ST_INIT, ST_DEF1, ST_DEF2, ST_PERM, ST_WORD1, ST_WORD2, ST_STRING1, @@ -316,7 +317,7 @@ Obj *AsmReader::read(std::istream &input) { nextPred = false; curInst->setPred(nextPredNum); } - state = Instruction::allSrcArgs[opc]?ST_INST2:ST_INST1; + state = Instruction::instTable[opc].allSrcArgs?ST_INST2:ST_INST1; } else { asmReaderError(yyline, "Unexpected token"); } break; case ASM_T_PREG: