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4
rtl/cache/VX_cache_bank_valid.v
vendored
4
rtl/cache/VX_cache_bank_valid.v
vendored
@@ -19,9 +19,9 @@ module VX_cache_bank_valid
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for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1)
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begin
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if (NUMBER_BANKS != 1) begin
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thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
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thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
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end else begin
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thread_track_banks[t_id] = i_p_valid[t_id];
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thread_track_banks[0][t_id] = i_p_valid[t_id];
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end
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end
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end
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2
rtl/cache/VX_d_cache.v
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2
rtl/cache/VX_d_cache.v
vendored
@@ -243,7 +243,7 @@ module VX_d_cache
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assign new_stored_valid = use_valid & (~threads_serviced_Qual);
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wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE) && (CACHE_WAYS)) && (CACHE_WAYS > 1);
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wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE)) && (CACHE_WAYS > 1);
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///////////////////////////////////////////////////////////////////////
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genvar cur_t;
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