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synchronous reset network optimization: only reset register when required

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This commit is contained in:
Blaise Tine
2020-11-11 20:54:54 -08:00
parent ce95c40aee
commit fceb561cbd
8 changed files with 11 additions and 20 deletions
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2
hw/opae/vortex_afu.sv
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@@ -904,7 +904,6 @@ always @(posedge clk) begin
if (reset) begin if (reset) begin
vx_snp_req_valid <= 0; vx_snp_req_valid <= 0;
vx_snp_req_addr <= 0; vx_snp_req_addr <= 0;
vx_snp_req_tag <= 0;
vx_snp_rsp_ready <= 0; vx_snp_rsp_ready <= 0;
snp_req_ctr <= 0; snp_req_ctr <= 0;
snp_rsp_ctr <= 0; snp_rsp_ctr <= 0;
@@ -971,7 +970,6 @@ assign cmd_csr_done = (STATE_CSR_WRITE == state) ? vx_csr_io_req_ready : vx_csr_
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
csr_io_req_sent <= 0; csr_io_req_sent <= 0;
cmd_csr_rdata <= 0;
end end
else begin else begin
if (vx_csr_io_req_valid && vx_csr_io_req_ready) begin if (vx_csr_io_req_valid && vx_csr_io_req_ready) begin

2
hw/rtl/VX_gpr_bypass.v
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@@ -36,8 +36,6 @@ module VX_gpr_bypass #(
delayed_push <= 0; delayed_push <= 0;
use_buffer <= 0; use_buffer <= 0;
use_buffer2 <= 0; use_buffer2 <= 0;
buffer <= 0;
buffer2 <= 0;
end else begin end else begin
delayed_push <= push; delayed_push <= push;
assert(!use_buffer2 || use_buffer); assert(!use_buffer2 || use_buffer);

1
hw/rtl/VX_gpr_stage.v
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@@ -62,7 +62,6 @@ module VX_gpr_stage #(
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
rs3_data <= 0;
read_rs3 <= 0; read_rs3 <= 0;
end else begin end else begin
if (rs3_delay) begin if (rs3_delay) begin

2
hw/rtl/VX_ibuffer.v
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@@ -20,7 +20,7 @@ module VX_ibuffer #(
localparam ADDRW = $clog2(SIZE); localparam ADDRW = $clog2(SIZE);
localparam NWARPSW = $clog2(`NUM_WARPS+1); localparam NWARPSW = $clog2(`NUM_WARPS+1);
reg [SIZEW-1:0] size_r [`NUM_WARPS-1:0]; reg [`NUM_WARPS-1:0][SIZEW-1:0] size_r;
wire [`NUM_WARPS-1:0] q_full; wire [`NUM_WARPS-1:0] q_full;
wire [`NUM_WARPS-1:0][SIZEW-1:0] q_size; wire [`NUM_WARPS-1:0][SIZEW-1:0] q_size;

1
hw/rtl/cache/VX_cache.v vendored
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@@ -267,7 +267,6 @@ module VX_cache #(
wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag; wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag;
wire curr_bank_snp_rsp_ready; wire curr_bank_snp_rsp_ready;
wire curr_bank_core_req_ready;
wire curr_bank_miss; wire curr_bank_miss;
// Core Req // Core Req

1
hw/rtl/libs/VX_bypass_buffer.v
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@@ -26,7 +26,6 @@ module VX_bypass_buffer #(
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
buffer_valid <= 0; buffer_valid <= 0;
buffer <= 0;
end else begin end else begin
if (ready_out) begin if (ready_out) begin
buffer_valid <= 0; buffer_valid <= 0;

4
hw/rtl/libs/VX_skid_buffer.v
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@@ -21,10 +21,8 @@ module VX_skid_buffer #(
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
data_out_r <= 0;
buffer <= 0;
use_buffer <= 0;
valid_out_r <= 0; valid_out_r <= 0;
use_buffer <= 0;
end else begin end else begin
if (ready_out) begin if (ready_out) begin
use_buffer <= 0; use_buffer <= 0;