From fd1726197b1a4848cd247eb0520d3d6ff75ae595 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sun, 7 Feb 2021 07:33:39 -0800 Subject: [PATCH] cache merge optimization --- hw/rtl/cache/VX_cache_core_rsp_merge.v | 21 +++++++++++++++------ hw/syn/opae/vortex_afu.qsf | 2 +- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index f44e007e..4796eb90 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -85,25 +85,34 @@ module VX_cache_core_rsp_merge #( end else begin reg [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; + reg [NUM_REQS-1:0][NUM_BANKS-1:0] bank_select_table; + wire [NUM_REQS-1:0] core_rsp_ready_unqual; always @(*) begin core_rsp_valid_unqual = 0; core_rsp_tag_unqual = 'x; - core_rsp_data_unqual = 'x; - core_rsp_bank_select = 0; + core_rsp_data_unqual = 'x; + bank_select_table = 'x; - for (integer i = 0; i < NUM_BANKS; i++) begin - if (per_bank_core_rsp_valid[i] - && !core_rsp_valid_unqual[per_bank_core_rsp_tid[i]]) begin + for (integer i = NUM_BANKS-1; i >= 0; --i) begin + if (per_bank_core_rsp_valid[i]) begin core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i]; core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; - core_rsp_bank_select[i] = core_rsp_ready_unqual[per_bank_core_rsp_tid[i]]; + bank_select_table[per_bank_core_rsp_tid[i]] = (1 << i); end end end + always @(*) begin + core_rsp_bank_select = 0; + for (integer i = 0; i < NUM_BANKS; i++) begin + core_rsp_bank_select[i] = core_rsp_ready_unqual[per_bank_core_rsp_tid[i]] + && bank_select_table[per_bank_core_rsp_tid[i]][i]; + end + end + for (genvar i = 0; i < NUM_REQS; i++) begin VX_skid_buffer #( .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH), diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/opae/vortex_afu.qsf index af8af68d..d92ca308 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/opae/vortex_afu.qsf @@ -9,7 +9,7 @@ set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name OPTIMIZATION_TECHNIQUE BALANCED set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" set_global_assignment -name FITTER_EFFORT "STANDARD FIT"