added altera fpu modules

2020-08-05 15:53:59 -07:00
parent d8bdaa2b4e
commit ffd9515881
48 changed files with 8888 additions and 459 deletions
--- a/hw/rtl/VX_mul_unit.v
+++ b/hw/rtl/VX_mul_unit.v
@@ -104,7 +104,7 @@ module VX_mul_unit #(
    VX_shift_register #(
        .DATAW(1 + `ISTAG_BITS + 1),
        .DEPTH(`LATENCY_IMUL)
-    ) mul_delay (
+    ) mul_shift_reg (
        .clk(clk),
        .reset(reset),
        .enable(~stall_mul),
@@ -115,7 +115,7 @@ module VX_mul_unit #(
    VX_shift_register #(
        .DATAW(1 + `ISTAG_BITS + `NUM_THREADS),
        .DEPTH(`LATENCY_IDIV)
-    ) div_delay (
+    ) div_shift_reg (
        .clk(clk),
        .reset(reset),
        .enable(~stall_div),