felsabbagh3
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0a553ad0db
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2019-11-05 20:39:27 -05:00 |
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felsabbagh3
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354086ffd1
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Simple runtime for bank verification
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2019-11-05 20:38:41 -05:00 |
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Savan Roshan
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8468e7d4d9
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Added prefix DCACHE_
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2019-11-05 08:33:38 -05:00 |
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felsabbagh3
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cb3e2da584
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Added vx_tempelate.c
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2019-11-04 18:59:39 -05:00 |
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Savan Roshan
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1db160a289
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Fixed parameterization
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2019-11-04 14:32:02 -05:00 |
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Savan Roshan
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8264339853
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Added Parameterization
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2019-11-04 13:20:34 -05:00 |
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felsabbagh3
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a28a1c45c1
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wsapwn tested - NOTE in vx_main.c
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2019-11-03 20:56:07 -05:00 |
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felsabbagh3
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a39979a844
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Fixed ASIC GPR warp number delay
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2019-11-03 15:56:18 -05:00 |
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felsabbagh3
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95d8a251db
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runtime tests
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2019-11-02 10:35:20 -04:00 |
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felsabbagh3
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bbb2373919
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Intrinsics: tests for TMC+Control Divergence
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2019-11-01 21:53:37 -04:00 |
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Savan Roshan
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2b9f6f3d0b
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Fixed eviction_wb
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2019-11-01 00:39:02 -04:00 |
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felsabbagh3
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46b09028d0
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Added runtime (kernel 2.0)
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2019-10-30 23:40:01 -04:00 |
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felsabbagh3
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06e5f6df1d
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Init num cycles
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2019-10-30 15:18:52 -04:00 |
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felsabbagh3
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7863175233
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Set associative bank working
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2019-10-30 14:57:20 -04:00 |
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felsabbagh3
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3b49b82c46
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GPR ASIC Working
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2019-10-29 23:20:16 -04:00 |
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felsabbagh3
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3caae2b88e
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2019-10-29 14:28:41 -04:00 |
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felsabbagh3
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4aa04e76e6
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Simulate debug
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2019-10-29 14:28:20 -04:00 |
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Lingjun Zhu
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3609742707
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Finished synthesis at 1GHz, cell count increases to 1870k
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2019-10-29 11:33:23 -04:00 |
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Lingjun Zhu
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3c6f0b5d15
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Included the SDC and DDC files
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2019-10-28 17:24:19 -04:00 |
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Lingjun Zhu
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fa5b476874
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Added the synthesis netlist
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2019-10-28 17:11:15 -04:00 |
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Lingjun Zhu
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0d8a7be5c6
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Finished synthesis with optimization
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2019-10-28 17:10:30 -04:00 |
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Lingjun Zhu
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b6558714ca
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Finished synthesis with all memory but no optimization
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2019-10-28 16:18:11 -04:00 |
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Lingjun Zhu
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0b30b3a35f
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Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
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2019-10-28 15:06:23 -04:00 |
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Lingjun Zhu
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50d567d70c
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Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
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2019-10-28 14:49:55 -04:00 |
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felsabbagh3
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557c987bb0
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Updated files list
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2019-10-28 14:29:07 -04:00 |
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felsabbagh3
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7af6575b97
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SYN=1
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2019-10-28 13:57:01 -04:00 |
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felsabbagh3
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28ee1d3c36
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Sucess Synthesis - Finding db
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2019-10-28 13:52:49 -04:00 |
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felsabbagh3
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a8d063e9ad
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Synthesis Cleanup 1
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2019-10-28 13:43:12 -04:00 |
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felsabbagh3
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88eab9e746
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Removed dependancy on
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2019-10-27 22:30:32 -04:00 |
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felsabbagh3
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8013708a5b
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Added fsyn for my synthesis
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2019-10-27 22:16:57 -04:00 |
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felsabbagh3
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1b7f28273b
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Removed -O3 from makefile
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2019-10-27 20:34:32 -04:00 |
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felsabbagh3
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0ee74bc566
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migrated 100% to modelsim
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2019-10-27 20:08:44 -04:00 |
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felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
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372c81d90c
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Generate VCD with ModelSim
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2019-10-26 19:35:21 -04:00 |
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felsabbagh3
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6fda88b68f
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Modelsim Makefile compile + simulate - DPI
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2019-10-26 19:01:49 -04:00 |
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felsabbagh3
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ad46194d1b
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fixed width
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2019-10-26 00:39:27 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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Elsabbagh
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9110e8367e
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modelsim
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2019-10-25 23:41:34 -04:00 |
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felsabbagh3
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667dbfbbe8
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Trying icarus
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2019-10-25 22:54:02 -04:00 |
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felsabbagh3
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820007ae80
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NUM_REQ
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2019-10-25 13:46:31 -04:00 |
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felsabbagh3
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c85c01e082
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Parametized cache
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2019-10-25 13:36:06 -04:00 |
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felsabbagh3
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89d0390965
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CACHE FINALLY WORKING
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2019-10-25 04:01:23 -04:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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de8de00f6e
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Finished cache not tested
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2019-10-23 19:07:26 -04:00 |
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felsabbagh3
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6340ffcc2a
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new cache states
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2019-10-23 15:07:14 -04:00 |
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felsabbagh3
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b4d921f49a
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set_top_level tcl
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2019-10-23 11:56:32 -04:00 |
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felsabbagh3
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1645a04b1d
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Fixed SM + added def SYN
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2019-10-22 15:56:30 -04:00 |
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felsabbagh3
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3cb5820ecd
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2019-10-22 13:19:00 -04:00 |
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felsabbagh3
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f68942c92a
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Added cache+shared memory search path
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2019-10-22 13:18:49 -04:00 |
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