Commit Graph

1362 Commits

Author SHA1 Message Date
Xandy Liu
1595ff08e2 PERF pipeline stalls and cache 2020-12-08 01:14:41 -05:00
Blaise Tine
0d0706411d CSR IO's critical path elimination 2020-12-06 16:07:36 -08:00
Blaise Tine
dada72f830 minor update 2020-12-06 15:28:58 -08:00
Blaise Tine
1332970636 refactoring cores clustering 2020-12-06 14:42:12 -08:00
Blaise Tine
b2652527bb data/dram bus refactoring 2020-12-06 03:37:22 -08:00
Blaise Tine
d0f2a3984d adding input buffering to bus arbiters to reduce backpressure delay propagation 2020-12-05 17:31:29 -08:00
Blaise Tine
13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
Blaise Tine
478d971389 minor update 2020-12-03 16:21:20 -08:00
Blaise Tine
fb60d0af87 decoupled load/store commits 2020-12-03 15:08:48 -08:00
Blaise Tine
c3ec4c9e90 minor update 2020-12-03 09:30:59 -08:00
Blaise Tine
0a8f41964d minor update 2020-12-03 08:47:03 -08:00
Blaise Tine
b7a724410b update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache) 2020-12-03 07:30:19 -08:00
Blaise Tine
f3b1069ce8 adding stream arbiter 2020-12-03 06:40:23 -08:00
Blaise Tine
f575f16f57 minor update 2020-12-01 12:57:02 -08:00
Blaise Tine
b677f724aa Use skid buffer on CSR IO bus to stop backpressure delay propagation into csr_unit 2020-12-01 12:37:15 -08:00
Blaise Tine
84a9f1e2d7 minor update 2020-12-01 12:00:05 -08:00
Blaise Tine
74c9e9ad1f minor update 2020-12-01 10:42:14 -08:00
Blaise Tine
26b5bd10b3 minor update 2020-12-01 10:07:26 -08:00
Blaise Tine
f9d98c5a2b fixed bank_core_req_arb critical path. 2020-12-01 08:47:52 -08:00
Blaise Tine
f68af3bb84 using mshr pending request size 2020-12-01 00:54:25 -08:00
Blaise Tine
97739e9dcf RAM blocks inference fixes 2020-11-30 14:02:47 -08:00
Blaise Tine
5758ef9ebf generic_register reset network optimization 2020-11-29 18:41:36 -08:00
Blaise Tine
def6a35693 shared memory optimization 2020-11-29 15:04:31 -08:00
Blaise Tine
b85391389b rename MSRQ to MSHR 2020-11-28 17:32:00 -05:00
Blaise Tine
ac1883a13f tabs cleanup 2020-11-28 17:08:01 -05:00
Blaise Tine
00d7473268 build warnings clean 2020-11-28 14:59:13 -05:00
Blaise Tine
0c3d91ee6d minor update 2020-11-28 03:22:11 -05:00
Blaise Tine
457f831435 fixed scoreboard stall 2020-11-28 03:14:20 -05:00
Blaise Tine
461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
Blaise Tine
71b98b166c minor update 2020-11-24 07:10:02 -08:00
Blaise Tine
c04d385641 minor update 2020-11-23 20:12:04 -08:00
Blaise Tine
eb307edd9c minor update 2020-11-23 17:34:06 -08:00
Blaise Tine
664ce28426 minor update 2020-11-23 12:21:39 -08:00
Blaise Tine
a7cd991c87 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-11-23 12:08:48 -08:00
Blaise Tine
f4ed1e97f7 minor update 2020-11-23 12:08:31 -08:00
Blaise Tine
2d4fef6dd6 fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles 2020-11-23 11:59:40 -08:00
Blaise Tine
7a7011d5c6 minor update (trace log) 2020-11-23 14:29:35 -05:00
Blaise Tine
e281d32138 travis timeout workaround 2020-11-22 19:07:46 -08:00
Blaise Tine
23cf72d7f4 travis timeout workaround 2020-11-22 14:28:46 -08:00
Blaise Tine
f9e1e11dc5 travis timeout workaround 2020-11-22 12:41:58 -08:00
Blaise Tine
20f22c7446 scope minor fix 2020-11-22 11:51:46 -08:00
Blaise Tine
39f6f2999b snp_forwarder fix 2020-11-22 06:55:45 -08:00
Blaise Tine
93fb036c4f blackbox.sh update 2020-11-21 16:01:31 -08:00
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736c822d06 merge 2020-11-21 12:36:05 -08:00
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7ae770f4eb config update 2020-11-21 12:27:42 -08:00
Blaise Tine
1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
tinebp
91fe3efa28 Update .travis.yml
increase timeout time
2020-11-17 10:05:26 -05:00
tinebp
cad321dd9e Update .travis.yml
disable parallel build
2020-11-17 08:35:04 -05:00
tinebp
e0fe624b1d Update .travis.yml
try clang compiler to work around gcc crash
2020-11-17 07:33:05 -05:00
Blaise Tine
a7da36c007 minor update 2020-11-17 03:19:35 -08:00