Blaise Tine
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9f34b2944c
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code refactoring for Vivado, sv2v, and yosys compatibility
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2021-09-27 08:55:10 -04:00 |
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Blaise Tine
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a60bfc5e01
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extending tracing feature for advanced debugging
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2021-08-15 05:10:46 -07:00 |
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Blaise Tine
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640c98a4e8
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Reverting Verilator versionb support to v4.200
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2021-08-14 00:45:56 -07:00 |
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Blaise Tine
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3c43308e71
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Makfile fixes for latest version of Verilator
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2021-08-13 04:35:40 -07:00 |
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Blaise Tine
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f12be56d7c
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fixed Verilator warnings
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2021-08-13 05:52:43 -04:00 |
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Blaise Tine
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c2b3aaa7d1
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enabling delayed tracing
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2021-08-12 20:05:43 -07:00 |
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Blaise Tine
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e0487e4555
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minor reset delay fix
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2021-07-16 21:31:46 -07:00 |
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Blaise Tine
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86aabbbf5d
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minor update
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2021-06-28 08:00:29 -07:00 |
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Blaise Tine
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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Blaise Tine
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2372067817
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minor update
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2021-06-22 09:30:36 -07:00 |
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Blaise Tine
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c331da5ff7
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adding fast DPI implemntation of imul and idiv
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2021-06-22 09:02:41 -07:00 |
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Blaise Tine
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a315d0087d
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opae_sim buffer index allocation bug fix
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2021-06-11 15:20:02 -07:00 |
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Blaise Tine
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df7d91d690
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more testing
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2021-05-26 15:29:39 -07:00 |
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Blaise Tine
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b3e54e66f8
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fixed compiler warnings
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2021-05-23 10:54:06 -07:00 |
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Blaise Tine
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bde6a69ea0
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adding support for multi-banks memory bus
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2021-05-04 07:32:03 -07:00 |
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Blaise Tine
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d504adb236
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afu mem controller refactoring
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2021-05-01 08:39:52 -07:00 |
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Blaise Tine
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95f057bc2e
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fpga build refactoring
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2021-04-29 06:17:28 -07:00 |
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Blaise Tine
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2216a3059d
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minor update
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2021-04-27 05:52:01 -04:00 |
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Blaise Tine
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64848788a1
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minor update
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2021-04-26 20:34:28 -07:00 |
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Blaise Tine
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8543e3a8bf
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code refactoring
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2021-04-26 02:34:21 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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cad21a4b92
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minor update
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2021-04-24 01:17:38 -04:00 |
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Blaise Tine
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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Blaise Tine
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ad11bdfc87
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fix warnings
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2021-03-09 04:58:00 -08:00 |
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Blaise Tine
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c0abd6ef3f
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Aligned memory allocation workaround for PACE clusters
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2021-03-09 03:25:45 -08:00 |
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Blaise Tine
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66ea340d05
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Fix RAM memory deallocation
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2021-03-09 01:52:56 -08:00 |
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Blaise Tine
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907e6868cd
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simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite
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2021-03-08 23:58:33 -08:00 |
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Blaise Tine
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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a9f82bceae
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updating kernels with 32-cores support
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2021-01-25 10:33:42 -05:00 |
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Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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7ae936c25f
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minor updates
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2021-01-14 23:06:03 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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762b8e2e3e
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fixed cache mshr critical path
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2021-01-04 12:49:40 -05:00 |
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Blaise Tine
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4bc3b537bd
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fixed reset fan-out
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2021-01-03 20:06:36 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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e4a00dd0d9
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fixed loader script stack setup
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2020-12-31 22:37:20 -05:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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d5438fd591
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merging perf counters
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2020-12-08 21:02:39 -08:00 |
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Blaise Tine
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d68b32cd60
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minor update
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2020-12-06 22:40:27 -08:00 |
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Blaise Tine
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b7a724410b
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update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
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2020-12-03 07:30:19 -08:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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00d7473268
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build warnings clean
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2020-11-28 14:59:13 -05:00 |
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Blaise Tine
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461be0880d
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fixed FPU-CSR data dependence
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2020-11-25 09:05:38 -08:00 |
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Blaise Tine
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c04d385641
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minor update
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2020-11-23 20:12:04 -08:00 |
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Blaise Tine
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664ce28426
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minor update
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2020-11-23 12:21:39 -08:00 |
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Blaise Tine
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2d4fef6dd6
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fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
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2020-11-23 11:59:40 -08:00 |
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Blaise Tine
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20f22c7446
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scope minor fix
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2020-11-22 11:51:46 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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