 Lingjun Zhu
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0ad491f20e
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Added dc.log
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2019-11-11 14:30:14 -05:00 |
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Lingjun Zhu
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0d8a7be5c6
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Finished synthesis with optimization
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2019-10-28 17:10:30 -04:00 |
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Lingjun Zhu
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b6558714ca
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Finished synthesis with all memory but no optimization
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2019-10-28 16:18:11 -04:00 |
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Lingjun Zhu
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0b30b3a35f
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Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
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2019-10-28 15:06:23 -04:00 |
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Lingjun Zhu
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50d567d70c
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Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
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2019-10-28 14:49:55 -04:00 |
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Lingjun Zhu
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d164ebfbc6
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Added log file of synthesis, too many registers are removed
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2019-10-17 14:25:54 -04:00 |
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