10 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	8a306de02d	runtime static library	2020-06-27 14:13:13 -04:00
Blaise Tine	106d707024	verilator suppor for opae (partial)	2020-06-03 06:22:49 -04:00
Blaise Tine	81745f08c9	added config.vh	2020-04-16 07:49:19 -04:00
Blaise Tine	12dc4d6874	refactoring fixes	2020-04-14 19:39:59 -04:00
Blaise Tine	fc155e1223	project directories reorganization	2020-04-14 06:35:20 -04:00
wgulian3	f126a23114	Generate define overrides based on env vars for C and Verilog. ... gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.	2020-03-26 04:08:43 -04:00
felsabbagh3	9a0c5e0dbc	Removed kernel	2019-11-07 00:15:07 -05:00
felsabbagh3	fcd3bbc4a1	old tb	2019-11-05 22:57:05 -05:00
felsabbagh3	95d8a251db	runtime tests	2019-11-02 10:35:20 -04:00
felsabbagh3	46b09028d0	Added runtime (kernel 2.0)	2019-10-30 23:40:01 -04:00