Blaise Tine
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16d5a8a09c
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opae rtl fixes
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2020-05-31 14:51:42 -07:00 |
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Blaise Tine
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6a3b237054
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minor update
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2020-05-29 00:57:59 -04:00 |
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felsabbagh3
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033381ab6f
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Force correct word selection when BANK_LINE_WORD=1
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2020-05-28 20:39:39 -07:00 |
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Blaise Tine
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33b273b204
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-28 18:34:25 -04:00 |
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Blaise Tine
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b930a822ad
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minor updates
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2020-05-28 18:34:03 -04:00 |
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Blaise Tine
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611ceb000a
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fixed warp_sched lock bug
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2020-05-28 08:52:20 -04:00 |
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Blaise Tine
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98b98b1005
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remove riscv_test bin files
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2020-05-27 19:01:36 -04:00 |
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Blaise Tine
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9e5885b820
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adding dram writeenable support + scheduler bug fixes
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2020-05-27 19:00:23 -04:00 |
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Tine, Blaise
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b43dd76d0d
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fixed typo
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2020-05-26 23:15:32 -04:00 |
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Blaise Tine
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61231cd2af
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OPAE rtl fixes
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2020-05-24 02:42:56 -07:00 |
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Blaise Tine
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a9f896b4f3
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fixed snoop forwarding bug and single bank support
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2020-05-24 04:29:43 -04:00 |
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Blaise Tine
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47ed6b18ff
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-24 01:37:55 -04:00 |
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felsabbagh3
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a1e9b512b0
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Added mrvq_recover_ready_state_st2 to optimize fills sent
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2020-05-23 21:47:51 -07:00 |
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felsabbagh3
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0cd9bd689e
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Added schedule_ptr to mrvq for speculative pops
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2020-05-23 21:36:57 -07:00 |
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Blaise Tine
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3a9e79d979
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revert byte_enable tag structure
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2020-05-23 22:23:25 -04:00 |
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Blaise Tine
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c54fa50715
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fixed snoop forwarder dequue to support out of order responses
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2020-05-23 20:19:54 -04:00 |
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Blaise Tine
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9398c07afb
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optimized avs_pending_reads in vortex_afu.sv
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2020-05-23 19:54:37 -04:00 |
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Blaise Tine
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507622f1a1
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fixed simulator snoop handling
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2020-05-23 19:26:59 -04:00 |
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Blaise Tine
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6882d88a62
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removed fill_invalidator (not needed anymore)
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2020-05-23 19:24:52 -04:00 |
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Blaise Tine
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f3b21aab8f
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remove unsued cache parameter LLVQ_SIZE
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2020-05-23 00:33:51 -04:00 |
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Blaise Tine
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70dadca9fe
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fix scheduler rename_table X values - reverted valid bits
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2020-05-23 00:22:56 -04:00 |
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Blaise Tine
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1512138a15
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minor update
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2020-05-22 19:14:07 -07:00 |
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Blaise Tine
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b02fc14da6
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fill invalifator fix + refactoring
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2020-05-21 20:38:55 -07:00 |
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Blaise Tine
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70c70407c9
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minor update
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2020-05-21 12:08:16 -07:00 |
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Blaise Tine
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002a28e568
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-21 14:52:36 -04:00 |
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Blaise Tine
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3c8620e770
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minor update
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2020-05-21 14:51:56 -04:00 |
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Blaise Tine
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cf22ef2bf3
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minor update
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2020-05-21 13:42:08 -04:00 |
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Blaise Tine
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8daab1c22b
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-21 01:11:38 -07:00 |
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Blaise Tine
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d12c40131e
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optimize generic_queue to support simple model for smaller size queues
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2020-05-21 04:04:27 -04:00 |
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Blaise Tine
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276fa5c919
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optimize generic_queue to support simple model for smaller size queues
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2020-05-21 03:34:03 -04:00 |
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Blaise Tine
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3f5fa64085
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-21 00:00:29 -07:00 |
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Blaise Tine
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f14996b4ae
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minor update
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2020-05-20 23:54:27 -07:00 |
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felsabbagh3
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7e091b53f8
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Added valid_table in scheduler and removed rename_table on reset
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2020-05-20 23:02:41 -07:00 |
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Blaise Tine
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a8bf62a168
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minor update
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2020-05-20 21:05:29 -04:00 |
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Blaise Tine
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240bdae13d
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minor update
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2020-05-20 20:58:17 -04:00 |
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Blaise Tine
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1102871180
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force random values for unitialized signals
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2020-05-20 20:57:15 -04:00 |
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Blaise Tine
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7e5fed3ec1
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-20 18:27:20 -04:00 |
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Blaise Tine
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d4cb8b6f66
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fixed renaem table reset logic
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2020-05-20 18:24:09 -04:00 |
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Blaise Tine
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72d54c749c
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fixed cache msrq reset logic
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2020-05-20 18:11:31 -04:00 |
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Blaise Tine
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e1b4862f85
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minor update
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2020-05-20 14:14:29 -07:00 |
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Blaise Tine
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cefd0d85af
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rtl refactoring
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2020-05-20 16:59:14 -04:00 |
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Blaise Tine
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b5569dd525
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OPAE rtl fixes
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2020-05-20 12:08:10 -07:00 |
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Blaise Tine
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e3bead147a
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erge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-19 17:40:45 -07:00 |
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Blaise Tine
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c37e6e2207
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opae rtl fixes
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2020-05-19 17:36:18 -07:00 |
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felsabbagh3
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cad92bbeb1
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Qualify scheduler_delay with valid signal
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2020-05-19 14:59:17 -07:00 |
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Blaise Tine
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c209d902a3
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update
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2020-05-19 17:41:51 -04:00 |
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Blaise Tine
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e269909db9
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opae rtl fixes
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2020-05-19 13:47:47 -07:00 |
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Blaise Tine
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0c88da2bfb
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opae rtl fixes
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2020-05-18 20:19:02 -07:00 |
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Blaise Tine
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11ace25f27
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opae rtl fixes
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2020-05-17 20:29:42 -07:00 |
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felsabbagh3
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26f9fc96c3
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Corner case where the pipeline is stalled, makes mrvq entereis valid, but when unstalled mrvq_init isn't set up correctly
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2020-05-16 21:20:57 -07:00 |
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