Commit Graph

63 Commits

Author SHA1 Message Date
Blaise Tine
b7a724410b update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache) 2020-12-03 07:30:19 -08:00
Blaise Tine
f68af3bb84 using mshr pending request size 2020-12-01 00:54:25 -08:00
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def6a35693 shared memory optimization 2020-11-29 15:04:31 -08:00
Blaise Tine
b85391389b rename MSRQ to MSHR 2020-11-28 17:32:00 -05:00
Blaise Tine
00d7473268 build warnings clean 2020-11-28 14:59:13 -05:00
Blaise Tine
7ae770f4eb config update 2020-11-21 12:27:42 -08:00
Blaise Tine
1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
Blaise Tine
4d94d33e8d constant integration updates 2020-11-15 09:12:48 -08:00
Blaise Tine
725322807e fixed DRAM response backpressure inside Cache 2020-11-10 05:24:57 -08:00
Blaise Tine
10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2 2020-11-08 01:31:46 -08:00
Blaise Tine
ba81d76e02 cache refactoring - phase 2 2020-11-03 04:51:40 -08:00
Blaise Tine
5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
Blaise Tine
9a9f7955f0 basic test timing + scope tracing ccip 2020-10-27 17:04:04 -04:00
Blaise Tine
7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
Blaise Tine
f6f95e0c46 mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL 2020-09-19 14:45:42 -04:00
Blaise Tine
36ec603d17 fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt 2020-09-08 07:05:26 -07:00
Blaise Tine
49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
Blaise Tine
42e3b6c45d fixed lmp_mult parameters, ram init filepath 2020-09-04 07:51:46 -07:00
Blaise Tine
31ffbe0d6a clean up 'stage_1_cycles' from cache 2020-09-01 03:39:03 -07:00
Blaise Tine
0a45a8beb3 minor update 2020-09-01 00:56:10 -07:00
Blaise Tine
4e8b9fb296 FPU SVDPI support complete 2020-09-01 00:59:37 -04:00
Blaise Tine
c1df08843c minor update 2020-08-31 09:34:19 -04:00
Blaise Tine
df711986bc FPU DPI fallback 2020-08-31 09:19:55 -04:00
Blaise Tine
fde3f46798 ibuffer optimization 2020-08-26 04:44:36 -07:00
Blaise Tine
1c9445745f fp_noncomp fixes 2020-08-23 16:53:28 -07:00
Blaise Tine
0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
Blaise Tine
b8cd3b0b28 gpr pipeline optimization 2020-08-01 12:38:30 -04:00
Blaise Tine
c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00
Blaise Tine
27e95530ef pipeline optimization 2020-07-30 03:06:01 -07:00
Blaise Tine
c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
Blaise Tine
e0a9089647 floating point support fixes 2020-07-27 16:01:56 -04:00
Blaise Tine
ff12393998 floating point support fixes 2020-07-27 04:53:13 -04:00
Blaise Tine
7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
Blaise Tine
1f63f9da25 new fpu implementation 2020-07-24 00:00:37 -04:00
Blaise Tine
25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00
Blaise Tine
2de61b5982 get device caps from CSRs 2020-06-30 00:08:23 -07:00
Blaise Tine
a70562d386 set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18 2020-06-29 08:03:19 -07:00
Blaise Tine
8302641510 fpga fixes 2020-06-27 14:03:20 -07:00
Blaise Tine
4e0e710182 OPAE rtl fixes 2020-06-04 15:44:03 -07:00
Blaise Tine
04fc34b848 minor update 2020-06-03 03:05:45 -07:00
Blaise Tine
16d5a8a09c opae rtl fixes 2020-05-31 14:51:42 -07:00
Blaise Tine
611ceb000a fixed warp_sched lock bug 2020-05-28 08:52:20 -04:00
Blaise Tine
9e5885b820 adding dram writeenable support + scheduler bug fixes 2020-05-27 19:00:23 -04:00
Blaise Tine
a9f896b4f3 fixed snoop forwarding bug and single bank support 2020-05-24 04:29:43 -04:00
Blaise Tine
6882d88a62 removed fill_invalidator (not needed anymore) 2020-05-23 19:24:52 -04:00
Blaise Tine
f3b21aab8f remove unsued cache parameter LLVQ_SIZE 2020-05-23 00:33:51 -04:00
Blaise Tine
70c70407c9 minor update 2020-05-21 12:08:16 -07:00
Blaise Tine
d623ef4029 snooping response handling fix 2020-05-14 23:05:46 -04:00
Blaise Tine
bcb9514799 snooping response handling fix 2020-05-14 11:01:41 -04:00
Blaise Tine
c49f01b769 snooping response handling 2020-05-11 22:55:44 -04:00