Blaise Tine
|
b459192dec
|
critical path optimization - fpga fmax @4c = ~212 mhz
|
2020-12-26 03:28:32 -08:00 |
|
Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
97739e9dcf
|
RAM blocks inference fixes
|
2020-11-30 14:02:47 -08:00 |
|
Blaise Tine
|
43ae82e788
|
vlsim fix, verilator fst trace, use ram optimization
|
2020-10-25 16:40:50 -07:00 |
|
Blaise Tine
|
32da50816f
|
scope refactoring: adding modules definitions to VCD trace
|
2020-10-12 23:26:02 -04:00 |
|
Blaise Tine
|
fde3f46798
|
ibuffer optimization
|
2020-08-26 04:44:36 -07:00 |
|
Blaise Tine
|
f292e5003d
|
quartus build fixes
|
2020-08-23 22:04:46 -07:00 |
|
Blaise Tine
|
6c12391338
|
pipeline refactoring - fmax >= 222 mhz
|
2020-08-14 21:50:14 -07:00 |
|
Blaise Tine
|
0d82a8aa4f
|
minor update
|
2020-07-30 03:09:11 -07:00 |
|