Blaise Tine
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8ab7c590fd
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disabling fetch's deadlock check when L1 caches are present
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2024-01-31 06:16:54 -08:00 |
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Blaise Tine
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e217bc2c23
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adding tracking for SFU stalls
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2023-12-28 12:12:11 -08:00 |
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Blaise Tine
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c7a81d1493
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adding sockets support to simx and cache subsystem refactoring
minor update
minor update
minor updates
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2023-12-20 15:16:12 -08:00 |
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Blaise Tine
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e04e026a14
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profiling update
minor updates
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2023-12-18 04:43:44 -08:00 |
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Blaise Tine
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24973ffca0
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scoreboard optimization & profiling
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2023-11-27 05:53:36 -08:00 |
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Blaise Tine
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d47cccc157
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Vortex 2.0 changes:
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
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2023-10-19 20:51:22 -07:00 |
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Blaise Tine
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d7737542e4
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cache uuid support
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2021-12-09 20:43:22 -05:00 |
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Blaise Tine
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41d7e6c63a
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cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
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2021-11-30 07:08:15 -05:00 |
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Blaise Tine
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fe862f64b1
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dispatch refactoring
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2021-10-19 15:16:00 -04:00 |
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Blaise Tine
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e248f744d5
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Merge branch 'master' of https://github.com/vortexgpgpu/vortex
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2021-10-19 03:07:13 -04:00 |
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Blaise Tine
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58a2140b92
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merge update
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2021-10-15 19:58:13 -07:00 |
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Blaise Tine
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e380ded5e1
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Merge branch 'master' into graphics
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2021-10-15 19:32:11 -07:00 |
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Santosh Raghav Srivatsan
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dd12d3f848
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vortex tutorial assignment 5 solution
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2021-10-15 18:25:54 -04:00 |
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Blaise Tine
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04249c3ee9
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code refactoring for Vivado compatibility
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2021-09-29 04:48:53 -04:00 |
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Blaise Tine
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a45261b530
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code refactoring for Vivado compatibility
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2021-09-29 03:24:17 -04:00 |
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Blaise Tine
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18c1dc2f0e
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fixed interface modports
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2021-09-28 02:42:04 -07:00 |
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Blaise Tine
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9f34b2944c
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code refactoring for Vivado, sv2v, and yosys compatibility
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2021-09-27 08:55:10 -04:00 |
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Blaise Tine
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3d052e9428
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fmax optimization bundle (250 MHz).
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2021-09-08 02:26:39 -07:00 |
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Blaise Tine
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05bc970900
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minor update
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2021-09-07 23:57:14 -07:00 |
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Blaise Tine
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3e014c8285
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fmax optimizations bundles
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2021-09-06 01:36:57 -07:00 |
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Blaise Tine
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b52ace5142
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area optimization bundle
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2021-09-05 23:35:44 -07:00 |
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Blaise Tine
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a801a16062
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instruction decode refactoring fixing naming collision
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2021-08-29 20:07:34 -07:00 |
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Blaise Tine
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b1eef0fb7c
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warp scheduler optimization
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2021-08-07 23:45:01 -07:00 |
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Blaise Tine
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b5af2065ee
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fetch optimization
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2021-08-07 12:57:14 -07:00 |
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Blaise Tine
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e4d9fd8a00
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thread mask redesign
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2021-08-05 17:32:58 -07:00 |
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Blaise Tine
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7b8fe11e6a
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unused variables refactoring
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2021-08-05 01:46:26 -07:00 |
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Blaise Tine
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bb1ceffadd
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rebase master update
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2021-07-30 21:03:14 -07:00 |
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Blaise Tine
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0319283ea7
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minor update
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2021-07-20 21:42:22 -07:00 |
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Blaise Tine
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8048796102
|
minor update
|
2021-07-20 21:23:31 -07:00 |
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Blaise Tine
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aa7b0da877
|
minor update
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2021-07-20 21:07:41 -07:00 |
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Blaise Tine
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d3b788784a
|
memory interface refactoring
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2021-07-20 21:06:55 -07:00 |
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Blaise Tine
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382585d33d
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minor update
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2021-07-17 07:22:16 -07:00 |
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Blaise Tine
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5c40422e4f
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dcache response bus optimization
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2021-07-12 10:14:48 -07:00 |
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Blaise Tine
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c6afc35989
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adding data fence support
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2021-06-28 06:12:18 -07:00 |
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Blaise Tine
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f84c8a0b5d
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instr_sched => ibuffer
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2021-06-27 19:36:43 -07:00 |
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Blaise Tine
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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Blaise Tine
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3cc1190cd7
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CSRs I/O refactoring
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2021-06-11 03:08:07 -07:00 |
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Blaise Tine
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5d2437d887
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refactoring cache_config
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2021-05-27 14:41:46 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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d808aa2735
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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Blaise Tine
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10a994d11a
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csr minor update
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2021-03-08 03:46:07 -08:00 |
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Blaise Tine
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062d02ddce
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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b441870789
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rename use_imm and use_PC
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2021-03-01 00:38:46 -08:00 |
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Blaise Tine
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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ab63ac9e5d
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cache request interfaces update
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2021-02-10 20:55:04 -08:00 |
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Blaise Tine
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7c4823e65c
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fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
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2021-01-11 23:55:09 -08:00 |
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Blaise Tine
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9f128085d5
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scoreboard optimization - using writeback's end-of-packet status
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2020-12-30 06:47:56 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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