c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
246 lines
11 KiB
Python
Executable File
246 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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import sys
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import argparse
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import csv
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import re
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def parse_args():
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parser = argparse.ArgumentParser(description='CPU trace log to CSV format converter.')
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parser.add_argument('-t', '--type', default='simx', help='log type (rtlsim or simx)')
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parser.add_argument('-o', '--csv', default='trace.csv', help='Output CSV file')
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parser.add_argument('log', help='Input log file')
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return parser.parse_args()
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def parse_simx(log_filename):
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pc_pattern = r"PC=(0x[0-9a-fA-F]+)"
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instr_pattern = r"Instr (0x[0-9a-fA-F]+):"
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opcode_pattern = r"Instr 0x[0-9a-fA-F]+: ([0-9a-zA-Z_\.]+)"
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core_id_pattern = r"cid=(\d+)"
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warp_id_pattern = r"wid=(\d+)"
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tmask_pattern = r"tmask=(\d+)"
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operands_pattern = r"Src\d+ Reg: (.+)"
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destination_pattern = r"Dest Reg: (.+)"
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uuid_pattern = r"#(\d+)"
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entries = []
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with open(log_filename, 'r') as log_file:
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instr_data = None
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for lineno, line in enumerate(log_file, start=1):
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if line.startswith("DEBUG Fetch:"):
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if instr_data:
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entries.append(instr_data)
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instr_data = {}
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instr_data["lineno"] = lineno
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instr_data["PC"] = re.search(pc_pattern, line).group(1)
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instr_data["core_id"] = re.search(core_id_pattern, line).group(1)
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instr_data["warp_id"] = re.search(warp_id_pattern, line).group(1)
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instr_data["tmask"] = re.search(tmask_pattern, line).group(1)
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instr_data["uuid"] = re.search(uuid_pattern, line).group(1)
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elif line.startswith("DEBUG Instr"):
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instr_data["instr"] = re.search(instr_pattern, line).group(1)
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instr_data["opcode"] = re.search(opcode_pattern, line).group(1)
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elif line.startswith("DEBUG Src"):
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src_reg = re.search(operands_pattern, line).group(1)
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instr_data["operands"] = (instr_data["operands"] + ', ' + src_reg) if 'operands' in instr_data else src_reg
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elif line.startswith("DEBUG Dest"):
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instr_data["destination"] = re.search(destination_pattern, line).group(1)
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if instr_data:
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entries.append(instr_data)
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return entries
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def reverse_binary(bin_str):
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return bin_str[::-1]
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def bin_to_array(bin_str):
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return [int(bit) for bit in bin_str]
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def append_reg(text, value, sep):
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if sep:
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text += ", "
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ivalue = int(value)
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if (ivalue >= 32):
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text += "f" + str(ivalue % 32)
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else:
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text += "x" + value
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sep = True
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return text, sep
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def append_imm(text, value, sep):
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if sep:
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text += ", "
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text += value
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sep = True
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return text, sep
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def append_value(text, reg, value, tmask_arr, sep):
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text, sep = append_reg(text, reg, sep)
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text += "={"
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for i in range(len(tmask_arr)):
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if i != 0:
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text += ", "
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if tmask_arr[i]:
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text += value[i]
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else:
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text +="-"
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text += "}"
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return text, sep
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def parse_rtlsim(log_filename):
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line_pattern = r"\d+: core(\d+)-(decode|issue|commit)"
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pc_pattern = r"PC=(0x[0-9a-fA-F]+)"
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instr_pattern = r"instr=(0x[0-9a-fA-F]+)"
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ex_pattern = r"ex=([a-zA-Z]+)"
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op_pattern = r"op=([\?0-9a-zA-Z_\.]+)"
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warp_id_pattern = r"wid=(\d+)"
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tmask_pattern = r"tmask=(\d+)"
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wb_pattern = r"wb=(\d)"
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opds_pattern = r"opds=(\d+)"
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use_imm_pattern = r"use_imm=(\d)"
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imm_pattern = r"imm=(0x[0-9a-fA-F]+)"
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rd_pattern = r"rd=(\d+)"
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rs1_pattern = r"rs1=(\d+)"
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rs2_pattern = r"rs2=(\d+)"
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rs3_pattern = r"rs3=(\d+)"
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rs1_data_pattern = r"rs1_data=\{(.+?)\}"
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rs2_data_pattern = r"rs2_data=\{(.+?)\}"
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rs3_data_pattern = r"rs3_data=\{(.+?)\}"
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rd_data_pattern = r"data=\{(.+?)\}"
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eop_pattern = r"eop=(\d)"
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uuid_pattern = r"#(\d+)"
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entries = []
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with open(log_filename, 'r') as log_file:
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instr_data = {}
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for lineno, line in enumerate(log_file, start=1):
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line_match = re.search(line_pattern, line)
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if line_match:
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PC = re.search(pc_pattern, line).group(1)
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warp_id = re.search(warp_id_pattern, line).group(1)
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tmask = re.search(tmask_pattern, line).group(1)
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uuid = re.search(uuid_pattern, line).group(1)
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core_id = line_match.group(1)
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stage = line_match.group(2)
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if stage == "decode":
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trace = {}
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trace["uuid"] = uuid
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trace["PC"] = PC
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trace["core_id"] = core_id
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trace["warp_id"] = warp_id
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trace["tmask"] = reverse_binary(tmask)
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trace["instr"] = re.search(instr_pattern, line).group(1)
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trace["opcode"] = re.search(op_pattern, line).group(1)
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trace["opds"] = bin_to_array(re.search(opds_pattern, line).group(1))
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trace["rd"] = re.search(rd_pattern, line).group(1)
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trace["rs1"] = re.search(rs1_pattern, line).group(1)
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trace["rs2"] = re.search(rs2_pattern, line).group(1)
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trace["rs3"] = re.search(rs3_pattern, line).group(1)
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trace["use_imm"] = re.search(use_imm_pattern, line).group(1) == "1"
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trace["imm"] = re.search(imm_pattern, line).group(1)
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instr_data[uuid] = trace
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elif stage == "issue":
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if uuid in instr_data:
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trace = instr_data[uuid]
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trace["lineno"] = lineno
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opds = trace["opds"]
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if opds[1]:
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trace["rs1_data"] = re.search(rs1_data_pattern, line).group(1).split(', ')[::-1]
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if opds[2]:
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trace["rs2_data"] = re.search(rs2_data_pattern, line).group(1).split(', ')[::-1]
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if opds[3]:
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trace["rs3_data"] = re.search(rs3_data_pattern, line).group(1).split(', ')[::-1]
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trace["issued"] = True
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instr_data[uuid] = trace
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elif stage == "commit":
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if uuid in instr_data:
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trace = instr_data[uuid]
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if "issued" in trace:
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opds = trace["opds"]
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dst_tmask_arr = bin_to_array(tmask)[::-1]
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wb = re.search(wb_pattern, line).group(1) == "1"
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if wb:
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rd_data = re.search(rd_data_pattern, line).group(1).split(', ')[::-1]
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if 'rd_data' in trace:
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merged_rd_data = trace['rd_data']
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for i in range(len(dst_tmask_arr)):
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if dst_tmask_arr[i] == 1:
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merged_rd_data[i] = rd_data[i]
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trace['rd_data'] = merged_rd_data
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else:
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trace['rd_data'] = rd_data
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instr_data[uuid] = trace
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eop = re.search(eop_pattern, line).group(1) == "1"
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if eop:
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tmask_arr = bin_to_array(trace["tmask"])
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destination = ''
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if wb:
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destination, sep = append_value(destination, trace["rd"], trace['rd_data'], tmask_arr, False)
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del trace['rd_data']
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trace["destination"] = destination
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operands = ''
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sep = False
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if opds[1]:
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operands, sep = append_value(operands, trace["rs1"], trace["rs1_data"], tmask_arr, sep)
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del trace["rs1_data"]
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if opds[2]:
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operands, sep = append_value(operands, trace["rs2"], trace["rs2_data"], tmask_arr, sep)
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del trace["rs2_data"]
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if opds[3]:
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operands, sep = append_value(operands, trace["rs3"], trace["rs3_data"], tmask_arr, sep)
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del trace["rs3_data"]
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trace["operands"] = operands
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del trace["opds"]
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del trace["rd"]
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del trace["rs1"]
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del trace["rs2"]
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del trace["rs3"]
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del trace["use_imm"]
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del trace["imm"]
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del trace["issued"]
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del instr_data[uuid]
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entries.append(trace)
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return entries
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def write_csv(log_filename, csv_filename, log_type):
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entries = None
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# parse log file
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if log_type == "rtlsim":
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entries = parse_rtlsim(log_filename)
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elif log_type == "simx":
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entries = parse_simx(log_filename)
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else:
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print('Error: invalid log type')
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sys.exit()
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# sort entries by uuid
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entries.sort(key=lambda x: (int(x['core_id']), int(x['warp_id']), int(x['lineno'])))
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for entry in entries:
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del entry['lineno']
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# write to CSV
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with open(csv_filename, 'w', newline='') as csv_file:
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fieldnames = ["uuid", "PC", "opcode", "instr", "core_id", "warp_id", "tmask", "operands", "destination"]
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writer = csv.DictWriter(csv_file, fieldnames=fieldnames)
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writer.writeheader()
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for entry in entries:
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writer.writerow(entry)
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def main():
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args = parse_args()
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write_csv(args.log, args.csv, args.type)
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if __name__ == "__main__":
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main()
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