130 lines
3.3 KiB
Verilog
130 lines
3.3 KiB
Verilog
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`include "VX_define.v"
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module VX_gpr (
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input wire clk,
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input wire valid_write_request,
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VX_gpr_read_inter VX_gpr_read,
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VX_wb_inter VX_writeback_inter,
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output reg[`NT_M1:0][31:0] out_a_reg_data,
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output reg[`NT_M1:0][31:0] out_b_reg_data
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);
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wire write_enable;
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assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
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// byte_enabled_simple_dual_port_ram first_ram(
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// .we (write_enable),
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// .clk (clk),
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// .waddr (VX_writeback_inter.rd),
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// .raddr1(VX_gpr_read.rs1),
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// .raddr2(VX_gpr_read.rs2),
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// .be (VX_writeback_inter.wb_valid),
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// .wdata (VX_writeback_inter.write_data),
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// .q1 (out_a_reg_data),
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// .q2 (out_b_reg_data)
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// );
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// =======
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// byte_enabled_simple_dual_port_ram first_ram(
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// .we (write_enable),
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// .clk (clk),
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// .waddr (VX_writeback_inter.rd),
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// .raddr1(VX_gpr_read.rs1),
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// .be (VX_writeback_inter.wb_valid),
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// .wdata (VX_writeback_inter.write_data),
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// .q1 (out_a_reg_data)
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// );
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// byte_enabled_simple_dual_port_ram second_ram(
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// .we (write_enable),
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// .clk (clk),
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// .waddr (VX_writeback_inter.rd),
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// .raddr1(VX_gpr_read.rs2),
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// .be (VX_writeback_inter.wb_valid),
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// .wdata (VX_writeback_inter.write_data),
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// .q1 (out_b_reg_data)
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// );
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// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
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/* verilator lint_off PINCONNECTEMPTY */
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rf2_32x128_wm1 first_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(out_a_reg_data),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(1'b0),
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.AA(VX_gpr_read.rs1),
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.CLKB(clk),
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.CENB(1'b0),
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.WENB(write_bit_mask),
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.AB(VX_writeback_inter.rd),
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.DB(VX_writeback_inter.write_data),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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/* verilator lint_on PINCONNECTEMPTY */
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/* verilator lint_off PINCONNECTEMPTY */
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rf2_32x128_wm1 second_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(out_b_reg_data),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(1'b0),
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.AA(VX_gpr_read.rs2),
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.CLKB(clk),
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.CENB(1'b0),
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.WENB(write_bit_mask),
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.AB(VX_writeback_inter.rd),
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.DB(VX_writeback_inter.write_data),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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endmodule
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