18 lines
194 B
Verilog
18 lines
194 B
Verilog
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`include "../VX_define.v"
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`ifndef VX_ICACHE_RSP
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`define VX_ICACHE_RSP
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interface VX_icache_response_inter ();
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// wire ready;
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// wire stall;
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wire[31:0] instruction;
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endinterface
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`endif |