Blaise Tine 10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

2020-11-08 01:31:46 -08:00

..

.gitignore

Merge branch 'master' of https://github.gatech.edu/casl/Vortex

2020-10-12 20:33:32 -07:00

fpga.cpp

fixed new AFU Driver bugs - now functional

2020-09-09 17:05:48 -04:00

fpga.h

fixed new AFU Driver bugs - now functional

2020-09-09 17:05:48 -04:00

Makefile

refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

2020-11-08 01:31:46 -08:00

opae_sim.cpp

cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count

2020-11-02 01:50:12 -08:00

opae_sim.h

cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count

2020-11-02 01:50:12 -08:00

ram.h

adding support for verilator-driven AFU driver: vlsim

2020-09-08 13:05:26 -04:00

verilator.vlt

adding support for verilator-driven AFU driver: vlsim

2020-09-08 13:05:26 -04:00

vortex_afu_shim.sv

scope refactoring: adding modules definitions to VCD trace

2020-10-12 23:26:02 -04:00