22 lines
495 B
Verilog
22 lines
495 B
Verilog
`include "VX_define.vh"
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module VX_priority_encoder #(
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parameter N = 1
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) (
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input wire [N-1:0] data_in,
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output reg [`LOG2UP(N)-1:0] data_out,
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output reg valid_out
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);
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integer i;
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always @(*) begin
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data_out = 0;
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valid_out = 0;
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for (i = N-1; i >= 0; i = i - 1) begin
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if (data_in[i]) begin
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data_out = `LOG2UP(N)'(i);
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valid_out = 1;
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end
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end
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end
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endmodule |