401 lines
11 KiB
Verilog
401 lines
11 KiB
Verilog
`ifndef VX_DEFINE
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`define VX_DEFINE
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`include "./VX_define_synth.v"
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`define NT_M1 (`NT-1)
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// NW_M1 is actually log2(NW)
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`define NW_M1 (`CLOG2(`NW))
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// Uncomment the below line if NW=1
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// `define ONLY
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// `define SYN 1
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// `define ASIC 1
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// `define SYN_FUNC 1
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`define NUM_BARRIERS 4
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`define R_INST 7'd51
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`define L_INST 7'd3
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`define ALU_INST 7'd19
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`define S_INST 7'd35
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`define B_INST 7'd99
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`define LUI_INST 7'd55
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`define AUIPC_INST 7'd23
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`define JAL_INST 7'd111
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`define JALR_INST 7'd103
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`define SYS_INST 7'd115
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`define GPGPU_INST 7'h6b
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`define WB_ALU 2'h1
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`define WB_MEM 2'h2
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`define WB_JAL 2'h3
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`define NO_WB 2'h0
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`define RS2_IMMED 1
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`define RS2_REG 0
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`define NO_MEM_READ 3'h7
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`define LB_MEM_READ 3'h0
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`define LH_MEM_READ 3'h1
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`define LW_MEM_READ 3'h2
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`define LBU_MEM_READ 3'h4
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`define LHU_MEM_READ 3'h5
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`define NO_MEM_WRITE 3'h7
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`define SB_MEM_WRITE 3'h0
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`define SH_MEM_WRITE 3'h1
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`define SW_MEM_WRITE 3'h2
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`define NO_BRANCH 3'h0
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`define BEQ 3'h1
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`define BNE 3'h2
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`define BLT 3'h3
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`define BGT 3'h4
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`define BLTU 3'h5
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`define BGTU 3'h6
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`define NO_ALU 5'd15
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`define ADD 5'd0
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`define SUB 5'd1
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`define SLLA 5'd2
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`define SLT 5'd3
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`define SLTU 5'd4
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`define XOR 5'd5
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`define SRL 5'd6
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`define SRA 5'd7
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`define OR 5'd8
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`define AND 5'd9
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`define SUBU 5'd10
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`define LUI_ALU 5'd11
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`define AUIPC_ALU 5'd12
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`define CSR_ALU_RW 5'd13
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`define CSR_ALU_RS 5'd14
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`define CSR_ALU_RC 5'd15
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`define MUL 5'd16
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`define MULH 5'd17
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`define MULHSU 5'd18
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`define MULHU 5'd19
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`define DIV 5'd20
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`define DIVU 5'd21
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`define REM 5'd22
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`define REMU 5'd23
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// WRITEBACK
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`define WB_ALU 2'h1
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`define WB_MEM 2'h2
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`define WB_JAL 2'h3
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`define NO_WB 2'h0
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// JAL
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`define JUMP 1'h1
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`define NO_JUMP 1'h0
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// STALLS
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`define STALL 1'h1
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`define NO_STALL 1'h0
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`define TAKEN 1'b1
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`define NOT_TAKEN 1'b0
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`define ZERO_REG 5'h0
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`define CLOG2(x) \
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(x <= 2) ? 1 : \
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(x <= 4) ? 2 : \
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(x <= 8) ? 3 : \
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(x <= 16) ? 4 : \
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(x <= 32) ? 5 : \
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(x <= 64) ? 6 : \
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(x <= 128) ? 7 : \
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(x <= 256) ? 8 : \
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(x <= 512) ? 9 : \
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(x <= 1024) ? 10 : \
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-199
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`define NUMBER_CORES_PER_CLUSTER 2
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`define NUMBER_CLUSTERS 2
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`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
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// `define SINGLE_CORE_BENCH 0
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`define GLOBAL_BLOCK_SIZE_BYTES 16
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// ========================================= Dcache Configurable Knobs =========================================
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// General Cache Knobs
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// Size of cache in bytes
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`define DCACHE_SIZE_BYTES 1024
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// Size of line inside a bank in bytes
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`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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// Number of banks {1, 2, 4, 8,...}
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`define DNUMBER_BANKS 8
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// Size of a word in bytes
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`define DWORD_SIZE_BYTES 4
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define DNUMBER_REQUESTS `NT
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// Number of cycles to complete stage 1 (read from memory)
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`define DSTAGE_1_CYCLES 2
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// Function ID
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`define DFUNC_ID 0
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// Bank Number of words in a line
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`define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES)
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`define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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`define DREQQ_SIZE `NT*`NW
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// Miss Reserv Queue Knob
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`define DMRVQ_SIZE `DREQQ_SIZE
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// Dram Fill Rsp Queue Size
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`define DDFPQ_SIZE 2
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// Snoop Req Queue
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`define DSNRQ_SIZE 8
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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`define DCWBQ_SIZE `DREQQ_SIZE
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// Dram Writeback Queue Size
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`define DDWBQ_SIZE 4
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// Dram Fill Req Queue Size
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`define DDFQQ_SIZE `DREQQ_SIZE
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// Lower Level Cache Hit Queue Size
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`define DLLVQ_SIZE 0
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// Fill Forward SNP Queue
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`define DFFSQ_SIZE 8
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// Fill Invalidator Size {Fill invalidator must be active}
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`define DFILL_INVALIDAOR_SIZE 16
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// Dram knobs
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`define DSIMULATED_DRAM_LATENCY_CYCLES 10
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// ========================================= Dcache Configurable Knobs =========================================
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// ========================================= Icache Configurable Knobs =========================================
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// General Cache Knobs
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// Size of cache in bytes
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`define ICACHE_SIZE_BYTES 1024
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// Size of line inside a bank in bytes
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`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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// Number of banks {1, 2, 4, 8,...}
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`define INUMBER_BANKS 8
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// Size of a word in bytes
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`define IWORD_SIZE_BYTES 4
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define INUMBER_REQUESTS 1
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// Number of cycles to complete stage 1 (read from memory)
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`define ISTAGE_1_CYCLES 2
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// Function ID
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`define IFUNC_ID 1
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// Bank Number of words in a line
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`define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
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`define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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`define IREQQ_SIZE `NW
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// Miss Reserv Queue Knob
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`define IMRVQ_SIZE `IREQQ_SIZE
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// Dram Fill Rsp Queue Size
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`define IDFPQ_SIZE 2
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// Snoop Req Queue
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`define ISNRQ_SIZE 8
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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`define ICWBQ_SIZE `IREQQ_SIZE
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// Dram Writeback Queue Size
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`define IDWBQ_SIZE 0
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// Dram Fill Req Queue Size
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`define IDFQQ_SIZE `IREQQ_SIZE
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// Lower Level Cache Hit Queue Size
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`define ILLVQ_SIZE 0
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// Fill Forward SNP Queue
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`define IFFSQ_SIZE 8
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// Fill Invalidator Size {Fill invalidator must be active}
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`define IFILL_INVALIDAOR_SIZE 16
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// Dram knobs
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`define ISIMULATED_DRAM_LATENCY_CYCLES 10
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// ========================================= Icache Configurable Knobs =========================================
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// ========================================= SM Configurable Knobs =========================================
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// General Cache Knobs
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// Size of cache in bytes
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`define SCACHE_SIZE_BYTES 1024
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// Size of line inside a bank in bytes
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`define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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// Number of banks {1, 2, 4, 8,...}
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`define SNUMBER_BANKS 8
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// Size of a word in bytes
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`define SWORD_SIZE_BYTES 4
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define SNUMBER_REQUESTS `NT
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// Number of cycles to complete stage 1 (read from memory)
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`define SSTAGE_1_CYCLES 2
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// Function ID
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`define SFUNC_ID 2
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// Bank Number of words in a line
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`define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES)
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`define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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`define SREQQ_SIZE `NW
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// Miss Reserv Queue Knob
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`define SMRVQ_SIZE `SREQQ_SIZE
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// Dram Fill Rsp Queue Size
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`define SDFPQ_SIZE 0
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// Snoop Req Queue
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`define SSNRQ_SIZE 0
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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`define SCWBQ_SIZE `SREQQ_SIZE
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// Dram Writeback Queue Size
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`define SDWBQ_SIZE 0
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// Dram Fill Req Queue Size
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`define SDFQQ_SIZE 0
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// Lower Level Cache Hit Queue Size
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`define SLLVQ_SIZE 0
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// Fill Forward SNP Queue
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`define SFFSQ_SIZE 0
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// Fill Invalidator Size {Fill invalidator must be active}
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`define SFILL_INVALIDAOR_SIZE 16
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// Dram knobs
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`define SSIMULATED_DRAM_LATENCY_CYCLES 10
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// ========================================= SM Configurable Knobs =========================================
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// ========================================= L2cache Configurable Knobs =========================================
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// General Cache Knobs
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// Size of cache in bytes
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`define LLCACHE_SIZE_BYTES 1024
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// Size of line inside a bank in bytes
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`define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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// Number of banks {1, 2, 4, 8,...}
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`define LLNUMBER_BANKS 8
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// Size of a word in bytes
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`define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES)
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER)
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// Number of cycles to complete stage 1 (read from memory)
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`define LLSTAGE_1_CYCLES 2
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// Function ID
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`define LLFUNC_ID 3
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// Bank Number of words in a line
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`define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES)
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`define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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`define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES_PER_CLUSTER)
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// Miss Reserv Queue Knob
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`define LLMRVQ_SIZE `LLREQQ_SIZE
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// Dram Fill Rsp Queue Size
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`define LLDFPQ_SIZE 2
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// Snoop Req Queue
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`define LLSNRQ_SIZE 8
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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`define LLCWBQ_SIZE `LLREQQ_SIZE
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// Dram Writeback Queue Size
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`define LLDWBQ_SIZE 4
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// Dram Fill Req Queue Size
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`define LLDFQQ_SIZE `LLREQQ_SIZE
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// Lower Level Cache Hit Queue Size
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`define LLLLVQ_SIZE 0
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// Fill Forward SNP Queue
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`define LLFFSQ_SIZE 8
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// Fill Invalidator Size {Fill invalidator must be active}
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`define LLFILL_INVALIDAOR_SIZE 16
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// Dram knobs
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`define LLSIMULATED_DRAM_LATENCY_CYCLES 10
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// ========================================= L2cache Configurable Knobs =========================================
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// ========================================= L3cache Configurable Knobs =========================================
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// General Cache Knobs
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// Size of cache in bytes
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`define L3CACHE_SIZE_BYTES 1024
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// Size of line inside a bank in bytes
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`define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
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// Number of banks {1, 2, 4, 8,...}
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`define L3NUMBER_BANKS 8
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// Size of a word in bytes
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`define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES)
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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`define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS)
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// Number of cycles to complete stage 1 (read from memory)
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`define L3STAGE_1_CYCLES 2
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// Function ID
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`define L3FUNC_ID 3
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// Bank Number of words in a line
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`define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
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`define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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`define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS)
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// Miss Reserv Queue Knob
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`define L3MRVQ_SIZE `LLREQQ_SIZE
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// Dram Fill Rsp Queue Size
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`define L3DFPQ_SIZE 2
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// Snoop Req Queue
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`define L3SNRQ_SIZE 8
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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`define L3CWBQ_SIZE `L3REQQ_SIZE
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// Dram Writeback Queue Size
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`define L3DWBQ_SIZE 4
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// Dram Fill Req Queue Size
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`define L3DFQQ_SIZE `L3REQQ_SIZE
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// Lower Level Cache Hit Queue Size
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`define L3LLVQ_SIZE 0
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// Fill Forward SNP Queue
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`define L3FFSQ_SIZE 8
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// Fill Invalidator Size {Fill invalidator must be active}
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`define L3FILL_INVALIDAOR_SIZE 16
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// Dram knobs
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`define L3SIMULATED_DRAM_LATENCY_CYCLES 10
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// ========================================= L3cache Configurable Knobs =========================================
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`endif
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