436 lines
8.3 KiB
Systemverilog
436 lines
8.3 KiB
Systemverilog
`ifndef VX_CONFIG
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`define VX_CONFIG
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`include "VX_user_config.vh"
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`ifndef NUM_CLUSTERS
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`define NUM_CLUSTERS 1
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`endif
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`ifndef NUM_CORES
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`define NUM_CORES 4
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`endif
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`ifndef NUM_WARPS
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`define NUM_WARPS 4
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`endif
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`ifndef NUM_THREADS
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`define NUM_THREADS 4
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`endif
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`ifndef NUM_BARRIERS
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`define NUM_BARRIERS 4
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`endif
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`ifndef L2_ENABLE
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`define L2_ENABLE (`NUM_CORES >= 4)
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`endif
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`ifndef L3_ENABLE
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`define L3_ENABLE (`NUM_CLUSTERS >= 4)
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`endif
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`ifndef GLOBAL_BLOCK_SIZE
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`define GLOBAL_BLOCK_SIZE 64
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`endif
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`ifndef L1_BLOCK_SIZE
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`define L1_BLOCK_SIZE (`NUM_THREADS * 4)
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`endif
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`ifndef STARTUP_ADDR
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`define STARTUP_ADDR 32'h80000000
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`endif
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`ifndef SHARED_MEM_BASE_ADDR
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`define SHARED_MEM_BASE_ADDR 32'h6FFFF000
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`endif
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`ifndef IO_BUS_BASE_ADDR
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`define IO_BUS_BASE_ADDR 32'hFF000000
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`endif
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`ifndef IO_BUS_ADDR_COUT
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`define IO_BUS_ADDR_COUT 32'hFFFFFFFC
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`endif
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`ifndef FRAME_BUFFER_BASE_ADDR
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`define FRAME_BUFFER_BASE_ADDR 32'hFF000000
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`endif
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`ifndef FRAME_BUFFER_WIDTH
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`define FRAME_BUFFER_WIDTH 16'd1920
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`endif
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`ifndef FRAME_BUFFER_HEIGHT
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`define FRAME_BUFFER_HEIGHT 16'd1080
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`endif
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`define FRAME_BUFFER_SIZE (FRAME_BUFFER_WIDTH * FRAME_BUFFER_HEIGHT)
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`ifndef EXT_M_DISABLE
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`define EXT_M_ENABLE
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`endif
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`ifndef EXT_F_DISABLE
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`define EXT_F_ENABLE
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`endif
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// Device identification
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`define VENDOR_ID 0
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`define ARCHITECTURE_ID 0
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`define IMPLEMENTATION_ID 0
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///////////////////////////////////////////////////////////////////////////////
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`ifndef LATENCY_IMUL
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`define LATENCY_IMUL 3
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`endif
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`ifndef LATENCY_FNONCOMP
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`define LATENCY_FNONCOMP 1
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`endif
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`ifndef LATENCY_FADDMUL
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`define LATENCY_FADDMUL 3
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`endif
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`ifndef LATENCY_FMADD
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`define LATENCY_FMADD 4
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`endif
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`ifndef LATENCY_FDIV
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`define LATENCY_FDIV 15
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`endif
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`ifndef LATENCY_FSQRT
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`define LATENCY_FSQRT 10
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`endif
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`ifndef LATENCY_ITOF
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`define LATENCY_ITOF 7
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`endif
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`ifndef LATENCY_FTOI
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`define LATENCY_FTOI 3
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`endif
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`ifndef LATENCY_FDIVSQRT
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`define LATENCY_FDIVSQRT 10
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`endif
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`ifndef LATENCY_FCONV
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`define LATENCY_FCONV 3
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`endif
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///////////////////////////////////////
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`ifndef PERF_ENABLE
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`define PERF_ENABLE
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`endif
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///////////////////////////////////////
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// CSR Addresses //////////////////////////////////////////////////////////////
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`define CSR_FFLAGS 12'h001
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`define CSR_FRM 12'h002
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`define CSR_FCSR 12'h003
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`define CSR_LTID 12'h020
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`define CSR_LWID 12'h021
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`define CSR_GTID 12'h022
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`define CSR_GWID 12'h023
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`define CSR_GCID 12'h024
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`define CSR_NT 12'h025
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`define CSR_NW 12'h026
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`define CSR_NC 12'h027
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// PERF: cache
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`define CSR_R_MISS 12'h030 // read misses
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`define CSR_R_MISS_H 12'h031
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`define CSR_W_MISS 12'h032 // write misses
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`define CSR_W_MISS_H 12'h033
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`define CSR_DRAM_ST 12'h034 // dram stalls
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`define CSR_DRAM_ST_H 12'h035
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`define CSR_CORE_RSP_ST 12'h036 // core_rsp stalls
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`define CSR_CORE_RSP_ST_H 12'h037
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`define CSR_MSRQ_ST 12'h038 // miss reserve queue stalls
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`define CSR_MSRQ_ST_H 12'h039
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`define CSR_TOTAL_ST 12'h03A // total stalls
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`define CSR_TOTAL_ST_H 12'h03B
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`define CSR_TOTAL_R 12'h03C // total reads
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`define CSR_TOTAL_R_H 12'h03D
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`define CSR_TOTAL_W 12'h03E // total writes
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`define CSR_TOTAL_W_H 12'h03F
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`define CSR_TOTAL_EV 12'h040 // total evictions
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`define CSR_TOTAL_EV_H 12'h041
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`define CSR_DRAM_LAT 12'h042 // dram latency (total)
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`define CSR_DRAM_LAT_H 12'h043
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`define CSR_DRAM_RSP 12'h044 // dram responses
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`define CSR_DRAM_RSP_H 12'h045
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// PERF: pipeline stalls
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`define CSR_FPU_ST 12'h046
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`define CSR_FPU_ST_H 12'h047
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`define CSR_MUL_ST 12'h048
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`define CSR_MUL_ST_H 12'h049
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`define CSR_CSR_ST 12'h04A
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`define CSR_CSR_ST_H 12'h04B
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`define CSR_ALU_ST 12'h04C
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`define CSR_ALU_ST_H 12'h04D
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`define CSR_GPU_ST 12'h04E
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`define CSR_GPU_ST_H 12'h04F
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`define CSR_LSU_ST 12'h050
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`define CSR_LSU_ST_H 12'h051
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`define CSR_IBUF_ST 12'h052
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`define CSR_IBUF_ST_H 12'h053
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`define CSR_SCRBRD_ST 12'h054
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`define CSR_SCRBRD_ST_H 12'h055
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`define CSR_ICACHE_ST 12'h056
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`define CSR_ICACHE_ST_H 12'h057
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//////////////////////////////////////////////////////////////
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`define CSR_SATP 12'h180
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`define CSR_PMPCFG0 12'h3A0
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`define CSR_PMPADDR0 12'h3B0
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`define CSR_MSTATUS 12'h300
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`define CSR_MISA 12'h301
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`define CSR_MEDELEG 12'h302
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`define CSR_MIDELEG 12'h303
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`define CSR_MIE 12'h304
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`define CSR_MTVEC 12'h305
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`define CSR_MEPC 12'h341
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`define CSR_CYCLE 12'hC00
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`define CSR_CYCLE_H 12'hC80
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`define CSR_INSTRET 12'hC02
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`define CSR_INSTRET_H 12'hC82
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`define CSR_MVENDORID 12'hF11
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`define CSR_MARCHID 12'hF12
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`define CSR_MIMPID 12'hF13
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`define CSR_MHARTID 12'hF14
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// Pipeline Queues ////////////////////////////////////////////////////////////
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// Size of instruction queue
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`ifndef IBUF_SIZE
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`define IBUF_SIZE 4
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`endif
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// Size of LSU Request Queue
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`ifndef LSUQ_SIZE
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`define LSUQ_SIZE 8
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`endif
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// Size of MUL Request Queue
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`ifndef MULQ_SIZE
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`define MULQ_SIZE 4
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`endif
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// Size of FPU Request Queue
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`ifndef FPUQ_SIZE
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`define FPUQ_SIZE 4
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`endif
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// Dcache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef DCACHE_SIZE
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`define DCACHE_SIZE 8192
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`endif
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// Number of banks
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`ifndef DNUM_BANKS
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`define DNUM_BANKS `NUM_THREADS
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`endif
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// Core Request Queue Size
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`ifndef DCREQ_SIZE
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`define DCREQ_SIZE 4
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`endif
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// Core Writeback Queue Size
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`ifndef DCWBQ_SIZE
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`define DCWBQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef DMSHR_SIZE
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`define DMSHR_SIZE `LSUQ_SIZE
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`endif
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// DRAM Request Queue Size
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`ifndef DDREQ_SIZE
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`define DDREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef DDRFQ_SIZE
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`define DDRFQ_SIZE 4
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`endif
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// Snoop Response Queue Size
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`ifndef DSNPQ_SIZE
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`define DSNPQ_SIZE 4
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`endif
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// Snoop Request Queue Size
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`ifndef DSNRQ_SIZE
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`define DSNRQ_SIZE 4
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`endif
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// Icache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef ICACHE_SIZE
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`define ICACHE_SIZE 4096
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`endif
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// Core Request Queue Size
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`ifndef ICREQ_SIZE
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`define ICREQ_SIZE 4
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`endif
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// Core Writeback Queue Size
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`ifndef ICWBQ_SIZE
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`define ICWBQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef IMSHR_SIZE
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`define IMSHR_SIZE `NUM_WARPS
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`endif
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// DRAM Request Queue Size
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`ifndef IDREQ_SIZE
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`define IDREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef IDRFQ_SIZE
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`define IDRFQ_SIZE 4
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`endif
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// SM Configurable Knobs //////////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef SMEM_SIZE
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`define SMEM_SIZE 4096
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`endif
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// Number of banks
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`ifndef SNUM_BANKS
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`define SNUM_BANKS `NUM_THREADS
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`endif
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// Core Request Queue Size
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`ifndef SCREQ_SIZE
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`define SCREQ_SIZE 4
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`endif
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// Core Writeback Queue Size
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`ifndef SCWBQ_SIZE
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`define SCWBQ_SIZE 4
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`endif
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// L2cache Configurable Knobs /////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef L2CACHE_SIZE
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`define L2CACHE_SIZE 131072
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`endif
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// Number of banks
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`ifndef L2NUM_BANKS
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`define L2NUM_BANKS `MIN(`NUM_CORES, 4)
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`endif
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// Core Request Queue Size
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`ifndef L2CREQ_SIZE
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`define L2CREQ_SIZE 4
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`endif
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// Core Writeback Queue Size
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`ifndef L2CWBQ_SIZE
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`define L2CWBQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef L2MSHR_SIZE
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`define L2MSHR_SIZE 8
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`endif
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// DRAM Request Queue Size
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`ifndef L2DREQ_SIZE
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`define L2DREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef L2DRFQ_SIZE
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`define L2DRFQ_SIZE 4
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`endif
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// Snoop Request Queue Size
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`ifndef L2SNRQ_SIZE
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`define L2SNRQ_SIZE 4
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`endif
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// Snoop Response Queue Size
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`ifndef L2SNPQ_SIZE
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`define L2SNPQ_SIZE 4
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`endif
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// L3cache Configurable Knobs /////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef L3CACHE_SIZE
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`define L3CACHE_SIZE 262144
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`endif
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// Number of banks
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`ifndef L3NUM_BANKS
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`define L3NUM_BANKS `MIN(`NUM_CLUSTERS, 4)
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`endif
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// Core Request Queue Size
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`ifndef L3CREQ_SIZE
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`define L3CREQ_SIZE 4
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`endif
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// Core Writeback Queue Size
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`ifndef L3CWBQ_SIZE
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`define L3CWBQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef L3MSHR_SIZE
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`define L3MSHR_SIZE 8
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`endif
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// DRAM Request Queue Size
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`ifndef L3DREQ_SIZE
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`define L3DREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef L3DRFQ_SIZE
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`define L3DRFQ_SIZE 4
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`endif
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// Snoop Request Queue Size
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`ifndef L3SNRQ_SIZE
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`define L3SNRQ_SIZE 4
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`endif
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// Snoop Response Queue Size
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`ifndef L3SNPQ_SIZE
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`define L3SNPQ_SIZE 4
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`endif
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`endif
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