200 lines
9.1 KiB
Verilog
200 lines
9.1 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_data #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// PERF: total reads
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_cache_if,
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VX_perf_pipeline_stall_if perf_pipeline_stall_if,
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`endif
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VX_cmt_to_csr_if cmt_to_csr_if,
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VX_fpu_to_csr_if fpu_to_csr_if,
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input wire read_enable,
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input wire[`CSR_ADDR_BITS-1:0] read_addr,
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input wire[`NW_BITS-1:0] read_wid,
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output wire[31:0] read_data,
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input wire write_enable,
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input wire[`CSR_ADDR_BITS-1:0] write_addr,
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input wire[`NW_BITS-1:0] write_wid,
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input wire[`CSR_WIDTH-1:0] write_data,
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input wire busy
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);
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reg [`CSR_WIDTH-1:0] csr_satp;
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reg [`CSR_WIDTH-1:0] csr_mstatus;
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reg [`CSR_WIDTH-1:0] csr_medeleg;
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reg [`CSR_WIDTH-1:0] csr_mideleg;
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reg [`CSR_WIDTH-1:0] csr_mie;
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reg [`CSR_WIDTH-1:0] csr_mtvec;
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reg [`CSR_WIDTH-1:0] csr_mepc;
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reg [`CSR_WIDTH-1:0] csr_pmpcfg [0:0];
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reg [`CSR_WIDTH-1:0] csr_pmpaddr [0:0];
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reg [63:0] csr_cycle;
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reg [63:0] csr_instret;
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reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0];
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reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0];
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reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm
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reg [31:0] read_data_r;
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always @(posedge clk) begin
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if (fpu_to_csr_if.write_enable) begin
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csr_fflags[fpu_to_csr_if.write_wid] <= fpu_to_csr_if.write_fflags;
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csr_fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] <= fpu_to_csr_if.write_fflags;
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end
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if (write_enable) begin
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case (write_addr)
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`CSR_FFLAGS: begin
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csr_fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0];
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csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0];
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end
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`CSR_FRM: begin
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csr_fcsr[write_wid][`FFG_BITS+`FRM_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
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csr_frm[write_wid] <= write_data[`FRM_BITS-1:0];
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end
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`CSR_FCSR: begin
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csr_fcsr[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0];
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csr_frm[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:`FFG_BITS];
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csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0];
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end
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`CSR_SATP: csr_satp <= write_data;
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`CSR_MSTATUS: csr_mstatus <= write_data;
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`CSR_MEDELEG: csr_medeleg <= write_data;
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`CSR_MIDELEG: csr_mideleg <= write_data;
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`CSR_MIE: csr_mie <= write_data;
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`CSR_MTVEC: csr_mtvec <= write_data;
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`CSR_MEPC: csr_mepc <= write_data;
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`CSR_PMPCFG0: csr_pmpcfg[0] <= write_data;
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`CSR_PMPADDR0: csr_pmpaddr[0] <= write_data;
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default: begin
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assert(~write_enable) else $error("%t: invalid CSR write address: %0h", $time, write_addr);
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end
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endcase
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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csr_cycle <= 0;
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csr_instret <= 0;
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end else begin
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if (busy) begin
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csr_cycle <= csr_cycle + 1;
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end
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if (cmt_to_csr_if.valid) begin
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csr_instret <= csr_instret + 64'(cmt_to_csr_if.commit_size);
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end
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end
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end
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always @(*) begin
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read_data_r = 'x;
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case (read_addr)
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`CSR_FFLAGS : read_data_r = 32'(csr_fflags[read_wid]);
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`CSR_FRM : read_data_r = 32'(csr_frm[read_wid]);
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`CSR_FCSR : read_data_r = 32'(csr_fcsr[read_wid]);
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`CSR_LWID : read_data_r = 32'(read_wid);
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`CSR_LTID ,
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`CSR_GTID ,
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`CSR_MHARTID ,
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`CSR_GWID : read_data_r = CORE_ID * `NUM_WARPS + 32'(read_wid);
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`CSR_GCID : read_data_r = CORE_ID;
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`CSR_NT : read_data_r = `NUM_THREADS;
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`CSR_NW : read_data_r = `NUM_WARPS;
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`CSR_NC : read_data_r = `NUM_CORES * `NUM_CLUSTERS;
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`ifdef PERF_ENABLE
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// PERF: cache
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`CSR_R_MISS : read_data_r = perf_cache_if.read_miss[31:0];
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`CSR_R_MISS_H : read_data_r = perf_cache_if.read_miss[63:32];
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`CSR_W_MISS : read_data_r = perf_cache_if.write_miss[31:0];
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`CSR_W_MISS_H : read_data_r = perf_cache_if.write_miss[63:32];
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`CSR_DRAM_ST : read_data_r = perf_cache_if.dram_stall[31:0];
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`CSR_DRAM_ST_H : read_data_r = perf_cache_if.dram_stall[63:32];
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`CSR_CORE_RSP_ST : read_data_r = perf_cache_if.core_rsp_stall[31:0];
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`CSR_CORE_RSP_ST_H: read_data_r = perf_cache_if.core_rsp_stall[63:32];
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`CSR_MSRQ_ST : read_data_r = perf_cache_if.msrq_stall[31:0];
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`CSR_MSRQ_ST_H : read_data_r = perf_cache_if.msrq_stall[63:32];
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`CSR_TOTAL_ST : read_data_r = perf_cache_if.total_stall[31:0];
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`CSR_TOTAL_ST_H : read_data_r = perf_cache_if.total_stall[63:32];
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`CSR_TOTAL_R : read_data_r = perf_cache_if.total_read[31:0];
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`CSR_TOTAL_R_H : read_data_r = perf_cache_if.total_read[63:32];
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`CSR_TOTAL_W : read_data_r = perf_cache_if.total_write[31:0];
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`CSR_TOTAL_W_H : read_data_r = perf_cache_if.total_write[63:32];
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`CSR_TOTAL_EV : read_data_r = perf_cache_if.total_eviction[31:0];
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`CSR_TOTAL_EV_H : read_data_r = perf_cache_if.total_eviction[63:32];
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`CSR_DRAM_LAT : read_data_r = perf_cache_if.dram_latency[31:0];
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`CSR_DRAM_LAT_H : read_data_r = perf_cache_if.dram_latency[63:32];
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`CSR_DRAM_RSP : read_data_r = perf_cache_if.dram_rsp[31:0];
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`CSR_DRAM_RSP_H : read_data_r = perf_cache_if.dram_rsp[63:32];
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// PERF: pipeline stalls
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`CSR_LSU_ST : read_data_r = perf_pipeline_stall_if.lsu_stall[31:0];
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`CSR_LSU_ST_H : read_data_r = perf_pipeline_stall_if.lsu_stall[63:32];
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`CSR_FPU_ST : read_data_r = perf_pipeline_stall_if.fpu_stall[31:0];
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`CSR_FPU_ST_H : read_data_r = perf_pipeline_stall_if.fpu_stall[63:32];
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`CSR_MUL_ST : read_data_r = perf_pipeline_stall_if.mul_stall[31:0];
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`CSR_MUL_ST_H : read_data_r = perf_pipeline_stall_if.mul_stall[63:32];
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`CSR_CSR_ST : read_data_r = perf_pipeline_stall_if.csr_stall[31:0];
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`CSR_CSR_ST_H : read_data_r = perf_pipeline_stall_if.csr_stall[63:32];
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`CSR_ALU_ST : read_data_r = perf_pipeline_stall_if.alu_stall[31:0];
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`CSR_ALU_ST_H : read_data_r = perf_pipeline_stall_if.alu_stall[63:32];
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`CSR_GPU_ST : read_data_r = perf_pipeline_stall_if.gpu_stall[31:0];
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`CSR_GPU_ST_H : read_data_r = perf_pipeline_stall_if.gpu_stall[63:32];
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`CSR_IBUF_ST : read_data_r = perf_pipeline_stall_if.ibuffer_stall[31:0];
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`CSR_IBUF_ST_H : read_data_r = perf_pipeline_stall_if.ibuffer_stall[63:32];
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`CSR_SCRBRD_ST : read_data_r = perf_pipeline_stall_if.scoreboard_stall[31:0];
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`CSR_SCRBRD_ST_H : read_data_r = perf_pipeline_stall_if.scoreboard_stall[63:32];
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`CSR_ICACHE_ST : read_data_r = perf_pipeline_stall_if.icache_stall[31:0];
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`CSR_ICACHE_ST_H : read_data_r = perf_pipeline_stall_if.icache_stall[63:32];
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`endif
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`CSR_SATP : read_data_r = 32'(csr_satp);
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`CSR_MSTATUS : read_data_r = 32'(csr_mstatus);
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`CSR_MISA : read_data_r = `ISA_CODE;
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`CSR_MEDELEG : read_data_r = 32'(csr_medeleg);
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`CSR_MIDELEG : read_data_r = 32'(csr_mideleg);
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`CSR_MIE : read_data_r = 32'(csr_mie);
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`CSR_MTVEC : read_data_r = 32'(csr_mtvec);
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`CSR_MEPC : read_data_r = 32'(csr_mepc);
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`CSR_PMPCFG0 : read_data_r = 32'(csr_pmpcfg[0]);
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`CSR_PMPADDR0 : read_data_r = 32'(csr_pmpaddr[0]);
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`CSR_CYCLE : read_data_r = csr_cycle[31:0];
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`CSR_CYCLE_H : read_data_r = csr_cycle[63:32];
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`CSR_INSTRET : read_data_r = csr_instret[31:0];
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`CSR_INSTRET_H : read_data_r = csr_instret[63:32];
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`CSR_MVENDORID : read_data_r = `VENDOR_ID;
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`CSR_MARCHID : read_data_r = `ARCHITECTURE_ID;
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`CSR_MIMPID : read_data_r = `IMPLEMENTATION_ID;
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default: begin
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assert(~read_enable) else $error("%t: invalid CSR read address: %0h", $time, read_addr);
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end
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endcase
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end
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assign read_data = read_data_r;
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assign fpu_to_csr_if.read_frm = csr_frm[fpu_to_csr_if.read_wid];
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endmodule |