152 lines
6.8 KiB
Verilog
152 lines
6.8 KiB
Verilog
`include "VX_define.vh"
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module VX_instr_demux (
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input wire clk,
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input wire reset,
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// inputs
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VX_decode_if execute_if,
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VX_gpr_rsp_if gpr_rsp_if,
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// outputs
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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wire [`NT_BITS-1:0] tid;
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VX_priority_encoder #(
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.N(`NUM_THREADS)
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) tid_select (
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.data_in (execute_if.tmask),
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.data_out (tid),
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`UNUSED_PIN (valid_out)
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);
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wire [31:0] next_PC = execute_if.PC + 4;
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// ALU unit
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wire alu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_ALU);
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wire alu_stall = alu_req_if.valid && ~alu_req_if.ready;
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wire is_br_op = `IS_BR_MOD(execute_if.op_mod);
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)),
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.R (1)
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) alu_pipe (
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.clk (clk),
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.reset (reset),
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.stall (alu_stall),
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.flush (1'b0),
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.data_in ({alu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data})
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);
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// lsu unit
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wire lsu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_LSU);
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wire lsu_stall = lsu_req_if.valid && ~lsu_req_if.ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `BYTEEN_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)),
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.R (1)
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) lsu_pipe (
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.clk (clk),
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.reset (reset),
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.stall (lsu_stall),
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.flush (1'b0),
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.data_in ({lsu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({lsu_req_if.valid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data})
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);
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// csr unit
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wire csr_req_valid = execute_if.valid && (execute_if.ex_type == `EX_CSR);
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wire csr_stall = csr_req_if.valid && ~csr_req_if.ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32),
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.R (1)
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) csr_pipe (
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.clk (clk),
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.reset (reset),
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.stall (csr_stall),
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.flush (1'b0),
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.data_in ({csr_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.rs2_is_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}),
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.data_out ({csr_req_if.valid, csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.rs2_is_imm, csr_req_if.rs1, csr_req_if.rs1_data})
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);
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// mul unit
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`ifdef EXT_M_ENABLE
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wire mul_req_valid = execute_if.valid && (execute_if.ex_type == `EX_MUL);
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wire mul_stall = mul_req_if.valid && ~mul_req_if.ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + `MUL_BITS + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)),
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.R (1)
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) mul_pipe (
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.clk (clk),
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.reset (reset),
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.stall (mul_stall),
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.flush (1'b0),
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.data_in ({mul_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `MUL_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({mul_req_if.valid, mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb, mul_req_if.rs1_data, mul_req_if.rs2_data})
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);
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`endif
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// fpu unit
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`ifdef EXT_F_ENABLE
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wire fpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_FPU);
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wire fpu_stall = fpu_req_if.valid && ~fpu_req_if.ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)),
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.R (1)
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) fpu_pipe (
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.clk (clk),
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.reset (reset),
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.stall (fpu_stall),
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.flush (1'b0),
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.data_in ({fpu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), execute_if.op_mod, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}),
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.data_out ({fpu_req_if.valid, fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data})
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);
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`else
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`UNUSED_VAR (gpr_rsp_if.rs3_data)
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`endif
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// gpu unit
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wire gpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_GPU);
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wire gpu_stall = gpu_req_if.valid && ~gpu_req_if.ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)),
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.R (1)
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) gpu_pipe (
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.clk (clk),
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.reset (reset),
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.stall (gpu_stall),
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.flush (1'b0),
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.data_in ({gpu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}),
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.data_out ({gpu_req_if.valid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data})
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);
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// can take next request?
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assign execute_if.ready = (!alu_stall && (execute_if.ex_type == `EX_ALU))
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|| (!lsu_stall && (execute_if.ex_type == `EX_LSU))
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|| (!csr_stall && (execute_if.ex_type == `EX_CSR))
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`ifdef EXT_M_ENABLE
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|| (!mul_stall && (execute_if.ex_type == `EX_MUL))
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`endif
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`ifdef EXT_F_ENABLE
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|| (!fpu_stall && (execute_if.ex_type == `EX_FPU))
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`endif
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|| (!gpu_stall && (execute_if.ex_type == `EX_GPU));
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endmodule |