99 lines
2.5 KiB
Verilog
99 lines
2.5 KiB
Verilog
`include "../VX_define.v"
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module VX_priority_encoder_sm
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#(
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parameter NB = 4,
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parameter BITS_PER_BANK = 3
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)
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(
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//INPUTS
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input wire clk,
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//input wire reset,
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input wire[`NT_M1:0] in_valid,
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input wire[`NT_M1:0][31:0] in_address,
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input wire[`NT_M1:0][31:0] in_data,
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// OUTPUTS
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// To SM Module
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output reg[NB:0] out_valid,
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output reg[NB:0][31:0] out_address,
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output reg[NB:0][31:0] out_data,
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// To Processor
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output wire[NB:0][1:0] req_num,
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output reg stall,
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output wire send_data // Finished all of the requests
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);
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reg[`NT_M1:0] left_requests;
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wire[`NT_M1:0] use_valid;
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wire requests_left = (|left_requests);
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assign use_valid = (requests_left) ? left_requests : in_valid;
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wire[NB:0][`NT_M1:0] bank_valids;
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VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
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.in_valids(use_valid),
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.in_addr(in_address),
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.bank_valids(bank_valids)
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);
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wire[NB:0] more_than_one_valid;
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genvar curr_bank;
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for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1)
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begin
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assign more_than_one_valid[curr_bank] = $countones(bank_valids[curr_bank]) > 1;
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end
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assign stall = (|more_than_one_valid);
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assign send_data = (!stall) && (|in_valid); // change
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wire[NB:0][1:0] internal_req_num;
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wire[NB:0] internal_out_valid;
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// There's one or less valid per bank
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genvar curr_bank_o;
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for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1)
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begin
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VX_generic_priority_encoder #(.N(4)) vx_priority_encoder(
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.valids(bank_valids[curr_bank_o]),
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.index(internal_req_num[curr_bank_o]),
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.found(internal_out_valid[curr_bank_o])
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);
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assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0;
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assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
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end
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reg[`NT_M1:0] serviced;
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genvar curr_b;
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always @(*) begin
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serviced = 0;
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for (curr_b = 0; curr_b <= NB; curr_b=curr_b+1) begin
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serviced[internal_req_num[curr_b]] = 1;
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end
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end
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assign req_num = internal_req_num;
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assign out_valid = internal_out_valid;
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wire[`NT_M1:0] serviced_qual = in_valid & (serviced);
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wire[`NT_M1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual);
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// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
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always @(posedge clk) begin
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if (!stall) left_requests <= 0;
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else left_requests <= new_left_requests;
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end
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endmodule |