956 lines
91 KiB
C++
956 lines
91 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Primary design header
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//
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// This header should be included by all source files instantiating the design.
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// The class here is then constructed to instantiate the design.
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// See the Verilator manual for examples.
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#ifndef _VVX_CACHE_H_
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#define _VVX_CACHE_H_ // guard
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#include "verilated_heavy.h"
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//==========
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class VVX_cache__Syms;
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class VVX_cache_VerilatedVcd;
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//----------
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VL_MODULE(VVX_cache) {
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public:
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// PORTS
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// The application code writes and reads these signals to
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// propagate new values into/out from the Verilated model.
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VL_IN8(clk,0,0);
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VL_IN8(reset,0,0);
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VL_IN8(core_req_valid,3,0);
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VL_IN8(core_req_rw,3,0);
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VL_IN16(core_req_byteen,15,0);
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VL_OUT8(core_req_ready,0,0);
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VL_OUT8(core_rsp_valid,3,0);
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VL_IN8(core_rsp_ready,0,0);
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VL_OUT8(dram_req_valid,0,0);
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VL_OUT8(dram_req_rw,0,0);
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VL_IN8(dram_req_ready,0,0);
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VL_IN8(dram_rsp_valid,0,0);
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VL_OUT8(dram_rsp_ready,0,0);
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VL_IN8(snp_req_valid,0,0);
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VL_IN8(snp_req_invalidate,0,0);
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VL_OUT8(snp_req_ready,0,0);
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VL_OUT8(snp_rsp_valid,0,0);
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VL_IN8(snp_rsp_ready,0,0);
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VL_OUT8(snp_fwdout_valid,1,0);
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VL_OUT8(snp_fwdout_invalidate,1,0);
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VL_OUT8(snp_fwdout_tag,1,0);
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VL_IN8(snp_fwdout_ready,1,0);
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VL_IN8(snp_fwdin_valid,1,0);
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VL_IN8(snp_fwdin_tag,1,0);
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VL_OUT8(snp_fwdin_ready,1,0);
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VL_OUT16(dram_req_byteen,15,0);
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VL_INW(core_req_addr,119,0,4);
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VL_INW(core_req_data,127,0,4);
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VL_OUTW(core_rsp_data,127,0,4);
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VL_OUT(dram_req_addr,27,0);
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VL_OUTW(dram_req_data,127,0,4);
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VL_OUT(dram_req_tag,27,0);
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VL_INW(dram_rsp_data,127,0,4);
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VL_IN(dram_rsp_tag,27,0);
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VL_IN(snp_req_addr,27,0);
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VL_IN(snp_req_tag,27,0);
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VL_OUT(snp_rsp_tag,27,0);
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VL_OUT64(snp_fwdout_addr,55,0);
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VL_IN64(core_req_tag,41,0);
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VL_OUT64(core_rsp_tag,41,0);
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// LOCAL SIGNALS
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// Internals; generally not touched by application code
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// Anonymous structures to workaround compiler member-count bugs
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struct {
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CData/*3:0*/ VX_cache__DOT__per_bank_core_req_ready;
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CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_valid;
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CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_tid;
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CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_ready;
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CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_req_valid;
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CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_rsp_ready;
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CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_ready;
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CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_valid;
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CData/*3:0*/ VX_cache__DOT__per_bank_snp_req_ready;
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CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_valid;
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CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_ready;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid;
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CData/*3:0*/ VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop;
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CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank;
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CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing;
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CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid;
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CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid;
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CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request;
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CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing;
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CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
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CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
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CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
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CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
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CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
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CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r;
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CData/*1:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index;
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CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual;
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CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid;
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CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use;
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CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value;
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CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill;
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CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original;
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CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
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CData/*1:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank;
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CData/*0:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid;
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CData/*3:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop;
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};
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struct {
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
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CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
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CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
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CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
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SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
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CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
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CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
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CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
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CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
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CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
};
|
|
struct {
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
|
|
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
|
|
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
|
|
QData/*63:0*/ VX_cache__DOT__per_bank_dram_wb_req_byteen;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
|
|
WData/*127:0*/ VX_cache__DOT__per_bank_core_rsp_data[4];
|
|
WData/*111:0*/ VX_cache__DOT__per_bank_dram_fill_req_addr[4];
|
|
WData/*111:0*/ VX_cache__DOT__per_bank_dram_wb_req_addr[4];
|
|
WData/*511:0*/ VX_cache__DOT__per_bank_dram_wb_req_data[16];
|
|
WData/*111:0*/ VX_cache__DOT__per_bank_snp_rsp_tag[4];
|
|
IData/*27:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr;
|
|
IData/*27:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r;
|
|
WData/*111:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4];
|
|
WData/*111:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4];
|
|
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4];
|
|
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4];
|
|
IData/*31:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
IData/*31:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
IData/*31:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
IData/*31:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
IData/*29:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0;
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5];
|
|
WData/*119:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[4];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[10];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[8];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[4];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i;
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j;
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[6];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[10];
|
|
WData/*415:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[13];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7];
|
|
IData/*29:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0;
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5];
|
|
};
|
|
struct {
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5];
|
|
WData/*119:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[4];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[10];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[8];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[4];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i;
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j;
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[6];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[10];
|
|
WData/*415:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[13];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7];
|
|
IData/*29:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0;
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5];
|
|
WData/*119:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[4];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[10];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[8];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[4];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i;
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j;
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[6];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[10];
|
|
WData/*415:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[13];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7];
|
|
IData/*29:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0;
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5];
|
|
WData/*119:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[4];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[10];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[8];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[4];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i;
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j;
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[6];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[10];
|
|
WData/*415:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[13];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7];
|
|
WData/*167:0*/ VX_cache__DOT__per_bank_core_rsp_tag[6];
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r;
|
|
QData/*41:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag;
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty;
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r;
|
|
QData/*41:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag;
|
|
};
|
|
struct {
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty;
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r;
|
|
QData/*41:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag;
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty;
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r;
|
|
QData/*41:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag;
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty;
|
|
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
|
|
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[4][4];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[1];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[1];
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[1];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[1];
|
|
QData/*48:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[1][4];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[1];
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64];
|
|
WData/*84:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[1];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[1];
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[1];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[1];
|
|
QData/*48:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[1][4];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[1];
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64];
|
|
WData/*84:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[1];
|
|
};
|
|
struct {
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[1];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[1];
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[1];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[1];
|
|
QData/*48:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[1][4];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[1];
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64];
|
|
WData/*84:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[1];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[1];
|
|
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[1];
|
|
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[1];
|
|
QData/*48:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[1][4];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[1];
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
|
|
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
|
|
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4];
|
|
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64];
|
|
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64];
|
|
WData/*84:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7];
|
|
};
|
|
|
|
// LOCAL VARIABLES
|
|
// Internals; generally not touched by application code
|
|
// Anonymous structures to workaround compiler member-count bugs
|
|
struct {
|
|
SData/*15:0*/ VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid;
|
|
CData/*3:0*/ __Vtableidx1;
|
|
CData/*3:0*/ __Vtableidx2;
|
|
CData/*3:0*/ __Vtableidx3;
|
|
CData/*3:0*/ __Vtableidx4;
|
|
CData/*3:0*/ __Vtableidx5;
|
|
CData/*3:0*/ __Vtableidx6;
|
|
CData/*3:0*/ __Vtableidx7;
|
|
CData/*3:0*/ __Vtableidx8;
|
|
CData/*0:0*/ __Vclklast__TOP__clk;
|
|
WData/*127:0*/ VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[4];
|
|
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4];
|
|
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
|
|
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
|
|
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
|
|
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
|
|
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
|
|
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
|
|
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
|
|
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
|
|
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
|
|
IData/*31:0*/ __Vm_traceActivity;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
|
|
};
|
|
struct {
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
|
|
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
|
|
};
|
|
static CData/*1:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16];
|
|
static CData/*0:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16];
|
|
static IData/*31:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
static CData/*1:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16];
|
|
static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16];
|
|
static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
static CData/*1:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16];
|
|
static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16];
|
|
static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
static CData/*1:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16];
|
|
static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16];
|
|
static IData/*31:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
static CData/*1:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
|
|
static CData/*0:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
|
|
static IData/*31:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
static CData/*1:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
|
|
static CData/*0:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
|
|
static IData/*31:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
static CData/*1:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
|
|
static CData/*0:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
|
|
static IData/*31:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
static CData/*1:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
|
|
static CData/*0:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
|
|
static IData/*31:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
|
|
|
|
// INTERNAL VARIABLES
|
|
// Internals; generally not touched by application code
|
|
VVX_cache__Syms* __VlSymsp; // Symbol table
|
|
|
|
// CONSTRUCTORS
|
|
private:
|
|
VL_UNCOPYABLE(VVX_cache); ///< Copying not allowed
|
|
public:
|
|
/// Construct the model; called by application code
|
|
/// The special name may be used to make a wrapper with a
|
|
/// single model invisible with respect to DPI scope names.
|
|
VVX_cache(const char* name = "TOP");
|
|
/// Destroy the model; called (often implicitly) by application code
|
|
~VVX_cache();
|
|
/// Trace signals in the model; called by application code
|
|
void trace(VerilatedVcdC* tfp, int levels, int options = 0);
|
|
|
|
// API METHODS
|
|
/// Evaluate the model. Application must call when inputs change.
|
|
void eval() { eval_step(); }
|
|
/// Evaluate when calling multiple units/models per time step.
|
|
void eval_step();
|
|
/// Evaluate at end of a timestep for tracing, when using eval_step().
|
|
/// Application must call after all eval() and before time changes.
|
|
void eval_end_step() {}
|
|
/// Simulation complete, run final blocks. Application must call on completion.
|
|
void final();
|
|
|
|
// INTERNAL METHODS
|
|
private:
|
|
static void _eval_initial_loop(VVX_cache__Syms* __restrict vlSymsp);
|
|
public:
|
|
void __Vconfigure(VVX_cache__Syms* symsp, bool first);
|
|
private:
|
|
static QData _change_request(VVX_cache__Syms* __restrict vlSymsp);
|
|
public:
|
|
static void _combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp);
|
|
static void _combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp);
|
|
private:
|
|
void _ctor_var_reset() VL_ATTR_COLD;
|
|
public:
|
|
static void _eval(VVX_cache__Syms* __restrict vlSymsp);
|
|
private:
|
|
#ifdef VL_DEBUG
|
|
void _eval_debug_assertions();
|
|
#endif // VL_DEBUG
|
|
public:
|
|
static void _eval_initial(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
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static void _eval_settle(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
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static void _initial__TOP__1(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
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static void _sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp);
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static void _settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
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static void traceChgThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
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static void traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
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static void traceChgThis__3(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
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static void traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
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static void traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
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static void traceChgThis__6(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
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static void traceFullThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
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static void traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
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static void traceInitThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
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static void traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
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static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code);
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static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code);
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static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code);
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} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
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//----------
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#endif // guard
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