18e3653d31
... by splitting vx_wmma_load to vx_wmma_load_{a,b} and pulling it
out of the innermost loop.
TODO: there's some duplicate address compute being done in the both
functions.
574 lines
22 KiB
C++
574 lines
22 KiB
C++
#define RISCV_CUSTOM3 0x7B
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#include <stdint.h>
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#include <vx_intrinsics.h>
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#include <vx_print.h>
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#include <vx_spawn.h>
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#include "common.h"
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#define NUM_LANES 8
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#define USE_TENSOR_CORE 1
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#define TC_SINGLE_WARP 0
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// number of loop around the inner 0..TCK..BK loop to simulate perfect-DRAM
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// scenario
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#define BK_LOOP 1
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#define TRANSPOSE_AS 1
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// Constraints on parameters:
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// * Memory:
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// (BM + BN) * BK * sizeof(float) <= sharedmem size.
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// BM * BK == BN * BK >= threadblock size >= NT * CORES_PER_CLUSTER
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// When larger, the kernel runs a sequential loop to read into sharedmem;
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// but smaller case is not handled.
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// * Compute:
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// ( M* N) / (TM*TN) == grid size >= NC*NW*NT
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// (BM*BN) / (TM*TN) == threadblock size < NT * NW * CORES_PER_CLUSTER
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// (BM*BN) / (TM*TN) == threadblock size >= NT * CORES_PER_CLUSTER
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// * Combining BM * BK >= (BM*BN) / (TM*TN) == threadblock yields
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// BM <= BK*TM*TN
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#define BM 32
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#define BN 32
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#define BK 32
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#define WM 16
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#define WN 8
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#define TCM 8
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#define TCN 8
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#define TCK 8
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#define WMITER (WM / TCM)
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#define WNITER (WN / TCN)
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#if USE_TENSOR_CORE == 1
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#define TM 1
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#define TN ((TCM * TCN) / NUM_LANES / TM)
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#else
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#define TM 1
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#define TN 1
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#endif
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#define ELEM_PER_THREAD (WMITER * WNITER * TM * TN)
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inline constexpr void map_operand_32lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// A (row major)
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// Figure 7(a) in paper
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// row 0~ 3: threadgroups 0 and 2
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// row 4~ 7: threadgroups 4 and 6
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// row 8~11: threadgroups 1 and 3
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// row 12~15: threadgroups 5 and 7
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row = tid % 4;
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row += (tg * 8) % 16;
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row += (tg / 4) * 4;
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// B (column major)
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// NOTE: Matrix B mapping in Figure 7(a) is incorrect; below is the
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// corrected mapping:
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// col 0~ 3: threadgroups 0 and 1
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// col 4~ 7: threadgroups 4 and 5
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// col 8~11: threadgroups 2 and 3
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// col 12~15: threadgroups 6 and 7
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col = tid % 4;
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col += ((tg % 4) / 2) * 8;
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col += (tg / 4) * 4;
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}
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inline constexpr void map_operand_8lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// A (row major)
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// row 0~ 3: threadgroup 0
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// row 4~ 7: threadgroup 1
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row = tid % 4;
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row += tg * 4;
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// B (column major)
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// col 0~ 3: threadgroup 0
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// col 4~ 7: threadgroup 1
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col = tid % 4;
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col += tg * 4;
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}
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inline constexpr void map_operand(const int tid, int &row, int &col) {
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if constexpr (NUM_LANES == 32) {
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map_operand_32lanes(tid, row, col);
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} else if constexpr (NUM_LANES == 8) {
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map_operand_8lanes(tid, row, col);
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} else {
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// FIXME: not allowed
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}
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}
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inline constexpr void map_c_32lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// C
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// Figure 7(b), left
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col = ((tg % 4) / 2) * 8;
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row = (tg * 8) % 16;
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row += (tg / 4) * 4;
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// Figure 7(b), right
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row += (tid % 4) % 2;
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col += ((tid % 4) / 2) * 2;
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}
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inline constexpr void map_c_8lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// C
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col = 0;
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row = tg * 4;
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// Figure 7(b), right
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row += (tid % 4) % 2;
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col += ((tid % 4) / 2) * 2;
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}
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inline constexpr void map_c(const int tid, int &row, int &col) {
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if constexpr (NUM_LANES == 32) {
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map_c_32lanes(tid, row, col);
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} else if constexpr (NUM_LANES == 8) {
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map_c_8lanes(tid, row, col);
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} else {
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// FIXME: not allowed
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}
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}
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inline void vx_wmma(const int dest_reg) {
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if (dest_reg == 0) {
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asm volatile (".insn r %0, 0, 0, x0, x0, x0" :: "i"(RISCV_CUSTOM3));
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} else {
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asm volatile (".insn r %0, 0, 0, x1, x0, x0" :: "i"(RISCV_CUSTOM3));
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}
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}
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// `local_k` is assumed to be multiple of TCK
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inline void vx_wmma_load_a(volatile float *smem_A, const int local_k,
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const int warp_row, const int wm_iter, const int thread_in_warp) {
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const int tid = thread_in_warp;
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const int tg = tid / 4;
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// TODO: this is duplicately computed between vx_wmma_load_a and vx_wmma_load_b
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int row = 0;
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int col = 0;
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map_operand(tid, row, col);
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constexpr int smem_A_rows = BM;
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constexpr int smem_A_cols = BK;
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constexpr int smem_AS_rows = BK;
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constexpr int smem_AS_cols = BM;
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constexpr int smem_B_rows = BK;
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constexpr int smem_B_cols = BN;
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if constexpr (!TRANSPOSE_AS) {
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int A_offset = (WM * warp_row + TCM * wm_iter + row) * smem_A_cols;
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// @perf: bank conflicts
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// f8-f15 stores a single row of A
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asm volatile("flw f0, %0" ::"m"(smem_A[A_offset + (local_k + 0)]));
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asm volatile("flw f1, %0" ::"m"(smem_A[A_offset + (local_k + 1)]));
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asm volatile("flw f2, %0" ::"m"(smem_A[A_offset + (local_k + 2)]));
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asm volatile("flw f3, %0" ::"m"(smem_A[A_offset + (local_k + 3)]));
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asm volatile("flw f4, %0" ::"m"(smem_A[A_offset + (local_k + 4)]));
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asm volatile("flw f5, %0" ::"m"(smem_A[A_offset + (local_k + 5)]));
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asm volatile("flw f6, %0" ::"m"(smem_A[A_offset + (local_k + 6)]));
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asm volatile("flw f7, %0" ::"m"(smem_A[A_offset + (local_k + 7)]));
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} else {
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// transposed A
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// f8-f15 stores a single row of A
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asm volatile("flw f0, %0" ::"m"(smem_A[((local_k + 0) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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asm volatile("flw f1, %0" ::"m"(smem_A[((local_k + 1) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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asm volatile("flw f2, %0" ::"m"(smem_A[((local_k + 2) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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asm volatile("flw f3, %0" ::"m"(smem_A[((local_k + 3) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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asm volatile("flw f4, %0" ::"m"(smem_A[((local_k + 4) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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asm volatile("flw f5, %0" ::"m"(smem_A[((local_k + 5) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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asm volatile("flw f6, %0" ::"m"(smem_A[((local_k + 6) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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asm volatile("flw f7, %0" ::"m"(smem_A[((local_k + 7) * smem_AS_cols) + (WM * warp_row + TCM * wm_iter) + row]));
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// #pragma GCC unroll 8
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// for (int i = 0; i < 8; i++) {
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// asm volatile("flw f0, %0" ::"m"(smem_A[((local_k + i) * smem_A_rows) + (WM * warp_row + TCM * wm_iter) + row]));
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// }
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}
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}
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// `local_k` is assumed to be multiple of TCK
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inline void vx_wmma_load_b(volatile float *smem_B, const int local_k,
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const int warp_col, const int wn_iter,
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const int thread_in_warp) {
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const int tid = thread_in_warp;
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const int tg = tid / 4;
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int row = 0;
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int col = 0;
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map_operand(tid, row, col);
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constexpr int smem_A_rows = BM;
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constexpr int smem_A_cols = BK;
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constexpr int smem_AS_rows = BK;
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constexpr int smem_AS_cols = BM;
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constexpr int smem_B_rows = BK;
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constexpr int smem_B_cols = BN;
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// f8-f15 stores a single column of B
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asm volatile("flw f8, %0" ::"m"(smem_B[((local_k + 0) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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asm volatile("flw f9, %0" ::"m"(smem_B[((local_k + 1) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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asm volatile("flw f10, %0" ::"m"(smem_B[((local_k + 2) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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asm volatile("flw f11, %0" ::"m"(smem_B[((local_k + 3) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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asm volatile("flw f12, %0" ::"m"(smem_B[((local_k + 4) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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asm volatile("flw f13, %0" ::"m"(smem_B[((local_k + 5) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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asm volatile("flw f14, %0" ::"m"(smem_B[((local_k + 6) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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asm volatile("flw f15, %0" ::"m"(smem_B[((local_k + 7) * smem_B_cols) + (WN * warp_col + TCN * wn_iter) + col]));
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}
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inline void initialize_C(const int dest_reg) {
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// initialize C to zeros
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if (dest_reg == 0) {
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asm volatile("fmv.w.x f16, x0");
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asm volatile("fmv.w.x f17, x0");
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asm volatile("fmv.w.x f18, x0");
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asm volatile("fmv.w.x f19, x0");
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asm volatile("fmv.w.x f20, x0");
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asm volatile("fmv.w.x f21, x0");
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asm volatile("fmv.w.x f22, x0");
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asm volatile("fmv.w.x f23, x0");
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} else {
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asm volatile("fmv.w.x f24, x0");
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asm volatile("fmv.w.x f25, x0");
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asm volatile("fmv.w.x f26, x0");
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asm volatile("fmv.w.x f27, x0");
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asm volatile("fmv.w.x f28, x0");
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asm volatile("fmv.w.x f29, x0");
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asm volatile("fmv.w.x f30, x0");
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asm volatile("fmv.w.x f31, x0");
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}
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}
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inline void write_results(volatile float *local_warp_results,
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const int thread_in_warp, const int warp_col,
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const int warp_row, const int wn_iter,
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const int wm_iter, const int dim_m, const int dim_n,
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float *C, const int threadblock_id_x,
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const int threadblock_id_y) {
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int tid = thread_in_warp;
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int tg = tid / 4;
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// these are [0, TCM/TCN)
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int tid_row = 0;
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int tid_col = 0;
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map_c(tid, tid_row, tid_col);
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int local_row = (WM * warp_row + TCM * wm_iter) + tid_row;
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int local_col = (WN * warp_col + TCN * wn_iter) + tid_col;
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float *global_offset_C = C +
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(BM * threadblock_id_y) * dim_n +
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BN * threadblock_id_x;
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// @perf: this likely causes a lot of gmem bank conflicts
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if (wm_iter == 0) {
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asm volatile ("fsw f16, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 0)]));
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asm volatile ("fsw f17, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 1)]));
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asm volatile ("fsw f18, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 0)]));
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asm volatile ("fsw f19, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 1)]));
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asm volatile ("fsw f20, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 4)]));
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asm volatile ("fsw f21, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 5)]));
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asm volatile ("fsw f22, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 4)]));
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asm volatile ("fsw f23, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 5)]));
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} else {
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asm volatile ("fsw f24, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 0)]));
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asm volatile ("fsw f25, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 1)]));
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asm volatile ("fsw f26, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 0)]));
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asm volatile ("fsw f27, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 1)]));
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asm volatile ("fsw f28, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 4)]));
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asm volatile ("fsw f29, %0" :: "m"(global_offset_C[dim_n * (local_row + 0) + (local_col + 5)]));
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asm volatile ("fsw f30, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 4)]));
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asm volatile ("fsw f31, %0" :: "m"(global_offset_C[dim_n * (local_row + 2) + (local_col + 5)]));
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}
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}
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inline void threadblock_barrier(unsigned int tid_in_threadblock,
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unsigned int barrier_id, unsigned int count) {
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vx_fence();
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vx_barrier(barrier_id, count);
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}
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inline void
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global_dmem_load(const uint32_t dim_n, const uint32_t dim_k, const uint32_t k,
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const float *A, const float *B, volatile float *local_a,
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volatile float *local_b, const uint32_t threadblock_id_x,
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const uint32_t threadblock_id_y, const uint32_t local_a_row,
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const uint32_t local_a_col, const uint32_t local_as_row,
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const uint32_t local_as_col, const uint32_t local_b_row,
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const uint32_t local_b_col) {
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// Data move from GMEM to SMEM
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//
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// Make sure global offset values for A and B are contiguous between
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// neighboring threads to ensure GMEM coalescing.
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//
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// TODO: Sharedmem swizzling is important here
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if constexpr (!TRANSPOSE_AS) {
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const uint32_t global_a_row = BM * threadblock_id_y + local_a_row;
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// number of rows a full TB can read at a time
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constexpr uint32_t row_stride_a = (BM * BN) / ELEM_PER_THREAD / BK;
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#pragma GCC unroll 1
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for (uint32_t local_row_offset = 0; local_row_offset < BM;
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local_row_offset += row_stride_a) {
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const uint32_t global_a_offset =
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dim_k * (global_a_row + local_row_offset) + (k + local_a_col);
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// NOTE: all threads in TB will do this load; make sure this is not
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// out-of-bounds of BM*BK
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local_a[BK * (local_a_row + local_row_offset) + local_a_col] =
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A[global_a_offset];
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}
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} else {
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const uint32_t global_a_row = BM * threadblock_id_y + local_as_col;
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// const uint32_t global_a_row = BM * threadblock_id_y + local_as_row;
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constexpr uint32_t row_stride_as = (BM * BN) / ELEM_PER_THREAD / BM;
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#pragma GCC unroll 1
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for (uint32_t local_row_offset = 0; local_row_offset < BK;
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local_row_offset += row_stride_as) {
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// @perf: bank conflicts here
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const uint32_t global_a_offset =
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dim_k * (global_a_row) + (k + local_as_row + local_row_offset);
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// FIXME experimenting with global coalescing
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// const uint32_t global_a_offset =
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// dim_k * (global_a_row + local_row_offset) + (k + local_as_col);
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local_a[BM * (local_as_row + local_row_offset) + local_as_col] =
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A[global_a_offset];
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}
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}
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constexpr uint32_t row_stride_b = (BM * BN) / ELEM_PER_THREAD / BN;
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const uint32_t global_b_col = BN * threadblock_id_x + local_b_col;
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#pragma GCC unroll 1
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for (uint32_t load_offset = 0; load_offset < BK;
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load_offset += row_stride_b) {
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const uint32_t global_b_offset =
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dim_n * (k + local_b_row + load_offset) + global_b_col;
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local_b[BN * (local_b_row + load_offset) + local_b_col] =
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B[global_b_offset];
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}
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}
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void thread_block_gemm(kernel_arg_t *__UNIFORM__ arg,
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const uint32_t tid_in_threadblock,
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const uint32_t threadblock_dim_x,
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const uint32_t threadblock_dim_y,
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const uint32_t threadblock_id_x,
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const uint32_t threadblock_id_y,
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const uint32_t threadblock_id_in_cluster,
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float *sharedmem_per_threadblock) {
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const float *A = (const float *)arg->addr_a;
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const float *B = (const float *)arg->addr_b;
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float *C = (float *)arg->addr_c;
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const uint32_t dim_m = arg->dim_m;
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const uint32_t dim_n = arg->dim_n;
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const uint32_t dim_k = arg->dim_k;
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const uint32_t local_a_row = tid_in_threadblock / BK;
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const uint32_t local_a_col = tid_in_threadblock % BK;
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const uint32_t local_as_row = tid_in_threadblock / BM;
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|
const uint32_t local_as_col = tid_in_threadblock % BM;
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const uint32_t local_b_row = tid_in_threadblock / BN;
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const uint32_t local_b_col = tid_in_threadblock % BN;
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|
|
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const uint32_t local_c_row = tid_in_threadblock / (BN / TN);
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const uint32_t local_c_col = tid_in_threadblock % (BN / TN);
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|
|
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// each thread generates TM output element
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float reg_c[TM * TN] = { 0.0f };
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float reg_a[TM] = { 0.0f };
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float reg_b[TN] = { 0.0f };
|
|
|
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const uint32_t warp_in_threadblock = tid_in_threadblock / NUM_LANES;
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const uint32_t warp_row = warp_in_threadblock / (BN / WN);
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const uint32_t warp_col = warp_in_threadblock % (BN / WN);
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const uint32_t tid_in_warp = tid_in_threadblock % NUM_LANES;
|
|
|
|
volatile float *local_a = sharedmem_per_threadblock;
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// const size_t local_a_elems = threadblock_dim_x * threadblock_dim_y;
|
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const size_t local_a_elems = (BM * BK);
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volatile float *local_b = sharedmem_per_threadblock + local_a_elems;
|
|
const size_t local_b_elems = (BK * BN);
|
|
volatile float *local_warp_results =
|
|
local_b + local_b_elems + (warp_in_threadblock * TCM * TCN);
|
|
|
|
// clear out C
|
|
initialize_C(0);
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|
initialize_C(1);
|
|
|
|
#pragma GCC unroll 1
|
|
for (uint32_t k = 0; k < dim_k; k += BK) {
|
|
global_dmem_load(dim_n, dim_k, k, A, B, local_a, local_b,
|
|
threadblock_id_x, threadblock_id_y, local_a_row,
|
|
local_a_col, local_as_row, local_as_col, local_b_row,
|
|
local_b_col);
|
|
|
|
threadblock_barrier(tid_in_threadblock, threadblock_id_in_cluster,
|
|
threadblock_dim_y);
|
|
|
|
#if USE_TENSOR_CORE
|
|
// @perf: this loop spills to stack a lot because of all the flws in
|
|
// vx_wmma_load
|
|
#pragma GCC unroll 1
|
|
for (int i = 0; i < BK_LOOP; i++) {
|
|
#pragma GCC unroll 1
|
|
for (uint32_t local_k = 0; local_k < BK; local_k += TCK) {
|
|
// perform wmma
|
|
// vx_wmma_load(local_a, local_b, warp_x, warp_y, tid_in_warp);
|
|
// FIXME: this is wrong!! need separate accumulation register for
|
|
// WM/WN_ITERS
|
|
#pragma GCC unroll 2
|
|
for (int wn_iter = 0; wn_iter < WNITER; wn_iter++) {
|
|
vx_wmma_load_b(local_b, local_k, warp_col, wn_iter, tid_in_warp);
|
|
// vx_wmma_load_b(local_b, 0, 0, 0, tid_in_warp);
|
|
#pragma GCC unroll 2
|
|
for (int wm_iter = 0; wm_iter < WMITER; wm_iter++) {
|
|
#if TC_SINGLE_WARP
|
|
if (warp_in_threadblock == 0) {
|
|
#endif
|
|
// if ((threadblock_id_in_cluster % 2) == 0) {
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// asm volatile("addi a0, a0, 0");
|
|
// }
|
|
// SMEM -> RF
|
|
vx_wmma_load_a(local_a, local_k, warp_row, wm_iter, tid_in_warp);
|
|
// vx_wmma_load_a(local_a, 0, 0, 0, tid_in_warp);
|
|
// compute
|
|
vx_wmma(wm_iter);
|
|
#if TC_SINGLE_WARP
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
threadblock_barrier(tid_in_threadblock, threadblock_id_in_cluster,
|
|
threadblock_dim_y);
|
|
|
|
#else
|
|
|
|
// Compute single tile*tile matmul
|
|
#pragma GCC unroll 4
|
|
for (uint32_t local_k = 0; local_k < BK; local_k++) {
|
|
// First, pump data from SMEM->RF
|
|
#pragma GCC unroll TM
|
|
for (uint32_t res_idx_m = 0; res_idx_m < TM; res_idx_m++) {
|
|
reg_a[res_idx_m] =
|
|
local_a[BK * (TM * local_c_row + res_idx_m) + local_k];
|
|
}
|
|
#pragma GCC unroll TN
|
|
for (uint32_t res_idx_n = 0; res_idx_n < TN; res_idx_n++) {
|
|
reg_b[res_idx_n] =
|
|
local_b[BN * local_k + (TN * local_c_col + res_idx_n)];
|
|
}
|
|
|
|
// Next, compute multiple result elements (TM*TN) by reusing data in RF
|
|
#pragma GCC unroll TM
|
|
for (uint32_t res_idx_m = 0; res_idx_m < TM; res_idx_m++) {
|
|
#pragma GCC unroll TN
|
|
for (uint32_t res_idx_n = 0; res_idx_n < TN; res_idx_n++) {
|
|
// NOTE use of local_b_row
|
|
reg_c[TN * res_idx_m + res_idx_n] +=
|
|
reg_a[res_idx_m] * reg_b[res_idx_n];
|
|
// reg_c[TN * res_idx_m + res_idx_n] +=
|
|
// local_a[BK * (TM * local_c_row + res_idx_m) + local_k] *
|
|
// local_b[BN * local_k + (TN * local_c_col + res_idx_n)];
|
|
}
|
|
}
|
|
}
|
|
|
|
threadblock_barrier(tid_in_threadblock, threadblock_id_in_cluster,
|
|
threadblock_dim_y);
|
|
#endif
|
|
}
|
|
|
|
#if USE_TENSOR_CORE
|
|
#pragma GCC unroll 1
|
|
for (int wm_iter = 0; wm_iter < WMITER; wm_iter++) {
|
|
#pragma GCC unroll 1
|
|
for (int wn_iter = 0; wn_iter < WNITER; wn_iter++) {
|
|
#if TC_SINGLE_WARP
|
|
if (warp_in_threadblock == 0) {
|
|
#endif
|
|
write_results(local_warp_results, tid_in_warp, warp_col, warp_row,
|
|
wn_iter, wm_iter, dim_m, dim_n, C, threadblock_id_x,
|
|
threadblock_id_y);
|
|
#if TC_SINGLE_WARP
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#else
|
|
|
|
// Store result data from RF to GMEM
|
|
#pragma GCC unroll TM
|
|
for (uint32_t res_idx_m = 0; res_idx_m < TM; res_idx_m++) {
|
|
#pragma GCC unroll TN
|
|
for (uint32_t res_idx_n = 0; res_idx_n < TN; res_idx_n++) {
|
|
C[dim_n * (BM * threadblock_id_y + TM * local_c_row + res_idx_m) +
|
|
(BN * threadblock_id_x + TN * local_c_col + res_idx_n)] =
|
|
reg_c[TN * res_idx_m + res_idx_n];
|
|
}
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
void kernel_body(int task_id, kernel_arg_t *__UNIFORM__ arg) {
|
|
// @perf: All threads are running these compute whose result is mostly same
|
|
// across the threadblock
|
|
|
|
const uint32_t threads_per_threadblock = (BM * BN) / (ELEM_PER_THREAD);
|
|
#ifdef RADIANCE
|
|
const uint32_t threadblocks_per_core = CORES_PER_CLUSTER * vx_num_threads() *
|
|
vx_num_warps() /
|
|
threads_per_threadblock;
|
|
#else
|
|
const uint32_t threadblocks_per_core =
|
|
vx_num_threads() * vx_num_warps() / threads_per_threadblock;
|
|
#endif
|
|
const uint32_t threadblock_dim_x = vx_num_threads();
|
|
const uint32_t threadblock_dim_y = vx_num_warps() / threadblocks_per_core;
|
|
const int threadblock_id = task_id / threads_per_threadblock;
|
|
const int threadblock_id_in_cluster = threadblock_id % threadblocks_per_core;
|
|
const int tid_in_threadblock = task_id % threads_per_threadblock;
|
|
|
|
const uint32_t dim_m = arg->dim_m;
|
|
const uint32_t dim_n = arg->dim_n;
|
|
const uint32_t dim_n_in_blocks = dim_n / BN;
|
|
const int threadblock_id_x = threadblock_id % dim_n_in_blocks;
|
|
const int threadblock_id_y = threadblock_id / dim_n_in_blocks;
|
|
|
|
// "static" shared memory allocation. This would determine threadblock
|
|
// occupancy of a single cluster
|
|
float *sharedmem_per_threadblock =
|
|
(float *)DEV_SMEM_START_ADDR + (2 * BM * BK) * threadblock_id_in_cluster;
|
|
thread_block_gemm(arg, tid_in_threadblock, threadblock_dim_x,
|
|
threadblock_dim_y, threadblock_id_x, threadblock_id_y,
|
|
threadblock_id_in_cluster, sharedmem_per_threadblock);
|
|
}
|
|
|
|
int main() {
|
|
kernel_arg_t *arg = (kernel_arg_t *)KERNEL_ARG_DEV_MEM_ADDR;
|
|
const uint32_t grid_size = arg->dim_m * arg->dim_n / ELEM_PER_THREAD;
|
|
#ifdef RADIANCE
|
|
vx_spawn_tasks_cluster(grid_size, (vx_spawn_tasks_cb)kernel_body, arg);
|
|
#else
|
|
// NOTE: This kernel assumes contiguous thread scheduling for efficient shared
|
|
// memory allocation, and therefore does not work with original vx_spawn_tasks
|
|
vx_spawn_tasks_contiguous(grid_size, (vx_spawn_tasks_cb)kernel_body, arg);
|
|
#endif
|
|
return 0;
|
|
}
|