155 lines
4.0 KiB
Verilog
155 lines
4.0 KiB
Verilog
`include "VX_define.vh"
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module VX_gpr (
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input wire clk,
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input wire reset,
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input wire valid_write_request_i,
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VX_gpr_read_if gpr_read_if,
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VX_wb_if writeback_if,
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output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_o,
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output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_o
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);
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wire write_enable;
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`ifndef ASIC
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assign write_enable = valid_write_request_i && ((writeback_if.wb != 0)) && (writeback_if.rd != 0);
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byte_enabled_simple_dual_port_ram first_ram(
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.we (write_enable),
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.clk (clk),
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.reset (reset),
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.waddr (writeback_if.rd),
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.raddr1(gpr_read_if.rs1),
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.raddr2(gpr_read_if.rs2),
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.be (writeback_if.wb_valid),
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.wdata (writeback_if.write_data),
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.q1 (a_reg_data_o),
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.q2 (b_reg_data_o)
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);
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`else
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assign write_enable = valid_write_request_i && ((writeback_if.wb != 0));
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wire going_to_write = write_enable & (|writeback_if.wb_valid);
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wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask;
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genvar curr_t;
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for (curr_t = 0; curr_t < `NUM_THREADS; curr_t=curr_t+1) begin
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wire local_write = write_enable & writeback_if.wb_valid[curr_t];
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assign write_bit_mask[curr_t] = {`NUM_GPRS{~local_write}};
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end
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// wire cenb = !going_to_write;
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wire cenb = 0;
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// wire cena_1 = (gpr_read_if.rs1 == 0);
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// wire cena_2 = (gpr_read_if.rs2 == 0);
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wire cena_1 = 0;
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wire cena_2 = 0;
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wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] temp_a;
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wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] temp_b;
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`ifndef SYN
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genvar thread;
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genvar curr_bit;
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for (thread = 0; thread < `NUM_THREADS; thread = thread + 1)
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begin
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for (curr_bit = 0; curr_bit < `NUM_GPRS; curr_bit=curr_bit+1)
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begin
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assign a_reg_data_o[thread][curr_bit] = ((temp_a[thread][curr_bit] === 1'dx) || cena_1 )? 1'b0 : temp_a[thread][curr_bit];
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assign b_reg_data_o[thread][curr_bit] = ((temp_b[thread][curr_bit] === 1'dx) || cena_2) ? 1'b0 : temp_b[thread][curr_bit];
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end
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end
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`else
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assign a_reg_data_o = temp_a;
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assign b_reg_data_o = temp_b;
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`endif
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wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = (writeback_if.rd != 0) ? writeback_if.write_data : 0;
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genvar curr_base_thread;
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for (curr_base_thread = 0; curr_base_thread < 'NT; curr_base_thread=curr_base_thread+4)
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begin
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`IGNORE_WARNINGS_BEGIN
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rf2_32x128_wm1 first_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(temp_a[(curr_base_thread+3):(curr_base_thread)]),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(cena_1),
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.AA(gpr_read_if.rs1[(curr_base_thread+3):(curr_base_thread)]),
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.CLKB(clk),
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.CENB(cenb),
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.WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]),
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.AB(writeback_if.rd[(curr_base_thread+3):(curr_base_thread)]),
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.DB(to_write[(curr_base_thread+3):(curr_base_thread)]),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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`IGNORE_WARNINGS_END
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`IGNORE_WARNINGS_BEGIN
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rf2_`NUM_GPRSx128_wm1 second_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(temp_b[(curr_base_thread+3):(curr_base_thread)]),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(cena_2),
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.AA(gpr_read_if.rs2[(curr_base_thread+3):(curr_base_thread)]),
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.CLKB(clk),
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.CENB(cenb),
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.WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]),
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.AB(writeback_if.rd[(curr_base_thread+3):(curr_base_thread)]),
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.DB(to_write[(curr_base_thread+3):(curr_base_thread)]),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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`IGNORE_WARNINGS_END
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end
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`endif
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endmodule
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