108 lines
3.5 KiB
Systemverilog
108 lines
3.5 KiB
Systemverilog
`include "VX_define.vh"
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module VX_gpu_unit #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_gpu_unit
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input wire clk,
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input wire reset,
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// Inputs
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VX_gpu_req_if.slave gpu_req_if,
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// Outputs
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VX_warp_ctl_if.master warp_ctl_if,
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VX_commit_if.master gpu_commit_if
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);
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import gpu_types::*;
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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gpu_tmc_t tmc;
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gpu_wspawn_t wspawn;
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gpu_barrier_t barrier;
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gpu_split_t split;
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wire is_wspawn = (gpu_req_if.op_type == `INST_GPU_WSPAWN);
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wire is_tmc = (gpu_req_if.op_type == `INST_GPU_TMC);
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wire is_split = (gpu_req_if.op_type == `INST_GPU_SPLIT);
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wire is_bar = (gpu_req_if.op_type == `INST_GPU_BAR);
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wire is_pred = (gpu_req_if.op_type == `INST_GPU_PRED);
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wire [31:0] rs1_data = gpu_req_if.rs1_data[gpu_req_if.tid];
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wire [`NUM_THREADS-1:0] taken_tmask;
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wire [`NUM_THREADS-1:0] not_taken_tmask;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire taken = (gpu_req_if.rs1_data[i] != 0);
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assign taken_tmask[i] = gpu_req_if.tmask[i] & taken;
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assign not_taken_tmask[i] = gpu_req_if.tmask[i] & ~taken;
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end
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// tmc
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wire [`NUM_THREADS-1:0] pred_mask = (taken_tmask != 0) ? taken_tmask : gpu_req_if.tmask;
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assign tmc.valid = is_tmc || is_pred;
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assign tmc.tmask = is_pred ? pred_mask : rs1_data[`NUM_THREADS-1:0];
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// wspawn
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wire [31:0] wspawn_pc = gpu_req_if.rs2_data;
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wire [`NUM_WARPS-1:0] wspawn_wmask;
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for (genvar i = 0; i < `NUM_WARPS; i++) begin
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assign wspawn_wmask[i] = (i < rs1_data);
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end
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assign wspawn.valid = is_wspawn;
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assign wspawn.wmask = wspawn_wmask;
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assign wspawn.pc = wspawn_pc;
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// split
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assign split.valid = is_split;
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assign split.diverged = (| taken_tmask) && (| not_taken_tmask);
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assign split.then_tmask = taken_tmask;
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assign split.else_tmask = not_taken_tmask;
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assign split.pc = gpu_req_if.next_PC;
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// barrier
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assign barrier.valid = is_bar;
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assign barrier.id = rs1_data[`NB_BITS-1:0];
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assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data - 1);
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// output
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wire stall = ~gpu_commit_if.ready && gpu_commit_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + `GPU_TMC_BITS + `GPU_WSPAWN_BITS + `GPU_SPLIT_BITS + `GPU_BARRIER_BITS),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall),
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.data_in ({gpu_req_if.valid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.rd, gpu_req_if.wb, tmc, wspawn, split, barrier}),
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.data_out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.rd, gpu_commit_if.wb, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.barrier})
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);
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assign gpu_commit_if.eop = 1'b1;
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assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready;
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assign warp_ctl_if.wid = gpu_commit_if.wid;
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// can accept new request?
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assign gpu_req_if.ready = ~stall;
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`SCOPE_ASSIGN (gpu_rsp_valid, warp_ctl_if.valid);
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`SCOPE_ASSIGN (gpu_rsp_wid, warp_ctl_if.wid);
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`SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc.valid);
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`SCOPE_ASSIGN (gpu_rsp_wspawn, warp_ctl_if.wspawn.valid);
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`SCOPE_ASSIGN (gpu_rsp_split, warp_ctl_if.split.valid);
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`SCOPE_ASSIGN (gpu_rsp_barrier, warp_ctl_if.barrier.valid);
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endmodule |