94 lines
2.4 KiB
Verilog
94 lines
2.4 KiB
Verilog
`include "VX_platform.vh"
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module VX_priority_encoder #(
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parameter N = 1,
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parameter REVERSE = 0,
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parameter FAST = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [N-1:0] onehot,
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output wire [LN-1:0] index,
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output wire valid_out
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);
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if (N == 1) begin
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assign onehot = data_in;
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assign index = 0;
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assign valid_out = data_in;
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end else if (N == 2) begin
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assign onehot = {~data_in[REVERSE], data_in[REVERSE]};
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assign index = ~data_in[REVERSE];
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assign valid_out = (| data_in);
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end else if (FAST) begin
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wire [N-1:0] scan_lo;
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VX_scan #(
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.N (N),
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.OP (2),
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.REVERSE (REVERSE)
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) scan (
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.data_in (data_in),
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.data_out (scan_lo)
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);
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if (REVERSE) begin
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assign onehot = scan_lo & {1'b1, (~scan_lo[N-1:1])};
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assign valid_out = scan_lo[0];
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end else begin
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assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
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assign valid_out = scan_lo[N-1];
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end
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VX_onehot_encoder #(
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.N (N),
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.REVERSE (REVERSE)
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) onehot_encoder (
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.data_in (onehot),
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.data_out (index),
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`UNUSED_PIN (valid)
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);
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end else begin
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reg [LN-1:0] index_r;
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reg [N-1:0] onehot_r;
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if (REVERSE) begin
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always @(*) begin
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index_r = 'x;
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onehot_r = 'x;
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for (integer i = 0; i < N; ++i) begin
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if (data_in[i]) begin
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index_r = LN'(i);
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onehot_r = 0;
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onehot_r[i] = 1'b1;
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end
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end
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end
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end else begin
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always @(*) begin
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index_r = 'x;
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onehot_r = 'x;
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for (integer i = N-1; i >= 0; --i) begin
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if (data_in[i]) begin
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index_r = LN'(i);
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onehot_r = 0;
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onehot_r[i] = 1'b1;
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end
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end
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end
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end
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assign index = index_r;
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assign onehot = onehot_r;
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assign valid_out = (| data_in);
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end
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endmodule |