126 lines
4.0 KiB
Verilog
126 lines
4.0 KiB
Verilog
module VX_mult
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#(
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parameter WIDTHA=1,
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parameter WIDTHB=1,
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parameter WIDTHP=1,
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parameter REP="UNSIGNED",
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parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
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parameter PIPELINE=0,
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parameter FORCE_LE="NO"
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)
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(
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input clock, aclr, clken,
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input [WIDTHA-1:0] dataa,
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input [WIDTHB-1:0] datab,
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output reg [WIDTHP-1:0] result
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);
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// synthesis read_comments_as_HDL on
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// localparam IMPL = "quartus";
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// synthesis read_comments_as_HDL off
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// altera translate_off
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localparam IMPL="fallback";
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// altera translate_on
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generate
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if (IMPL == "quartus") begin
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localparam lpm_speed=SPEED == "HIGHEST" ? 10:5;
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if (FORCE_LE == "YES") begin
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lpm_mult#(
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.LPM_WIDTHA(WIDTHA),
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.LPM_WIDTHB(WIDTHB),
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.LPM_WIDTHP(WIDTHP),
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.LPM_REPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
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.MAXIMIZE_SPEED(lpm_speed)
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) quartus_mult(
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.clock(clock),
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.aclr(aclr),
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.clken(clken),
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.dataa(dataa),
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.datab(datab),
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.result(result)
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);
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end
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else begin
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lpm_mult#(
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.LPM_WIDTHA(WIDTHA),
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.LPM_WIDTHB(WIDTHB),
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.LPM_WIDTHP(WIDTHP),
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.LPM_REPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.MAXIMIZE_SPEED(lpm_speed)
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) quartus_mult(
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.clock(clock),
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.aclr(aclr),
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.clken(clken),
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.dataa(dataa),
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.datab(datab),
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.result(result)
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);
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end
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end
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else begin
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wire [WIDTHA-1:0] dataa_pipe_end;
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wire [WIDTHB-1:0] datab_pipe_end;
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if (PIPELINE == 0) begin
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assign dataa_pipe_end = dataa;
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assign datab_pipe_end = datab;
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end else begin
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reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
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reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
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genvar pipe_stage;
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for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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dataa_pipe[pipe_stage+1] <= 0;
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datab_pipe[pipe_stage+1] <= 0;
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end
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else if (clken) begin
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dataa_pipe[pipe_stage+1] <= dataa_pipe[pipe_stage];
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datab_pipe[pipe_stage+1] <= datab_pipe[pipe_stage];
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end
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end
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end
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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dataa_pipe[0] <= 0;
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datab_pipe[0] <= 0;
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end
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else if (clken) begin
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dataa_pipe[0] <= dataa;
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datab_pipe[0] <= datab;
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end
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end
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assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
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assign datab_pipe_end = datab_pipe[PIPELINE-1];
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end
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/* * * * * * * * * * * * * * * * * * * * * * */
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/* Do the actual fallback computation here */
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/* * * * * * * * * * * * * * * * * * * * * * */
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if (REP == "SIGNED") begin
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assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
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end
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else begin
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assign result = dataa_pipe_end*datab_pipe_end;
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end
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end
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endgenerate
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endmodule: VX_mult
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