209 lines
8.0 KiB
Verilog
209 lines
8.0 KiB
Verilog
`include "VX_define.vh"
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`include "fpnew_pkg.sv"
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`include "defs_div_sqrt_mvp.sv"
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`TRACING_OFF
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module VX_fpnew
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#(
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parameter TAGW = 1,
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parameter FMULADD = 1,
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parameter FDIVSQRT = 1,
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parameter FNONCOMP = 1,
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parameter FCONV = 1
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [TAGW-1:0] tag_in,
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input wire [`FPU_BITS-1:0] op_type,
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input wire [`MOD_BITS-1:0] frm,
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input wire [`NUM_THREADS-1:0][31:0] dataa,
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input wire [`NUM_THREADS-1:0][31:0] datab,
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input wire [`NUM_THREADS-1:0][31:0] datac,
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output wire [`NUM_THREADS-1:0][31:0] result,
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output wire has_fflags,
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output fflags_t [`NUM_THREADS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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localparam UNIT_FMULADD = FMULADD ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED;
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localparam UNIT_FDIVSQRT = FDIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;
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localparam UNIT_FNONCOMP = FNONCOMP ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED;
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localparam UNIT_FCONV = FCONV ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;
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localparam FOP_BITS = fpnew_pkg::OP_BITS;
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localparam FMTF_BITS = $clog2(fpnew_pkg::NUM_FP_FORMATS);
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localparam FMTI_BITS = $clog2(fpnew_pkg::NUM_INT_FORMATS);
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localparam FPU_DPATHW = 32'd32;
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localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
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Width: FPU_DPATHW,
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EnableVectors: 1'b0,
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EnableNanBox: 1'b1,
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FpFmtMask: 5'b10000,
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IntFmtMask: 4'b0010
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};
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localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
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PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL
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'{default: `LATENCY_FDIVSQRT}, // DIVSQRT
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'{default: `LATENCY_FNCP}, // NONCOMP
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'{default: `LATENCY_FCVT}}, // CONV
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UnitTypes:'{'{default: UNIT_FMULADD}, // ADDMUL
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'{default: UNIT_FDIVSQRT}, // DIVSQRT
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'{default: UNIT_FNONCOMP}, // NONCOMP
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'{default: UNIT_FCONV}}, // CONV
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PipeConfig: fpnew_pkg::DISTRIBUTED
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};
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wire fpu_ready_in, fpu_valid_in;
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wire fpu_ready_out, fpu_valid_out;
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reg [TAGW-1:0] fpu_tag_in, fpu_tag_out;
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reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands;
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wire [FMTF_BITS-1:0] fpu_src_fmt = fpnew_pkg::FP32;
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wire [FMTF_BITS-1:0] fpu_dst_fmt = fpnew_pkg::FP32;
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wire [FMTI_BITS-1:0] fpu_int_fmt = fpnew_pkg::INT32;
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wire [`NUM_THREADS-1:0][31:0] fpu_result;
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fpnew_pkg::status_t [`NUM_THREADS-1:0] fpu_status;
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reg [FOP_BITS-1:0] fpu_op;
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reg [`FRM_BITS-1:0] fpu_rnd;
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reg fpu_op_mod;
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reg fpu_has_fflags, fpu_has_fflags_out;
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always @(*) begin
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fpu_op = fpnew_pkg::SGNJ;
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fpu_rnd = frm;
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fpu_op_mod = 0;
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fpu_has_fflags = 1;
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fpu_operands[0] = dataa;
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fpu_operands[1] = datab;
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fpu_operands[2] = datac;
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case (op_type)
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`FPU_ADD: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = dataa;
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fpu_operands[2] = datab;
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end
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`FPU_SUB: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = dataa;
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fpu_operands[2] = datab;
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fpu_op_mod = 1;
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end
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`FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end
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`FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end
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`FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end
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`FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end
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`FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
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`FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
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`FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end
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`FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end
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`FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end
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`FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end
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`FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end
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`FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end
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`FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end
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`FPU_MISC: begin
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case (frm)
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0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fpu_has_fflags = 0; end
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1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fpu_has_fflags = 0; end
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2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fpu_has_fflags = 0; end
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3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end
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4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end
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default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fpu_has_fflags = 0; end
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endcase
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end
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default:;
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endcase
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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if (0 == i) begin
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fpnew_top #(
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.Features (FPU_FEATURES),
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.Implementation (FPU_IMPLEMENTATION),
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.TagType (logic[TAGW+1+1-1:0])
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) fpnew_core (
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.clk_i (clk),
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.rst_ni (1'b1),
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.operands_i ({fpu_operands[2][0], fpu_operands[1][0], fpu_operands[0][0]}),
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.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
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.op_i (fpnew_pkg::operation_e'(fpu_op)),
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.op_mod_i (fpu_op_mod),
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.src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)),
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.dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)),
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.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
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.vectorial_op_i (1'b0),
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.tag_i ({fpu_tag_in, fpu_has_fflags}),
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.in_valid_i (fpu_valid_in),
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.in_ready_o (fpu_ready_in),
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.flush_i (reset),
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.result_o (fpu_result[0]),
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.status_o (fpu_status[0]),
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.tag_o ({fpu_tag_out, fpu_has_fflags_out}),
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.out_valid_o (fpu_valid_out),
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.out_ready_i (fpu_ready_out),
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`UNUSED_PIN (busy_o)
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);
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end else begin
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fpnew_top #(
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.Features (FPU_FEATURES),
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.Implementation (FPU_IMPLEMENTATION),
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.TagType (logic)
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) fpnew_core (
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.clk_i (clk),
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.rst_ni (1'b1),
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.operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}),
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.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
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.op_i (fpnew_pkg::operation_e'(fpu_op)),
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.op_mod_i (fpu_op_mod),
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.src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)),
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.dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)),
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.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
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.vectorial_op_i (1'b0),
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.tag_i (1'b0),
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.in_valid_i (fpu_valid_in),
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`UNUSED_PIN (in_ready_o),
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.flush_i (reset),
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.result_o (fpu_result[i]),
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.status_o (fpu_status[i]),
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`UNUSED_PIN (tag_o),
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`UNUSED_PIN (out_valid_o),
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.out_ready_i (fpu_ready_out),
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`UNUSED_PIN (busy_o)
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);
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end
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end
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assign fpu_valid_in = valid_in;
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assign ready_in = fpu_ready_in;
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assign fpu_tag_in = tag_in;
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assign tag_out = fpu_tag_out;
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assign result = fpu_result;
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assign has_fflags = fpu_has_fflags_out;
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assign fflags = fpu_status;
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assign valid_out = fpu_valid_out;
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assign fpu_ready_out = ready_out;
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endmodule
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`TRACING_ON |