70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
module VX_csr_handler (
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input wire clk,
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input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done
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VX_csr_write_request_if vx_csr_w_req,
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input wire in_wb_valid,
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output wire[31:0] out_decode_csr_data // done
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);
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wire in_mem_is_csr;
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wire[`CSR_ADDR_SIZE-1:0] in_mem_csr_address;
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wire[31:0] in_mem_csr_result;
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assign in_mem_is_csr = vx_csr_w_req.is_csr;
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assign in_mem_csr_address = vx_csr_w_req.csr_address;
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assign in_mem_csr_result = vx_csr_w_req.csr_result;
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reg [`CSR_WIDTH-1:0] csr [`NUM_CSRS-1:0];
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reg [63:0] cycle;
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reg [63:0] instret;
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reg [`CSR_ADDR_SIZE-1:0] decode_csr_address;
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wire read_cycle;
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wire read_cycleh;
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wire read_instret;
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wire read_instreth;
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initial begin
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cycle = 0;
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instret = 0;
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decode_csr_address = 0;
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end
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always @(posedge clk) begin
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cycle <= cycle + 1;
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decode_csr_address <= in_decode_csr_address;
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if (in_wb_valid) begin
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instret <= instret + 1;
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end
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end
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reg[`CSR_WIDTH-1:0] data_read;
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always @(posedge clk) begin
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if (in_mem_is_csr) begin
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csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
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end
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end
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assign data_read = csr[decode_csr_address];
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assign read_cycle = decode_csr_address == `CSR_CYCL_L;
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assign read_cycleh = decode_csr_address == `CSR_CYCL_H;
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assign read_instret = decode_csr_address == `CSR_INST_L;
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assign read_instreth = decode_csr_address == `CSR_INST_H;
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assign out_decode_csr_data = read_cycle ? cycle[31:0] :
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read_cycleh ? cycle[63:32] :
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read_instret ? instret[31:0] :
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read_instreth ? instret[63:32] :
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{{20{1'b0}}, data_read};
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endmodule // VX_csr_handler
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