354 lines
10 KiB
C++
354 lines
10 KiB
C++
// C++ libraries
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#include <utility>
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#include <iostream>
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#include <map>
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#include <iterator>
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#include <iomanip>
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#include <fstream>
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#include <unistd.h>
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#include <vector>
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#include <math.h>
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#include <algorithm>
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#include "VX_define.h"
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#include "VVX_d_cache_encapsulate.h"
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#include "verilated.h"
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#include "d_cache_test_bench_debug.h"
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#ifdef VCD_OUTPUT
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#include <verilated_vcd_c.h>
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#endif
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// void set_Index (auto & var, int index, int size, auto val)
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// {
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// int real_shift
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// }
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class VX_d_cache
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{
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public:
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VX_d_cache();
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~VX_d_cache();
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bool simulate();
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bool operation(int, bool);
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VVX_d_cache_encapsulate * vx_d_cache_;
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long int curr_cycle;
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int stats_total_cycles = 0;
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int stats_dram_accesses = 0;
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#ifdef VCD_OUTPUT
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VerilatedVcdC *m_trace;
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#endif
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};
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VX_d_cache::VX_d_cache() : curr_cycle(0), stats_total_cycles(0), stats_dram_accesses(0)
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{
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this->vx_d_cache_ = new VVX_d_cache_encapsulate;
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#ifdef VCD_OUTPUT
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this->m_trace = new VerilatedVcdC;
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this->vx_d_cache_->trace(m_trace, 99);
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this->m_trace->open("trace.vcd");
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#endif
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//this->results.open("../results.txt");
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}
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VX_d_cache::~VX_d_cache()
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{
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delete this->vx_d_cache_;
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#ifdef VCD_OUTPUT
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m_trace->close();
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#endif
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}
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bool VX_d_cache::operation(int counter_value, bool do_op) {
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if (do_op) {
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vx_d_cache_->i_p_initial_request = 1;
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} else {
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vx_d_cache_->i_p_initial_request = 0;
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}
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if (counter_value == 0 && do_op) { // Write to bank 1-4 at index 64
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vx_d_cache_->i_p_initial_request = 1;
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vx_d_cache_->i_p_read_or_write = 1;
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vx_d_cache_->i_m_ready = 0;
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_valid[j] = 1;
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vx_d_cache_->i_p_writedata[j] = 0x7f6f8f6f;
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vx_d_cache_->i_m_readdata[j][0] = 1;
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if (j == 0) {
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vx_d_cache_->i_p_addr[0] = 0x30001004; // bank 1
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} else if (j == 1) {
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vx_d_cache_->i_p_addr[1] = 0x30001008; // bank 2
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} else if (j == 2) {
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vx_d_cache_->i_p_addr[2] = 0x3000100c; // bank 3
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} else {
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vx_d_cache_->i_p_addr[3] = 0x30010010; // bank 4 -- This is serviced 1st, then the other 3 banks are at once
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}
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}
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} else if (counter_value == 1 && do_op) { // Write to bank 4-7 at index 108
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vx_d_cache_->i_p_initial_request = 1;
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vx_d_cache_->i_p_read_or_write = 1;
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vx_d_cache_->i_m_ready = 0;
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_valid[j] = 1;
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vx_d_cache_->i_p_writedata[j] = 0xd1d2d2d3;
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vx_d_cache_->i_m_readdata[j][0] = 1;
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if (j == 0) {
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vx_d_cache_->i_p_addr[0] = 0x30001c14; // bank 5
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} else if (j == 1) {
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vx_d_cache_->i_p_addr[1] = 0x30001c18; // bank 6
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} else if (j == 2) {
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vx_d_cache_->i_p_addr[2] = 0x30001c1c; // bank 7
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} else {
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vx_d_cache_->i_p_addr[3] = 0x30001c10; // bank 4
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}
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}
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} else if (counter_value == 2 && do_op) { // Read from bank 1-4 at those indexes
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_initial_request = 1;
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vx_d_cache_->i_p_read_or_write = 0;
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vx_d_cache_->i_m_ready = 0;
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_valid[j] = 1;
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vx_d_cache_->i_p_writedata[j] = 0x23232332;
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vx_d_cache_->i_m_readdata[j][0] = 1;
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if (j == 0) {
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vx_d_cache_->i_p_addr[0] = 0x30001004; // bank 1
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} else if (j == 1) {
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vx_d_cache_->i_p_addr[1] = 0x30001c18; // bank 5
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} else if (j == 2) {
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vx_d_cache_->i_p_addr[2] = 0x3000100c; // bank 3
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} else {
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vx_d_cache_->i_p_addr[3] = 0x30001c1c;; // bank 7
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}
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}
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}
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} else if (counter_value == 3 && do_op) { // Write to Bank 1-5 (evictions will need to take place)
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vx_d_cache_->i_p_initial_request = 1;
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vx_d_cache_->i_p_read_or_write = 1;
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vx_d_cache_->i_m_ready = 0;
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_valid[j] = 1;
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vx_d_cache_->i_m_readdata[j][0] = 1;
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if (j == 0) {
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vx_d_cache_->i_p_addr[0] = 0x20001004; // bank 1
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb0;
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} else if (j == 1) {
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vx_d_cache_->i_p_addr[1] = 0x20001008; // bank 2
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb1;
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} else if (j == 2) {
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vx_d_cache_->i_p_addr[2] = 0x2000100c; // bank 3
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb2;
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} else {
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vx_d_cache_->i_p_addr[3] = 0x20001c14; // bank 5
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb3;
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}
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}
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} else if (counter_value == 4 && do_op) { // Read from addresses that were just overwritten above ^^^
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vx_d_cache_->i_p_initial_request = 1;
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vx_d_cache_->i_p_read_or_write = 0;
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vx_d_cache_->i_m_ready = 0;
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_valid[j] = 1;
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vx_d_cache_->i_p_writedata[j] = 0x23232332;
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vx_d_cache_->i_m_readdata[j][0] = 1;
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if (j == 0) {
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vx_d_cache_->i_p_addr[0] = 0x20001004; // bank 1
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} else if (j == 1) {
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vx_d_cache_->i_p_addr[1] = 0x20001008; // bank 2
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} else if (j == 2) {
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vx_d_cache_->i_p_addr[2] = 0x2000100c; // bank 3
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} else {
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vx_d_cache_->i_p_addr[3] = 0x20001c14; // bank 5
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}
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}
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}
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/* These will check writing multiple threads writing to the same block
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} else if (counter_value == 3 && do_op) { // Write to Bank 0
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vx_d_cache_->i_p_initial_request = 1;
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vx_d_cache_->i_p_read_or_write = 1;
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vx_d_cache_->i_m_ready = 0;
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_valid[j] = 1;
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vx_d_cache_->i_m_readdata[j][0] = 1;
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if (j == 0) {
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vx_d_cache_->i_p_addr[0] = 0x30001f00; // bank 0
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb0;
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} else if (j == 1) {
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vx_d_cache_->i_p_addr[1] = 0x30001c00; // bank 0
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb1;
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} else if (j == 2) {
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vx_d_cache_->i_p_addr[2] = 0x30001a00; // bank 0
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb2;
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} else {
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vx_d_cache_->i_p_addr[3] = 0x30001904; // bank 1
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vx_d_cache_->i_p_writedata[j] = 0xaaaabbb3;
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}
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}
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} else if (counter_value == 4 && do_op) { // Read from Bank 0
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vx_d_cache_->i_p_initial_request = 1;
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vx_d_cache_->i_p_read_or_write = 0;
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vx_d_cache_->i_m_ready = 0;
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for (int j = 0; j < NT; j++) {
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vx_d_cache_->i_p_valid[j] = 1;
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vx_d_cache_->i_p_writedata[j] = 0x23232332;
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vx_d_cache_->i_m_readdata[j][0] = 1;
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if (j == 0) {
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vx_d_cache_->i_p_addr[0] = 0x30001f00; // bank 0
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} else if (j == 1) {
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vx_d_cache_->i_p_addr[1] = 0x30001c00; // bank 0
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} else if (j == 2) {
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vx_d_cache_->i_p_addr[2] = 0x30001a00; // bank 0
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} else {
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vx_d_cache_->i_p_addr[3] = 0x30001904; // bank 1
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}
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}
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}
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*/
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// Handle Memory Accesses
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unsigned int read_data_from_mem = 0x1111 + counter_value + this->stats_total_cycles;
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if (vx_d_cache_->o_m_valid) {
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this->stats_dram_accesses = this->stats_dram_accesses + 1; // (assuming memory access takes 20 cycles)
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this->stats_total_cycles += 1;
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vx_d_cache_->clk = 0;
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vx_d_cache_->eval();
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#ifdef VCD_OUTPUT
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m_trace->dump(2*this->stats_total_cycles);
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#endif
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vx_d_cache_->clk = 1;
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vx_d_cache_->eval();
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#ifdef VCD_OUTPUT
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m_trace->dump((2*this->stats_total_cycles)+1);
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#endif
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vx_d_cache_->i_m_ready = 1;
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for (int j1 = 0; j1 < 8; j1++) {
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for (int j2 = 0; j2 < 4; j2++) {
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vx_d_cache_->i_m_readdata[j1][j2] = read_data_from_mem;
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}
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}
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} else {
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vx_d_cache_->i_m_ready = 0;
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}
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if (vx_d_cache_->o_p_waitrequest == 0) {
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return true;
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} else {
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return false;
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}
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}
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bool VX_d_cache::simulate()
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{
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// this->instruction_file_name = file_to_simulate;
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// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
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// this->ProcessFile();
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// auto start_time = std::chrono::high_resolution_clock::now();
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//static bool stop = false;
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//static int counter = 0;
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//counter = 0;
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//stop = false;
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// auto start_time = clock();
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vx_d_cache_->clk = 0;
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vx_d_cache_->rst = 1;
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//vortex->eval();
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//counter = 0;
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vx_d_cache_->rst = 0;
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bool cont = false;
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bool out_operation = false;
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bool do_operation = true;
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int other_counter = 0;
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//while (this->stop && ((other_counter < 5)))
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while (other_counter < 5)
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{
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// std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
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// istop = ibus_driver();
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// dstop = !dbus_driver();
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vx_d_cache_->clk = 1;
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vx_d_cache_->eval();
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#ifdef VCD_OUTPUT
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m_trace->dump(2*this->stats_total_cycles);
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#endif
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//vortex->eval();
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//dstop = !dbus_driver();
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out_operation = operation(other_counter, do_operation);
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vx_d_cache_->clk = 0;
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vx_d_cache_->eval();
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#ifdef VCD_OUTPUT
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m_trace->dump((2*this->stats_total_cycles)+1);
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#endif
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//vortex->eval();
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/*
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// stop = istop && dstop;
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stop = vortex->out_ebreak;
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if (stop || cont)
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{
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cont = true;
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counter++;
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} else
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{
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counter = 0;
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}
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*/
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if (out_operation) {
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other_counter++;
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do_operation = true;
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} else {
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do_operation = false;
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}
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++(this->stats_total_cycles);
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if (this->stats_total_cycles > 5000) {
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break;
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}
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}
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std::cerr << "New Total Cycles: " << (this->stats_total_cycles + (this->stats_dram_accesses * 20)) << "\n";
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//uint32_t status;
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//ram.getWord(0, &status);
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//this->print_stats();
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return (true);
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}
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