634 lines
26 KiB
Verilog
634 lines
26 KiB
Verilog
`include "VX_cache_config.vh"
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`include "VX_define.vh"
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module VX_bank
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#(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
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parameter FUNC_ID = 0,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Forward SNP Queue
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parameter FFSQ_SIZE = 8,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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)
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(
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input wire clk,
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input wire reset,
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// Input Core Request
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input wire delay_req,
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input wire [NUM_REQUESTS-1:0] bank_valids,
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input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
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input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
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input wire [4:0] bank_rd,
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input wire [NUM_REQUESTS-1:0][1:0] bank_wb,
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input wire [31:0] bank_pc,
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input wire [`NW_BITS-1:0] bank_warp_num,
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input wire [NUM_REQUESTS-1:0][2:0] bank_mem_read,
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input wire [NUM_REQUESTS-1:0][2:0] bank_mem_write,
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output wire reqq_full,
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// Output Core WB
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input wire bank_wb_pop,
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output wire bank_wb_valid,
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output wire [`LOG2UP(NUM_REQUESTS)-1:0] bank_wb_tid,
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output wire [4:0] bank_wb_rd,
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output wire [1:0] bank_wb_wb,
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output wire [`NW_BITS-1:0] bank_wb_warp_num,
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output wire [`WORD_SIZE_RNG] bank_wb_data,
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output wire [31:0] bank_wb_pc,
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output wire [31:0] bank_wb_address,
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// Dram Fill Requests
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output wire dram_fill_req,
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output wire[31:0] dram_fill_req_addr,
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output wire dram_because_of_snp,
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output wire dram_snp_full,
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input wire dram_fill_req_queue_full,
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// Dram Fill Response
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_addr,
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input wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_fill_rsp_data,
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output wire dram_fill_accept,
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// Dram WB Requests
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input wire dram_wb_queue_pop,
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output wire dram_wb_req,
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output wire[31:0] dram_wb_req_addr,
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output wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_wb_req_data,
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// Snp Request
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input wire snp_req,
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input wire[31:0] snp_req_addr,
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output wire snrq_full,
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output wire snp_fwd,
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output wire[31:0] snp_fwd_addr,
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input wire snp_fwd_pop
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);
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reg snoop_state = 0;
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always @(posedge clk) begin
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if (reset) begin
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snoop_state <= 0;
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end else begin
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snoop_state <= (snoop_state | snp_req) && ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID));
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end
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end
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wire snrq_pop;
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wire snrq_empty;
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wire snrq_valid_st0;
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wire[31:0] snrq_addr_st0;
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assign snrq_valid_st0 = !snrq_empty;
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VX_generic_queue_ll #(.DATAW(32), .SIZE(SNRQ_SIZE)) snr_queue(
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.clk (clk),
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.reset (reset),
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.push (snp_req),
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.in_data (snp_req_addr),
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.pop (snrq_pop),
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.out_data(snrq_addr_st0),
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.empty (snrq_empty),
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.full (snrq_full)
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);
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wire dfpq_pop;
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wire dfpq_empty;
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wire dfpq_full;
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wire[31:0] dfpq_addr_st0;
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wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dfpq_filldata_st0;
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assign dram_fill_accept = !dfpq_full;
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VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE)) dfp_queue(
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.clk (clk),
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.reset (reset),
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.push (dram_fill_rsp),
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.in_data ({dram_fill_addr, dram_fill_rsp_data}),
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.pop (dfpq_pop),
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.out_data({dfpq_addr_st0, dfpq_filldata_st0}),
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.empty (dfpq_empty),
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.full (dfpq_full)
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);
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wire reqq_pop;
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wire reqq_push;
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wire reqq_empty;
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wire reqq_req_st0;
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wire[`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0;
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wire [31:0] reqq_req_addr_st0;
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wire [`WORD_SIZE_RNG] reqq_req_writeword_st0;
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wire [4:0] reqq_req_rd_st0;
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wire [1:0] reqq_req_wb_st0;
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wire [`NW_BITS-1:0] reqq_req_warp_num_st0;
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wire [2:0] reqq_req_mem_read_st0;
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wire [2:0] reqq_req_mem_write_st0;
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wire [31:0] reqq_req_pc_st0;
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assign reqq_push = !delay_req && (|bank_valids);
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VX_cache_req_queue #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
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)
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req_queue
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(
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.clk (clk),
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.reset (reset),
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// Enqueue
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.reqq_push (reqq_push),
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.bank_valids (bank_valids),
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.bank_addr (bank_addr),
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.bank_writedata (bank_writedata),
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.bank_rd (bank_rd),
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.bank_pc (bank_pc),
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.bank_wb (bank_wb),
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.bank_warp_num (bank_warp_num),
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.bank_mem_read (bank_mem_read),
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.bank_mem_write (bank_mem_write),
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// Dequeue
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.reqq_pop (reqq_pop),
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.reqq_req_st0 (reqq_req_st0),
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.reqq_req_tid_st0 (reqq_req_tid_st0),
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.reqq_req_addr_st0 (reqq_req_addr_st0),
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.reqq_req_writedata_st0(reqq_req_writeword_st0),
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.reqq_req_rd_st0 (reqq_req_rd_st0),
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.reqq_req_wb_st0 (reqq_req_wb_st0),
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.reqq_req_warp_num_st0 (reqq_req_warp_num_st0),
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.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
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.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
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.reqq_req_pc_st0 (reqq_req_pc_st0),
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.reqq_empty (reqq_empty),
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.reqq_full (reqq_full)
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);
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wire mrvq_pop;
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wire mrvq_full;
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wire mrvq_stop;
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wire mrvq_valid_st0;
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wire[`LOG2UP(NUM_REQUESTS)-1:0] mrvq_tid_st0;
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wire [31:0] mrvq_addr_st0;
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wire [`WORD_SIZE_RNG] mrvq_writeword_st0;
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wire [4:0] mrvq_rd_st0;
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wire [1:0] mrvq_wb_st0;
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wire [31:0] miss_resrv_pc_st0;
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wire [`NW_BITS-1:0] mrvq_warp_num_st0;
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wire [2:0] mrvq_mem_read_st0;
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wire [2:0] mrvq_mem_write_st0;
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wire miss_add;
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wire[31:0] miss_add_addr;
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wire[`WORD_SIZE_RNG] miss_add_data;
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wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid;
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wire[4:0] miss_add_rd;
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wire[1:0] miss_add_wb;
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wire[`NW_BITS-1:0] miss_add_warp_num;
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wire[2:0] miss_add_mem_read;
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wire[2:0] miss_add_mem_write;
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wire[31:0] miss_add_pc;
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wire[31:0] addr_st2;
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wire is_fill_st2;
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VX_cache_miss_resrv #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
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)
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mrvq_queue
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(
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.clk (clk),
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.reset (reset),
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// Enqueue
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.miss_add (miss_add), // Need to do all
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.miss_add_addr (miss_add_addr),
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.miss_add_data (miss_add_data),
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.miss_add_tid (miss_add_tid),
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.miss_add_rd (miss_add_rd),
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.miss_add_wb (miss_add_wb),
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.miss_add_warp_num (miss_add_warp_num),
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.miss_add_mem_read (miss_add_mem_read),
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.miss_add_mem_write (miss_add_mem_write),
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.miss_add_pc (miss_add_pc),
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.miss_resrv_full (mrvq_full),
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.miss_resrv_stop (mrvq_stop),
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// Broadcast
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.is_fill_st1 (is_fill_st2),
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.fill_addr_st1 (addr_st2),
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// Dequeue
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.miss_resrv_pop (mrvq_pop),
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.miss_resrv_valid_st0 (mrvq_valid_st0),
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.miss_resrv_addr_st0 (mrvq_addr_st0),
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.miss_resrv_data_st0 (mrvq_writeword_st0),
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.miss_resrv_tid_st0 (mrvq_tid_st0),
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.miss_resrv_rd_st0 (mrvq_rd_st0),
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.miss_resrv_wb_st0 (mrvq_wb_st0),
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.miss_resrv_pc_st0 (miss_resrv_pc_st0),
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.miss_resrv_warp_num_st0 (mrvq_warp_num_st0),
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.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
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.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
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);
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wire stall_bank_pipe;
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reg is_fill_in_pipe;
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wire valid_st1 [STAGE_1_CYCLES-1:0];
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wire is_fill_st1 [STAGE_1_CYCLES-1:0];
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wire going_to_write_st1[STAGE_1_CYCLES-1:0];
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wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
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integer p_stage;
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always @(*) begin
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is_fill_in_pipe = 0;
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for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin
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if (is_fill_st1[p_stage]) is_fill_in_pipe = 1;
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end
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if (is_fill_st2) is_fill_in_pipe = 1;
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end
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// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2;
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assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe;
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assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe;
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assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !is_fill_in_pipe;
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assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe;
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integer st1_cycle;
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wire qual_is_fill_st0;
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wire qual_valid_st0;
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wire [31:0] qual_addr_st0;
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wire [`WORD_SIZE_RNG] qual_writeword_st0;
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wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] qual_writedata_st0;
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wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
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wire qual_going_to_write_st0;
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wire qual_is_snp;
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wire [31:0] qual_pc_st0;
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wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0];
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wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
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wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
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wire is_snp_st1 [STAGE_1_CYCLES-1:0];
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wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0];
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assign qual_is_fill_st0 = dfpq_pop;
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// always @(*) begin
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// if (qual_is_fill_st0 && (FUNC_ID == 3)) begin
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// $display("WHAT THE FUCK FUNC_ID: %x", FUNC_ID);
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// end
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// end
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assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop;
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assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
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mrvq_pop ? mrvq_addr_st0 :
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reqq_pop ? reqq_req_addr_st0 :
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snrq_pop ? snrq_addr_st0 :
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0;
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assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 57;
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assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } :
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reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
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0;
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assign qual_going_to_write_st0 = dfpq_pop ? 1 :
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(mrvq_pop && (mrvq_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
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(reqq_pop && (reqq_req_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
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(snrq_pop) ? 1 :
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0;
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assign qual_pc_st0 = (reqq_pop) ? reqq_req_pc_st0 :
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(mrvq_pop) ? miss_resrv_pc_st0 :
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(dfpq_pop) ? 32'hdeadbeef :
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(snrq_pop) ? 32'hb00b0000 :
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32'h0;
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assign qual_is_snp = snrq_pop ? 1 : 0;
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assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
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reqq_pop ? reqq_req_writeword_st0 :
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0;
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VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_c0 (
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.clk (clk),
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.reset(reset),
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.stall(stall_bank_pipe),
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.flush(0),
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.in ({qual_is_snp , qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0, qual_pc_st0 }),
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.out ({is_snp_st1[0], going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0] , pc_st1[0]})
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);
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genvar curr_stage;
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generate
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for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
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VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_cc (
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.clk (clk),
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.reset(reset),
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.stall(stall_bank_pipe),
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.flush(0),
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.in ({is_snp_st1[curr_stage-1], going_to_write_st1[curr_stage-1], valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1], pc_st1[curr_stage-1]}),
|
|
.out ({is_snp_st1[curr_stage] , going_to_write_st1[curr_stage] , valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] , pc_st1[curr_stage]})
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
|
|
wire[`WORD_SIZE_RNG] readword_st1e;
|
|
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] readdata_st1e;
|
|
wire[`TAG_SELECT_SIZE_RNG] readtag_st1e;
|
|
wire miss_st1e;
|
|
wire dirty_st1e;
|
|
wire[31:0] pc_st1e;
|
|
|
|
|
|
wire [4:0] rd_st1e;
|
|
wire [1:0] wb_st1e;
|
|
wire [`NW_BITS-1:0] warp_num_st1e;
|
|
wire [2:0] mem_read_st1e;
|
|
wire [2:0] mem_write_st1e;
|
|
wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e;
|
|
wire fill_saw_dirty_st1e;
|
|
wire is_snp_st1e;
|
|
|
|
assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1];
|
|
assign pc_st1e = pc_st1[STAGE_1_CYCLES-1];
|
|
assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
|
|
|
|
|
|
VX_tag_data_access #(
|
|
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
|
|
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
|
|
.NUM_REQUESTS (NUM_REQUESTS),
|
|
.STAGE_1_CYCLES (STAGE_1_CYCLES),
|
|
.FUNC_ID (FUNC_ID),
|
|
.REQQ_SIZE (REQQ_SIZE),
|
|
.MRVQ_SIZE (MRVQ_SIZE),
|
|
.DFPQ_SIZE (DFPQ_SIZE),
|
|
.SNRQ_SIZE (SNRQ_SIZE),
|
|
.CWBQ_SIZE (CWBQ_SIZE),
|
|
.DWBQ_SIZE (DWBQ_SIZE),
|
|
.DFQQ_SIZE (DFQQ_SIZE),
|
|
.LLVQ_SIZE (LLVQ_SIZE),
|
|
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
|
|
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
|
|
)
|
|
VX_tag_data_access
|
|
(
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.stall (stall_bank_pipe),
|
|
.stall_bank_pipe(stall_bank_pipe),
|
|
|
|
// Initial Read
|
|
.readaddr_st10 (addr_st1[0]),
|
|
|
|
// Actual Read/Write
|
|
.valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]),
|
|
.writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]),
|
|
.writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]),
|
|
.writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]),
|
|
.writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]),
|
|
|
|
.mem_write_st1e(mem_write_st1e),
|
|
.mem_read_st1e (mem_read_st1e),
|
|
|
|
.is_snp_st1e (is_snp_st1e),
|
|
|
|
// Read Data
|
|
.readword_st1e (readword_st1e),
|
|
.readdata_st1e (readdata_st1e),
|
|
.readtag_st1e (readtag_st1e),
|
|
.miss_st1e (miss_st1e),
|
|
.dirty_st1e (dirty_st1e),
|
|
.fill_saw_dirty_st1e(fill_saw_dirty_st1e)
|
|
);
|
|
|
|
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
|
|
|
|
wire valid_st2;
|
|
wire[`WORD_SIZE_RNG] writeword_st2;
|
|
wire[`WORD_SIZE_RNG] readword_st2;
|
|
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] readdata_st2;
|
|
wire miss_st2;
|
|
wire dirty_st2;
|
|
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
|
|
wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
|
|
wire fill_saw_dirty_st2;
|
|
wire is_snp_st2;
|
|
wire [31:0] pc_st2;
|
|
|
|
|
|
VX_generic_register #(.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2)) st_1e_2 (
|
|
.clk (clk),
|
|
.reset(reset),
|
|
.stall(stall_bank_pipe),
|
|
.flush(0),
|
|
.in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
|
|
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 })
|
|
);
|
|
|
|
|
|
wire should_flush;
|
|
wire dwbq_push;
|
|
|
|
wire cwbq_full;
|
|
wire dwbq_full;
|
|
wire ffsq_full;
|
|
wire invalidate_fill;
|
|
|
|
// Enqueue to miss reserv if it's a valid miss
|
|
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !(should_flush && dwbq_push) && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
|
|
assign miss_add_pc = pc_st2;
|
|
assign miss_add_addr = addr_st2;
|
|
assign miss_add_data = writeword_st2;
|
|
assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
|
|
|
|
|
|
// Enqueue to CWB Queue
|
|
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
|
|
wire [`WORD_SIZE_RNG] cwbq_data = readword_st2;
|
|
wire [`LOG2UP(NUM_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
|
|
wire [4:0] cwbq_rd = miss_add_rd;
|
|
wire [1:0] cwbq_wb = miss_add_wb;
|
|
wire [`NW_BITS-1:0] cwbq_warp_num = miss_add_warp_num;
|
|
wire [31:0] cwbq_pc = pc_st2;
|
|
|
|
wire cwbq_empty;
|
|
assign bank_wb_valid = !cwbq_empty;
|
|
VX_generic_queue_ll #(.DATAW( `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
.push (cwbq_push),
|
|
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}),
|
|
|
|
.pop (bank_wb_pop),
|
|
.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc, bank_wb_address}),
|
|
.empty (cwbq_empty),
|
|
.full (cwbq_full)
|
|
);
|
|
|
|
assign should_flush = snoop_state && valid_st2 && (miss_add_mem_write != `NO_MEM_WRITE) && !is_snp_st2 && !is_fill_st2;
|
|
// Enqueue to DWB Queue
|
|
assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
|
|
wire[31:0] dwbq_req_addr;
|
|
wire dwbq_empty;
|
|
|
|
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dwbq_req_data;
|
|
if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
|
|
assign dwbq_req_data = (should_flush && dwbq_push) ? writeword_st2 : readdata_st2;
|
|
assign dwbq_req_addr = (should_flush && dwbq_push) ? (addr_st2) : ({readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK);
|
|
end else begin
|
|
assign dwbq_req_data = readdata_st2;
|
|
assign dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
|
|
end
|
|
|
|
|
|
|
|
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_queue_full && !is_snp_st2;
|
|
wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
|
|
VX_fill_invalidator #(
|
|
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
|
|
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
|
|
.NUM_REQUESTS (NUM_REQUESTS),
|
|
.STAGE_1_CYCLES (STAGE_1_CYCLES),
|
|
.REQQ_SIZE (REQQ_SIZE),
|
|
.MRVQ_SIZE (MRVQ_SIZE),
|
|
.DFPQ_SIZE (DFPQ_SIZE),
|
|
.SNRQ_SIZE (SNRQ_SIZE),
|
|
.CWBQ_SIZE (CWBQ_SIZE),
|
|
.DWBQ_SIZE (DWBQ_SIZE),
|
|
.DFQQ_SIZE (DFQQ_SIZE),
|
|
.LLVQ_SIZE (LLVQ_SIZE),
|
|
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
|
|
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
|
|
)
|
|
VX_fill_invalidator
|
|
(
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.possible_fill (possible_fill),
|
|
.success_fill (is_fill_st2),
|
|
.fill_addr (fill_invalidator_addr),
|
|
|
|
.invalidate_fill (invalidate_fill)
|
|
);
|
|
|
|
// Enqueu in dram_fill_req
|
|
assign dram_fill_req = possible_fill && !invalidate_fill;
|
|
assign dram_because_of_snp = is_snp_st2 && valid_st2 && miss_st2;
|
|
assign dram_snp_full = snrq_full && snp_req;
|
|
assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK;
|
|
|
|
assign dram_wb_req = !dwbq_empty;
|
|
VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE)) dwb_queue(
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
.push (dwbq_push),
|
|
.in_data ({dwbq_req_addr, dwbq_req_data}),
|
|
|
|
.pop (dram_wb_queue_pop),
|
|
.out_data({dram_wb_req_addr, dram_wb_req_data}),
|
|
.empty (dwbq_empty),
|
|
.full (dwbq_full)
|
|
);
|
|
|
|
wire snp_fwd_push;
|
|
wire ffsq_empty;
|
|
|
|
assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
|
|
assign snp_fwd = !ffsq_empty;
|
|
VX_generic_queue_ll #(.DATAW(32), .SIZE(FFSQ_SIZE)) ffs_queue(
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.push (snp_fwd_push),
|
|
.in_data ({addr_st2}),
|
|
.pop (snp_fwd_pop),
|
|
.out_data({snp_fwd_addr}),
|
|
.empty (ffsq_empty),
|
|
.full (ffsq_full)
|
|
);
|
|
|
|
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
|
|
|
|
endmodule : VX_bank |